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1.3 KiB


A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.


  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from
git clone
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../
  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:
git clone
cd microwatt
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null


  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check


This is functional, but very simple. We still have quite a lot to do:

  • Need to implement a simple non pipelined divide
  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)