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232 lines
9.1 KiB
VHDL
232 lines
9.1 KiB
VHDL
-- syscon module, a bunch of misc global system control MMIO registers
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.wishbone_types.all;
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entity syscon is
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generic (
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SIG_VALUE : std_ulogic_vector(63 downto 0) := x"f00daa5500010001";
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CLK_FREQ : integer;
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HAS_UART : boolean;
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HAS_DRAM : boolean;
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BRAM_SIZE : integer;
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DRAM_SIZE : integer;
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DRAM_INIT_SIZE : integer;
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HAS_SPI_FLASH : boolean;
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SPI_FLASH_OFFSET : integer;
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HAS_LITEETH : boolean;
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HAS_SD_CARD : boolean;
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UART0_IS_16550 : boolean;
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HAS_UART1 : boolean
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);
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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-- Wishbone ports:
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wishbone_in : in wb_io_master_out;
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wishbone_out : out wb_io_slave_out;
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-- System control ports
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dram_at_0 : out std_ulogic;
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core_reset : out std_ulogic;
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soc_reset : out std_ulogic
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);
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end entity syscon;
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architecture behaviour of syscon is
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-- Register address bits
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constant SYS_REG_BITS : positive := 6;
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-- Register addresses (matches wishbone addr downto 3, ie, 8 bytes per reg)
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constant SYS_REG_SIG : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000000";
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constant SYS_REG_INFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000001";
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constant SYS_REG_BRAMINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000010";
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constant SYS_REG_DRAMINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000011";
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constant SYS_REG_CLKINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000100";
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constant SYS_REG_CTRL : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000101";
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constant SYS_REG_DRAMINITINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000110";
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constant SYS_REG_SPIFLASHINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000111";
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constant SYS_REG_UART0_INFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001000";
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constant SYS_REG_UART1_INFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001001";
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-- Muxed reg read signal
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signal reg_out : std_ulogic_vector(63 downto 0);
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-- INFO register bits
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constant SYS_REG_INFO_HAS_UART : integer := 0; -- Has a UART (always set)
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constant SYS_REG_INFO_HAS_DRAM : integer := 1; -- Has DRAM
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constant SYS_REG_INFO_HAS_BRAM : integer := 2; -- Has "main" BRAM
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constant SYS_REG_INFO_HAS_SPIF : integer := 3; -- Has SPI flash
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constant SYS_REG_INFO_HAS_LETH : integer := 4; -- Has LiteEth ethernet
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constant SYS_REG_INFO_HAS_LSYS : integer := 5; -- Has 6-bit address syscon
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constant SYS_REG_INFO_HAS_URT1 : integer := 6; -- Has second UART
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constant SYS_REG_INFO_HAS_ARTB : integer := 7; -- Has architected TB frequency
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constant SYS_REG_INFO_HAS_SDCARD : integer := 8; -- Has LiteSDCard SD-card interface
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-- BRAMINFO contains the BRAM size in the bottom 52 bits
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-- DRAMINFO contains the DRAM size if any in the bottom 52 bits
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-- (both have reserved top bits for future use)
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-- CLKINFO contains the CLK frequency is HZ in the bottom 40 bits
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-- CTRL register bits
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constant SYS_REG_CTRL_BITS : positive := 3;
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constant SYS_REG_CTRL_DRAM_AT_0 : integer := 0;
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constant SYS_REG_CTRL_CORE_RESET : integer := 1;
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constant SYS_REG_CTRL_SOC_RESET : integer := 2;
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-- SPI Info register bits
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--
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-- Top 32-bit is flash offset which is the amount of flash
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-- reserved for the FPGA bitfile if any
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constant SYS_REG_SPI_INFO_IS_FLASH : integer := 0;
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-- UART0/1 info registers bits
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--
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-- 0 ..31 : UART clock freq (in HZ)
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-- 32 : UART is 16550 (otherwise pp)
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--
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-- Ctrl register
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signal reg_ctrl : std_ulogic_vector(SYS_REG_CTRL_BITS-1 downto 0);
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signal reg_ctrl_out : std_ulogic_vector(63 downto 0);
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-- Others
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signal reg_info : std_ulogic_vector(63 downto 0);
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signal reg_braminfo : std_ulogic_vector(63 downto 0);
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signal reg_draminfo : std_ulogic_vector(63 downto 0);
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signal reg_dramiinfo : std_ulogic_vector(63 downto 0);
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signal reg_clkinfo : std_ulogic_vector(63 downto 0);
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signal reg_spiinfo : std_ulogic_vector(63 downto 0);
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signal reg_uart0info : std_ulogic_vector(63 downto 0);
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signal reg_uart1info : std_ulogic_vector(63 downto 0);
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signal info_has_dram : std_ulogic;
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signal info_has_bram : std_ulogic;
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signal info_has_uart : std_ulogic;
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signal info_has_spif : std_ulogic;
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signal info_has_leth : std_ulogic;
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signal info_has_lsdc : std_ulogic;
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signal info_has_urt1 : std_ulogic;
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signal info_clk : std_ulogic_vector(39 downto 0);
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signal info_fl_off : std_ulogic_vector(31 downto 0);
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signal uinfo_16550 : std_ulogic;
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signal uinfo_freq : std_ulogic_vector(31 downto 0);
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-- Wishbone response latch
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signal wb_rsp : wb_io_slave_out;
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begin
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-- Generated output signals
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dram_at_0 <= '1' when BRAM_SIZE = 0 else reg_ctrl(SYS_REG_CTRL_DRAM_AT_0);
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soc_reset <= reg_ctrl(SYS_REG_CTRL_SOC_RESET);
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core_reset <= reg_ctrl(SYS_REG_CTRL_CORE_RESET);
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-- Info register is hard wired
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info_has_uart <= '1' when HAS_UART else '0';
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info_has_dram <= '1' when HAS_DRAM else '0';
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info_has_bram <= '1' when BRAM_SIZE /= 0 else '0';
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info_has_spif <= '1' when HAS_SPI_FLASH else '0';
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info_has_leth <= '1' when HAS_LITEETH else '0';
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info_has_lsdc <= '1' when HAS_SD_CARD else '0';
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info_has_urt1 <= '1' when HAS_UART1 else '0';
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info_clk <= std_ulogic_vector(to_unsigned(CLK_FREQ, 40));
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reg_info <= (SYS_REG_INFO_HAS_UART => info_has_uart,
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SYS_REG_INFO_HAS_DRAM => info_has_dram,
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SYS_REG_INFO_HAS_BRAM => info_has_bram,
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SYS_REG_INFO_HAS_SPIF => info_has_spif,
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SYS_REG_INFO_HAS_LETH => info_has_leth,
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SYS_REG_INFO_HAS_SDCARD => info_has_lsdc,
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SYS_REG_INFO_HAS_LSYS => '1',
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SYS_REG_INFO_HAS_URT1 => info_has_urt1,
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others => '0');
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reg_braminfo <= x"000" & std_ulogic_vector(to_unsigned(BRAM_SIZE, 52));
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reg_draminfo <= x"000" & std_ulogic_vector(to_unsigned(DRAM_SIZE, 52)) when HAS_DRAM
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else (others => '0');
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reg_dramiinfo <= x"000" & std_ulogic_vector(to_unsigned(DRAM_INIT_SIZE, 52)) when HAS_DRAM
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else (others => '0');
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reg_clkinfo <= (39 downto 0 => info_clk,
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others => '0');
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info_fl_off <= std_ulogic_vector(to_unsigned(SPI_FLASH_OFFSET, 32));
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reg_spiinfo <= (31 downto 0 => info_fl_off,
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others => '0');
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-- Control register read composition
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reg_ctrl_out <= (63 downto SYS_REG_CTRL_BITS => '0',
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SYS_REG_CTRL_BITS-1 downto 0 => reg_ctrl);
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-- UART info registers read composition
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uinfo_16550 <= '1' when UART0_IS_16550 else '0';
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uinfo_freq <= std_ulogic_vector(to_unsigned(CLK_FREQ, 32));
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reg_uart0info <= (32 => uinfo_16550,
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31 downto 0 => uinfo_freq,
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others => '0');
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reg_uart1info <= (32 => '1',
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31 downto 0 => uinfo_freq,
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others => '0');
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-- Wishbone response
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wb_rsp.ack <= wishbone_in.cyc and wishbone_in.stb;
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with wishbone_in.adr(SYS_REG_BITS downto 1) select reg_out <=
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SIG_VALUE when SYS_REG_SIG,
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reg_info when SYS_REG_INFO,
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reg_braminfo when SYS_REG_BRAMINFO,
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reg_draminfo when SYS_REG_DRAMINFO,
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reg_dramiinfo when SYS_REG_DRAMINITINFO,
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reg_clkinfo when SYS_REG_CLKINFO,
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reg_ctrl_out when SYS_REG_CTRL,
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reg_spiinfo when SYS_REG_SPIFLASHINFO,
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reg_uart0info when SYS_REG_UART0_INFO,
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reg_uart1info when SYS_REG_UART1_INFO,
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(others => '0') when others;
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wb_rsp.dat <= reg_out(63 downto 32) when wishbone_in.adr(0) = '1' else
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reg_out(31 downto 0);
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wb_rsp.stall <= '0';
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-- Wishbone response latch
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regs_read: process(clk)
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begin
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if rising_edge(clk) then
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-- Send response from latch
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wishbone_out <= wb_rsp;
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end if;
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end process;
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-- Register writes
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regs_write: process(clk)
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begin
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if rising_edge(clk) then
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if (rst) then
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reg_ctrl <= (others => '0');
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else
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if wishbone_in.cyc and wishbone_in.stb and wishbone_in.we then
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-- Change this if CTRL ever has more than 32 bits
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if wishbone_in.adr(SYS_REG_BITS downto 1) = SYS_REG_CTRL and
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wishbone_in.adr(0) = '0' then
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reg_ctrl(SYS_REG_CTRL_BITS-1 downto 0) <=
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wishbone_in.dat(SYS_REG_CTRL_BITS-1 downto 0);
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end if;
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end if;
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-- Reset auto-clear
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if reg_ctrl(SYS_REG_CTRL_SOC_RESET) = '1' then
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reg_ctrl(SYS_REG_CTRL_SOC_RESET) <= '0';
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end if;
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if reg_ctrl(SYS_REG_CTRL_CORE_RESET) = '1' then
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reg_ctrl(SYS_REG_CTRL_CORE_RESET) <= '0';
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end if;
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-- If BRAM doesn't exist, force DRAM at 0
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if BRAM_SIZE = 0 then
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reg_ctrl(SYS_REG_CTRL_DRAM_AT_0) <= '1';
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end if;
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end if;
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end if;
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end process;
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end architecture behaviour;
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