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24 lines
476 B
VHDL
24 lines
476 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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library work;
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use work.wishbone_types.all;
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entity dram_init_mem is
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port (
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clk : in std_ulogic;
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wb_in : in wb_io_master_out;
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wb_out : out wb_io_slave_out
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);
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end entity dram_init_mem;
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architecture rtl of dram_init_mem is
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wb_out.dat <= (others => '0');
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wb_out.stall <= '0';
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wb_out.ack <= wb_in.stb and wb_in.cyc;
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end architecture rtl;
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