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			85 lines
		
	
	
		
			2.7 KiB
		
	
	
	
		
			Plaintext
		
	
			
		
		
	
	
			85 lines
		
	
	
		
			2.7 KiB
		
	
	
	
		
			Plaintext
		
	
| $ version 1.1
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| 
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| # Signals in entities :
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| /core_dram_tb/dram/rst
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| /core_dram_tb/dram/system_clk
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| /core_dram_tb/dram/system_reset
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| /core_dram_tb/dram/wb_in
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| /core_dram_tb/dram/wb_out
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| /core_dram_tb/dram/user_port0_cmd_valid
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| /core_dram_tb/dram/user_port0_cmd_ready
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| /core_dram_tb/dram/user_port0_cmd_we
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| /core_dram_tb/dram/user_port0_cmd_addr
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| /core_dram_tb/dram/user_port0_wdata_valid
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| /core_dram_tb/dram/user_port0_wdata_ready
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| /core_dram_tb/dram/user_port0_wdata_we
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| /core_dram_tb/dram/user_port0_wdata_data
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| /core_dram_tb/dram/user_port0_rdata_valid
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| /core_dram_tb/dram/user_port0_rdata_ready
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| /core_dram_tb/dram/user_port0_rdata_data
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| /core_dram_tb/dram/cache_tags
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| /core_dram_tb/dram/cache_valids
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| /core_dram_tb/dram/storeq_rd_ready
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| /core_dram_tb/dram/storeq_rd_valid
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| /core_dram_tb/dram/storeq_rd_data
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| /core_dram_tb/dram/storeq_wr_ready
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| /core_dram_tb/dram/storeq_wr_valid
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| /core_dram_tb/dram/storeq_wr_data
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| /core_dram_tb/dram/accept_store
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| /core_dram_tb/dram/state
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| /core_dram_tb/dram/wb_req
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| /core_dram_tb/dram/store_queued
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| /core_dram_tb/dram/read_ack_0
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| /core_dram_tb/dram/read_ack_1
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| /core_dram_tb/dram/read_ad3_0
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| /core_dram_tb/dram/read_ad3_1
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| /core_dram_tb/dram/read_way_0
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| /core_dram_tb/dram/read_way_1
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| /core_dram_tb/dram/req_index
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| /core_dram_tb/dram/req_row
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| /core_dram_tb/dram/req_hit_way
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| /core_dram_tb/dram/req_tag
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| /core_dram_tb/dram/req_op
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| /core_dram_tb/dram/req_laddr
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| /core_dram_tb/dram/req_ad3
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| /core_dram_tb/dram/req_we
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| /core_dram_tb/dram/req_wdata
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| /core_dram_tb/dram/store_way
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| /core_dram_tb/dram/store_index
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| /core_dram_tb/dram/store_row
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| /core_dram_tb/dram/cache_out
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| /core_dram_tb/dram/plru_victim
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| /core_dram_tb/dram/replace_way
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| /core_dram_tb/dram/rams/do_read
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| /core_dram_tb/dram/rams/do_write
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| /core_dram_tb/dram/rams/rd_addr
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| /core_dram_tb/dram/rams/wr_addr
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| /core_dram_tb/dram/rams/wr_data
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| /core_dram_tb/dram/rams/wr_sel
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| /core_dram_tb/dram/rams/wr_sel_m
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| /core_dram_tb/dram/rams/dout
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| /core_dram_tb/dram/rams/way/clk
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| /core_dram_tb/dram/rams/way/rd_en
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| /core_dram_tb/dram/rams/way/rd_addr
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| /core_dram_tb/dram/rams/way/rd_data
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| /core_dram_tb/dram/rams/way/wr_sel
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| /core_dram_tb/dram/rams/way/wr_addr
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| /core_dram_tb/dram/rams/way/wr_data
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| /core_dram_tb/dram/rams/way/rd_data0
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| /core_dram_tb/dram/store_queue/wr_ready
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| /core_dram_tb/dram/store_queue/wr_valid
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| /core_dram_tb/dram/store_queue/wr_data
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| /core_dram_tb/dram/store_queue/rd_ready
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| /core_dram_tb/dram/store_queue/rd_valid
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| /core_dram_tb/dram/store_queue/rd_data
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| /core_dram_tb/dram/store_queue/rd_idx
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| /core_dram_tb/dram/store_queue/rd_next
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| /core_dram_tb/dram/store_queue/wr_idx
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| /core_dram_tb/dram/store_queue/wr_next
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| /core_dram_tb/dram/store_queue/op_prev
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| /core_dram_tb/dram/store_queue/op_next
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| /core_dram_tb/dram/store_queue/full
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| /core_dram_tb/dram/store_queue/empty
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| /core_dram_tb/dram/store_queue/push
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| /core_dram_tb/dram/store_queue/pop
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