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58 lines
1.5 KiB
VHDL
58 lines
1.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.common.all;
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package crhelpers is
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subtype crnum_t is integer range 0 to 7;
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subtype crmask_t is std_ulogic_vector(7 downto 0);
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function fxm_to_num(fxm: crmask_t) return crnum_t;
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function num_to_fxm(num: crnum_t) return crmask_t;
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end package crhelpers;
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package body crhelpers is
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function fxm_to_num(fxm: crmask_t) return crnum_t is
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begin
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-- If multiple fields are set (undefined), match existing
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-- hardware by returning the first one.
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for i in 0 to 7 loop
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-- Big endian bit numbering
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if fxm(7-i) = '1' then
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return i;
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end if;
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end loop;
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-- If no fields are set (undefined), also match existing
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-- hardware by returning cr7.
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return 7;
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end;
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function num_to_fxm(num: crnum_t) return crmask_t is
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begin
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case num is
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when 0 =>
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return "10000000";
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when 1 =>
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return "01000000";
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when 2 =>
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return "00100000";
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when 3 =>
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return "00010000";
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when 4 =>
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return "00001000";
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when 5 =>
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return "00000100";
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when 6 =>
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return "00000010";
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when 7 =>
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return "00000001";
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when others =>
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return "00000000";
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end case;
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end;
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end package body crhelpers;
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