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25 lines
427 B
Verilog
25 lines
427 B
Verilog
module multiply_add_64x64
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#(
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parameter BITS=64
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) (
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`ifdef USE_POWER_PINS
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inout VPWR,
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inout VGND,
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`endif
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input clk,
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input [BITS-1:0] a,
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input [BITS-1:0] b,
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input [BITS*2-1:0] c,
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output [BITS*2-1:0] o
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);
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reg [BITS*2-1:0] o_tmp[2:0];
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always @(posedge clk) begin
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o_tmp[2] = o_tmp[1];
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o_tmp[1] = o_tmp[0];
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o_tmp[0] = (a * b) + c;
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end
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assign o = o_tmp[2];
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endmodule
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