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392 lines
12 KiB
VHDL
392 lines
12 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.wishbone_types.all;
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entity spi_rxtx is
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generic (
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DATA_LINES : positive := 1; -- Number of data lines
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-- 1=MISO/MOSI, otherwise 2 or 4
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INPUT_DELAY : natural range 0 to 1 := 1 -- Delay latching of SPI input:
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-- 0=no delay, 1=clk/2
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);
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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--
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-- Clock divider
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-- SCK = CLK/((CLK_DIV+1)*2) : 0=CLK/2, 1=CLK/4, 2=CLK/6....
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--
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-- This need to be changed before a command.
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-- XX TODO add handshake
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clk_div_i : in natural range 0 to 255;
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--
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-- Command port (includes write data)
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--
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-- Valid & ready: command sampled when valid=1 and ready=1
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cmd_valid_i : in std_ulogic;
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cmd_ready_o : out std_ulogic;
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-- Command modes:
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-- 000 : Single bit read+write
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-- 010 : Single bit read
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-- 011 : Single bit write
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-- 100 : Dual read
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-- 101 : Dual write
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-- 110 : Quad read
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-- 111 : Quad write
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cmd_mode_i : in std_ulogic_vector(2 downto 0);
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-- # clocks-1 in a command (#bits-1)
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cmd_clks_i : in std_ulogic_vector(2 downto 0);
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-- Write data (sampled with command)
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cmd_txd_i : in std_ulogic_vector(7 downto 0);
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--
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-- Read data port. Data valid when d_ack=1, no ready
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-- signal, receiver must be ready
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--
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d_rxd_o : out std_ulogic_vector(7 downto 0);
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d_ack_o : out std_ulogic := '0';
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-- Set when all commands are done. Needed for callers to know when
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-- to release CS#
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bus_idle_o : out std_ulogic;
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--
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-- SPI port. These might need to go into special IOBUFs or STARTUPE2 on
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-- Xilinx.
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--
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-- Data lines are organized as follow:
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--
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-- DATA_LINES = 1
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--
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-- sdat_o(0) is MOSI (master output slave input)
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-- sdat_i(0) is MISO (master input slave output)
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--
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-- DATA_LINES > 1
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--
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-- sdat_o(0..n) are DQ(0..n)
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-- sdat_i(0..n) are DQ(0..n)
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--
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-- as such, beware that:
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--
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-- sdat_o(0) is MOSI (master output slave input)
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-- sdat_i(1) is MISO (master input slave output)
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--
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-- In order to leave dealing with the details of how to wire the tristate
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-- and bidirectional pins to the system specific toplevel, we separate
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-- the input and output signals, and provide a "sdat_oe" signal which
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-- is the "output enable" of each line.
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--
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sck : out std_ulogic;
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sdat_o : out std_ulogic_vector(DATA_LINES-1 downto 0);
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sdat_oe : out std_ulogic_vector(DATA_LINES-1 downto 0);
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sdat_i : in std_ulogic_vector(DATA_LINES-1 downto 0)
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);
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end entity spi_rxtx;
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architecture rtl of spi_rxtx is
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-- Internal clock signal. Output is gated by sck_en_int
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signal sck_0 : std_ulogic;
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signal sck_1 : std_ulogic;
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-- Clock divider latch
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signal clk_div : natural range 0 to 255;
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-- 1 clk pulses indicating when to send and when to latch
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--
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-- Typically for CPOL=CPHA
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-- sck_send is sck falling edge
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-- sck_recv is sck rising edge
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--
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-- Those pulses are generated "ahead" of the corresponding
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-- edge so then are "seen" at the rising sysclk edge matching
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-- the corresponding sck edgeg.
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signal sck_send : std_ulogic;
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signal sck_recv : std_ulogic;
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-- Command mode latch
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signal cmd_mode : std_ulogic_vector(2 downto 0);
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-- Output shift register (use fifo ?)
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signal oreg : std_ulogic_vector(7 downto 0);
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-- Input latch
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signal dat_i_l : std_ulogic_vector(DATA_LINES-1 downto 0);
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-- Data ack latch
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signal dat_ack_l : std_ulogic;
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-- Delayed recv signal for the read machine
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signal sck_recv_d : std_ulogic := '0';
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-- Input shift register (use fifo ?)
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signal ireg : std_ulogic_vector(7 downto 0) := (others => '0');
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-- Bit counter
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signal bit_count : std_ulogic_vector(2 downto 0);
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-- Next/start/stop command signals. Set when counter goes negative
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signal next_cmd : std_ulogic;
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signal start_cmd : std_ulogic;
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signal end_cmd : std_ulogic;
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function data_single(mode : std_ulogic_vector(2 downto 0)) return boolean is
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begin
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return mode(2) = '0';
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end;
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function data_dual(mode : std_ulogic_vector(2 downto 0)) return boolean is
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begin
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return mode(2 downto 1) = "10";
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end;
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function data_quad(mode : std_ulogic_vector(2 downto 0)) return boolean is
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begin
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return mode(2 downto 1) = "11";
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end;
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function data_write(mode : std_ulogic_vector(2 downto 0)) return boolean is
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begin
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return mode(0) = '1';
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end;
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type state_t is (STANDBY, DATA);
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signal state : state_t := STANDBY;
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begin
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-- We don't support multiple data lines at this point
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assert DATA_LINES = 1 or DATA_LINES = 2 or DATA_LINES = 4
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report "Unsupported DATA_LINES configuration !" severity failure;
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-- Clock generation
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--
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-- XX HARD WIRE CPOL=1 CPHA=1 for now
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sck_gen: process(clk)
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variable counter : integer range 0 to 255;
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begin
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if rising_edge(clk) then
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if rst = '1' then
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sck_0 <= '1';
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sck_1 <= '1';
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sck_send <= '0';
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sck_recv <= '0';
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clk_div <= 0;
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counter := 0;
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elsif counter = clk_div then
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counter := 0;
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-- Latch new divider
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clk_div <= clk_div_i;
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-- Internal version of the clock
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sck_0 <= not sck_0;
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-- Generate send/receive pulses to run out state machine
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sck_recv <= not sck_0;
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sck_send <= sck_0;
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else
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counter := counter + 1;
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sck_recv <= '0';
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sck_send <= '0';
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end if;
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-- Delayed version of the clock to line up with
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-- the up/down signals
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--
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-- XXX Figure out a better way
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if (state = DATA and end_cmd = '0') or (next_cmd = '1' and cmd_valid_i = '1') then
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sck_1 <= sck_0;
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else
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sck_1 <= '1';
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end if;
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end if;
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end process;
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-- SPI clock
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sck <= sck_1;
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-- Ready to start the next command. This is set on the clock down
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-- after the counter goes negative.
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-- Note: in addition to latching a new command, this will cause
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-- the counter to be reloaded.
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next_cmd <= '1' when sck_send = '1' and bit_count = "111" else '0';
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-- We start a command when we have a valid request at that time.
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start_cmd <= next_cmd and cmd_valid_i;
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-- We end commands if we get start_cmd and there's nothing to
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-- start. This sends up to standby holding CLK high
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end_cmd <= next_cmd and not cmd_valid_i;
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-- Generate cmd_ready. It will go up and down with sck, we could
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-- gate it with cmd_valid to make it look cleaner but that would
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-- add yet another combinational loop on the wishbone that I'm
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-- to avoid.
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cmd_ready_o <= next_cmd;
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-- Generate bus_idle_o
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bus_idle_o <= '1' when state = STANDBY else '0';
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-- Main state machine. Also generates cmd and data ACKs
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machine: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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state <= STANDBY;
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cmd_mode <= "000";
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else
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-- First clk down of a new cycle. Latch a request if any
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-- or get out.
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if start_cmd = '1' then
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state <= DATA;
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cmd_mode <= cmd_mode_i;
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elsif end_cmd = '1' then
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state <= STANDBY;
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end if;
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end if;
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end if;
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end process;
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-- Run the bit counter in DATA state. It will update on rising
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-- SCK edges. It starts at d_clks on command latch
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count_bit: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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bit_count <= (others => '0');
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else
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if start_cmd = '1' then
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bit_count <= cmd_clks_i;
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elsif state /= DATA then
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bit_count <= (others => '1');
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elsif sck_recv = '1' then
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bit_count <= std_ulogic_vector(unsigned(bit_count) - 1);
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end if;
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end if;
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end if;
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end process;
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-- Shift output data
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shift_out: process(clk)
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begin
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if rising_edge(clk) then
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-- Starting a command
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if start_cmd = '1' then
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oreg <= cmd_txd_i(7 downto 0);
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elsif sck_send = '1' then
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-- Get shift amount
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if data_single(cmd_mode) then
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oreg <= oreg(6 downto 0) & '0';
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elsif data_dual(cmd_mode) then
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oreg <= oreg(5 downto 0) & "00";
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else
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oreg <= oreg(3 downto 0) & "0000";
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end if;
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end if;
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end if;
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end process;
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-- Data out
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sdat_o(0) <= oreg(7);
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dl2: if DATA_LINES > 1 generate
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sdat_o(1) <= oreg(6);
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end generate;
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dl4: if DATA_LINES > 2 generate
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sdat_o(2) <= oreg(5);
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sdat_o(3) <= oreg(4);
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end generate;
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-- Data lines direction
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dlines: process(all)
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begin
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for i in DATA_LINES-1 downto 0 loop
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sdat_oe(i) <= '0';
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if state = DATA then
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-- In single mode, we always enable MOSI, otherwise
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-- we control the output enable based on the direction
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-- of transfer.
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--
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if i = 0 and (data_single(cmd_mode) or data_write(cmd_mode)) then
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sdat_oe(i) <= '1';
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end if;
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if i = 1 and data_dual(cmd_mode) and data_write(cmd_mode) then
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sdat_oe(i) <= '1';
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end if;
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if i > 0 and data_quad(cmd_mode) and data_write(cmd_mode) then
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sdat_oe(i) <= '1';
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end if;
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end if;
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end loop;
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end process;
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-- Latch input data no delay
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input_delay_0: if INPUT_DELAY = 0 generate
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process(clk)
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begin
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if rising_edge(clk) then
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dat_i_l <= sdat_i;
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end if;
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end process;
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end generate;
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-- Latch input data half clock delay
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input_delay_1: if INPUT_DELAY = 1 generate
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process(clk)
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begin
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if falling_edge(clk) then
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dat_i_l <= sdat_i;
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end if;
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end process;
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end generate;
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-- Shift input data
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shift_in: process(clk)
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begin
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if rising_edge(clk) then
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-- Delay the receive signal to match the input latch
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if state = DATA then
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sck_recv_d <= sck_recv;
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else
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sck_recv_d <= '0';
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end if;
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-- Generate read data acks
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if bit_count = "000" and sck_recv = '1' then
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dat_ack_l <= not cmd_mode(0);
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else
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dat_ack_l <= '0';
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end if;
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-- And delay them as well
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d_ack_o <= dat_ack_l;
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-- Shift register on delayed data & receive signal
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if sck_recv_d = '1' then
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if DATA_LINES = 1 then
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ireg <= ireg(6 downto 0) & dat_i_l(0);
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else
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if data_dual(cmd_mode) then
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ireg <= ireg(5 downto 0) & dat_i_l(1) & dat_i_l(0);
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elsif data_quad(cmd_mode) then
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ireg <= ireg(3 downto 0) & dat_i_l(3) & dat_i_l(2) & dat_i_l(1) & dat_i_l(0);
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else
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assert(data_single(cmd_mode));
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ireg <= ireg(6 downto 0) & dat_i_l(1);
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end if;
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end if;
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end if;
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end if;
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end process;
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-- Data recieve register
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d_rxd_o <= ireg;
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end architecture;
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