cores
/
microwatt
mirror of https://github.com/antonblanchard/microwatt
3
1
Fork 1
Code Issues Projects Releases Wiki Activity
You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
master
caravel-mpw7-20221125
caravel-mpw7-20220822
branch-alias
trace-test
gitignore
litedram-update
liteeth-update
fix-sdcard
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '4b2c23703c'
${ noResults }
microwatt/litedram/gen-src/sdram_init
History
Benjamin Herrenschmidt 079af6443e litedram: Update generator to work with latest LiteX 
Some changes in LiteX broke us. Adapt the build system and
increase the init RAM size to 24KB.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		4 years ago
..
include litedram: Update generator to work with latest LiteX 4 years ago
libc litedram: Add support for Microwatt-initialized controller 5 years ago
Makefile litedram: Update generator to work with latest LiteX 4 years ago
bin2hex.py litedram: Add basic support for LiteX LiteDRAM 5 years ago
head.S litedram: Update generator to work with latest LiteX 4 years ago
main.c litedram: Update generator to work with latest LiteX 4 years ago
sdram_init.lds.S soc: Rework interconnect 5 years ago