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71 lines
1.9 KiB
VHDL
71 lines
1.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.wishbone_types.all;
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-- TODO: Use an array of master/slaves with parametric size
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entity wishbone_arbiter is
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generic(
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NUM_MASTERS : positive := 3
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);
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port (clk : in std_ulogic;
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rst : in std_ulogic;
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wb_masters_in : in wishbone_master_out_vector(0 to NUM_MASTERS-1);
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wb_masters_out : out wishbone_slave_out_vector(0 to NUM_MASTERS-1);
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wb_slave_out : out wishbone_master_out;
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wb_slave_in : in wishbone_slave_out
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);
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end wishbone_arbiter;
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architecture behave of wishbone_arbiter is
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subtype wb_arb_master_t is integer range 0 to NUM_MASTERS-1;
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signal candidate, selected : wb_arb_master_t;
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signal busy : std_ulogic;
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begin
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busy <= wb_masters_in(selected).cyc;
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wishbone_muxes: process(selected, candidate, busy, wb_slave_in, wb_masters_in)
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variable early_sel : wb_arb_master_t;
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begin
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early_sel := selected;
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if busy = '0' then
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early_sel := candidate;
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end if;
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wb_slave_out <= wb_masters_in(early_sel);
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for i in 0 to NUM_MASTERS-1 loop
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wb_masters_out(i).dat <= wb_slave_in.dat;
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wb_masters_out(i).ack <= wb_slave_in.ack when early_sel = i else '0';
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wb_masters_out(i).stall <= wb_slave_in.stall when early_sel = i else '1';
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end loop;
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end process;
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-- Candidate selection is dumb, priority order... we could
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-- instead consider some form of fairness but it's not really
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-- an issue at the moment.
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--
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wishbone_candidate: process(all)
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begin
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candidate <= selected;
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for i in NUM_MASTERS-1 downto 0 loop
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if wb_masters_in(i).cyc = '1' then
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candidate <= i;
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end if;
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end loop;
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end process;
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wishbone_arbiter_process: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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selected <= 0;
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elsif busy = '0' then
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selected <= candidate;
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end if;
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end if;
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end process;
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end behave;
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