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135 lines
4.6 KiB
VHDL
135 lines
4.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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entity register_file is
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generic (
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SIM : boolean := false
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);
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port(
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clk : in std_logic;
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d_in : in Decode2ToRegisterFileType;
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d_out : out RegisterFileToDecode2Type;
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w_in : in WritebackToRegisterFileType;
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dbg_gpr_req : in std_ulogic;
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dbg_gpr_ack : out std_ulogic;
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dbg_gpr_addr : in gspr_index_t;
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dbg_gpr_data : out std_ulogic_vector(63 downto 0);
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-- debug
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sim_dump : in std_ulogic;
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sim_dump_done : out std_ulogic
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);
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end entity register_file;
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architecture behaviour of register_file is
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type regfile is array(0 to 63) of std_ulogic_vector(63 downto 0);
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signal registers : regfile := (others => (others => '0'));
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signal rd_port_b : std_ulogic_vector(63 downto 0);
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signal dbg_data : std_ulogic_vector(63 downto 0);
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signal dbg_ack : std_ulogic;
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begin
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-- synchronous writes
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register_write_0: process(clk)
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begin
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if rising_edge(clk) then
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if w_in.write_enable = '1' then
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assert not(is_x(w_in.write_data)) and not(is_x(w_in.write_reg)) severity failure;
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if w_in.write_reg(5) = '0' then
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report "Writing GPR " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data);
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else
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report "Writing GSPR " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data);
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end if;
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registers(to_integer(unsigned(w_in.write_reg))) <= w_in.write_data;
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end if;
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end if;
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end process register_write_0;
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-- asynchronous reads
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register_read_0: process(all)
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variable b_addr : gspr_index_t;
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begin
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if d_in.read1_enable = '1' then
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report "Reading GPR " & to_hstring(d_in.read1_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read1_reg))));
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end if;
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if d_in.read2_enable = '1' then
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report "Reading GPR " & to_hstring(d_in.read2_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read2_reg))));
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end if;
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if d_in.read3_enable = '1' then
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report "Reading GPR " & to_hstring(d_in.read3_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read3_reg))));
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end if;
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d_out.read1_data <= registers(to_integer(unsigned(d_in.read1_reg)));
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-- B read port is multiplexed with reads from the debug circuitry
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if d_in.read2_enable = '0' and dbg_gpr_req = '1' and dbg_ack = '0' then
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b_addr := dbg_gpr_addr;
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else
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b_addr := d_in.read2_reg;
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end if;
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rd_port_b <= registers(to_integer(unsigned(b_addr)));
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d_out.read2_data <= rd_port_b;
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d_out.read3_data <= registers(to_integer(unsigned(gpr_to_gspr(d_in.read3_reg))));
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-- Forward any written data
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if w_in.write_enable = '1' then
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if d_in.read1_reg = w_in.write_reg then
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d_out.read1_data <= w_in.write_data;
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end if;
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if d_in.read2_reg = w_in.write_reg then
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d_out.read2_data <= w_in.write_data;
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end if;
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if gpr_to_gspr(d_in.read3_reg) = w_in.write_reg then
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d_out.read3_data <= w_in.write_data;
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end if;
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end if;
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end process register_read_0;
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-- Latch read data and ack if dbg read requested and B port not busy
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dbg_register_read: process(clk)
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begin
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if rising_edge(clk) then
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if dbg_gpr_req = '1' then
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if d_in.read2_enable = '0' and dbg_ack = '0' then
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dbg_data <= rd_port_b;
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dbg_ack <= '1';
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end if;
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else
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dbg_ack <= '0';
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end if;
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end if;
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end process;
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dbg_gpr_ack <= dbg_ack;
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dbg_gpr_data <= dbg_data;
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-- Dump registers if core terminates
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sim_dump_test: if SIM generate
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dump_registers: process(all)
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begin
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if sim_dump = '1' then
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loop_0: for i in 0 to 31 loop
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report "GPR" & integer'image(i) & " " & to_hstring(registers(i));
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end loop loop_0;
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report "LR " & to_hstring(registers(to_integer(unsigned(fast_spr_num(SPR_LR)))));
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report "CTR " & to_hstring(registers(to_integer(unsigned(fast_spr_num(SPR_CTR)))));
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report "XER " & to_hstring(registers(to_integer(unsigned(fast_spr_num(SPR_XER)))));
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sim_dump_done <= '1';
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else
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sim_dump_done <= '0';
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end if;
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end process;
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end generate;
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-- Keep GHDL synthesis happy
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sim_dump_test_synth: if not SIM generate
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sim_dump_done <= '0';
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end generate;
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end architecture behaviour;
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