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246 lines
7.8 KiB
VHDL
246 lines
7.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.common.all;
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entity control is
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generic (
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PIPELINE_DEPTH : natural := 2
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);
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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complete_in : in std_ulogic;
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valid_in : in std_ulogic;
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flush_in : in std_ulogic;
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stall_in : in std_ulogic;
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sgl_pipe_in : in std_ulogic;
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stop_mark_in : in std_ulogic;
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gpr_write_valid_in : in std_ulogic;
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gpr_write_in : in gspr_index_t;
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gpr_bypassable : in std_ulogic;
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gpr_a_read_valid_in : in std_ulogic;
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gpr_a_read_in : in gspr_index_t;
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gpr_b_read_valid_in : in std_ulogic;
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gpr_b_read_in : in gspr_index_t;
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gpr_c_read_valid_in : in std_ulogic;
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gpr_c_read_in : in gpr_index_t;
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cr_read_in : in std_ulogic;
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cr_write_in : in std_ulogic;
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valid_out : out std_ulogic;
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stall_out : out std_ulogic;
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stopped_out : out std_ulogic;
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gpr_bypass_a : out std_ulogic;
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gpr_bypass_b : out std_ulogic;
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gpr_bypass_c : out std_ulogic
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);
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end entity control;
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architecture rtl of control is
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type state_type is (IDLE, WAIT_FOR_PREV_TO_COMPLETE, WAIT_FOR_CURR_TO_COMPLETE);
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type reg_internal_type is record
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state : state_type;
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outstanding : integer range -1 to PIPELINE_DEPTH+2;
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end record;
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constant reg_internal_init : reg_internal_type := (state => IDLE, outstanding => 0);
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signal r_int, rin_int : reg_internal_type := reg_internal_init;
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signal stall_a_out : std_ulogic;
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signal stall_b_out : std_ulogic;
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signal stall_c_out : std_ulogic;
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signal cr_stall_out : std_ulogic;
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signal gpr_write_valid : std_ulogic := '0';
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signal cr_write_valid : std_ulogic := '0';
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signal gpr_c_read_in_fmt : std_ulogic_vector(5 downto 0);
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begin
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gpr_hazard0: entity work.gpr_hazard
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generic map (
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PIPELINE_DEPTH => PIPELINE_DEPTH
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)
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port map (
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clk => clk,
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stall_in => stall_in,
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gpr_write_valid_in => gpr_write_valid,
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gpr_write_in => gpr_write_in,
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bypass_avail => gpr_bypassable,
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gpr_read_valid_in => gpr_a_read_valid_in,
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gpr_read_in => gpr_a_read_in,
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stall_out => stall_a_out,
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use_bypass => gpr_bypass_a
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);
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gpr_hazard1: entity work.gpr_hazard
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generic map (
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PIPELINE_DEPTH => PIPELINE_DEPTH
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)
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port map (
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clk => clk,
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stall_in => stall_in,
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gpr_write_valid_in => gpr_write_valid,
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gpr_write_in => gpr_write_in,
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bypass_avail => gpr_bypassable,
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gpr_read_valid_in => gpr_b_read_valid_in,
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gpr_read_in => gpr_b_read_in,
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stall_out => stall_b_out,
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use_bypass => gpr_bypass_b
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);
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gpr_c_read_in_fmt <= "0" & gpr_c_read_in;
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gpr_hazard2: entity work.gpr_hazard
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generic map (
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PIPELINE_DEPTH => PIPELINE_DEPTH
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)
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port map (
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clk => clk,
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stall_in => stall_in,
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gpr_write_valid_in => gpr_write_valid,
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gpr_write_in => gpr_write_in,
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bypass_avail => gpr_bypassable,
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gpr_read_valid_in => gpr_c_read_valid_in,
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gpr_read_in => gpr_c_read_in_fmt,
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stall_out => stall_c_out,
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use_bypass => gpr_bypass_c
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);
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cr_hazard0: entity work.cr_hazard
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generic map (
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PIPELINE_DEPTH => PIPELINE_DEPTH
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)
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port map (
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clk => clk,
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stall_in => stall_in,
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cr_read_in => cr_read_in,
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cr_write_in => cr_write_valid,
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stall_out => cr_stall_out
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);
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control0: process(clk)
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begin
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if rising_edge(clk) then
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assert r_int.outstanding >= 0 and r_int.outstanding <= (PIPELINE_DEPTH+1) report "Outstanding bad " & integer'image(r_int.outstanding) severity failure;
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r_int <= rin_int;
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end if;
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end process;
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control1 : process(all)
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variable v_int : reg_internal_type;
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variable valid_tmp : std_ulogic;
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variable stall_tmp : std_ulogic;
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begin
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v_int := r_int;
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-- asynchronous
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valid_tmp := valid_in and not flush_in and not stall_in;
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stall_tmp := stall_in;
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if complete_in = '1' then
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v_int.outstanding := r_int.outstanding - 1;
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end if;
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if rst = '1' then
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v_int.state := IDLE;
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v_int.outstanding := 0;
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stall_tmp := '0';
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valid_tmp := '0';
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end if;
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-- Handle debugger stop
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stopped_out <= '0';
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if stop_mark_in = '1' and v_int.outstanding = 0 then
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stopped_out <= '1';
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end if;
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-- state machine to handle instructions that must be single
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-- through the pipeline.
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case r_int.state is
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when IDLE =>
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if valid_tmp = '1' then
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if (sgl_pipe_in = '1') then
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if v_int.outstanding /= 0 then
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v_int.state := WAIT_FOR_PREV_TO_COMPLETE;
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stall_tmp := '1';
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else
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-- send insn out and wait on it to complete
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v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
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end if;
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else
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-- let it go out if there are no GPR hazards
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stall_tmp := stall_a_out or stall_b_out or stall_c_out or cr_stall_out;
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end if;
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end if;
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when WAIT_FOR_PREV_TO_COMPLETE =>
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if v_int.outstanding = 0 then
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-- send insn out and wait on it to complete
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v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
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else
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stall_tmp := '1';
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end if;
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when WAIT_FOR_CURR_TO_COMPLETE =>
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if v_int.outstanding = 0 then
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v_int.state := IDLE;
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-- XXX Don't replicate this
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if valid_tmp = '1' then
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if (sgl_pipe_in = '1') then
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if v_int.outstanding /= 0 then
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v_int.state := WAIT_FOR_PREV_TO_COMPLETE;
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stall_tmp := '1';
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else
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-- send insn out and wait on it to complete
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v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
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end if;
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else
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-- let it go out if there are no GPR hazards
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stall_tmp := stall_a_out or stall_b_out or stall_c_out or cr_stall_out;
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end if;
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end if;
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else
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stall_tmp := '1';
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end if;
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end case;
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if stall_tmp = '1' then
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valid_tmp := '0';
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end if;
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if valid_tmp = '1' then
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v_int.outstanding := v_int.outstanding + 1;
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gpr_write_valid <= gpr_write_valid_in;
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cr_write_valid <= cr_write_in;
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else
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gpr_write_valid <= '0';
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cr_write_valid <= '0';
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end if;
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-- update outputs
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valid_out <= valid_tmp;
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stall_out <= stall_tmp;
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-- update registers
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rin_int <= v_int;
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end process;
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end;
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