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205 lines
8.4 KiB
VHDL
205 lines
8.4 KiB
VHDL
-- Sim GPIO, based on potato GPIO by
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-- Kristian Klomsten Skordal.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.sim_console.all;
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--! @brief Generic Wishbone GPIO Module.
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--!
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--! The following registers are defined:
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--! |---------|------------------------------------------------------------------|
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--! | Address | Description |
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--! |---------|------------------------------------------------------------------|
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--! | 0x00 | Describes the port: (read-only) |
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--! | | bits 0-5: The number of pins |
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--! | 0x08 | Input values, one bit per pin (read/write), |
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--! | | If the pin is set to output, writing 1 will toggle the pin |
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--! | 0x10 | Output values, one bit per pin (read/write) |
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--! | 0x18 | Set register, Output = Output | set register (write-only) |
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--! | 0x20 | Clear register, Output = Output & ~(clear register) (write-only) |
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--! | 0x28 | Type, three bits per pin (read/write), pins 0-20 |
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--! | 0x30 | Type, three bits per pin (read/write), pins 21-41 |
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--! | 0x38 | Type, three bits per pin (read/write), pins 42-63 |
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--! | | Types: MSB LSB |
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--! | | 0 0 0 Input, Interrupt disabled |
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--! | | 0 1 0 Input, Interrupt when low |
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--! | | 0 1 1 Input, Interrupt when high |
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--! | | 1 0 0 Input, Interrupt when falling |
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--! | | 1 0 1 Input, Interrupt when rising |
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--! | | 1 1 1 Output |
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--! | | others Undefined |
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--! | 0x40 | Interrupt Triggered, one bit per pin (read/write) |
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--! |---------|------------------------------------------------------------------|
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--!
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--! Writes to the output register for input pins are ignored.
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entity pp_soc_gpio is
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generic(
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NUM_GPIOS : natural := 64
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);
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port(
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clk : in std_logic;
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reset : in std_logic;
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irq : out std_logic;
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-- GPIO interface:
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gpio : inout std_logic_vector(NUM_GPIOS - 1 downto 0);
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-- Wishbone interface:
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wb_adr_in : in std_logic_vector(7 downto 0);
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wb_dat_in : in std_logic_vector(63 downto 0);
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wb_dat_out : out std_logic_vector(63 downto 0);
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wb_cyc_in : in std_logic;
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wb_stb_in : in std_logic;
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wb_we_in : in std_logic;
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wb_ack_out : out std_logic
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);
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end entity pp_soc_gpio;
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architecture behaviour of pp_soc_gpio is
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type type_array is array (natural range 0 to NUM_GPIOS - 1) of
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std_logic_vector(2 downto 0);
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signal input_buffer : std_logic_vector(NUM_GPIOS - 1 downto 0);
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signal input_register_prev : std_logic_vector(NUM_GPIOS - 1 downto 0);
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signal input_register : std_logic_vector(NUM_GPIOS - 1 downto 0);
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signal output_register : std_logic_vector(NUM_GPIOS - 1 downto 0);
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signal type_register : type_array;
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signal irq_triggered_register : std_logic_vector(NUM_GPIOS - 1 downto 0);
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signal ack : std_logic := '0';
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begin
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assert NUM_GPIOS >= 0 and NUM_GPIOS <= 64
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report "Only a number between 0 and 64 (inclusive) GPIOs are supported!"
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severity FAILURE;
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wb_ack_out <= ack and wb_cyc_in and wb_stb_in;
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wishbone: process(clk)
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begin
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if rising_edge(clk) then
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for i in 0 to NUM_GPIOS - 1 loop
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gpio(i) <= output_register(i) when type_register(i) = b"111" else 'Z';
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input_register_prev(i) <= input_register(i);
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input_register(i) <= input_buffer(i);
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input_buffer(i) <= gpio(i) when type_register(i) /= b"111";
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case type_register(i) is
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when b"010" =>
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if gpio(i) = '0' then
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irq_triggered_register(i) <= '1';
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irq <= '1';
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end if;
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when b"011" =>
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if gpio(i) = '1' then
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irq_triggered_register(i) <= '1';
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irq <= '1';
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end if;
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when b"100" =>
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if input_register(i) = '0' and input_register_prev(i) = '1' then
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irq_triggered_register(i) <= '1';
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irq <= '1';
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end if;
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when b"101" =>
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if input_register(i) = '1' and input_register_prev(i) = '0' then
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irq_triggered_register(i) <= '1';
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irq <= '1';
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end if;
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when others =>
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end case;
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end loop;
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if reset = '1' then
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input_register <= (others => '0');
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output_register <= (others => '0');
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wb_dat_out <= (others => '0');
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for i in 0 to NUM_GPIOS - 1 loop
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type_register(i) <= (others => '0');
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end loop;
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irq_triggered_register <= (others => '0');
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ack <= '0';
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else
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if wb_cyc_in = '1' and wb_stb_in = '1' and ack = '0' then
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if wb_we_in = '1' then
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case wb_adr_in is
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when x"08" => --! Input Value
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output_register <= output_register xor wb_dat_in(NUM_GPIOS - 1 downto 0);
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report "GPIO output " & to_hstring(output_register);
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when x"10" => --! Output Value
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output_register <= wb_dat_in(NUM_GPIOS - 1 downto 0);
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report "GPIO output " & to_hstring(output_register);
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when x"18" => --! Set
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output_register <= output_register OR wb_dat_in(NUM_GPIOS - 1 downto 0);
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report "GPIO output " & to_hstring(output_register);
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when x"20" => --! Clear
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output_register <= output_register AND NOT(wb_dat_in(NUM_GPIOS - 1 downto 0));
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report "GPIO output " & to_hstring(output_register);
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when x"28" => --! Type Pins 0-20
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for i in 0 to MINIMUM(NUM_GPIOS - 1, 20) loop
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type_register(i) <= (wb_dat_in((i + 1) * 3 - 1 downto i * 3));
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report "GPIO type for pin " & integer'image(i) & " is " & to_hstring((wb_dat_in((i + 1) * 3 - 1 downto i * 3)));
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end loop;
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when x"30" => --! Type Pins 21-41
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for i in 21 to MINIMUM(NUM_GPIOS - 1, 41) loop
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type_register(i) <= (wb_dat_in((i - 21 + 1) * 3 - 1 downto (i - 21) * 3));
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report "GPIO type for pin " & integer'image(i) & " is " & to_hstring((wb_dat_in((i - 21 + 1) * 3 - 1 downto (i- 21) * 3)));
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end loop;
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when x"38" => --! Type Pins 42-63
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for i in 42 to MINIMUM(NUM_GPIOS - 1, 63) loop
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type_register(i) <= (wb_dat_in((i - 42 + 1) * 3 - 1 downto (i - 42) * 3));
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report "GPIO type for pin " & integer'image(i) & " is " & to_hstring((wb_dat_in((i - 42 + 1) * 3 - 1 downto (i- 21) * 3)));
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end loop;
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when others =>
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end case;
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ack <= '1';
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else
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case wb_adr_in is
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when x"00" => --! Description
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wb_dat_out <= std_logic_vector(to_unsigned(NUM_GPIOS, wb_dat_out'length));
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report "Read GPIO Description register as " & to_hstring(wb_dat_out);
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when x"08" => --! Input Value
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wb_dat_out <= std_logic_vector(resize(unsigned(input_register), wb_dat_out'length));
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report "Read GPIO Input value as " & to_hstring(wb_dat_out);
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when x"10" => --! Output value
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wb_dat_out <= std_logic_vector(resize(unsigned(output_register), wb_dat_out'length));
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report "Read GPIO Output register as " & to_hstring(wb_dat_out);
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when x"28" => --! Type Pins 0-20
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for i in 0 to MINIMUM(NUM_GPIOS - 1, 20) loop
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wb_dat_out((i + 1) * 3 - 1 downto i * 3) <= type_register(i);
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end loop;
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report "Read GPIO Type register 0 as " & to_hstring(wb_dat_out);
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when x"30" => --! Type Pins 21-41
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for i in 21 to MINIMUM(NUM_GPIOS - 1, 41) loop
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wb_dat_out((i - 21 + 1) * 3 - 1 downto (i - 21) * 3) <= type_register(i);
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end loop;
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report "Read GPIO Type register 1 as " & to_hstring(wb_dat_out);
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when x"38" => --! Type Pins 42-63
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for i in 21 to MINIMUM(NUM_GPIOS - 1, 41) loop
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wb_dat_out((i - 21 + 1) * 3 - 1 downto (i - 21) * 3) <= type_register(i);
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end loop;
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report "Read GPIO Type register 2 as " & to_hstring(wb_dat_out);
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when x"40" => --! Interrupts triggered
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wb_dat_out <= std_logic_vector(resize(unsigned(irq_triggered_register), wb_dat_out'length));
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irq_triggered_register <= (others => '0');
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irq <= '0';
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report "Read IRQ Triggered register as " & to_hstring(wb_dat_out);
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when others =>
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end case;
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report "ack";
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ack <= '1';
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end if;
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elsif wb_stb_in = '0' then
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ack <= '0';
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end if;
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end if;
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end if;
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end process wishbone;
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end architecture behaviour; |