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60 lines
1.9 KiB
VHDL
60 lines
1.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity soc_reset is
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generic (
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PLL_RESET_CLOCKS : integer := 32;
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SOC_RESET_CLOCKS : integer := 32;
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RESET_LOW : boolean := true
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);
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port (
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ext_clk : in std_ulogic;
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pll_clk : in std_ulogic;
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pll_locked_in : in std_ulogic;
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ext_rst_in : in std_ulogic;
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pll_rst_out : out std_ulogic;
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rst_out : out std_ulogic
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);
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end soc_reset;
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architecture rtl of soc_reset is
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signal ext_rst_n : std_ulogic;
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signal rst_n : std_ulogic;
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signal pll_rst_reg : std_ulogic_vector(PLL_RESET_CLOCKS downto 0) := (others => '1');
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signal soc_rst_reg : std_ulogic_vector(SOC_RESET_CLOCKS downto 0) := (others => '1');
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begin
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ext_rst_n <= ext_rst_in when RESET_LOW else not ext_rst_in;
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rst_n <= ext_rst_n and pll_locked_in;
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-- PLL reset is active high
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pll_rst_out <= pll_rst_reg(0);
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-- Pass active high reset around
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rst_out <= soc_rst_reg(0);
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-- Wait for external clock to become stable before starting the PLL
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-- By the time the FPGA has been loaded the clock should be well and
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-- truly stable, but lets give it a few cycles to be sure.
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pll_reset_0 : process(ext_clk)
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begin
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if (rising_edge(ext_clk)) then
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pll_rst_reg <= '0' & pll_rst_reg(pll_rst_reg'length-1 downto 1);
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end if;
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end process;
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-- Once our clock is stable and the external reset button isn't being
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-- pressed, assert the SOC reset for long enough for the CPU pipeline
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-- to clear completely.
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soc_reset_0 : process(pll_clk)
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begin
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if (rising_edge(pll_clk)) then
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if (rst_n = '0') then
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soc_rst_reg <= (others => '1');
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else
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soc_rst_reg <= '0' & soc_rst_reg(soc_rst_reg'length-1 downto 1);
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end if;
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end if;
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end process;
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end rtl;
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