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107 lines
2.8 KiB
VHDL
107 lines
2.8 KiB
VHDL
-- Based on:
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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library work;
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use work.wishbone_types.all;
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use work.pp_utilities.all;
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--! @brief Simple memory module for use in Wishbone-based systems.
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entity mw_soc_memory is
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generic(
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MEMORY_SIZE : natural := 4096; --! Memory size in bytes.
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RAM_INIT_FILE : string
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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-- Wishbone interface:
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wishbone_in : in wishbone_master_out;
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wishbone_out : out wishbone_slave_out
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);
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end entity mw_soc_memory;
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architecture behaviour of mw_soc_memory is
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signal wb_adr_in : std_logic_vector(log2(MEMORY_SIZE) - 1 downto 0);
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type ram_t is array(0 to (MEMORY_SIZE / 8) - 1) of std_logic_vector(63 downto 0);
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impure function init_ram(name : STRING) return ram_t is
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file ram_file : text open read_mode is name;
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variable ram_line : line;
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variable temp_word : std_logic_vector(63 downto 0);
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variable temp_ram : ram_t := (others => (others => '0'));
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begin
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for i in 0 to (MEMORY_SIZE/8)-1 loop
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exit when endfile(ram_file);
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readline(ram_file, ram_line);
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hread(ram_line, temp_word);
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temp_ram(i) := temp_word;
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end loop;
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return temp_ram;
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end function;
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signal memory : ram_t := init_ram(RAM_INIT_FILE);
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attribute ram_style : string;
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attribute ram_style of memory : signal is "block";
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attribute ram_decomp : string;
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attribute ram_decomp of memory : signal is "power";
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type state_type is (IDLE, ACK);
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signal state : state_type;
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signal read_ack : std_logic;
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begin
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wb_adr_in <= wishbone_in.adr(log2(MEMORY_SIZE) - 1 downto 0);
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wishbone_out.ack <= read_ack and wishbone_in.stb;
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memory_0: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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read_ack <= '0';
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state <= IDLE;
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else
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if wishbone_in.cyc = '1' then
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case state is
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when IDLE =>
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if wishbone_in.stb = '1' and wishbone_in.we = '1' then
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for i in 0 to 7 loop
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if wishbone_in.sel(i) = '1' then
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memory(to_integer(unsigned(wb_adr_in(wb_adr_in'left downto 3))))(((i + 1) * 8) - 1 downto i * 8)
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<= wishbone_in.dat(((i + 1) * 8) - 1 downto i * 8);
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end if;
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end loop;
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read_ack <= '1';
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state <= ACK;
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elsif wishbone_in.stb = '1' then
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wishbone_out.dat <= memory(to_integer(unsigned(wb_adr_in(wb_adr_in'left downto 3))));
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read_ack <= '1';
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state <= ACK;
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end if;
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when ACK =>
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read_ack <= '0';
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state <= IDLE;
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end case;
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else
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state <= IDLE;
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read_ack <= '0';
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end if;
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end if;
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end if;
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end process;
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end architecture behaviour;
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