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Paul Mackerras af814a0d5e Provide debug access to SPRs in loadstore1 and mmu ... They are accessible as GSPR 0x3c - PID, 0x3d - PTCR, 0x3e - DSISR and 0x3f - DAR. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>		2 years ago
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fmt_log	decode: Add a facility field to the instruction decode tables	3 years ago
mw_debug	Provide debug access to SPRs in loadstore1 and mmu	2 years ago
bin2hex.py	bin2hex: Make sure to generate little endian files	4 years ago
dependencies.py	uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl	4 years ago
gen_icache_tb.py	icache_tb: Improve test and include test file	5 years ago
run_test.sh	Move XER low bits out of register file	2 years ago
run_test_console.sh	Add test cases for new exceptions and supervisor state	4 years ago
test_micropython.py	Update micropython	4 years ago
test_micropython_long.py	Update micropython	4 years ago
test_micropython_verilator.py	makefile: Add some verilator micropython tests	3 years ago
test_micropython_verilator_long.py	makefile: Add some verilator micropython tests	3 years ago
vhdltags	Add VHDL TAGS	4 years ago