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73 lines
2.1 KiB
VHDL
73 lines
2.1 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity plrufn is
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generic (
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BITS : positive := 2
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)
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;
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port (
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acc : in std_ulogic_vector(BITS-1 downto 0);
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tree_in : in std_ulogic_vector(2 ** BITS - 2 downto 0);
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tree_out : out std_ulogic_vector(2 ** BITS - 2 downto 0);
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lru : out std_ulogic_vector(BITS-1 downto 0)
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);
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end entity plrufn;
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architecture rtl of plrufn is
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-- Each level of the tree (from leaf to root) has half the number of nodes
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-- of the previous level. So for a 2^N bits LRU, we have a level of N/2 bits
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-- one of N/4 bits etc.. down to 1. This gives us 2^N-1 nodes. Ie, 2 bits
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-- LRU has 3 nodes (2 + 1), 4 bits LRU has 15 nodes (8 + 4 + 2 + 1) etc...
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constant count : positive := 2 ** BITS - 1;
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subtype node_t is integer range 0 to count - 1;
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begin
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get_lru: process(tree_in)
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variable node : node_t;
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variable abit : std_ulogic;
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begin
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node := 0;
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for i in 0 to BITS-1 loop
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abit := tree_in(node);
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if is_X(abit) then
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abit := '0';
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end if;
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lru(BITS-1-i) <= abit;
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if i /= BITS-1 then
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node := node * 2;
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if abit = '1' then
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node := node + 2;
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else
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node := node + 1;
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end if;
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end if;
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end loop;
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end process;
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update_lru: process(all)
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variable node : node_t;
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variable abit : std_ulogic;
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begin
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tree_out <= tree_in;
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node := 0;
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for i in 0 to BITS-1 loop
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abit := acc(BITS-1-i);
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if is_X(abit) then
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abit := '0';
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end if;
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tree_out(node) <= not abit;
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if i /= BITS-1 then
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node := node * 2;
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if abit = '1' then
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node := node + 2;
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else
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node := node + 1;
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end if;
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end if;
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end loop;
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end process;
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end;
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