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32 lines
757 B
VHDL
32 lines
757 B
VHDL
-- Dummy/empty DMI interface to make toplevel happy on unsupported FPGAs
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.wishbone_types.all;
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entity dmi_dtm is
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generic(ABITS : INTEGER:=8;
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DBITS : INTEGER:=32);
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port(sys_clk : in std_ulogic;
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sys_reset : in std_ulogic;
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dmi_addr : out std_ulogic_vector(ABITS - 1 downto 0);
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dmi_din : in std_ulogic_vector(DBITS - 1 downto 0);
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dmi_dout : out std_ulogic_vector(DBITS - 1 downto 0);
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dmi_req : out std_ulogic;
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dmi_wr : out std_ulogic;
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dmi_ack : in std_ulogic
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);
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end entity dmi_dtm;
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architecture behaviour of dmi_dtm is
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begin
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dmi_addr <= (others => '0');
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dmi_dout <= (others => '0');
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dmi_req <= '0';
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dmi_wr <= '0';
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end architecture behaviour;
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