cores
/
microwatt
mirror of https://github.com/antonblanchard/microwatt
3
1
Fork 1
Code Issues Projects Releases Wiki Activity
You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
master
caravel-mpw7-20221125
caravel-mpw7-20220822
branch-alias
trace-test
gitignore
litedram-update
liteeth-update
fix-sdcard
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '34e10cc52c'
${ noResults }
microwatt/litedram/extras
History
Benjamin Herrenschmidt bedc9c0085 litedram: l2: Add a few comments about litedram behaviour 
litedram ignores a couple of signals of his "pseudo-axi" port,
this adds a bit of documentation around it.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		4 years ago
..
fusesoc-add-files.py litedram: Remove old "VexRiscV" based initializations 5 years ago
litedram-wrapper-l2.vhdl litedram: l2: Add a few comments about litedram behaviour 4 years ago
sim_dram_verilate.mk litedram: Add simulation support 5 years ago
sim_litedram.vhdl litedram: Add simulation support 5 years ago
sim_litedram_c.cpp litedram: Add simulation support 5 years ago
wave.gtkw litedram: Add an L2 cache with store queue 5 years ago
wave.opt litedram: Add an L2 cache with store queue 5 years ago
wave_tb.gtkw litedram: l2: Latency improvements 4 years ago