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microwatt/fpga
Benjamin Herrenschmidt 3349bdc798 ram: Add block RAM pipelining
This adds an output buffer to help with timing and allows the BRAMs
to actually pipeline.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
..
LICENSE
arty_a7.xdc fpga: Arty A7's don't need multiple filesets 5 years ago
clk_gen_bypass.vhd Fix clk_gen_bypass 5 years ago
clk_gen_mcmm.vhd Improve PLL/MMCM clocks configuration 5 years ago
clk_gen_plle2.vhd Improve PLL/MMCM clocks configuration 5 years ago
cmod_a7-35.xdc
firmware.hex
hello_world.hex
mw_soc_memory.vhdl ram: Add block RAM pipelining 5 years ago
nexys-video.xdc
nexys_a7.xdc
pp_fifo.vhd fifo: Reformat 5 years ago
pp_soc_uart.vhd pp_uart: reformat 5 years ago
pp_utilities.vhd
soc_reset.vhdl
soc_reset_tb.vhdl
toplevel.vhdl Add option to not flatten hierarchy 5 years ago