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70 lines
1.6 KiB
VHDL
70 lines
1.6 KiB
VHDL
-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2018 <kristian.skordal@wafflemail.net>
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library ieee;
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use ieee.std_logic_1164.all;
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use work.pp_utilities.all;
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--! @brief System reset unit.
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--! Because most resets in the processor core are synchronous, at least one
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--! clock pulse has to be given to the processor while the reset signal is
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--! asserted. However, if the clock generator is being reset at the same time,
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--! the system clock might not run during reset, preventing the processor from
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--! properly resetting.
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entity pp_soc_reset is
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generic(
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RESET_CYCLE_COUNT : natural := 20000000
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);
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port(
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clk : in std_logic;
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reset_n : in std_logic;
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reset_out : out std_logic;
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system_clk : in std_logic;
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system_clk_locked : in std_logic
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);
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end entity pp_soc_reset;
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architecture behaviour of pp_soc_reset is
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subtype counter_type is natural range 0 to RESET_CYCLE_COUNT;
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signal counter : counter_type;
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signal fast_reset : std_logic := '0';
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signal slow_reset : std_logic := '1';
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begin
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reset_out <= slow_reset;
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-- process(clk)
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-- begin
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-- if rising_edge(clk) then
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-- if reset_n = '0' then
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-- fast_reset <= '1';
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-- elsif system_clk_locked = '1' then
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-- if fast_reset = '1' and slow_reset = '1' then
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-- fast_reset <= '0';
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-- end if;
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-- end if;
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-- end if;
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-- end process;
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process(system_clk)
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begin
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if rising_edge(system_clk) then
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if reset_n = '0' then
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slow_reset <= '1';
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counter <= RESET_CYCLE_COUNT;
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else
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if counter = 0 then
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slow_reset <= '0';
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else
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counter <= counter - 1;
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end if;
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end if;
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end if;
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end process;
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end architecture behaviour;
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