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105 lines
3.6 KiB
Makefile
105 lines
3.6 KiB
Makefile
GHDL=ghdl
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GHDLFLAGS=--std=08 --work=unisim
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CFLAGS=-O2 -Wall
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# We need a version of GHDL built with either the LLVM or gcc backend.
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# Fedora provides this, but other distros may not. Another option is to use
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# the Docker image.
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#
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# Uncomment one of these to build with Docker or podman
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#DOCKER=docker
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DOCKER=podman
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#
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# Uncomment these lines to build with Docker/podman
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PWD = $(shell pwd)
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DOCKERARGS = run --rm -v $(PWD):/src:z -w /src
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GHDL = $(DOCKER) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 ghdl
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CC = $(DOCKER) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 gcc
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all = core_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
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rotator_tb countzero_tb wishbone_bram_tb soc_reset_tb
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all: $(all)
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CORE_FILES=decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl
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CORE_FILES+=fetch2.vhdl utils.vhdl plru.vhdl cache_ram.vhdl icache.vhdl
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CORE_FILES+=decode1.vhdl helpers.vhdl insn_helpers.vhdl gpr_hazard.vhdl
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CORE_FILES+=cr_hazard.vhdl control.vhdl decode2.vhdl register_file.vhdl
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CORE_FILES+=cr_file.vhdl crhelpers.vhdl ppc_fx_insns.vhdl rotator.vhdl
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CORE_FILES+=logical.vhdl countzero.vhdl multiply.vhdl divider.vhdl
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CORE_FILES+=execute1.vhdl loadstore1.vhdl mmu.vhdl dcache.vhdl
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CORE_FILES+=writeback.vhdl core_debug.vhdl core.vhdl
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SOC_FILES=wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl
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SOC_FILES+=wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl
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SOC_SIM_FILES=sim_console.vhdl sim_uart.vhdl sim_bram_helpers.vhdl
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SOC_SIM_FILES+=sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl
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SOC_SIM_FILES+=sim-unisim/BUFG.vhdl sim-unisim/unisim_vcomponents.vhdl
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SOC_SIM_FILES+=dmi_dtm_xilinx.vhdl
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SOC_SIM_C_FILES=sim_vhpi_c.o sim_bram_helpers_c.o sim_console_c.o
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SOC_SIM_C_FILES+=sim_jtag_socket_c.o
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SOC_SIM_OBJ_FILES=$(SOC_SIM_C_FILES:.c=.o)
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comma := ,
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SOC_SIM_LINK=$(patsubst %,-Wl$(comma)%,$(SOC_SIM_OBJ_FILES))
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CORE_TBS=multiply_tb divider_tb rotator_tb countzero_tb
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SOC_TBS=core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb
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$(processes): %_processes: tests/%.o main.c
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$(SOC_TBS): %: $(CORE_FILES) $(SOC_FILES) $(SOC_SIM_FILES) $(SOC_SIM_OBJ_FILES) %.vhdl
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$(GHDL) -c $(GHDLFLAGS) $(SOC_SIM_LINK) $(CORE_FILES) $(SOC_FILES) $(SOC_SIM_FILES) $@.vhdl -e $@
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$(CORE_TBS): %: $(CORE_FILES) glibc_random.vhdl glibc_random_helpers.vhdl %.vhdl
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$(GHDL) -c $(GHDLFLAGS) $(CORE_FILES) glibc_random.vhdl glibc_random_helpers.vhdl $@.vhdl -e $@
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soc_reset_tb: fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl
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$(GHDL) -c $(GHDLFLAGS) fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl -e $@
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tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))
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tests_console = $(sort $(patsubst tests/%.console_out,%,$(wildcard tests/*.console_out)))
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check: $(tests) $(tests_console) test_micropython test_micropython_long
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check_light: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test_micropython test_micropython_long $(tests_console)
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$(tests): core_tb
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@./scripts/run_test.sh $@
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$(tests_console): core_tb
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@./scripts/run_test_console.sh $@
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test_micropython: core_tb
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@./scripts/test_micropython.py
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test_micropython_long: core_tb
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@./scripts/test_micropython_long.py
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TAGS:
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find . -name '*.vhdl' | xargs ./scripts/vhdltags
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.PHONY: TAGS
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_clean:
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rm -f *.o work-*cf unisim-*cf $(all)
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rm -f fpga/*.o fpga/work-*cf
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rm -f sim-unisim/*.o sim-unisim/unisim-*cf
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rm -f TAGS
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rm -f scripts/mw_debug/*.o
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rm -f scripts/mw_debug/mw_debug
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clean: _clean
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make -f scripts/mw_debug/Makefile clean
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make -f hello_world/Makefile clean
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distclean: _clean
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rm -f *~ fpga/*~ lib/*~ console/*~ include/*~
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rm -rf litedram/build
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rm -f litedram/extras/*~
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rm -f litedram/gen-src/*~
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rm -f litedram/gen-src/sdram_init/*~
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make -f scripts/mw_debug/Makefile distclean
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make -f hello_world/Makefile distclean
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