A tiny Open POWER ISA softcore written in VHDL 2008

openpower ppc64le processor vhdl

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Anton Blanchard 1b559aee31 Fix count-leading/trailing-zeroes The current code simulates correctly, but produces miscompares when synthesized onto an FPGA. On closer inspection GHDL synthesis complains about inferred latches and there does seem to be issues. Convert it to variables that are always initialized to zero at the start of the process. Fixes: `24a4a796ce` ("execute: Consolidate count-leading/trailing-zeroes implementations") Signed-off-by: Anton Blanchard <anton@linux.ibm.com>		5 years ago
fpga	…
hello_world	…
scripts	…
sim-unisim	…
tests	…
.gitignore	…
.travis.yml	…
LICENSE	…
Makefile	Merge pull request #83 from paulusmack/logical	5 years ago
README.md	…
cache_ram.vhdl	icache: Set associative icache	5 years ago
common.vhdl	Merge pull request #81 from antonblanchard/logical	5 years ago
core.vhdl	icache: Set associative icache	5 years ago
core_debug.vhdl	fetch/icache: Fit icache in BRAM	5 years ago
core_tb.vhdl	…
countzero.vhdl	Fix count-leading/trailing-zeroes	5 years ago
cr_file.vhdl	…
crhelpers.vhdl	…
decode1.vhdl	execute: Consolidate count-leading/trailing-zeroes implementations	5 years ago
decode2.vhdl	Consolidate logical instructions	5 years ago
decode_types.vhdl	execute: Consolidate count-leading/trailing-zeroes implementations	5 years ago
divider.vhdl	…
divider_tb.vhdl	…
dmi_dtm_dummy.vhdl	…
dmi_dtm_tb.vhdl	…
dmi_dtm_xilinx.vhdl	…
execute1.vhdl	execute: Consolidate count-leading/trailing-zeroes implementations	5 years ago
execute2.vhdl	…
fetch1.vhdl	fetch/icache: Fit icache in BRAM	5 years ago
fetch2.vhdl	fetch2: Remove blank line	5 years ago
glibc_random.vhdl	…
glibc_random_helpers.vhdl	…
helpers.vhdl	…
icache.vhdl	icache: Set associative icache	5 years ago
icache_tb.vhdl	icache: Use narrower block RAMs	5 years ago
insn_helpers.vhdl	…
loadstore1.vhdl	…
loadstore2.vhdl	…
logical.vhdl	Consolidate logical instructions	5 years ago
microwatt.core	Merge pull request #83 from paulusmack/logical	5 years ago
multiply.vhdl	…
multiply_tb.vhdl	…
plru.vhdl	icache: Set associative icache	5 years ago
plru_tb.vhdl	plru: Add a simple PLRU module	5 years ago
ppc_fx_insns.vhdl	…
register_file.vhdl	…
rotator.vhdl	…
rotator_tb.vhdl	…
sim_console.vhdl	…
sim_console_c.c	…
sim_jtag.vhdl	…
sim_jtag_socket.vhdl	…
sim_jtag_socket_c.c	…
sim_uart.vhdl	…
simple_ram_behavioural.vhdl	…
simple_ram_behavioural_helpers.vhdl	…
simple_ram_behavioural_helpers_c.c	…
simple_ram_behavioural_tb.bin	…
simple_ram_behavioural_tb.vhdl	…
soc.vhdl	…
wishbone_arbiter.vhdl	…
wishbone_debug_master.vhdl	…
wishbone_types.vhdl	…
writeback.vhdl	…

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com

git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Create a working directory and point FuseSoC at microwatt:

mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board):

fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

There are a few instructions still to be implemented
Need to add caches and bypassing (in progress)
Need to add supervisor state (in progress)