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139 lines
3.4 KiB
VHDL
139 lines
3.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity dcache_tb is
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end dcache_tb;
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architecture behave of dcache_tb is
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signal clk : std_ulogic;
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signal rst : std_ulogic;
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signal d_in : Loadstore1ToDcacheType;
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signal d_out : DcacheToLoadstore1Type;
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signal m_in : MmuToDcacheType;
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signal m_out : DcacheToMmuType;
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signal wb_bram_in : wishbone_master_out;
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signal wb_bram_out : wishbone_slave_out;
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constant clk_period : time := 10 ns;
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begin
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dcache0: entity work.dcache
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generic map(
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LINE_SIZE => 64,
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NUM_LINES => 4
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)
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port map(
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clk => clk,
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rst => rst,
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d_in => d_in,
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d_out => d_out,
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m_in => m_in,
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m_out => m_out,
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wishbone_out => wb_bram_in,
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wishbone_in => wb_bram_out
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);
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-- BRAM Memory slave
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bram0: entity work.wishbone_bram_wrapper
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generic map(
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MEMORY_SIZE => 1024,
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RAM_INIT_FILE => "icache_test.bin"
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)
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port map(
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clk => clk,
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rst => rst,
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wishbone_in => wb_bram_in,
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wishbone_out => wb_bram_out
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);
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clk_process: process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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rst_process: process
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begin
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rst <= '1';
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wait for 2*clk_period;
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rst <= '0';
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wait;
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end process;
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stim: process
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begin
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-- Clear stuff
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d_in.valid <= '0';
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d_in.load <= '0';
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d_in.nc <= '0';
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d_in.addr <= (others => '0');
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d_in.data <= (others => '0');
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m_in.valid <= '0';
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m_in.addr <= (others => '0');
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m_in.pte <= (others => '0');
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wait for 4*clk_period;
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wait until rising_edge(clk);
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-- Cacheable read of address 4
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d_in.load <= '1';
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d_in.nc <= '0';
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d_in.addr <= x"0000000000000004";
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d_in.valid <= '1';
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wait until rising_edge(clk);
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d_in.valid <= '0';
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wait until rising_edge(clk) and d_out.valid = '1';
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assert d_out.data = x"0000000100000000"
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report "data @" & to_hstring(d_in.addr) &
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"=" & to_hstring(d_out.data) &
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" expected 0000000100000000"
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severity failure;
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-- wait for clk_period;
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-- Cacheable read of address 30
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d_in.load <= '1';
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d_in.nc <= '0';
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d_in.addr <= x"0000000000000030";
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d_in.valid <= '1';
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wait until rising_edge(clk);
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d_in.valid <= '0';
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wait until rising_edge(clk) and d_out.valid = '1';
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assert d_out.data = x"0000000D0000000C"
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report "data @" & to_hstring(d_in.addr) &
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"=" & to_hstring(d_out.data) &
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" expected 0000000D0000000C"
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severity failure;
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-- Non-cacheable read of address 100
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d_in.load <= '1';
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d_in.nc <= '1';
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d_in.addr <= x"0000000000000100";
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d_in.valid <= '1';
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wait until rising_edge(clk);
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d_in.valid <= '0';
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wait until rising_edge(clk) and d_out.valid = '1';
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assert d_out.data = x"0000004100000040"
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report "data @" & to_hstring(d_in.addr) &
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"=" & to_hstring(d_out.data) &
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" expected 0000004100000040"
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severity failure;
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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std.env.finish;
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end process;
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end;
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