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Anton Blanchard 6cbf456388 SOC memory wishbone should clear ACK regardless of STB ... The memory wishbone doesn't clear ACK and move the state machine on until STB is de-asserted. This seems like it isn't compliant with the spec and results in a maximum throughput of 1 transfer every 3 cycles. Fixing this improves the situation to one transfer every 2 cycles. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>		6 years ago
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LICENSE	Initial import of microwatt	6 years ago
arty_a7-35.xdc	Merge pull request #20 from antonblanchard/reset-rework2	6 years ago
clk_gen_bypass.vhd	Fix clk_gen_bypass	6 years ago
clk_gen_mcmm.vhd	Remove names from end record statements	6 years ago
clk_gen_plle2.vhd	Remove names from end record statements	6 years ago
cmod_a7-35.xdc	Cmod A7-35 support	6 years ago
firmware.hex	Add a few more FPGA related files	6 years ago
hello_world.hex	Rebuild hello world assuming a 50MHz clock	6 years ago
mw_soc_memory.vhdl	SOC memory wishbone should clear ACK regardless of STB	6 years ago
nexys-video.xdc	Rename a few reset signals	6 years ago
nexys_a7.xdc	Merge pull request #20 from antonblanchard/reset-rework2	6 years ago
nodivide.patch	Add a few more FPGA related files	6 years ago
pp_fifo.vhd	Initial import of microwatt	6 years ago
pp_soc_uart.vhd	Initial import of microwatt	6 years ago
pp_utilities.vhd	Initial import of microwatt	6 years ago
soc_reset.vhdl	Rework SOC reset	6 years ago
soc_reset_tb.vhdl	Rework SOC reset	6 years ago
toplevel.vhdl	Share soc.vhdl between FPGA and sim	6 years ago