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Paul Mackerras
11d299e161
This adds a 256-entry, 4-way set associative TLB which stores mappings from virtual addresses composed of a PID and EA to 4kB real page addresses. Because each entry is tagged with a PID value, there is no need to flush it when the PIDR register is changed, unlike the L1 TLBs in the icache and dcache. This should improve performance when context switches between processes are frequent. EAs are assumed to lie in a 4PB range (52-bit) as both of the architected page table formats used by Linux map a 4PB space per PID (ignoring quadrant bits). A 512 x 64-bit block RAM is used to store both tags and data (PTE values) for the TLB. The RAM is divided into 64 groups of 8 words (each word being 64 bits), giving 128 bits per entry. In order to speed up flush-by-PID operations, the valid bits, PID tags and two address tag bits are stored in a single 64-bit word (word 0 of the block). Flush-by-PID operations read word 0 of each block and write back zeroes to the entries which match the PID being flushed. Flush all operations just writes zeroes to word 0 of every block. A pseudo-LRU array implemented in a separate 64 x 3-bit RAM is used to determine a victim entry to be evicted when a new entry is to be written and all four entries in the set are valid. The sets are indexed using a 6-bit hash of some of the EA and PID bits. Now that tlbie is actually using the PID argument in RS, we need to make sure that the code in tests/mmu/mmu.c sets it correctly. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
6 days ago | |
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| .. | ||
| Makefile | 6 years ago | |
| head.S | 3 months ago | |
| mmu.c | 6 days ago | |
| powerpc.lds | 6 years ago | |