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549 lines
19 KiB
VHDL
549 lines
19 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library unisim;
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use unisim.vcomponents.all;
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library work;
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use work.wishbone_types.all;
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entity toplevel is
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generic (
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MEMORY_SIZE : integer := 16384;
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RAM_INIT_FILE : string := "firmware.hex";
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RESET_LOW : boolean := true;
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CLK_FREQUENCY : positive := 100000000;
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HAS_FPU : boolean := true;
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USE_LITEDRAM : boolean := false;
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NO_BRAM : boolean := false;
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DISABLE_FLATTEN_CORE : boolean := false;
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SCLK_STARTUPE2 : boolean := false;
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SPI_FLASH_OFFSET : integer := 4194304;
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SPI_FLASH_DEF_CKDV : natural := 1;
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SPI_FLASH_DEF_QUAD : boolean := true;
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LOG_LENGTH : natural := 512;
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USE_LITEETH : boolean := false;
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UART_IS_16550 : boolean := false;
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HAS_UART1 : boolean := true
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);
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port(
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ext_clk : in std_ulogic;
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ext_rst_n : in std_ulogic;
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-- UART0 signals:
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uart_main_tx : out std_ulogic;
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uart_main_rx : in std_ulogic;
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-- UART1 signals:
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uart_pmod_tx : out std_ulogic;
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uart_pmod_rx : in std_ulogic;
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uart_pmod_cts_n : in std_ulogic;
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uart_pmod_rts_n : out std_ulogic;
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-- LEDs
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led0_b : out std_ulogic;
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led0_g : out std_ulogic;
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led0_r : out std_ulogic;
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led4 : out std_ulogic;
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led5 : out std_ulogic;
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led6 : out std_ulogic;
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led7 : out std_ulogic;
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-- SPI
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spi_flash_cs_n : out std_ulogic;
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spi_flash_clk : out std_ulogic;
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spi_flash_mosi : inout std_ulogic;
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spi_flash_miso : inout std_ulogic;
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spi_flash_wp_n : inout std_ulogic;
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spi_flash_hold_n : inout std_ulogic;
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-- Ethernet
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eth_ref_clk : out std_ulogic;
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eth_clocks_tx : in std_ulogic;
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eth_clocks_rx : in std_ulogic;
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eth_rst_n : out std_ulogic;
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eth_mdio : inout std_ulogic;
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eth_mdc : out std_ulogic;
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eth_rx_dv : in std_ulogic;
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eth_rx_er : in std_ulogic;
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eth_rx_data : in std_ulogic_vector(3 downto 0);
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eth_tx_en : out std_ulogic;
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eth_tx_data : out std_ulogic_vector(3 downto 0);
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eth_col : in std_ulogic;
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eth_crs : in std_ulogic;
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-- DRAM wires
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ddram_a : out std_ulogic_vector(13 downto 0);
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ddram_ba : out std_ulogic_vector(2 downto 0);
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ddram_ras_n : out std_ulogic;
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ddram_cas_n : out std_ulogic;
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ddram_we_n : out std_ulogic;
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ddram_cs_n : out std_ulogic;
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ddram_dm : out std_ulogic_vector(1 downto 0);
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ddram_dq : inout std_ulogic_vector(15 downto 0);
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ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
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ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
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ddram_clk_p : out std_ulogic;
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ddram_clk_n : out std_ulogic;
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ddram_cke : out std_ulogic;
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ddram_odt : out std_ulogic;
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ddram_reset_n : out std_ulogic
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);
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end entity toplevel;
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architecture behaviour of toplevel is
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-- Reset signals:
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signal soc_rst : std_ulogic;
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signal pll_rst : std_ulogic;
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-- Internal clock signals:
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signal system_clk : std_ulogic;
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signal system_clk_locked : std_ulogic;
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signal eth_clk_locked : std_ulogic;
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-- External IOs from the SoC
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signal wb_ext_io_in : wb_io_master_out;
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signal wb_ext_io_out : wb_io_slave_out;
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signal wb_ext_is_dram_csr : std_ulogic;
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signal wb_ext_is_dram_init : std_ulogic;
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signal wb_ext_is_eth : std_ulogic;
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-- DRAM main data wishbone connection
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signal wb_dram_in : wishbone_master_out;
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signal wb_dram_out : wishbone_slave_out;
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-- DRAM control wishbone connection
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signal wb_dram_ctrl_out : wb_io_slave_out := wb_io_slave_out_init;
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-- LiteEth connection
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signal ext_irq_eth : std_ulogic;
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signal wb_eth_out : wb_io_slave_out := wb_io_slave_out_init;
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-- Control/status
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signal core_alt_reset : std_ulogic;
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-- Status LED
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signal led0_b_pwm : std_ulogic;
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signal led0_r_pwm : std_ulogic;
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signal led0_g_pwm : std_ulogic;
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-- Dumb PWM for the LEDs, those RGB LEDs are too bright otherwise
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signal pwm_counter : std_ulogic_vector(8 downto 0);
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-- SPI flash
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signal spi_sck : std_ulogic;
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signal spi_cs_n : std_ulogic;
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signal spi_sdat_o : std_ulogic_vector(3 downto 0);
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signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
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signal spi_sdat_i : std_ulogic_vector(3 downto 0);
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-- Fixup various memory sizes based on generics
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function get_bram_size return natural is
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begin
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if USE_LITEDRAM and NO_BRAM then
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return 0;
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else
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return MEMORY_SIZE;
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end if;
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end function;
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function get_payload_size return natural is
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begin
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if USE_LITEDRAM and NO_BRAM then
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return MEMORY_SIZE;
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else
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return 0;
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end if;
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end function;
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constant BRAM_SIZE : natural := get_bram_size;
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constant PAYLOAD_SIZE : natural := get_payload_size;
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begin
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-- Main SoC
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soc0: entity work.soc
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generic map(
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MEMORY_SIZE => BRAM_SIZE,
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RAM_INIT_FILE => RAM_INIT_FILE,
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SIM => false,
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CLK_FREQ => CLK_FREQUENCY,
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HAS_FPU => HAS_FPU,
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HAS_DRAM => USE_LITEDRAM,
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DRAM_SIZE => 256 * 1024 * 1024,
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DRAM_INIT_SIZE => PAYLOAD_SIZE,
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DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
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HAS_SPI_FLASH => true,
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SPI_FLASH_DLINES => 4,
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SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
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SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
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SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
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LOG_LENGTH => LOG_LENGTH,
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HAS_LITEETH => USE_LITEETH,
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UART0_IS_16550 => UART_IS_16550,
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HAS_UART1 => HAS_UART1
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)
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port map (
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-- System signals
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system_clk => system_clk,
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rst => soc_rst,
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-- UART signals
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uart0_txd => uart_main_tx,
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uart0_rxd => uart_main_rx,
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-- UART1 signals
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uart1_txd => uart_pmod_tx,
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uart1_rxd => uart_pmod_rx,
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-- SPI signals
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spi_flash_sck => spi_sck,
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spi_flash_cs_n => spi_cs_n,
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spi_flash_sdat_o => spi_sdat_o,
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spi_flash_sdat_oe => spi_sdat_oe,
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spi_flash_sdat_i => spi_sdat_i,
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-- External interrupts
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ext_irq_eth => ext_irq_eth,
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-- DRAM wishbone
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wb_dram_in => wb_dram_in,
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wb_dram_out => wb_dram_out,
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wb_ext_io_in => wb_ext_io_in,
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wb_ext_io_out => wb_ext_io_out,
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wb_ext_is_dram_csr => wb_ext_is_dram_csr,
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wb_ext_is_dram_init => wb_ext_is_dram_init,
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wb_ext_is_eth => wb_ext_is_eth,
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alt_reset => core_alt_reset
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);
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uart_pmod_rts_n <= '0';
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-- SPI Flash
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--
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-- Note: Unlike many other boards, the SPI flash on the Arty has
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-- an actual pin to generate the clock and doesn't require to use
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-- the STARTUPE2 primitive.
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--
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spi_flash_cs_n <= spi_cs_n;
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spi_flash_mosi <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
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spi_flash_miso <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
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spi_flash_wp_n <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
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spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z';
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spi_sdat_i(0) <= spi_flash_mosi;
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spi_sdat_i(1) <= spi_flash_miso;
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spi_sdat_i(2) <= spi_flash_wp_n;
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spi_sdat_i(3) <= spi_flash_hold_n;
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spi_sclk_startupe2: if SCLK_STARTUPE2 generate
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spi_flash_clk <= 'Z';
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STARTUPE2_INST: STARTUPE2
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port map (
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CLK => '0',
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GSR => '0',
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GTS => '0',
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KEYCLEARB => '0',
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PACK => '0',
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USRCCLKO => spi_sck,
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USRCCLKTS => '0',
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USRDONEO => '1',
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USRDONETS => '0'
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);
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end generate;
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spi_direct_sclk: if not SCLK_STARTUPE2 generate
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spi_flash_clk <= spi_sck;
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end generate;
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nodram: if not USE_LITEDRAM generate
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signal ddram_clk_dummy : std_ulogic;
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begin
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reset_controller: entity work.soc_reset
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generic map(
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RESET_LOW => RESET_LOW
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)
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port map(
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ext_clk => ext_clk,
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pll_clk => system_clk,
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pll_locked_in => system_clk_locked and eth_clk_locked,
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ext_rst_in => ext_rst_n,
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pll_rst_out => pll_rst,
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rst_out => soc_rst
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);
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clkgen: entity work.clock_generator
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generic map(
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CLK_INPUT_HZ => 100000000,
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CLK_OUTPUT_HZ => CLK_FREQUENCY
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)
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port map(
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ext_clk => ext_clk,
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pll_rst_in => pll_rst,
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pll_clk_out => system_clk,
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pll_locked_out => system_clk_locked
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);
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led0_b_pwm <= '1';
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led0_r_pwm <= '1';
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led0_g_pwm <= '0';
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core_alt_reset <= '0';
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-- Vivado barfs on those differential signals if left
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-- unconnected. So instanciate a diff. buffer and feed
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-- it a constant '0'.
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dummy_dram_clk: OBUFDS
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port map (
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O => ddram_clk_p,
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OB => ddram_clk_n,
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I => ddram_clk_dummy
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);
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ddram_clk_dummy <= '0';
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end generate;
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has_dram: if USE_LITEDRAM generate
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signal dram_init_done : std_ulogic;
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signal dram_init_error : std_ulogic;
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signal dram_sys_rst : std_ulogic;
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signal rst_gen_rst : std_ulogic;
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begin
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-- Eventually dig out the frequency from the generator
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-- but for now, assert it's 100Mhz
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assert CLK_FREQUENCY = 100000000;
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reset_controller: entity work.soc_reset
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generic map(
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RESET_LOW => RESET_LOW,
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PLL_RESET_BITS => 18,
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SOC_RESET_BITS => 1
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)
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port map(
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ext_clk => ext_clk,
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pll_clk => system_clk,
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pll_locked_in => eth_clk_locked,
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ext_rst_in => ext_rst_n,
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pll_rst_out => pll_rst,
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rst_out => rst_gen_rst
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);
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-- Generate SoC reset
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soc_rst_gen: process(system_clk)
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begin
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if ext_rst_n = '0' then
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soc_rst <= '1';
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elsif rising_edge(system_clk) then
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soc_rst <= dram_sys_rst or not eth_clk_locked or not system_clk_locked;
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end if;
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end process;
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dram: entity work.litedram_wrapper
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generic map(
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DRAM_ABITS => 24,
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DRAM_ALINES => 14,
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DRAM_DLINES => 16,
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DRAM_PORT_WIDTH => 128,
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PAYLOAD_FILE => RAM_INIT_FILE,
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PAYLOAD_SIZE => PAYLOAD_SIZE
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)
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port map(
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clk_in => ext_clk,
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rst => pll_rst,
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system_clk => system_clk,
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system_reset => dram_sys_rst,
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core_alt_reset => core_alt_reset,
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pll_locked => system_clk_locked,
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wb_in => wb_dram_in,
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wb_out => wb_dram_out,
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wb_ctrl_in => wb_ext_io_in,
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wb_ctrl_out => wb_dram_ctrl_out,
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wb_ctrl_is_csr => wb_ext_is_dram_csr,
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wb_ctrl_is_init => wb_ext_is_dram_init,
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init_done => dram_init_done,
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init_error => dram_init_error,
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ddram_a => ddram_a,
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ddram_ba => ddram_ba,
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ddram_ras_n => ddram_ras_n,
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ddram_cas_n => ddram_cas_n,
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ddram_we_n => ddram_we_n,
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ddram_cs_n => ddram_cs_n,
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ddram_dm => ddram_dm,
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ddram_dq => ddram_dq,
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ddram_dqs_p => ddram_dqs_p,
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ddram_dqs_n => ddram_dqs_n,
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ddram_clk_p => ddram_clk_p,
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ddram_clk_n => ddram_clk_n,
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ddram_cke => ddram_cke,
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ddram_odt => ddram_odt,
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ddram_reset_n => ddram_reset_n
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);
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led0_b_pwm <= not dram_init_done;
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led0_r_pwm <= dram_init_error;
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led0_g_pwm <= dram_init_done and not dram_init_error;
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end generate;
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has_liteeth : if USE_LITEETH generate
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component liteeth_core port (
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sys_clock : in std_ulogic;
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sys_reset : in std_ulogic;
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mii_eth_clocks_tx : in std_ulogic;
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mii_eth_clocks_rx : in std_ulogic;
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mii_eth_rst_n : out std_ulogic;
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mii_eth_mdio : in std_ulogic;
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mii_eth_mdc : out std_ulogic;
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mii_eth_rx_dv : in std_ulogic;
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mii_eth_rx_er : in std_ulogic;
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mii_eth_rx_data : in std_ulogic_vector(3 downto 0);
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mii_eth_tx_en : out std_ulogic;
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mii_eth_tx_data : out std_ulogic_vector(3 downto 0);
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mii_eth_col : in std_ulogic;
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mii_eth_crs : in std_ulogic;
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wishbone_adr : in std_ulogic_vector(29 downto 0);
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wishbone_dat_w : in std_ulogic_vector(31 downto 0);
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wishbone_dat_r : out std_ulogic_vector(31 downto 0);
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wishbone_sel : in std_ulogic_vector(3 downto 0);
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wishbone_cyc : in std_ulogic;
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wishbone_stb : in std_ulogic;
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wishbone_ack : out std_ulogic;
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wishbone_we : in std_ulogic;
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wishbone_cti : in std_ulogic_vector(2 downto 0);
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wishbone_bte : in std_ulogic_vector(1 downto 0);
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wishbone_err : out std_ulogic;
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interrupt : out std_ulogic
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);
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end component;
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signal wb_eth_cyc : std_ulogic;
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signal wb_eth_adr : std_ulogic_vector(29 downto 0);
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-- Change this to use a PLL instead of a BUFR to generate the 25Mhz
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-- reference clock to the PHY.
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constant USE_PLL : boolean := false;
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begin
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eth_use_pll: if USE_PLL generate
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signal eth_clk_25 : std_ulogic;
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signal eth_clkfb : std_ulogic;
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begin
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pll_eth : PLLE2_BASE
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generic map (
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BANDWIDTH => "OPTIMIZED",
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CLKFBOUT_MULT => 16,
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CLKIN1_PERIOD => 10.0,
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CLKOUT0_DIVIDE => 64,
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DIVCLK_DIVIDE => 1,
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STARTUP_WAIT => "FALSE")
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port map (
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CLKOUT0 => eth_clk_25,
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CLKOUT1 => open,
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CLKOUT2 => open,
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CLKOUT3 => open,
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CLKOUT4 => open,
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CLKOUT5 => open,
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CLKFBOUT => eth_clkfb,
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LOCKED => eth_clk_locked,
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CLKIN1 => ext_clk,
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PWRDWN => '0',
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RST => pll_rst,
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CLKFBIN => eth_clkfb);
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eth_clk_buf: BUFG
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port map (
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I => eth_clk_25,
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O => eth_ref_clk
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);
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end generate;
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eth_use_bufr: if not USE_PLL generate
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eth_clk_div: BUFR
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generic map (
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BUFR_DIVIDE => "4"
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)
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port map (
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I => system_clk,
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O => eth_ref_clk,
|
|
CE => '1',
|
|
CLR => '0'
|
|
);
|
|
eth_clk_locked <= '1';
|
|
end generate;
|
|
|
|
liteeth : liteeth_core
|
|
port map(
|
|
sys_clock => system_clk,
|
|
sys_reset => soc_rst,
|
|
mii_eth_clocks_tx => eth_clocks_tx,
|
|
mii_eth_clocks_rx => eth_clocks_rx,
|
|
mii_eth_rst_n => eth_rst_n,
|
|
mii_eth_mdio => eth_mdio,
|
|
mii_eth_mdc => eth_mdc,
|
|
mii_eth_rx_dv => eth_rx_dv,
|
|
mii_eth_rx_er => eth_rx_er,
|
|
mii_eth_rx_data => eth_rx_data,
|
|
mii_eth_tx_en => eth_tx_en,
|
|
mii_eth_tx_data => eth_tx_data,
|
|
mii_eth_col => eth_col,
|
|
mii_eth_crs => eth_crs,
|
|
wishbone_adr => wb_eth_adr,
|
|
wishbone_dat_w => wb_ext_io_in.dat,
|
|
wishbone_dat_r => wb_eth_out.dat,
|
|
wishbone_sel => wb_ext_io_in.sel,
|
|
wishbone_cyc => wb_eth_cyc,
|
|
wishbone_stb => wb_ext_io_in.stb,
|
|
wishbone_ack => wb_eth_out.ack,
|
|
wishbone_we => wb_ext_io_in.we,
|
|
wishbone_cti => "000",
|
|
wishbone_bte => "00",
|
|
wishbone_err => open,
|
|
interrupt => ext_irq_eth
|
|
);
|
|
|
|
-- Gate cyc with "chip select" from soc
|
|
wb_eth_cyc <= wb_ext_io_in.cyc and wb_ext_is_eth;
|
|
|
|
-- Remove top address bits as liteeth decoder doesn't know about them
|
|
wb_eth_adr <= x"000" & "000" & wb_ext_io_in.adr(16 downto 2);
|
|
|
|
-- LiteETH isn't pipelined
|
|
wb_eth_out.stall <= not wb_eth_out.ack;
|
|
|
|
end generate;
|
|
|
|
no_liteeth : if not USE_LITEETH generate
|
|
eth_clk_locked <= '1';
|
|
ext_irq_eth <= '0';
|
|
end generate;
|
|
|
|
-- Mux WB response on the IO bus
|
|
wb_ext_io_out <= wb_eth_out when wb_ext_is_eth = '1' else wb_dram_ctrl_out;
|
|
|
|
leds_pwm : process(system_clk)
|
|
begin
|
|
if rising_edge(system_clk) then
|
|
pwm_counter <= std_ulogic_vector(signed(pwm_counter) + 1);
|
|
if pwm_counter(8 downto 4) = "00000" then
|
|
led0_b <= led0_b_pwm;
|
|
led0_r <= led0_r_pwm;
|
|
led0_g <= led0_g_pwm;
|
|
else
|
|
led0_b <= '0';
|
|
led0_r <= '0';
|
|
led0_g <= '0';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
led4 <= system_clk_locked;
|
|
led5 <= eth_clk_locked;
|
|
led6 <= not soc_rst;
|
|
led7 <= not spi_flash_cs_n;
|
|
|
|
end architecture behaviour;
|