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91 lines
2.0 KiB
VHDL
91 lines
2.0 KiB
VHDL
-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 <kristian.skordal@wafflemail.net>
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library ieee;
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use ieee.std_logic_1164.all;
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package pp_utilities is
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--! Converts a boolean to an std_logic.
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function to_std_logic(input : in boolean) return std_logic;
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-- Checks if a number is 2^n:
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function is_pow2(input : in natural) return boolean;
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--! Calculates log2 with integers.
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function log2(input : in natural) return natural;
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-- Gets the value of the sel signals to the wishbone interconnect for the specified
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-- operand size and address.
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function wb_get_data_sel(size : in std_logic_vector(1 downto 0); address : in std_logic_vector)
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return std_logic_vector;
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end package pp_utilities;
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package body pp_utilities is
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function to_std_logic(input : in boolean) return std_logic is
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begin
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if input then
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return '1';
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else
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return '0';
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end if;
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end function to_std_logic;
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function is_pow2(input : in natural) return boolean is
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variable c : natural := 1;
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begin
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for i in 0 to 31 loop
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if input = c then
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return true;
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end if;
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c := c * 2;
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end loop;
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return false;
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end function is_pow2;
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function log2(input : in natural) return natural is
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variable retval : natural := 0;
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variable temp : natural := input;
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begin
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while temp > 1 loop
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retval := retval + 1;
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temp := temp / 2;
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end loop;
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return retval;
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end function log2;
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function wb_get_data_sel(size : in std_logic_vector(1 downto 0); address : in std_logic_vector)
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return std_logic_vector is
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begin
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case size is
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when b"01" =>
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case address(1 downto 0) is
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when b"00" =>
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return b"0001";
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when b"01" =>
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return b"0010";
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when b"10" =>
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return b"0100";
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when b"11" =>
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return b"1000";
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when others =>
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return b"0001";
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end case;
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when b"10" =>
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if address(1) = '0' then
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return b"0011";
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else
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return b"1100";
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end if;
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when others =>
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return b"1111";
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end case;
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end function wb_get_data_sel;
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end package body pp_utilities;
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