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Benjamin Herrenschmidt 05bbbf0772 litedram: Pipeline store acks in L2 ... There is a long timing path to generate the ack signal from the L2 cache as it's fully combinational for stores, including signals coming from litedram. Instead, pipeline the store acks. This will introduce a cycle latency but should improve timing. Also the core will eventually be smart enough not to wait for store acks to complete them anyway. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		4 years ago
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fusesoc-add-files.py	litedram: Remove old "VexRiscV" based initializations	4 years ago
litedram-wrapper-l2.vhdl	litedram: Pipeline store acks in L2	4 years ago
sim_dram_verilate.mk	litedram: Add simulation support	4 years ago
sim_litedram.vhdl	litedram: Add simulation support	4 years ago
sim_litedram_c.cpp	litedram: Add simulation support	4 years ago
wave.gtkw	litedram: Add an L2 cache with store queue	4 years ago
wave.opt	litedram: Add an L2 cache with store queue	4 years ago
wave_tb.gtkw	litedram: Test bench	4 years ago