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This implements the LPCR (Logical Partition Control Register) with 5 read/write bits. The other 59 bits are read-only; two (HR and UPRT) read as 1 and the rest as 0. The bits that are implemented are: * HAIL - enables taking interrupts with relocation on * LD - enables large decrementer mode * HEIC - disables external interrupts when set * LPES - controls how external interrupts are delivered * HVICE - does nothing at present since there is no source of Hypervisor Virtualization Interrupts. This also fixes a bug where MSR[RI] was getting cleared by the delivery of hypervisor interrupts. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
3 weeks ago | |
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fmt_log | 4 months ago | |
mw_debug | 3 weeks ago | |
bin2hex.py | 5 years ago | |
dependencies.py | 5 years ago | |
gen_icache_tb.py | 6 years ago | |
make_version.sh | 3 years ago | |
make_version_fusesoc.py | 3 years ago | |
run_test.sh | 1 year ago | |
run_test_console.sh | 3 years ago | |
test_micropython.py | 5 years ago | |
test_micropython_long.py | 5 years ago | |
test_micropython_verilator.py | 4 years ago | |
test_micropython_verilator_long.py | 4 years ago | |
vhdltags | 5 years ago |