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This implements the hypervisor doorbell exception and interrupt and the msgsnd, msgclr and msgsync instructions (msgsync is a no-op). The msgsnd instruction can generate a hypervisor doorbell interrupt on any CPU in the system. To achieve this, each core sends its hypervisor doorbell messages to the soc level, which ORs together the bits for each CPU and sends it to that CPU. The privileged doorbell exception/interrupt and the msgsndp/msgclrp instructions are not required since we don't implement SMT. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
1 week ago | |
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fmt_log | 1 week ago | |
mw_debug | 5 months ago | |
bin2hex.py | 5 years ago | |
dependencies.py | 5 years ago | |
gen_icache_tb.py | 6 years ago | |
make_version.sh | 3 years ago | |
make_version_fusesoc.py | 3 years ago | |
run_test.sh | 2 years ago | |
run_test_console.sh | 3 years ago | |
test_micropython.py | 6 years ago | |
test_micropython_long.py | 6 years ago | |
test_micropython_verilator.py | 4 years ago | |
test_micropython_verilator_long.py | 4 years ago | |
vhdltags | 5 years ago |