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microwatt/liteeth/generated/arty/liteeth_core.v

3468 lines
198 KiB
Verilog

//--------------------------------------------------------------------------------
// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:37:00
//--------------------------------------------------------------------------------
module liteeth_core(
input wire sys_clock,
input wire sys_reset,
input wire mii_eth_clocks_tx,
input wire mii_eth_clocks_rx,
output wire mii_eth_rst_n,
inout wire mii_eth_mdio,
output wire mii_eth_mdc,
input wire mii_eth_rx_dv,
input wire mii_eth_rx_er,
input wire [3:0] mii_eth_rx_data,
output reg mii_eth_tx_en,
output reg [3:0] mii_eth_tx_data,
input wire mii_eth_col,
input wire mii_eth_crs,
input wire [29:0] wishbone_adr,
input wire [31:0] wishbone_dat_w,
output wire [31:0] wishbone_dat_r,
input wire [3:0] wishbone_sel,
input wire wishbone_cyc,
input wire wishbone_stb,
output wire wishbone_ack,
input wire wishbone_we,
input wire [2:0] wishbone_cti,
input wire [1:0] wishbone_bte,
output wire wishbone_err,
output wire interrupt
);
reg main_maccore_maccore_soc_rst = 1'd0;
wire main_maccore_maccore_cpu_rst;
reg [1:0] main_maccore_maccore_reset_storage = 2'd0;
reg main_maccore_maccore_reset_re = 1'd0;
reg [31:0] main_maccore_maccore_scratch_storage = 32'd305419896;
reg main_maccore_maccore_scratch_re = 1'd0;
wire [31:0] main_maccore_maccore_bus_errors_status;
wire main_maccore_maccore_bus_errors_we;
reg main_maccore_maccore_bus_errors_re = 1'd0;
wire main_maccore_maccore_bus_error;
reg [31:0] main_maccore_maccore_bus_errors = 32'd0;
(* dont_touch = "true" *) wire sys_clk;
wire sys_rst;
wire por_clk;
reg main_maccore_int_rst = 1'd1;
reg main_maccore_ethphy_reset_storage = 1'd0;
reg main_maccore_ethphy_reset_re = 1'd0;
(* dont_touch = "true" *) wire eth_rx_clk;
wire eth_rx_rst;
(* dont_touch = "true" *) wire eth_tx_clk;
wire eth_tx_rst;
wire main_maccore_ethphy_reset0;
wire main_maccore_ethphy_reset1;
reg [8:0] main_maccore_ethphy_counter = 9'd0;
wire main_maccore_ethphy_counter_done;
wire main_maccore_ethphy_counter_ce;
wire main_maccore_ethphy_liteethphymiitx_sink_sink_valid;
wire main_maccore_ethphy_liteethphymiitx_sink_sink_ready;
wire main_maccore_ethphy_liteethphymiitx_sink_sink_first;
wire main_maccore_ethphy_liteethphymiitx_sink_sink_last;
wire [7:0] main_maccore_ethphy_liteethphymiitx_sink_sink_payload_data;
wire main_maccore_ethphy_liteethphymiitx_sink_sink_payload_last_be;
wire main_maccore_ethphy_liteethphymiitx_sink_sink_payload_error;
wire main_maccore_ethphy_liteethphymiitx_converter_sink_valid;
wire main_maccore_ethphy_liteethphymiitx_converter_sink_ready;
reg main_maccore_ethphy_liteethphymiitx_converter_sink_first = 1'd0;
reg main_maccore_ethphy_liteethphymiitx_converter_sink_last = 1'd0;
wire [7:0] main_maccore_ethphy_liteethphymiitx_converter_sink_payload_data;
wire main_maccore_ethphy_liteethphymiitx_converter_source_valid;
wire main_maccore_ethphy_liteethphymiitx_converter_source_ready;
wire main_maccore_ethphy_liteethphymiitx_converter_source_first;
wire main_maccore_ethphy_liteethphymiitx_converter_source_last;
wire [3:0] main_maccore_ethphy_liteethphymiitx_converter_source_payload_data;
wire main_maccore_ethphy_liteethphymiitx_converter_converter_sink_valid;
wire main_maccore_ethphy_liteethphymiitx_converter_converter_sink_ready;
wire main_maccore_ethphy_liteethphymiitx_converter_converter_sink_first;
wire main_maccore_ethphy_liteethphymiitx_converter_converter_sink_last;
reg [7:0] main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data = 8'd0;
wire main_maccore_ethphy_liteethphymiitx_converter_converter_source_valid;
wire main_maccore_ethphy_liteethphymiitx_converter_converter_source_ready;
wire main_maccore_ethphy_liteethphymiitx_converter_converter_source_first;
wire main_maccore_ethphy_liteethphymiitx_converter_converter_source_last;
reg [3:0] main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_data = 4'd0;
wire main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_valid_token_count;
reg main_maccore_ethphy_liteethphymiitx_converter_converter_mux = 1'd0;
wire main_maccore_ethphy_liteethphymiitx_converter_converter_first;
wire main_maccore_ethphy_liteethphymiitx_converter_converter_last;
wire main_maccore_ethphy_liteethphymiitx_converter_source_source_valid;
wire main_maccore_ethphy_liteethphymiitx_converter_source_source_ready;
wire main_maccore_ethphy_liteethphymiitx_converter_source_source_first;
wire main_maccore_ethphy_liteethphymiitx_converter_source_source_last;
wire [3:0] main_maccore_ethphy_liteethphymiitx_converter_source_source_payload_data;
wire main_maccore_ethphy_liteethphymiirx_source_source_valid;
wire main_maccore_ethphy_liteethphymiirx_source_source_ready;
wire main_maccore_ethphy_liteethphymiirx_source_source_first;
wire main_maccore_ethphy_liteethphymiirx_source_source_last;
wire [7:0] main_maccore_ethphy_liteethphymiirx_source_source_payload_data;
reg main_maccore_ethphy_liteethphymiirx_source_source_payload_last_be = 1'd0;
reg main_maccore_ethphy_liteethphymiirx_source_source_payload_error = 1'd0;
reg main_maccore_ethphy_liteethphymiirx_converter_sink_valid = 1'd0;
wire main_maccore_ethphy_liteethphymiirx_converter_sink_ready;
reg main_maccore_ethphy_liteethphymiirx_converter_sink_first = 1'd0;
wire main_maccore_ethphy_liteethphymiirx_converter_sink_last;
reg [3:0] main_maccore_ethphy_liteethphymiirx_converter_sink_payload_data = 4'd0;
wire main_maccore_ethphy_liteethphymiirx_converter_source_valid;
wire main_maccore_ethphy_liteethphymiirx_converter_source_ready;
wire main_maccore_ethphy_liteethphymiirx_converter_source_first;
wire main_maccore_ethphy_liteethphymiirx_converter_source_last;
reg [7:0] main_maccore_ethphy_liteethphymiirx_converter_source_payload_data = 8'd0;
wire main_maccore_ethphy_liteethphymiirx_converter_converter_sink_valid;
wire main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready;
wire main_maccore_ethphy_liteethphymiirx_converter_converter_sink_first;
wire main_maccore_ethphy_liteethphymiirx_converter_converter_sink_last;
wire [3:0] main_maccore_ethphy_liteethphymiirx_converter_converter_sink_payload_data;
wire main_maccore_ethphy_liteethphymiirx_converter_converter_source_valid;
wire main_maccore_ethphy_liteethphymiirx_converter_converter_source_ready;
reg main_maccore_ethphy_liteethphymiirx_converter_converter_source_first = 1'd0;
reg main_maccore_ethphy_liteethphymiirx_converter_converter_source_last = 1'd0;
reg [7:0] main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_data = 8'd0;
reg [1:0] main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_valid_token_count = 2'd0;
reg main_maccore_ethphy_liteethphymiirx_converter_converter_demux = 1'd0;
wire main_maccore_ethphy_liteethphymiirx_converter_converter_load_part;
reg main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all = 1'd0;
wire main_maccore_ethphy_liteethphymiirx_converter_source_source_valid;
wire main_maccore_ethphy_liteethphymiirx_converter_source_source_ready;
wire main_maccore_ethphy_liteethphymiirx_converter_source_source_first;
wire main_maccore_ethphy_liteethphymiirx_converter_source_source_last;
wire [7:0] main_maccore_ethphy_liteethphymiirx_converter_source_source_payload_data;
reg main_maccore_ethphy_liteethphymiirx_converter_reset = 1'd0;
wire main_maccore_ethphy_mdc;
wire main_maccore_ethphy_oe;
wire main_maccore_ethphy_w;
reg [2:0] main_maccore_ethphy__w_storage = 3'd0;
reg main_maccore_ethphy__w_re = 1'd0;
reg main_maccore_ethphy_r = 1'd0;
reg main_maccore_ethphy__r_status = 1'd0;
wire main_maccore_ethphy__r_we;
reg main_maccore_ethphy__r_re = 1'd0;
wire main_maccore_ethphy_data_w;
wire main_maccore_ethphy_data_oe;
wire main_maccore_ethphy_data_r;
wire main_tx_gap_inserter_sink_valid;
reg main_tx_gap_inserter_sink_ready = 1'd0;
wire main_tx_gap_inserter_sink_first;
wire main_tx_gap_inserter_sink_last;
wire [7:0] main_tx_gap_inserter_sink_payload_data;
wire main_tx_gap_inserter_sink_payload_last_be;
wire main_tx_gap_inserter_sink_payload_error;
reg main_tx_gap_inserter_source_valid = 1'd0;
wire main_tx_gap_inserter_source_ready;
reg main_tx_gap_inserter_source_first = 1'd0;
reg main_tx_gap_inserter_source_last = 1'd0;
reg [7:0] main_tx_gap_inserter_source_payload_data = 8'd0;
reg main_tx_gap_inserter_source_payload_last_be = 1'd0;
reg main_tx_gap_inserter_source_payload_error = 1'd0;
reg [3:0] main_tx_gap_inserter_counter = 4'd0;
reg main_preamble_crc_status = 1'd1;
wire main_preamble_crc_we;
reg main_preamble_crc_re = 1'd0;
reg [31:0] main_preamble_errors_status = 32'd0;
wire main_preamble_errors_we;
reg main_preamble_errors_re = 1'd0;
reg [31:0] main_crc_errors_status = 32'd0;
wire main_crc_errors_we;
reg main_crc_errors_re = 1'd0;
wire main_preamble_inserter_sink_valid;
reg main_preamble_inserter_sink_ready = 1'd0;
wire main_preamble_inserter_sink_first;
wire main_preamble_inserter_sink_last;
wire [7:0] main_preamble_inserter_sink_payload_data;
wire main_preamble_inserter_sink_payload_last_be;
wire main_preamble_inserter_sink_payload_error;
reg main_preamble_inserter_source_valid = 1'd0;
wire main_preamble_inserter_source_ready;
reg main_preamble_inserter_source_first = 1'd0;
reg main_preamble_inserter_source_last = 1'd0;
reg [7:0] main_preamble_inserter_source_payload_data = 8'd0;
wire main_preamble_inserter_source_payload_last_be;
reg main_preamble_inserter_source_payload_error = 1'd0;
reg [63:0] main_preamble_inserter_preamble = 64'd15372286728091293013;
reg [2:0] main_preamble_inserter_count = 3'd0;
wire main_preamble_checker_sink_valid;
reg main_preamble_checker_sink_ready = 1'd0;
wire main_preamble_checker_sink_first;
wire main_preamble_checker_sink_last;
wire [7:0] main_preamble_checker_sink_payload_data;
wire main_preamble_checker_sink_payload_last_be;
wire main_preamble_checker_sink_payload_error;
reg main_preamble_checker_source_valid = 1'd0;
wire main_preamble_checker_source_ready;
reg main_preamble_checker_source_first = 1'd0;
reg main_preamble_checker_source_last = 1'd0;
wire [7:0] main_preamble_checker_source_payload_data;
wire main_preamble_checker_source_payload_last_be;
reg main_preamble_checker_source_payload_error = 1'd0;
reg main_preamble_checker_error = 1'd0;
wire main_liteethmaccrc32inserter_sink_valid;
reg main_liteethmaccrc32inserter_sink_ready = 1'd0;
wire main_liteethmaccrc32inserter_sink_first;
wire main_liteethmaccrc32inserter_sink_last;
wire [7:0] main_liteethmaccrc32inserter_sink_payload_data;
wire main_liteethmaccrc32inserter_sink_payload_last_be;
wire main_liteethmaccrc32inserter_sink_payload_error;
reg main_liteethmaccrc32inserter_source_valid = 1'd0;
wire main_liteethmaccrc32inserter_source_ready;
reg main_liteethmaccrc32inserter_source_first = 1'd0;
reg main_liteethmaccrc32inserter_source_last = 1'd0;
reg [7:0] main_liteethmaccrc32inserter_source_payload_data = 8'd0;
reg main_liteethmaccrc32inserter_source_payload_last_be = 1'd0;
reg main_liteethmaccrc32inserter_source_payload_error = 1'd0;
reg [7:0] main_liteethmaccrc32inserter_data0 = 8'd0;
wire [31:0] main_liteethmaccrc32inserter_value;
wire main_liteethmaccrc32inserter_error;
wire [7:0] main_liteethmaccrc32inserter_data1;
wire [31:0] main_liteethmaccrc32inserter_last;
reg [31:0] main_liteethmaccrc32inserter_next = 32'd0;
reg [31:0] main_liteethmaccrc32inserter_reg = 32'd4294967295;
reg main_liteethmaccrc32inserter_ce = 1'd0;
reg main_liteethmaccrc32inserter_reset = 1'd0;
reg [1:0] main_liteethmaccrc32inserter_cnt = 2'd3;
wire main_liteethmaccrc32inserter_cnt_done;
reg main_liteethmaccrc32inserter_is_ongoing0 = 1'd0;
reg main_liteethmaccrc32inserter_is_ongoing1 = 1'd0;
wire main_crc32_inserter_sink_valid;
wire main_crc32_inserter_sink_ready;
wire main_crc32_inserter_sink_first;
wire main_crc32_inserter_sink_last;
wire [7:0] main_crc32_inserter_sink_payload_data;
wire main_crc32_inserter_sink_payload_last_be;
wire main_crc32_inserter_sink_payload_error;
reg main_crc32_inserter_source_valid = 1'd0;
wire main_crc32_inserter_source_ready;
reg main_crc32_inserter_source_first = 1'd0;
reg main_crc32_inserter_source_last = 1'd0;
reg [7:0] main_crc32_inserter_source_payload_data = 8'd0;
reg main_crc32_inserter_source_payload_last_be = 1'd0;
reg main_crc32_inserter_source_payload_error = 1'd0;
wire main_liteethmaccrc32checker_sink_sink_valid;
reg main_liteethmaccrc32checker_sink_sink_ready = 1'd0;
wire main_liteethmaccrc32checker_sink_sink_first;
wire main_liteethmaccrc32checker_sink_sink_last;
wire [7:0] main_liteethmaccrc32checker_sink_sink_payload_data;
wire main_liteethmaccrc32checker_sink_sink_payload_last_be;
wire main_liteethmaccrc32checker_sink_sink_payload_error;
wire main_liteethmaccrc32checker_source_source_valid;
wire main_liteethmaccrc32checker_source_source_ready;
reg main_liteethmaccrc32checker_source_source_first = 1'd0;
wire main_liteethmaccrc32checker_source_source_last;
wire [7:0] main_liteethmaccrc32checker_source_source_payload_data;
wire main_liteethmaccrc32checker_source_source_payload_last_be;
reg main_liteethmaccrc32checker_source_source_payload_error = 1'd0;
wire main_liteethmaccrc32checker_error;
wire [7:0] main_liteethmaccrc32checker_crc_data0;
wire [31:0] main_liteethmaccrc32checker_crc_value;
wire main_liteethmaccrc32checker_crc_error;
wire [7:0] main_liteethmaccrc32checker_crc_data1;
wire [31:0] main_liteethmaccrc32checker_crc_last;
reg [31:0] main_liteethmaccrc32checker_crc_next = 32'd0;
reg [31:0] main_liteethmaccrc32checker_crc_reg = 32'd4294967295;
reg main_liteethmaccrc32checker_crc_ce = 1'd0;
reg main_liteethmaccrc32checker_crc_reset = 1'd0;
reg main_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0;
wire main_liteethmaccrc32checker_syncfifo_sink_ready;
wire main_liteethmaccrc32checker_syncfifo_sink_first;
wire main_liteethmaccrc32checker_syncfifo_sink_last;
wire [7:0] main_liteethmaccrc32checker_syncfifo_sink_payload_data;
wire main_liteethmaccrc32checker_syncfifo_sink_payload_last_be;
wire main_liteethmaccrc32checker_syncfifo_sink_payload_error;
wire main_liteethmaccrc32checker_syncfifo_source_valid;
wire main_liteethmaccrc32checker_syncfifo_source_ready;
wire main_liteethmaccrc32checker_syncfifo_source_first;
wire main_liteethmaccrc32checker_syncfifo_source_last;
wire [7:0] main_liteethmaccrc32checker_syncfifo_source_payload_data;
wire main_liteethmaccrc32checker_syncfifo_source_payload_last_be;
wire main_liteethmaccrc32checker_syncfifo_source_payload_error;
wire main_liteethmaccrc32checker_syncfifo_syncfifo_we;
wire main_liteethmaccrc32checker_syncfifo_syncfifo_writable;
wire main_liteethmaccrc32checker_syncfifo_syncfifo_re;
wire main_liteethmaccrc32checker_syncfifo_syncfifo_readable;
wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_din;
wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_dout;
reg [2:0] main_liteethmaccrc32checker_syncfifo_level = 3'd0;
reg main_liteethmaccrc32checker_syncfifo_replace = 1'd0;
reg [2:0] main_liteethmaccrc32checker_syncfifo_produce = 3'd0;
reg [2:0] main_liteethmaccrc32checker_syncfifo_consume = 3'd0;
reg [2:0] main_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0;
wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_r;
wire main_liteethmaccrc32checker_syncfifo_wrport_we;
wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_w;
wire main_liteethmaccrc32checker_syncfifo_do_read;
wire [2:0] main_liteethmaccrc32checker_syncfifo_rdport_adr;
wire [11:0] main_liteethmaccrc32checker_syncfifo_rdport_dat_r;
wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data;
wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be;
wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error;
wire main_liteethmaccrc32checker_syncfifo_fifo_in_first;
wire main_liteethmaccrc32checker_syncfifo_fifo_in_last;
wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data;
wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be;
wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error;
wire main_liteethmaccrc32checker_syncfifo_fifo_out_first;
wire main_liteethmaccrc32checker_syncfifo_fifo_out_last;
reg main_liteethmaccrc32checker_fifo_reset = 1'd0;
wire main_liteethmaccrc32checker_fifo_in;
wire main_liteethmaccrc32checker_fifo_out;
wire main_liteethmaccrc32checker_fifo_full;
wire main_crc32_checker_sink_valid;
wire main_crc32_checker_sink_ready;
wire main_crc32_checker_sink_first;
wire main_crc32_checker_sink_last;
wire [7:0] main_crc32_checker_sink_payload_data;
wire main_crc32_checker_sink_payload_last_be;
wire main_crc32_checker_sink_payload_error;
reg main_crc32_checker_source_valid = 1'd0;
wire main_crc32_checker_source_ready;
reg main_crc32_checker_source_first = 1'd0;
reg main_crc32_checker_source_last = 1'd0;
reg [7:0] main_crc32_checker_source_payload_data = 8'd0;
reg main_crc32_checker_source_payload_last_be = 1'd0;
reg main_crc32_checker_source_payload_error = 1'd0;
wire main_ps_preamble_error_i;
wire main_ps_preamble_error_o;
reg main_ps_preamble_error_toggle_i = 1'd0;
wire main_ps_preamble_error_toggle_o;
reg main_ps_preamble_error_toggle_o_r = 1'd0;
wire main_ps_crc_error_i;
wire main_ps_crc_error_o;
reg main_ps_crc_error_toggle_i = 1'd0;
wire main_ps_crc_error_toggle_o;
reg main_ps_crc_error_toggle_o_r = 1'd0;
wire main_padding_inserter_sink_valid;
reg main_padding_inserter_sink_ready = 1'd0;
wire main_padding_inserter_sink_first;
wire main_padding_inserter_sink_last;
wire [7:0] main_padding_inserter_sink_payload_data;
wire main_padding_inserter_sink_payload_last_be;
wire main_padding_inserter_sink_payload_error;
reg main_padding_inserter_source_valid = 1'd0;
wire main_padding_inserter_source_ready;
reg main_padding_inserter_source_first = 1'd0;
reg main_padding_inserter_source_last = 1'd0;
reg [7:0] main_padding_inserter_source_payload_data = 8'd0;
reg main_padding_inserter_source_payload_last_be = 1'd0;
reg main_padding_inserter_source_payload_error = 1'd0;
reg [15:0] main_padding_inserter_counter = 16'd0;
wire main_padding_inserter_counter_done;
wire main_padding_checker_sink_valid;
wire main_padding_checker_sink_ready;
wire main_padding_checker_sink_first;
wire main_padding_checker_sink_last;
wire [7:0] main_padding_checker_sink_payload_data;
wire main_padding_checker_sink_payload_last_be;
wire main_padding_checker_sink_payload_error;
wire main_padding_checker_source_valid;
wire main_padding_checker_source_ready;
wire main_padding_checker_source_first;
wire main_padding_checker_source_last;
wire [7:0] main_padding_checker_source_payload_data;
wire main_padding_checker_source_payload_last_be;
wire main_padding_checker_source_payload_error;
wire main_tx_last_be_sink_valid;
reg main_tx_last_be_sink_ready = 1'd0;
wire main_tx_last_be_sink_first;
wire main_tx_last_be_sink_last;
wire [7:0] main_tx_last_be_sink_payload_data;
wire main_tx_last_be_sink_payload_last_be;
wire main_tx_last_be_sink_payload_error;
reg main_tx_last_be_source_valid = 1'd0;
wire main_tx_last_be_source_ready;
reg main_tx_last_be_source_first = 1'd0;
reg main_tx_last_be_source_last = 1'd0;
reg [7:0] main_tx_last_be_source_payload_data = 8'd0;
reg main_tx_last_be_source_payload_last_be = 1'd0;
reg main_tx_last_be_source_payload_error = 1'd0;
wire main_rx_last_be_sink_valid;
wire main_rx_last_be_sink_ready;
wire main_rx_last_be_sink_first;
wire main_rx_last_be_sink_last;
wire [7:0] main_rx_last_be_sink_payload_data;
wire main_rx_last_be_sink_payload_last_be;
wire main_rx_last_be_sink_payload_error;
wire main_rx_last_be_source_valid;
wire main_rx_last_be_source_ready;
wire main_rx_last_be_source_first;
wire main_rx_last_be_source_last;
wire [7:0] main_rx_last_be_source_payload_data;
reg main_rx_last_be_source_payload_last_be = 1'd0;
wire main_rx_last_be_source_payload_error;
wire main_tx_converter_sink_valid;
wire main_tx_converter_sink_ready;
wire main_tx_converter_sink_first;
wire main_tx_converter_sink_last;
wire [31:0] main_tx_converter_sink_payload_data;
wire [3:0] main_tx_converter_sink_payload_last_be;
wire [3:0] main_tx_converter_sink_payload_error;
wire main_tx_converter_source_valid;
wire main_tx_converter_source_ready;
wire main_tx_converter_source_first;
wire main_tx_converter_source_last;
wire [7:0] main_tx_converter_source_payload_data;
wire main_tx_converter_source_payload_last_be;
wire main_tx_converter_source_payload_error;
wire main_tx_converter_converter_sink_valid;
wire main_tx_converter_converter_sink_ready;
wire main_tx_converter_converter_sink_first;
wire main_tx_converter_converter_sink_last;
reg [39:0] main_tx_converter_converter_sink_payload_data = 40'd0;
wire main_tx_converter_converter_source_valid;
wire main_tx_converter_converter_source_ready;
wire main_tx_converter_converter_source_first;
wire main_tx_converter_converter_source_last;
reg [9:0] main_tx_converter_converter_source_payload_data = 10'd0;
wire main_tx_converter_converter_source_payload_valid_token_count;
reg [1:0] main_tx_converter_converter_mux = 2'd0;
wire main_tx_converter_converter_first;
wire main_tx_converter_converter_last;
wire main_tx_converter_source_source_valid;
wire main_tx_converter_source_source_ready;
wire main_tx_converter_source_source_first;
wire main_tx_converter_source_source_last;
wire [9:0] main_tx_converter_source_source_payload_data;
wire main_rx_converter_sink_valid;
wire main_rx_converter_sink_ready;
wire main_rx_converter_sink_first;
wire main_rx_converter_sink_last;
wire [7:0] main_rx_converter_sink_payload_data;
wire main_rx_converter_sink_payload_last_be;
wire main_rx_converter_sink_payload_error;
wire main_rx_converter_source_valid;
wire main_rx_converter_source_ready;
wire main_rx_converter_source_first;
wire main_rx_converter_source_last;
reg [31:0] main_rx_converter_source_payload_data = 32'd0;
reg [3:0] main_rx_converter_source_payload_last_be = 4'd0;
reg [3:0] main_rx_converter_source_payload_error = 4'd0;
wire main_rx_converter_converter_sink_valid;
wire main_rx_converter_converter_sink_ready;
wire main_rx_converter_converter_sink_first;
wire main_rx_converter_converter_sink_last;
wire [9:0] main_rx_converter_converter_sink_payload_data;
wire main_rx_converter_converter_source_valid;
wire main_rx_converter_converter_source_ready;
reg main_rx_converter_converter_source_first = 1'd0;
reg main_rx_converter_converter_source_last = 1'd0;
reg [39:0] main_rx_converter_converter_source_payload_data = 40'd0;
reg [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0;
reg [1:0] main_rx_converter_converter_demux = 2'd0;
wire main_rx_converter_converter_load_part;
reg main_rx_converter_converter_strobe_all = 1'd0;
wire main_rx_converter_source_source_valid;
wire main_rx_converter_source_source_ready;
wire main_rx_converter_source_source_first;
wire main_rx_converter_source_source_last;
wire [39:0] main_rx_converter_source_source_payload_data;
wire main_tx_cdc_sink_sink_valid;
wire main_tx_cdc_sink_sink_ready;
wire main_tx_cdc_sink_sink_first;
wire main_tx_cdc_sink_sink_last;
wire [31:0] main_tx_cdc_sink_sink_payload_data;
wire [3:0] main_tx_cdc_sink_sink_payload_last_be;
wire [3:0] main_tx_cdc_sink_sink_payload_error;
wire main_tx_cdc_source_source_valid;
wire main_tx_cdc_source_source_ready;
wire main_tx_cdc_source_source_first;
wire main_tx_cdc_source_source_last;
wire [31:0] main_tx_cdc_source_source_payload_data;
wire [3:0] main_tx_cdc_source_source_payload_last_be;
wire [3:0] main_tx_cdc_source_source_payload_error;
wire main_tx_cdc_cdc_sink_valid;
wire main_tx_cdc_cdc_sink_ready;
wire main_tx_cdc_cdc_sink_first;
wire main_tx_cdc_cdc_sink_last;
wire [31:0] main_tx_cdc_cdc_sink_payload_data;
wire [3:0] main_tx_cdc_cdc_sink_payload_last_be;
wire [3:0] main_tx_cdc_cdc_sink_payload_error;
wire main_tx_cdc_cdc_source_valid;
wire main_tx_cdc_cdc_source_ready;
wire main_tx_cdc_cdc_source_first;
wire main_tx_cdc_cdc_source_last;
wire [31:0] main_tx_cdc_cdc_source_payload_data;
wire [3:0] main_tx_cdc_cdc_source_payload_last_be;
wire [3:0] main_tx_cdc_cdc_source_payload_error;
wire main_tx_cdc_cdc_asyncfifo_we;
wire main_tx_cdc_cdc_asyncfifo_writable;
wire main_tx_cdc_cdc_asyncfifo_re;
wire main_tx_cdc_cdc_asyncfifo_readable;
wire [41:0] main_tx_cdc_cdc_asyncfifo_din;
wire [41:0] main_tx_cdc_cdc_asyncfifo_dout;
wire main_tx_cdc_cdc_graycounter0_ce;
(* dont_touch = "true" *) reg [5:0] main_tx_cdc_cdc_graycounter0_q = 6'd0;
wire [5:0] main_tx_cdc_cdc_graycounter0_q_next;
reg [5:0] main_tx_cdc_cdc_graycounter0_q_binary = 6'd0;
reg [5:0] main_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0;
wire main_tx_cdc_cdc_graycounter1_ce;
(* dont_touch = "true" *) reg [5:0] main_tx_cdc_cdc_graycounter1_q = 6'd0;
wire [5:0] main_tx_cdc_cdc_graycounter1_q_next;
reg [5:0] main_tx_cdc_cdc_graycounter1_q_binary = 6'd0;
reg [5:0] main_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0;
wire [5:0] main_tx_cdc_cdc_produce_rdomain;
wire [5:0] main_tx_cdc_cdc_consume_wdomain;
wire [4:0] main_tx_cdc_cdc_wrport_adr;
wire [41:0] main_tx_cdc_cdc_wrport_dat_r;
wire main_tx_cdc_cdc_wrport_we;
wire [41:0] main_tx_cdc_cdc_wrport_dat_w;
wire [4:0] main_tx_cdc_cdc_rdport_adr;
wire [41:0] main_tx_cdc_cdc_rdport_dat_r;
wire [31:0] main_tx_cdc_cdc_fifo_in_payload_data;
wire [3:0] main_tx_cdc_cdc_fifo_in_payload_last_be;
wire [3:0] main_tx_cdc_cdc_fifo_in_payload_error;
wire main_tx_cdc_cdc_fifo_in_first;
wire main_tx_cdc_cdc_fifo_in_last;
wire [31:0] main_tx_cdc_cdc_fifo_out_payload_data;
wire [3:0] main_tx_cdc_cdc_fifo_out_payload_last_be;
wire [3:0] main_tx_cdc_cdc_fifo_out_payload_error;
wire main_tx_cdc_cdc_fifo_out_first;
wire main_tx_cdc_cdc_fifo_out_last;
wire main_rx_cdc_sink_sink_valid;
wire main_rx_cdc_sink_sink_ready;
wire main_rx_cdc_sink_sink_first;
wire main_rx_cdc_sink_sink_last;
wire [31:0] main_rx_cdc_sink_sink_payload_data;
wire [3:0] main_rx_cdc_sink_sink_payload_last_be;
wire [3:0] main_rx_cdc_sink_sink_payload_error;
wire main_rx_cdc_source_source_valid;
wire main_rx_cdc_source_source_ready;
wire main_rx_cdc_source_source_first;
wire main_rx_cdc_source_source_last;
wire [31:0] main_rx_cdc_source_source_payload_data;
wire [3:0] main_rx_cdc_source_source_payload_last_be;
wire [3:0] main_rx_cdc_source_source_payload_error;
wire main_rx_cdc_cdc_sink_valid;
wire main_rx_cdc_cdc_sink_ready;
wire main_rx_cdc_cdc_sink_first;
wire main_rx_cdc_cdc_sink_last;
wire [31:0] main_rx_cdc_cdc_sink_payload_data;
wire [3:0] main_rx_cdc_cdc_sink_payload_last_be;
wire [3:0] main_rx_cdc_cdc_sink_payload_error;
wire main_rx_cdc_cdc_source_valid;
wire main_rx_cdc_cdc_source_ready;
wire main_rx_cdc_cdc_source_first;
wire main_rx_cdc_cdc_source_last;
wire [31:0] main_rx_cdc_cdc_source_payload_data;
wire [3:0] main_rx_cdc_cdc_source_payload_last_be;
wire [3:0] main_rx_cdc_cdc_source_payload_error;
wire main_rx_cdc_cdc_asyncfifo_we;
wire main_rx_cdc_cdc_asyncfifo_writable;
wire main_rx_cdc_cdc_asyncfifo_re;
wire main_rx_cdc_cdc_asyncfifo_readable;
wire [41:0] main_rx_cdc_cdc_asyncfifo_din;
wire [41:0] main_rx_cdc_cdc_asyncfifo_dout;
wire main_rx_cdc_cdc_graycounter0_ce;
(* dont_touch = "true" *) reg [5:0] main_rx_cdc_cdc_graycounter0_q = 6'd0;
wire [5:0] main_rx_cdc_cdc_graycounter0_q_next;
reg [5:0] main_rx_cdc_cdc_graycounter0_q_binary = 6'd0;
reg [5:0] main_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0;
wire main_rx_cdc_cdc_graycounter1_ce;
(* dont_touch = "true" *) reg [5:0] main_rx_cdc_cdc_graycounter1_q = 6'd0;
wire [5:0] main_rx_cdc_cdc_graycounter1_q_next;
reg [5:0] main_rx_cdc_cdc_graycounter1_q_binary = 6'd0;
reg [5:0] main_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0;
wire [5:0] main_rx_cdc_cdc_produce_rdomain;
wire [5:0] main_rx_cdc_cdc_consume_wdomain;
wire [4:0] main_rx_cdc_cdc_wrport_adr;
wire [41:0] main_rx_cdc_cdc_wrport_dat_r;
wire main_rx_cdc_cdc_wrport_we;
wire [41:0] main_rx_cdc_cdc_wrport_dat_w;
wire [4:0] main_rx_cdc_cdc_rdport_adr;
wire [41:0] main_rx_cdc_cdc_rdport_dat_r;
wire [31:0] main_rx_cdc_cdc_fifo_in_payload_data;
wire [3:0] main_rx_cdc_cdc_fifo_in_payload_last_be;
wire [3:0] main_rx_cdc_cdc_fifo_in_payload_error;
wire main_rx_cdc_cdc_fifo_in_first;
wire main_rx_cdc_cdc_fifo_in_last;
wire [31:0] main_rx_cdc_cdc_fifo_out_payload_data;
wire [3:0] main_rx_cdc_cdc_fifo_out_payload_last_be;
wire [3:0] main_rx_cdc_cdc_fifo_out_payload_error;
wire main_rx_cdc_cdc_fifo_out_first;
wire main_rx_cdc_cdc_fifo_out_last;
wire main_sink_valid;
wire main_sink_ready;
wire main_sink_first;
wire main_sink_last;
wire [31:0] main_sink_payload_data;
wire [3:0] main_sink_payload_last_be;
wire [3:0] main_sink_payload_error;
wire main_source_valid;
wire main_source_ready;
wire main_source_first;
wire main_source_last;
wire [31:0] main_source_payload_data;
wire [3:0] main_source_payload_last_be;
wire [3:0] main_source_payload_error;
wire [29:0] main_bus_adr;
wire [31:0] main_bus_dat_w;
wire [31:0] main_bus_dat_r;
wire [3:0] main_bus_sel;
wire main_bus_cyc;
wire main_bus_stb;
wire main_bus_ack;
wire main_bus_we;
wire [2:0] main_bus_cti;
wire [1:0] main_bus_bte;
wire main_bus_err;
wire main_writer_sink_sink_valid;
reg main_writer_sink_sink_ready = 1'd1;
wire main_writer_sink_sink_first;
wire main_writer_sink_sink_last;
wire [31:0] main_writer_sink_sink_payload_data;
wire [3:0] main_writer_sink_sink_payload_last_be;
wire [3:0] main_writer_sink_sink_payload_error;
wire main_writer_slot_status;
wire main_writer_slot_we;
reg main_writer_slot_re = 1'd0;
wire [31:0] main_writer_length_status;
wire main_writer_length_we;
reg main_writer_length_re = 1'd0;
reg [31:0] main_writer_errors_status = 32'd0;
wire main_writer_errors_we;
reg main_writer_errors_re = 1'd0;
wire main_writer_irq;
wire main_writer_available_status;
wire main_writer_available_pending;
wire main_writer_available_trigger;
reg main_writer_available_clear = 1'd0;
wire main_writer_available0;
wire main_writer_status_status;
wire main_writer_status_we;
reg main_writer_status_re = 1'd0;
wire main_writer_available1;
wire main_writer_pending_status;
wire main_writer_pending_we;
reg main_writer_pending_re = 1'd0;
reg main_writer_pending_r = 1'd0;
wire main_writer_available2;
reg main_writer_enable_storage = 1'd0;
reg main_writer_enable_re = 1'd0;
reg [2:0] main_writer_inc = 3'd0;
reg [31:0] main_writer_counter = 32'd0;
reg main_writer_slot = 1'd0;
reg main_writer_slot_ce = 1'd0;
reg main_writer_start = 1'd0;
reg main_writer_ongoing = 1'd0;
reg main_writer_stat_fifo_sink_valid = 1'd0;
wire main_writer_stat_fifo_sink_ready;
reg main_writer_stat_fifo_sink_first = 1'd0;
reg main_writer_stat_fifo_sink_last = 1'd0;
wire main_writer_stat_fifo_sink_payload_slot;
wire [31:0] main_writer_stat_fifo_sink_payload_length;
wire main_writer_stat_fifo_source_valid;
wire main_writer_stat_fifo_source_ready;
wire main_writer_stat_fifo_source_first;
wire main_writer_stat_fifo_source_last;
wire main_writer_stat_fifo_source_payload_slot;
wire [31:0] main_writer_stat_fifo_source_payload_length;
wire main_writer_stat_fifo_syncfifo_we;
wire main_writer_stat_fifo_syncfifo_writable;
wire main_writer_stat_fifo_syncfifo_re;
wire main_writer_stat_fifo_syncfifo_readable;
wire [34:0] main_writer_stat_fifo_syncfifo_din;
wire [34:0] main_writer_stat_fifo_syncfifo_dout;
reg [1:0] main_writer_stat_fifo_level = 2'd0;
reg main_writer_stat_fifo_replace = 1'd0;
reg main_writer_stat_fifo_produce = 1'd0;
reg main_writer_stat_fifo_consume = 1'd0;
reg main_writer_stat_fifo_wrport_adr = 1'd0;
wire [34:0] main_writer_stat_fifo_wrport_dat_r;
wire main_writer_stat_fifo_wrport_we;
wire [34:0] main_writer_stat_fifo_wrport_dat_w;
wire main_writer_stat_fifo_do_read;
wire main_writer_stat_fifo_rdport_adr;
wire [34:0] main_writer_stat_fifo_rdport_dat_r;
wire main_writer_stat_fifo_fifo_in_payload_slot;
wire [31:0] main_writer_stat_fifo_fifo_in_payload_length;
wire main_writer_stat_fifo_fifo_in_first;
wire main_writer_stat_fifo_fifo_in_last;
wire main_writer_stat_fifo_fifo_out_payload_slot;
wire [31:0] main_writer_stat_fifo_fifo_out_payload_length;
wire main_writer_stat_fifo_fifo_out_first;
wire main_writer_stat_fifo_fifo_out_last;
reg [8:0] main_writer_memory0_adr = 9'd0;
wire [31:0] main_writer_memory0_dat_r;
reg main_writer_memory0_we = 1'd0;
reg [31:0] main_writer_memory0_dat_w = 32'd0;
reg [8:0] main_writer_memory1_adr = 9'd0;
wire [31:0] main_writer_memory1_dat_r;
reg main_writer_memory1_we = 1'd0;
reg [31:0] main_writer_memory1_dat_w = 32'd0;
reg main_reader_source_source_valid = 1'd0;
wire main_reader_source_source_ready;
reg main_reader_source_source_first = 1'd0;
reg main_reader_source_source_last = 1'd0;
reg [31:0] main_reader_source_source_payload_data = 32'd0;
reg [3:0] main_reader_source_source_payload_last_be = 4'd0;
reg [3:0] main_reader_source_source_payload_error = 4'd0;
reg main_reader_start_start_re = 1'd0;
wire main_reader_start_start_r;
reg main_reader_start_start_we = 1'd0;
reg main_reader_start_start_w = 1'd0;
wire main_reader_ready_status;
wire main_reader_ready_we;
reg main_reader_ready_re = 1'd0;
wire [1:0] main_reader_level_status;
wire main_reader_level_we;
reg main_reader_level_re = 1'd0;
reg main_reader_slot_storage = 1'd0;
reg main_reader_slot_re = 1'd0;
reg [10:0] main_reader_length_storage = 11'd0;
reg main_reader_length_re = 1'd0;
wire main_reader_irq;
wire main_reader_eventsourcepulse_status;
reg main_reader_eventsourcepulse_pending = 1'd0;
reg main_reader_eventsourcepulse_trigger = 1'd0;
reg main_reader_eventsourcepulse_clear = 1'd0;
wire main_reader_event00;
wire main_reader_status_status;
wire main_reader_status_we;
reg main_reader_status_re = 1'd0;
wire main_reader_event01;
wire main_reader_pending_status;
wire main_reader_pending_we;
reg main_reader_pending_re = 1'd0;
reg main_reader_pending_r = 1'd0;
wire main_reader_event02;
reg main_reader_enable_storage = 1'd0;
reg main_reader_enable_re = 1'd0;
reg main_reader_start = 1'd0;
wire main_reader_cmd_fifo_sink_valid;
wire main_reader_cmd_fifo_sink_ready;
reg main_reader_cmd_fifo_sink_first = 1'd0;
reg main_reader_cmd_fifo_sink_last = 1'd0;
wire main_reader_cmd_fifo_sink_payload_slot;
wire [10:0] main_reader_cmd_fifo_sink_payload_length;
wire main_reader_cmd_fifo_source_valid;
reg main_reader_cmd_fifo_source_ready = 1'd0;
wire main_reader_cmd_fifo_source_first;
wire main_reader_cmd_fifo_source_last;
wire main_reader_cmd_fifo_source_payload_slot;
wire [10:0] main_reader_cmd_fifo_source_payload_length;
wire main_reader_cmd_fifo_syncfifo_we;
wire main_reader_cmd_fifo_syncfifo_writable;
wire main_reader_cmd_fifo_syncfifo_re;
wire main_reader_cmd_fifo_syncfifo_readable;
wire [13:0] main_reader_cmd_fifo_syncfifo_din;
wire [13:0] main_reader_cmd_fifo_syncfifo_dout;
reg [1:0] main_reader_cmd_fifo_level = 2'd0;
reg main_reader_cmd_fifo_replace = 1'd0;
reg main_reader_cmd_fifo_produce = 1'd0;
reg main_reader_cmd_fifo_consume = 1'd0;
reg main_reader_cmd_fifo_wrport_adr = 1'd0;
wire [13:0] main_reader_cmd_fifo_wrport_dat_r;
wire main_reader_cmd_fifo_wrport_we;
wire [13:0] main_reader_cmd_fifo_wrport_dat_w;
wire main_reader_cmd_fifo_do_read;
wire main_reader_cmd_fifo_rdport_adr;
wire [13:0] main_reader_cmd_fifo_rdport_dat_r;
wire main_reader_cmd_fifo_fifo_in_payload_slot;
wire [10:0] main_reader_cmd_fifo_fifo_in_payload_length;
wire main_reader_cmd_fifo_fifo_in_first;
wire main_reader_cmd_fifo_fifo_in_last;
wire main_reader_cmd_fifo_fifo_out_payload_slot;
wire [10:0] main_reader_cmd_fifo_fifo_out_payload_length;
wire main_reader_cmd_fifo_fifo_out_first;
wire main_reader_cmd_fifo_fifo_out_last;
reg [10:0] main_reader_read_address = 11'd0;
reg [10:0] main_reader_counter = 11'd0;
wire [8:0] main_reader_memory0_adr;
wire [31:0] main_reader_memory0_dat_r;
wire [8:0] main_reader_memory1_adr;
wire [31:0] main_reader_memory1_dat_r;
wire main_ev_irq;
wire [29:0] main_sram0_bus_adr0;
wire [31:0] main_sram0_bus_dat_w0;
wire [31:0] main_sram0_bus_dat_r0;
wire [3:0] main_sram0_bus_sel0;
wire main_sram0_bus_cyc0;
wire main_sram0_bus_stb0;
reg main_sram0_bus_ack0 = 1'd0;
wire main_sram0_bus_we0;
wire [2:0] main_sram0_bus_cti0;
wire [1:0] main_sram0_bus_bte0;
reg main_sram0_bus_err0 = 1'd0;
wire [8:0] main_sram0_adr0;
wire [31:0] main_sram0_dat_r0;
wire [29:0] main_sram1_bus_adr0;
wire [31:0] main_sram1_bus_dat_w0;
wire [31:0] main_sram1_bus_dat_r0;
wire [3:0] main_sram1_bus_sel0;
wire main_sram1_bus_cyc0;
wire main_sram1_bus_stb0;
reg main_sram1_bus_ack0 = 1'd0;
wire main_sram1_bus_we0;
wire [2:0] main_sram1_bus_cti0;
wire [1:0] main_sram1_bus_bte0;
reg main_sram1_bus_err0 = 1'd0;
wire [8:0] main_sram1_adr0;
wire [31:0] main_sram1_dat_r0;
wire [29:0] main_sram0_bus_adr1;
wire [31:0] main_sram0_bus_dat_w1;
wire [31:0] main_sram0_bus_dat_r1;
wire [3:0] main_sram0_bus_sel1;
wire main_sram0_bus_cyc1;
wire main_sram0_bus_stb1;
reg main_sram0_bus_ack1 = 1'd0;
wire main_sram0_bus_we1;
wire [2:0] main_sram0_bus_cti1;
wire [1:0] main_sram0_bus_bte1;
reg main_sram0_bus_err1 = 1'd0;
wire [8:0] main_sram0_adr1;
wire [31:0] main_sram0_dat_r1;
reg [3:0] main_sram0_we = 4'd0;
wire [31:0] main_sram0_dat_w;
wire [29:0] main_sram1_bus_adr1;
wire [31:0] main_sram1_bus_dat_w1;
wire [31:0] main_sram1_bus_dat_r1;
wire [3:0] main_sram1_bus_sel1;
wire main_sram1_bus_cyc1;
wire main_sram1_bus_stb1;
reg main_sram1_bus_ack1 = 1'd0;
wire main_sram1_bus_we1;
wire [2:0] main_sram1_bus_cti1;
wire [1:0] main_sram1_bus_bte1;
reg main_sram1_bus_err1 = 1'd0;
wire [8:0] main_sram1_adr1;
wire [31:0] main_sram1_dat_r1;
reg [3:0] main_sram1_we = 4'd0;
wire [31:0] main_sram1_dat_w;
reg [3:0] main_slave_sel = 4'd0;
reg [3:0] main_slave_sel_r = 4'd0;
wire [29:0] main_wb_bus_adr;
wire [31:0] main_wb_bus_dat_w;
wire [31:0] main_wb_bus_dat_r;
wire [3:0] main_wb_bus_sel;
wire main_wb_bus_cyc;
wire main_wb_bus_stb;
wire main_wb_bus_ack;
wire main_wb_bus_we;
wire [2:0] main_wb_bus_cti;
wire [1:0] main_wb_bus_bte;
wire main_wb_bus_err;
reg builder_liteethmacgap_state = 1'd0;
reg builder_liteethmacgap_next_state = 1'd0;
reg [3:0] main_tx_gap_inserter_counter_liteethmacgap_next_value = 4'd0;
reg main_tx_gap_inserter_counter_liteethmacgap_next_value_ce = 1'd0;
reg [1:0] builder_liteethmacpreambleinserter_state = 2'd0;
reg [1:0] builder_liteethmacpreambleinserter_next_state = 2'd0;
reg [2:0] main_preamble_inserter_count_liteethmacpreambleinserter_next_value = 3'd0;
reg main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce = 1'd0;
reg builder_liteethmacpreamblechecker_state = 1'd0;
reg builder_liteethmacpreamblechecker_next_state = 1'd0;
reg [1:0] builder_liteethmaccrc32inserter_state = 2'd0;
reg [1:0] builder_liteethmaccrc32inserter_next_state = 2'd0;
reg [1:0] builder_liteethmaccrc32checker_state = 2'd0;
reg [1:0] builder_liteethmaccrc32checker_next_state = 2'd0;
reg builder_liteethmacpaddinginserter_state = 1'd0;
reg builder_liteethmacpaddinginserter_next_state = 1'd0;
reg [15:0] main_padding_inserter_counter_liteethmacpaddinginserter_next_value = 16'd0;
reg main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce = 1'd0;
reg builder_liteethmactxlastbe_state = 1'd0;
reg builder_liteethmactxlastbe_next_state = 1'd0;
reg [2:0] builder_liteethmacsramwriter_state = 3'd0;
reg [2:0] builder_liteethmacsramwriter_next_state = 3'd0;
reg [31:0] main_writer_counter_t_next_value = 32'd0;
reg main_writer_counter_t_next_value_ce = 1'd0;
reg [31:0] main_writer_errors_status_f_next_value = 32'd0;
reg main_writer_errors_status_f_next_value_ce = 1'd0;
reg [1:0] builder_liteethmacsramreader_state = 2'd0;
reg [1:0] builder_liteethmacsramreader_next_state = 2'd0;
reg [10:0] main_reader_counter_next_value = 11'd0;
reg main_reader_counter_next_value_ce = 1'd0;
reg [13:0] builder_maccore_adr = 14'd0;
reg builder_maccore_we = 1'd0;
reg [31:0] builder_maccore_dat_w = 32'd0;
wire [31:0] builder_maccore_dat_r;
wire [29:0] builder_maccore_wishbone_adr;
wire [31:0] builder_maccore_wishbone_dat_w;
reg [31:0] builder_maccore_wishbone_dat_r = 32'd0;
wire [3:0] builder_maccore_wishbone_sel;
wire builder_maccore_wishbone_cyc;
wire builder_maccore_wishbone_stb;
reg builder_maccore_wishbone_ack = 1'd0;
wire builder_maccore_wishbone_we;
wire [2:0] builder_maccore_wishbone_cti;
wire [1:0] builder_maccore_wishbone_bte;
reg builder_maccore_wishbone_err = 1'd0;
wire [29:0] builder_shared_adr;
wire [31:0] builder_shared_dat_w;
reg [31:0] builder_shared_dat_r = 32'd0;
wire [3:0] builder_shared_sel;
wire builder_shared_cyc;
wire builder_shared_stb;
reg builder_shared_ack = 1'd0;
wire builder_shared_we;
wire [2:0] builder_shared_cti;
wire [1:0] builder_shared_bte;
wire builder_shared_err;
wire builder_request;
wire builder_grant;
reg [1:0] builder_slave_sel = 2'd0;
reg [1:0] builder_slave_sel_r = 2'd0;
reg builder_error = 1'd0;
wire builder_wait;
wire builder_done;
reg [19:0] builder_count = 20'd1000000;
wire [13:0] builder_interface0_bank_bus_adr;
wire builder_interface0_bank_bus_we;
wire [31:0] builder_interface0_bank_bus_dat_w;
reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0;
reg builder_csrbank0_reset0_re = 1'd0;
wire [1:0] builder_csrbank0_reset0_r;
reg builder_csrbank0_reset0_we = 1'd0;
wire [1:0] builder_csrbank0_reset0_w;
reg builder_csrbank0_scratch0_re = 1'd0;
wire [31:0] builder_csrbank0_scratch0_r;
reg builder_csrbank0_scratch0_we = 1'd0;
wire [31:0] builder_csrbank0_scratch0_w;
reg builder_csrbank0_bus_errors_re = 1'd0;
wire [31:0] builder_csrbank0_bus_errors_r;
reg builder_csrbank0_bus_errors_we = 1'd0;
wire [31:0] builder_csrbank0_bus_errors_w;
wire builder_csrbank0_sel;
wire [13:0] builder_interface1_bank_bus_adr;
wire builder_interface1_bank_bus_we;
wire [31:0] builder_interface1_bank_bus_dat_w;
reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0;
reg builder_csrbank1_sram_writer_slot_re = 1'd0;
wire builder_csrbank1_sram_writer_slot_r;
reg builder_csrbank1_sram_writer_slot_we = 1'd0;
wire builder_csrbank1_sram_writer_slot_w;
reg builder_csrbank1_sram_writer_length_re = 1'd0;
wire [31:0] builder_csrbank1_sram_writer_length_r;
reg builder_csrbank1_sram_writer_length_we = 1'd0;
wire [31:0] builder_csrbank1_sram_writer_length_w;
reg builder_csrbank1_sram_writer_errors_re = 1'd0;
wire [31:0] builder_csrbank1_sram_writer_errors_r;
reg builder_csrbank1_sram_writer_errors_we = 1'd0;
wire [31:0] builder_csrbank1_sram_writer_errors_w;
reg builder_csrbank1_sram_writer_ev_status_re = 1'd0;
wire builder_csrbank1_sram_writer_ev_status_r;
reg builder_csrbank1_sram_writer_ev_status_we = 1'd0;
wire builder_csrbank1_sram_writer_ev_status_w;
reg builder_csrbank1_sram_writer_ev_pending_re = 1'd0;
wire builder_csrbank1_sram_writer_ev_pending_r;
reg builder_csrbank1_sram_writer_ev_pending_we = 1'd0;
wire builder_csrbank1_sram_writer_ev_pending_w;
reg builder_csrbank1_sram_writer_ev_enable0_re = 1'd0;
wire builder_csrbank1_sram_writer_ev_enable0_r;
reg builder_csrbank1_sram_writer_ev_enable0_we = 1'd0;
wire builder_csrbank1_sram_writer_ev_enable0_w;
reg builder_csrbank1_sram_reader_ready_re = 1'd0;
wire builder_csrbank1_sram_reader_ready_r;
reg builder_csrbank1_sram_reader_ready_we = 1'd0;
wire builder_csrbank1_sram_reader_ready_w;
reg builder_csrbank1_sram_reader_level_re = 1'd0;
wire [1:0] builder_csrbank1_sram_reader_level_r;
reg builder_csrbank1_sram_reader_level_we = 1'd0;
wire [1:0] builder_csrbank1_sram_reader_level_w;
reg builder_csrbank1_sram_reader_slot0_re = 1'd0;
wire builder_csrbank1_sram_reader_slot0_r;
reg builder_csrbank1_sram_reader_slot0_we = 1'd0;
wire builder_csrbank1_sram_reader_slot0_w;
reg builder_csrbank1_sram_reader_length0_re = 1'd0;
wire [10:0] builder_csrbank1_sram_reader_length0_r;
reg builder_csrbank1_sram_reader_length0_we = 1'd0;
wire [10:0] builder_csrbank1_sram_reader_length0_w;
reg builder_csrbank1_sram_reader_ev_status_re = 1'd0;
wire builder_csrbank1_sram_reader_ev_status_r;
reg builder_csrbank1_sram_reader_ev_status_we = 1'd0;
wire builder_csrbank1_sram_reader_ev_status_w;
reg builder_csrbank1_sram_reader_ev_pending_re = 1'd0;
wire builder_csrbank1_sram_reader_ev_pending_r;
reg builder_csrbank1_sram_reader_ev_pending_we = 1'd0;
wire builder_csrbank1_sram_reader_ev_pending_w;
reg builder_csrbank1_sram_reader_ev_enable0_re = 1'd0;
wire builder_csrbank1_sram_reader_ev_enable0_r;
reg builder_csrbank1_sram_reader_ev_enable0_we = 1'd0;
wire builder_csrbank1_sram_reader_ev_enable0_w;
reg builder_csrbank1_preamble_crc_re = 1'd0;
wire builder_csrbank1_preamble_crc_r;
reg builder_csrbank1_preamble_crc_we = 1'd0;
wire builder_csrbank1_preamble_crc_w;
reg builder_csrbank1_preamble_errors_re = 1'd0;
wire [31:0] builder_csrbank1_preamble_errors_r;
reg builder_csrbank1_preamble_errors_we = 1'd0;
wire [31:0] builder_csrbank1_preamble_errors_w;
reg builder_csrbank1_crc_errors_re = 1'd0;
wire [31:0] builder_csrbank1_crc_errors_r;
reg builder_csrbank1_crc_errors_we = 1'd0;
wire [31:0] builder_csrbank1_crc_errors_w;
wire builder_csrbank1_sel;
wire [13:0] builder_interface2_bank_bus_adr;
wire builder_interface2_bank_bus_we;
wire [31:0] builder_interface2_bank_bus_dat_w;
reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0;
reg builder_csrbank2_crg_reset0_re = 1'd0;
wire builder_csrbank2_crg_reset0_r;
reg builder_csrbank2_crg_reset0_we = 1'd0;
wire builder_csrbank2_crg_reset0_w;
reg builder_csrbank2_mdio_w0_re = 1'd0;
wire [2:0] builder_csrbank2_mdio_w0_r;
reg builder_csrbank2_mdio_w0_we = 1'd0;
wire [2:0] builder_csrbank2_mdio_w0_w;
reg builder_csrbank2_mdio_r_re = 1'd0;
wire builder_csrbank2_mdio_r_r;
reg builder_csrbank2_mdio_r_we = 1'd0;
wire builder_csrbank2_mdio_r_w;
wire builder_csrbank2_sel;
wire [13:0] builder_csr_interconnect_adr;
wire builder_csr_interconnect_we;
wire [31:0] builder_csr_interconnect_dat_w;
wire [31:0] builder_csr_interconnect_dat_r;
reg builder_state = 1'd0;
reg builder_next_state = 1'd0;
reg [29:0] builder_array_muxed0 = 30'd0;
reg [31:0] builder_array_muxed1 = 32'd0;
reg [3:0] builder_array_muxed2 = 4'd0;
reg builder_array_muxed3 = 1'd0;
reg builder_array_muxed4 = 1'd0;
reg builder_array_muxed5 = 1'd0;
reg [2:0] builder_array_muxed6 = 3'd0;
reg [1:0] builder_array_muxed7 = 2'd0;
wire builder_rst_meta0;
wire builder_rst_meta1;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl0_regs0 = 1'd0;
(* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl0_regs1 = 1'd0;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl1_regs0 = 1'd0;
(* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl1_regs1 = 1'd0;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl2_regs0 = 1'd0;
(* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl2_regs1 = 1'd0;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl3_regs0 = 6'd0;
(* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl3_regs1 = 6'd0;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl4_regs0 = 6'd0;
(* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl4_regs1 = 6'd0;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl5_regs0 = 6'd0;
(* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl5_regs1 = 6'd0;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl6_regs0 = 6'd0;
(* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl6_regs1 = 6'd0;
assign main_wb_bus_adr = wishbone_adr;
assign main_wb_bus_dat_w = wishbone_dat_w;
assign wishbone_dat_r = main_wb_bus_dat_r;
assign main_wb_bus_sel = wishbone_sel;
assign main_wb_bus_cyc = wishbone_cyc;
assign main_wb_bus_stb = wishbone_stb;
assign wishbone_ack = main_wb_bus_ack;
assign main_wb_bus_we = wishbone_we;
assign main_wb_bus_cti = wishbone_cti;
assign main_wb_bus_bte = wishbone_bte;
assign wishbone_err = main_wb_bus_err;
assign interrupt = main_ev_irq;
assign main_maccore_maccore_bus_error = builder_error;
assign main_maccore_maccore_bus_errors_status = main_maccore_maccore_bus_errors;
assign sys_clk = sys_clock;
assign por_clk = sys_clock;
assign sys_rst = main_maccore_int_rst;
assign eth_rx_clk = mii_eth_clocks_rx;
assign eth_tx_clk = mii_eth_clocks_tx;
assign main_maccore_ethphy_reset0 = (main_maccore_ethphy_reset_storage | main_maccore_ethphy_reset1);
assign mii_eth_rst_n = (~main_maccore_ethphy_reset0);
assign main_maccore_ethphy_counter_done = (main_maccore_ethphy_counter == 9'd256);
assign main_maccore_ethphy_counter_ce = (~main_maccore_ethphy_counter_done);
assign main_maccore_ethphy_reset1 = (~main_maccore_ethphy_counter_done);
assign main_maccore_ethphy_liteethphymiitx_converter_sink_valid = main_maccore_ethphy_liteethphymiitx_sink_sink_valid;
assign main_maccore_ethphy_liteethphymiitx_converter_sink_payload_data = main_maccore_ethphy_liteethphymiitx_sink_sink_payload_data;
assign main_maccore_ethphy_liteethphymiitx_sink_sink_ready = main_maccore_ethphy_liteethphymiitx_converter_sink_ready;
assign main_maccore_ethphy_liteethphymiitx_converter_source_ready = 1'd1;
assign main_maccore_ethphy_liteethphymiitx_converter_converter_sink_valid = main_maccore_ethphy_liteethphymiitx_converter_sink_valid;
assign main_maccore_ethphy_liteethphymiitx_converter_converter_sink_first = main_maccore_ethphy_liteethphymiitx_converter_sink_first;
assign main_maccore_ethphy_liteethphymiitx_converter_converter_sink_last = main_maccore_ethphy_liteethphymiitx_converter_sink_last;
assign main_maccore_ethphy_liteethphymiitx_converter_sink_ready = main_maccore_ethphy_liteethphymiitx_converter_converter_sink_ready;
always @(*) begin
main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data <= 8'd0;
main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data[3:0] <= main_maccore_ethphy_liteethphymiitx_converter_sink_payload_data[3:0];
main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data[7:4] <= main_maccore_ethphy_liteethphymiitx_converter_sink_payload_data[7:4];
end
assign main_maccore_ethphy_liteethphymiitx_converter_source_valid = main_maccore_ethphy_liteethphymiitx_converter_source_source_valid;
assign main_maccore_ethphy_liteethphymiitx_converter_source_first = main_maccore_ethphy_liteethphymiitx_converter_source_source_first;
assign main_maccore_ethphy_liteethphymiitx_converter_source_last = main_maccore_ethphy_liteethphymiitx_converter_source_source_last;
assign main_maccore_ethphy_liteethphymiitx_converter_source_source_ready = main_maccore_ethphy_liteethphymiitx_converter_source_ready;
assign {main_maccore_ethphy_liteethphymiitx_converter_source_payload_data} = main_maccore_ethphy_liteethphymiitx_converter_source_source_payload_data;
assign main_maccore_ethphy_liteethphymiitx_converter_source_source_valid = main_maccore_ethphy_liteethphymiitx_converter_converter_source_valid;
assign main_maccore_ethphy_liteethphymiitx_converter_converter_source_ready = main_maccore_ethphy_liteethphymiitx_converter_source_source_ready;
assign main_maccore_ethphy_liteethphymiitx_converter_source_source_first = main_maccore_ethphy_liteethphymiitx_converter_converter_source_first;
assign main_maccore_ethphy_liteethphymiitx_converter_source_source_last = main_maccore_ethphy_liteethphymiitx_converter_converter_source_last;
assign main_maccore_ethphy_liteethphymiitx_converter_source_source_payload_data = main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_data;
assign main_maccore_ethphy_liteethphymiitx_converter_converter_first = (main_maccore_ethphy_liteethphymiitx_converter_converter_mux == 1'd0);
assign main_maccore_ethphy_liteethphymiitx_converter_converter_last = (main_maccore_ethphy_liteethphymiitx_converter_converter_mux == 1'd1);
assign main_maccore_ethphy_liteethphymiitx_converter_converter_source_valid = main_maccore_ethphy_liteethphymiitx_converter_converter_sink_valid;
assign main_maccore_ethphy_liteethphymiitx_converter_converter_source_first = (main_maccore_ethphy_liteethphymiitx_converter_converter_sink_first & main_maccore_ethphy_liteethphymiitx_converter_converter_first);
assign main_maccore_ethphy_liteethphymiitx_converter_converter_source_last = (main_maccore_ethphy_liteethphymiitx_converter_converter_sink_last & main_maccore_ethphy_liteethphymiitx_converter_converter_last);
assign main_maccore_ethphy_liteethphymiitx_converter_converter_sink_ready = (main_maccore_ethphy_liteethphymiitx_converter_converter_last & main_maccore_ethphy_liteethphymiitx_converter_converter_source_ready);
always @(*) begin
main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_data <= 4'd0;
case (main_maccore_ethphy_liteethphymiitx_converter_converter_mux)
1'd0: begin
main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_data <= main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data[3:0];
end
default: begin
main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_data <= main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data[7:4];
end
endcase
end
assign main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_valid_token_count = main_maccore_ethphy_liteethphymiitx_converter_converter_last;
assign main_maccore_ethphy_liteethphymiirx_converter_sink_last = (~mii_eth_rx_dv);
assign main_maccore_ethphy_liteethphymiirx_source_source_valid = main_maccore_ethphy_liteethphymiirx_converter_source_valid;
assign main_maccore_ethphy_liteethphymiirx_converter_source_ready = main_maccore_ethphy_liteethphymiirx_source_source_ready;
assign main_maccore_ethphy_liteethphymiirx_source_source_first = main_maccore_ethphy_liteethphymiirx_converter_source_first;
assign main_maccore_ethphy_liteethphymiirx_source_source_last = main_maccore_ethphy_liteethphymiirx_converter_source_last;
assign main_maccore_ethphy_liteethphymiirx_source_source_payload_data = main_maccore_ethphy_liteethphymiirx_converter_source_payload_data;
assign main_maccore_ethphy_liteethphymiirx_converter_converter_sink_valid = main_maccore_ethphy_liteethphymiirx_converter_sink_valid;
assign main_maccore_ethphy_liteethphymiirx_converter_converter_sink_first = main_maccore_ethphy_liteethphymiirx_converter_sink_first;
assign main_maccore_ethphy_liteethphymiirx_converter_converter_sink_last = main_maccore_ethphy_liteethphymiirx_converter_sink_last;
assign main_maccore_ethphy_liteethphymiirx_converter_sink_ready = main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready;
assign main_maccore_ethphy_liteethphymiirx_converter_converter_sink_payload_data = {main_maccore_ethphy_liteethphymiirx_converter_sink_payload_data};
assign main_maccore_ethphy_liteethphymiirx_converter_source_valid = main_maccore_ethphy_liteethphymiirx_converter_source_source_valid;
assign main_maccore_ethphy_liteethphymiirx_converter_source_first = main_maccore_ethphy_liteethphymiirx_converter_source_source_first;
assign main_maccore_ethphy_liteethphymiirx_converter_source_last = main_maccore_ethphy_liteethphymiirx_converter_source_source_last;
assign main_maccore_ethphy_liteethphymiirx_converter_source_source_ready = main_maccore_ethphy_liteethphymiirx_converter_source_ready;
always @(*) begin
main_maccore_ethphy_liteethphymiirx_converter_source_payload_data <= 8'd0;
main_maccore_ethphy_liteethphymiirx_converter_source_payload_data[3:0] <= main_maccore_ethphy_liteethphymiirx_converter_source_source_payload_data[3:0];
main_maccore_ethphy_liteethphymiirx_converter_source_payload_data[7:4] <= main_maccore_ethphy_liteethphymiirx_converter_source_source_payload_data[7:4];
end
assign main_maccore_ethphy_liteethphymiirx_converter_source_source_valid = main_maccore_ethphy_liteethphymiirx_converter_converter_source_valid;
assign main_maccore_ethphy_liteethphymiirx_converter_converter_source_ready = main_maccore_ethphy_liteethphymiirx_converter_source_source_ready;
assign main_maccore_ethphy_liteethphymiirx_converter_source_source_first = main_maccore_ethphy_liteethphymiirx_converter_converter_source_first;
assign main_maccore_ethphy_liteethphymiirx_converter_source_source_last = main_maccore_ethphy_liteethphymiirx_converter_converter_source_last;
assign main_maccore_ethphy_liteethphymiirx_converter_source_source_payload_data = main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_data;
assign main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready = ((~main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all) | main_maccore_ethphy_liteethphymiirx_converter_converter_source_ready);
assign main_maccore_ethphy_liteethphymiirx_converter_converter_source_valid = main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all;
assign main_maccore_ethphy_liteethphymiirx_converter_converter_load_part = (main_maccore_ethphy_liteethphymiirx_converter_converter_sink_valid & main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready);
assign mii_eth_mdc = main_maccore_ethphy__w_storage[0];
assign main_maccore_ethphy_data_oe = main_maccore_ethphy__w_storage[1];
assign main_maccore_ethphy_data_w = main_maccore_ethphy__w_storage[2];
assign main_tx_cdc_sink_sink_valid = main_source_valid;
assign main_source_ready = main_tx_cdc_sink_sink_ready;
assign main_tx_cdc_sink_sink_first = main_source_first;
assign main_tx_cdc_sink_sink_last = main_source_last;
assign main_tx_cdc_sink_sink_payload_data = main_source_payload_data;
assign main_tx_cdc_sink_sink_payload_last_be = main_source_payload_last_be;
assign main_tx_cdc_sink_sink_payload_error = main_source_payload_error;
assign main_sink_valid = main_rx_cdc_source_source_valid;
assign main_rx_cdc_source_source_ready = main_sink_ready;
assign main_sink_first = main_rx_cdc_source_source_first;
assign main_sink_last = main_rx_cdc_source_source_last;
assign main_sink_payload_data = main_rx_cdc_source_source_payload_data;
assign main_sink_payload_last_be = main_rx_cdc_source_source_payload_last_be;
assign main_sink_payload_error = main_rx_cdc_source_source_payload_error;
assign main_ps_preamble_error_i = main_preamble_checker_error;
assign main_ps_crc_error_i = main_liteethmaccrc32checker_error;
always @(*) begin
main_tx_gap_inserter_source_valid <= 1'd0;
builder_liteethmacgap_next_state <= 1'd0;
main_tx_gap_inserter_counter_liteethmacgap_next_value <= 4'd0;
main_tx_gap_inserter_source_first <= 1'd0;
main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd0;
main_tx_gap_inserter_source_last <= 1'd0;
main_tx_gap_inserter_source_payload_data <= 8'd0;
main_tx_gap_inserter_source_payload_last_be <= 1'd0;
main_tx_gap_inserter_source_payload_error <= 1'd0;
main_tx_gap_inserter_sink_ready <= 1'd0;
builder_liteethmacgap_next_state <= builder_liteethmacgap_state;
case (builder_liteethmacgap_state)
1'd1: begin
main_tx_gap_inserter_counter_liteethmacgap_next_value <= (main_tx_gap_inserter_counter + 1'd1);
main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1;
if ((main_tx_gap_inserter_counter == 4'd11)) begin
builder_liteethmacgap_next_state <= 1'd0;
end
end
default: begin
main_tx_gap_inserter_counter_liteethmacgap_next_value <= 1'd0;
main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1;
main_tx_gap_inserter_source_valid <= main_tx_gap_inserter_sink_valid;
main_tx_gap_inserter_sink_ready <= main_tx_gap_inserter_source_ready;
main_tx_gap_inserter_source_first <= main_tx_gap_inserter_sink_first;
main_tx_gap_inserter_source_last <= main_tx_gap_inserter_sink_last;
main_tx_gap_inserter_source_payload_data <= main_tx_gap_inserter_sink_payload_data;
main_tx_gap_inserter_source_payload_last_be <= main_tx_gap_inserter_sink_payload_last_be;
main_tx_gap_inserter_source_payload_error <= main_tx_gap_inserter_sink_payload_error;
if (((main_tx_gap_inserter_sink_valid & main_tx_gap_inserter_sink_last) & main_tx_gap_inserter_sink_ready)) begin
builder_liteethmacgap_next_state <= 1'd1;
end
end
endcase
end
assign main_preamble_inserter_source_payload_last_be = main_preamble_inserter_sink_payload_last_be;
always @(*) begin
builder_liteethmacpreambleinserter_next_state <= 2'd0;
main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= 3'd0;
main_preamble_inserter_source_valid <= 1'd0;
main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd0;
main_preamble_inserter_source_first <= 1'd0;
main_preamble_inserter_source_last <= 1'd0;
main_preamble_inserter_source_payload_data <= 8'd0;
main_preamble_inserter_source_payload_error <= 1'd0;
main_preamble_inserter_sink_ready <= 1'd0;
main_preamble_inserter_source_payload_data <= main_preamble_inserter_sink_payload_data;
builder_liteethmacpreambleinserter_next_state <= builder_liteethmacpreambleinserter_state;
case (builder_liteethmacpreambleinserter_state)
1'd1: begin
main_preamble_inserter_source_valid <= 1'd1;
case (main_preamble_inserter_count)
1'd0: begin
main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[7:0];
end
1'd1: begin
main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[15:8];
end
2'd2: begin
main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[23:16];
end
2'd3: begin
main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[31:24];
end
3'd4: begin
main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[39:32];
end
3'd5: begin
main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[47:40];
end
3'd6: begin
main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[55:48];
end
default: begin
main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[63:56];
end
endcase
if (main_preamble_inserter_source_ready) begin
if ((main_preamble_inserter_count == 3'd7)) begin
builder_liteethmacpreambleinserter_next_state <= 2'd2;
end else begin
main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= (main_preamble_inserter_count + 1'd1);
main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1;
end
end
end
2'd2: begin
main_preamble_inserter_source_valid <= main_preamble_inserter_sink_valid;
main_preamble_inserter_sink_ready <= main_preamble_inserter_source_ready;
main_preamble_inserter_source_first <= main_preamble_inserter_sink_first;
main_preamble_inserter_source_last <= main_preamble_inserter_sink_last;
main_preamble_inserter_source_payload_error <= main_preamble_inserter_sink_payload_error;
if (((main_preamble_inserter_sink_valid & main_preamble_inserter_sink_last) & main_preamble_inserter_source_ready)) begin
builder_liteethmacpreambleinserter_next_state <= 1'd0;
end
end
default: begin
main_preamble_inserter_sink_ready <= 1'd1;
main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= 1'd0;
main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1;
if (main_preamble_inserter_sink_valid) begin
main_preamble_inserter_sink_ready <= 1'd0;
builder_liteethmacpreambleinserter_next_state <= 1'd1;
end
end
endcase
end
assign main_preamble_checker_source_payload_data = main_preamble_checker_sink_payload_data;
assign main_preamble_checker_source_payload_last_be = main_preamble_checker_sink_payload_last_be;
always @(*) begin
builder_liteethmacpreamblechecker_next_state <= 1'd0;
main_preamble_checker_source_first <= 1'd0;
main_preamble_checker_sink_ready <= 1'd0;
main_preamble_checker_source_last <= 1'd0;
main_preamble_checker_source_payload_error <= 1'd0;
main_preamble_checker_error <= 1'd0;
main_preamble_checker_source_valid <= 1'd0;
builder_liteethmacpreamblechecker_next_state <= builder_liteethmacpreamblechecker_state;
case (builder_liteethmacpreamblechecker_state)
1'd1: begin
main_preamble_checker_source_valid <= main_preamble_checker_sink_valid;
main_preamble_checker_sink_ready <= main_preamble_checker_source_ready;
main_preamble_checker_source_first <= main_preamble_checker_sink_first;
main_preamble_checker_source_last <= main_preamble_checker_sink_last;
main_preamble_checker_source_payload_error <= main_preamble_checker_sink_payload_error;
if (((main_preamble_checker_source_valid & main_preamble_checker_source_last) & main_preamble_checker_source_ready)) begin
builder_liteethmacpreamblechecker_next_state <= 1'd0;
end
end
default: begin
main_preamble_checker_sink_ready <= 1'd1;
if (((main_preamble_checker_sink_valid & (~main_preamble_checker_sink_last)) & (main_preamble_checker_sink_payload_data == 8'd213))) begin
builder_liteethmacpreamblechecker_next_state <= 1'd1;
end
if ((main_preamble_checker_sink_valid & main_preamble_checker_sink_last)) begin
main_preamble_checker_error <= 1'd1;
end
end
endcase
end
assign main_liteethmaccrc32inserter_cnt_done = (main_liteethmaccrc32inserter_cnt == 1'd0);
assign main_liteethmaccrc32inserter_sink_valid = main_crc32_inserter_source_valid;
assign main_crc32_inserter_source_ready = main_liteethmaccrc32inserter_sink_ready;
assign main_liteethmaccrc32inserter_sink_first = main_crc32_inserter_source_first;
assign main_liteethmaccrc32inserter_sink_last = main_crc32_inserter_source_last;
assign main_liteethmaccrc32inserter_sink_payload_data = main_crc32_inserter_source_payload_data;
assign main_liteethmaccrc32inserter_sink_payload_last_be = main_crc32_inserter_source_payload_last_be;
assign main_liteethmaccrc32inserter_sink_payload_error = main_crc32_inserter_source_payload_error;
assign main_liteethmaccrc32inserter_data1 = main_liteethmaccrc32inserter_data0;
assign main_liteethmaccrc32inserter_last = main_liteethmaccrc32inserter_reg;
assign main_liteethmaccrc32inserter_value = (~{main_liteethmaccrc32inserter_reg[0], main_liteethmaccrc32inserter_reg[1], main_liteethmaccrc32inserter_reg[2], main_liteethmaccrc32inserter_reg[3], main_liteethmaccrc32inserter_reg[4], main_liteethmaccrc32inserter_reg[5], main_liteethmaccrc32inserter_reg[6], main_liteethmaccrc32inserter_reg[7], main_liteethmaccrc32inserter_reg[8], main_liteethmaccrc32inserter_reg[9], main_liteethmaccrc32inserter_reg[10], main_liteethmaccrc32inserter_reg[11], main_liteethmaccrc32inserter_reg[12], main_liteethmaccrc32inserter_reg[13], main_liteethmaccrc32inserter_reg[14], main_liteethmaccrc32inserter_reg[15], main_liteethmaccrc32inserter_reg[16], main_liteethmaccrc32inserter_reg[17], main_liteethmaccrc32inserter_reg[18], main_liteethmaccrc32inserter_reg[19], main_liteethmaccrc32inserter_reg[20], main_liteethmaccrc32inserter_reg[21], main_liteethmaccrc32inserter_reg[22], main_liteethmaccrc32inserter_reg[23], main_liteethmaccrc32inserter_reg[24], main_liteethmaccrc32inserter_reg[25], main_liteethmaccrc32inserter_reg[26], main_liteethmaccrc32inserter_reg[27], main_liteethmaccrc32inserter_reg[28], main_liteethmaccrc32inserter_reg[29], main_liteethmaccrc32inserter_reg[30], main_liteethmaccrc32inserter_reg[31]});
assign main_liteethmaccrc32inserter_error = (main_liteethmaccrc32inserter_next != 32'd3338984827);
always @(*) begin
main_liteethmaccrc32inserter_next <= 32'd0;
main_liteethmaccrc32inserter_next[0] <= (((main_liteethmaccrc32inserter_last[24] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
main_liteethmaccrc32inserter_next[1] <= (((((((main_liteethmaccrc32inserter_last[25] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
main_liteethmaccrc32inserter_next[2] <= (((((((((main_liteethmaccrc32inserter_last[26] ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
main_liteethmaccrc32inserter_next[3] <= (((((((main_liteethmaccrc32inserter_last[27] ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]);
main_liteethmaccrc32inserter_next[4] <= (((((((((main_liteethmaccrc32inserter_last[28] ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
main_liteethmaccrc32inserter_next[5] <= (((((((((((((main_liteethmaccrc32inserter_last[29] ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
main_liteethmaccrc32inserter_next[6] <= (((((((((((main_liteethmaccrc32inserter_last[30] ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]);
main_liteethmaccrc32inserter_next[7] <= (((((((((main_liteethmaccrc32inserter_last[31] ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]);
main_liteethmaccrc32inserter_next[8] <= ((((((((main_liteethmaccrc32inserter_last[0] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]);
main_liteethmaccrc32inserter_next[9] <= ((((((((main_liteethmaccrc32inserter_last[1] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]);
main_liteethmaccrc32inserter_next[10] <= ((((((((main_liteethmaccrc32inserter_last[2] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]);
main_liteethmaccrc32inserter_next[11] <= ((((((((main_liteethmaccrc32inserter_last[3] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]);
main_liteethmaccrc32inserter_next[12] <= ((((((((((((main_liteethmaccrc32inserter_last[4] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
main_liteethmaccrc32inserter_next[13] <= ((((((((((((main_liteethmaccrc32inserter_last[5] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]);
main_liteethmaccrc32inserter_next[14] <= ((((((((((main_liteethmaccrc32inserter_last[6] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]);
main_liteethmaccrc32inserter_next[15] <= ((((((((main_liteethmaccrc32inserter_last[7] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]);
main_liteethmaccrc32inserter_next[16] <= ((((((main_liteethmaccrc32inserter_last[8] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]);
main_liteethmaccrc32inserter_next[17] <= ((((((main_liteethmaccrc32inserter_last[9] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]);
main_liteethmaccrc32inserter_next[18] <= ((((((main_liteethmaccrc32inserter_last[10] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]);
main_liteethmaccrc32inserter_next[19] <= ((((main_liteethmaccrc32inserter_last[11] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]);
main_liteethmaccrc32inserter_next[20] <= ((main_liteethmaccrc32inserter_last[12] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]);
main_liteethmaccrc32inserter_next[21] <= ((main_liteethmaccrc32inserter_last[13] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]);
main_liteethmaccrc32inserter_next[22] <= ((main_liteethmaccrc32inserter_last[14] ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]);
main_liteethmaccrc32inserter_next[23] <= ((((((main_liteethmaccrc32inserter_last[15] ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
main_liteethmaccrc32inserter_next[24] <= ((((((main_liteethmaccrc32inserter_last[16] ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]);
main_liteethmaccrc32inserter_next[25] <= ((((main_liteethmaccrc32inserter_last[17] ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]);
main_liteethmaccrc32inserter_next[26] <= ((((((((main_liteethmaccrc32inserter_last[18] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]);
main_liteethmaccrc32inserter_next[27] <= ((((((((main_liteethmaccrc32inserter_last[19] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]);
main_liteethmaccrc32inserter_next[28] <= ((((((main_liteethmaccrc32inserter_last[20] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]);
main_liteethmaccrc32inserter_next[29] <= ((((((main_liteethmaccrc32inserter_last[21] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]);
main_liteethmaccrc32inserter_next[30] <= ((((main_liteethmaccrc32inserter_last[22] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]);
main_liteethmaccrc32inserter_next[31] <= ((main_liteethmaccrc32inserter_last[23] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]);
end
always @(*) begin
main_liteethmaccrc32inserter_source_valid <= 1'd0;
main_liteethmaccrc32inserter_source_first <= 1'd0;
main_liteethmaccrc32inserter_source_last <= 1'd0;
main_liteethmaccrc32inserter_source_payload_data <= 8'd0;
main_liteethmaccrc32inserter_source_payload_last_be <= 1'd0;
main_liteethmaccrc32inserter_source_payload_error <= 1'd0;
builder_liteethmaccrc32inserter_next_state <= 2'd0;
main_liteethmaccrc32inserter_data0 <= 8'd0;
main_liteethmaccrc32inserter_is_ongoing0 <= 1'd0;
main_liteethmaccrc32inserter_sink_ready <= 1'd0;
main_liteethmaccrc32inserter_is_ongoing1 <= 1'd0;
main_liteethmaccrc32inserter_ce <= 1'd0;
main_liteethmaccrc32inserter_reset <= 1'd0;
builder_liteethmaccrc32inserter_next_state <= builder_liteethmaccrc32inserter_state;
case (builder_liteethmaccrc32inserter_state)
1'd1: begin
main_liteethmaccrc32inserter_ce <= (main_liteethmaccrc32inserter_sink_valid & main_liteethmaccrc32inserter_source_ready);
main_liteethmaccrc32inserter_data0 <= main_liteethmaccrc32inserter_sink_payload_data;
main_liteethmaccrc32inserter_source_valid <= main_liteethmaccrc32inserter_sink_valid;
main_liteethmaccrc32inserter_sink_ready <= main_liteethmaccrc32inserter_source_ready;
main_liteethmaccrc32inserter_source_first <= main_liteethmaccrc32inserter_sink_first;
main_liteethmaccrc32inserter_source_last <= main_liteethmaccrc32inserter_sink_last;
main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_sink_payload_data;
main_liteethmaccrc32inserter_source_payload_last_be <= main_liteethmaccrc32inserter_sink_payload_last_be;
main_liteethmaccrc32inserter_source_payload_error <= main_liteethmaccrc32inserter_sink_payload_error;
main_liteethmaccrc32inserter_source_last <= 1'd0;
if (((main_liteethmaccrc32inserter_sink_valid & main_liteethmaccrc32inserter_sink_last) & main_liteethmaccrc32inserter_source_ready)) begin
builder_liteethmaccrc32inserter_next_state <= 2'd2;
end
end
2'd2: begin
main_liteethmaccrc32inserter_source_valid <= 1'd1;
case (main_liteethmaccrc32inserter_cnt)
1'd0: begin
main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[31:24];
end
1'd1: begin
main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[23:16];
end
2'd2: begin
main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[15:8];
end
default: begin
main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[7:0];
end
endcase
if (main_liteethmaccrc32inserter_cnt_done) begin
main_liteethmaccrc32inserter_source_last <= 1'd1;
if (main_liteethmaccrc32inserter_source_ready) begin
builder_liteethmaccrc32inserter_next_state <= 1'd0;
end
end
main_liteethmaccrc32inserter_is_ongoing1 <= 1'd1;
end
default: begin
main_liteethmaccrc32inserter_reset <= 1'd1;
main_liteethmaccrc32inserter_sink_ready <= 1'd1;
if (main_liteethmaccrc32inserter_sink_valid) begin
main_liteethmaccrc32inserter_sink_ready <= 1'd0;
builder_liteethmaccrc32inserter_next_state <= 1'd1;
end
main_liteethmaccrc32inserter_is_ongoing0 <= 1'd1;
end
endcase
end
assign main_crc32_inserter_sink_ready = ((~main_crc32_inserter_source_valid) | main_crc32_inserter_source_ready);
assign main_liteethmaccrc32checker_fifo_full = (main_liteethmaccrc32checker_syncfifo_level == 3'd4);
assign main_liteethmaccrc32checker_fifo_in = (main_liteethmaccrc32checker_sink_sink_valid & ((~main_liteethmaccrc32checker_fifo_full) | main_liteethmaccrc32checker_fifo_out));
assign main_liteethmaccrc32checker_fifo_out = (main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready);
assign main_liteethmaccrc32checker_syncfifo_sink_first = main_liteethmaccrc32checker_sink_sink_first;
assign main_liteethmaccrc32checker_syncfifo_sink_last = main_liteethmaccrc32checker_sink_sink_last;
assign main_liteethmaccrc32checker_syncfifo_sink_payload_data = main_liteethmaccrc32checker_sink_sink_payload_data;
assign main_liteethmaccrc32checker_syncfifo_sink_payload_last_be = main_liteethmaccrc32checker_sink_sink_payload_last_be;
assign main_liteethmaccrc32checker_syncfifo_sink_payload_error = main_liteethmaccrc32checker_sink_sink_payload_error;
always @(*) begin
main_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0;
main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_sink_sink_valid;
main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_fifo_in;
end
always @(*) begin
main_liteethmaccrc32checker_sink_sink_ready <= 1'd0;
main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_syncfifo_sink_ready;
main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_fifo_in;
end
assign main_liteethmaccrc32checker_source_source_valid = (main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_fifo_full);
assign main_liteethmaccrc32checker_source_source_last = main_liteethmaccrc32checker_sink_sink_last;
assign main_liteethmaccrc32checker_syncfifo_source_ready = main_liteethmaccrc32checker_fifo_out;
assign main_liteethmaccrc32checker_source_source_payload_data = main_liteethmaccrc32checker_syncfifo_source_payload_data;
assign main_liteethmaccrc32checker_source_source_payload_last_be = main_liteethmaccrc32checker_syncfifo_source_payload_last_be;
always @(*) begin
main_liteethmaccrc32checker_source_source_payload_error <= 1'd0;
main_liteethmaccrc32checker_source_source_payload_error <= main_liteethmaccrc32checker_syncfifo_source_payload_error;
main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_sink_sink_payload_error | main_liteethmaccrc32checker_crc_error);
end
assign main_liteethmaccrc32checker_error = ((main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_last) & main_liteethmaccrc32checker_crc_error);
assign main_liteethmaccrc32checker_crc_data0 = main_liteethmaccrc32checker_sink_sink_payload_data;
assign main_liteethmaccrc32checker_sink_sink_valid = main_crc32_checker_source_valid;
assign main_crc32_checker_source_ready = main_liteethmaccrc32checker_sink_sink_ready;
assign main_liteethmaccrc32checker_sink_sink_first = main_crc32_checker_source_first;
assign main_liteethmaccrc32checker_sink_sink_last = main_crc32_checker_source_last;
assign main_liteethmaccrc32checker_sink_sink_payload_data = main_crc32_checker_source_payload_data;
assign main_liteethmaccrc32checker_sink_sink_payload_last_be = main_crc32_checker_source_payload_last_be;
assign main_liteethmaccrc32checker_sink_sink_payload_error = main_crc32_checker_source_payload_error;
assign main_liteethmaccrc32checker_crc_data1 = main_liteethmaccrc32checker_crc_data0;
assign main_liteethmaccrc32checker_crc_last = main_liteethmaccrc32checker_crc_reg;
assign main_liteethmaccrc32checker_crc_value = (~{main_liteethmaccrc32checker_crc_reg[0], main_liteethmaccrc32checker_crc_reg[1], main_liteethmaccrc32checker_crc_reg[2], main_liteethmaccrc32checker_crc_reg[3], main_liteethmaccrc32checker_crc_reg[4], main_liteethmaccrc32checker_crc_reg[5], main_liteethmaccrc32checker_crc_reg[6], main_liteethmaccrc32checker_crc_reg[7], main_liteethmaccrc32checker_crc_reg[8], main_liteethmaccrc32checker_crc_reg[9], main_liteethmaccrc32checker_crc_reg[10], main_liteethmaccrc32checker_crc_reg[11], main_liteethmaccrc32checker_crc_reg[12], main_liteethmaccrc32checker_crc_reg[13], main_liteethmaccrc32checker_crc_reg[14], main_liteethmaccrc32checker_crc_reg[15], main_liteethmaccrc32checker_crc_reg[16], main_liteethmaccrc32checker_crc_reg[17], main_liteethmaccrc32checker_crc_reg[18], main_liteethmaccrc32checker_crc_reg[19], main_liteethmaccrc32checker_crc_reg[20], main_liteethmaccrc32checker_crc_reg[21], main_liteethmaccrc32checker_crc_reg[22], main_liteethmaccrc32checker_crc_reg[23], main_liteethmaccrc32checker_crc_reg[24], main_liteethmaccrc32checker_crc_reg[25], main_liteethmaccrc32checker_crc_reg[26], main_liteethmaccrc32checker_crc_reg[27], main_liteethmaccrc32checker_crc_reg[28], main_liteethmaccrc32checker_crc_reg[29], main_liteethmaccrc32checker_crc_reg[30], main_liteethmaccrc32checker_crc_reg[31]});
assign main_liteethmaccrc32checker_crc_error = (main_liteethmaccrc32checker_crc_next != 32'd3338984827);
always @(*) begin
main_liteethmaccrc32checker_crc_next <= 32'd0;
main_liteethmaccrc32checker_crc_next[0] <= (((main_liteethmaccrc32checker_crc_last[24] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
main_liteethmaccrc32checker_crc_next[1] <= (((((((main_liteethmaccrc32checker_crc_last[25] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
main_liteethmaccrc32checker_crc_next[2] <= (((((((((main_liteethmaccrc32checker_crc_last[26] ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
main_liteethmaccrc32checker_crc_next[3] <= (((((((main_liteethmaccrc32checker_crc_last[27] ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]);
main_liteethmaccrc32checker_crc_next[4] <= (((((((((main_liteethmaccrc32checker_crc_last[28] ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
main_liteethmaccrc32checker_crc_next[5] <= (((((((((((((main_liteethmaccrc32checker_crc_last[29] ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
main_liteethmaccrc32checker_crc_next[6] <= (((((((((((main_liteethmaccrc32checker_crc_last[30] ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]);
main_liteethmaccrc32checker_crc_next[7] <= (((((((((main_liteethmaccrc32checker_crc_last[31] ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]);
main_liteethmaccrc32checker_crc_next[8] <= ((((((((main_liteethmaccrc32checker_crc_last[0] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]);
main_liteethmaccrc32checker_crc_next[9] <= ((((((((main_liteethmaccrc32checker_crc_last[1] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]);
main_liteethmaccrc32checker_crc_next[10] <= ((((((((main_liteethmaccrc32checker_crc_last[2] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]);
main_liteethmaccrc32checker_crc_next[11] <= ((((((((main_liteethmaccrc32checker_crc_last[3] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]);
main_liteethmaccrc32checker_crc_next[12] <= ((((((((((((main_liteethmaccrc32checker_crc_last[4] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
main_liteethmaccrc32checker_crc_next[13] <= ((((((((((((main_liteethmaccrc32checker_crc_last[5] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]);
main_liteethmaccrc32checker_crc_next[14] <= ((((((((((main_liteethmaccrc32checker_crc_last[6] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]);
main_liteethmaccrc32checker_crc_next[15] <= ((((((((main_liteethmaccrc32checker_crc_last[7] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]);
main_liteethmaccrc32checker_crc_next[16] <= ((((((main_liteethmaccrc32checker_crc_last[8] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]);
main_liteethmaccrc32checker_crc_next[17] <= ((((((main_liteethmaccrc32checker_crc_last[9] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]);
main_liteethmaccrc32checker_crc_next[18] <= ((((((main_liteethmaccrc32checker_crc_last[10] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]);
main_liteethmaccrc32checker_crc_next[19] <= ((((main_liteethmaccrc32checker_crc_last[11] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]);
main_liteethmaccrc32checker_crc_next[20] <= ((main_liteethmaccrc32checker_crc_last[12] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]);
main_liteethmaccrc32checker_crc_next[21] <= ((main_liteethmaccrc32checker_crc_last[13] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]);
main_liteethmaccrc32checker_crc_next[22] <= ((main_liteethmaccrc32checker_crc_last[14] ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]);
main_liteethmaccrc32checker_crc_next[23] <= ((((((main_liteethmaccrc32checker_crc_last[15] ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
main_liteethmaccrc32checker_crc_next[24] <= ((((((main_liteethmaccrc32checker_crc_last[16] ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]);
main_liteethmaccrc32checker_crc_next[25] <= ((((main_liteethmaccrc32checker_crc_last[17] ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]);
main_liteethmaccrc32checker_crc_next[26] <= ((((((((main_liteethmaccrc32checker_crc_last[18] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]);
main_liteethmaccrc32checker_crc_next[27] <= ((((((((main_liteethmaccrc32checker_crc_last[19] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]);
main_liteethmaccrc32checker_crc_next[28] <= ((((((main_liteethmaccrc32checker_crc_last[20] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]);
main_liteethmaccrc32checker_crc_next[29] <= ((((((main_liteethmaccrc32checker_crc_last[21] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]);
main_liteethmaccrc32checker_crc_next[30] <= ((((main_liteethmaccrc32checker_crc_last[22] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]);
main_liteethmaccrc32checker_crc_next[31] <= ((main_liteethmaccrc32checker_crc_last[23] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]);
end
assign main_liteethmaccrc32checker_syncfifo_syncfifo_din = {main_liteethmaccrc32checker_syncfifo_fifo_in_last, main_liteethmaccrc32checker_syncfifo_fifo_in_first, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data};
assign {main_liteethmaccrc32checker_syncfifo_fifo_out_last, main_liteethmaccrc32checker_syncfifo_fifo_out_first, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = main_liteethmaccrc32checker_syncfifo_syncfifo_dout;
assign main_liteethmaccrc32checker_syncfifo_sink_ready = main_liteethmaccrc32checker_syncfifo_syncfifo_writable;
assign main_liteethmaccrc32checker_syncfifo_syncfifo_we = main_liteethmaccrc32checker_syncfifo_sink_valid;
assign main_liteethmaccrc32checker_syncfifo_fifo_in_first = main_liteethmaccrc32checker_syncfifo_sink_first;
assign main_liteethmaccrc32checker_syncfifo_fifo_in_last = main_liteethmaccrc32checker_syncfifo_sink_last;
assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data = main_liteethmaccrc32checker_syncfifo_sink_payload_data;
assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = main_liteethmaccrc32checker_syncfifo_sink_payload_last_be;
assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error = main_liteethmaccrc32checker_syncfifo_sink_payload_error;
assign main_liteethmaccrc32checker_syncfifo_source_valid = main_liteethmaccrc32checker_syncfifo_syncfifo_readable;
assign main_liteethmaccrc32checker_syncfifo_source_first = main_liteethmaccrc32checker_syncfifo_fifo_out_first;
assign main_liteethmaccrc32checker_syncfifo_source_last = main_liteethmaccrc32checker_syncfifo_fifo_out_last;
assign main_liteethmaccrc32checker_syncfifo_source_payload_data = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data;
assign main_liteethmaccrc32checker_syncfifo_source_payload_last_be = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be;
assign main_liteethmaccrc32checker_syncfifo_source_payload_error = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error;
assign main_liteethmaccrc32checker_syncfifo_syncfifo_re = main_liteethmaccrc32checker_syncfifo_source_ready;
always @(*) begin
main_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0;
if (main_liteethmaccrc32checker_syncfifo_replace) begin
main_liteethmaccrc32checker_syncfifo_wrport_adr <= (main_liteethmaccrc32checker_syncfifo_produce - 1'd1);
end else begin
main_liteethmaccrc32checker_syncfifo_wrport_adr <= main_liteethmaccrc32checker_syncfifo_produce;
end
end
assign main_liteethmaccrc32checker_syncfifo_wrport_dat_w = main_liteethmaccrc32checker_syncfifo_syncfifo_din;
assign main_liteethmaccrc32checker_syncfifo_wrport_we = (main_liteethmaccrc32checker_syncfifo_syncfifo_we & (main_liteethmaccrc32checker_syncfifo_syncfifo_writable | main_liteethmaccrc32checker_syncfifo_replace));
assign main_liteethmaccrc32checker_syncfifo_do_read = (main_liteethmaccrc32checker_syncfifo_syncfifo_readable & main_liteethmaccrc32checker_syncfifo_syncfifo_re);
assign main_liteethmaccrc32checker_syncfifo_rdport_adr = main_liteethmaccrc32checker_syncfifo_consume;
assign main_liteethmaccrc32checker_syncfifo_syncfifo_dout = main_liteethmaccrc32checker_syncfifo_rdport_dat_r;
assign main_liteethmaccrc32checker_syncfifo_syncfifo_writable = (main_liteethmaccrc32checker_syncfifo_level != 3'd5);
assign main_liteethmaccrc32checker_syncfifo_syncfifo_readable = (main_liteethmaccrc32checker_syncfifo_level != 1'd0);
always @(*) begin
main_liteethmaccrc32checker_fifo_reset <= 1'd0;
builder_liteethmaccrc32checker_next_state <= 2'd0;
main_liteethmaccrc32checker_crc_ce <= 1'd0;
main_liteethmaccrc32checker_crc_reset <= 1'd0;
builder_liteethmaccrc32checker_next_state <= builder_liteethmaccrc32checker_state;
case (builder_liteethmaccrc32checker_state)
1'd1: begin
if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin
main_liteethmaccrc32checker_crc_ce <= 1'd1;
builder_liteethmaccrc32checker_next_state <= 2'd2;
end
end
2'd2: begin
if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin
main_liteethmaccrc32checker_crc_ce <= 1'd1;
if (main_liteethmaccrc32checker_sink_sink_last) begin
builder_liteethmaccrc32checker_next_state <= 1'd0;
end
end
end
default: begin
main_liteethmaccrc32checker_crc_reset <= 1'd1;
main_liteethmaccrc32checker_fifo_reset <= 1'd1;
builder_liteethmaccrc32checker_next_state <= 1'd1;
end
endcase
end
assign main_crc32_checker_sink_ready = ((~main_crc32_checker_source_valid) | main_crc32_checker_source_ready);
assign main_ps_preamble_error_o = (main_ps_preamble_error_toggle_o ^ main_ps_preamble_error_toggle_o_r);
assign main_ps_crc_error_o = (main_ps_crc_error_toggle_o ^ main_ps_crc_error_toggle_o_r);
assign main_padding_inserter_counter_done = (main_padding_inserter_counter >= 6'd59);
always @(*) begin
main_padding_inserter_source_valid <= 1'd0;
main_padding_inserter_source_first <= 1'd0;
main_padding_inserter_source_last <= 1'd0;
main_padding_inserter_source_payload_data <= 8'd0;
main_padding_inserter_source_payload_last_be <= 1'd0;
main_padding_inserter_source_payload_error <= 1'd0;
builder_liteethmacpaddinginserter_next_state <= 1'd0;
main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 16'd0;
main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd0;
main_padding_inserter_sink_ready <= 1'd0;
builder_liteethmacpaddinginserter_next_state <= builder_liteethmacpaddinginserter_state;
case (builder_liteethmacpaddinginserter_state)
1'd1: begin
main_padding_inserter_source_valid <= 1'd1;
main_padding_inserter_source_last <= main_padding_inserter_counter_done;
main_padding_inserter_source_payload_data <= 1'd0;
if ((main_padding_inserter_source_valid & main_padding_inserter_source_ready)) begin
main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= (main_padding_inserter_counter + 1'd1);
main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1;
if (main_padding_inserter_counter_done) begin
main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0;
main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1;
builder_liteethmacpaddinginserter_next_state <= 1'd0;
end
end
end
default: begin
main_padding_inserter_source_valid <= main_padding_inserter_sink_valid;
main_padding_inserter_sink_ready <= main_padding_inserter_source_ready;
main_padding_inserter_source_first <= main_padding_inserter_sink_first;
main_padding_inserter_source_last <= main_padding_inserter_sink_last;
main_padding_inserter_source_payload_data <= main_padding_inserter_sink_payload_data;
main_padding_inserter_source_payload_last_be <= main_padding_inserter_sink_payload_last_be;
main_padding_inserter_source_payload_error <= main_padding_inserter_sink_payload_error;
if ((main_padding_inserter_source_valid & main_padding_inserter_source_ready)) begin
main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= (main_padding_inserter_counter + 1'd1);
main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1;
if (main_padding_inserter_sink_last) begin
if ((~main_padding_inserter_counter_done)) begin
main_padding_inserter_source_last <= 1'd0;
builder_liteethmacpaddinginserter_next_state <= 1'd1;
end else begin
main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0;
main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1;
end
end
end
end
endcase
end
assign main_padding_checker_source_valid = main_padding_checker_sink_valid;
assign main_padding_checker_sink_ready = main_padding_checker_source_ready;
assign main_padding_checker_source_first = main_padding_checker_sink_first;
assign main_padding_checker_source_last = main_padding_checker_sink_last;
assign main_padding_checker_source_payload_data = main_padding_checker_sink_payload_data;
assign main_padding_checker_source_payload_last_be = main_padding_checker_sink_payload_last_be;
assign main_padding_checker_source_payload_error = main_padding_checker_sink_payload_error;
always @(*) begin
main_tx_last_be_source_valid <= 1'd0;
main_tx_last_be_sink_ready <= 1'd0;
main_tx_last_be_source_first <= 1'd0;
main_tx_last_be_source_last <= 1'd0;
main_tx_last_be_source_payload_data <= 8'd0;
main_tx_last_be_source_payload_error <= 1'd0;
builder_liteethmactxlastbe_next_state <= 1'd0;
builder_liteethmactxlastbe_next_state <= builder_liteethmactxlastbe_state;
case (builder_liteethmactxlastbe_state)
1'd1: begin
main_tx_last_be_sink_ready <= 1'd1;
if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_last)) begin
builder_liteethmactxlastbe_next_state <= 1'd0;
end
end
default: begin
main_tx_last_be_source_valid <= main_tx_last_be_sink_valid;
main_tx_last_be_sink_ready <= main_tx_last_be_source_ready;
main_tx_last_be_source_first <= main_tx_last_be_sink_first;
main_tx_last_be_source_payload_data <= main_tx_last_be_sink_payload_data;
main_tx_last_be_source_payload_error <= main_tx_last_be_sink_payload_error;
main_tx_last_be_source_last <= main_tx_last_be_sink_payload_last_be;
if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin
if ((main_tx_last_be_sink_payload_last_be & (~main_tx_last_be_sink_last))) begin
builder_liteethmactxlastbe_next_state <= 1'd1;
end
end
end
endcase
end
assign main_rx_last_be_source_valid = main_rx_last_be_sink_valid;
assign main_rx_last_be_sink_ready = main_rx_last_be_source_ready;
assign main_rx_last_be_source_first = main_rx_last_be_sink_first;
assign main_rx_last_be_source_last = main_rx_last_be_sink_last;
assign main_rx_last_be_source_payload_data = main_rx_last_be_sink_payload_data;
assign main_rx_last_be_source_payload_error = main_rx_last_be_sink_payload_error;
always @(*) begin
main_rx_last_be_source_payload_last_be <= 1'd0;
main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be;
main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last;
end
assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid;
assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first;
assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last;
assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready;
always @(*) begin
main_tx_converter_converter_sink_payload_data <= 40'd0;
main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0];
main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0];
main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0];
main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8];
main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1];
main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1];
main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16];
main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2];
main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2];
main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24];
main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3];
main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3];
end
assign main_tx_converter_source_valid = main_tx_converter_source_source_valid;
assign main_tx_converter_source_first = main_tx_converter_source_source_first;
assign main_tx_converter_source_last = main_tx_converter_source_source_last;
assign main_tx_converter_source_source_ready = main_tx_converter_source_ready;
assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data;
assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid;
assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready;
assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first;
assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last;
assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data;
assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0);
assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3);
assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid;
assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first);
assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last);
assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready);
always @(*) begin
main_tx_converter_converter_source_payload_data <= 10'd0;
case (main_tx_converter_converter_mux)
1'd0: begin
main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0];
end
1'd1: begin
main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10];
end
2'd2: begin
main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20];
end
default: begin
main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30];
end
endcase
end
assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last;
assign main_rx_converter_converter_sink_valid = main_rx_converter_sink_valid;
assign main_rx_converter_converter_sink_first = main_rx_converter_sink_first;
assign main_rx_converter_converter_sink_last = main_rx_converter_sink_last;
assign main_rx_converter_sink_ready = main_rx_converter_converter_sink_ready;
assign main_rx_converter_converter_sink_payload_data = {main_rx_converter_sink_payload_error, main_rx_converter_sink_payload_last_be, main_rx_converter_sink_payload_data};
assign main_rx_converter_source_valid = main_rx_converter_source_source_valid;
assign main_rx_converter_source_first = main_rx_converter_source_source_first;
assign main_rx_converter_source_last = main_rx_converter_source_source_last;
assign main_rx_converter_source_source_ready = main_rx_converter_source_ready;
always @(*) begin
main_rx_converter_source_payload_data <= 32'd0;
main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0];
main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10];
main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20];
main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30];
end
always @(*) begin
main_rx_converter_source_payload_last_be <= 4'd0;
main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8];
main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18];
main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28];
main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38];
end
always @(*) begin
main_rx_converter_source_payload_error <= 4'd0;
main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9];
main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19];
main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29];
main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39];
end
assign main_rx_converter_source_source_valid = main_rx_converter_converter_source_valid;
assign main_rx_converter_converter_source_ready = main_rx_converter_source_source_ready;
assign main_rx_converter_source_source_first = main_rx_converter_converter_source_first;
assign main_rx_converter_source_source_last = main_rx_converter_converter_source_last;
assign main_rx_converter_source_source_payload_data = main_rx_converter_converter_source_payload_data;
assign main_rx_converter_converter_sink_ready = ((~main_rx_converter_converter_strobe_all) | main_rx_converter_converter_source_ready);
assign main_rx_converter_converter_source_valid = main_rx_converter_converter_strobe_all;
assign main_rx_converter_converter_load_part = (main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready);
assign main_tx_cdc_cdc_sink_valid = main_tx_cdc_sink_sink_valid;
assign main_tx_cdc_sink_sink_ready = main_tx_cdc_cdc_sink_ready;
assign main_tx_cdc_cdc_sink_first = main_tx_cdc_sink_sink_first;
assign main_tx_cdc_cdc_sink_last = main_tx_cdc_sink_sink_last;
assign main_tx_cdc_cdc_sink_payload_data = main_tx_cdc_sink_sink_payload_data;
assign main_tx_cdc_cdc_sink_payload_last_be = main_tx_cdc_sink_sink_payload_last_be;
assign main_tx_cdc_cdc_sink_payload_error = main_tx_cdc_sink_sink_payload_error;
assign main_tx_cdc_source_source_valid = main_tx_cdc_cdc_source_valid;
assign main_tx_cdc_cdc_source_ready = main_tx_cdc_source_source_ready;
assign main_tx_cdc_source_source_first = main_tx_cdc_cdc_source_first;
assign main_tx_cdc_source_source_last = main_tx_cdc_cdc_source_last;
assign main_tx_cdc_source_source_payload_data = main_tx_cdc_cdc_source_payload_data;
assign main_tx_cdc_source_source_payload_last_be = main_tx_cdc_cdc_source_payload_last_be;
assign main_tx_cdc_source_source_payload_error = main_tx_cdc_cdc_source_payload_error;
assign main_tx_cdc_cdc_asyncfifo_din = {main_tx_cdc_cdc_fifo_in_last, main_tx_cdc_cdc_fifo_in_first, main_tx_cdc_cdc_fifo_in_payload_error, main_tx_cdc_cdc_fifo_in_payload_last_be, main_tx_cdc_cdc_fifo_in_payload_data};
assign {main_tx_cdc_cdc_fifo_out_last, main_tx_cdc_cdc_fifo_out_first, main_tx_cdc_cdc_fifo_out_payload_error, main_tx_cdc_cdc_fifo_out_payload_last_be, main_tx_cdc_cdc_fifo_out_payload_data} = main_tx_cdc_cdc_asyncfifo_dout;
assign main_tx_cdc_cdc_sink_ready = main_tx_cdc_cdc_asyncfifo_writable;
assign main_tx_cdc_cdc_asyncfifo_we = main_tx_cdc_cdc_sink_valid;
assign main_tx_cdc_cdc_fifo_in_first = main_tx_cdc_cdc_sink_first;
assign main_tx_cdc_cdc_fifo_in_last = main_tx_cdc_cdc_sink_last;
assign main_tx_cdc_cdc_fifo_in_payload_data = main_tx_cdc_cdc_sink_payload_data;
assign main_tx_cdc_cdc_fifo_in_payload_last_be = main_tx_cdc_cdc_sink_payload_last_be;
assign main_tx_cdc_cdc_fifo_in_payload_error = main_tx_cdc_cdc_sink_payload_error;
assign main_tx_cdc_cdc_source_valid = main_tx_cdc_cdc_asyncfifo_readable;
assign main_tx_cdc_cdc_source_first = main_tx_cdc_cdc_fifo_out_first;
assign main_tx_cdc_cdc_source_last = main_tx_cdc_cdc_fifo_out_last;
assign main_tx_cdc_cdc_source_payload_data = main_tx_cdc_cdc_fifo_out_payload_data;
assign main_tx_cdc_cdc_source_payload_last_be = main_tx_cdc_cdc_fifo_out_payload_last_be;
assign main_tx_cdc_cdc_source_payload_error = main_tx_cdc_cdc_fifo_out_payload_error;
assign main_tx_cdc_cdc_asyncfifo_re = main_tx_cdc_cdc_source_ready;
assign main_tx_cdc_cdc_graycounter0_ce = (main_tx_cdc_cdc_asyncfifo_writable & main_tx_cdc_cdc_asyncfifo_we);
assign main_tx_cdc_cdc_graycounter1_ce = (main_tx_cdc_cdc_asyncfifo_readable & main_tx_cdc_cdc_asyncfifo_re);
assign main_tx_cdc_cdc_asyncfifo_writable = (((main_tx_cdc_cdc_graycounter0_q[5] == main_tx_cdc_cdc_consume_wdomain[5]) | (main_tx_cdc_cdc_graycounter0_q[4] == main_tx_cdc_cdc_consume_wdomain[4])) | (main_tx_cdc_cdc_graycounter0_q[3:0] != main_tx_cdc_cdc_consume_wdomain[3:0]));
assign main_tx_cdc_cdc_asyncfifo_readable = (main_tx_cdc_cdc_graycounter1_q != main_tx_cdc_cdc_produce_rdomain);
assign main_tx_cdc_cdc_wrport_adr = main_tx_cdc_cdc_graycounter0_q_binary[4:0];
assign main_tx_cdc_cdc_wrport_dat_w = main_tx_cdc_cdc_asyncfifo_din;
assign main_tx_cdc_cdc_wrport_we = main_tx_cdc_cdc_graycounter0_ce;
assign main_tx_cdc_cdc_rdport_adr = main_tx_cdc_cdc_graycounter1_q_next_binary[4:0];
assign main_tx_cdc_cdc_asyncfifo_dout = main_tx_cdc_cdc_rdport_dat_r;
always @(*) begin
main_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0;
if (main_tx_cdc_cdc_graycounter0_ce) begin
main_tx_cdc_cdc_graycounter0_q_next_binary <= (main_tx_cdc_cdc_graycounter0_q_binary + 1'd1);
end else begin
main_tx_cdc_cdc_graycounter0_q_next_binary <= main_tx_cdc_cdc_graycounter0_q_binary;
end
end
assign main_tx_cdc_cdc_graycounter0_q_next = (main_tx_cdc_cdc_graycounter0_q_next_binary ^ main_tx_cdc_cdc_graycounter0_q_next_binary[5:1]);
always @(*) begin
main_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0;
if (main_tx_cdc_cdc_graycounter1_ce) begin
main_tx_cdc_cdc_graycounter1_q_next_binary <= (main_tx_cdc_cdc_graycounter1_q_binary + 1'd1);
end else begin
main_tx_cdc_cdc_graycounter1_q_next_binary <= main_tx_cdc_cdc_graycounter1_q_binary;
end
end
assign main_tx_cdc_cdc_graycounter1_q_next = (main_tx_cdc_cdc_graycounter1_q_next_binary ^ main_tx_cdc_cdc_graycounter1_q_next_binary[5:1]);
assign main_rx_cdc_cdc_sink_valid = main_rx_cdc_sink_sink_valid;
assign main_rx_cdc_sink_sink_ready = main_rx_cdc_cdc_sink_ready;
assign main_rx_cdc_cdc_sink_first = main_rx_cdc_sink_sink_first;
assign main_rx_cdc_cdc_sink_last = main_rx_cdc_sink_sink_last;
assign main_rx_cdc_cdc_sink_payload_data = main_rx_cdc_sink_sink_payload_data;
assign main_rx_cdc_cdc_sink_payload_last_be = main_rx_cdc_sink_sink_payload_last_be;
assign main_rx_cdc_cdc_sink_payload_error = main_rx_cdc_sink_sink_payload_error;
assign main_rx_cdc_source_source_valid = main_rx_cdc_cdc_source_valid;
assign main_rx_cdc_cdc_source_ready = main_rx_cdc_source_source_ready;
assign main_rx_cdc_source_source_first = main_rx_cdc_cdc_source_first;
assign main_rx_cdc_source_source_last = main_rx_cdc_cdc_source_last;
assign main_rx_cdc_source_source_payload_data = main_rx_cdc_cdc_source_payload_data;
assign main_rx_cdc_source_source_payload_last_be = main_rx_cdc_cdc_source_payload_last_be;
assign main_rx_cdc_source_source_payload_error = main_rx_cdc_cdc_source_payload_error;
assign main_rx_cdc_cdc_asyncfifo_din = {main_rx_cdc_cdc_fifo_in_last, main_rx_cdc_cdc_fifo_in_first, main_rx_cdc_cdc_fifo_in_payload_error, main_rx_cdc_cdc_fifo_in_payload_last_be, main_rx_cdc_cdc_fifo_in_payload_data};
assign {main_rx_cdc_cdc_fifo_out_last, main_rx_cdc_cdc_fifo_out_first, main_rx_cdc_cdc_fifo_out_payload_error, main_rx_cdc_cdc_fifo_out_payload_last_be, main_rx_cdc_cdc_fifo_out_payload_data} = main_rx_cdc_cdc_asyncfifo_dout;
assign main_rx_cdc_cdc_sink_ready = main_rx_cdc_cdc_asyncfifo_writable;
assign main_rx_cdc_cdc_asyncfifo_we = main_rx_cdc_cdc_sink_valid;
assign main_rx_cdc_cdc_fifo_in_first = main_rx_cdc_cdc_sink_first;
assign main_rx_cdc_cdc_fifo_in_last = main_rx_cdc_cdc_sink_last;
assign main_rx_cdc_cdc_fifo_in_payload_data = main_rx_cdc_cdc_sink_payload_data;
assign main_rx_cdc_cdc_fifo_in_payload_last_be = main_rx_cdc_cdc_sink_payload_last_be;
assign main_rx_cdc_cdc_fifo_in_payload_error = main_rx_cdc_cdc_sink_payload_error;
assign main_rx_cdc_cdc_source_valid = main_rx_cdc_cdc_asyncfifo_readable;
assign main_rx_cdc_cdc_source_first = main_rx_cdc_cdc_fifo_out_first;
assign main_rx_cdc_cdc_source_last = main_rx_cdc_cdc_fifo_out_last;
assign main_rx_cdc_cdc_source_payload_data = main_rx_cdc_cdc_fifo_out_payload_data;
assign main_rx_cdc_cdc_source_payload_last_be = main_rx_cdc_cdc_fifo_out_payload_last_be;
assign main_rx_cdc_cdc_source_payload_error = main_rx_cdc_cdc_fifo_out_payload_error;
assign main_rx_cdc_cdc_asyncfifo_re = main_rx_cdc_cdc_source_ready;
assign main_rx_cdc_cdc_graycounter0_ce = (main_rx_cdc_cdc_asyncfifo_writable & main_rx_cdc_cdc_asyncfifo_we);
assign main_rx_cdc_cdc_graycounter1_ce = (main_rx_cdc_cdc_asyncfifo_readable & main_rx_cdc_cdc_asyncfifo_re);
assign main_rx_cdc_cdc_asyncfifo_writable = (((main_rx_cdc_cdc_graycounter0_q[5] == main_rx_cdc_cdc_consume_wdomain[5]) | (main_rx_cdc_cdc_graycounter0_q[4] == main_rx_cdc_cdc_consume_wdomain[4])) | (main_rx_cdc_cdc_graycounter0_q[3:0] != main_rx_cdc_cdc_consume_wdomain[3:0]));
assign main_rx_cdc_cdc_asyncfifo_readable = (main_rx_cdc_cdc_graycounter1_q != main_rx_cdc_cdc_produce_rdomain);
assign main_rx_cdc_cdc_wrport_adr = main_rx_cdc_cdc_graycounter0_q_binary[4:0];
assign main_rx_cdc_cdc_wrport_dat_w = main_rx_cdc_cdc_asyncfifo_din;
assign main_rx_cdc_cdc_wrport_we = main_rx_cdc_cdc_graycounter0_ce;
assign main_rx_cdc_cdc_rdport_adr = main_rx_cdc_cdc_graycounter1_q_next_binary[4:0];
assign main_rx_cdc_cdc_asyncfifo_dout = main_rx_cdc_cdc_rdport_dat_r;
always @(*) begin
main_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0;
if (main_rx_cdc_cdc_graycounter0_ce) begin
main_rx_cdc_cdc_graycounter0_q_next_binary <= (main_rx_cdc_cdc_graycounter0_q_binary + 1'd1);
end else begin
main_rx_cdc_cdc_graycounter0_q_next_binary <= main_rx_cdc_cdc_graycounter0_q_binary;
end
end
assign main_rx_cdc_cdc_graycounter0_q_next = (main_rx_cdc_cdc_graycounter0_q_next_binary ^ main_rx_cdc_cdc_graycounter0_q_next_binary[5:1]);
always @(*) begin
main_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0;
if (main_rx_cdc_cdc_graycounter1_ce) begin
main_rx_cdc_cdc_graycounter1_q_next_binary <= (main_rx_cdc_cdc_graycounter1_q_binary + 1'd1);
end else begin
main_rx_cdc_cdc_graycounter1_q_next_binary <= main_rx_cdc_cdc_graycounter1_q_binary;
end
end
assign main_rx_cdc_cdc_graycounter1_q_next = (main_rx_cdc_cdc_graycounter1_q_next_binary ^ main_rx_cdc_cdc_graycounter1_q_next_binary[5:1]);
assign main_tx_converter_sink_valid = main_tx_cdc_source_source_valid;
assign main_tx_cdc_source_source_ready = main_tx_converter_sink_ready;
assign main_tx_converter_sink_first = main_tx_cdc_source_source_first;
assign main_tx_converter_sink_last = main_tx_cdc_source_source_last;
assign main_tx_converter_sink_payload_data = main_tx_cdc_source_source_payload_data;
assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_source_payload_last_be;
assign main_tx_converter_sink_payload_error = main_tx_cdc_source_source_payload_error;
assign main_tx_last_be_sink_valid = main_tx_converter_source_valid;
assign main_tx_converter_source_ready = main_tx_last_be_sink_ready;
assign main_tx_last_be_sink_first = main_tx_converter_source_first;
assign main_tx_last_be_sink_last = main_tx_converter_source_last;
assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data;
assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be;
assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error;
assign main_padding_inserter_sink_valid = main_tx_last_be_source_valid;
assign main_tx_last_be_source_ready = main_padding_inserter_sink_ready;
assign main_padding_inserter_sink_first = main_tx_last_be_source_first;
assign main_padding_inserter_sink_last = main_tx_last_be_source_last;
assign main_padding_inserter_sink_payload_data = main_tx_last_be_source_payload_data;
assign main_padding_inserter_sink_payload_last_be = main_tx_last_be_source_payload_last_be;
assign main_padding_inserter_sink_payload_error = main_tx_last_be_source_payload_error;
assign main_crc32_inserter_sink_valid = main_padding_inserter_source_valid;
assign main_padding_inserter_source_ready = main_crc32_inserter_sink_ready;
assign main_crc32_inserter_sink_first = main_padding_inserter_source_first;
assign main_crc32_inserter_sink_last = main_padding_inserter_source_last;
assign main_crc32_inserter_sink_payload_data = main_padding_inserter_source_payload_data;
assign main_crc32_inserter_sink_payload_last_be = main_padding_inserter_source_payload_last_be;
assign main_crc32_inserter_sink_payload_error = main_padding_inserter_source_payload_error;
assign main_preamble_inserter_sink_valid = main_liteethmaccrc32inserter_source_valid;
assign main_liteethmaccrc32inserter_source_ready = main_preamble_inserter_sink_ready;
assign main_preamble_inserter_sink_first = main_liteethmaccrc32inserter_source_first;
assign main_preamble_inserter_sink_last = main_liteethmaccrc32inserter_source_last;
assign main_preamble_inserter_sink_payload_data = main_liteethmaccrc32inserter_source_payload_data;
assign main_preamble_inserter_sink_payload_last_be = main_liteethmaccrc32inserter_source_payload_last_be;
assign main_preamble_inserter_sink_payload_error = main_liteethmaccrc32inserter_source_payload_error;
assign main_tx_gap_inserter_sink_valid = main_preamble_inserter_source_valid;
assign main_preamble_inserter_source_ready = main_tx_gap_inserter_sink_ready;
assign main_tx_gap_inserter_sink_first = main_preamble_inserter_source_first;
assign main_tx_gap_inserter_sink_last = main_preamble_inserter_source_last;
assign main_tx_gap_inserter_sink_payload_data = main_preamble_inserter_source_payload_data;
assign main_tx_gap_inserter_sink_payload_last_be = main_preamble_inserter_source_payload_last_be;
assign main_tx_gap_inserter_sink_payload_error = main_preamble_inserter_source_payload_error;
assign main_maccore_ethphy_liteethphymiitx_sink_sink_valid = main_tx_gap_inserter_source_valid;
assign main_tx_gap_inserter_source_ready = main_maccore_ethphy_liteethphymiitx_sink_sink_ready;
assign main_maccore_ethphy_liteethphymiitx_sink_sink_first = main_tx_gap_inserter_source_first;
assign main_maccore_ethphy_liteethphymiitx_sink_sink_last = main_tx_gap_inserter_source_last;
assign main_maccore_ethphy_liteethphymiitx_sink_sink_payload_data = main_tx_gap_inserter_source_payload_data;
assign main_maccore_ethphy_liteethphymiitx_sink_sink_payload_last_be = main_tx_gap_inserter_source_payload_last_be;
assign main_maccore_ethphy_liteethphymiitx_sink_sink_payload_error = main_tx_gap_inserter_source_payload_error;
assign main_preamble_checker_sink_valid = main_maccore_ethphy_liteethphymiirx_source_source_valid;
assign main_maccore_ethphy_liteethphymiirx_source_source_ready = main_preamble_checker_sink_ready;
assign main_preamble_checker_sink_first = main_maccore_ethphy_liteethphymiirx_source_source_first;
assign main_preamble_checker_sink_last = main_maccore_ethphy_liteethphymiirx_source_source_last;
assign main_preamble_checker_sink_payload_data = main_maccore_ethphy_liteethphymiirx_source_source_payload_data;
assign main_preamble_checker_sink_payload_last_be = main_maccore_ethphy_liteethphymiirx_source_source_payload_last_be;
assign main_preamble_checker_sink_payload_error = main_maccore_ethphy_liteethphymiirx_source_source_payload_error;
assign main_crc32_checker_sink_valid = main_preamble_checker_source_valid;
assign main_preamble_checker_source_ready = main_crc32_checker_sink_ready;
assign main_crc32_checker_sink_first = main_preamble_checker_source_first;
assign main_crc32_checker_sink_last = main_preamble_checker_source_last;
assign main_crc32_checker_sink_payload_data = main_preamble_checker_source_payload_data;
assign main_crc32_checker_sink_payload_last_be = main_preamble_checker_source_payload_last_be;
assign main_crc32_checker_sink_payload_error = main_preamble_checker_source_payload_error;
assign main_padding_checker_sink_valid = main_liteethmaccrc32checker_source_source_valid;
assign main_liteethmaccrc32checker_source_source_ready = main_padding_checker_sink_ready;
assign main_padding_checker_sink_first = main_liteethmaccrc32checker_source_source_first;
assign main_padding_checker_sink_last = main_liteethmaccrc32checker_source_source_last;
assign main_padding_checker_sink_payload_data = main_liteethmaccrc32checker_source_source_payload_data;
assign main_padding_checker_sink_payload_last_be = main_liteethmaccrc32checker_source_source_payload_last_be;
assign main_padding_checker_sink_payload_error = main_liteethmaccrc32checker_source_source_payload_error;
assign main_rx_last_be_sink_valid = main_padding_checker_source_valid;
assign main_padding_checker_source_ready = main_rx_last_be_sink_ready;
assign main_rx_last_be_sink_first = main_padding_checker_source_first;
assign main_rx_last_be_sink_last = main_padding_checker_source_last;
assign main_rx_last_be_sink_payload_data = main_padding_checker_source_payload_data;
assign main_rx_last_be_sink_payload_last_be = main_padding_checker_source_payload_last_be;
assign main_rx_last_be_sink_payload_error = main_padding_checker_source_payload_error;
assign main_rx_converter_sink_valid = main_rx_last_be_source_valid;
assign main_rx_last_be_source_ready = main_rx_converter_sink_ready;
assign main_rx_converter_sink_first = main_rx_last_be_source_first;
assign main_rx_converter_sink_last = main_rx_last_be_source_last;
assign main_rx_converter_sink_payload_data = main_rx_last_be_source_payload_data;
assign main_rx_converter_sink_payload_last_be = main_rx_last_be_source_payload_last_be;
assign main_rx_converter_sink_payload_error = main_rx_last_be_source_payload_error;
assign main_rx_cdc_sink_sink_valid = main_rx_converter_source_valid;
assign main_rx_converter_source_ready = main_rx_cdc_sink_sink_ready;
assign main_rx_cdc_sink_sink_first = main_rx_converter_source_first;
assign main_rx_cdc_sink_sink_last = main_rx_converter_source_last;
assign main_rx_cdc_sink_sink_payload_data = main_rx_converter_source_payload_data;
assign main_rx_cdc_sink_sink_payload_last_be = main_rx_converter_source_payload_last_be;
assign main_rx_cdc_sink_sink_payload_error = main_rx_converter_source_payload_error;
assign main_writer_sink_sink_valid = main_sink_valid;
assign main_sink_ready = main_writer_sink_sink_ready;
assign main_writer_sink_sink_first = main_sink_first;
assign main_writer_sink_sink_last = main_sink_last;
assign main_writer_sink_sink_payload_data = main_sink_payload_data;
assign main_writer_sink_sink_payload_last_be = main_sink_payload_last_be;
assign main_writer_sink_sink_payload_error = main_sink_payload_error;
assign main_source_valid = main_reader_source_source_valid;
assign main_reader_source_source_ready = main_source_ready;
assign main_source_first = main_reader_source_source_first;
assign main_source_last = main_reader_source_source_last;
assign main_source_payload_data = main_reader_source_source_payload_data;
assign main_source_payload_last_be = main_reader_source_source_payload_last_be;
assign main_source_payload_error = main_reader_source_source_payload_error;
always @(*) begin
main_writer_inc <= 3'd0;
case (main_writer_sink_sink_payload_last_be)
1'd1: begin
main_writer_inc <= 1'd1;
end
2'd2: begin
main_writer_inc <= 2'd2;
end
3'd4: begin
main_writer_inc <= 2'd3;
end
default: begin
main_writer_inc <= 3'd4;
end
endcase
end
assign main_writer_stat_fifo_sink_payload_slot = main_writer_slot;
assign main_writer_stat_fifo_sink_payload_length = main_writer_counter;
assign main_writer_stat_fifo_source_ready = main_writer_available_clear;
assign main_writer_available_trigger = main_writer_stat_fifo_source_valid;
assign main_writer_slot_status = main_writer_stat_fifo_source_payload_slot;
assign main_writer_length_status = main_writer_stat_fifo_source_payload_length;
always @(*) begin
main_writer_memory0_we <= 1'd0;
main_writer_memory0_dat_w <= 32'd0;
main_writer_memory1_adr <= 9'd0;
main_writer_memory1_we <= 1'd0;
main_writer_memory0_adr <= 9'd0;
main_writer_memory1_dat_w <= 32'd0;
case (main_writer_slot)
1'd0: begin
main_writer_memory0_adr <= main_writer_counter[31:2];
main_writer_memory0_dat_w <= main_writer_sink_sink_payload_data;
if ((main_writer_sink_sink_valid & main_writer_ongoing)) begin
main_writer_memory0_we <= 4'd15;
end
end
1'd1: begin
main_writer_memory1_adr <= main_writer_counter[31:2];
main_writer_memory1_dat_w <= main_writer_sink_sink_payload_data;
if ((main_writer_sink_sink_valid & main_writer_ongoing)) begin
main_writer_memory1_we <= 4'd15;
end
end
endcase
end
assign main_writer_available0 = main_writer_available_status;
assign main_writer_available1 = main_writer_available_pending;
always @(*) begin
main_writer_available_clear <= 1'd0;
if ((main_writer_pending_re & main_writer_pending_r)) begin
main_writer_available_clear <= 1'd1;
end
end
assign main_writer_irq = (main_writer_pending_status & main_writer_enable_storage);
assign main_writer_available_status = main_writer_available_trigger;
assign main_writer_available_pending = main_writer_available_trigger;
assign main_writer_stat_fifo_syncfifo_din = {main_writer_stat_fifo_fifo_in_last, main_writer_stat_fifo_fifo_in_first, main_writer_stat_fifo_fifo_in_payload_length, main_writer_stat_fifo_fifo_in_payload_slot};
assign {main_writer_stat_fifo_fifo_out_last, main_writer_stat_fifo_fifo_out_first, main_writer_stat_fifo_fifo_out_payload_length, main_writer_stat_fifo_fifo_out_payload_slot} = main_writer_stat_fifo_syncfifo_dout;
assign main_writer_stat_fifo_sink_ready = main_writer_stat_fifo_syncfifo_writable;
assign main_writer_stat_fifo_syncfifo_we = main_writer_stat_fifo_sink_valid;
assign main_writer_stat_fifo_fifo_in_first = main_writer_stat_fifo_sink_first;
assign main_writer_stat_fifo_fifo_in_last = main_writer_stat_fifo_sink_last;
assign main_writer_stat_fifo_fifo_in_payload_slot = main_writer_stat_fifo_sink_payload_slot;
assign main_writer_stat_fifo_fifo_in_payload_length = main_writer_stat_fifo_sink_payload_length;
assign main_writer_stat_fifo_source_valid = main_writer_stat_fifo_syncfifo_readable;
assign main_writer_stat_fifo_source_first = main_writer_stat_fifo_fifo_out_first;
assign main_writer_stat_fifo_source_last = main_writer_stat_fifo_fifo_out_last;
assign main_writer_stat_fifo_source_payload_slot = main_writer_stat_fifo_fifo_out_payload_slot;
assign main_writer_stat_fifo_source_payload_length = main_writer_stat_fifo_fifo_out_payload_length;
assign main_writer_stat_fifo_syncfifo_re = main_writer_stat_fifo_source_ready;
always @(*) begin
main_writer_stat_fifo_wrport_adr <= 1'd0;
if (main_writer_stat_fifo_replace) begin
main_writer_stat_fifo_wrport_adr <= (main_writer_stat_fifo_produce - 1'd1);
end else begin
main_writer_stat_fifo_wrport_adr <= main_writer_stat_fifo_produce;
end
end
assign main_writer_stat_fifo_wrport_dat_w = main_writer_stat_fifo_syncfifo_din;
assign main_writer_stat_fifo_wrport_we = (main_writer_stat_fifo_syncfifo_we & (main_writer_stat_fifo_syncfifo_writable | main_writer_stat_fifo_replace));
assign main_writer_stat_fifo_do_read = (main_writer_stat_fifo_syncfifo_readable & main_writer_stat_fifo_syncfifo_re);
assign main_writer_stat_fifo_rdport_adr = main_writer_stat_fifo_consume;
assign main_writer_stat_fifo_syncfifo_dout = main_writer_stat_fifo_rdport_dat_r;
assign main_writer_stat_fifo_syncfifo_writable = (main_writer_stat_fifo_level != 2'd2);
assign main_writer_stat_fifo_syncfifo_readable = (main_writer_stat_fifo_level != 1'd0);
always @(*) begin
main_writer_start <= 1'd0;
main_writer_counter_t_next_value_ce <= 1'd0;
main_writer_ongoing <= 1'd0;
main_writer_slot_ce <= 1'd0;
main_writer_errors_status_f_next_value <= 32'd0;
main_writer_stat_fifo_sink_valid <= 1'd0;
main_writer_errors_status_f_next_value_ce <= 1'd0;
builder_liteethmacsramwriter_next_state <= 3'd0;
main_writer_counter_t_next_value <= 32'd0;
builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state;
case (builder_liteethmacsramwriter_state)
1'd1: begin
if (main_writer_sink_sink_valid) begin
if ((main_writer_counter == 11'd1530)) begin
builder_liteethmacsramwriter_next_state <= 2'd3;
end else begin
main_writer_counter_t_next_value <= (main_writer_counter + main_writer_inc);
main_writer_counter_t_next_value_ce <= 1'd1;
main_writer_ongoing <= 1'd1;
end
if (main_writer_sink_sink_last) begin
if (((main_writer_sink_sink_payload_error & main_writer_sink_sink_payload_last_be) != 1'd0)) begin
builder_liteethmacsramwriter_next_state <= 2'd2;
end else begin
builder_liteethmacsramwriter_next_state <= 3'd4;
end
end
end
end
2'd2: begin
main_writer_counter_t_next_value <= 1'd0;
main_writer_counter_t_next_value_ce <= 1'd1;
builder_liteethmacsramwriter_next_state <= 1'd0;
end
2'd3: begin
if ((main_writer_sink_sink_valid & main_writer_sink_sink_last)) begin
builder_liteethmacsramwriter_next_state <= 3'd4;
end
end
3'd4: begin
main_writer_counter_t_next_value <= 1'd0;
main_writer_counter_t_next_value_ce <= 1'd1;
main_writer_slot_ce <= 1'd1;
main_writer_stat_fifo_sink_valid <= 1'd1;
builder_liteethmacsramwriter_next_state <= 1'd0;
end
default: begin
if (main_writer_sink_sink_valid) begin
if (main_writer_stat_fifo_sink_ready) begin
main_writer_start <= 1'd1;
main_writer_ongoing <= 1'd1;
main_writer_counter_t_next_value <= (main_writer_counter + main_writer_inc);
main_writer_counter_t_next_value_ce <= 1'd1;
builder_liteethmacsramwriter_next_state <= 1'd1;
end else begin
main_writer_errors_status_f_next_value <= (main_writer_errors_status + 1'd1);
main_writer_errors_status_f_next_value_ce <= 1'd1;
builder_liteethmacsramwriter_next_state <= 2'd3;
end
end
end
endcase
end
assign main_reader_cmd_fifo_sink_valid = main_reader_start_start_re;
assign main_reader_cmd_fifo_sink_payload_slot = main_reader_slot_storage;
assign main_reader_cmd_fifo_sink_payload_length = main_reader_length_storage;
assign main_reader_ready_status = main_reader_cmd_fifo_sink_ready;
assign main_reader_level_status = main_reader_cmd_fifo_level;
always @(*) begin
main_reader_source_source_payload_last_be <= 4'd0;
if (main_reader_source_source_last) begin
case (main_reader_cmd_fifo_source_payload_length[1:0])
1'd0: begin
main_reader_source_source_payload_last_be <= 4'd8;
end
1'd1: begin
main_reader_source_source_payload_last_be <= 1'd1;
end
2'd2: begin
main_reader_source_source_payload_last_be <= 2'd2;
end
2'd3: begin
main_reader_source_source_payload_last_be <= 3'd4;
end
endcase
end
end
assign main_reader_memory0_adr = main_reader_read_address[10:2];
assign main_reader_memory1_adr = main_reader_read_address[10:2];
always @(*) begin
main_reader_source_source_payload_data <= 32'd0;
case (main_reader_cmd_fifo_source_payload_slot)
1'd0: begin
main_reader_source_source_payload_data <= main_reader_memory0_dat_r;
end
1'd1: begin
main_reader_source_source_payload_data <= main_reader_memory1_dat_r;
end
endcase
end
assign main_reader_event00 = main_reader_eventsourcepulse_status;
assign main_reader_event01 = main_reader_eventsourcepulse_pending;
always @(*) begin
main_reader_eventsourcepulse_clear <= 1'd0;
if ((main_reader_pending_re & main_reader_pending_r)) begin
main_reader_eventsourcepulse_clear <= 1'd1;
end
end
assign main_reader_irq = (main_reader_pending_status & main_reader_enable_storage);
assign main_reader_eventsourcepulse_status = 1'd0;
assign main_reader_cmd_fifo_syncfifo_din = {main_reader_cmd_fifo_fifo_in_last, main_reader_cmd_fifo_fifo_in_first, main_reader_cmd_fifo_fifo_in_payload_length, main_reader_cmd_fifo_fifo_in_payload_slot};
assign {main_reader_cmd_fifo_fifo_out_last, main_reader_cmd_fifo_fifo_out_first, main_reader_cmd_fifo_fifo_out_payload_length, main_reader_cmd_fifo_fifo_out_payload_slot} = main_reader_cmd_fifo_syncfifo_dout;
assign main_reader_cmd_fifo_sink_ready = main_reader_cmd_fifo_syncfifo_writable;
assign main_reader_cmd_fifo_syncfifo_we = main_reader_cmd_fifo_sink_valid;
assign main_reader_cmd_fifo_fifo_in_first = main_reader_cmd_fifo_sink_first;
assign main_reader_cmd_fifo_fifo_in_last = main_reader_cmd_fifo_sink_last;
assign main_reader_cmd_fifo_fifo_in_payload_slot = main_reader_cmd_fifo_sink_payload_slot;
assign main_reader_cmd_fifo_fifo_in_payload_length = main_reader_cmd_fifo_sink_payload_length;
assign main_reader_cmd_fifo_source_valid = main_reader_cmd_fifo_syncfifo_readable;
assign main_reader_cmd_fifo_source_first = main_reader_cmd_fifo_fifo_out_first;
assign main_reader_cmd_fifo_source_last = main_reader_cmd_fifo_fifo_out_last;
assign main_reader_cmd_fifo_source_payload_slot = main_reader_cmd_fifo_fifo_out_payload_slot;
assign main_reader_cmd_fifo_source_payload_length = main_reader_cmd_fifo_fifo_out_payload_length;
assign main_reader_cmd_fifo_syncfifo_re = main_reader_cmd_fifo_source_ready;
always @(*) begin
main_reader_cmd_fifo_wrport_adr <= 1'd0;
if (main_reader_cmd_fifo_replace) begin
main_reader_cmd_fifo_wrport_adr <= (main_reader_cmd_fifo_produce - 1'd1);
end else begin
main_reader_cmd_fifo_wrport_adr <= main_reader_cmd_fifo_produce;
end
end
assign main_reader_cmd_fifo_wrport_dat_w = main_reader_cmd_fifo_syncfifo_din;
assign main_reader_cmd_fifo_wrport_we = (main_reader_cmd_fifo_syncfifo_we & (main_reader_cmd_fifo_syncfifo_writable | main_reader_cmd_fifo_replace));
assign main_reader_cmd_fifo_do_read = (main_reader_cmd_fifo_syncfifo_readable & main_reader_cmd_fifo_syncfifo_re);
assign main_reader_cmd_fifo_rdport_adr = main_reader_cmd_fifo_consume;
assign main_reader_cmd_fifo_syncfifo_dout = main_reader_cmd_fifo_rdport_dat_r;
assign main_reader_cmd_fifo_syncfifo_writable = (main_reader_cmd_fifo_level != 2'd2);
assign main_reader_cmd_fifo_syncfifo_readable = (main_reader_cmd_fifo_level != 1'd0);
always @(*) begin
main_reader_source_source_last <= 1'd0;
builder_liteethmacsramreader_next_state <= 2'd0;
main_reader_counter_next_value <= 11'd0;
main_reader_read_address <= 11'd0;