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a2d391dcae decode2: Reduce metavalue warnings Paul Mackerras 2022-08-12 19:46:45 +1000
4fcc2500c2 core_debug: Reduce metavalue warnings Paul Mackerras 2022-08-12 19:46:09 +1000
221a7b3df0 icache: Reduce metavalue warnings Paul Mackerras 2022-08-12 19:42:35 +1000
6fe9dc9640 dcache: Reduce metavalue warnings Paul Mackerras 2022-08-12 19:38:16 +1000
ff63ffdbfd

Merge pull request #382 from paulusmack/master Michael Neuling 2022-08-10 15:33:15 +1000
0073d23e73

Merge pull request #392 from paulusmack/fix-branch-alias Michael Neuling 2022-08-10 12:43:29 +1000
20f49f06f8 multiply_tb: Fix multiply_tb.vhdl for the new multiplier interface #382 Paul Mackerras 2022-08-10 12:03:36 +1000
b0aa5340b8 execute1: Make it clear that divide logic is not included when HAS_FPU=true Paul Mackerras 2022-08-10 11:33:10 +1000
d1e8e62fee Remove option for "short" 16x16 bit multiplier Paul Mackerras 2022-07-19 12:29:47 +1000
f093e30a64 Merge branch 'fix-branch-alias' into branch-alias #392 Michael Neuling 2022-08-10 10:29:59 +1000
b9efc9a608

Merge pull request #388 from antonblanchard/trace-test Michael Neuling 2022-08-10 10:25:59 +1000
769f5c3a53 fetch1: Fix bug where BTC entries don't match on MSR[IR] Paul Mackerras 2022-08-10 10:13:50 +1000
e02d8060ed Change the multiplier interface to support signed multipliers Paul Mackerras 2022-08-08 22:26:39 +1000
25f93fc17e Add branch alias test branch-alias Anton Blanchard 2022-08-09 20:32:52 +1000
af9fe3467c xilinx_mult: Prepare for doing signed multiplication Paul Mackerras 2022-08-08 17:06:46 +1000
595a758400 execute1: Add a pipelined 33-bit signed multiplier Paul Mackerras 2022-07-16 11:49:28 +1000
58e799b350 predecode: Add more comments to row_predecode_rom and insn_code values Paul Mackerras 2022-08-04 15:25:06 +1000
6db626d245 icache: Log 36 bits of instruction rather than 32 Paul Mackerras 2022-08-04 15:17:25 +1000
30f6574135 predecode: Work around apparent yosys/nextpnr bug Paul Mackerras 2022-08-04 14:57:12 +1000
21ab36a0c0 Pre-decode instructions when writing them to icache Paul Mackerras 2022-07-29 20:29:26 +1000
26dc1e879c Eliminate use of primary opcode outside of decode1 Paul Mackerras 2022-07-28 20:28:41 +1000
c9aea45ffe decode1: Divide insn_code values into ranges to indicate register usage Paul Mackerras 2022-07-28 19:00:04 +1000
c3ee10f013 decode1: Split instruction decoding into two steps Paul Mackerras 2022-07-26 18:21:19 +1000
5380d80039 decode1: Use block RAMs in decode Paul Mackerras 2022-07-26 14:55:29 +1000
47895f8aff decode2: Decode unit and single-pipe attributes for mfspr/mtspr in decode2 Paul Mackerras 2022-07-30 09:42:19 +1000
09965b9102 FPU: Set sign of 0 result of subtraction in pack_dp Paul Mackerras 2022-05-27 22:23:50 +1000
932da4c114 FPU: Simplify IDLE state code Paul Mackerras 2022-05-21 19:36:17 +1000
8da05e5331 FPU: Make an explicit exponent data path Paul Mackerras 2022-05-14 21:46:40 +1000
03ca9b5dd5 FPU: Minor fix and simplifications Paul Mackerras 2022-05-14 11:59:14 +1000
7a60c118ed loadstore1: Simplify address generation in OP_FETCH_FAILED case Paul Mackerras 2022-07-29 08:27:10 +1000
795b6e2a6b Remove leftover logic for 16-byte loads and stores Paul Mackerras 2022-07-28 20:46:59 +1000
fc58559ee8 writeback: Eliminate unintentional inferred latch Paul Mackerras 2022-08-09 19:48:30 +1000
2562053af3

Merge pull request #390 from shenki/fix-whide-warnings Michael Neuling 2022-08-09 16:23:37 +1000
3c9b3c39ae

Merge pull request #389 from paulusmack/fix-sc Anton Blanchard 2022-08-09 14:15:56 +1000
3c27abcc40 tests/trace: Test trace vs system call interrupt #388 trace-test Anton Blanchard 2022-08-09 07:08:02 +1000
939c7e39dd execute1: Fix trace interrupt on sc instruction #389 Paul Mackerras 2022-08-09 12:30:48 +1000
dc6a4b1406 soc: Fix -Whide warning #390 Joel Stanley 2022-08-08 20:24:54 +0930
c6ca844c88 xics: Fix -Whide warnings Joel Stanley 2022-08-08 20:21:27 +0930
60c54fb959 fpu: Fix -Whide warnings Joel Stanley 2022-08-05 15:12:45 +0930
2641e6d5cd

Merge pull request #387 from antonblanchard/gitignore Michael Neuling 2022-08-08 15:54:14 +1000
ad37b2e07c Add litesdcard/build to gitignore #387 gitignore Anton Blanchard 2022-08-07 17:44:04 +1000
a2c9c9b3cf

Merge pull request #384 from antonblanchard/litedram-update Paul Mackerras 2022-08-05 10:52:31 +1000
aa1d2b16d7 litedram: Regenerate #384 litedram-update Anton Blanchard 2022-08-04 21:26:17 +1000
89ce8a8b17 liteeth: Regenerate #385 liteeth-update Anton Blanchard 2022-08-04 21:29:36 +1000
e0bf743d7a litedram: MIGEN_GIT_SHA1 no longer defined Anton Blanchard 2022-08-04 21:25:13 +1000
2ca21ebcae

Merge pull request #383 from antonblanchard/fix-sdcard Paul Mackerras 2022-08-04 19:35:52 +1000
83fe8b629c litesdcard: Fix and regenerate Verilog #383 fix-sdcard Anton Blanchard 2022-08-04 18:24:56 +1000
76a7b98840

Merge pull request #381 from shingarov/gitignore-artifacts Paul Mackerras 2022-08-01 15:53:01 +1000
de8fd492c8

Merge pull request #378 from mikey/ux-cleanup Paul Mackerras 2022-08-01 15:52:33 +1000
8e234ddb5a Gitignore build artifacts #381 Boris Shingarov 2022-07-29 03:47:56 -0400
eeac86c9d8 test: Add test for metavalues #378 Michael Neuling 2022-07-28 15:29:25 +1000
72fcca8e52 tests: Update FPU test output Michael Neuling 2022-07-28 15:28:25 +1000
f34b2488e4 tests: Minor script cleanups Michael Neuling 2022-07-28 14:47:51 +1000
438a76dafd Metavalue cleanup for register_file.vhdl Michael Neuling 2022-07-14 10:32:37 +1000
7a3e5cac3b Metavalue cleanup for pmu.vhdl Michael Neuling 2022-07-14 10:32:37 +1000
43e62dbd9e Metavalue cleanup for rotator.vhdl Michael Neuling 2022-07-14 10:32:37 +1000
5a03de4c90 Metavalue cleanup for mmu.vhdl Michael Neuling 2022-07-14 10:32:16 +1000
738702f2e2 Metavalue cleanup for loadstore1.vhdl Michael Neuling 2022-07-14 10:32:05 +1000
404abefd92 Metavalue cleanup for icache.vhdl Michael Neuling 2022-07-14 10:31:53 +1000
43dadca052 Metavalue cleanup for fpu.vhdl Michael Neuling 2022-07-14 10:31:43 +1000
9e134f2e2f Metavalue cleanup for fetch1.vhdl Michael Neuling 2022-07-14 10:31:32 +1000
e440db13d7 Metavalue cleanup for execute1.vhdl Michael Neuling 2022-07-14 10:31:20 +1000
602ba25c70 Metavalue cleanup for decoder1.vhdl Michael Neuling 2022-07-14 10:30:57 +1000
7656abd765 Metavalue cleanup for helpers.vhdl Michael Neuling 2022-07-14 10:29:11 +1000
caf458be37 Metavalue cleanup for common.vhdl Michael Neuling 2022-07-28 09:50:26 +1000
281a125f1f

Merge pull request #379 from paulusmack/master Michael Neuling 2022-07-26 10:08:33 +1000
bad9a9a2e8

Merge pull request #380 from iagocaran/master Michael Neuling 2022-07-25 16:31:12 +1000
a060ad5085 tests/pmu: Cleanup whitespace in pmc.c #380 Michael Neuling 2022-07-25 15:03:40 +1000
d6121cd636 Use register addresses from decode1 for dependency tracking #379 Paul Mackerras 2022-07-14 15:47:21 +1000
1d7de2f1da register_file: Make read access to register file synchronous Paul Mackerras 2022-02-22 09:30:05 +1100
06c13d4988 decode1: Work out register addresses in decode1 Paul Mackerras 2022-02-21 19:29:09 +1100
047be5c0c3 loadstore1: Do SPR reading in stage 2 rather than stage 3 Paul Mackerras 2022-03-23 18:02:28 +0000
af814a0d5e Provide debug access to SPRs in loadstore1 and mmu Paul Mackerras 2022-02-24 11:37:17 +1100
d0f319290f Restore debug access to SPRs Paul Mackerras 2022-02-25 16:46:34 +1100
fdb3ef6874 Finish off taking SPRs out of register file Paul Mackerras 2022-02-19 19:03:49 +1100
337b104250 Move LR, CTR and TAR out of the register file Paul Mackerras 2022-07-12 11:20:17 +1000
bc4d02cb0d Start removing SPRs from register file Paul Mackerras 2022-07-12 08:52:05 +1000
73cc5167ec Use FPU for division instructions if we have an FPU Paul Mackerras 2022-05-09 19:18:42 +1000
34330552e8 FPU: Add logic for 32-bit integer division Paul Mackerras 2022-05-07 22:34:23 +1000
a95f8aab38 FPU: Add integer division logic to FPU Paul Mackerras 2022-05-07 18:28:33 +1000
23d5c4edc5 FPU: Convert internal R, A, B, and C registers to 8.56 format Paul Mackerras 2022-05-02 09:39:26 +1000
d1850fea29 Track hazards explicitly for XER overflow bits Paul Mackerras 2022-07-09 18:29:48 +1000
7c240a664b fetch1: Fix debug stop again Paul Mackerras 2022-07-09 13:17:18 +1000
e598c2aef8 control: Reimplement serialization using tags Paul Mackerras 2022-07-09 11:55:13 +1000
2da08bcf2e decode1: Remove stash buffer Paul Mackerras 2022-07-08 16:37:12 +1000
2f45e545ed decode2: Rework to make the stall_out signal come from a register Paul Mackerras 2022-07-08 14:07:28 +1000
c9e838b656 Remove support for lq, stq, lqarx and stqcx. Paul Mackerras 2022-06-04 17:37:48 +1000
0bd1e24024 decode2: Rename 'r' to 'dc2' Paul Mackerras 2022-07-04 18:23:03 +1000
ebe1caab85 decode1: Reduce number of single-issue instructions Paul Mackerras 2022-07-02 22:23:35 +1000
9a8a8e50f8 FPU: Add stage-2 stall ability to FPU Paul Mackerras 2022-07-02 14:17:18 +1000
ef122868d5 Do CR0 setting for Rc=1 instructions in execute2 instead of writeback Paul Mackerras 2022-06-28 18:18:08 +1000
e030a500e8 Allow integer instructions and load/store instructions to execute together Paul Mackerras 2022-06-27 18:53:04 +1000
4b6148ada6 Add a bypass path from the execute2 stage Paul Mackerras 2022-06-28 08:40:42 +1000
3510071d9a Add a second execute stage to the pipeline Paul Mackerras 2022-06-30 20:33:33 +1000
521a5403a9 execute1: Rename 'r' to 'ex1' Paul Mackerras 2022-06-18 17:29:43 +1000
813e2317bf execute1: Restructure to separate out execution of side effects Paul Mackerras 2022-06-18 16:24:30 +1000
de1bf10114 tests/pmu: Add load/store completed, instruction count and cycle count tests Iago Caran Aquino 2022-07-19 17:24:14 -0300
204fedc63f Move XER low bits out of register file Paul Mackerras 2022-06-29 20:02:36 +1000
bdd4d04162 Simplify flow control in the dcache and loadstore units Paul Mackerras 2022-06-11 19:20:57 +1000
5d008f2f20

Merge 4e3cf62f5b into 35e0dbed34 #187 Joel Stanley 2022-06-17 08:08:35 +0800