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caravel-mpw7-20221125
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trace-test
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litedram-update
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fix-sdcard
fpu-init
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core_debug-init
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fpu-typo
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caravel-mpw6-20220530
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log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
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orange-crab-freq
dcache-nc-fix
remove-potato-uart
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jtag-port-2
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Commit Graph

5 Commits (f705fc5e197b746e2f3103f8ac4e2abc8f8b8696)

Author SHA1 Message Date
Paul Mackerras 3fb0a9ed26 litedram: Update generated code 
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 2 weeks ago
Paul Mackerras 14359affbb litedram: Regenerate gateware and software from recent upstream litedram 
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 11 months ago
Matt Johnston 89d8cf0788 Regenerate litedram with updated sdram init 
Using

litedram c770dd62edc281c370f9e2c694fe4ac1525a0b4a
litex e570b612b2a9d8f8d2002d79497bda0dc35b936a

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
 2 years ago
Anton Blanchard aa1d2b16d7 litedram: Regenerate 
Regenerate from upstream litex. Something in the update has improved
memory read and write performance quite a lot on my Nexys Video:

Before:

  Write speed: 83.2MiB/s
   Read speed: 140.4MiB/s

After:

  Write speed: 352.1MiB/s
   Read speed: 218.5MiB/s

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Matt Johnston 8901e84d8d litedram: Add orangecrab-85-0.2 target 
Parameters are based on
https://github.com/gregdavill/OrangeCrab-test-sw/blob/main/hw/OrangeCrab-bitstream.py
and litex-boards orangecrab.py

rtt_nom and cmd_delay are overridden for OrangeCrab, we do the same here.

Generated with litedram and litex
62abf9c ("litedram_gen: Add block_until_ready port parameter to control blocking behaviour.")
add2746a ("tools/litex_cli: Rename wb to bus.")

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
 3 years ago