Commit Graph

1 Commits (047be5c0c3b2f12c9321412518e17b7267fe14ea)

Author SHA1 Message Date
Benjamin Herrenschmidt a3857aac94 litedram: Add an L2 cache with store queue
This adds a cache between the wishbone and litedram with the following
features (at this point, it's still evolving)

  - 128 bytes line width in order to have a reasonable amount of
litedram pipelining on the 128-bit wide data port.

  - Configurable geometry otherwise

  - Stores are acked immediately on wishbone whether hit or miss
(minus a 2 cycles delay if there's a previous load response in the
way) and sent to LiteDRAM via 8 entries (configurable) store queue

Signed-off-by: Benjamin Herrenschmidt <>
4 years ago