From 0254e406856bcf1d8756fb8ea40e33767e34cbe6 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Mon, 9 Sep 2019 13:03:27 +1000 Subject: [PATCH] Fix issues with CR rework It simulated fine, but didn't synthesize. Fix some obvious issues to get us going again. Fixes: 9fbaea6f0819 ("Rework CR file and add forwarding") Signed-off-by: Anton Blanchard --- common.vhdl | 1 - cr_file.vhdl | 16 ++++++++-------- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/common.vhdl b/common.vhdl index 1c4a8f7..6c0963f 100644 --- a/common.vhdl +++ b/common.vhdl @@ -51,7 +51,6 @@ package common is output_carry: std_ulogic; input_cr: std_ulogic; output_cr: std_ulogic; - input_cr_data: std_ulogic_vector(31 downto 0); end record; constant Decode2ToExecute1Init : Decode2ToExecute1Type := (valid => '0', insn_type => OP_ILLEGAL, lr => '0', rc => '0', input_carry => '0', output_carry => '0', input_cr => '0', output_cr => '0', others => (others => '0')); diff --git a/cr_file.vhdl b/cr_file.vhdl index bf1378e..51b348e 100644 --- a/cr_file.vhdl +++ b/cr_file.vhdl @@ -22,14 +22,19 @@ architecture behaviour of cr_file is begin cr_create_0: process(all) variable hi, lo : integer := 0; + variable cr_tmp : std_ulogic_vector(31 downto 0) := (others => '0'); begin + cr_tmp := crs; + for i in 0 to 7 loop if w_in.write_cr_mask(i) = '1' then lo := i*4; hi := lo + 3; - crs_updated(hi downto lo) <= w_in.write_cr_data(hi downto lo); + cr_tmp(hi downto lo) := w_in.write_cr_data(hi downto lo); end if; end loop; + + crs_updated <= cr_tmp; end process; -- synchronous writes @@ -38,23 +43,18 @@ begin if rising_edge(clk) then if w_in.write_cr_enable = '1' then report "Writing " & to_hstring(w_in.write_cr_data) & " to CR mask " & to_hstring(w_in.write_cr_mask); - crs <= crs_updated; end if; + crs <= crs_updated; end if; end process; -- asynchronous reads cr_read_0: process(all) - variable hi, lo : integer := 0; begin -- just return the entire CR to make mfcrf easier for now if d_in.read = '1' then report "Reading CR " & to_hstring(crs_updated); end if; - if w_in.write_cr_enable then - d_out.read_cr_data <= crs_updated; - else - d_out.read_cr_data <= crs; - end if; + d_out.read_cr_data <= crs; end process; end architecture behaviour;