From f124dc4a4099eb666f8f99d82ad5331d66ac1ebf Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 8 May 2020 11:40:39 +1000 Subject: [PATCH 01/16] xics: Add missing fusesoc core file Signed-off-by: Benjamin Herrenschmidt --- microwatt.core | 1 + 1 file changed, 1 insertion(+) diff --git a/microwatt.core b/microwatt.core index a2d6ab5..0d8531e 100644 --- a/microwatt.core +++ b/microwatt.core @@ -45,6 +45,7 @@ filesets: - wishbone_debug_master.vhdl - wishbone_bram_wrapper.vhdl - soc.vhdl + - xics.vhdl file_type : vhdlSource-2008 fpga: From 0f97b320f6c997494772f5a3e8adb867e28c148c Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Mon, 30 Sep 2019 14:07:16 +1000 Subject: [PATCH 02/16] Change default frequency to 100Mhz LiteDRAM at the moment pretty much enforces 100Mhz, and our software isn't quite yet adaptable, so switch out default to 100Mhz accross the board. Recent timing improvements should make it a non-issue. Signed-off-by: Benjamin Herrenschmidt --- microwatt.core | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/microwatt.core b/microwatt.core index 0d8531e..0558470 100644 --- a/microwatt.core +++ b/microwatt.core @@ -187,7 +187,7 @@ parameters: datatype : int description : Generated system clock frequency in HZ (for top-generic based boards) paramtype : generic - default : 50000000 + default : 100000000 disable_flatten_core: datatype : bool From 3687486d366a50ec19e9437e4332f857d96b7158 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 30 Apr 2020 17:52:11 +1000 Subject: [PATCH 03/16] Update hello_world for 100Mhz clock Signed-off-by: Benjamin Herrenschmidt --- fpga/hello_world.hex | 24 +----------------------- hello_world/console.c | 2 +- 2 files changed, 2 insertions(+), 24 deletions(-) diff --git a/fpga/hello_world.hex b/fpga/hello_world.hex index 0de746a..6bbe412 100644 --- a/fpga/hello_world.hex +++ b/fpga/hello_world.hex @@ -516,7 +516,7 @@ e8010010ebc1fff0 3d20c0003842a000 6129200060000000 f922800079290020 -3940001a3d20c000 +394000353d20c000 7929002061292018 4e800020f9490000 0000000000000000 @@ -562,25 +562,3 @@ f80100103bff7190 0000018001000000 6f57206f6c6c6548 0000000a0d646c72 -0000000000000010 -0141780400527a01 -0000001000010c1b -fffffe5800000018 -0000000000000040 -0000002c00000010 -00000038fffffe84 -0000001000000000 -fffffea800000040 -0000000000000034 -0000005400000028 -00000050fffffec8 -9f029e0041094500 -437e4111300e4401 -4106dedf41000e0a -000000100000000b -fffffeec00000080 -000000000000002c -000000940000001c -00000054ffffff04 -44019f0041094400 -0000007e4111300e diff --git a/hello_world/console.c b/hello_world/console.c index 9abd6b9..4069244 100644 --- a/hello_world/console.c +++ b/hello_world/console.c @@ -9,7 +9,7 @@ static uint64_t potato_uart_base; -#define PROC_FREQ 50000000 +#define PROC_FREQ 100000000 #define UART_FREQ 115200 #define UART_BASE 0xc0002000 From fa50df56ef572aa23b1aaa58cc4d8f9fb32086df Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Mon, 4 May 2020 22:16:22 +1000 Subject: [PATCH 04/16] mw_debug: Fix core reset mw_debug creset would poke the START bit instead of the RESET bit Signed-off-by: Benjamin Herrenschmidt --- scripts/mw_debug/mw_debug.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/mw_debug/mw_debug.c b/scripts/mw_debug/mw_debug.c index f1a7cab..7bcf4f9 100644 --- a/scripts/mw_debug/mw_debug.c +++ b/scripts/mw_debug/mw_debug.c @@ -392,7 +392,7 @@ static void core_start(void) static void core_reset(void) { - check(dmi_write(DBG_CORE_CTRL, DBG_CORE_CTRL_START), "resetting core"); + check(dmi_write(DBG_CORE_CTRL, DBG_CORE_CTRL_RESET), "resetting core"); } static void core_step(void) From 31b55b2a75cd439a00c5eeb3f246e4c2805137ed Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 8 May 2020 11:36:37 +1000 Subject: [PATCH 05/16] core: Improve core reset The icache would still spit out an instruction which could cause a 0x700 instead of a reset. Signed-off-by: Benjamin Herrenschmidt --- control.vhdl | 13 +++++++------ fetch2.vhdl | 1 + icache.vhdl | 2 +- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/control.vhdl b/control.vhdl index 064ff98..55f5649 100644 --- a/control.vhdl +++ b/control.vhdl @@ -159,6 +159,13 @@ begin v_int.outstanding := r_int.outstanding - 1; end if; + if rst = '1' then + v_int.state := IDLE; + v_int.outstanding := 0; + stall_tmp := '0'; + valid_tmp := '0'; + end if; + -- Handle debugger stop stopped_out <= '0'; if stop_mark_in = '1' and v_int.outstanding = 0 then @@ -228,12 +235,6 @@ begin cr_write_valid <= '0'; end if; - if rst = '1' then - v_int.state := IDLE; - v_int.outstanding := 0; - stall_tmp := '0'; - end if; - -- update outputs valid_out <= valid_tmp; stall_out <= stall_tmp; diff --git a/fetch2.vhdl b/fetch2.vhdl index 99f92ee..5474ca6 100644 --- a/fetch2.vhdl +++ b/fetch2.vhdl @@ -105,6 +105,7 @@ begin -- Clear stash on reset if rst = '1' then v_int.stash_valid := '0'; + v.valid := '0'; end if; -- Update registers diff --git a/icache.vhdl b/icache.vhdl index 343c73a..3eaf548 100644 --- a/icache.vhdl +++ b/icache.vhdl @@ -385,7 +385,7 @@ begin end loop; -- Generate the "hit" and "miss" signals for the synchronous blocks - req_is_hit <= i_in.req and is_hit and not flush_in; + req_is_hit <= i_in.req and is_hit and not flush_in and not rst; req_is_miss <= i_in.req and not is_hit and not flush_in; req_hit_way <= hit_way; From 982cf166ddded32ce9a3cd156cea96e69ab85a38 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 10 Sep 2019 18:05:32 +0100 Subject: [PATCH 06/16] litedram: Add basic support for LiteX LiteDRAM This comes in two parts: - A generator script which uses LiteX to generate litedram cores along with their init files for various boards (currently Arty and Nexys-video). This comes with configs for arty and nexys_video. - A fusesoc "generator" which uses pre-generated litedram cores The generation process is manual on purpose. This include pre-generated cores for the two above boards. This is done so that one doesn't have to install LiteX to build microwatt. In addition, the generator script or wrapper vhdl tend to break when LiteX changes significantly which happens. This is still rather standalone and hasn't been plumbed into the SoC or the FPGA toplevel files yet. At this point LiteDRAM self-initializes using a built-in VexRiscv "Minimum" core obtained from LiteX and included in this commit. There is some plumbing to generate and cores that are initialized by Microwatt directly but this isn't working yet and so isn't enabled yet. Signed-off-by: Benjamin Herrenschmidt --- Makefile | 14 +- litedram/extras/VexRiscv.v | 3967 +++ litedram/extras/fusesoc-add-files.py | 45 + litedram/gen-src/arty.yml | 42 + litedram/gen-src/generate.py | 150 + litedram/gen-src/nexys-video.yml | 42 + litedram/gen-src/sdram_init/Makefile | 75 + litedram/gen-src/sdram_init/bin2hex.py | 17 + litedram/gen-src/sdram_init/head.S | 102 + litedram/gen-src/sdram_init/include/system.h | 3 + .../gen-src/sdram_init/libc/include/assert.h | 29 + .../sdram_init/libc/include/compiler.h | 54 + .../gen-src/sdram_init/libc/include/ctype.h | 26 + .../gen-src/sdram_init/libc/include/errno.h | 36 + .../gen-src/sdram_init/libc/include/stdint.h | 30 + .../gen-src/sdram_init/libc/include/stdio.h | 35 + .../gen-src/sdram_init/libc/include/stdlib.h | 25 + .../gen-src/sdram_init/libc/include/string.h | 45 + .../gen-src/sdram_init/libc/include/unistd.h | 26 + .../gen-src/sdram_init/libc/src/isdigit.c | 26 + .../gen-src/sdram_init/libc/src/isprint.c | 19 + .../gen-src/sdram_init/libc/src/isspace.c | 30 + .../gen-src/sdram_init/libc/src/isxdigit.c | 22 + litedram/gen-src/sdram_init/libc/src/memchr.c | 28 + litedram/gen-src/sdram_init/libc/src/memcmp.c | 29 + litedram/gen-src/sdram_init/libc/src/memcpy.c | 36 + .../gen-src/sdram_init/libc/src/memmove.c | 36 + litedram/gen-src/sdram_init/libc/src/memset.c | 40 + .../gen-src/sdram_init/libc/src/strcasecmp.c | 27 + litedram/gen-src/sdram_init/libc/src/strcat.c | 26 + litedram/gen-src/sdram_init/libc/src/strchr.c | 28 + litedram/gen-src/sdram_init/libc/src/strcmp.c | 25 + litedram/gen-src/sdram_init/libc/src/strcpy.c | 23 + litedram/gen-src/sdram_init/libc/src/strlen.c | 40 + .../gen-src/sdram_init/libc/src/strncasecmp.c | 30 + .../gen-src/sdram_init/libc/src/strncmp.c | 30 + .../gen-src/sdram_init/libc/src/strncpy.c | 33 + .../gen-src/sdram_init/libc/src/strrchr.c | 28 + litedram/gen-src/sdram_init/libc/src/strstr.c | 39 + litedram/gen-src/sdram_init/libc/src/strtok.c | 48 + litedram/gen-src/sdram_init/libc/src/strtol.c | 113 + .../gen-src/sdram_init/libc/src/strtoul.c | 103 + .../gen-src/sdram_init/libc/src/tolower.c | 19 + .../gen-src/sdram_init/libc/src/toupper.c | 21 + .../gen-src/sdram_init/libc/src/vsnprintf.c | 304 + litedram/gen-src/sdram_init/main.c | 162 + litedram/gen-src/sdram_init/sdram_init.lds | 12 + litedram/gen-src/wrapper-mw-init.vhdl | 303 + litedram/gen-src/wrapper-self-init.vhdl | 214 + litedram/generated/arty/init-cpu.txt | 1 + litedram/generated/arty/litedram-wrapper.vhdl | 214 + litedram/generated/arty/litedram_core.init | 5817 +++++ litedram/generated/arty/litedram_core.v | 19893 +++++++++++++++ litedram/generated/nexys-video/init-cpu.txt | 1 + .../nexys-video/litedram-wrapper.vhdl | 214 + .../generated/nexys-video/litedram_core.init | 5817 +++++ .../generated/nexys-video/litedram_core.v | 19915 ++++++++++++++++ litedram/litedram.core | 15 + microwatt.core | 9 + scripts/mw_debug/Makefile | 5 + 60 files changed, 58556 insertions(+), 2 deletions(-) create mode 100644 litedram/extras/VexRiscv.v create mode 100644 litedram/extras/fusesoc-add-files.py create mode 100644 litedram/gen-src/arty.yml create mode 100755 litedram/gen-src/generate.py create mode 100644 litedram/gen-src/nexys-video.yml create mode 100644 litedram/gen-src/sdram_init/Makefile create mode 100755 litedram/gen-src/sdram_init/bin2hex.py create mode 100644 litedram/gen-src/sdram_init/head.S create mode 100644 litedram/gen-src/sdram_init/include/system.h create mode 100644 litedram/gen-src/sdram_init/libc/include/assert.h create mode 100644 litedram/gen-src/sdram_init/libc/include/compiler.h create mode 100644 litedram/gen-src/sdram_init/libc/include/ctype.h create mode 100644 litedram/gen-src/sdram_init/libc/include/errno.h create mode 100644 litedram/gen-src/sdram_init/libc/include/stdint.h create mode 100644 litedram/gen-src/sdram_init/libc/include/stdio.h create mode 100644 litedram/gen-src/sdram_init/libc/include/stdlib.h create mode 100644 litedram/gen-src/sdram_init/libc/include/string.h create mode 100644 litedram/gen-src/sdram_init/libc/include/unistd.h create mode 100644 litedram/gen-src/sdram_init/libc/src/isdigit.c create mode 100644 litedram/gen-src/sdram_init/libc/src/isprint.c create mode 100644 litedram/gen-src/sdram_init/libc/src/isspace.c create mode 100644 litedram/gen-src/sdram_init/libc/src/isxdigit.c create mode 100644 litedram/gen-src/sdram_init/libc/src/memchr.c create mode 100644 litedram/gen-src/sdram_init/libc/src/memcmp.c create mode 100644 litedram/gen-src/sdram_init/libc/src/memcpy.c create mode 100644 litedram/gen-src/sdram_init/libc/src/memmove.c create mode 100644 litedram/gen-src/sdram_init/libc/src/memset.c create mode 100644 litedram/gen-src/sdram_init/libc/src/strcasecmp.c create mode 100644 litedram/gen-src/sdram_init/libc/src/strcat.c create mode 100644 litedram/gen-src/sdram_init/libc/src/strchr.c create mode 100644 litedram/gen-src/sdram_init/libc/src/strcmp.c create mode 100644 litedram/gen-src/sdram_init/libc/src/strcpy.c create mode 100644 litedram/gen-src/sdram_init/libc/src/strlen.c create mode 100644 litedram/gen-src/sdram_init/libc/src/strncasecmp.c create mode 100644 litedram/gen-src/sdram_init/libc/src/strncmp.c create mode 100644 litedram/gen-src/sdram_init/libc/src/strncpy.c create mode 100644 litedram/gen-src/sdram_init/libc/src/strrchr.c create mode 100644 litedram/gen-src/sdram_init/libc/src/strstr.c create mode 100644 litedram/gen-src/sdram_init/libc/src/strtok.c create mode 100644 litedram/gen-src/sdram_init/libc/src/strtol.c create mode 100644 litedram/gen-src/sdram_init/libc/src/strtoul.c create mode 100644 litedram/gen-src/sdram_init/libc/src/tolower.c create mode 100644 litedram/gen-src/sdram_init/libc/src/toupper.c create mode 100644 litedram/gen-src/sdram_init/libc/src/vsnprintf.c create mode 100644 litedram/gen-src/sdram_init/main.c create mode 100644 litedram/gen-src/sdram_init/sdram_init.lds create mode 100644 litedram/gen-src/wrapper-mw-init.vhdl create mode 100644 litedram/gen-src/wrapper-self-init.vhdl create mode 100644 litedram/generated/arty/init-cpu.txt create mode 100644 litedram/generated/arty/litedram-wrapper.vhdl create mode 100644 litedram/generated/arty/litedram_core.init create mode 100644 litedram/generated/arty/litedram_core.v create mode 100644 litedram/generated/nexys-video/init-cpu.txt create mode 100644 litedram/generated/nexys-video/litedram-wrapper.vhdl create mode 100644 litedram/generated/nexys-video/litedram_core.init create mode 100644 litedram/generated/nexys-video/litedram_core.v create mode 100644 litedram/litedram.core diff --git a/Makefile b/Makefile index ed74176..1978d01 100644 --- a/Makefile +++ b/Makefile @@ -152,11 +152,21 @@ TAGS: .PHONY: TAGS -clean: +_clean: rm -f *.o work-*cf unisim-*cf $(all) rm -f fpga/*.o fpga/work-*cf rm -f sim-unisim/*.o sim-unisim/unisim-*cf rm -f TAGS + rm -f scripts/mw_debug/*.o + rm -f scripts/mw_debug/mw_debug -distclean: clean +clean: _clean + make -f scripts/mw_debug/Makefile clean + +distclean: _clean rm -f *~ fpga/~ + rm -rf litedram/build + rm -f litedram/extras/*~ + rm -f litedram/gen-src/*~ + rm -f litedram/gen-src/sdram_init/*~ + make -f scripts/mw_debug/Makefile distclean diff --git a/litedram/extras/VexRiscv.v b/litedram/extras/VexRiscv.v new file mode 100644 index 0000000..0fda9d8 --- /dev/null +++ b/litedram/extras/VexRiscv.v @@ -0,0 +1,3967 @@ +// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8 +// Date : 23/03/2020, 17:06:53 +// Component : VexRiscv + + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +module StreamFifoLowLatency ( + input io_push_valid, + output io_push_ready, + input io_push_payload_error, + input [31:0] io_push_payload_inst, + output reg io_pop_valid, + input io_pop_ready, + output reg io_pop_payload_error, + output reg [31:0] io_pop_payload_inst, + input io_flush, + output [0:0] io_occupancy, + input clk, + input reset); + wire _zz_5_; + wire [0:0] _zz_6_; + reg _zz_1_; + reg pushPtr_willIncrement; + reg pushPtr_willClear; + wire pushPtr_willOverflowIfInc; + wire pushPtr_willOverflow; + reg popPtr_willIncrement; + reg popPtr_willClear; + wire popPtr_willOverflowIfInc; + wire popPtr_willOverflow; + wire ptrMatch; + reg risingOccupancy; + wire empty; + wire full; + wire pushing; + wire popping; + wire [32:0] _zz_2_; + wire [32:0] _zz_3_; + reg [32:0] _zz_4_; + assign _zz_5_ = (! empty); + assign _zz_6_ = _zz_2_[0 : 0]; + always @ (*) begin + _zz_1_ = 1'b0; + if(pushing)begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + pushPtr_willIncrement = 1'b0; + if(pushing)begin + pushPtr_willIncrement = 1'b1; + end + end + + always @ (*) begin + pushPtr_willClear = 1'b0; + if(io_flush)begin + pushPtr_willClear = 1'b1; + end + end + + assign pushPtr_willOverflowIfInc = 1'b1; + assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement); + always @ (*) begin + popPtr_willIncrement = 1'b0; + if(popping)begin + popPtr_willIncrement = 1'b1; + end + end + + always @ (*) begin + popPtr_willClear = 1'b0; + if(io_flush)begin + popPtr_willClear = 1'b1; + end + end + + assign popPtr_willOverflowIfInc = 1'b1; + assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement); + assign ptrMatch = 1'b1; + assign empty = (ptrMatch && (! risingOccupancy)); + assign full = (ptrMatch && risingOccupancy); + assign pushing = (io_push_valid && io_push_ready); + assign popping = (io_pop_valid && io_pop_ready); + assign io_push_ready = (! full); + always @ (*) begin + if(_zz_5_)begin + io_pop_valid = 1'b1; + end else begin + io_pop_valid = io_push_valid; + end + end + + assign _zz_2_ = _zz_3_; + always @ (*) begin + if(_zz_5_)begin + io_pop_payload_error = _zz_6_[0]; + end else begin + io_pop_payload_error = io_push_payload_error; + end + end + + always @ (*) begin + if(_zz_5_)begin + io_pop_payload_inst = _zz_2_[32 : 1]; + end else begin + io_pop_payload_inst = io_push_payload_inst; + end + end + + assign io_occupancy = (risingOccupancy && ptrMatch); + assign _zz_3_ = _zz_4_; + always @ (posedge clk) begin + if(reset) begin + risingOccupancy <= 1'b0; + end else begin + if((pushing != popping))begin + risingOccupancy <= pushing; + end + if(io_flush)begin + risingOccupancy <= 1'b0; + end + end + end + + always @ (posedge clk) begin + if(_zz_1_)begin + _zz_4_ <= {io_push_payload_inst,io_push_payload_error}; + end + end + +endmodule + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + output iBusWishbone_CYC, + output iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [1:0] iBusWishbone_BTE, + output [2:0] iBusWishbone_CTI, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output reg [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [1:0] dBusWishbone_BTE, + output [2:0] dBusWishbone_CTI, + input clk, + input reset); + reg [31:0] _zz_161_; + reg [31:0] _zz_162_; + reg [31:0] _zz_163_; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; + wire _zz_164_; + wire _zz_165_; + wire _zz_166_; + wire _zz_167_; + wire _zz_168_; + wire _zz_169_; + wire _zz_170_; + wire [1:0] _zz_171_; + wire _zz_172_; + wire _zz_173_; + wire _zz_174_; + wire _zz_175_; + wire _zz_176_; + wire _zz_177_; + wire _zz_178_; + wire _zz_179_; + wire _zz_180_; + wire _zz_181_; + wire _zz_182_; + wire _zz_183_; + wire _zz_184_; + wire _zz_185_; + wire _zz_186_; + wire _zz_187_; + wire [1:0] _zz_188_; + wire _zz_189_; + wire [3:0] _zz_190_; + wire [2:0] _zz_191_; + wire [31:0] _zz_192_; + wire [2:0] _zz_193_; + wire [0:0] _zz_194_; + wire [2:0] _zz_195_; + wire [0:0] _zz_196_; + wire [2:0] _zz_197_; + wire [0:0] _zz_198_; + wire [2:0] _zz_199_; + wire [0:0] _zz_200_; + wire [2:0] _zz_201_; + wire [2:0] _zz_202_; + wire [0:0] _zz_203_; + wire [0:0] _zz_204_; + wire [0:0] _zz_205_; + wire [0:0] _zz_206_; + wire [0:0] _zz_207_; + wire [0:0] _zz_208_; + wire [0:0] _zz_209_; + wire [0:0] _zz_210_; + wire [0:0] _zz_211_; + wire [0:0] _zz_212_; + wire [0:0] _zz_213_; + wire [0:0] _zz_214_; + wire [2:0] _zz_215_; + wire [4:0] _zz_216_; + wire [11:0] _zz_217_; + wire [11:0] _zz_218_; + wire [31:0] _zz_219_; + wire [31:0] _zz_220_; + wire [31:0] _zz_221_; + wire [31:0] _zz_222_; + wire [31:0] _zz_223_; + wire [31:0] _zz_224_; + wire [31:0] _zz_225_; + wire [31:0] _zz_226_; + wire [32:0] _zz_227_; + wire [19:0] _zz_228_; + wire [11:0] _zz_229_; + wire [11:0] _zz_230_; + wire [1:0] _zz_231_; + wire [1:0] _zz_232_; + wire [1:0] _zz_233_; + wire [1:0] _zz_234_; + wire [0:0] _zz_235_; + wire [0:0] _zz_236_; + wire [0:0] _zz_237_; + wire [0:0] _zz_238_; + wire [0:0] _zz_239_; + wire [0:0] _zz_240_; + wire [6:0] _zz_241_; + wire _zz_242_; + wire _zz_243_; + wire [1:0] _zz_244_; + wire [31:0] _zz_245_; + wire [31:0] _zz_246_; + wire [31:0] _zz_247_; + wire _zz_248_; + wire [0:0] _zz_249_; + wire [0:0] _zz_250_; + wire _zz_251_; + wire [0:0] _zz_252_; + wire [18:0] _zz_253_; + wire [31:0] _zz_254_; + wire [31:0] _zz_255_; + wire [31:0] _zz_256_; + wire [31:0] _zz_257_; + wire [31:0] _zz_258_; + wire [31:0] _zz_259_; + wire _zz_260_; + wire [1:0] _zz_261_; + wire [1:0] _zz_262_; + wire _zz_263_; + wire [0:0] _zz_264_; + wire [14:0] _zz_265_; + wire [31:0] _zz_266_; + wire [31:0] _zz_267_; + wire [31:0] _zz_268_; + wire [31:0] _zz_269_; + wire [0:0] _zz_270_; + wire [0:0] _zz_271_; + wire [0:0] _zz_272_; + wire [0:0] _zz_273_; + wire _zz_274_; + wire [0:0] _zz_275_; + wire [11:0] _zz_276_; + wire [31:0] _zz_277_; + wire [31:0] _zz_278_; + wire [31:0] _zz_279_; + wire _zz_280_; + wire [0:0] _zz_281_; + wire [1:0] _zz_282_; + wire [0:0] _zz_283_; + wire [0:0] _zz_284_; + wire [1:0] _zz_285_; + wire [1:0] _zz_286_; + wire _zz_287_; + wire [0:0] _zz_288_; + wire [8:0] _zz_289_; + wire [31:0] _zz_290_; + wire [31:0] _zz_291_; + wire [31:0] _zz_292_; + wire [31:0] _zz_293_; + wire [31:0] _zz_294_; + wire [31:0] _zz_295_; + wire [31:0] _zz_296_; + wire [31:0] _zz_297_; + wire _zz_298_; + wire _zz_299_; + wire [0:0] _zz_300_; + wire [0:0] _zz_301_; + wire [1:0] _zz_302_; + wire [1:0] _zz_303_; + wire _zz_304_; + wire [0:0] _zz_305_; + wire [5:0] _zz_306_; + wire [31:0] _zz_307_; + wire [31:0] _zz_308_; + wire [31:0] _zz_309_; + wire [31:0] _zz_310_; + wire _zz_311_; + wire _zz_312_; + wire [1:0] _zz_313_; + wire [1:0] _zz_314_; + wire _zz_315_; + wire [0:0] _zz_316_; + wire [2:0] _zz_317_; + wire [31:0] _zz_318_; + wire [31:0] _zz_319_; + wire [31:0] _zz_320_; + wire [31:0] _zz_321_; + wire _zz_322_; + wire [0:0] _zz_323_; + wire [0:0] _zz_324_; + wire [0:0] _zz_325_; + wire [1:0] _zz_326_; + wire [5:0] _zz_327_; + wire [5:0] _zz_328_; + wire _zz_329_; + wire _zz_330_; + wire [31:0] _zz_331_; + wire [31:0] _zz_332_; + wire [31:0] _zz_333_; + wire [31:0] _zz_334_; + wire [31:0] _zz_335_; + wire [31:0] _zz_336_; + wire [31:0] _zz_337_; + wire _zz_338_; + wire [0:0] _zz_339_; + wire [2:0] _zz_340_; + wire [31:0] _zz_341_; + wire [31:0] _zz_342_; + wire _zz_343_; + wire _zz_344_; + wire [31:0] _zz_345_; + wire [31:0] _zz_346_; + wire [31:0] _zz_347_; + wire _zz_348_; + wire [0:0] _zz_349_; + wire [12:0] _zz_350_; + wire [31:0] _zz_351_; + wire [31:0] _zz_352_; + wire [31:0] _zz_353_; + wire _zz_354_; + wire [0:0] _zz_355_; + wire [6:0] _zz_356_; + wire [31:0] _zz_357_; + wire [31:0] _zz_358_; + wire [31:0] _zz_359_; + wire _zz_360_; + wire [0:0] _zz_361_; + wire [0:0] _zz_362_; + wire [31:0] decode_RS1; + wire execute_BRANCH_DO; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_SRC2_FORCE_ZERO; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_1_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_2_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_3_; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire decode_CSR_WRITE_OPCODE; + wire [31:0] execute_BRANCH_CALC; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_STORE; + wire [31:0] memory_MEMORY_READ_DATA; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire decode_IS_CSR; + wire [31:0] decode_RS2; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7_; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_8_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_9_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_10_; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_11_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_12_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_13_; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_14_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_15_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_16_; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_17_; + wire `AluCtrlEnum_defaultEncoding_type _zz_18_; + wire `AluCtrlEnum_defaultEncoding_type _zz_19_; + wire decode_CSR_READ_OPCODE; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_20_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_21_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_22_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_23_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_24_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_25_; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_26_; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_27_; + wire _zz_28_; + wire _zz_29_; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_30_; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] _zz_31_; + wire [31:0] execute_PC; + wire [31:0] execute_RS1; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_32_; + wire _zz_33_; + wire decode_RS2_USE; + wire decode_RS1_USE; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] _zz_34_; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_35_; + wire _zz_36_; + wire [31:0] _zz_37_; + wire [31:0] _zz_38_; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_39_; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_40_; + wire [31:0] _zz_41_; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_42_; + wire [31:0] _zz_43_; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire _zz_44_; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_45_; + wire [31:0] _zz_46_; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_47_; + wire [31:0] _zz_48_; + wire _zz_49_; + reg _zz_50_; + wire [31:0] _zz_51_; + wire [31:0] _zz_52_; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire decode_INSTRUCTION_READY; + wire _zz_53_; + wire _zz_54_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_55_; + wire _zz_56_; + wire _zz_57_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_58_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_59_; + wire `AluCtrlEnum_defaultEncoding_type _zz_60_; + wire _zz_61_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_62_; + wire _zz_63_; + wire _zz_64_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_65_; + wire _zz_66_; + wire _zz_67_; + wire _zz_68_; + wire _zz_69_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_70_; + wire _zz_71_; + wire writeBack_MEMORY_STORE; + reg [31:0] _zz_72_; + wire writeBack_MEMORY_ENABLE; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_MEMORY_READ_DATA; + wire memory_MMU_FAULT; + wire [31:0] memory_MMU_RSP_physicalAddress; + wire memory_MMU_RSP_isIoAccess; + wire memory_MMU_RSP_allowRead; + wire memory_MMU_RSP_allowWrite; + wire memory_MMU_RSP_allowExecute; + wire memory_MMU_RSP_exception; + wire memory_MMU_RSP_refilling; + wire [31:0] memory_PC; + wire memory_ALIGNEMENT_FAULT; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_STORE; + wire memory_MEMORY_ENABLE; + wire [31:0] _zz_73_; + wire [31:0] _zz_74_; + wire _zz_75_; + wire _zz_76_; + wire _zz_77_; + wire _zz_78_; + wire _zz_79_; + wire _zz_80_; + wire execute_MMU_FAULT; + wire [31:0] execute_MMU_RSP_physicalAddress; + wire execute_MMU_RSP_isIoAccess; + wire execute_MMU_RSP_allowRead; + wire execute_MMU_RSP_allowWrite; + wire execute_MMU_RSP_allowExecute; + wire execute_MMU_RSP_exception; + wire execute_MMU_RSP_refilling; + wire _zz_81_; + wire [31:0] execute_SRC_ADD; + wire [1:0] _zz_82_; + wire [31:0] execute_RS2; + wire [31:0] execute_INSTRUCTION; + wire execute_MEMORY_STORE; + wire execute_MEMORY_ENABLE; + wire execute_ALIGNEMENT_FAULT; + wire _zz_83_; + wire decode_MEMORY_ENABLE; + reg [31:0] _zz_84_; + reg [31:0] _zz_85_; + wire [31:0] decode_PC; + wire [31:0] _zz_86_; + wire [31:0] _zz_87_; + wire [31:0] _zz_88_; + wire [31:0] decode_INSTRUCTION; + wire [31:0] _zz_89_; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + reg decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + wire execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + reg memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + wire writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + wire writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusSimplePlugin_fetcherHalt; + reg IBusSimplePlugin_fetcherflushIt; + reg IBusSimplePlugin_incomingInstruction; + wire IBusSimplePlugin_pcValids_0; + wire IBusSimplePlugin_pcValids_1; + wire IBusSimplePlugin_pcValids_2; + wire IBusSimplePlugin_pcValids_3; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + wire [31:0] iBus_cmd_payload_pc; + wire iBus_rsp_valid; + wire iBus_rsp_payload_error; + wire [31:0] iBus_rsp_payload_inst; + wire IBusSimplePlugin_decodeExceptionPort_valid; + reg [3:0] IBusSimplePlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusSimplePlugin_decodeExceptionPort_payload_badAddr; + wire IBusSimplePlugin_mmuBus_cmd_isValid; + wire [31:0] IBusSimplePlugin_mmuBus_cmd_virtualAddress; + wire IBusSimplePlugin_mmuBus_cmd_bypassTranslation; + wire [31:0] IBusSimplePlugin_mmuBus_rsp_physicalAddress; + wire IBusSimplePlugin_mmuBus_rsp_isIoAccess; + wire IBusSimplePlugin_mmuBus_rsp_allowRead; + wire IBusSimplePlugin_mmuBus_rsp_allowWrite; + wire IBusSimplePlugin_mmuBus_rsp_allowExecute; + wire IBusSimplePlugin_mmuBus_rsp_exception; + wire IBusSimplePlugin_mmuBus_rsp_refilling; + wire IBusSimplePlugin_mmuBus_end; + wire IBusSimplePlugin_mmuBus_busy; + wire IBusSimplePlugin_redoBranch_valid; + wire [31:0] IBusSimplePlugin_redoBranch_payload; + reg DBusSimplePlugin_memoryExceptionPort_valid; + reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; + wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + wire DBusSimplePlugin_mmuBus_cmd_isValid; + wire [31:0] DBusSimplePlugin_mmuBus_cmd_virtualAddress; + wire DBusSimplePlugin_mmuBus_cmd_bypassTranslation; + wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; + wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; + wire DBusSimplePlugin_mmuBus_rsp_allowRead; + wire DBusSimplePlugin_mmuBus_rsp_allowWrite; + wire DBusSimplePlugin_mmuBus_rsp_allowExecute; + wire DBusSimplePlugin_mmuBus_rsp_exception; + wire DBusSimplePlugin_mmuBus_rsp_refilling; + wire DBusSimplePlugin_mmuBus_end; + wire DBusSimplePlugin_mmuBus_busy; + reg DBusSimplePlugin_redoBranch_valid; + wire [31:0] DBusSimplePlugin_redoBranch_payload; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + wire IBusSimplePlugin_jump_pcLoad_valid; + wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; + wire [3:0] _zz_90_; + wire [3:0] _zz_91_; + wire _zz_92_; + wire _zz_93_; + wire _zz_94_; + wire IBusSimplePlugin_fetchPc_output_valid; + wire IBusSimplePlugin_fetchPc_output_ready; + wire [31:0] IBusSimplePlugin_fetchPc_output_payload; + reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusSimplePlugin_fetchPc_corrected; + reg IBusSimplePlugin_fetchPc_pcRegPropagate; + reg IBusSimplePlugin_fetchPc_booted; + reg IBusSimplePlugin_fetchPc_inc; + reg [31:0] IBusSimplePlugin_fetchPc_pc; + reg IBusSimplePlugin_iBusRsp_stages_0_input_valid; + reg IBusSimplePlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_0_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload; + reg IBusSimplePlugin_iBusRsp_stages_0_halt; + wire IBusSimplePlugin_iBusRsp_stages_0_inputSample; + wire IBusSimplePlugin_iBusRsp_stages_1_input_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_1_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload; + wire IBusSimplePlugin_iBusRsp_stages_1_halt; + wire IBusSimplePlugin_iBusRsp_stages_1_inputSample; + wire _zz_95_; + wire _zz_96_; + wire _zz_97_; + wire _zz_98_; + reg _zz_99_; + reg IBusSimplePlugin_iBusRsp_readyForError; + wire IBusSimplePlugin_iBusRsp_inputBeforeStage_valid; + wire IBusSimplePlugin_iBusRsp_inputBeforeStage_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc; + wire IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error; + wire [31:0] IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst; + wire IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc; + wire IBusSimplePlugin_injector_decodeInput_valid; + wire IBusSimplePlugin_injector_decodeInput_ready; + wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc; + wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error; + wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + wire IBusSimplePlugin_injector_decodeInput_payload_isRvc; + reg _zz_100_; + reg [31:0] _zz_101_; + reg _zz_102_; + reg [31:0] _zz_103_; + reg _zz_104_; + reg IBusSimplePlugin_injector_nextPcCalc_valids_0; + reg IBusSimplePlugin_injector_nextPcCalc_valids_1; + reg IBusSimplePlugin_injector_nextPcCalc_valids_2; + reg IBusSimplePlugin_injector_nextPcCalc_valids_3; + reg IBusSimplePlugin_injector_nextPcCalc_valids_4; + reg IBusSimplePlugin_injector_decodeRemoved; + reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode; + reg IBusSimplePlugin_cmd_valid; + wire IBusSimplePlugin_cmd_ready; + wire [31:0] IBusSimplePlugin_cmd_payload_pc; + reg [2:0] IBusSimplePlugin_pendingCmd; + wire [2:0] IBusSimplePlugin_pendingCmdNext; + reg [31:0] IBusSimplePlugin_mmu_joinCtx_physicalAddress; + reg IBusSimplePlugin_mmu_joinCtx_isIoAccess; + reg IBusSimplePlugin_mmu_joinCtx_allowRead; + reg IBusSimplePlugin_mmu_joinCtx_allowWrite; + reg IBusSimplePlugin_mmu_joinCtx_allowExecute; + reg IBusSimplePlugin_mmu_joinCtx_exception; + reg IBusSimplePlugin_mmu_joinCtx_refilling; + reg [2:0] IBusSimplePlugin_rspJoin_discardCounter; + wire IBusSimplePlugin_rspJoin_rspBufferOutput_valid; + wire IBusSimplePlugin_rspJoin_rspBufferOutput_ready; + wire IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst; + wire iBus_rsp_takeWhen_valid; + wire iBus_rsp_takeWhen_payload_error; + wire [31:0] iBus_rsp_takeWhen_payload_inst; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc; + reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; + wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + wire IBusSimplePlugin_rspJoin_join_valid; + wire IBusSimplePlugin_rspJoin_join_ready; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc; + wire IBusSimplePlugin_rspJoin_join_payload_rsp_error; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + wire IBusSimplePlugin_rspJoin_join_payload_isRvc; + reg IBusSimplePlugin_rspJoin_exceptionDetected; + reg IBusSimplePlugin_rspJoin_redoRequired; + wire _zz_105_; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [1:0] dBus_cmd_payload_size; + wire dBus_rsp_ready; + wire dBus_rsp_error; + wire [31:0] dBus_rsp_data; + wire _zz_106_; + reg execute_DBusSimplePlugin_skipCmd; + reg [31:0] _zz_107_; + reg [3:0] _zz_108_; + wire [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] writeBack_DBusSimplePlugin_rspShifted; + wire _zz_109_; + reg [31:0] _zz_110_; + wire _zz_111_; + reg [31:0] _zz_112_; + reg [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire [25:0] _zz_113_; + wire _zz_114_; + wire _zz_115_; + wire _zz_116_; + wire _zz_117_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_118_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_119_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_120_; + wire `AluCtrlEnum_defaultEncoding_type _zz_121_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_122_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_123_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_124_; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_125_; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_126_; + reg [31:0] _zz_127_; + wire _zz_128_; + reg [19:0] _zz_129_; + wire _zz_130_; + reg [19:0] _zz_131_; + reg [31:0] _zz_132_; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + reg execute_LightShifterPlugin_isActive; + wire execute_LightShifterPlugin_isShift; + reg [4:0] execute_LightShifterPlugin_amplitudeReg; + wire [4:0] execute_LightShifterPlugin_amplitude; + wire [31:0] execute_LightShifterPlugin_shiftInput; + wire execute_LightShifterPlugin_done; + reg [31:0] _zz_133_; + reg _zz_134_; + reg _zz_135_; + wire _zz_136_; + reg _zz_137_; + reg [4:0] _zz_138_; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_139_; + reg _zz_140_; + reg _zz_141_; + wire [31:0] execute_BranchPlugin_branch_src1; + wire _zz_142_; + reg [10:0] _zz_143_; + wire _zz_144_; + reg [19:0] _zz_145_; + wire _zz_146_; + reg [18:0] _zz_147_; + reg [31:0] _zz_148_; + wire [31:0] execute_BranchPlugin_branch_src2; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_149_; + wire _zz_150_; + wire _zz_151_; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_152_; + wire _zz_153_; + wire [1:0] _zz_154_; + wire _zz_155_; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + wire execute_CsrPlugin_inWfi /* verilator public */ ; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + reg [31:0] execute_CsrPlugin_readData; + wire execute_CsrPlugin_writeInstruction; + wire execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_156_; + wire [31:0] _zz_157_; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg execute_to_memory_MMU_FAULT; + reg decode_to_execute_CSR_READ_OPCODE; + reg [31:0] execute_to_memory_MMU_RSP_physicalAddress; + reg execute_to_memory_MMU_RSP_isIoAccess; + reg execute_to_memory_MMU_RSP_allowRead; + reg execute_to_memory_MMU_RSP_allowWrite; + reg execute_to_memory_MMU_RSP_allowExecute; + reg execute_to_memory_MMU_RSP_exception; + reg execute_to_memory_MMU_RSP_refilling; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg execute_to_memory_ALIGNEMENT_FAULT; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_IS_CSR; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + reg decode_to_execute_MEMORY_STORE; + reg execute_to_memory_MEMORY_STORE; + reg memory_to_writeBack_MEMORY_STORE; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BRANCH_DO; + reg [31:0] decode_to_execute_RS1; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire iBus_cmd_m2sPipe_valid; + wire iBus_cmd_m2sPipe_ready; + wire [31:0] iBus_cmd_m2sPipe_payload_pc; + reg _zz_158_; + reg [31:0] _zz_159_; + wire dBus_cmd_halfPipe_valid; + wire dBus_cmd_halfPipe_ready; + wire dBus_cmd_halfPipe_payload_wr; + wire [31:0] dBus_cmd_halfPipe_payload_address; + wire [31:0] dBus_cmd_halfPipe_payload_data; + wire [1:0] dBus_cmd_halfPipe_payload_size; + reg dBus_cmd_halfPipe_regs_valid; + reg dBus_cmd_halfPipe_regs_ready; + reg dBus_cmd_halfPipe_regs_payload_wr; + reg [31:0] dBus_cmd_halfPipe_regs_payload_address; + reg [31:0] dBus_cmd_halfPipe_regs_payload_data; + reg [1:0] dBus_cmd_halfPipe_regs_payload_size; + reg [3:0] _zz_160_; + `ifndef SYNTHESIS + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_1__string; + reg [23:0] _zz_2__string; + reg [23:0] _zz_3__string; + reg [39:0] _zz_4__string; + reg [39:0] _zz_5__string; + reg [39:0] _zz_6__string; + reg [39:0] _zz_7__string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_8__string; + reg [39:0] _zz_9__string; + reg [39:0] _zz_10__string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_11__string; + reg [95:0] _zz_12__string; + reg [95:0] _zz_13__string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_14__string; + reg [31:0] _zz_15__string; + reg [31:0] _zz_16__string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_17__string; + reg [63:0] _zz_18__string; + reg [63:0] _zz_19__string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_20__string; + reg [71:0] _zz_21__string; + reg [71:0] _zz_22__string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_23__string; + reg [39:0] _zz_24__string; + reg [39:0] _zz_25__string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_26__string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_27__string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_30__string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_32__string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_35__string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_40__string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_42__string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_45__string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_47__string; + reg [39:0] _zz_55__string; + reg [39:0] _zz_58__string; + reg [31:0] _zz_59__string; + reg [63:0] _zz_60__string; + reg [23:0] _zz_62__string; + reg [95:0] _zz_65__string; + reg [71:0] _zz_70__string; + reg [71:0] _zz_118__string; + reg [95:0] _zz_119__string; + reg [23:0] _zz_120__string; + reg [63:0] _zz_121__string; + reg [31:0] _zz_122__string; + reg [39:0] _zz_123__string; + reg [39:0] _zz_124__string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + `endif + + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + assign _zz_164_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000))); + assign _zz_165_ = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_166_ = ({decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid} != (2'b00)); + assign _zz_167_ = (! execute_arbitration_isStuckByOthers); + assign _zz_168_ = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != (2'b00)); + assign _zz_169_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_170_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_171_ = writeBack_INSTRUCTION[29 : 28]; + assign _zz_172_ = (IBusSimplePlugin_mmuBus_rsp_exception || IBusSimplePlugin_mmuBus_rsp_refilling); + assign _zz_173_ = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute))); + assign _zz_174_ = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); + assign _zz_175_ = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + assign _zz_176_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_177_ = (1'b1 || (! 1'b1)); + assign _zz_178_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_179_ = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_180_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_181_ = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_182_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_183_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))); + assign _zz_184_ = ((_zz_149_ && 1'b1) && (! 1'b0)); + assign _zz_185_ = ((_zz_150_ && 1'b1) && (! 1'b0)); + assign _zz_186_ = ((_zz_151_ && 1'b1) && (! 1'b0)); + assign _zz_187_ = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_188_ = writeBack_INSTRUCTION[13 : 12]; + assign _zz_189_ = execute_INSTRUCTION[13]; + assign _zz_190_ = (_zz_90_ - (4'b0001)); + assign _zz_191_ = {IBusSimplePlugin_fetchPc_inc,(2'b00)}; + assign _zz_192_ = {29'd0, _zz_191_}; + assign _zz_193_ = (IBusSimplePlugin_pendingCmd + _zz_195_); + assign _zz_194_ = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); + assign _zz_195_ = {2'd0, _zz_194_}; + assign _zz_196_ = iBus_rsp_valid; + assign _zz_197_ = {2'd0, _zz_196_}; + assign _zz_198_ = (iBus_rsp_valid && (IBusSimplePlugin_rspJoin_discardCounter != (3'b000))); + assign _zz_199_ = {2'd0, _zz_198_}; + assign _zz_200_ = iBus_rsp_valid; + assign _zz_201_ = {2'd0, _zz_200_}; + assign _zz_202_ = (memory_MEMORY_STORE ? (3'b110) : (3'b100)); + assign _zz_203_ = _zz_113_[2 : 2]; + assign _zz_204_ = _zz_113_[4 : 4]; + assign _zz_205_ = _zz_113_[5 : 5]; + assign _zz_206_ = _zz_113_[6 : 6]; + assign _zz_207_ = _zz_113_[9 : 9]; + assign _zz_208_ = _zz_113_[10 : 10]; + assign _zz_209_ = _zz_113_[13 : 13]; + assign _zz_210_ = _zz_113_[20 : 20]; + assign _zz_211_ = _zz_113_[21 : 21]; + assign _zz_212_ = _zz_113_[24 : 24]; + assign _zz_213_ = _zz_113_[25 : 25]; + assign _zz_214_ = execute_SRC_LESS; + assign _zz_215_ = (3'b100); + assign _zz_216_ = execute_INSTRUCTION[19 : 15]; + assign _zz_217_ = execute_INSTRUCTION[31 : 20]; + assign _zz_218_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_219_ = ($signed(_zz_220_) + $signed(_zz_223_)); + assign _zz_220_ = ($signed(_zz_221_) + $signed(_zz_222_)); + assign _zz_221_ = execute_SRC1; + assign _zz_222_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_223_ = (execute_SRC_USE_SUB_LESS ? _zz_224_ : _zz_225_); + assign _zz_224_ = (32'b00000000000000000000000000000001); + assign _zz_225_ = (32'b00000000000000000000000000000000); + assign _zz_226_ = (_zz_227_ >>> 1); + assign _zz_227_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_228_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_229_ = execute_INSTRUCTION[31 : 20]; + assign _zz_230_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_231_ = (_zz_152_ & (~ _zz_232_)); + assign _zz_232_ = (_zz_152_ - (2'b01)); + assign _zz_233_ = (_zz_154_ & (~ _zz_234_)); + assign _zz_234_ = (_zz_154_ - (2'b01)); + assign _zz_235_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_236_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_237_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_238_ = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_239_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_240_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_241_ = ({3'd0,_zz_160_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + assign _zz_242_ = 1'b1; + assign _zz_243_ = 1'b1; + assign _zz_244_ = {_zz_94_,_zz_93_}; + assign _zz_245_ = (32'b00000000000000000000000000010000); + assign _zz_246_ = (decode_INSTRUCTION & (32'b00010000000000000011000001010000)); + assign _zz_247_ = (32'b00000000000000000000000001010000); + assign _zz_248_ = ((decode_INSTRUCTION & (32'b00010000010000000011000001010000)) == (32'b00010000000000000000000001010000)); + assign _zz_249_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000100000)); + assign _zz_250_ = (1'b0); + assign _zz_251_ = ({(_zz_254_ == _zz_255_),(_zz_256_ == _zz_257_)} != (2'b00)); + assign _zz_252_ = ((_zz_258_ == _zz_259_) != (1'b0)); + assign _zz_253_ = {(_zz_260_ != (1'b0)),{(_zz_261_ != _zz_262_),{_zz_263_,{_zz_264_,_zz_265_}}}}; + assign _zz_254_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); + assign _zz_255_ = (32'b00000000000000000000000000100100); + assign _zz_256_ = (decode_INSTRUCTION & (32'b00000000000000000011000001010100)); + assign _zz_257_ = (32'b00000000000000000001000000010000); + assign _zz_258_ = (decode_INSTRUCTION & (32'b00000000000000000001000000000000)); + assign _zz_259_ = (32'b00000000000000000001000000000000); + assign _zz_260_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000)); + assign _zz_261_ = {_zz_115_,(_zz_266_ == _zz_267_)}; + assign _zz_262_ = (2'b00); + assign _zz_263_ = ((_zz_268_ == _zz_269_) != (1'b0)); + assign _zz_264_ = ({_zz_270_,_zz_271_} != (2'b00)); + assign _zz_265_ = {(_zz_272_ != _zz_273_),{_zz_274_,{_zz_275_,_zz_276_}}}; + assign _zz_266_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011100)); + assign _zz_267_ = (32'b00000000000000000000000000000100); + assign _zz_268_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); + assign _zz_269_ = (32'b00000000000000000000000001000000); + assign _zz_270_ = ((decode_INSTRUCTION & _zz_277_) == (32'b00000000000000000110000000010000)); + assign _zz_271_ = ((decode_INSTRUCTION & _zz_278_) == (32'b00000000000000000100000000010000)); + assign _zz_272_ = ((decode_INSTRUCTION & _zz_279_) == (32'b00000000000000000010000000010000)); + assign _zz_273_ = (1'b0); + assign _zz_274_ = ({_zz_280_,{_zz_281_,_zz_282_}} != (4'b0000)); + assign _zz_275_ = ({_zz_283_,_zz_284_} != (2'b00)); + assign _zz_276_ = {(_zz_285_ != _zz_286_),{_zz_287_,{_zz_288_,_zz_289_}}}; + assign _zz_277_ = (32'b00000000000000000110000000010100); + assign _zz_278_ = (32'b00000000000000000101000000010100); + assign _zz_279_ = (32'b00000000000000000110000000010100); + assign _zz_280_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000000)); + assign _zz_281_ = ((decode_INSTRUCTION & _zz_290_) == (32'b00000000000000000000000000000000)); + assign _zz_282_ = {(_zz_291_ == _zz_292_),(_zz_293_ == _zz_294_)}; + assign _zz_283_ = _zz_117_; + assign _zz_284_ = ((decode_INSTRUCTION & _zz_295_) == (32'b00000000000000000000000000100000)); + assign _zz_285_ = {_zz_117_,(_zz_296_ == _zz_297_)}; + assign _zz_286_ = (2'b00); + assign _zz_287_ = ({_zz_298_,_zz_299_} != (2'b00)); + assign _zz_288_ = ({_zz_300_,_zz_301_} != (2'b00)); + assign _zz_289_ = {(_zz_302_ != _zz_303_),{_zz_304_,{_zz_305_,_zz_306_}}}; + assign _zz_290_ = (32'b00000000000000000000000000011000); + assign _zz_291_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100)); + assign _zz_292_ = (32'b00000000000000000010000000000000); + assign _zz_293_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100)); + assign _zz_294_ = (32'b00000000000000000001000000000000); + assign _zz_295_ = (32'b00000000000000000000000001110000); + assign _zz_296_ = (decode_INSTRUCTION & (32'b00000000000000000000000000100000)); + assign _zz_297_ = (32'b00000000000000000000000000000000); + assign _zz_298_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000000000)); + assign _zz_299_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000001000000000000)); + assign _zz_300_ = ((decode_INSTRUCTION & _zz_307_) == (32'b00000000000000000001000001010000)); + assign _zz_301_ = ((decode_INSTRUCTION & _zz_308_) == (32'b00000000000000000010000001010000)); + assign _zz_302_ = {(_zz_309_ == _zz_310_),_zz_116_}; + assign _zz_303_ = (2'b00); + assign _zz_304_ = ({_zz_311_,_zz_116_} != (2'b00)); + assign _zz_305_ = (_zz_312_ != (1'b0)); + assign _zz_306_ = {(_zz_313_ != _zz_314_),{_zz_315_,{_zz_316_,_zz_317_}}}; + assign _zz_307_ = (32'b00000000000000000001000001010000); + assign _zz_308_ = (32'b00000000000000000010000001010000); + assign _zz_309_ = (decode_INSTRUCTION & (32'b00000000000000000000000000010100)); + assign _zz_310_ = (32'b00000000000000000000000000000100); + assign _zz_311_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000100)); + assign _zz_312_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000000000000)); + assign _zz_313_ = {(_zz_318_ == _zz_319_),(_zz_320_ == _zz_321_)}; + assign _zz_314_ = (2'b00); + assign _zz_315_ = ({_zz_322_,{_zz_323_,_zz_324_}} != (3'b000)); + assign _zz_316_ = ({_zz_325_,_zz_326_} != (3'b000)); + assign _zz_317_ = {(_zz_327_ != _zz_328_),{_zz_329_,_zz_330_}}; + assign _zz_318_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100)); + assign _zz_319_ = (32'b00000000000000000000000000100000); + assign _zz_320_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); + assign _zz_321_ = (32'b00000000000000000000000000100000); + assign _zz_322_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000001000000)); + assign _zz_323_ = ((decode_INSTRUCTION & _zz_331_) == (32'b00000000000000000010000000010000)); + assign _zz_324_ = ((decode_INSTRUCTION & _zz_332_) == (32'b01000000000000000000000000110000)); + assign _zz_325_ = ((decode_INSTRUCTION & _zz_333_) == (32'b00000000000000000000000001000000)); + assign _zz_326_ = {(_zz_334_ == _zz_335_),(_zz_336_ == _zz_337_)}; + assign _zz_327_ = {_zz_115_,{_zz_338_,{_zz_339_,_zz_340_}}}; + assign _zz_328_ = (6'b000000); + assign _zz_329_ = ((_zz_341_ == _zz_342_) != (1'b0)); + assign _zz_330_ = ({_zz_343_,_zz_344_} != (2'b00)); + assign _zz_331_ = (32'b00000000000000000010000000010100); + assign _zz_332_ = (32'b01000000000000000100000000110100); + assign _zz_333_ = (32'b00000000000000000000000001010000); + assign _zz_334_ = (decode_INSTRUCTION & (32'b00000000000000000000000000111000)); + assign _zz_335_ = (32'b00000000000000000000000000000000); + assign _zz_336_ = (decode_INSTRUCTION & (32'b00000000010000000011000001000000)); + assign _zz_337_ = (32'b00000000000000000000000001000000); + assign _zz_338_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000010000)) == (32'b00000000000000000001000000010000)); + assign _zz_339_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000010000)); + assign _zz_340_ = {_zz_114_,{((decode_INSTRUCTION & (32'b00000000000000000000000000001100)) == (32'b00000000000000000000000000000100)),((decode_INSTRUCTION & (32'b00000000000000000000000000101000)) == (32'b00000000000000000000000000000000))}}; + assign _zz_341_ = (decode_INSTRUCTION & (32'b00000000000000000111000001010100)); + assign _zz_342_ = (32'b00000000000000000101000000010000); + assign _zz_343_ = ((decode_INSTRUCTION & (32'b01000000000000000011000001010100)) == (32'b01000000000000000001000000010000)); + assign _zz_344_ = ((decode_INSTRUCTION & (32'b00000000000000000111000001010100)) == (32'b00000000000000000001000000010000)); + assign _zz_345_ = (32'b00000000000000000001000001111111); + assign _zz_346_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); + assign _zz_347_ = (32'b00000000000000000010000001110011); + assign _zz_348_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); + assign _zz_349_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); + assign _zz_350_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_351_) == (32'b00000000000000000000000000000011)),{(_zz_352_ == _zz_353_),{_zz_354_,{_zz_355_,_zz_356_}}}}}}; + assign _zz_351_ = (32'b00000000000000000101000001011111); + assign _zz_352_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); + assign _zz_353_ = (32'b00000000000000000000000001100011); + assign _zz_354_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); + assign _zz_355_ = ((decode_INSTRUCTION & (32'b11111110000000000000000001111111)) == (32'b00000000000000000000000000110011)); + assign _zz_356_ = {((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & (32'b11111100000000000011000001111111)) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & _zz_357_) == (32'b00000000000000000101000000110011)),{(_zz_358_ == _zz_359_),{_zz_360_,{_zz_361_,_zz_362_}}}}}}; + assign _zz_357_ = (32'b10111110000000000111000001111111); + assign _zz_358_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); + assign _zz_359_ = (32'b00000000000000000000000000110011); + assign _zz_360_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)); + assign _zz_361_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011)); + assign _zz_362_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00000000000000000000000001110011)); + always @ (posedge clk) begin + if(_zz_50_) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_242_) begin + _zz_161_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_243_) begin + _zz_162_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( + .io_push_valid(iBus_rsp_takeWhen_valid), + .io_push_ready(IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready), + .io_push_payload_error(iBus_rsp_takeWhen_payload_error), + .io_push_payload_inst(iBus_rsp_takeWhen_payload_inst), + .io_pop_valid(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid), + .io_pop_ready(IBusSimplePlugin_rspJoin_rspBufferOutput_ready), + .io_pop_payload_error(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error), + .io_pop_payload_inst(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst), + .io_flush(IBusSimplePlugin_fetcherflushIt), + .io_occupancy(IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy), + .clk(clk), + .reset(reset) + ); + always @(*) begin + case(_zz_244_) + 2'b00 : begin + _zz_163_ = CsrPlugin_jumpInterface_payload; + end + 2'b01 : begin + _zz_163_ = DBusSimplePlugin_redoBranch_payload; + end + 2'b10 : begin + _zz_163_ = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_163_ = IBusSimplePlugin_redoBranch_payload; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_1_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_1__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_1__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_1__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_1__string = "PC "; + default : _zz_1__string = "???"; + endcase + end + always @(*) begin + case(_zz_2_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_2__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_2__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_2__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_2__string = "PC "; + default : _zz_2__string = "???"; + endcase + end + always @(*) begin + case(_zz_3_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_3__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_3__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_3__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_3__string = "PC "; + default : _zz_3__string = "???"; + endcase + end + always @(*) begin + case(_zz_4_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4__string = "ECALL"; + default : _zz_4__string = "?????"; + endcase + end + always @(*) begin + case(_zz_5_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5__string = "ECALL"; + default : _zz_5__string = "?????"; + endcase + end + always @(*) begin + case(_zz_6_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6__string = "ECALL"; + default : _zz_6__string = "?????"; + endcase + end + always @(*) begin + case(_zz_7_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7__string = "ECALL"; + default : _zz_7__string = "?????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_8_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_8__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_8__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8__string = "ECALL"; + default : _zz_8__string = "?????"; + endcase + end + always @(*) begin + case(_zz_9_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_9__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_9__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9__string = "ECALL"; + default : _zz_9__string = "?????"; + endcase + end + always @(*) begin + case(_zz_10_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_10__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_10__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10__string = "ECALL"; + default : _zz_10__string = "?????"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_11_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_11__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_11__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_11__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_11__string = "URS1 "; + default : _zz_11__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_12_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_12__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_12__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_12__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_12__string = "URS1 "; + default : _zz_12__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_13_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_13__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_13__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_13__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_13__string = "URS1 "; + default : _zz_13__string = "????????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_14_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_14__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_14__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_14__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_14__string = "JALR"; + default : _zz_14__string = "????"; + endcase + end + always @(*) begin + case(_zz_15_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_15__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_15__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_15__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_15__string = "JALR"; + default : _zz_15__string = "????"; + endcase + end + always @(*) begin + case(_zz_16_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_16__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_16__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_16__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_16__string = "JALR"; + default : _zz_16__string = "????"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_17_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_17__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_17__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_17__string = "BITWISE "; + default : _zz_17__string = "????????"; + endcase + end + always @(*) begin + case(_zz_18_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_18__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_18__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_18__string = "BITWISE "; + default : _zz_18__string = "????????"; + endcase + end + always @(*) begin + case(_zz_19_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_19__string = "BITWISE "; + default : _zz_19__string = "????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_20_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_20__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_20__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_20__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_20__string = "SRA_1 "; + default : _zz_20__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_21_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_21__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_21__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_21__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_21__string = "SRA_1 "; + default : _zz_21__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_22_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_22__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_22__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_22__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_22__string = "SRA_1 "; + default : _zz_22__string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_23_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_23__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_23__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_23__string = "AND_1"; + default : _zz_23__string = "?????"; + endcase + end + always @(*) begin + case(_zz_24_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_24__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_24__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_24__string = "AND_1"; + default : _zz_24__string = "?????"; + endcase + end + always @(*) begin + case(_zz_25_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_25__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_25__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_25__string = "AND_1"; + default : _zz_25__string = "?????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_26_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_26__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_26__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26__string = "ECALL"; + default : _zz_26__string = "?????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_27_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_27__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_27__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27__string = "ECALL"; + default : _zz_27__string = "?????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_30_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_30__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_30__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_30__string = "ECALL"; + default : _zz_30__string = "?????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_32_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_32__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_32__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_32__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_32__string = "JALR"; + default : _zz_32__string = "????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_35_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_35__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_35__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_35__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_35__string = "SRA_1 "; + default : _zz_35__string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_40_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_40__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_40__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_40__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_40__string = "PC "; + default : _zz_40__string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_42_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_42__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_42__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_42__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_42__string = "URS1 "; + default : _zz_42__string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_45_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_45__string = "BITWISE "; + default : _zz_45__string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_47_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_47__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_47__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_47__string = "AND_1"; + default : _zz_47__string = "?????"; + endcase + end + always @(*) begin + case(_zz_55_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_55__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_55__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_55__string = "ECALL"; + default : _zz_55__string = "?????"; + endcase + end + always @(*) begin + case(_zz_58_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_58__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_58__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_58__string = "AND_1"; + default : _zz_58__string = "?????"; + endcase + end + always @(*) begin + case(_zz_59_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_59__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_59__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_59__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_59__string = "JALR"; + default : _zz_59__string = "????"; + endcase + end + always @(*) begin + case(_zz_60_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_60__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_60__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_60__string = "BITWISE "; + default : _zz_60__string = "????????"; + endcase + end + always @(*) begin + case(_zz_62_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_62__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_62__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_62__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_62__string = "PC "; + default : _zz_62__string = "???"; + endcase + end + always @(*) begin + case(_zz_65_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_65__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_65__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_65__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_65__string = "URS1 "; + default : _zz_65__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_70_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_70__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_70__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_70__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_70__string = "SRA_1 "; + default : _zz_70__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_118_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_118__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_118__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_118__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_118__string = "SRA_1 "; + default : _zz_118__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_119_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_119__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_119__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_119__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_119__string = "URS1 "; + default : _zz_119__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_120_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_120__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_120__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_120__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_120__string = "PC "; + default : _zz_120__string = "???"; + endcase + end + always @(*) begin + case(_zz_121_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_121__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_121__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_121__string = "BITWISE "; + default : _zz_121__string = "????????"; + endcase + end + always @(*) begin + case(_zz_122_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_122__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_122__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_122__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_122__string = "JALR"; + default : _zz_122__string = "????"; + endcase + end + always @(*) begin + case(_zz_123_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_123__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_123__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_123__string = "AND_1"; + default : _zz_123__string = "?????"; + endcase + end + always @(*) begin + case(_zz_124_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_124__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_124__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_124__string = "ECALL"; + default : _zz_124__string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + default : decode_to_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + default : execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : memory_to_writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + `endif + + assign decode_RS1 = _zz_52_; + assign execute_BRANCH_DO = _zz_33_; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_54_; + assign decode_SRC2_FORCE_ZERO = _zz_44_; + assign decode_SRC2_CTRL = _zz_1_; + assign _zz_2_ = _zz_3_; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_46_; + assign decode_CSR_WRITE_OPCODE = _zz_29_; + assign execute_BRANCH_CALC = _zz_31_; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = _zz_86_; + assign decode_SRC_LESS_UNSIGNED = _zz_63_; + assign decode_MEMORY_STORE = _zz_56_; + assign memory_MEMORY_READ_DATA = _zz_73_; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_53_; + assign decode_IS_CSR = _zz_64_; + assign decode_RS2 = _zz_51_; + assign _zz_4_ = _zz_5_; + assign _zz_6_ = _zz_7_; + assign decode_ENV_CTRL = _zz_8_; + assign _zz_9_ = _zz_10_; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_82_; + assign decode_SRC1_CTRL = _zz_11_; + assign _zz_12_ = _zz_13_; + assign decode_BRANCH_CTRL = _zz_14_; + assign _zz_15_ = _zz_16_; + assign decode_ALU_CTRL = _zz_17_; + assign _zz_18_ = _zz_19_; + assign decode_CSR_READ_OPCODE = _zz_28_; + assign decode_SHIFT_CTRL = _zz_20_; + assign _zz_21_ = _zz_22_; + assign decode_ALU_BITWISE_CTRL = _zz_23_; + assign _zz_24_ = _zz_25_; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_26_; + assign execute_ENV_CTRL = _zz_27_; + assign writeBack_ENV_CTRL = _zz_30_; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PC = decode_to_execute_PC; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_CTRL = _zz_32_; + assign decode_RS2_USE = _zz_67_; + assign decode_RS1_USE = _zz_61_; + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_34_ = execute_REGFILE_WRITE_DATA; + if(_zz_164_)begin + _zz_34_ = _zz_133_; + end + if(_zz_165_)begin + _zz_34_ = execute_CsrPlugin_readData; + end + end + + assign execute_SHIFT_CTRL = _zz_35_; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_39_ = execute_PC; + assign execute_SRC2_CTRL = _zz_40_; + assign execute_SRC1_CTRL = _zz_42_; + assign decode_SRC_USE_SUB_LESS = _zz_68_; + assign decode_SRC_ADD_ZERO = _zz_57_; + assign execute_SRC_ADD_SUB = _zz_38_; + assign execute_SRC_LESS = _zz_36_; + assign execute_ALU_CTRL = _zz_45_; + assign execute_SRC2 = _zz_41_; + assign execute_SRC1 = _zz_43_; + assign execute_ALU_BITWISE_CTRL = _zz_47_; + assign _zz_48_ = writeBack_INSTRUCTION; + assign _zz_49_ = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_50_ = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_50_ = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = _zz_89_; + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_69_; + if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = _zz_71_; + assign decode_INSTRUCTION_READY = 1'b1; + assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; + always @ (*) begin + _zz_72_ = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_72_ = writeBack_DBusSimplePlugin_rspFormated; + end + end + + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; + assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; + assign memory_MMU_RSP_physicalAddress = execute_to_memory_MMU_RSP_physicalAddress; + assign memory_MMU_RSP_isIoAccess = execute_to_memory_MMU_RSP_isIoAccess; + assign memory_MMU_RSP_allowRead = execute_to_memory_MMU_RSP_allowRead; + assign memory_MMU_RSP_allowWrite = execute_to_memory_MMU_RSP_allowWrite; + assign memory_MMU_RSP_allowExecute = execute_to_memory_MMU_RSP_allowExecute; + assign memory_MMU_RSP_exception = execute_to_memory_MMU_RSP_exception; + assign memory_MMU_RSP_refilling = execute_to_memory_MMU_RSP_refilling; + assign memory_PC = execute_to_memory_PC; + assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MMU_FAULT = _zz_81_; + assign execute_MMU_RSP_physicalAddress = _zz_74_; + assign execute_MMU_RSP_isIoAccess = _zz_75_; + assign execute_MMU_RSP_allowRead = _zz_76_; + assign execute_MMU_RSP_allowWrite = _zz_77_; + assign execute_MMU_RSP_allowExecute = _zz_78_; + assign execute_MMU_RSP_exception = _zz_79_; + assign execute_MMU_RSP_refilling = _zz_80_; + assign execute_SRC_ADD = _zz_37_; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_ALIGNEMENT_FAULT = _zz_83_; + assign decode_MEMORY_ENABLE = _zz_66_; + always @ (*) begin + _zz_84_ = memory_FORMAL_PC_NEXT; + if(DBusSimplePlugin_redoBranch_valid)begin + _zz_84_ = DBusSimplePlugin_redoBranch_payload; + end + if(BranchPlugin_jumpInterface_valid)begin + _zz_84_ = BranchPlugin_jumpInterface_payload; + end + end + + always @ (*) begin + _zz_85_ = decode_FORMAL_PC_NEXT; + if(IBusSimplePlugin_redoBranch_valid)begin + _zz_85_ = IBusSimplePlugin_redoBranch_payload; + end + end + + assign decode_PC = _zz_88_; + assign decode_INSTRUCTION = _zz_87_; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + decode_arbitration_haltItself = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if((decode_arbitration_isValid && (_zz_134_ || _zz_135_)))begin + decode_arbitration_haltByOther = 1'b1; + end + if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin + decode_arbitration_haltByOther = decode_arbitration_isValid; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_166_)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_flushIt = 1'b0; + if(IBusSimplePlugin_redoBranch_valid)begin + decode_arbitration_flushIt = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_flushNext = 1'b0; + if(IBusSimplePlugin_redoBranch_valid)begin + decode_arbitration_flushNext = 1'b1; + end + if(_zz_166_)begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_106_)))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_164_)begin + if(_zz_167_)begin + if(! execute_LightShifterPlugin_done) begin + execute_arbitration_haltItself = 1'b1; + end + end + end + if(_zz_165_)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + assign execute_arbitration_haltByOther = 1'b0; + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(CsrPlugin_selfException_valid)begin + execute_arbitration_removeIt = 1'b1; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + assign execute_arbitration_flushIt = 1'b0; + always @ (*) begin + execute_arbitration_flushNext = 1'b0; + if(CsrPlugin_selfException_valid)begin + execute_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin + memory_arbitration_haltItself = 1'b1; + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(_zz_168_)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_flushIt = 1'b0; + if(DBusSimplePlugin_redoBranch_valid)begin + memory_arbitration_flushIt = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(DBusSimplePlugin_redoBranch_valid)begin + memory_arbitration_flushNext = 1'b1; + end + if(BranchPlugin_jumpInterface_valid)begin + memory_arbitration_flushNext = 1'b1; + end + if(_zz_168_)begin + memory_arbitration_flushNext = 1'b1; + end + end + + assign writeBack_arbitration_haltItself = 1'b0; + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + assign writeBack_arbitration_flushIt = 1'b0; + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(_zz_169_)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_170_)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusSimplePlugin_fetcherHalt = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + if(_zz_169_)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + if(_zz_170_)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusSimplePlugin_fetcherflushIt = 1'b0; + if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin + IBusSimplePlugin_fetcherflushIt = 1'b1; + end + end + + always @ (*) begin + IBusSimplePlugin_incomingInstruction = 1'b0; + if(IBusSimplePlugin_iBusRsp_stages_1_input_valid)begin + IBusSimplePlugin_incomingInstruction = 1'b1; + end + if(IBusSimplePlugin_injector_decodeInput_valid)begin + IBusSimplePlugin_incomingInstruction = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_169_)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_170_)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + if(_zz_169_)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + end + if(_zz_170_)begin + case(_zz_171_) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + assign CsrPlugin_forceMachineWire = 1'b0; + assign CsrPlugin_allowInterrupts = 1'b1; + assign CsrPlugin_allowException = 1'b1; + assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,IBusSimplePlugin_redoBranch_valid}}} != (4'b0000)); + assign _zz_90_ = {IBusSimplePlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}}; + assign _zz_91_ = (_zz_90_ & (~ _zz_190_)); + assign _zz_92_ = _zz_91_[3]; + assign _zz_93_ = (_zz_91_[1] || _zz_92_); + assign _zz_94_ = (_zz_91_[2] || _zz_92_); + assign IBusSimplePlugin_jump_pcLoad_payload = _zz_163_; + always @ (*) begin + IBusSimplePlugin_fetchPc_corrected = 1'b0; + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_corrected = 1'b1; + end + end + + always @ (*) begin + IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusSimplePlugin_iBusRsp_stages_1_input_ready)begin + IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + always @ (*) begin + IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_192_); + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload; + end + IBusSimplePlugin_fetchPc_pc[0] = 1'b0; + IBusSimplePlugin_fetchPc_pc[1] = 1'b0; + end + + assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted); + assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc; + always @ (*) begin + IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; + if(IBusSimplePlugin_mmuBus_busy)begin + IBusSimplePlugin_iBusRsp_stages_0_input_valid = 1'b0; + end + end + + assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready; + assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload; + assign IBusSimplePlugin_iBusRsp_stages_0_inputSample = 1'b1; + always @ (*) begin + IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; + if((IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmd_valid) || (! IBusSimplePlugin_cmd_ready))))begin + IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; + end + if(_zz_172_)begin + IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; + end + end + + assign _zz_95_ = (! IBusSimplePlugin_iBusRsp_stages_0_halt); + always @ (*) begin + IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_95_); + if(IBusSimplePlugin_mmuBus_busy)begin + IBusSimplePlugin_iBusRsp_stages_0_input_ready = 1'b0; + end + end + + assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_95_); + assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload; + assign IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0; + assign _zz_96_ = (! IBusSimplePlugin_iBusRsp_stages_1_halt); + assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_96_); + assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_96_); + assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; + assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_97_; + assign _zz_97_ = ((1'b0 && (! _zz_98_)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); + assign _zz_98_ = _zz_99_; + assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_98_; + assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg; + always @ (*) begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b1; + if(IBusSimplePlugin_injector_decodeInput_valid)begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b0; + end + if((! IBusSimplePlugin_pcValids_0))begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusSimplePlugin_iBusRsp_inputBeforeStage_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready); + assign IBusSimplePlugin_injector_decodeInput_valid = _zz_100_; + assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_101_; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_102_; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_103_; + assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_104_; + assign _zz_89_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst); + assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_1; + assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_2; + assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_3; + assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_4; + assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = (IBusSimplePlugin_injector_decodeInput_valid && (! IBusSimplePlugin_injector_decodeRemoved)); + assign _zz_88_ = IBusSimplePlugin_injector_decodeInput_payload_pc; + assign _zz_87_ = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + assign _zz_86_ = (decode_PC + (32'b00000000000000000000000000000100)); + assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; + assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; + assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; + assign IBusSimplePlugin_pendingCmdNext = (_zz_193_ - _zz_197_); + always @ (*) begin + IBusSimplePlugin_cmd_valid = ((IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) && (IBusSimplePlugin_pendingCmd != (3'b111))); + if(_zz_172_)begin + IBusSimplePlugin_cmd_valid = 1'b0; + end + end + + assign IBusSimplePlugin_mmuBus_cmd_isValid = IBusSimplePlugin_iBusRsp_stages_0_input_valid; + assign IBusSimplePlugin_mmuBus_cmd_virtualAddress = IBusSimplePlugin_iBusRsp_stages_0_input_payload; + assign IBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0; + assign IBusSimplePlugin_mmuBus_end = ((IBusSimplePlugin_iBusRsp_stages_0_output_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) || IBusSimplePlugin_fetcherflushIt); + assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_mmuBus_rsp_physicalAddress[31 : 2],(2'b00)}; + assign iBus_rsp_takeWhen_valid = (iBus_rsp_valid && (! (IBusSimplePlugin_rspJoin_discardCounter != (3'b000)))); + assign iBus_rsp_takeWhen_payload_error = iBus_rsp_payload_error; + assign iBus_rsp_takeWhen_payload_inst = iBus_rsp_payload_inst; + assign IBusSimplePlugin_rspJoin_rspBufferOutput_valid = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; + assign IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + assign IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload; + always @ (*) begin + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error; + if((! IBusSimplePlugin_rspJoin_rspBufferOutput_valid))begin + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0; + end + end + + assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst; + always @ (*) begin + IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; + if(_zz_173_)begin + IBusSimplePlugin_rspJoin_exceptionDetected = 1'b1; + end + end + + always @ (*) begin + IBusSimplePlugin_rspJoin_redoRequired = 1'b0; + if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_mmu_joinCtx_refilling))begin + IBusSimplePlugin_rspJoin_redoRequired = 1'b1; + end + end + + assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBufferOutput_valid); + assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc; + assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; + assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; + assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready) : IBusSimplePlugin_rspJoin_join_ready); + assign IBusSimplePlugin_rspJoin_rspBufferOutput_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); + assign _zz_105_ = (! (IBusSimplePlugin_rspJoin_exceptionDetected || IBusSimplePlugin_rspJoin_redoRequired)); + assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_inputBeforeStage_ready && _zz_105_); + assign IBusSimplePlugin_iBusRsp_inputBeforeStage_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_105_); + assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; + assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; + assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; + assign IBusSimplePlugin_redoBranch_valid = (IBusSimplePlugin_rspJoin_redoRequired && IBusSimplePlugin_iBusRsp_readyForError); + assign IBusSimplePlugin_redoBranch_payload = decode_PC; + always @ (*) begin + IBusSimplePlugin_decodeExceptionPort_payload_code = (4'bxxxx); + if(_zz_173_)begin + IBusSimplePlugin_decodeExceptionPort_payload_code = (4'b1100); + end + end + + assign IBusSimplePlugin_decodeExceptionPort_payload_badAddr = {IBusSimplePlugin_rspJoin_join_payload_pc[31 : 2],(2'b00)}; + assign IBusSimplePlugin_decodeExceptionPort_valid = (IBusSimplePlugin_rspJoin_exceptionDetected && IBusSimplePlugin_iBusRsp_readyForError); + assign _zz_106_ = 1'b0; + assign _zz_83_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0)))); + always @ (*) begin + execute_DBusSimplePlugin_skipCmd = 1'b0; + if(execute_ALIGNEMENT_FAULT)begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + if((execute_MMU_FAULT || execute_MMU_RSP_refilling))begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + end + + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_106_)); + assign dBus_cmd_payload_wr = execute_MEMORY_STORE; + assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_107_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_107_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_107_ = execute_RS2[31 : 0]; + end + endcase + end + + assign dBus_cmd_payload_data = _zz_107_; + assign _zz_82_ = dBus_cmd_payload_address[1 : 0]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_108_ = (4'b0001); + end + 2'b01 : begin + _zz_108_ = (4'b0011); + end + default : begin + _zz_108_ = (4'b1111); + end + endcase + end + + assign execute_DBusSimplePlugin_formalMask = (_zz_108_ <<< dBus_cmd_payload_address[1 : 0]); + assign DBusSimplePlugin_mmuBus_cmd_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign DBusSimplePlugin_mmuBus_cmd_virtualAddress = execute_SRC_ADD; + assign DBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0; + assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; + assign _zz_81_ = ((execute_MMU_RSP_exception || ((! execute_MMU_RSP_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP_allowRead) && (! execute_MEMORY_STORE))); + assign _zz_74_ = DBusSimplePlugin_mmuBus_rsp_physicalAddress; + assign _zz_75_ = DBusSimplePlugin_mmuBus_rsp_isIoAccess; + assign _zz_76_ = DBusSimplePlugin_mmuBus_rsp_allowRead; + assign _zz_77_ = DBusSimplePlugin_mmuBus_rsp_allowWrite; + assign _zz_78_ = DBusSimplePlugin_mmuBus_rsp_allowExecute; + assign _zz_79_ = DBusSimplePlugin_mmuBus_rsp_exception; + assign _zz_80_ = DBusSimplePlugin_mmuBus_rsp_refilling; + assign _zz_73_ = dBus_rsp_data; + always @ (*) begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + if(_zz_174_)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + if(memory_ALIGNEMENT_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + if(memory_MMU_RSP_refilling)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + end else begin + if(memory_MMU_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + end + if(_zz_175_)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + end + end + + always @ (*) begin + DBusSimplePlugin_memoryExceptionPort_payload_code = (4'bxxxx); + if(_zz_174_)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = (4'b0101); + end + if(memory_ALIGNEMENT_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_202_}; + end + if(! memory_MMU_RSP_refilling) begin + if(memory_MMU_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? (4'b1111) : (4'b1101)); + end + end + end + + assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; + always @ (*) begin + DBusSimplePlugin_redoBranch_valid = 1'b0; + if(memory_MMU_RSP_refilling)begin + DBusSimplePlugin_redoBranch_valid = 1'b1; + end + if(_zz_175_)begin + DBusSimplePlugin_redoBranch_valid = 1'b0; + end + end + + assign DBusSimplePlugin_redoBranch_payload = memory_PC; + always @ (*) begin + writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; + end + 2'b10 : begin + writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; + end + 2'b11 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_109_ = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_110_[31] = _zz_109_; + _zz_110_[30] = _zz_109_; + _zz_110_[29] = _zz_109_; + _zz_110_[28] = _zz_109_; + _zz_110_[27] = _zz_109_; + _zz_110_[26] = _zz_109_; + _zz_110_[25] = _zz_109_; + _zz_110_[24] = _zz_109_; + _zz_110_[23] = _zz_109_; + _zz_110_[22] = _zz_109_; + _zz_110_[21] = _zz_109_; + _zz_110_[20] = _zz_109_; + _zz_110_[19] = _zz_109_; + _zz_110_[18] = _zz_109_; + _zz_110_[17] = _zz_109_; + _zz_110_[16] = _zz_109_; + _zz_110_[15] = _zz_109_; + _zz_110_[14] = _zz_109_; + _zz_110_[13] = _zz_109_; + _zz_110_[12] = _zz_109_; + _zz_110_[11] = _zz_109_; + _zz_110_[10] = _zz_109_; + _zz_110_[9] = _zz_109_; + _zz_110_[8] = _zz_109_; + _zz_110_[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_111_ = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_112_[31] = _zz_111_; + _zz_112_[30] = _zz_111_; + _zz_112_[29] = _zz_111_; + _zz_112_[28] = _zz_111_; + _zz_112_[27] = _zz_111_; + _zz_112_[26] = _zz_111_; + _zz_112_[25] = _zz_111_; + _zz_112_[24] = _zz_111_; + _zz_112_[23] = _zz_111_; + _zz_112_[22] = _zz_111_; + _zz_112_[21] = _zz_111_; + _zz_112_[20] = _zz_111_; + _zz_112_[19] = _zz_111_; + _zz_112_[18] = _zz_111_; + _zz_112_[17] = _zz_111_; + _zz_112_[16] = _zz_111_; + _zz_112_[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_188_) + 2'b00 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_110_; + end + 2'b01 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_112_; + end + default : begin + writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; + end + endcase + end + + assign IBusSimplePlugin_mmuBus_rsp_physicalAddress = IBusSimplePlugin_mmuBus_cmd_virtualAddress; + assign IBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusSimplePlugin_mmuBus_rsp_isIoAccess = IBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusSimplePlugin_mmuBus_rsp_exception = 1'b0; + assign IBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusSimplePlugin_mmuBus_busy = 1'b0; + assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_virtualAddress; + assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; + assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusSimplePlugin_mmuBus_busy = 1'b0; + assign _zz_114_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000)); + assign _zz_115_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); + assign _zz_116_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); + assign _zz_117_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); + assign _zz_113_ = {(_zz_114_ != (1'b0)),{(((decode_INSTRUCTION & _zz_245_) == (32'b00000000000000000000000000010000)) != (1'b0)),{((_zz_246_ == _zz_247_) != (1'b0)),{(_zz_248_ != (1'b0)),{(_zz_249_ != _zz_250_),{_zz_251_,{_zz_252_,_zz_253_}}}}}}}; + assign _zz_71_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_345_) == (32'b00000000000000000001000001110011)),{(_zz_346_ == _zz_347_),{_zz_348_,{_zz_349_,_zz_350_}}}}}}} != (20'b00000000000000000000)); + assign _zz_118_ = _zz_113_[1 : 0]; + assign _zz_70_ = _zz_118_; + assign _zz_69_ = _zz_203_[0]; + assign _zz_68_ = _zz_204_[0]; + assign _zz_67_ = _zz_205_[0]; + assign _zz_66_ = _zz_206_[0]; + assign _zz_119_ = _zz_113_[8 : 7]; + assign _zz_65_ = _zz_119_; + assign _zz_64_ = _zz_207_[0]; + assign _zz_63_ = _zz_208_[0]; + assign _zz_120_ = _zz_113_[12 : 11]; + assign _zz_62_ = _zz_120_; + assign _zz_61_ = _zz_209_[0]; + assign _zz_121_ = _zz_113_[15 : 14]; + assign _zz_60_ = _zz_121_; + assign _zz_122_ = _zz_113_[17 : 16]; + assign _zz_59_ = _zz_122_; + assign _zz_123_ = _zz_113_[19 : 18]; + assign _zz_58_ = _zz_123_; + assign _zz_57_ = _zz_210_[0]; + assign _zz_56_ = _zz_211_[0]; + assign _zz_124_ = _zz_113_[23 : 22]; + assign _zz_55_ = _zz_124_; + assign _zz_54_ = _zz_212_[0]; + assign _zz_53_ = _zz_213_[0]; + assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = (4'b0010); + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_161_; + assign decode_RegFilePlugin_rs2Data = _zz_162_; + assign _zz_52_ = decode_RegFilePlugin_rs1Data; + assign _zz_51_ = decode_RegFilePlugin_rs2Data; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_49_ && writeBack_arbitration_isFiring); + if(_zz_125_)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + assign lastStageRegFileWrite_payload_address = _zz_48_[11 : 7]; + assign lastStageRegFileWrite_payload_data = _zz_72_; + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_126_ = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_126_ = {31'd0, _zz_214_}; + end + default : begin + _zz_126_ = execute_SRC_ADD_SUB; + end + endcase + end + + assign _zz_46_ = _zz_126_; + assign _zz_44_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_127_ = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_127_ = {29'd0, _zz_215_}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_127_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + end + default : begin + _zz_127_ = {27'd0, _zz_216_}; + end + endcase + end + + assign _zz_43_ = _zz_127_; + assign _zz_128_ = _zz_217_[11]; + always @ (*) begin + _zz_129_[19] = _zz_128_; + _zz_129_[18] = _zz_128_; + _zz_129_[17] = _zz_128_; + _zz_129_[16] = _zz_128_; + _zz_129_[15] = _zz_128_; + _zz_129_[14] = _zz_128_; + _zz_129_[13] = _zz_128_; + _zz_129_[12] = _zz_128_; + _zz_129_[11] = _zz_128_; + _zz_129_[10] = _zz_128_; + _zz_129_[9] = _zz_128_; + _zz_129_[8] = _zz_128_; + _zz_129_[7] = _zz_128_; + _zz_129_[6] = _zz_128_; + _zz_129_[5] = _zz_128_; + _zz_129_[4] = _zz_128_; + _zz_129_[3] = _zz_128_; + _zz_129_[2] = _zz_128_; + _zz_129_[1] = _zz_128_; + _zz_129_[0] = _zz_128_; + end + + assign _zz_130_ = _zz_218_[11]; + always @ (*) begin + _zz_131_[19] = _zz_130_; + _zz_131_[18] = _zz_130_; + _zz_131_[17] = _zz_130_; + _zz_131_[16] = _zz_130_; + _zz_131_[15] = _zz_130_; + _zz_131_[14] = _zz_130_; + _zz_131_[13] = _zz_130_; + _zz_131_[12] = _zz_130_; + _zz_131_[11] = _zz_130_; + _zz_131_[10] = _zz_130_; + _zz_131_[9] = _zz_130_; + _zz_131_[8] = _zz_130_; + _zz_131_[7] = _zz_130_; + _zz_131_[6] = _zz_130_; + _zz_131_[5] = _zz_130_; + _zz_131_[4] = _zz_130_; + _zz_131_[3] = _zz_130_; + _zz_131_[2] = _zz_130_; + _zz_131_[1] = _zz_130_; + _zz_131_[0] = _zz_130_; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_132_ = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_132_ = {_zz_129_,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_132_ = {_zz_131_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_132_ = _zz_39_; + end + endcase + end + + assign _zz_41_ = _zz_132_; + always @ (*) begin + execute_SrcPlugin_addSub = _zz_219_; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign _zz_38_ = execute_SrcPlugin_addSub; + assign _zz_37_ = execute_SrcPlugin_addSub; + assign _zz_36_ = execute_SrcPlugin_less; + assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); + assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); + assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); + assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000)); + always @ (*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_133_ = (execute_LightShifterPlugin_shiftInput <<< 1); + end + default : begin + _zz_133_ = _zz_226_; + end + endcase + end + + always @ (*) begin + _zz_134_ = 1'b0; + if(_zz_137_)begin + if((_zz_138_ == decode_INSTRUCTION[19 : 15]))begin + _zz_134_ = 1'b1; + end + end + if(_zz_176_)begin + if(_zz_177_)begin + if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + _zz_134_ = 1'b1; + end + end + end + if(_zz_178_)begin + if(_zz_179_)begin + if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + _zz_134_ = 1'b1; + end + end + end + if(_zz_180_)begin + if(_zz_181_)begin + if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + _zz_134_ = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_134_ = 1'b0; + end + end + + always @ (*) begin + _zz_135_ = 1'b0; + if(_zz_137_)begin + if((_zz_138_ == decode_INSTRUCTION[24 : 20]))begin + _zz_135_ = 1'b1; + end + end + if(_zz_176_)begin + if(_zz_177_)begin + if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin + _zz_135_ = 1'b1; + end + end + end + if(_zz_178_)begin + if(_zz_179_)begin + if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin + _zz_135_ = 1'b1; + end + end + end + if(_zz_180_)begin + if(_zz_181_)begin + if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin + _zz_135_ = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_135_ = 1'b0; + end + end + + assign _zz_136_ = (_zz_49_ && writeBack_arbitration_isFiring); + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_139_ = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_139_ == (3'b000))) begin + _zz_140_ = execute_BranchPlugin_eq; + end else if((_zz_139_ == (3'b001))) begin + _zz_140_ = (! execute_BranchPlugin_eq); + end else if((((_zz_139_ & (3'b101)) == (3'b101)))) begin + _zz_140_ = (! execute_SRC_LESS); + end else begin + _zz_140_ = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_141_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_141_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_141_ = 1'b1; + end + default : begin + _zz_141_ = _zz_140_; + end + endcase + end + + assign _zz_33_ = _zz_141_; + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); + assign _zz_142_ = _zz_228_[19]; + always @ (*) begin + _zz_143_[10] = _zz_142_; + _zz_143_[9] = _zz_142_; + _zz_143_[8] = _zz_142_; + _zz_143_[7] = _zz_142_; + _zz_143_[6] = _zz_142_; + _zz_143_[5] = _zz_142_; + _zz_143_[4] = _zz_142_; + _zz_143_[3] = _zz_142_; + _zz_143_[2] = _zz_142_; + _zz_143_[1] = _zz_142_; + _zz_143_[0] = _zz_142_; + end + + assign _zz_144_ = _zz_229_[11]; + always @ (*) begin + _zz_145_[19] = _zz_144_; + _zz_145_[18] = _zz_144_; + _zz_145_[17] = _zz_144_; + _zz_145_[16] = _zz_144_; + _zz_145_[15] = _zz_144_; + _zz_145_[14] = _zz_144_; + _zz_145_[13] = _zz_144_; + _zz_145_[12] = _zz_144_; + _zz_145_[11] = _zz_144_; + _zz_145_[10] = _zz_144_; + _zz_145_[9] = _zz_144_; + _zz_145_[8] = _zz_144_; + _zz_145_[7] = _zz_144_; + _zz_145_[6] = _zz_144_; + _zz_145_[5] = _zz_144_; + _zz_145_[4] = _zz_144_; + _zz_145_[3] = _zz_144_; + _zz_145_[2] = _zz_144_; + _zz_145_[1] = _zz_144_; + _zz_145_[0] = _zz_144_; + end + + assign _zz_146_ = _zz_230_[11]; + always @ (*) begin + _zz_147_[18] = _zz_146_; + _zz_147_[17] = _zz_146_; + _zz_147_[16] = _zz_146_; + _zz_147_[15] = _zz_146_; + _zz_147_[14] = _zz_146_; + _zz_147_[13] = _zz_146_; + _zz_147_[12] = _zz_146_; + _zz_147_[11] = _zz_146_; + _zz_147_[10] = _zz_146_; + _zz_147_[9] = _zz_146_; + _zz_147_[8] = _zz_146_; + _zz_147_[7] = _zz_146_; + _zz_147_[6] = _zz_146_; + _zz_147_[5] = _zz_146_; + _zz_147_[4] = _zz_146_; + _zz_147_[3] = _zz_146_; + _zz_147_[2] = _zz_146_; + _zz_147_[1] = _zz_146_; + _zz_147_[0] = _zz_146_; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_148_ = {{_zz_143_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_148_ = {_zz_145_,execute_INSTRUCTION[31 : 20]}; + end + default : begin + _zz_148_ = {{_zz_147_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + end + endcase + end + + assign execute_BranchPlugin_branch_src2 = _zz_148_; + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign _zz_31_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); + assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; + always @ (*) begin + CsrPlugin_privilege = (2'b11); + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = (2'b11); + end + end + + assign CsrPlugin_misa_base = (2'b01); + assign CsrPlugin_misa_extensions = (26'b00000000000000000001000010); + assign _zz_149_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_150_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_151_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_152_ = {decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid}; + assign _zz_153_ = _zz_231_[0]; + assign _zz_154_ = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_155_ = _zz_233_[0]; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_166_)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(_zz_168_)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(writeBack_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_lastStageWasWfi = 1'b0; + always @ (*) begin + CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusSimplePlugin_pcValids_3); + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = (2'bxx); + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign _zz_29_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); + assign _zz_28_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); + assign execute_CsrPlugin_inWfi = 1'b0; + assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001100000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001101000001 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001100000101 : begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b001101000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001101000011 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b111111000000 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b001100000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001101000010 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + default : begin + end + endcase + if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + CsrPlugin_selfException_valid = 1'b0; + if(_zz_182_)begin + CsrPlugin_selfException_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_selfException_payload_code = (4'bxxxx); + if(_zz_182_)begin + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = (4'b1000); + end + default : begin + CsrPlugin_selfException_payload_code = (4'b1011); + end + endcase + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + always @ (*) begin + execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + execute_CsrPlugin_readData[31 : 0] = _zz_156_; + end + 12'b001100000000 : begin + execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; + end + 12'b001101000001 : begin + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; + end + 12'b001100000101 : begin + end + 12'b001101000100 : begin + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; + end + 12'b001101000011 : begin + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; + end + 12'b111111000000 : begin + execute_CsrPlugin_readData[31 : 0] = _zz_157_; + end + 12'b001100000100 : begin + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; + end + 12'b001101000010 : begin + execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; + execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + default : begin + end + endcase + end + + assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_189_) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign _zz_157_ = (_zz_156_ & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_157_ != (32'b00000000000000000000000000000000)); + assign _zz_25_ = decode_ALU_BITWISE_CTRL; + assign _zz_23_ = _zz_58_; + assign _zz_47_ = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_22_ = decode_SHIFT_CTRL; + assign _zz_20_ = _zz_70_; + assign _zz_35_ = decode_to_execute_SHIFT_CTRL; + assign _zz_19_ = decode_ALU_CTRL; + assign _zz_17_ = _zz_60_; + assign _zz_45_ = decode_to_execute_ALU_CTRL; + assign _zz_16_ = decode_BRANCH_CTRL; + assign _zz_14_ = _zz_59_; + assign _zz_32_ = decode_to_execute_BRANCH_CTRL; + assign _zz_13_ = decode_SRC1_CTRL; + assign _zz_11_ = _zz_65_; + assign _zz_42_ = decode_to_execute_SRC1_CTRL; + assign _zz_10_ = decode_ENV_CTRL; + assign _zz_7_ = execute_ENV_CTRL; + assign _zz_5_ = memory_ENV_CTRL; + assign _zz_8_ = _zz_55_; + assign _zz_27_ = decode_to_execute_ENV_CTRL; + assign _zz_26_ = execute_to_memory_ENV_CTRL; + assign _zz_30_ = memory_to_writeBack_ENV_CTRL; + assign _zz_3_ = decode_SRC2_CTRL; + assign _zz_1_ = _zz_62_; + assign _zz_40_ = decode_to_execute_SRC2_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000))); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000))); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00))); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0))); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + assign iBus_cmd_ready = ((1'b1 && (! iBus_cmd_m2sPipe_valid)) || iBus_cmd_m2sPipe_ready); + assign iBus_cmd_m2sPipe_valid = _zz_158_; + assign iBus_cmd_m2sPipe_payload_pc = _zz_159_; + assign iBusWishbone_ADR = (iBus_cmd_m2sPipe_payload_pc >>> 2); + assign iBusWishbone_CTI = (3'b000); + assign iBusWishbone_BTE = (2'b00); + assign iBusWishbone_SEL = (4'b1111); + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + assign iBusWishbone_CYC = iBus_cmd_m2sPipe_valid; + assign iBusWishbone_STB = iBus_cmd_m2sPipe_valid; + assign iBus_cmd_m2sPipe_ready = (iBus_cmd_m2sPipe_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = (iBusWishbone_CYC && iBusWishbone_ACK); + assign iBus_rsp_payload_inst = iBusWishbone_DAT_MISO; + assign iBus_rsp_payload_error = 1'b0; + assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; + assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; + assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; + assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; + assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; + assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; + assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); + assign dBusWishbone_CTI = (3'b000); + assign dBusWishbone_BTE = (2'b00); + always @ (*) begin + case(dBus_cmd_halfPipe_payload_size) + 2'b00 : begin + _zz_160_ = (4'b0001); + end + 2'b01 : begin + _zz_160_ = (4'b0011); + end + default : begin + _zz_160_ = (4'b1111); + end + endcase + end + + always @ (*) begin + dBusWishbone_SEL = _zz_241_[3:0]; + if((! dBus_cmd_halfPipe_payload_wr))begin + dBusWishbone_SEL = (4'b1111); + end + end + + assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; + assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; + assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); + assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid; + assign dBusWishbone_STB = dBus_cmd_halfPipe_valid; + assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); + assign dBus_rsp_data = dBusWishbone_DAT_MISO; + assign dBus_rsp_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusSimplePlugin_fetchPc_pcReg <= externalResetVector; + IBusSimplePlugin_fetchPc_booted <= 1'b0; + IBusSimplePlugin_fetchPc_inc <= 1'b0; + _zz_99_ <= 1'b0; + _zz_100_ <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusSimplePlugin_injector_decodeRemoved <= 1'b0; + IBusSimplePlugin_pendingCmd <= (3'b000); + IBusSimplePlugin_rspJoin_discardCounter <= (3'b000); + _zz_125_ <= 1'b1; + execute_LightShifterPlugin_isActive <= 1'b0; + _zz_137_ <= 1'b0; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + _zz_156_ <= (32'b00000000000000000000000000000000); + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); + memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); + _zz_158_ <= 1'b0; + dBus_cmd_halfPipe_regs_valid <= 1'b0; + dBus_cmd_halfPipe_regs_ready <= 1'b1; + end else begin + IBusSimplePlugin_fetchPc_booted <= 1'b1; + if((IBusSimplePlugin_fetchPc_corrected || IBusSimplePlugin_fetchPc_pcRegPropagate))begin + IBusSimplePlugin_fetchPc_inc <= 1'b0; + end + if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_inc <= 1'b0; + end + if((IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetcherflushIt) || IBusSimplePlugin_fetchPc_pcRegPropagate)))begin + IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc; + end + if(IBusSimplePlugin_fetcherflushIt)begin + _zz_99_ <= 1'b0; + end + if(_zz_97_)begin + _zz_99_ <= IBusSimplePlugin_iBusRsp_stages_0_output_valid; + end + if(IBusSimplePlugin_iBusRsp_inputBeforeStage_ready)begin + _zz_100_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_valid; + end + if(IBusSimplePlugin_fetcherflushIt)begin + _zz_100_ <= 1'b0; + end + if(IBusSimplePlugin_fetcherflushIt)begin + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)))begin + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusSimplePlugin_fetcherflushIt)begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusSimplePlugin_injector_decodeInput_ready)))begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0; + end + if(IBusSimplePlugin_fetcherflushIt)begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusSimplePlugin_fetcherflushIt)begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1; + end + if(IBusSimplePlugin_fetcherflushIt)begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusSimplePlugin_fetcherflushIt)begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2; + end + if(IBusSimplePlugin_fetcherflushIt)begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusSimplePlugin_fetcherflushIt)begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= IBusSimplePlugin_injector_nextPcCalc_valids_3; + end + if(IBusSimplePlugin_fetcherflushIt)begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(decode_arbitration_removeIt)begin + IBusSimplePlugin_injector_decodeRemoved <= 1'b1; + end + if(IBusSimplePlugin_fetcherflushIt)begin + IBusSimplePlugin_injector_decodeRemoved <= 1'b0; + end + IBusSimplePlugin_pendingCmd <= IBusSimplePlugin_pendingCmdNext; + IBusSimplePlugin_rspJoin_discardCounter <= (IBusSimplePlugin_rspJoin_discardCounter - _zz_199_); + if(IBusSimplePlugin_fetcherflushIt)begin + IBusSimplePlugin_rspJoin_discardCounter <= (IBusSimplePlugin_pendingCmd - _zz_201_); + end + _zz_125_ <= 1'b0; + if(_zz_164_)begin + if(_zz_167_)begin + execute_LightShifterPlugin_isActive <= 1'b1; + if(execute_LightShifterPlugin_done)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + end + end + if(execute_arbitration_removeIt)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + _zz_137_ <= _zz_136_; + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_183_)begin + if(_zz_184_)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_185_)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_186_)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_169_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_170_)begin + case(_zz_171_) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= ({_zz_151_,{_zz_150_,_zz_149_}} != (3'b000)); + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= memory_REGFILE_WRITE_DATA; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + if(execute_CsrPlugin_writeEnable)begin + _zz_156_ <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000000 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_235_[0]; + CsrPlugin_mstatus_MIE <= _zz_236_[0]; + end + end + 12'b001101000001 : begin + end + 12'b001100000101 : begin + end + 12'b001101000100 : begin + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001100000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_238_[0]; + CsrPlugin_mie_MTIE <= _zz_239_[0]; + CsrPlugin_mie_MSIE <= _zz_240_[0]; + end + end + 12'b001101000010 : begin + end + default : begin + end + endcase + if(iBus_cmd_ready)begin + _zz_158_ <= iBus_cmd_valid; + end + if(_zz_187_)begin + dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; + dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); + end else begin + dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); + dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + end + end + end + + always @ (posedge clk) begin + if(IBusSimplePlugin_iBusRsp_inputBeforeStage_ready)begin + _zz_101_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc; + _zz_102_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error; + _zz_103_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst; + _zz_104_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc; + end + if(IBusSimplePlugin_injector_decodeInput_ready)begin + IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst; + end + if(IBusSimplePlugin_iBusRsp_stages_1_output_ready)begin + IBusSimplePlugin_mmu_joinCtx_physicalAddress <= IBusSimplePlugin_mmuBus_rsp_physicalAddress; + IBusSimplePlugin_mmu_joinCtx_isIoAccess <= IBusSimplePlugin_mmuBus_rsp_isIoAccess; + IBusSimplePlugin_mmu_joinCtx_allowRead <= IBusSimplePlugin_mmuBus_rsp_allowRead; + IBusSimplePlugin_mmu_joinCtx_allowWrite <= IBusSimplePlugin_mmuBus_rsp_allowWrite; + IBusSimplePlugin_mmu_joinCtx_allowExecute <= IBusSimplePlugin_mmuBus_rsp_allowExecute; + IBusSimplePlugin_mmu_joinCtx_exception <= IBusSimplePlugin_mmuBus_rsp_exception; + IBusSimplePlugin_mmu_joinCtx_refilling <= IBusSimplePlugin_mmuBus_rsp_refilling; + end + if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin + $display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend"); + end + if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin + $display("ERROR DBusSimplePlugin doesn't allow writeback stage stall when read happend"); + end + if(_zz_164_)begin + if(_zz_167_)begin + execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001)); + end + end + if(_zz_136_)begin + _zz_138_ <= _zz_48_[11 : 7]; + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + end + if(_zz_166_)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_153_ ? IBusSimplePlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_153_ ? IBusSimplePlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + end + if(_zz_168_)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_155_ ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_155_ ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); + end + if(_zz_183_)begin + if(_zz_184_)begin + CsrPlugin_interrupt_code <= (4'b0111); + CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(_zz_185_)begin + CsrPlugin_interrupt_code <= (4'b0011); + CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(_zz_186_)begin + CsrPlugin_interrupt_code <= (4'b1011); + CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + end + if(_zz_169_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_24_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_21_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MMU_RSP_physicalAddress <= execute_MMU_RSP_physicalAddress; + execute_to_memory_MMU_RSP_isIoAccess <= execute_MMU_RSP_isIoAccess; + execute_to_memory_MMU_RSP_allowRead <= execute_MMU_RSP_allowRead; + execute_to_memory_MMU_RSP_allowWrite <= execute_MMU_RSP_allowWrite; + execute_to_memory_MMU_RSP_allowExecute <= execute_MMU_RSP_allowExecute; + execute_to_memory_MMU_RSP_exception <= execute_MMU_RSP_exception; + execute_to_memory_MMU_RSP_refilling <= execute_MMU_RSP_refilling; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_18_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_15_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_12_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_9_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_6_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_4_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_85_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_84_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_39_; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_34_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_2_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + end + 12'b001100000000 : begin + end + 12'b001101000001 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000101 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + 12'b001101000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_237_[0]; + end + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001100000100 : begin + end + 12'b001101000010 : begin + end + default : begin + end + endcase + if(iBus_cmd_ready)begin + _zz_159_ <= iBus_cmd_payload_pc; + end + if(_zz_187_)begin + dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; + dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; + dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; + dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + end + end + +endmodule + diff --git a/litedram/extras/fusesoc-add-files.py b/litedram/extras/fusesoc-add-files.py new file mode 100644 index 0000000..60e9642 --- /dev/null +++ b/litedram/extras/fusesoc-add-files.py @@ -0,0 +1,45 @@ +#!/usr/bin/python3 +from fusesoc.capi2.generator import Generator +import os +import sys +import pathlib + +class LiteDRAMGenerator(Generator): + def run(self): + board = self.config.get('board') + + # Collect a bunch of directory path + script_dir = os.path.dirname(sys.argv[0]) + base_dir = os.path.join(script_dir, os.pardir) + gen_dir = os.path.join(base_dir, "generated", board) + extras_dir = os.path.join(base_dir, "extras") + + print("Adding LiteDRAM for board... ", board) + + # Grab init-cpu.txt if it exists + cpu_file = os.path.join(gen_dir, "init-cpu.txt") + if os.path.exists(cpu_file): + cpu = pathlib.Path(cpu_file).read_text() + else: + cpu = None + + # Add files to fusesoc + files = [] + f = os.path.join(gen_dir, "litedram_core.v") + files.append({f : {'file_type' : 'verilogSource'}}) + f = os.path.join(gen_dir, "litedram-wrapper.vhdl") + files.append({f : {'file_type' : 'vhdlSource-2008'}}) + f = os.path.join(gen_dir, "litedram_core.init") + files.append({f : {'file_type' : 'user'}}) + + # Look for init CPU types and add corresponding files + if cpu == "vexriscv": + f = os.path.join(base_dir, "extras", "VexRiscv.v") + files.append({f : {'file_type' : 'verilogSource'}}) + + self.add_files(files) + +g = LiteDRAMGenerator() +g.run() +g.write() + diff --git a/litedram/gen-src/arty.yml b/litedram/gen-src/arty.yml new file mode 100644 index 0000000..e82316a --- /dev/null +++ b/litedram/gen-src/arty.yml @@ -0,0 +1,42 @@ +# This file is Copyright (c) 2018-2019 Florent Kermarrec +# License: BSD + +{ + # General ------------------------------------------------------------------ + "cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32) + "cpu_variant":"minimal", + "speedgrade": -1, # FPGA speedgrade + "memtype": "DDR3", # DRAM type + + # PHY ---------------------------------------------------------------------- + "cmd_delay": 0, # Command additional delay (in taps) + "cmd_latency": 0, # Command additional latency + "sdram_module": "MT41K128M16", # SDRAM modules of the board or SO-DIMM + "sdram_module_nb": 2, # Number of byte groups + "sdram_rank_nb": 1, # Number of ranks + "sdram_phy": "A7DDRPHY", # Type of FPGA PHY + + # Electrical --------------------------------------------------------------- + "rtt_nom": "60ohm", # Nominal termination + "rtt_wr": "60ohm", # Write termination + "ron": "34ohm", # Output driver impedance + + # Frequency ---------------------------------------------------------------- + "input_clk_freq": 100e6, # Input clock frequency + "sys_clk_freq": 100e6, # System clock frequency (DDR_clk = 4 x sys_clk) + "iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency + + # Core --------------------------------------------------------------------- + "cmd_buffer_depth": 16, # Depth of the command buffer + + # User Ports --------------------------------------------------------------- + "user_ports": { + "native_0": { + "type": "native", + }, + }, + + # CSR Port ----------------------------------------------------------------- + "csr_expose": "False", # expose access to CSR (I/O) ports + "csr_align" : 32, # CSR alignment +} diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py new file mode 100755 index 0000000..37ee427 --- /dev/null +++ b/litedram/gen-src/generate.py @@ -0,0 +1,150 @@ +#!/usr/bin/python3 + +from fusesoc.capi2.generator import Generator +from litex.build.tools import write_to_file +from litex.build.tools import replace_in_file +from litex.build.generic_platform import * +from litex.build.xilinx import XilinxPlatform +from litex.build.lattice import LatticePlatform +from litex.soc.integration.builder import * +from litedram.gen import * +import subprocess +import os +import sys +import yaml +import shutil + +def make_new_dir(base, added): + r = os.path.join(base, added) + if os.path.exists(r): + shutil.rmtree(r) + os.mkdir(r) + return r + +gen_src_dir = os.path.dirname(os.path.realpath(__file__)) +base_dir = os.path.join(gen_src_dir, os.pardir) +build_top_dir = make_new_dir(base_dir, "build") +gen_src_dir = os.path.join(base_dir, "gen-src") +gen_dir = make_new_dir(base_dir, "generated") + +# Build the init code for microwatt-initialized DRAM +# +# XXX Not working yet +# +def build_init_code(build_dir): + + # More path fudging + sw_dir = os.path.join(build_dir, "software"); + sw_inc_dir = os.path.join(build_dir, "include") + gen_inc_dir = os.path.join(sw_inc_dir, "generated") + src_dir = os.path.join(gen_src_dir, "sdram_init") + lxbios_src_dir = os.path.join(soc_directory, "software", "bios") + lxbios_inc_dir = os.path.join(soc_directory, "software", "include") + print(" sw dir:", sw_dir) + print("gen_inc_dir:", gen_inc_dir) + print(" src dir:", src_dir) + print(" lx src dir:", lxbios_src_dir) + print(" lx inc dir:", lxbios_inc_dir) + + # Generate mem.h + mem_h = "#define MAIN_RAM_BASE 0x40000000" + write_to_file(os.path.join(gen_inc_dir, "mem.h"), mem_h) + + # Environment + env_vars = [] + def _makefile_escape(s): # From LiteX + return s.replace("\\", "\\\\") + def add_var(k, v): + env_vars.append("{}={}\n".format(k, _makefile_escape(v))) + + add_var("BUILD_DIR", sw_dir) + add_var("SRC_DIR", src_dir) + add_var("GENINC_DIR", gen_inc_dir) + add_var("LXSRC_DIR", lxbios_src_dir) + add_var("LXINC_DIR", lxbios_inc_dir) + write_to_file(os.path.join(gen_inc_dir, "variables.mak"), "".join(env_vars)) + + # Build init code + print(" Generating init software...") + makefile = os.path.join(src_dir, "Makefile") + r = subprocess.check_call(["make", "-C", build_dir, "-I", gen_inc_dir, "-f", makefile]) + print("Make result:", r) + + return os.path.join(sw_dir, "obj", "sdram_init.hex") + +def generate_one(t): + + print("Generating target:", t) + + # Muck with directory path + build_dir = make_new_dir(build_top_dir, t) + t_dir = make_new_dir(gen_dir, t) + + # Grab config file + cfile = os.path.join(gen_src_dir, t + ".yml") + core_config = yaml.load(open(cfile).read(), Loader=yaml.Loader) + + ### TODO: Make most stuff below a function in litedram gen.py and + ### call it rather than duplicate it + ### + + # Convert YAML elements to Python/LiteX + for k, v in core_config.items(): + replaces = {"False": False, "True": True, "None": None} + for r in replaces.keys(): + if v == r: + core_config[k] = replaces[r] + if "clk_freq" in k: + core_config[k] = float(core_config[k]) + if k == "sdram_module": + core_config[k] = getattr(litedram_modules, core_config[k]) + if k == "sdram_phy": + core_config[k] = getattr(litedram_phys, core_config[k]) + + # Generate core + if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]: + platform = LatticePlatform("LFE5UM5G-45F-8BG381C", io=[], toolchain="trellis") + elif core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]: + platform = XilinxPlatform("", io=[], toolchain="vivado") + else: + raise ValueError("Unsupported SDRAM PHY: {}".format(core_config["sdram_phy"])) + + soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000) + + # Build into build_dir + builder = Builder(soc, output_dir=build_dir, compile_gateware=False) + vns = builder.build(build_name="litedram_core", regular_comb=False) + + # Grab generated gatewar dir + gw_dir = os.path.join(build_dir, "gateware") + + # Generate init-cpu.txt if any and generate init code if none + cpu = core_config["cpu"] + if cpu is None: + print("Microwatt based inits not supported yet !") + src_wrap_file = os.path.join(gen_src_dir, "wrapper-mw-init.vhdl") + src_init_file = build_init_code(build_dir) + else: + write_to_file(os.path.join(t_dir, "init-cpu.txt"), cpu) + src_wrap_file = os.path.join(gen_src_dir, "wrapper-self-init.vhdl") + src_init_file = os.path.join(gw_dir, "mem.init") + + # Copy generated files to target dir, amend them if necessary + core_file = os.path.join(gw_dir, "litedram_core.v") + dst_init_file = os.path.join(t_dir, "litedram_core.init") + dst_wrap_file = os.path.join(t_dir, "litedram-wrapper.vhdl") + replace_in_file(core_file, "mem.init", "litedram_core.init") + shutil.copy(core_file, t_dir) + shutil.copyfile(src_init_file, dst_init_file) + shutil.copyfile(src_wrap_file, dst_wrap_file) + +def main(): + + targets = ['arty','nexys-video'] + for t in targets: + generate_one(t) + + # XXX TODO: Remove build dir unless told not to via cmdline option + +if __name__ == "__main__": + main() diff --git a/litedram/gen-src/nexys-video.yml b/litedram/gen-src/nexys-video.yml new file mode 100644 index 0000000..640ccab --- /dev/null +++ b/litedram/gen-src/nexys-video.yml @@ -0,0 +1,42 @@ +# This file is Copyright (c) 2018-2019 Florent Kermarrec +# License: BSD + +{ + # General ------------------------------------------------------------------ + "cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32) + "cpu_variant":"minimal", + "speedgrade": -1, # FPGA speedgrade + "memtype": "DDR3", # DRAM type + + # PHY ---------------------------------------------------------------------- + "cmd_delay": 0, # Command additional delay (in taps) + "cmd_latency": 0, # Command additional latency + "sdram_module": "MT41K256M16", # SDRAM modules of the board or SO-DIMM + "sdram_module_nb": 2, # Number of byte groups + "sdram_rank_nb": 1, # Number of ranks + "sdram_phy": "A7DDRPHY", # Type of FPGA PHY + + # Electrical --------------------------------------------------------------- + "rtt_nom": "60ohm", # Nominal termination + "rtt_wr": "60ohm", # Write termination + "ron": "34ohm", # Output driver impedance + + # Frequency ---------------------------------------------------------------- + "input_clk_freq": 100e6, # Input clock frequency + "sys_clk_freq": 100e6, # System clock frequency (DDR_clk = 4 x sys_clk) + "iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency + + # Core --------------------------------------------------------------------- + "cmd_buffer_depth": 16, # Depth of the command buffer + + # User Ports --------------------------------------------------------------- + "user_ports": { + "native_0": { + "type": "native", + }, + }, + + # CSR Port ----------------------------------------------------------------- + "csr_expose": "False", # expose access to CSR (I/O) ports + "csr_align" : 32, # 64-bit alignment +} diff --git a/litedram/gen-src/sdram_init/Makefile b/litedram/gen-src/sdram_init/Makefile new file mode 100644 index 0000000..ce57732 --- /dev/null +++ b/litedram/gen-src/sdram_init/Makefile @@ -0,0 +1,75 @@ +#### Directories + +include variables.mak +OBJ = $(BUILD_DIR)/obj + +PROGRAM = sdram_init +OBJECTS = $(OBJ)/head.o $(OBJ)/main.o $(OBJ)/sdram.o + +#### Compiler + +ARCH = $(shell uname -m) +ifneq ("$(ARCH)", "ppc64") +ifneq ("$(ARCH)", "ppc64le") + CROSS_COMPILE = powerpc64le-linux-gnu- + endif + endif + +CC = $(CROSS_COMPILE)gcc +LD = $(CROSS_COMPILE)ld +OBJCOPY = $(CROSS_COMPILE)objcopy + +#### Flags + +CPPFLAGS = -nostdinc +CPPFLAGS += -I$(SRC_DIR)/libc/include -I$(LXSRC_DIR) -I$(LXINC_DIR) -I$(GENINC_DIR) -I$(SRC_DIR)/include +CPPFLAGS += -isystem $(shell $(CC) -print-file-name=include) +CFLAGS = -Os -g -Wall -std=c99 -m64 -mabi=elfv2 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections -fno-delete-null-pointer-checks +ASFLAGS = $(CPPFLAGS) $(CFLAGS) +LDFLAGS = -static -nostdlib -Ttext-segment=0xffff0000 -T $(SRC_DIR)/$(PROGRAM).lds --gc-sections + +#### Pretty print + +ifeq ($(VERBOSE),1) +define Q + $(2) +endef +else +define Q + @echo " [$1] $(3)" + @$(2) +endef +endif + +#### Rules. This is a bit crappy, I'm sure we can do better with the +#### handling of the various path, but this will have to do +#### until I can be bothered getting my head around the finer +#### points of Makefiles + +all: objdir $(OBJ)/$(PROGRAM).hex + +$(OBJ)/sdram.o: $(LXSRC_DIR)/sdram.c + $(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@) +$(OBJ)/%.o : $(SRC_DIR)/%.S + $(call Q,AS, $(CC) $(ASFLAGS) -c $< -o $@, $@) +$(OBJ)/%.o : $(SRC_DIR)/%.c + $(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@) +$(OBJ)/%.o : $(SRC_DIR)/libc/src/%.c + $(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@) + +LIBC_SRC := $(wildcard $(SRC_DIR)/libc/src/*.c) +LIBC_OBJ := $(patsubst $(SRC_DIR)/libc/src/%.c, $(OBJ)/%.o,$(LIBC_SRC)) +$(OBJ)/libc.o: $(LIBC_OBJ) + $(call Q,LD, $(LD) -r -o $@ $^, $@) + +$(OBJ)/$(PROGRAM).elf: $(OBJECTS) $(OBJ)/libc.o + $(call Q,LD, $(LD) $(LDFLAGS) -o $@ $^, $@) + +$(OBJ)/$(PROGRAM).bin: $(OBJ)/$(PROGRAM).elf + $(call Q,OC, $(OBJCOPY) -O binary -S $^ $@, $@) + +$(OBJ)/$(PROGRAM).hex: $(OBJ)/$(PROGRAM).bin + $(call Q,HX, $(SRC_DIR)/bin2hex.py $^ > $@, $@) + +objdir: + @mkdir -p $(OBJ) diff --git a/litedram/gen-src/sdram_init/bin2hex.py b/litedram/gen-src/sdram_init/bin2hex.py new file mode 100755 index 0000000..af278bc --- /dev/null +++ b/litedram/gen-src/sdram_init/bin2hex.py @@ -0,0 +1,17 @@ +#!/usr/bin/python3 + +import sys +import subprocess +import struct + +with open(sys.argv[1], "rb") as f: + while True: + word = f.read(8) + if len(word) == 8: + print("%016x" % struct.unpack('Q', word)); + elif len(word) == 4: + print("00000000%08x" % struct.unpack('I', word)); + elif len(word) == 0: + exit(0); + else: + raise Exception("Bad length") diff --git a/litedram/gen-src/sdram_init/head.S b/litedram/gen-src/sdram_init/head.S new file mode 100644 index 0000000..2c750f9 --- /dev/null +++ b/litedram/gen-src/sdram_init/head.S @@ -0,0 +1,102 @@ +/* Copyright 2013-2014 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define STACK_TOP 0xffff4000 + +#define FIXUP_ENDIAN \ + tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ + b 191f; /* Skip trampoline if endian is good */ \ + .long 0xa600607d; /* mfmsr r11 */ \ + .long 0x01006b69; /* xori r11,r11,1 */ \ + .long 0x05009f42; /* bcl 20,31,$+4 */ \ + .long 0xa602487d; /* mflr r10 */ \ + .long 0x14004a39; /* addi r10,r10,20 */ \ + .long 0xa64b5a7d; /* mthsrr0 r10 */ \ + .long 0xa64b7b7d; /* mthsrr1 r11 */ \ + .long 0x2402004c; /* hrfid */ \ +191: + + +/* Load an immediate 64-bit value into a register */ +#define LOAD_IMM64(r, e) \ + lis r,(e)@highest; \ + ori r,r,(e)@higher; \ + rldicr r,r, 32, 31; \ + oris r,r, (e)@h; \ + ori r,r, (e)@l; + + .section ".head","ax" + + . = 0 +.global start +start: + FIXUP_ENDIAN + + /* setup stack */ + LOAD_IMM64(%r1, STACK_TOP - 0x100) + LOAD_IMM64(%r12, main) + mtctr %r12, + bctrl + ba 0 + + /* XXX: litedram init should not take exceptions, maybe we could get + * rid of these to save space, along with a core tweak to suppress + * exceptions in case they happen (just terminate ?) + */ + +#define EXCEPTION(nr) \ + .= nr; \ + b . + + /* More exception stubs */ + EXCEPTION(0x100) + EXCEPTION(0x200) + EXCEPTION(0x300) + EXCEPTION(0x380) + EXCEPTION(0x400) + EXCEPTION(0x480) + EXCEPTION(0x500) + EXCEPTION(0x600) + EXCEPTION(0x700) + EXCEPTION(0x800) + EXCEPTION(0x900) + EXCEPTION(0x980) + EXCEPTION(0xa00) + EXCEPTION(0xb00) + EXCEPTION(0xc00) + EXCEPTION(0xd00) + EXCEPTION(0xe00) + EXCEPTION(0xe20) + EXCEPTION(0xe40) + EXCEPTION(0xe60) + EXCEPTION(0xe80) + EXCEPTION(0xf00) + EXCEPTION(0xf20) + EXCEPTION(0xf40) + EXCEPTION(0xf60) + EXCEPTION(0xf80) +#if 0 + EXCEPTION(0x1000) + EXCEPTION(0x1100) + EXCEPTION(0x1200) + EXCEPTION(0x1300) + EXCEPTION(0x1400) + EXCEPTION(0x1500) + EXCEPTION(0x1600) +#endif + + .text + diff --git a/litedram/gen-src/sdram_init/include/system.h b/litedram/gen-src/sdram_init/include/system.h new file mode 100644 index 0000000..b5df315 --- /dev/null +++ b/litedram/gen-src/sdram_init/include/system.h @@ -0,0 +1,3 @@ +static inline void flush_cpu_dcache(void) { } +static inline void flush_l2_cache(void) { } + diff --git a/litedram/gen-src/sdram_init/libc/include/assert.h b/litedram/gen-src/sdram_init/libc/include/assert.h new file mode 100644 index 0000000..2c49fd7 --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/include/assert.h @@ -0,0 +1,29 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008, 2012 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#ifndef _ASSERT_H +#define _ASSERT_H + +#define assert(cond) \ + do { if (!(cond)) { \ + assert_fail(__FILE__ \ + ":" stringify(__LINE__) \ + ":" stringify(cond)); } \ + } while(0) + +void __attribute__((noreturn)) assert_fail(const char *msg); + +#define stringify(expr) stringify_1(expr) +/* Double-indirection required to stringify expansions */ +#define stringify_1(expr) #expr + +#endif diff --git a/litedram/gen-src/sdram_init/libc/include/compiler.h b/litedram/gen-src/sdram_init/libc/include/compiler.h new file mode 100644 index 0000000..c36b14f --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/include/compiler.h @@ -0,0 +1,54 @@ +/* Copyright 2013-2014 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __COMPILER_H +#define __COMPILER_H + +#ifndef __ASSEMBLY__ + +#include + +/* Macros for various compiler bits and pieces */ +#define __packed __attribute__((packed)) +#define __align(x) __attribute__((__aligned__(x))) +#define __unused __attribute__((unused)) +#define __used __attribute__((used)) +#define __section(x) __attribute__((__section__(x))) +#define __noreturn __attribute__((noreturn)) +/* not __const as this has a different meaning (const) */ +#define __attrconst __attribute__((const)) +#define __warn_unused_result __attribute__((warn_unused_result)) +#define __noinline __attribute__((noinline)) + +#if 0 /* Provided by gcc stddef.h */ +#define offsetof(type,m) __builtin_offsetof(type,m) +#endif + +#define __nomcount __attribute__((no_instrument_function)) + +/* Compiler barrier */ +static inline void barrier(void) +{ +// asm volatile("" : : : "memory"); +} + +#endif /* __ASSEMBLY__ */ + +/* Stringification macro */ +#define __tostr(x) #x +#define tostr(x) __tostr(x) + +#endif /* __COMPILER_H */ diff --git a/litedram/gen-src/sdram_init/libc/include/ctype.h b/litedram/gen-src/sdram_init/libc/include/ctype.h new file mode 100644 index 0000000..60c98b0 --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/include/ctype.h @@ -0,0 +1,26 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#ifndef _CTYPE_H +#define _CTYPE_H + +#include + +int __attrconst isdigit(int c); +int __attrconst isxdigit(int c); +int __attrconst isprint(int c); +int __attrconst isspace(int c); + +int __attrconst tolower(int c); +int __attrconst toupper(int c); + +#endif diff --git a/litedram/gen-src/sdram_init/libc/include/errno.h b/litedram/gen-src/sdram_init/libc/include/errno.h new file mode 100644 index 0000000..c2bd987 --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/include/errno.h @@ -0,0 +1,36 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#ifndef _ERRNO_H +#define _ERRNO_H + +extern int errno; + +/* + * Error number definitions + */ +#define EPERM 1 /* not permitted */ +#define ENOENT 2 /* file or directory not found */ +#define EIO 5 /* input/output error */ +#define EBADF 9 /* Bad file number */ +#define ENOMEM 12 /* not enough space */ +#define EACCES 13 /* permission denied */ +#define EFAULT 14 /* bad address */ +#define EBUSY 16 /* resource busy */ +#define EEXIST 17 /* file already exists */ +#define ENODEV 19 /* device not found */ +#define EINVAL 22 /* invalid argument */ +#define EDOM 33 /* math argument out of domain of func */ +#define ERANGE 34 /* math result not representable */ +#define ENOSYS 38 /* Function not implemented */ + +#endif diff --git a/litedram/gen-src/sdram_init/libc/include/stdint.h b/litedram/gen-src/sdram_init/libc/include/stdint.h new file mode 100644 index 0000000..2a2c1d9 --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/include/stdint.h @@ -0,0 +1,30 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#ifndef _STDINT_H +#define _STDINT_H + +typedef unsigned char uint8_t; +typedef signed char int8_t; + +typedef unsigned short uint16_t; +typedef signed short int16_t; + +typedef unsigned int uint32_t; +typedef signed int int32_t; + +typedef unsigned long long uint64_t; +typedef signed long long int64_t; + +typedef unsigned long int uintptr_t; + +#endif diff --git a/litedram/gen-src/sdram_init/libc/include/stdio.h b/litedram/gen-src/sdram_init/libc/include/stdio.h new file mode 100644 index 0000000..764d755 --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/include/stdio.h @@ -0,0 +1,35 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#ifndef _STDIO_H +#define _STDIO_H + +#include +#include "stddef.h" + +#define EOF (-1) + +int _printf(const char *format, ...) __attribute__((format (printf, 1, 2))); + +#ifndef pr_fmt +#define pr_fmt(fmt) fmt +#endif + +#define printf(f, ...) do { _printf(pr_fmt(f), ##__VA_ARGS__); } while(0) + +int snprintf(char *str, size_t size, const char *format, ...) __attribute__((format (printf, 3, 4))); +int vsnprintf(char *str, size_t size, const char *format, va_list); + +int putchar(int ch); +int puts(const char *str); + +#endif diff --git a/litedram/gen-src/sdram_init/libc/include/stdlib.h b/litedram/gen-src/sdram_init/libc/include/stdlib.h new file mode 100644 index 0000000..f5d8b31 --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/include/stdlib.h @@ -0,0 +1,25 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#ifndef _STDLIB_H +#define _STDLIB_H + +#include "stddef.h" + +#define RAND_MAX 32767 + +int atoi(const char *str); +long atol(const char *str); +unsigned long int strtoul(const char *nptr, char **endptr, int base); +long int strtol(const char *nptr, char **endptr, int base); + +#endif diff --git a/litedram/gen-src/sdram_init/libc/include/string.h b/litedram/gen-src/sdram_init/libc/include/string.h new file mode 100644 index 0000000..2172bdc --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/include/string.h @@ -0,0 +1,45 @@ +/****************************************************************************** + * Copyright (c) 2004, 2016 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#ifndef _STRING_H +#define _STRING_H + +#include "stddef.h" + +char *strcpy(char *dest, const char *src); +char *strncpy(char *dest, const char *src, size_t n); +char *strcat(char *dest, const char *src); +int strcmp(const char *s1, const char *s2); +int strncmp(const char *s1, const char *s2, size_t n); +int strcasecmp(const char *s1, const char *s2); +int strncasecmp(const char *s1, const char *s2, size_t n); +char *strchr(const char *s, int c); +char *strrchr(const char *s, int c); +size_t strlen(const char *s); +size_t strnlen(const char *s, size_t n); +char *strstr(const char *hay, const char *needle); +char *strtok(char *src, const char *pattern); +char *strdup(const char *src); + +void *memset(void *s, int c, size_t n); +void *memchr(const void *s, int c, size_t n); +void *memcpy(void *dest, const void *src, size_t n); +void *memcpy_from_ci(void *destpp, const void *srcpp, size_t len); +void *memmove(void *dest, const void *src, size_t n); +int memcmp(const void *s1, const void *s2, size_t n); + +static inline int ffs(unsigned long val) +{ + return __builtin_ffs(val); +} + +#endif diff --git a/litedram/gen-src/sdram_init/libc/include/unistd.h b/litedram/gen-src/sdram_init/libc/include/unistd.h new file mode 100644 index 0000000..bc53472 --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/include/unistd.h @@ -0,0 +1,26 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#ifndef _UNISTD_H +#define _UNISTD_H + +#include + +typedef long ssize_t; + +extern int open(const char *name, int flags); +extern int close(int fd); +extern ssize_t read(int fd, void *buf, size_t count); +extern ssize_t write(int fd, const void *buf, size_t count); +extern ssize_t lseek(int fd, long offset, int whence); + +#endif diff --git a/litedram/gen-src/sdram_init/libc/src/isdigit.c b/litedram/gen-src/sdram_init/libc/src/isdigit.c new file mode 100644 index 0000000..68cd4eb --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/isdigit.c @@ -0,0 +1,26 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include +#include + +int __attrconst isdigit(int ch) +{ + switch (ch) { + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + return 1; + + default: + return 0; + } +} diff --git a/litedram/gen-src/sdram_init/libc/src/isprint.c b/litedram/gen-src/sdram_init/libc/src/isprint.c new file mode 100644 index 0000000..0a7c94c --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/isprint.c @@ -0,0 +1,19 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include +#include + +int __attrconst isprint(int ch) +{ + return (ch >= 32 && ch < 127); +} diff --git a/litedram/gen-src/sdram_init/libc/src/isspace.c b/litedram/gen-src/sdram_init/libc/src/isspace.c new file mode 100644 index 0000000..f9fa36a --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/isspace.c @@ -0,0 +1,30 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include +#include + +int __attrconst isspace(int ch) +{ + switch (ch) { + case ' ': + case '\f': + case '\n': + case '\r': + case '\t': + case '\v': + return 1; + + default: + return 0; + } +} diff --git a/litedram/gen-src/sdram_init/libc/src/isxdigit.c b/litedram/gen-src/sdram_init/libc/src/isxdigit.c new file mode 100644 index 0000000..d3c7388 --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/isxdigit.c @@ -0,0 +1,22 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include +#include + +int __attrconst isxdigit(int ch) +{ + return ( + (ch >= '0' && ch <= '9') | + (ch >= 'A' && ch <= 'F') | + (ch >= 'a' && ch <= 'f') ); +} diff --git a/litedram/gen-src/sdram_init/libc/src/memchr.c b/litedram/gen-src/sdram_init/libc/src/memchr.c new file mode 100644 index 0000000..db9a147 --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/memchr.c @@ -0,0 +1,28 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include + +void *memchr(const void *ptr, int c, size_t n); +void *memchr(const void *ptr, int c, size_t n) +{ + unsigned char ch = (unsigned char)c; + const unsigned char *p = ptr; + + while (n-- > 0) { + if (*p == ch) + return (void *)p; + p += 1; + } + + return NULL; +} diff --git a/litedram/gen-src/sdram_init/libc/src/memcmp.c b/litedram/gen-src/sdram_init/libc/src/memcmp.c new file mode 100644 index 0000000..b270b59 --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/memcmp.c @@ -0,0 +1,29 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include + +int memcmp(const void *ptr1, const void *ptr2, size_t n); +int memcmp(const void *ptr1, const void *ptr2, size_t n) +{ + const unsigned char *p1 = ptr1; + const unsigned char *p2 = ptr2; + + while (n-- > 0) { + if (*p1 != *p2) + return (*p1 - *p2); + p1 += 1; + p2 += 1; + } + + return 0; +} diff --git a/litedram/gen-src/sdram_init/libc/src/memcpy.c b/litedram/gen-src/sdram_init/libc/src/memcpy.c new file mode 100644 index 0000000..3ab0490 --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/memcpy.c @@ -0,0 +1,36 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include +#include + +void *memcpy(void *dest, const void *src, size_t n); +void *memcpy(void *dest, const void *src, size_t n) +{ + void *ret = dest; + + while (n >= 8) { + *(uint64_t *)dest = *(uint64_t *)src; + dest += 8; + src += 8; + n -= 8; + } + + while (n > 0) { + *(uint8_t *)dest = *(uint8_t *)src; + dest += 1; + src += 1; + n -= 1; + } + + return ret; +} diff --git a/litedram/gen-src/sdram_init/libc/src/memmove.c b/litedram/gen-src/sdram_init/libc/src/memmove.c new file mode 100644 index 0000000..76aef6c --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/memmove.c @@ -0,0 +1,36 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include + +void *memcpy(void *dest, const void *src, size_t n); +void *memmove(void *dest, const void *src, size_t n); +void *memmove(void *dest, const void *src, size_t n) +{ + /* Do the buffers overlap in a bad way? */ + if (src < dest && src + n >= dest) { + char *cdest; + const char *csrc; + int i; + + /* Copy from end to start */ + cdest = dest + n - 1; + csrc = src + n - 1; + for (i = 0; i < n; i++) { + *cdest-- = *csrc--; + } + return dest; + } else { + /* Normal copy is possible */ + return memcpy(dest, src, n); + } +} diff --git a/litedram/gen-src/sdram_init/libc/src/memset.c b/litedram/gen-src/sdram_init/libc/src/memset.c new file mode 100644 index 0000000..80eea11 --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/memset.c @@ -0,0 +1,40 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#define CACHE_LINE_SIZE 128 + +#include + +void *memset(void *dest, int c, size_t size); +void *memset(void *dest, int c, size_t size) +{ + unsigned char *d = (unsigned char *)dest; + unsigned long big_c = 0; + + if (c) { + big_c = c; + big_c |= (big_c << 8) | big_c; + big_c |= (big_c << 16) | big_c; + big_c |= (big_c << 32) | big_c; + } + while (size >= 8 && c == 0) { + *((unsigned long *)d) = big_c; + d+=8; + size-=8; + } + + while (size-- > 0) { + *d++ = (unsigned char)c; + } + + return dest; +} diff --git a/litedram/gen-src/sdram_init/libc/src/strcasecmp.c b/litedram/gen-src/sdram_init/libc/src/strcasecmp.c new file mode 100644 index 0000000..ba1aedb --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/strcasecmp.c @@ -0,0 +1,27 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include + +int strcasecmp(const char *s1, const char *s2); +int strcasecmp(const char *s1, const char *s2) +{ + while (*s1 != 0 && *s2 != 0) { + if (toupper(*s1) != toupper(*s2)) + break; + ++s1; + ++s2; + } + + return *s1 - *s2; +} + diff --git a/litedram/gen-src/sdram_init/libc/src/strcat.c b/litedram/gen-src/sdram_init/libc/src/strcat.c new file mode 100644 index 0000000..329cc88 --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/strcat.c @@ -0,0 +1,26 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include + +size_t strlen(const char *s); +char *strcpy(char *dst, const char *src); +char *strcat(char *dst, const char *src); +char *strcat(char *dst, const char *src) +{ + size_t p; + + p = strlen(dst); + strcpy(&dst[p], src); + + return dst; +} diff --git a/litedram/gen-src/sdram_init/libc/src/strchr.c b/litedram/gen-src/sdram_init/libc/src/strchr.c new file mode 100644 index 0000000..88f25f9 --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/strchr.c @@ -0,0 +1,28 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include + +char *strchr(const char *s, int c); +char *strchr(const char *s, int c) +{ + char cb = c; + + while (*s != 0) { + if (*s == cb) { + return (char *)s; + } + s += 1; + } + + return NULL; +} diff --git a/litedram/gen-src/sdram_init/libc/src/strcmp.c b/litedram/gen-src/sdram_init/libc/src/strcmp.c new file mode 100644 index 0000000..5afbae2 --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/strcmp.c @@ -0,0 +1,25 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +int strcmp(const char *s1, const char *s2); +int strcmp(const char *s1, const char *s2) +{ + while (*s1 != 0 && *s2 != 0) { + if (*s1 != *s2) + break; + s1 += 1; + s2 += 1; + } + + return *s1 - *s2; +} + diff --git a/litedram/gen-src/sdram_init/libc/src/strcpy.c b/litedram/gen-src/sdram_init/libc/src/strcpy.c new file mode 100644 index 0000000..514be17 --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/strcpy.c @@ -0,0 +1,23 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +char *strcpy(char *dst, const char *src); +char *strcpy(char *dst, const char *src) +{ + char *ptr = dst; + + do { + *ptr++ = *src; + } while (*src++ != 0); + + return dst; +} diff --git a/litedram/gen-src/sdram_init/libc/src/strlen.c b/litedram/gen-src/sdram_init/libc/src/strlen.c new file mode 100644 index 0000000..f3c5a83 --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/strlen.c @@ -0,0 +1,40 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include + +size_t strlen(const char *s); +size_t strlen(const char *s) +{ + size_t len = 0; + + while (*s != 0) { + len += 1; + s += 1; + } + + return len; +} + +size_t strnlen(const char *s, size_t n); +size_t strnlen(const char *s, size_t n) +{ + size_t len = 0; + + while (*s != 0 && n) { + len += 1; + s += 1; + n--; + } + + return len; +} diff --git a/litedram/gen-src/sdram_init/libc/src/strncasecmp.c b/litedram/gen-src/sdram_init/libc/src/strncasecmp.c new file mode 100644 index 0000000..c6b158e --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/strncasecmp.c @@ -0,0 +1,30 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include + +int strncasecmp(const char *s1, const char *s2, size_t n); +int strncasecmp(const char *s1, const char *s2, size_t n) +{ + if (n < 1) + return 0; + + while (*s1 != 0 && *s2 != 0 && --n > 0) { + if (toupper(*s1) != toupper(*s2)) + break; + ++s1; + ++s2; + } + + return toupper(*s1) - toupper(*s2); +} + diff --git a/litedram/gen-src/sdram_init/libc/src/strncmp.c b/litedram/gen-src/sdram_init/libc/src/strncmp.c new file mode 100644 index 0000000..a5422c0 --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/strncmp.c @@ -0,0 +1,30 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include + +int strncmp(const char *s1, const char *s2, size_t n); +int strncmp(const char *s1, const char *s2, size_t n) +{ + if (n < 1) + return 0; + + while (*s1 != 0 && *s2 != 0 && --n > 0) { + if (*s1 != *s2) + break; + s1 += 1; + s2 += 1; + } + + return *s1 - *s2; +} + diff --git a/litedram/gen-src/sdram_init/libc/src/strncpy.c b/litedram/gen-src/sdram_init/libc/src/strncpy.c new file mode 100644 index 0000000..621c89b --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/strncpy.c @@ -0,0 +1,33 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include + +char *strncpy(char *dst, const char *src, size_t n); +char *strncpy(char *dst, const char *src, size_t n) +{ + char *ret = dst; + + /* Copy string */ + while (*src != 0 && n > 0) { + *dst++ = *src++; + n -= 1; + } + + /* strncpy always clears the rest of destination string... */ + while (n > 0) { + *dst++ = 0; + n -= 1; + } + + return ret; +} diff --git a/litedram/gen-src/sdram_init/libc/src/strrchr.c b/litedram/gen-src/sdram_init/libc/src/strrchr.c new file mode 100644 index 0000000..262a682 --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/strrchr.c @@ -0,0 +1,28 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008, 2019 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include + +char *strrchr(const char *s, int c); +char *strrchr(const char *s, int c) +{ + char *last = NULL; + char cb = c; + + while (*s != 0) { + if (*s == cb) + last = (char *)s; + s += 1; + } + + return last; +} diff --git a/litedram/gen-src/sdram_init/libc/src/strstr.c b/litedram/gen-src/sdram_init/libc/src/strstr.c new file mode 100644 index 0000000..cd9ccae --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/strstr.c @@ -0,0 +1,39 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include + +size_t strlen(const char *s); +int strncmp(const char *s1, const char *s2, size_t n); +char *strstr(const char *hay, const char *needle); +char *strstr(const char *hay, const char *needle) +{ + char *pos; + size_t hlen, nlen; + + if (hay == NULL || needle == NULL) + return NULL; + + hlen = strlen(hay); + nlen = strlen(needle); + if (nlen < 1) + return (char *)hay; + + for (pos = (char *)hay; pos < hay + hlen; pos++) { + if (strncmp(pos, needle, nlen) == 0) { + return pos; + } + } + + return NULL; +} + diff --git a/litedram/gen-src/sdram_init/libc/src/strtok.c b/litedram/gen-src/sdram_init/libc/src/strtok.c new file mode 100644 index 0000000..fcc3fce --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/strtok.c @@ -0,0 +1,48 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include + +char *strtok(char *src, const char *pattern); +char *strtok(char *src, const char *pattern) +{ + static char *nxtTok; + char *retVal = NULL; + + if (!src) { + src = nxtTok; + if (!src) + return retVal; + } + + while (*src) { + const char *pp = pattern; + while (*pp) { + if (*pp == *src) { + break; + } + pp++; + } + if (!*pp) { + if (!retVal) + retVal = src; + else if (!src[-1]) + break; + } else + *src = '\0'; + src++; + } + + nxtTok = src; + + return retVal; +} diff --git a/litedram/gen-src/sdram_init/libc/src/strtol.c b/litedram/gen-src/sdram_init/libc/src/strtol.c new file mode 100644 index 0000000..c7c52af --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/strtol.c @@ -0,0 +1,113 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include + +long int strtol(const char *S, char **PTR,int BASE) +{ + long rval = 0; + short int negative = 0; + short int digit; + // *PTR is S, unless PTR is NULL, in which case i override it with my own ptr + char* ptr; + if (PTR == NULL) + { + //override + PTR = &ptr; + } + // i use PTR to advance through the string + *PTR = (char *) S; + //check if BASE is ok + if ((BASE < 0) || BASE > 36) + { + return 0; + } + // ignore white space at beginning of S + while ((**PTR == ' ') + || (**PTR == '\t') + || (**PTR == '\n') + || (**PTR == '\r') + ) + { + (*PTR)++; + } + // check if S starts with "-" in which case the return value is negative + if (**PTR == '-') + { + negative = 1; + (*PTR)++; + } + // if BASE is 0... determine the base from the first chars... + if (BASE == 0) + { + // if S starts with "0x", BASE = 16, else 10 + if ((**PTR == '0') && (*((*PTR)+1) == 'x')) + { + BASE = 16; + } + else + { + BASE = 10; + } + } + if (BASE == 16) + { + // S may start with "0x" + if ((**PTR == '0') && (*((*PTR)+1) == 'x')) + { + (*PTR)++; + (*PTR)++; + } + } + //until end of string + while (**PTR) + { + if (((**PTR) >= '0') && ((**PTR) <= '9')) + { + //digit (0..9) + digit = **PTR - '0'; + } + else if (((**PTR) >= 'a') && ((**PTR) <='z')) + { + //alphanumeric digit lowercase(a (10) .. z (35) ) + digit = (**PTR - 'a') + 10; + } + else if (((**PTR) >= 'A') && ((**PTR) <='Z')) + { + //alphanumeric digit uppercase(a (10) .. z (35) ) + digit = (**PTR - 'A') + 10; + } + else + { + //end of parseable number reached... + break; + } + if (digit < BASE) + { + rval = (rval * BASE) + digit; + } + else + { + //digit found, but its too big for current base + //end of parseable number reached... + break; + } + //next... + (*PTR)++; + } + if (negative) + { + return rval * -1; + } + //else + return rval; +} diff --git a/litedram/gen-src/sdram_init/libc/src/strtoul.c b/litedram/gen-src/sdram_init/libc/src/strtoul.c new file mode 100644 index 0000000..e6e63ae --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/strtoul.c @@ -0,0 +1,103 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include + +unsigned long int strtoul(const char *S, char **PTR,int BASE) +{ + unsigned long rval = 0; + short int digit; + // *PTR is S, unless PTR is NULL, in which case i override it with my own ptr + char* ptr; + if (PTR == NULL) + { + //override + PTR = &ptr; + } + // i use PTR to advance through the string + *PTR = (char *) S; + //check if BASE is ok + if ((BASE < 0) || BASE > 36) + { + return 0; + } + // ignore white space at beginning of S + while ((**PTR == ' ') + || (**PTR == '\t') + || (**PTR == '\n') + || (**PTR == '\r') + ) + { + (*PTR)++; + } + // if BASE is 0... determine the base from the first chars... + if (BASE == 0) + { + // if S starts with "0x", BASE = 16, else 10 + if ((**PTR == '0') && (*((*PTR)+1) == 'x')) + { + BASE = 16; + } + else + { + BASE = 10; + } + } + if (BASE == 16) + { + // S may start with "0x" + if ((**PTR == '0') && (*((*PTR)+1) == 'x')) + { + (*PTR)++; + (*PTR)++; + } + } + //until end of string + while (**PTR) + { + if (((**PTR) >= '0') && ((**PTR) <='9')) + { + //digit (0..9) + digit = **PTR - '0'; + } + else if (((**PTR) >= 'a') && ((**PTR) <='z')) + { + //alphanumeric digit lowercase(a (10) .. z (35) ) + digit = (**PTR - 'a') + 10; + } + else if (((**PTR) >= 'A') && ((**PTR) <='Z')) + { + //alphanumeric digit uppercase(a (10) .. z (35) ) + digit = (**PTR - 'A') + 10; + } + else + { + //end of parseable number reached... + break; + } + if (digit < BASE) + { + rval = (rval * BASE) + digit; + } + else + { + //digit found, but its too big for current base + //end of parseable number reached... + break; + } + //next... + (*PTR)++; + } + //done + return rval; +} + diff --git a/litedram/gen-src/sdram_init/libc/src/tolower.c b/litedram/gen-src/sdram_init/libc/src/tolower.c new file mode 100644 index 0000000..398a1eb --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/tolower.c @@ -0,0 +1,19 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include +#include + +int __attrconst tolower(int c) +{ + return (((c >= 'A') && (c <= 'Z')) ? (c - 'A' + 'a' ) : c); +} diff --git a/litedram/gen-src/sdram_init/libc/src/toupper.c b/litedram/gen-src/sdram_init/libc/src/toupper.c new file mode 100644 index 0000000..6b52363 --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/toupper.c @@ -0,0 +1,21 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include +#include "ctype.h" + +int __attrconst toupper (int cha) +{ + if((cha >= 'a') && (cha <= 'z')) + return(cha - 'a' + 'A'); + return(cha); +} diff --git a/litedram/gen-src/sdram_init/libc/src/vsnprintf.c b/litedram/gen-src/sdram_init/libc/src/vsnprintf.c new file mode 100644 index 0000000..034ccab --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/src/vsnprintf.c @@ -0,0 +1,304 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#include +#include +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "ctype.h" +#include + +static const unsigned long long convert[] = { + 0x0, 0xFF, 0xFFFF, 0xFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFFFFULL, 0xFFFFFFFFFFFFULL, 0xFFFFFFFFFFFFFFULL, 0xFFFFFFFFFFFFFFFFULL +}; + +static int +print_str_fill(char **buffer, size_t bufsize, char *sizec, + const char *str, char c) +{ + size_t i, sizei, len; + char *bstart = *buffer; + + sizei = strtoul(sizec, NULL, 10); + len = strlen(str); + if (sizei > len) { + for (i = 0; + (i < (sizei - len)) && ((*buffer - bstart) < bufsize); + i++) { + **buffer = c; + *buffer += 1; + } + } + return 1; +} + +static int +print_str(char **buffer, size_t bufsize, const char *str) +{ + char *bstart = *buffer; + size_t i; + + for (i = 0; (i < strlen(str)) && ((*buffer - bstart) < bufsize); i++) { + **buffer = str[i]; + *buffer += 1; + } + return 1; +} + +static unsigned int __attrconst +print_intlen(unsigned long value, unsigned short int base) +{ + int i = 0; + + while (value > 0) { + if (base == 16) + value >>= 4; + else + value /= base; + i++; + } + if (i == 0) + i = 1; + return i; +} + +static int +print_itoa(char **buffer, size_t bufsize, unsigned long value, + unsigned short base, bool upper) +{ + const char zeichen[] = {'0','1','2','3','4','5','6','7','8','9','a','b','c','d','e','f'}; + char c; + int i, len; + + if(base <= 2 || base > 16) + return 0; + + len = i = print_intlen(value, base); + + /* Don't print to buffer if bufsize is not enough. */ + if (len > bufsize) + return 0; + + do { + c = zeichen[value % base]; + if (upper) + c = toupper(c); + + (*buffer)[--i] = c; + value /= base; + } while(value); + + *buffer += len; + + return 1; +} + + + +static int +print_fill(char **buffer, size_t bufsize, char *sizec, unsigned long size, + unsigned short int base, char c, int optlen) +{ + int i, sizei, len; + char *bstart = *buffer; + + sizei = strtoul(sizec, NULL, 10); + len = print_intlen(size, base) + optlen; + if (sizei > len) { + for (i = 0; + (i < (sizei - len)) && ((*buffer - bstart) < bufsize); + i++) { + **buffer = c; + *buffer += 1; + } + } + + return 0; +} + + +static int +print_format(char **buffer, size_t bufsize, const char *format, void *var) +{ + char *start; + unsigned int i = 0, length_mod = sizeof(int); + unsigned long value = 0; + unsigned long signBit; + char *form, sizec[32]; + char sign = ' '; + bool upper = false; + + form = (char *) format; + start = *buffer; + + form++; + if(*form == '0' || *form == '.') { + sign = '0'; + form++; + } + + while ((*form != '\0') && ((*buffer - start) < bufsize)) { + switch(*form) { + case 'u': + case 'd': + case 'i': + sizec[i] = '\0'; + value = (unsigned long) var; + signBit = 0x1ULL << (length_mod * 8 - 1); + if ((*form != 'u') && (signBit & value)) { + **buffer = '-'; + *buffer += 1; + value = (-(unsigned long)value) & convert[length_mod]; + } + print_fill(buffer, bufsize - (*buffer - start), + sizec, value, 10, sign, 0); + print_itoa(buffer, bufsize - (*buffer - start), + value, 10, upper); + break; + case 'X': + upper = true; + /* fallthrough */ + case 'x': + sizec[i] = '\0'; + value = (unsigned long) var & convert[length_mod]; + print_fill(buffer, bufsize - (*buffer - start), + sizec, value, 16, sign, 0); + print_itoa(buffer, bufsize - (*buffer - start), + value, 16, upper); + break; + case 'O': + case 'o': + sizec[i] = '\0'; + value = (long int) var & convert[length_mod]; + print_fill(buffer, bufsize - (*buffer - start), + sizec, value, 8, sign, 0); + print_itoa(buffer, bufsize - (*buffer - start), + value, 8, upper); + break; + case 'p': + sizec[i] = '\0'; + print_fill(buffer, bufsize - (*buffer - start), + sizec, (unsigned long) var, 16, ' ', 2); + print_str(buffer, bufsize - (*buffer - start), + "0x"); + print_itoa(buffer, bufsize - (*buffer - start), + (unsigned long) var, 16, upper); + break; + case 'c': + sizec[i] = '\0'; + print_fill(buffer, bufsize - (*buffer - start), + sizec, 1, 10, ' ', 0); + **buffer = (unsigned long) var; + *buffer += 1; + break; + case 's': + sizec[i] = '\0'; + print_str_fill(buffer, + bufsize - (*buffer - start), sizec, + (char *) var, ' '); + + print_str(buffer, bufsize - (*buffer - start), + (char *) var); + break; + case 'l': + form++; + if(*form == 'l') { + length_mod = sizeof(long long int); + } else { + form--; + length_mod = sizeof(long int); + } + break; + case 'h': + form++; + if(*form == 'h') { + length_mod = sizeof(signed char); + } else { + form--; + length_mod = sizeof(short int); + } + break; + case 'z': + length_mod = sizeof(size_t); + break; + default: + if(*form >= '0' && *form <= '9') + sizec[i++] = *form; + } + form++; + } + + + return (long int) (*buffer - start); +} + + +/* + * The vsnprintf function prints a formatted strings into a buffer. + * BUG: buffer size checking does not fully work yet + */ +int +vsnprintf(char *buffer, size_t bufsize, const char *format, va_list arg) +{ + char *ptr, *bstart; + + bstart = buffer; + ptr = (char *) format; + + /* + * Return from here if size passed is zero, otherwise we would + * overrun buffer while setting NULL character at the end. + */ + if (!buffer || !bufsize) + return 0; + + /* Leave one space for NULL character */ + bufsize--; + + while(*ptr != '\0' && (buffer - bstart) < bufsize) + { + if(*ptr == '%') { + char formstr[20]; + int i=0; + + do { + formstr[i] = *ptr; + ptr++; + i++; + } while(!(*ptr == 'd' || *ptr == 'i' || *ptr == 'u' || *ptr == 'x' || *ptr == 'X' + || *ptr == 'p' || *ptr == 'c' || *ptr == 's' || *ptr == '%' + || *ptr == 'O' || *ptr == 'o' )); + formstr[i++] = *ptr; + formstr[i] = '\0'; + if(*ptr == '%') { + *buffer++ = '%'; + } else { + print_format(&buffer, + bufsize - (buffer - bstart), + formstr, va_arg(arg, void *)); + } + ptr++; + } else { + + *buffer = *ptr; + + buffer++; + ptr++; + } + } + + *buffer = '\0'; + + return (buffer - bstart); +} diff --git a/litedram/gen-src/sdram_init/main.c b/litedram/gen-src/sdram_init/main.c new file mode 100644 index 0000000..cc8b714 --- /dev/null +++ b/litedram/gen-src/sdram_init/main.c @@ -0,0 +1,162 @@ +#include +#include +#include +#include +#include +#include + +#include "sdram.h" + +/* + * Core UART functions to implement for a port + */ + +static uint64_t potato_uart_base; + +#define PROC_FREQ 100000000 +#define UART_FREQ 115200 +#define UART_BASE 0xc0002000 +#define SYSCON_BASE 0xc0000000 + +#define POTATO_CONSOLE_TX 0x00 +#define POTATO_CONSOLE_RX 0x08 +#define POTATO_CONSOLE_STATUS 0x10 +#define POTATO_CONSOLE_STATUS_RX_EMPTY 0x01 +#define POTATO_CONSOLE_STATUS_TX_EMPTY 0x02 +#define POTATO_CONSOLE_STATUS_RX_FULL 0x04 +#define POTATO_CONSOLE_STATUS_TX_FULL 0x08 +#define POTATO_CONSOLE_CLOCK_DIV 0x18 +#define POTATO_CONSOLE_IRQ_EN 0x20 + +static inline uint8_t readb(unsigned long addr) +{ + __asm__ volatile("sync" : : : "memory"); + return *((volatile uint8_t *)addr); +} + +static inline uint64_t readq(unsigned long addr) +{ + __asm__ volatile("sync" : : : "memory"); + return *((volatile uint64_t *)addr); +} + +static inline void writeb(uint8_t val, unsigned long addr) +{ + __asm__ volatile("sync" : : : "memory"); + *((volatile uint8_t *)addr) = val; +} + +static inline void writeq(uint64_t val, unsigned long addr) +{ + __asm__ volatile("sync" : : : "memory"); + *((volatile uint64_t *)addr) = val; +} + +static uint8_t potato_uart_reg_read(int offset) +{ + return readb(potato_uart_base + offset); +} + +static void potato_uart_reg_write(int offset, uint8_t val) +{ + writeb(val, potato_uart_base + offset); +} + +static bool potato_uart_rx_empty(void) +{ + uint8_t val = potato_uart_reg_read(POTATO_CONSOLE_STATUS); + + return (val & POTATO_CONSOLE_STATUS_RX_EMPTY) != 0; +} + +static int potato_uart_tx_full(void) +{ + uint8_t val = potato_uart_reg_read(POTATO_CONSOLE_STATUS); + + return (val & POTATO_CONSOLE_STATUS_TX_FULL) != 0; +} + +static char potato_uart_read(void) +{ + return potato_uart_reg_read(POTATO_CONSOLE_RX); +} + +static void potato_uart_write(char c) +{ + potato_uart_reg_write(POTATO_CONSOLE_TX, c); +} + +static unsigned long potato_uart_divisor(unsigned long proc_freq, + unsigned long uart_freq) +{ + return proc_freq / (uart_freq * 16) - 1; +} + +void potato_uart_init(void) +{ + potato_uart_base = UART_BASE; + + potato_uart_reg_write(POTATO_CONSOLE_CLOCK_DIV, + potato_uart_divisor(PROC_FREQ, UART_FREQ)); +} + +int getchar(void) +{ + while (potato_uart_rx_empty()) + /* Do nothing */ ; + + return potato_uart_read(); +} + +int putchar(int c) +{ + while (potato_uart_tx_full()) + /* Do Nothing */; + + potato_uart_write(c); + return c; +} + +void putstr(const char *str, unsigned long len) +{ + for (unsigned long i = 0; i < len; i++) { + if (str[i] == '\n') + putchar('\r'); + putchar(str[i]); + } +} + +int _printf(const char *fmt, ...) +{ + int count; + char buffer[320]; + va_list ap; + + va_start(ap, fmt); + count = vsnprintf(buffer, sizeof(buffer), fmt, ap); + va_end(ap); + putstr(buffer, count); + return count; +} + +void flush_cpu_dcache(void) { } +void flush_cpu_icache(void) { } +void flush_l2_cache(void) { } + +void main(void) +{ + int i; + + // Let things settle ... not sure why but UART not happy otherwise + potato_uart_init(); + for (i = 0; i < 10000; i++) + potato_uart_reg_read(POTATO_CONSOLE_STATUS); + printf("Welcome to Microwatt !\n"); + printf(" SIG: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x00)); + printf(" INFO: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x08)); + printf(" BRAMINFO: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x10)); + printf(" DRAMINFO: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x18)); + printf(" CTRL: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x20)); + sdrinit(); + printf("Booting from BRAM...\n"); +} diff --git a/litedram/gen-src/sdram_init/sdram_init.lds b/litedram/gen-src/sdram_init/sdram_init.lds new file mode 100644 index 0000000..f76e77f --- /dev/null +++ b/litedram/gen-src/sdram_init/sdram_init.lds @@ -0,0 +1,12 @@ +SECTIONS +{ + . = 0xffff0000; + start = .; + .head : { + KEEP(*(.head)) + } + . = 0xffff1000; + .text : { *(.text*) *(.sfpr) *(.rodata*) } + .data : { *(.data*) } + .bss : { *(.bss*) } +} diff --git a/litedram/gen-src/wrapper-mw-init.vhdl b/litedram/gen-src/wrapper-mw-init.vhdl new file mode 100644 index 0000000..70ff006 --- /dev/null +++ b/litedram/gen-src/wrapper-mw-init.vhdl @@ -0,0 +1,303 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; + +library work; +use work.wishbone_types.all; +use work.sim_console.all; + +entity litedram_wrapper is + generic ( + DRAM_ABITS : positive; + DRAM_ALINES : positive + ); + port( + -- LiteDRAM generates the system clock and reset + -- from the input clkin + clk_in : in std_ulogic; + rst : in std_ulogic; + system_clk : out std_ulogic; + system_reset : out std_ulogic; + core_alt_reset : out std_ulogic; + pll_locked : out std_ulogic; + + -- Wishbone ports: + wb_in : in wishbone_master_out; + wb_out : out wishbone_slave_out; + wb_is_csr : in std_ulogic; + wb_is_init : in std_ulogic; + + -- Init core serial debug + serial_tx : out std_ulogic; + serial_rx : in std_ulogic; + + -- Misc + init_done : out std_ulogic; + init_error : out std_ulogic; + + -- DRAM wires + ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : out std_ulogic_vector(1 downto 0); + ddram_dqs_n : out std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic + ); +end entity litedram_wrapper; + +architecture behaviour of litedram_wrapper is + + component litedram_core port ( + clk : in std_ulogic; + rst : in std_ulogic; + pll_locked : out std_ulogic; + ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : out std_ulogic_vector(1 downto 0); + ddram_dqs_n : out std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic; + init_done : out std_ulogic; + init_error : out std_ulogic; + user_clk : out std_ulogic; + user_rst : out std_ulogic; + csr_port0_adr : in std_ulogic_vector(13 downto 0); + csr_port0_we : in std_ulogic; + csr_port0_dat_w : in std_ulogic_vector(7 downto 0); + csr_port0_dat_r : out std_ulogic_vector(7 downto 0); + user_port0_cmd_valid : in std_ulogic; + user_port0_cmd_ready : out std_ulogic; + user_port0_cmd_we : in std_ulogic; + user_port0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0); + user_port0_wdata_valid : in std_ulogic; + user_port0_wdata_ready : out std_ulogic; + user_port0_wdata_we : in std_ulogic_vector(15 downto 0); + user_port0_wdata_data : in std_ulogic_vector(127 downto 0); + user_port0_rdata_valid : out std_ulogic; + user_port0_rdata_ready : in std_ulogic; + user_port0_rdata_data : out std_ulogic_vector(127 downto 0) + ); + end component; + + signal user_port0_cmd_valid : std_ulogic; + signal user_port0_cmd_ready : std_ulogic; + signal user_port0_cmd_we : std_ulogic; + signal user_port0_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0); + signal user_port0_wdata_valid : std_ulogic; + signal user_port0_wdata_ready : std_ulogic; + signal user_port0_wdata_we : std_ulogic_vector(15 downto 0); + signal user_port0_wdata_data : std_ulogic_vector(127 downto 0); + signal user_port0_rdata_valid : std_ulogic; + signal user_port0_rdata_ready : std_ulogic; + signal user_port0_rdata_data : std_ulogic_vector(127 downto 0); + + signal ad3 : std_ulogic; + + signal dram_user_reset : std_ulogic; + + signal csr_port0_adr : std_ulogic_vector(13 downto 0); + signal csr_port0_we : std_ulogic; + signal csr_port0_dat_w : std_ulogic_vector(7 downto 0); + signal csr_port0_dat_r : std_ulogic_vector(7 downto 0); + signal csr_port_read_comb : std_ulogic_vector(63 downto 0); + signal csr_valid : std_ulogic; + signal csr_write_valid : std_ulogic; + + signal wb_init_in : wishbone_master_out; + signal wb_init_out : wishbone_slave_out; + + type state_t is (CMD, MWRITE, MREAD, CSR); + signal state : state_t; + + constant INIT_RAM_SIZE : integer := 16384; + constant INIT_RAM_ABITS :integer := 14; + constant INIT_RAM_FILE : string := "sdram_init.hex"; + + type ram_t is array(0 to (INIT_RAM_SIZE / 8) - 1) of std_logic_vector(63 downto 0); + + impure function init_load_ram(name : string) return ram_t is + file ram_file : text open read_mode is name; + variable temp_word : std_logic_vector(63 downto 0); + variable temp_ram : ram_t := (others => (others => '0')); + variable ram_line : line; + begin + for i in 0 to (INIT_RAM_SIZE/8)-1 loop + exit when endfile(ram_file); + readline(ram_file, ram_line); + hread(ram_line, temp_word); + temp_ram(i) := temp_word; + end loop; + return temp_ram; + end function; + + signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE); + + attribute ram_style : string; + attribute ram_style of init_ram: signal is "block"; + +begin + + -- BRAM Memory slave + init_ram_0: process(system_clk) + variable adr : integer; + begin + if rising_edge(system_clk) then + wb_init_out.ack <= '0'; + if (wb_init_in.cyc and wb_init_in.stb) = '1' then + adr := to_integer((unsigned(wb_init_in.adr(INIT_RAM_ABITS-1 downto 3)))); + if wb_init_in.we = '0' then + wb_init_out.dat <= init_ram(adr); + else + for i in 0 to 7 loop + if wb_init_in.sel(i) = '1' then + init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= + wb_init_in.dat(((i + 1) * 8) - 1 downto i * 8); + end if; + end loop; + end if; + wb_init_out.ack <= not wb_init_out.ack; + end if; + end if; + end process; + + wb_init_in.adr <= wb_in.adr; + wb_init_in.dat <= wb_in.dat; + wb_init_in.sel <= wb_in.sel; + wb_init_in.we <= wb_in.we; + wb_init_in.stb <= wb_in.stb; + wb_init_in.cyc <= wb_in.cyc and wb_is_init; + + -- Address bit 3 selects the top or bottom half of the data + -- bus (64-bit wishbone vs. 128-bit DRAM interface) + -- + ad3 <= wb_in.adr(3); + + -- DRAM data interface signals + user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init) + when state = CMD else '0'; + user_port0_cmd_we <= wb_in.we when state = CMD else '0'; + user_port0_wdata_valid <= '1' when state = MWRITE else '0'; + user_port0_rdata_ready <= '1' when state = MREAD else '0'; + user_port0_cmd_addr <= wb_in.adr(DRAM_ABITS+3 downto 4); + user_port0_wdata_data <= wb_in.dat & wb_in.dat; + user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else + "00000000" & wb_in.sel; + + -- DRAM CSR interface signals. We only support access to the bottom byte + csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; + csr_write_valid <= wb_in.we and wb_in.sel(0); + csr_port0_adr <= wb_in.adr(15 downto 3) & '0' when wb_is_csr = '1' else (others => '0'); + csr_port0_dat_w <= wb_in.dat(7 downto 0); + csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; + + -- Wishbone out signals + wb_out.ack <= '1' when state = CSR else + wb_init_out.ack when wb_is_init = '1' else + user_port0_wdata_ready when state = MWRITE else + user_port0_rdata_valid when state = MREAD else '0'; + + csr_port_read_comb <= x"00000000000000" & csr_port0_dat_r; + wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else + wb_init_out.dat when wb_is_init = '1' else + user_port0_rdata_data(127 downto 64) when ad3 = '1' else + user_port0_rdata_data(63 downto 0); + -- We don't do pipelining yet. + wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack; + + -- Reset ignored, the reset controller use the pll lock signal, + -- and alternate core reset address set when DRAM is not initialized. + -- + system_reset <= '0'; + core_alt_reset <= not init_done; + + -- State machine + sm: process(system_clk) + begin + + if rising_edge(system_clk) then + if dram_user_reset = '1' then + state <= CMD; + else + case state is + when CMD => + if csr_valid = '1' then + state <= CSR; + elsif (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then + state <= MWRITE when wb_in.we = '1' else MREAD; + end if; + when MWRITE => + if user_port0_wdata_ready = '1' then + state <= CMD; + end if; + when MREAD => + if user_port0_rdata_valid = '1' then + state <= CMD; + end if; + when CSR => + state <= CMD; + end case; + end if; + end if; + end process; + + litedram: litedram_core + port map( + clk => clk_in, + rst => rst, + pll_locked => pll_locked, + ddram_a => ddram_a, + ddram_ba => ddram_ba, + ddram_ras_n => ddram_ras_n, + ddram_cas_n => ddram_cas_n, + ddram_we_n => ddram_we_n, + ddram_cs_n => ddram_cs_n, + ddram_dm => ddram_dm, + ddram_dq => ddram_dq, + ddram_dqs_p => ddram_dqs_p, + ddram_dqs_n => ddram_dqs_n, + ddram_clk_p => ddram_clk_p, + ddram_clk_n => ddram_clk_n, + ddram_cke => ddram_cke, + ddram_odt => ddram_odt, + ddram_reset_n => ddram_reset_n, + init_done => init_done, + init_error => init_error, + user_clk => system_clk, + user_rst => dram_user_reset, + csr_port0_adr => csr_port0_adr, + csr_port0_we => csr_port0_we, + csr_port0_dat_w => csr_port0_dat_w, + csr_port0_dat_r => csr_port0_dat_r, + user_port0_cmd_valid => user_port0_cmd_valid, + user_port0_cmd_ready => user_port0_cmd_ready, + user_port0_cmd_we => user_port0_cmd_we, + user_port0_cmd_addr => user_port0_cmd_addr, + user_port0_wdata_valid => user_port0_wdata_valid, + user_port0_wdata_ready => user_port0_wdata_ready, + user_port0_wdata_we => user_port0_wdata_we, + user_port0_wdata_data => user_port0_wdata_data, + user_port0_rdata_valid => user_port0_rdata_valid, + user_port0_rdata_ready => user_port0_rdata_ready, + user_port0_rdata_data => user_port0_rdata_data + ); + +end architecture behaviour; diff --git a/litedram/gen-src/wrapper-self-init.vhdl b/litedram/gen-src/wrapper-self-init.vhdl new file mode 100644 index 0000000..0664866 --- /dev/null +++ b/litedram/gen-src/wrapper-self-init.vhdl @@ -0,0 +1,214 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; + +library work; +use work.wishbone_types.all; +use work.sim_console.all; + +entity litedram_wrapper is + generic ( + DRAM_ABITS : positive; + DRAM_ALINES : positive + ); + port( + -- LiteDRAM generates the system clock and reset + -- from the input clkin + clk_in : in std_ulogic; + rst : in std_ulogic; + system_clk : out std_ulogic; + system_reset : out std_ulogic; + core_alt_reset : out std_ulogic; + pll_locked : out std_ulogic; + + -- Wishbone ports: + wb_in : in wishbone_master_out; + wb_out : out wishbone_slave_out; + wb_is_csr : in std_ulogic; + wb_is_init : in std_ulogic; + + -- Init core serial debug + serial_tx : out std_ulogic; + serial_rx : in std_ulogic; + + -- Misc + init_done : out std_ulogic; + init_error : out std_ulogic; + + -- DRAM wires + ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic + ); +end entity litedram_wrapper; + +architecture behaviour of litedram_wrapper is + + component litedram_core port ( + clk : in std_ulogic; + rst : in std_ulogic; + serial_tx : out std_ulogic; + serial_rx : in std_ulogic; + pll_locked : out std_ulogic; + ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic; + init_done : out std_ulogic; + init_error : out std_ulogic; + user_clk : out std_ulogic; + user_rst : out std_ulogic; + user_port_native_0_cmd_valid : in std_ulogic; + user_port_native_0_cmd_ready : out std_ulogic; + user_port_native_0_cmd_we : in std_ulogic; + user_port_native_0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0); + user_port_native_0_wdata_valid : in std_ulogic; + user_port_native_0_wdata_ready : out std_ulogic; + user_port_native_0_wdata_we : in std_ulogic_vector(15 downto 0); + user_port_native_0_wdata_data : in std_ulogic_vector(127 downto 0); + user_port_native_0_rdata_valid : out std_ulogic; + user_port_native_0_rdata_ready : in std_ulogic; + user_port_native_0_rdata_data : out std_ulogic_vector(127 downto 0) + ); + end component; + + signal user_port0_cmd_valid : std_ulogic; + signal user_port0_cmd_ready : std_ulogic; + signal user_port0_cmd_we : std_ulogic; + signal user_port0_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0); + signal user_port0_wdata_valid : std_ulogic; + signal user_port0_wdata_ready : std_ulogic; + signal user_port0_wdata_we : std_ulogic_vector(15 downto 0); + signal user_port0_wdata_data : std_ulogic_vector(127 downto 0); + signal user_port0_rdata_valid : std_ulogic; + signal user_port0_rdata_ready : std_ulogic; + signal user_port0_rdata_data : std_ulogic_vector(127 downto 0); + + signal ad3 : std_ulogic; + + signal dram_user_reset : std_ulogic; + + type state_t is (CMD, MWRITE, MREAD); + signal state : state_t; + +begin + + -- Address bit 3 selects the top or bottom half of the data + -- bus (64-bit wishbone vs. 128-bit DRAM interface) + -- + ad3 <= wb_in.adr(3); + + -- DRAM interface signals + user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init) + when state = CMD else '0'; + user_port0_cmd_we <= wb_in.we when state = CMD else '0'; + user_port0_wdata_valid <= '1' when state = MWRITE else '0'; + user_port0_rdata_ready <= '1' when state = MREAD else '0'; + user_port0_cmd_addr <= wb_in.adr(DRAM_ABITS+3 downto 4); + user_port0_wdata_data <= wb_in.dat & wb_in.dat; + user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else + "00000000" & wb_in.sel; + + -- Wishbone out signals. CSR and init memory do nothing, just ack + wb_out.ack <= '1' when (wb_is_csr = '1' or wb_is_init = '1') else + user_port0_wdata_ready when state = MWRITE else + user_port0_rdata_valid when state = MREAD else '0'; + wb_out.dat <= (others => '0') when (wb_is_csr = '1' or wb_is_init = '1') else + user_port0_rdata_data(127 downto 64) when ad3 = '1' else + user_port0_rdata_data(63 downto 0); + wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack; + + -- Reset, lift it when init done, no alt core reset + system_reset <= dram_user_reset or not init_done; + core_alt_reset <= '0'; + + -- State machine + sm: process(system_clk) + begin + + if rising_edge(system_clk) then + if dram_user_reset = '1' then + state <= CMD; + else + case state is + when CMD => + if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then + state <= MWRITE when wb_in.we = '1' else MREAD; + end if; + when MWRITE => + if user_port0_wdata_ready = '1' then + state <= CMD; + end if; + when MREAD => + if user_port0_rdata_valid = '1' then + state <= CMD; + end if; + end case; + end if; + end if; + end process; + + litedram: litedram_core + port map( + clk => clk_in, + rst => rst, + serial_tx => serial_tx, + serial_rx => serial_rx, + pll_locked => pll_locked, + ddram_a => ddram_a, + ddram_ba => ddram_ba, + ddram_ras_n => ddram_ras_n, + ddram_cas_n => ddram_cas_n, + ddram_we_n => ddram_we_n, + ddram_cs_n => ddram_cs_n, + ddram_dm => ddram_dm, + ddram_dq => ddram_dq, + ddram_dqs_p => ddram_dqs_p, + ddram_dqs_n => ddram_dqs_n, + ddram_clk_p => ddram_clk_p, + ddram_clk_n => ddram_clk_n, + ddram_cke => ddram_cke, + ddram_odt => ddram_odt, + ddram_reset_n => ddram_reset_n, + init_done => init_done, + init_error => init_error, + user_clk => system_clk, + user_rst => dram_user_reset, + user_port_native_0_cmd_valid => user_port0_cmd_valid, + user_port_native_0_cmd_ready => user_port0_cmd_ready, + user_port_native_0_cmd_we => user_port0_cmd_we, + user_port_native_0_cmd_addr => user_port0_cmd_addr, + user_port_native_0_wdata_valid => user_port0_wdata_valid, + user_port_native_0_wdata_ready => user_port0_wdata_ready, + user_port_native_0_wdata_we => user_port0_wdata_we, + user_port_native_0_wdata_data => user_port0_wdata_data, + user_port_native_0_rdata_valid => user_port0_rdata_valid, + user_port_native_0_rdata_ready => user_port0_rdata_ready, + user_port_native_0_rdata_data => user_port0_rdata_data + ); + +end architecture behaviour; diff --git a/litedram/generated/arty/init-cpu.txt b/litedram/generated/arty/init-cpu.txt new file mode 100644 index 0000000..b0b6e79 --- /dev/null +++ b/litedram/generated/arty/init-cpu.txt @@ -0,0 +1 @@ +vexriscv \ No newline at end of file diff --git a/litedram/generated/arty/litedram-wrapper.vhdl b/litedram/generated/arty/litedram-wrapper.vhdl new file mode 100644 index 0000000..0664866 --- /dev/null +++ b/litedram/generated/arty/litedram-wrapper.vhdl @@ -0,0 +1,214 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; + +library work; +use work.wishbone_types.all; +use work.sim_console.all; + +entity litedram_wrapper is + generic ( + DRAM_ABITS : positive; + DRAM_ALINES : positive + ); + port( + -- LiteDRAM generates the system clock and reset + -- from the input clkin + clk_in : in std_ulogic; + rst : in std_ulogic; + system_clk : out std_ulogic; + system_reset : out std_ulogic; + core_alt_reset : out std_ulogic; + pll_locked : out std_ulogic; + + -- Wishbone ports: + wb_in : in wishbone_master_out; + wb_out : out wishbone_slave_out; + wb_is_csr : in std_ulogic; + wb_is_init : in std_ulogic; + + -- Init core serial debug + serial_tx : out std_ulogic; + serial_rx : in std_ulogic; + + -- Misc + init_done : out std_ulogic; + init_error : out std_ulogic; + + -- DRAM wires + ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic + ); +end entity litedram_wrapper; + +architecture behaviour of litedram_wrapper is + + component litedram_core port ( + clk : in std_ulogic; + rst : in std_ulogic; + serial_tx : out std_ulogic; + serial_rx : in std_ulogic; + pll_locked : out std_ulogic; + ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic; + init_done : out std_ulogic; + init_error : out std_ulogic; + user_clk : out std_ulogic; + user_rst : out std_ulogic; + user_port_native_0_cmd_valid : in std_ulogic; + user_port_native_0_cmd_ready : out std_ulogic; + user_port_native_0_cmd_we : in std_ulogic; + user_port_native_0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0); + user_port_native_0_wdata_valid : in std_ulogic; + user_port_native_0_wdata_ready : out std_ulogic; + user_port_native_0_wdata_we : in std_ulogic_vector(15 downto 0); + user_port_native_0_wdata_data : in std_ulogic_vector(127 downto 0); + user_port_native_0_rdata_valid : out std_ulogic; + user_port_native_0_rdata_ready : in std_ulogic; + user_port_native_0_rdata_data : out std_ulogic_vector(127 downto 0) + ); + end component; + + signal user_port0_cmd_valid : std_ulogic; + signal user_port0_cmd_ready : std_ulogic; + signal user_port0_cmd_we : std_ulogic; + signal user_port0_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0); + signal user_port0_wdata_valid : std_ulogic; + signal user_port0_wdata_ready : std_ulogic; + signal user_port0_wdata_we : std_ulogic_vector(15 downto 0); + signal user_port0_wdata_data : std_ulogic_vector(127 downto 0); + signal user_port0_rdata_valid : std_ulogic; + signal user_port0_rdata_ready : std_ulogic; + signal user_port0_rdata_data : std_ulogic_vector(127 downto 0); + + signal ad3 : std_ulogic; + + signal dram_user_reset : std_ulogic; + + type state_t is (CMD, MWRITE, MREAD); + signal state : state_t; + +begin + + -- Address bit 3 selects the top or bottom half of the data + -- bus (64-bit wishbone vs. 128-bit DRAM interface) + -- + ad3 <= wb_in.adr(3); + + -- DRAM interface signals + user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init) + when state = CMD else '0'; + user_port0_cmd_we <= wb_in.we when state = CMD else '0'; + user_port0_wdata_valid <= '1' when state = MWRITE else '0'; + user_port0_rdata_ready <= '1' when state = MREAD else '0'; + user_port0_cmd_addr <= wb_in.adr(DRAM_ABITS+3 downto 4); + user_port0_wdata_data <= wb_in.dat & wb_in.dat; + user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else + "00000000" & wb_in.sel; + + -- Wishbone out signals. CSR and init memory do nothing, just ack + wb_out.ack <= '1' when (wb_is_csr = '1' or wb_is_init = '1') else + user_port0_wdata_ready when state = MWRITE else + user_port0_rdata_valid when state = MREAD else '0'; + wb_out.dat <= (others => '0') when (wb_is_csr = '1' or wb_is_init = '1') else + user_port0_rdata_data(127 downto 64) when ad3 = '1' else + user_port0_rdata_data(63 downto 0); + wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack; + + -- Reset, lift it when init done, no alt core reset + system_reset <= dram_user_reset or not init_done; + core_alt_reset <= '0'; + + -- State machine + sm: process(system_clk) + begin + + if rising_edge(system_clk) then + if dram_user_reset = '1' then + state <= CMD; + else + case state is + when CMD => + if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then + state <= MWRITE when wb_in.we = '1' else MREAD; + end if; + when MWRITE => + if user_port0_wdata_ready = '1' then + state <= CMD; + end if; + when MREAD => + if user_port0_rdata_valid = '1' then + state <= CMD; + end if; + end case; + end if; + end if; + end process; + + litedram: litedram_core + port map( + clk => clk_in, + rst => rst, + serial_tx => serial_tx, + serial_rx => serial_rx, + pll_locked => pll_locked, + ddram_a => ddram_a, + ddram_ba => ddram_ba, + ddram_ras_n => ddram_ras_n, + ddram_cas_n => ddram_cas_n, + ddram_we_n => ddram_we_n, + ddram_cs_n => ddram_cs_n, + ddram_dm => ddram_dm, + ddram_dq => ddram_dq, + ddram_dqs_p => ddram_dqs_p, + ddram_dqs_n => ddram_dqs_n, + ddram_clk_p => ddram_clk_p, + ddram_clk_n => ddram_clk_n, + ddram_cke => ddram_cke, + ddram_odt => ddram_odt, + ddram_reset_n => ddram_reset_n, + init_done => init_done, + init_error => init_error, + user_clk => system_clk, + user_rst => dram_user_reset, + user_port_native_0_cmd_valid => user_port0_cmd_valid, + user_port_native_0_cmd_ready => user_port0_cmd_ready, + user_port_native_0_cmd_we => user_port0_cmd_we, + user_port_native_0_cmd_addr => user_port0_cmd_addr, + user_port_native_0_wdata_valid => user_port0_wdata_valid, + user_port_native_0_wdata_ready => user_port0_wdata_ready, + user_port_native_0_wdata_we => user_port0_wdata_we, + user_port_native_0_wdata_data => user_port0_wdata_data, + user_port_native_0_rdata_valid => user_port0_rdata_valid, + user_port_native_0_rdata_ready => user_port0_rdata_ready, + user_port_native_0_rdata_data => user_port0_rdata_data + ); + +end architecture behaviour; diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init new file mode 100644 index 0000000..60f87de --- /dev/null +++ b/litedram/generated/arty/litedram_core.init @@ -0,0 +1,5817 @@ +b00006f +13 +13 +13 +13 +13 +13 +13 +fe112e23 +fe512c23 +fe612a23 +fe712823 +fea12623 +feb12423 +fec12223 +fed12023 +fce12e23 +fcf12c23 +fd012a23 +fd112823 +fdc12623 +fdd12423 +fde12223 +fdf12023 +fc010113 +94000ef +3c12083 +3812283 +3412303 +3012383 +2c12503 +2812583 +2412603 +2012683 +1c12703 +1812783 +1412803 +1012883 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Auto-generated by Migen (dc9cfe6) & LiteX (79ee135f) on 2020-05-08 01:29:17 +//-------------------------------------------------------------------------------- +module litedram_core( + output reg serial_tx, + input wire serial_rx, + input wire clk, + input wire rst, + output wire pll_locked, + output wire [13:0] ddram_a, + output wire [2:0] ddram_ba, + output wire ddram_ras_n, + output wire ddram_cas_n, + output wire ddram_we_n, + output wire ddram_cs_n, + output wire [1:0] ddram_dm, + inout wire [15:0] ddram_dq, + inout wire [1:0] ddram_dqs_p, + inout wire [1:0] ddram_dqs_n, + output wire ddram_clk_p, + output wire ddram_clk_n, + output wire ddram_cke, + output wire ddram_odt, + output wire ddram_reset_n, + output wire init_done, + output wire init_error, + output wire user_clk, + output wire user_rst, + input wire user_port_native_0_cmd_valid, + output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_we, + input wire [23:0] user_port_native_0_cmd_addr, + input wire user_port_native_0_wdata_valid, + output wire user_port_native_0_wdata_ready, + input wire [15:0] user_port_native_0_wdata_we, + input wire [127:0] user_port_native_0_wdata_data, + output wire user_port_native_0_rdata_valid, + input wire user_port_native_0_rdata_ready, + output wire [127:0] user_port_native_0_rdata_data +); + +reg soc_litedramcore_soccontroller_reset_storage = 1'd0; +reg soc_litedramcore_soccontroller_reset_re = 1'd0; +reg [31:0] soc_litedramcore_soccontroller_scratch_storage = 32'd305419896; +reg soc_litedramcore_soccontroller_scratch_re = 1'd0; +wire [31:0] soc_litedramcore_soccontroller_bus_errors_status; +wire soc_litedramcore_soccontroller_bus_errors_we; +wire soc_litedramcore_soccontroller_reset; +wire soc_litedramcore_soccontroller_bus_error; +reg [31:0] soc_litedramcore_soccontroller_bus_errors = 32'd0; +wire soc_litedramcore_cpu_reset; +reg [31:0] soc_litedramcore_cpu_interrupt = 32'd0; +wire [29:0] soc_litedramcore_cpu_ibus_adr; +wire [31:0] soc_litedramcore_cpu_ibus_dat_w; +wire [31:0] soc_litedramcore_cpu_ibus_dat_r; +wire [3:0] soc_litedramcore_cpu_ibus_sel; +wire soc_litedramcore_cpu_ibus_cyc; +wire soc_litedramcore_cpu_ibus_stb; +wire soc_litedramcore_cpu_ibus_ack; +wire soc_litedramcore_cpu_ibus_we; +wire [2:0] soc_litedramcore_cpu_ibus_cti; +wire [1:0] soc_litedramcore_cpu_ibus_bte; +wire soc_litedramcore_cpu_ibus_err; +wire [29:0] soc_litedramcore_cpu_dbus_adr; +wire [31:0] soc_litedramcore_cpu_dbus_dat_w; +wire [31:0] soc_litedramcore_cpu_dbus_dat_r; +wire [3:0] soc_litedramcore_cpu_dbus_sel; +wire soc_litedramcore_cpu_dbus_cyc; +wire soc_litedramcore_cpu_dbus_stb; +wire soc_litedramcore_cpu_dbus_ack; +wire soc_litedramcore_cpu_dbus_we; +wire [2:0] soc_litedramcore_cpu_dbus_cti; +wire [1:0] soc_litedramcore_cpu_dbus_bte; +wire soc_litedramcore_cpu_dbus_err; +reg [31:0] soc_litedramcore_vexriscv = 32'd0; +wire [29:0] soc_litedramcore_litedramcore_ram_bus_adr; +wire [31:0] soc_litedramcore_litedramcore_ram_bus_dat_w; +wire [31:0] soc_litedramcore_litedramcore_ram_bus_dat_r; +wire [3:0] soc_litedramcore_litedramcore_ram_bus_sel; +wire soc_litedramcore_litedramcore_ram_bus_cyc; +wire soc_litedramcore_litedramcore_ram_bus_stb; +reg soc_litedramcore_litedramcore_ram_bus_ack = 1'd0; +wire soc_litedramcore_litedramcore_ram_bus_we; +wire [2:0] soc_litedramcore_litedramcore_ram_bus_cti; +wire [1:0] soc_litedramcore_litedramcore_ram_bus_bte; +reg soc_litedramcore_litedramcore_ram_bus_err = 1'd0; +wire [12:0] soc_litedramcore_litedramcore_adr; +wire [31:0] soc_litedramcore_litedramcore_dat_r; +wire [29:0] soc_litedramcore_ram_bus_ram_bus_adr; +wire [31:0] soc_litedramcore_ram_bus_ram_bus_dat_w; +wire [31:0] soc_litedramcore_ram_bus_ram_bus_dat_r; +wire [3:0] soc_litedramcore_ram_bus_ram_bus_sel; +wire soc_litedramcore_ram_bus_ram_bus_cyc; +wire soc_litedramcore_ram_bus_ram_bus_stb; +reg soc_litedramcore_ram_bus_ram_bus_ack = 1'd0; +wire soc_litedramcore_ram_bus_ram_bus_we; +wire [2:0] soc_litedramcore_ram_bus_ram_bus_cti; +wire [1:0] soc_litedramcore_ram_bus_ram_bus_bte; +reg soc_litedramcore_ram_bus_ram_bus_err = 1'd0; +wire [9:0] soc_litedramcore_ram_adr; +wire [31:0] soc_litedramcore_ram_dat_r; +reg [3:0] soc_litedramcore_ram_we = 4'd0; +wire [31:0] soc_litedramcore_ram_dat_w; +reg [31:0] soc_litedramcore_storage = 32'd4947802; +reg soc_litedramcore_re = 1'd0; +wire soc_litedramcore_sink_valid; +reg soc_litedramcore_sink_ready = 1'd0; +wire soc_litedramcore_sink_first; +wire soc_litedramcore_sink_last; +wire [7:0] soc_litedramcore_sink_payload_data; +reg soc_litedramcore_uart_clk_txen = 1'd0; +reg [31:0] soc_litedramcore_phase_accumulator_tx = 32'd0; +reg [7:0] soc_litedramcore_tx_reg = 8'd0; +reg [3:0] soc_litedramcore_tx_bitcount = 4'd0; +reg soc_litedramcore_tx_busy = 1'd0; +reg soc_litedramcore_source_valid = 1'd0; +wire soc_litedramcore_source_ready; +reg soc_litedramcore_source_first = 1'd0; +reg soc_litedramcore_source_last = 1'd0; +reg [7:0] soc_litedramcore_source_payload_data = 8'd0; +reg soc_litedramcore_uart_clk_rxen = 1'd0; +reg [31:0] soc_litedramcore_phase_accumulator_rx = 32'd0; +wire soc_litedramcore_rx; +reg soc_litedramcore_rx_r = 1'd0; +reg [7:0] soc_litedramcore_rx_reg = 8'd0; +reg [3:0] soc_litedramcore_rx_bitcount = 4'd0; +reg soc_litedramcore_rx_busy = 1'd0; +wire soc_litedramcore_uart_rxtx_re; +wire [7:0] soc_litedramcore_uart_rxtx_r; +wire soc_litedramcore_uart_rxtx_we; +wire [7:0] soc_litedramcore_uart_rxtx_w; +wire soc_litedramcore_uart_txfull_status; +wire soc_litedramcore_uart_txfull_we; +wire soc_litedramcore_uart_rxempty_status; +wire soc_litedramcore_uart_rxempty_we; +wire soc_litedramcore_uart_irq; +wire soc_litedramcore_uart_tx_status; +reg soc_litedramcore_uart_tx_pending = 1'd0; +wire soc_litedramcore_uart_tx_trigger; +reg soc_litedramcore_uart_tx_clear = 1'd0; +reg soc_litedramcore_uart_tx_old_trigger = 1'd0; +wire soc_litedramcore_uart_rx_status; +reg soc_litedramcore_uart_rx_pending = 1'd0; +wire soc_litedramcore_uart_rx_trigger; +reg soc_litedramcore_uart_rx_clear = 1'd0; +reg soc_litedramcore_uart_rx_old_trigger = 1'd0; +wire soc_litedramcore_uart_eventmanager_status_re; +wire [1:0] soc_litedramcore_uart_eventmanager_status_r; +wire soc_litedramcore_uart_eventmanager_status_we; +reg [1:0] soc_litedramcore_uart_eventmanager_status_w = 2'd0; +wire soc_litedramcore_uart_eventmanager_pending_re; +wire [1:0] soc_litedramcore_uart_eventmanager_pending_r; +wire soc_litedramcore_uart_eventmanager_pending_we; +reg [1:0] soc_litedramcore_uart_eventmanager_pending_w = 2'd0; +reg [1:0] soc_litedramcore_uart_eventmanager_storage = 2'd0; +reg soc_litedramcore_uart_eventmanager_re = 1'd0; +wire soc_litedramcore_uart_uart_sink_valid; +wire soc_litedramcore_uart_uart_sink_ready; +wire soc_litedramcore_uart_uart_sink_first; +wire soc_litedramcore_uart_uart_sink_last; +wire [7:0] soc_litedramcore_uart_uart_sink_payload_data; +wire soc_litedramcore_uart_uart_source_valid; +wire soc_litedramcore_uart_uart_source_ready; +wire soc_litedramcore_uart_uart_source_first; +wire soc_litedramcore_uart_uart_source_last; +wire [7:0] soc_litedramcore_uart_uart_source_payload_data; +wire soc_litedramcore_uart_tx_fifo_sink_valid; +wire soc_litedramcore_uart_tx_fifo_sink_ready; +reg soc_litedramcore_uart_tx_fifo_sink_first = 1'd0; +reg soc_litedramcore_uart_tx_fifo_sink_last = 1'd0; +wire [7:0] soc_litedramcore_uart_tx_fifo_sink_payload_data; +wire soc_litedramcore_uart_tx_fifo_source_valid; +wire soc_litedramcore_uart_tx_fifo_source_ready; +wire soc_litedramcore_uart_tx_fifo_source_first; +wire soc_litedramcore_uart_tx_fifo_source_last; +wire [7:0] soc_litedramcore_uart_tx_fifo_source_payload_data; +wire soc_litedramcore_uart_tx_fifo_re; +reg soc_litedramcore_uart_tx_fifo_readable = 1'd0; +wire soc_litedramcore_uart_tx_fifo_syncfifo_we; +wire soc_litedramcore_uart_tx_fifo_syncfifo_writable; +wire soc_litedramcore_uart_tx_fifo_syncfifo_re; +wire soc_litedramcore_uart_tx_fifo_syncfifo_readable; +wire [9:0] soc_litedramcore_uart_tx_fifo_syncfifo_din; +wire [9:0] soc_litedramcore_uart_tx_fifo_syncfifo_dout; +reg [4:0] soc_litedramcore_uart_tx_fifo_level0 = 5'd0; +reg soc_litedramcore_uart_tx_fifo_replace = 1'd0; +reg [3:0] soc_litedramcore_uart_tx_fifo_produce = 4'd0; +reg [3:0] soc_litedramcore_uart_tx_fifo_consume = 4'd0; +reg [3:0] soc_litedramcore_uart_tx_fifo_wrport_adr = 4'd0; +wire [9:0] soc_litedramcore_uart_tx_fifo_wrport_dat_r; +wire soc_litedramcore_uart_tx_fifo_wrport_we; +wire [9:0] soc_litedramcore_uart_tx_fifo_wrport_dat_w; +wire soc_litedramcore_uart_tx_fifo_do_read; +wire [3:0] soc_litedramcore_uart_tx_fifo_rdport_adr; +wire [9:0] soc_litedramcore_uart_tx_fifo_rdport_dat_r; +wire soc_litedramcore_uart_tx_fifo_rdport_re; +wire [4:0] soc_litedramcore_uart_tx_fifo_level1; +wire [7:0] soc_litedramcore_uart_tx_fifo_fifo_in_payload_data; +wire soc_litedramcore_uart_tx_fifo_fifo_in_first; +wire soc_litedramcore_uart_tx_fifo_fifo_in_last; +wire [7:0] soc_litedramcore_uart_tx_fifo_fifo_out_payload_data; +wire soc_litedramcore_uart_tx_fifo_fifo_out_first; +wire soc_litedramcore_uart_tx_fifo_fifo_out_last; +wire soc_litedramcore_uart_rx_fifo_sink_valid; +wire soc_litedramcore_uart_rx_fifo_sink_ready; +wire soc_litedramcore_uart_rx_fifo_sink_first; +wire soc_litedramcore_uart_rx_fifo_sink_last; +wire [7:0] soc_litedramcore_uart_rx_fifo_sink_payload_data; +wire soc_litedramcore_uart_rx_fifo_source_valid; +wire soc_litedramcore_uart_rx_fifo_source_ready; +wire soc_litedramcore_uart_rx_fifo_source_first; +wire soc_litedramcore_uart_rx_fifo_source_last; +wire [7:0] soc_litedramcore_uart_rx_fifo_source_payload_data; +wire soc_litedramcore_uart_rx_fifo_re; +reg soc_litedramcore_uart_rx_fifo_readable = 1'd0; +wire soc_litedramcore_uart_rx_fifo_syncfifo_we; +wire soc_litedramcore_uart_rx_fifo_syncfifo_writable; +wire soc_litedramcore_uart_rx_fifo_syncfifo_re; +wire soc_litedramcore_uart_rx_fifo_syncfifo_readable; +wire [9:0] soc_litedramcore_uart_rx_fifo_syncfifo_din; +wire [9:0] soc_litedramcore_uart_rx_fifo_syncfifo_dout; +reg [4:0] soc_litedramcore_uart_rx_fifo_level0 = 5'd0; +reg soc_litedramcore_uart_rx_fifo_replace = 1'd0; +reg [3:0] soc_litedramcore_uart_rx_fifo_produce = 4'd0; +reg [3:0] soc_litedramcore_uart_rx_fifo_consume = 4'd0; +reg [3:0] soc_litedramcore_uart_rx_fifo_wrport_adr = 4'd0; +wire [9:0] soc_litedramcore_uart_rx_fifo_wrport_dat_r; +wire soc_litedramcore_uart_rx_fifo_wrport_we; +wire [9:0] soc_litedramcore_uart_rx_fifo_wrport_dat_w; +wire soc_litedramcore_uart_rx_fifo_do_read; +wire [3:0] soc_litedramcore_uart_rx_fifo_rdport_adr; +wire [9:0] soc_litedramcore_uart_rx_fifo_rdport_dat_r; +wire soc_litedramcore_uart_rx_fifo_rdport_re; +wire [4:0] soc_litedramcore_uart_rx_fifo_level1; +wire [7:0] soc_litedramcore_uart_rx_fifo_fifo_in_payload_data; +wire soc_litedramcore_uart_rx_fifo_fifo_in_first; +wire soc_litedramcore_uart_rx_fifo_fifo_in_last; +wire [7:0] soc_litedramcore_uart_rx_fifo_fifo_out_payload_data; +wire soc_litedramcore_uart_rx_fifo_fifo_out_first; +wire soc_litedramcore_uart_rx_fifo_fifo_out_last; +reg soc_litedramcore_uart_reset = 1'd0; +reg [31:0] soc_litedramcore_timer_load_storage = 32'd0; +reg soc_litedramcore_timer_load_re = 1'd0; +reg [31:0] soc_litedramcore_timer_reload_storage = 32'd0; +reg soc_litedramcore_timer_reload_re = 1'd0; +reg soc_litedramcore_timer_en_storage = 1'd0; +reg soc_litedramcore_timer_en_re = 1'd0; +reg soc_litedramcore_timer_update_value_storage = 1'd0; +reg soc_litedramcore_timer_update_value_re = 1'd0; +reg [31:0] soc_litedramcore_timer_value_status = 32'd0; +wire soc_litedramcore_timer_value_we; +wire soc_litedramcore_timer_irq; +wire soc_litedramcore_timer_zero_status; +reg soc_litedramcore_timer_zero_pending = 1'd0; +wire soc_litedramcore_timer_zero_trigger; +reg soc_litedramcore_timer_zero_clear = 1'd0; +reg soc_litedramcore_timer_zero_old_trigger = 1'd0; +wire soc_litedramcore_timer_eventmanager_status_re; +wire soc_litedramcore_timer_eventmanager_status_r; +wire soc_litedramcore_timer_eventmanager_status_we; +wire soc_litedramcore_timer_eventmanager_status_w; +wire soc_litedramcore_timer_eventmanager_pending_re; +wire soc_litedramcore_timer_eventmanager_pending_r; +wire soc_litedramcore_timer_eventmanager_pending_we; +wire soc_litedramcore_timer_eventmanager_pending_w; +reg soc_litedramcore_timer_eventmanager_storage = 1'd0; +reg soc_litedramcore_timer_eventmanager_re = 1'd0; +reg [31:0] soc_litedramcore_timer_value = 32'd0; +reg [13:0] soc_litedramcore_interface_adr = 14'd0; +reg soc_litedramcore_interface_we = 1'd0; +wire [7:0] soc_litedramcore_interface_dat_w; +wire [7:0] soc_litedramcore_interface_dat_r; +wire [29:0] soc_litedramcore_bus_wishbone_adr; +wire [31:0] soc_litedramcore_bus_wishbone_dat_w; +wire [31:0] soc_litedramcore_bus_wishbone_dat_r; +wire [3:0] soc_litedramcore_bus_wishbone_sel; +wire soc_litedramcore_bus_wishbone_cyc; +wire soc_litedramcore_bus_wishbone_stb; +reg soc_litedramcore_bus_wishbone_ack = 1'd0; +wire soc_litedramcore_bus_wishbone_we; +wire [2:0] soc_litedramcore_bus_wishbone_cti; +wire [1:0] soc_litedramcore_bus_wishbone_bte; +reg soc_litedramcore_bus_wishbone_err = 1'd0; +wire sys_clk; +wire sys_rst; +wire sys4x_clk; +wire sys4x_dqs_clk; +wire iodelay_clk; +wire iodelay_rst; +wire soc_sys_pll_reset; +wire soc_sys_pll_locked; +wire soc_s7pll0_clkin; +wire soc_s7pll0_clkout0; +wire soc_s7pll0_clkout_buf0; +wire soc_s7pll0_clkout1; +wire soc_s7pll0_clkout_buf1; +wire soc_s7pll0_clkout2; +wire soc_s7pll0_clkout_buf2; +wire soc_iodelay_pll_reset; +wire soc_iodelay_pll_locked; +wire soc_s7pll1_clkin; +wire soc_s7pll1_clkout; +wire soc_s7pll1_clkout_buf; +reg [3:0] soc_reset_counter = 4'd15; +reg soc_ic_reset = 1'd1; +reg [4:0] soc_a7ddrphy_half_sys8x_taps_storage = 5'd8; +reg soc_a7ddrphy_half_sys8x_taps_re = 1'd0; +reg soc_a7ddrphy_wlevel_en_storage = 1'd0; +reg soc_a7ddrphy_wlevel_en_re = 1'd0; +wire soc_a7ddrphy_wlevel_strobe_re; +wire soc_a7ddrphy_wlevel_strobe_r; +wire soc_a7ddrphy_wlevel_strobe_we; +reg soc_a7ddrphy_wlevel_strobe_w = 1'd0; +wire soc_a7ddrphy_cdly_rst_re; +wire soc_a7ddrphy_cdly_rst_r; +wire soc_a7ddrphy_cdly_rst_we; +reg soc_a7ddrphy_cdly_rst_w = 1'd0; +wire soc_a7ddrphy_cdly_inc_re; +wire soc_a7ddrphy_cdly_inc_r; +wire soc_a7ddrphy_cdly_inc_we; +reg soc_a7ddrphy_cdly_inc_w = 1'd0; +reg [1:0] soc_a7ddrphy_dly_sel_storage = 2'd0; +reg soc_a7ddrphy_dly_sel_re = 1'd0; +wire soc_a7ddrphy_rdly_dq_rst_re; +wire soc_a7ddrphy_rdly_dq_rst_r; +wire soc_a7ddrphy_rdly_dq_rst_we; +reg soc_a7ddrphy_rdly_dq_rst_w = 1'd0; +wire soc_a7ddrphy_rdly_dq_inc_re; +wire soc_a7ddrphy_rdly_dq_inc_r; +wire soc_a7ddrphy_rdly_dq_inc_we; +reg soc_a7ddrphy_rdly_dq_inc_w = 1'd0; +wire soc_a7ddrphy_rdly_dq_bitslip_rst_re; +wire soc_a7ddrphy_rdly_dq_bitslip_rst_r; +wire soc_a7ddrphy_rdly_dq_bitslip_rst_we; +reg soc_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +wire soc_a7ddrphy_rdly_dq_bitslip_re; +wire soc_a7ddrphy_rdly_dq_bitslip_r; +wire soc_a7ddrphy_rdly_dq_bitslip_we; +reg soc_a7ddrphy_rdly_dq_bitslip_w = 1'd0; +wire [13:0] soc_a7ddrphy_dfi_p0_address; +wire [2:0] soc_a7ddrphy_dfi_p0_bank; +wire soc_a7ddrphy_dfi_p0_cas_n; +wire soc_a7ddrphy_dfi_p0_cs_n; +wire soc_a7ddrphy_dfi_p0_ras_n; +wire soc_a7ddrphy_dfi_p0_we_n; +wire soc_a7ddrphy_dfi_p0_cke; +wire soc_a7ddrphy_dfi_p0_odt; +wire soc_a7ddrphy_dfi_p0_reset_n; +wire soc_a7ddrphy_dfi_p0_act_n; +wire [31:0] soc_a7ddrphy_dfi_p0_wrdata; +wire soc_a7ddrphy_dfi_p0_wrdata_en; +wire [3:0] soc_a7ddrphy_dfi_p0_wrdata_mask; +wire soc_a7ddrphy_dfi_p0_rddata_en; +reg [31:0] soc_a7ddrphy_dfi_p0_rddata = 32'd0; +reg soc_a7ddrphy_dfi_p0_rddata_valid = 1'd0; +wire [13:0] soc_a7ddrphy_dfi_p1_address; +wire [2:0] soc_a7ddrphy_dfi_p1_bank; +wire soc_a7ddrphy_dfi_p1_cas_n; +wire soc_a7ddrphy_dfi_p1_cs_n; +wire soc_a7ddrphy_dfi_p1_ras_n; +wire soc_a7ddrphy_dfi_p1_we_n; +wire soc_a7ddrphy_dfi_p1_cke; +wire soc_a7ddrphy_dfi_p1_odt; +wire soc_a7ddrphy_dfi_p1_reset_n; +wire soc_a7ddrphy_dfi_p1_act_n; +wire [31:0] soc_a7ddrphy_dfi_p1_wrdata; +wire soc_a7ddrphy_dfi_p1_wrdata_en; +wire [3:0] soc_a7ddrphy_dfi_p1_wrdata_mask; +wire soc_a7ddrphy_dfi_p1_rddata_en; +reg [31:0] soc_a7ddrphy_dfi_p1_rddata = 32'd0; +reg soc_a7ddrphy_dfi_p1_rddata_valid = 1'd0; +wire [13:0] soc_a7ddrphy_dfi_p2_address; +wire [2:0] soc_a7ddrphy_dfi_p2_bank; +wire soc_a7ddrphy_dfi_p2_cas_n; +wire soc_a7ddrphy_dfi_p2_cs_n; +wire soc_a7ddrphy_dfi_p2_ras_n; +wire soc_a7ddrphy_dfi_p2_we_n; +wire soc_a7ddrphy_dfi_p2_cke; +wire soc_a7ddrphy_dfi_p2_odt; +wire soc_a7ddrphy_dfi_p2_reset_n; +wire soc_a7ddrphy_dfi_p2_act_n; +wire [31:0] soc_a7ddrphy_dfi_p2_wrdata; +wire soc_a7ddrphy_dfi_p2_wrdata_en; +wire [3:0] soc_a7ddrphy_dfi_p2_wrdata_mask; +wire soc_a7ddrphy_dfi_p2_rddata_en; +reg [31:0] soc_a7ddrphy_dfi_p2_rddata = 32'd0; +reg soc_a7ddrphy_dfi_p2_rddata_valid = 1'd0; +wire [13:0] soc_a7ddrphy_dfi_p3_address; +wire [2:0] soc_a7ddrphy_dfi_p3_bank; +wire soc_a7ddrphy_dfi_p3_cas_n; +wire soc_a7ddrphy_dfi_p3_cs_n; +wire soc_a7ddrphy_dfi_p3_ras_n; +wire soc_a7ddrphy_dfi_p3_we_n; +wire soc_a7ddrphy_dfi_p3_cke; +wire soc_a7ddrphy_dfi_p3_odt; +wire soc_a7ddrphy_dfi_p3_reset_n; +wire soc_a7ddrphy_dfi_p3_act_n; +wire [31:0] soc_a7ddrphy_dfi_p3_wrdata; +wire soc_a7ddrphy_dfi_p3_wrdata_en; +wire [3:0] soc_a7ddrphy_dfi_p3_wrdata_mask; +wire soc_a7ddrphy_dfi_p3_rddata_en; +reg [31:0] soc_a7ddrphy_dfi_p3_rddata = 32'd0; +reg soc_a7ddrphy_dfi_p3_rddata_valid = 1'd0; +wire soc_a7ddrphy_sd_clk_se_nodelay; +reg soc_a7ddrphy_dqs_oe = 1'd0; +reg soc_a7ddrphy_dqs_oe_delayed = 1'd0; +wire soc_a7ddrphy_dqspattern0; +wire soc_a7ddrphy_dqspattern1; +reg [7:0] soc_a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] soc_a7ddrphy_dqspattern_o1 = 8'd0; +wire [1:0] soc_a7ddrphy_dqs_i; +wire [1:0] soc_a7ddrphy_dqs_i_delayed; +wire soc_a7ddrphy_dqs_o_no_delay0; +wire soc_a7ddrphy_dqs_t0; +wire soc_a7ddrphy0; +wire soc_a7ddrphy_dqs_o_no_delay1; +wire soc_a7ddrphy_dqs_t1; +wire soc_a7ddrphy1; +wire soc_a7ddrphy_dq_oe; +reg soc_a7ddrphy_dq_oe_delayed = 1'd0; +wire soc_a7ddrphy_dq_o_nodelay0; +wire soc_a7ddrphy_dq_i_nodelay0; +wire soc_a7ddrphy_dq_i_delayed0; +wire soc_a7ddrphy_dq_t0; +wire [7:0] soc_a7ddrphy_dq_i_data0; +wire [7:0] soc_a7ddrphy_bitslip0_i; +reg [7:0] soc_a7ddrphy_bitslip0_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip0_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip0_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay1; +wire soc_a7ddrphy_dq_i_nodelay1; +wire soc_a7ddrphy_dq_i_delayed1; +wire soc_a7ddrphy_dq_t1; +wire [7:0] soc_a7ddrphy_dq_i_data1; +wire [7:0] soc_a7ddrphy_bitslip1_i; +reg [7:0] soc_a7ddrphy_bitslip1_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip1_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip1_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay2; +wire soc_a7ddrphy_dq_i_nodelay2; +wire soc_a7ddrphy_dq_i_delayed2; +wire soc_a7ddrphy_dq_t2; +wire [7:0] soc_a7ddrphy_dq_i_data2; +wire [7:0] soc_a7ddrphy_bitslip2_i; +reg [7:0] soc_a7ddrphy_bitslip2_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip2_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip2_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay3; +wire soc_a7ddrphy_dq_i_nodelay3; +wire soc_a7ddrphy_dq_i_delayed3; +wire soc_a7ddrphy_dq_t3; +wire [7:0] soc_a7ddrphy_dq_i_data3; +wire [7:0] soc_a7ddrphy_bitslip3_i; +reg [7:0] soc_a7ddrphy_bitslip3_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip3_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip3_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay4; +wire soc_a7ddrphy_dq_i_nodelay4; +wire soc_a7ddrphy_dq_i_delayed4; +wire soc_a7ddrphy_dq_t4; +wire [7:0] soc_a7ddrphy_dq_i_data4; +wire [7:0] soc_a7ddrphy_bitslip4_i; +reg [7:0] soc_a7ddrphy_bitslip4_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip4_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip4_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay5; +wire soc_a7ddrphy_dq_i_nodelay5; +wire soc_a7ddrphy_dq_i_delayed5; +wire soc_a7ddrphy_dq_t5; +wire [7:0] soc_a7ddrphy_dq_i_data5; +wire [7:0] soc_a7ddrphy_bitslip5_i; +reg [7:0] soc_a7ddrphy_bitslip5_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip5_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip5_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay6; +wire soc_a7ddrphy_dq_i_nodelay6; +wire soc_a7ddrphy_dq_i_delayed6; +wire soc_a7ddrphy_dq_t6; +wire [7:0] soc_a7ddrphy_dq_i_data6; +wire [7:0] soc_a7ddrphy_bitslip6_i; +reg [7:0] soc_a7ddrphy_bitslip6_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip6_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip6_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay7; +wire soc_a7ddrphy_dq_i_nodelay7; +wire soc_a7ddrphy_dq_i_delayed7; +wire soc_a7ddrphy_dq_t7; +wire [7:0] soc_a7ddrphy_dq_i_data7; +wire [7:0] soc_a7ddrphy_bitslip7_i; +reg [7:0] soc_a7ddrphy_bitslip7_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip7_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip7_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay8; +wire soc_a7ddrphy_dq_i_nodelay8; +wire soc_a7ddrphy_dq_i_delayed8; +wire soc_a7ddrphy_dq_t8; +wire [7:0] soc_a7ddrphy_dq_i_data8; +wire [7:0] soc_a7ddrphy_bitslip8_i; +reg [7:0] soc_a7ddrphy_bitslip8_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip8_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip8_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay9; +wire soc_a7ddrphy_dq_i_nodelay9; +wire soc_a7ddrphy_dq_i_delayed9; +wire soc_a7ddrphy_dq_t9; +wire [7:0] soc_a7ddrphy_dq_i_data9; +wire [7:0] soc_a7ddrphy_bitslip9_i; +reg [7:0] soc_a7ddrphy_bitslip9_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip9_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip9_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay10; +wire soc_a7ddrphy_dq_i_nodelay10; +wire soc_a7ddrphy_dq_i_delayed10; +wire soc_a7ddrphy_dq_t10; +wire [7:0] soc_a7ddrphy_dq_i_data10; +wire [7:0] soc_a7ddrphy_bitslip10_i; +reg [7:0] soc_a7ddrphy_bitslip10_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip10_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip10_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay11; +wire soc_a7ddrphy_dq_i_nodelay11; +wire soc_a7ddrphy_dq_i_delayed11; +wire soc_a7ddrphy_dq_t11; +wire [7:0] soc_a7ddrphy_dq_i_data11; +wire [7:0] soc_a7ddrphy_bitslip11_i; +reg [7:0] soc_a7ddrphy_bitslip11_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip11_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip11_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay12; +wire soc_a7ddrphy_dq_i_nodelay12; +wire soc_a7ddrphy_dq_i_delayed12; +wire soc_a7ddrphy_dq_t12; +wire [7:0] soc_a7ddrphy_dq_i_data12; +wire [7:0] soc_a7ddrphy_bitslip12_i; +reg [7:0] soc_a7ddrphy_bitslip12_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip12_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip12_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay13; +wire soc_a7ddrphy_dq_i_nodelay13; +wire soc_a7ddrphy_dq_i_delayed13; +wire soc_a7ddrphy_dq_t13; +wire [7:0] soc_a7ddrphy_dq_i_data13; +wire [7:0] soc_a7ddrphy_bitslip13_i; +reg [7:0] soc_a7ddrphy_bitslip13_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip13_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip13_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay14; +wire soc_a7ddrphy_dq_i_nodelay14; +wire soc_a7ddrphy_dq_i_delayed14; +wire soc_a7ddrphy_dq_t14; +wire [7:0] soc_a7ddrphy_dq_i_data14; +wire [7:0] soc_a7ddrphy_bitslip14_i; +reg [7:0] soc_a7ddrphy_bitslip14_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip14_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip14_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay15; +wire soc_a7ddrphy_dq_i_nodelay15; +wire soc_a7ddrphy_dq_i_delayed15; +wire soc_a7ddrphy_dq_t15; +wire [7:0] soc_a7ddrphy_dq_i_data15; +wire [7:0] soc_a7ddrphy_bitslip15_i; +reg [7:0] soc_a7ddrphy_bitslip15_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip15_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip15_r = 16'd0; +wire [7:0] soc_a7ddrphy_rddata_en; +reg [7:0] soc_a7ddrphy_rddata_en_last = 8'd0; +wire [3:0] soc_a7ddrphy_wrdata_en; +reg [3:0] soc_a7ddrphy_wrdata_en_last = 4'd0; +wire [13:0] soc_sdram_inti_p0_address; +wire [2:0] soc_sdram_inti_p0_bank; +reg soc_sdram_inti_p0_cas_n = 1'd1; +reg soc_sdram_inti_p0_cs_n = 1'd1; +reg soc_sdram_inti_p0_ras_n = 1'd1; +reg soc_sdram_inti_p0_we_n = 1'd1; +wire soc_sdram_inti_p0_cke; +wire soc_sdram_inti_p0_odt; +wire soc_sdram_inti_p0_reset_n; +reg soc_sdram_inti_p0_act_n = 1'd1; +wire [31:0] soc_sdram_inti_p0_wrdata; +wire soc_sdram_inti_p0_wrdata_en; +wire [3:0] soc_sdram_inti_p0_wrdata_mask; +wire soc_sdram_inti_p0_rddata_en; +reg [31:0] soc_sdram_inti_p0_rddata = 32'd0; +reg soc_sdram_inti_p0_rddata_valid = 1'd0; +wire [13:0] soc_sdram_inti_p1_address; +wire [2:0] soc_sdram_inti_p1_bank; +reg soc_sdram_inti_p1_cas_n = 1'd1; +reg soc_sdram_inti_p1_cs_n = 1'd1; +reg soc_sdram_inti_p1_ras_n = 1'd1; +reg soc_sdram_inti_p1_we_n = 1'd1; +wire soc_sdram_inti_p1_cke; +wire soc_sdram_inti_p1_odt; +wire soc_sdram_inti_p1_reset_n; +reg soc_sdram_inti_p1_act_n = 1'd1; +wire [31:0] soc_sdram_inti_p1_wrdata; +wire soc_sdram_inti_p1_wrdata_en; +wire [3:0] soc_sdram_inti_p1_wrdata_mask; +wire soc_sdram_inti_p1_rddata_en; +reg [31:0] soc_sdram_inti_p1_rddata = 32'd0; +reg soc_sdram_inti_p1_rddata_valid = 1'd0; +wire [13:0] soc_sdram_inti_p2_address; +wire [2:0] soc_sdram_inti_p2_bank; +reg soc_sdram_inti_p2_cas_n = 1'd1; +reg soc_sdram_inti_p2_cs_n = 1'd1; +reg soc_sdram_inti_p2_ras_n = 1'd1; +reg soc_sdram_inti_p2_we_n = 1'd1; +wire soc_sdram_inti_p2_cke; +wire soc_sdram_inti_p2_odt; +wire soc_sdram_inti_p2_reset_n; +reg soc_sdram_inti_p2_act_n = 1'd1; +wire [31:0] soc_sdram_inti_p2_wrdata; +wire soc_sdram_inti_p2_wrdata_en; +wire [3:0] soc_sdram_inti_p2_wrdata_mask; +wire soc_sdram_inti_p2_rddata_en; +reg [31:0] soc_sdram_inti_p2_rddata = 32'd0; +reg soc_sdram_inti_p2_rddata_valid = 1'd0; +wire [13:0] soc_sdram_inti_p3_address; +wire [2:0] soc_sdram_inti_p3_bank; +reg soc_sdram_inti_p3_cas_n = 1'd1; +reg soc_sdram_inti_p3_cs_n = 1'd1; +reg soc_sdram_inti_p3_ras_n = 1'd1; +reg soc_sdram_inti_p3_we_n = 1'd1; +wire soc_sdram_inti_p3_cke; +wire soc_sdram_inti_p3_odt; +wire soc_sdram_inti_p3_reset_n; +reg soc_sdram_inti_p3_act_n = 1'd1; +wire [31:0] soc_sdram_inti_p3_wrdata; +wire soc_sdram_inti_p3_wrdata_en; +wire [3:0] soc_sdram_inti_p3_wrdata_mask; +wire soc_sdram_inti_p3_rddata_en; +reg [31:0] soc_sdram_inti_p3_rddata = 32'd0; +reg soc_sdram_inti_p3_rddata_valid = 1'd0; +wire [13:0] soc_sdram_slave_p0_address; +wire [2:0] soc_sdram_slave_p0_bank; +wire soc_sdram_slave_p0_cas_n; +wire soc_sdram_slave_p0_cs_n; +wire soc_sdram_slave_p0_ras_n; +wire soc_sdram_slave_p0_we_n; +wire soc_sdram_slave_p0_cke; +wire soc_sdram_slave_p0_odt; +wire soc_sdram_slave_p0_reset_n; +wire soc_sdram_slave_p0_act_n; +wire [31:0] soc_sdram_slave_p0_wrdata; +wire soc_sdram_slave_p0_wrdata_en; +wire [3:0] soc_sdram_slave_p0_wrdata_mask; +wire soc_sdram_slave_p0_rddata_en; +reg [31:0] soc_sdram_slave_p0_rddata = 32'd0; +reg soc_sdram_slave_p0_rddata_valid = 1'd0; +wire [13:0] soc_sdram_slave_p1_address; +wire [2:0] soc_sdram_slave_p1_bank; +wire soc_sdram_slave_p1_cas_n; +wire soc_sdram_slave_p1_cs_n; +wire soc_sdram_slave_p1_ras_n; +wire soc_sdram_slave_p1_we_n; +wire soc_sdram_slave_p1_cke; +wire soc_sdram_slave_p1_odt; +wire soc_sdram_slave_p1_reset_n; +wire soc_sdram_slave_p1_act_n; +wire [31:0] soc_sdram_slave_p1_wrdata; +wire soc_sdram_slave_p1_wrdata_en; +wire [3:0] soc_sdram_slave_p1_wrdata_mask; +wire soc_sdram_slave_p1_rddata_en; +reg [31:0] soc_sdram_slave_p1_rddata = 32'd0; +reg soc_sdram_slave_p1_rddata_valid = 1'd0; +wire [13:0] soc_sdram_slave_p2_address; +wire [2:0] soc_sdram_slave_p2_bank; +wire soc_sdram_slave_p2_cas_n; +wire soc_sdram_slave_p2_cs_n; +wire soc_sdram_slave_p2_ras_n; +wire soc_sdram_slave_p2_we_n; +wire soc_sdram_slave_p2_cke; +wire soc_sdram_slave_p2_odt; +wire soc_sdram_slave_p2_reset_n; +wire soc_sdram_slave_p2_act_n; +wire [31:0] soc_sdram_slave_p2_wrdata; +wire soc_sdram_slave_p2_wrdata_en; +wire [3:0] soc_sdram_slave_p2_wrdata_mask; +wire soc_sdram_slave_p2_rddata_en; +reg [31:0] soc_sdram_slave_p2_rddata = 32'd0; +reg soc_sdram_slave_p2_rddata_valid = 1'd0; +wire [13:0] soc_sdram_slave_p3_address; +wire [2:0] soc_sdram_slave_p3_bank; +wire soc_sdram_slave_p3_cas_n; +wire soc_sdram_slave_p3_cs_n; +wire soc_sdram_slave_p3_ras_n; +wire soc_sdram_slave_p3_we_n; +wire soc_sdram_slave_p3_cke; +wire soc_sdram_slave_p3_odt; +wire soc_sdram_slave_p3_reset_n; +wire soc_sdram_slave_p3_act_n; +wire [31:0] soc_sdram_slave_p3_wrdata; +wire soc_sdram_slave_p3_wrdata_en; +wire [3:0] soc_sdram_slave_p3_wrdata_mask; +wire soc_sdram_slave_p3_rddata_en; +reg [31:0] soc_sdram_slave_p3_rddata = 32'd0; +reg soc_sdram_slave_p3_rddata_valid = 1'd0; +reg [13:0] soc_sdram_master_p0_address = 14'd0; +reg [2:0] soc_sdram_master_p0_bank = 3'd0; +reg soc_sdram_master_p0_cas_n = 1'd1; +reg soc_sdram_master_p0_cs_n = 1'd1; +reg soc_sdram_master_p0_ras_n = 1'd1; +reg soc_sdram_master_p0_we_n = 1'd1; +reg soc_sdram_master_p0_cke = 1'd0; +reg soc_sdram_master_p0_odt = 1'd0; +reg soc_sdram_master_p0_reset_n = 1'd0; +reg soc_sdram_master_p0_act_n = 1'd1; +reg [31:0] soc_sdram_master_p0_wrdata = 32'd0; +reg soc_sdram_master_p0_wrdata_en = 1'd0; +reg [3:0] soc_sdram_master_p0_wrdata_mask = 4'd0; +reg soc_sdram_master_p0_rddata_en = 1'd0; +wire [31:0] soc_sdram_master_p0_rddata; +wire soc_sdram_master_p0_rddata_valid; +reg [13:0] soc_sdram_master_p1_address = 14'd0; +reg [2:0] soc_sdram_master_p1_bank = 3'd0; +reg soc_sdram_master_p1_cas_n = 1'd1; +reg soc_sdram_master_p1_cs_n = 1'd1; +reg soc_sdram_master_p1_ras_n = 1'd1; +reg soc_sdram_master_p1_we_n = 1'd1; +reg soc_sdram_master_p1_cke = 1'd0; +reg soc_sdram_master_p1_odt = 1'd0; +reg soc_sdram_master_p1_reset_n = 1'd0; +reg soc_sdram_master_p1_act_n = 1'd1; +reg [31:0] soc_sdram_master_p1_wrdata = 32'd0; +reg soc_sdram_master_p1_wrdata_en = 1'd0; +reg [3:0] soc_sdram_master_p1_wrdata_mask = 4'd0; +reg soc_sdram_master_p1_rddata_en = 1'd0; +wire [31:0] soc_sdram_master_p1_rddata; +wire soc_sdram_master_p1_rddata_valid; +reg [13:0] soc_sdram_master_p2_address = 14'd0; +reg [2:0] soc_sdram_master_p2_bank = 3'd0; +reg soc_sdram_master_p2_cas_n = 1'd1; +reg soc_sdram_master_p2_cs_n = 1'd1; +reg soc_sdram_master_p2_ras_n = 1'd1; +reg soc_sdram_master_p2_we_n = 1'd1; +reg soc_sdram_master_p2_cke = 1'd0; +reg soc_sdram_master_p2_odt = 1'd0; +reg soc_sdram_master_p2_reset_n = 1'd0; +reg soc_sdram_master_p2_act_n = 1'd1; +reg [31:0] soc_sdram_master_p2_wrdata = 32'd0; +reg soc_sdram_master_p2_wrdata_en = 1'd0; +reg [3:0] soc_sdram_master_p2_wrdata_mask = 4'd0; +reg soc_sdram_master_p2_rddata_en = 1'd0; +wire [31:0] soc_sdram_master_p2_rddata; +wire soc_sdram_master_p2_rddata_valid; +reg [13:0] soc_sdram_master_p3_address = 14'd0; +reg [2:0] soc_sdram_master_p3_bank = 3'd0; +reg soc_sdram_master_p3_cas_n = 1'd1; +reg soc_sdram_master_p3_cs_n = 1'd1; +reg soc_sdram_master_p3_ras_n = 1'd1; +reg soc_sdram_master_p3_we_n = 1'd1; +reg soc_sdram_master_p3_cke = 1'd0; +reg soc_sdram_master_p3_odt = 1'd0; +reg soc_sdram_master_p3_reset_n = 1'd0; +reg soc_sdram_master_p3_act_n = 1'd1; +reg [31:0] soc_sdram_master_p3_wrdata = 32'd0; +reg soc_sdram_master_p3_wrdata_en = 1'd0; +reg [3:0] soc_sdram_master_p3_wrdata_mask = 4'd0; +reg soc_sdram_master_p3_rddata_en = 1'd0; +wire [31:0] soc_sdram_master_p3_rddata; +wire soc_sdram_master_p3_rddata_valid; +reg [3:0] soc_sdram_storage = 4'd0; +reg soc_sdram_re = 1'd0; +reg [5:0] soc_sdram_phaseinjector0_command_storage = 6'd0; +reg soc_sdram_phaseinjector0_command_re = 1'd0; +wire soc_sdram_phaseinjector0_command_issue_re; +wire soc_sdram_phaseinjector0_command_issue_r; +wire soc_sdram_phaseinjector0_command_issue_we; +reg soc_sdram_phaseinjector0_command_issue_w = 1'd0; +reg [13:0] soc_sdram_phaseinjector0_address_storage = 14'd0; +reg soc_sdram_phaseinjector0_address_re = 1'd0; +reg [2:0] soc_sdram_phaseinjector0_baddress_storage = 3'd0; +reg soc_sdram_phaseinjector0_baddress_re = 1'd0; +reg [31:0] soc_sdram_phaseinjector0_wrdata_storage = 32'd0; +reg soc_sdram_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] soc_sdram_phaseinjector0_status = 32'd0; +wire soc_sdram_phaseinjector0_we; +reg [5:0] soc_sdram_phaseinjector1_command_storage = 6'd0; +reg soc_sdram_phaseinjector1_command_re = 1'd0; +wire soc_sdram_phaseinjector1_command_issue_re; +wire soc_sdram_phaseinjector1_command_issue_r; +wire soc_sdram_phaseinjector1_command_issue_we; +reg soc_sdram_phaseinjector1_command_issue_w = 1'd0; +reg [13:0] soc_sdram_phaseinjector1_address_storage = 14'd0; +reg soc_sdram_phaseinjector1_address_re = 1'd0; +reg [2:0] soc_sdram_phaseinjector1_baddress_storage = 3'd0; +reg soc_sdram_phaseinjector1_baddress_re = 1'd0; +reg [31:0] soc_sdram_phaseinjector1_wrdata_storage = 32'd0; +reg soc_sdram_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] soc_sdram_phaseinjector1_status = 32'd0; +wire soc_sdram_phaseinjector1_we; +reg [5:0] soc_sdram_phaseinjector2_command_storage = 6'd0; +reg soc_sdram_phaseinjector2_command_re = 1'd0; +wire soc_sdram_phaseinjector2_command_issue_re; +wire soc_sdram_phaseinjector2_command_issue_r; +wire soc_sdram_phaseinjector2_command_issue_we; +reg soc_sdram_phaseinjector2_command_issue_w = 1'd0; +reg [13:0] soc_sdram_phaseinjector2_address_storage = 14'd0; +reg soc_sdram_phaseinjector2_address_re = 1'd0; +reg [2:0] soc_sdram_phaseinjector2_baddress_storage = 3'd0; +reg soc_sdram_phaseinjector2_baddress_re = 1'd0; +reg [31:0] soc_sdram_phaseinjector2_wrdata_storage = 32'd0; +reg soc_sdram_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] soc_sdram_phaseinjector2_status = 32'd0; +wire soc_sdram_phaseinjector2_we; +reg [5:0] soc_sdram_phaseinjector3_command_storage = 6'd0; +reg soc_sdram_phaseinjector3_command_re = 1'd0; +wire soc_sdram_phaseinjector3_command_issue_re; +wire soc_sdram_phaseinjector3_command_issue_r; +wire soc_sdram_phaseinjector3_command_issue_we; +reg soc_sdram_phaseinjector3_command_issue_w = 1'd0; +reg [13:0] soc_sdram_phaseinjector3_address_storage = 14'd0; +reg soc_sdram_phaseinjector3_address_re = 1'd0; +reg [2:0] soc_sdram_phaseinjector3_baddress_storage = 3'd0; +reg soc_sdram_phaseinjector3_baddress_re = 1'd0; +reg [31:0] soc_sdram_phaseinjector3_wrdata_storage = 32'd0; +reg soc_sdram_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] soc_sdram_phaseinjector3_status = 32'd0; +wire soc_sdram_phaseinjector3_we; +wire soc_sdram_interface_bank0_valid; +wire soc_sdram_interface_bank0_ready; +wire soc_sdram_interface_bank0_we; +wire [20:0] soc_sdram_interface_bank0_addr; +wire soc_sdram_interface_bank0_lock; +wire soc_sdram_interface_bank0_wdata_ready; +wire soc_sdram_interface_bank0_rdata_valid; +wire soc_sdram_interface_bank1_valid; +wire soc_sdram_interface_bank1_ready; +wire soc_sdram_interface_bank1_we; +wire [20:0] soc_sdram_interface_bank1_addr; +wire soc_sdram_interface_bank1_lock; +wire soc_sdram_interface_bank1_wdata_ready; +wire soc_sdram_interface_bank1_rdata_valid; +wire soc_sdram_interface_bank2_valid; +wire soc_sdram_interface_bank2_ready; +wire soc_sdram_interface_bank2_we; +wire [20:0] soc_sdram_interface_bank2_addr; +wire soc_sdram_interface_bank2_lock; +wire soc_sdram_interface_bank2_wdata_ready; +wire soc_sdram_interface_bank2_rdata_valid; +wire soc_sdram_interface_bank3_valid; +wire soc_sdram_interface_bank3_ready; +wire soc_sdram_interface_bank3_we; +wire [20:0] soc_sdram_interface_bank3_addr; +wire soc_sdram_interface_bank3_lock; +wire soc_sdram_interface_bank3_wdata_ready; +wire soc_sdram_interface_bank3_rdata_valid; +wire soc_sdram_interface_bank4_valid; +wire soc_sdram_interface_bank4_ready; +wire soc_sdram_interface_bank4_we; +wire [20:0] soc_sdram_interface_bank4_addr; +wire soc_sdram_interface_bank4_lock; +wire soc_sdram_interface_bank4_wdata_ready; +wire soc_sdram_interface_bank4_rdata_valid; +wire soc_sdram_interface_bank5_valid; +wire soc_sdram_interface_bank5_ready; +wire soc_sdram_interface_bank5_we; +wire [20:0] soc_sdram_interface_bank5_addr; +wire soc_sdram_interface_bank5_lock; +wire soc_sdram_interface_bank5_wdata_ready; +wire soc_sdram_interface_bank5_rdata_valid; +wire soc_sdram_interface_bank6_valid; +wire soc_sdram_interface_bank6_ready; +wire soc_sdram_interface_bank6_we; +wire [20:0] soc_sdram_interface_bank6_addr; +wire soc_sdram_interface_bank6_lock; +wire soc_sdram_interface_bank6_wdata_ready; +wire soc_sdram_interface_bank6_rdata_valid; +wire soc_sdram_interface_bank7_valid; +wire soc_sdram_interface_bank7_ready; +wire soc_sdram_interface_bank7_we; +wire [20:0] soc_sdram_interface_bank7_addr; +wire soc_sdram_interface_bank7_lock; +wire soc_sdram_interface_bank7_wdata_ready; +wire soc_sdram_interface_bank7_rdata_valid; +reg [127:0] soc_sdram_interface_wdata = 128'd0; +reg [15:0] soc_sdram_interface_wdata_we = 16'd0; +wire [127:0] soc_sdram_interface_rdata; +reg [13:0] soc_sdram_dfi_p0_address = 14'd0; +reg [2:0] soc_sdram_dfi_p0_bank = 3'd0; +reg soc_sdram_dfi_p0_cas_n = 1'd1; +reg soc_sdram_dfi_p0_cs_n = 1'd1; +reg soc_sdram_dfi_p0_ras_n = 1'd1; +reg soc_sdram_dfi_p0_we_n = 1'd1; +wire soc_sdram_dfi_p0_cke; +wire soc_sdram_dfi_p0_odt; +wire soc_sdram_dfi_p0_reset_n; +reg soc_sdram_dfi_p0_act_n = 1'd1; +wire [31:0] soc_sdram_dfi_p0_wrdata; +reg soc_sdram_dfi_p0_wrdata_en = 1'd0; +wire [3:0] soc_sdram_dfi_p0_wrdata_mask; +reg soc_sdram_dfi_p0_rddata_en = 1'd0; +wire [31:0] soc_sdram_dfi_p0_rddata; +wire soc_sdram_dfi_p0_rddata_valid; +reg [13:0] soc_sdram_dfi_p1_address = 14'd0; +reg [2:0] soc_sdram_dfi_p1_bank = 3'd0; +reg soc_sdram_dfi_p1_cas_n = 1'd1; +reg soc_sdram_dfi_p1_cs_n = 1'd1; +reg soc_sdram_dfi_p1_ras_n = 1'd1; +reg soc_sdram_dfi_p1_we_n = 1'd1; +wire soc_sdram_dfi_p1_cke; +wire soc_sdram_dfi_p1_odt; +wire soc_sdram_dfi_p1_reset_n; +reg soc_sdram_dfi_p1_act_n = 1'd1; +wire [31:0] soc_sdram_dfi_p1_wrdata; +reg soc_sdram_dfi_p1_wrdata_en = 1'd0; +wire [3:0] soc_sdram_dfi_p1_wrdata_mask; +reg soc_sdram_dfi_p1_rddata_en = 1'd0; +wire [31:0] soc_sdram_dfi_p1_rddata; +wire soc_sdram_dfi_p1_rddata_valid; +reg [13:0] soc_sdram_dfi_p2_address = 14'd0; +reg [2:0] soc_sdram_dfi_p2_bank = 3'd0; +reg soc_sdram_dfi_p2_cas_n = 1'd1; +reg soc_sdram_dfi_p2_cs_n = 1'd1; +reg soc_sdram_dfi_p2_ras_n = 1'd1; +reg soc_sdram_dfi_p2_we_n = 1'd1; +wire soc_sdram_dfi_p2_cke; +wire soc_sdram_dfi_p2_odt; +wire soc_sdram_dfi_p2_reset_n; +reg soc_sdram_dfi_p2_act_n = 1'd1; +wire [31:0] soc_sdram_dfi_p2_wrdata; +reg soc_sdram_dfi_p2_wrdata_en = 1'd0; +wire [3:0] soc_sdram_dfi_p2_wrdata_mask; +reg soc_sdram_dfi_p2_rddata_en = 1'd0; +wire [31:0] soc_sdram_dfi_p2_rddata; +wire soc_sdram_dfi_p2_rddata_valid; +reg [13:0] soc_sdram_dfi_p3_address = 14'd0; +reg [2:0] soc_sdram_dfi_p3_bank = 3'd0; +reg soc_sdram_dfi_p3_cas_n = 1'd1; +reg soc_sdram_dfi_p3_cs_n = 1'd1; +reg soc_sdram_dfi_p3_ras_n = 1'd1; +reg soc_sdram_dfi_p3_we_n = 1'd1; +wire soc_sdram_dfi_p3_cke; +wire soc_sdram_dfi_p3_odt; +wire soc_sdram_dfi_p3_reset_n; +reg soc_sdram_dfi_p3_act_n = 1'd1; +wire [31:0] soc_sdram_dfi_p3_wrdata; +reg soc_sdram_dfi_p3_wrdata_en = 1'd0; +wire [3:0] soc_sdram_dfi_p3_wrdata_mask; +reg soc_sdram_dfi_p3_rddata_en = 1'd0; +wire [31:0] soc_sdram_dfi_p3_rddata; +wire soc_sdram_dfi_p3_rddata_valid; +reg soc_sdram_cmd_valid = 1'd0; +reg soc_sdram_cmd_ready = 1'd0; +reg soc_sdram_cmd_last = 1'd0; +reg [13:0] soc_sdram_cmd_payload_a = 14'd0; +reg [2:0] soc_sdram_cmd_payload_ba = 3'd0; +reg soc_sdram_cmd_payload_cas = 1'd0; +reg soc_sdram_cmd_payload_ras = 1'd0; +reg soc_sdram_cmd_payload_we = 1'd0; +reg soc_sdram_cmd_payload_is_read = 1'd0; +reg soc_sdram_cmd_payload_is_write = 1'd0; +wire soc_sdram_wants_refresh; +wire soc_sdram_wants_zqcs; +wire soc_sdram_timer_wait; +wire soc_sdram_timer_done0; +wire [9:0] soc_sdram_timer_count0; +wire soc_sdram_timer_done1; +reg [9:0] soc_sdram_timer_count1 = 10'd781; +wire soc_sdram_postponer_req_i; +reg soc_sdram_postponer_req_o = 1'd0; +reg soc_sdram_postponer_count = 1'd0; +reg soc_sdram_sequencer_start0 = 1'd0; +wire soc_sdram_sequencer_done0; +wire soc_sdram_sequencer_start1; +reg soc_sdram_sequencer_done1 = 1'd0; +reg [5:0] soc_sdram_sequencer_counter = 6'd0; +reg soc_sdram_sequencer_count = 1'd0; +wire soc_sdram_zqcs_timer_wait; +wire soc_sdram_zqcs_timer_done0; +wire [26:0] soc_sdram_zqcs_timer_count0; +wire soc_sdram_zqcs_timer_done1; +reg [26:0] soc_sdram_zqcs_timer_count1 = 27'd99999999; +reg soc_sdram_zqcs_executer_start = 1'd0; +reg soc_sdram_zqcs_executer_done = 1'd0; +reg [4:0] soc_sdram_zqcs_executer_counter = 5'd0; +wire soc_sdram_bankmachine0_req_valid; +wire soc_sdram_bankmachine0_req_ready; +wire soc_sdram_bankmachine0_req_we; +wire [20:0] soc_sdram_bankmachine0_req_addr; +wire soc_sdram_bankmachine0_req_lock; +reg soc_sdram_bankmachine0_req_wdata_ready = 1'd0; +reg soc_sdram_bankmachine0_req_rdata_valid = 1'd0; +wire soc_sdram_bankmachine0_refresh_req; +reg soc_sdram_bankmachine0_refresh_gnt = 1'd0; +reg soc_sdram_bankmachine0_cmd_valid = 1'd0; +reg soc_sdram_bankmachine0_cmd_ready = 1'd0; +reg [13:0] soc_sdram_bankmachine0_cmd_payload_a = 14'd0; +wire [2:0] soc_sdram_bankmachine0_cmd_payload_ba; +reg soc_sdram_bankmachine0_cmd_payload_cas = 1'd0; +reg soc_sdram_bankmachine0_cmd_payload_ras = 1'd0; +reg soc_sdram_bankmachine0_cmd_payload_we = 1'd0; +reg soc_sdram_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg soc_sdram_bankmachine0_cmd_payload_is_read = 1'd0; +reg soc_sdram_bankmachine0_cmd_payload_is_write = 1'd0; +reg soc_sdram_bankmachine0_auto_precharge = 1'd0; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready; +reg soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we; +wire [20:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +wire [23:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +wire [23:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +reg [4:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_level = 5'd0; +reg soc_sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we; +wire [23:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read; +wire [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr; +wire [23:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +wire soc_sdram_bankmachine0_cmd_buffer_sink_valid; +wire soc_sdram_bankmachine0_cmd_buffer_sink_ready; +wire soc_sdram_bankmachine0_cmd_buffer_sink_first; +wire soc_sdram_bankmachine0_cmd_buffer_sink_last; +wire soc_sdram_bankmachine0_cmd_buffer_sink_payload_we; +wire [20:0] soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr; +reg soc_sdram_bankmachine0_cmd_buffer_source_valid = 1'd0; +wire soc_sdram_bankmachine0_cmd_buffer_source_ready; +reg soc_sdram_bankmachine0_cmd_buffer_source_first = 1'd0; +reg soc_sdram_bankmachine0_cmd_buffer_source_last = 1'd0; +reg soc_sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_sdram_bankmachine0_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_sdram_bankmachine0_row = 14'd0; +reg soc_sdram_bankmachine0_row_opened = 1'd0; +wire soc_sdram_bankmachine0_row_hit; +reg soc_sdram_bankmachine0_row_open = 1'd0; +reg soc_sdram_bankmachine0_row_close = 1'd0; +reg soc_sdram_bankmachine0_row_col_n_addr_sel = 1'd0; +wire soc_sdram_bankmachine0_twtpcon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine0_twtpcon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine0_twtpcon_count = 3'd0; +wire soc_sdram_bankmachine0_trccon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine0_trccon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine0_trccon_count = 3'd0; +wire soc_sdram_bankmachine0_trascon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine0_trascon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine0_trascon_count = 3'd0; +wire soc_sdram_bankmachine1_req_valid; +wire soc_sdram_bankmachine1_req_ready; +wire soc_sdram_bankmachine1_req_we; +wire [20:0] soc_sdram_bankmachine1_req_addr; +wire soc_sdram_bankmachine1_req_lock; +reg soc_sdram_bankmachine1_req_wdata_ready = 1'd0; +reg soc_sdram_bankmachine1_req_rdata_valid = 1'd0; +wire soc_sdram_bankmachine1_refresh_req; +reg soc_sdram_bankmachine1_refresh_gnt = 1'd0; +reg soc_sdram_bankmachine1_cmd_valid = 1'd0; +reg soc_sdram_bankmachine1_cmd_ready = 1'd0; +reg [13:0] soc_sdram_bankmachine1_cmd_payload_a = 14'd0; +wire [2:0] soc_sdram_bankmachine1_cmd_payload_ba; +reg soc_sdram_bankmachine1_cmd_payload_cas = 1'd0; +reg soc_sdram_bankmachine1_cmd_payload_ras = 1'd0; +reg soc_sdram_bankmachine1_cmd_payload_we = 1'd0; +reg soc_sdram_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg soc_sdram_bankmachine1_cmd_payload_is_read = 1'd0; +reg soc_sdram_bankmachine1_cmd_payload_is_write = 1'd0; +reg soc_sdram_bankmachine1_auto_precharge = 1'd0; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready; +reg soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we; +wire [20:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +wire [23:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +wire [23:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +reg [4:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_level = 5'd0; +reg soc_sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we; +wire [23:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read; +wire [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr; +wire [23:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +wire soc_sdram_bankmachine1_cmd_buffer_sink_valid; +wire soc_sdram_bankmachine1_cmd_buffer_sink_ready; +wire soc_sdram_bankmachine1_cmd_buffer_sink_first; +wire soc_sdram_bankmachine1_cmd_buffer_sink_last; +wire soc_sdram_bankmachine1_cmd_buffer_sink_payload_we; +wire [20:0] soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr; +reg soc_sdram_bankmachine1_cmd_buffer_source_valid = 1'd0; +wire soc_sdram_bankmachine1_cmd_buffer_source_ready; +reg soc_sdram_bankmachine1_cmd_buffer_source_first = 1'd0; +reg soc_sdram_bankmachine1_cmd_buffer_source_last = 1'd0; +reg soc_sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_sdram_bankmachine1_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_sdram_bankmachine1_row = 14'd0; +reg soc_sdram_bankmachine1_row_opened = 1'd0; +wire soc_sdram_bankmachine1_row_hit; +reg soc_sdram_bankmachine1_row_open = 1'd0; +reg soc_sdram_bankmachine1_row_close = 1'd0; +reg soc_sdram_bankmachine1_row_col_n_addr_sel = 1'd0; +wire soc_sdram_bankmachine1_twtpcon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine1_twtpcon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine1_twtpcon_count = 3'd0; +wire soc_sdram_bankmachine1_trccon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine1_trccon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine1_trccon_count = 3'd0; +wire soc_sdram_bankmachine1_trascon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine1_trascon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine1_trascon_count = 3'd0; +wire soc_sdram_bankmachine2_req_valid; +wire soc_sdram_bankmachine2_req_ready; +wire soc_sdram_bankmachine2_req_we; +wire [20:0] soc_sdram_bankmachine2_req_addr; +wire soc_sdram_bankmachine2_req_lock; +reg soc_sdram_bankmachine2_req_wdata_ready = 1'd0; +reg soc_sdram_bankmachine2_req_rdata_valid = 1'd0; +wire soc_sdram_bankmachine2_refresh_req; +reg soc_sdram_bankmachine2_refresh_gnt = 1'd0; +reg soc_sdram_bankmachine2_cmd_valid = 1'd0; +reg soc_sdram_bankmachine2_cmd_ready = 1'd0; +reg [13:0] soc_sdram_bankmachine2_cmd_payload_a = 14'd0; +wire [2:0] soc_sdram_bankmachine2_cmd_payload_ba; +reg soc_sdram_bankmachine2_cmd_payload_cas = 1'd0; +reg soc_sdram_bankmachine2_cmd_payload_ras = 1'd0; +reg soc_sdram_bankmachine2_cmd_payload_we = 1'd0; +reg soc_sdram_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg soc_sdram_bankmachine2_cmd_payload_is_read = 1'd0; +reg soc_sdram_bankmachine2_cmd_payload_is_write = 1'd0; +reg soc_sdram_bankmachine2_auto_precharge = 1'd0; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready; +reg soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we; +wire [20:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +wire [23:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +wire [23:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +reg [4:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_level = 5'd0; +reg soc_sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we; +wire [23:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read; +wire [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr; +wire [23:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +wire soc_sdram_bankmachine2_cmd_buffer_sink_valid; +wire soc_sdram_bankmachine2_cmd_buffer_sink_ready; +wire soc_sdram_bankmachine2_cmd_buffer_sink_first; +wire soc_sdram_bankmachine2_cmd_buffer_sink_last; +wire soc_sdram_bankmachine2_cmd_buffer_sink_payload_we; +wire [20:0] soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr; +reg soc_sdram_bankmachine2_cmd_buffer_source_valid = 1'd0; +wire soc_sdram_bankmachine2_cmd_buffer_source_ready; +reg soc_sdram_bankmachine2_cmd_buffer_source_first = 1'd0; +reg soc_sdram_bankmachine2_cmd_buffer_source_last = 1'd0; +reg soc_sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_sdram_bankmachine2_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_sdram_bankmachine2_row = 14'd0; +reg soc_sdram_bankmachine2_row_opened = 1'd0; +wire soc_sdram_bankmachine2_row_hit; +reg soc_sdram_bankmachine2_row_open = 1'd0; +reg soc_sdram_bankmachine2_row_close = 1'd0; +reg soc_sdram_bankmachine2_row_col_n_addr_sel = 1'd0; +wire soc_sdram_bankmachine2_twtpcon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine2_twtpcon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine2_twtpcon_count = 3'd0; +wire soc_sdram_bankmachine2_trccon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine2_trccon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine2_trccon_count = 3'd0; +wire soc_sdram_bankmachine2_trascon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine2_trascon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine2_trascon_count = 3'd0; +wire soc_sdram_bankmachine3_req_valid; +wire soc_sdram_bankmachine3_req_ready; +wire soc_sdram_bankmachine3_req_we; +wire [20:0] soc_sdram_bankmachine3_req_addr; +wire soc_sdram_bankmachine3_req_lock; +reg soc_sdram_bankmachine3_req_wdata_ready = 1'd0; +reg soc_sdram_bankmachine3_req_rdata_valid = 1'd0; +wire soc_sdram_bankmachine3_refresh_req; +reg soc_sdram_bankmachine3_refresh_gnt = 1'd0; +reg soc_sdram_bankmachine3_cmd_valid = 1'd0; +reg soc_sdram_bankmachine3_cmd_ready = 1'd0; +reg [13:0] soc_sdram_bankmachine3_cmd_payload_a = 14'd0; +wire [2:0] soc_sdram_bankmachine3_cmd_payload_ba; +reg soc_sdram_bankmachine3_cmd_payload_cas = 1'd0; +reg soc_sdram_bankmachine3_cmd_payload_ras = 1'd0; +reg soc_sdram_bankmachine3_cmd_payload_we = 1'd0; +reg soc_sdram_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg soc_sdram_bankmachine3_cmd_payload_is_read = 1'd0; +reg soc_sdram_bankmachine3_cmd_payload_is_write = 1'd0; +reg soc_sdram_bankmachine3_auto_precharge = 1'd0; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready; +reg soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we; +wire [20:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +wire [23:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +wire [23:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +reg [4:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_level = 5'd0; +reg soc_sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we; +wire [23:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read; +wire [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr; +wire [23:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +wire soc_sdram_bankmachine3_cmd_buffer_sink_valid; +wire soc_sdram_bankmachine3_cmd_buffer_sink_ready; +wire soc_sdram_bankmachine3_cmd_buffer_sink_first; +wire soc_sdram_bankmachine3_cmd_buffer_sink_last; +wire soc_sdram_bankmachine3_cmd_buffer_sink_payload_we; +wire [20:0] soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr; +reg soc_sdram_bankmachine3_cmd_buffer_source_valid = 1'd0; +wire soc_sdram_bankmachine3_cmd_buffer_source_ready; +reg soc_sdram_bankmachine3_cmd_buffer_source_first = 1'd0; +reg soc_sdram_bankmachine3_cmd_buffer_source_last = 1'd0; +reg soc_sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_sdram_bankmachine3_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_sdram_bankmachine3_row = 14'd0; +reg soc_sdram_bankmachine3_row_opened = 1'd0; +wire soc_sdram_bankmachine3_row_hit; +reg soc_sdram_bankmachine3_row_open = 1'd0; +reg soc_sdram_bankmachine3_row_close = 1'd0; +reg soc_sdram_bankmachine3_row_col_n_addr_sel = 1'd0; +wire soc_sdram_bankmachine3_twtpcon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine3_twtpcon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine3_twtpcon_count = 3'd0; +wire soc_sdram_bankmachine3_trccon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine3_trccon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine3_trccon_count = 3'd0; +wire soc_sdram_bankmachine3_trascon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine3_trascon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine3_trascon_count = 3'd0; +wire soc_sdram_bankmachine4_req_valid; +wire soc_sdram_bankmachine4_req_ready; +wire soc_sdram_bankmachine4_req_we; +wire [20:0] soc_sdram_bankmachine4_req_addr; +wire soc_sdram_bankmachine4_req_lock; +reg soc_sdram_bankmachine4_req_wdata_ready = 1'd0; +reg soc_sdram_bankmachine4_req_rdata_valid = 1'd0; +wire soc_sdram_bankmachine4_refresh_req; +reg soc_sdram_bankmachine4_refresh_gnt = 1'd0; +reg soc_sdram_bankmachine4_cmd_valid = 1'd0; +reg soc_sdram_bankmachine4_cmd_ready = 1'd0; +reg [13:0] soc_sdram_bankmachine4_cmd_payload_a = 14'd0; +wire [2:0] soc_sdram_bankmachine4_cmd_payload_ba; +reg soc_sdram_bankmachine4_cmd_payload_cas = 1'd0; +reg soc_sdram_bankmachine4_cmd_payload_ras = 1'd0; +reg soc_sdram_bankmachine4_cmd_payload_we = 1'd0; +reg soc_sdram_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg soc_sdram_bankmachine4_cmd_payload_is_read = 1'd0; +reg soc_sdram_bankmachine4_cmd_payload_is_write = 1'd0; +reg soc_sdram_bankmachine4_auto_precharge = 1'd0; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready; +reg soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we; +wire [20:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +wire [23:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +wire [23:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +reg [4:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_level = 5'd0; +reg soc_sdram_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we; +wire [23:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read; +wire [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr; +wire [23:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +wire soc_sdram_bankmachine4_cmd_buffer_sink_valid; +wire soc_sdram_bankmachine4_cmd_buffer_sink_ready; +wire soc_sdram_bankmachine4_cmd_buffer_sink_first; +wire soc_sdram_bankmachine4_cmd_buffer_sink_last; +wire soc_sdram_bankmachine4_cmd_buffer_sink_payload_we; +wire [20:0] soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr; +reg soc_sdram_bankmachine4_cmd_buffer_source_valid = 1'd0; +wire soc_sdram_bankmachine4_cmd_buffer_source_ready; +reg soc_sdram_bankmachine4_cmd_buffer_source_first = 1'd0; +reg soc_sdram_bankmachine4_cmd_buffer_source_last = 1'd0; +reg soc_sdram_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_sdram_bankmachine4_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_sdram_bankmachine4_row = 14'd0; +reg soc_sdram_bankmachine4_row_opened = 1'd0; +wire soc_sdram_bankmachine4_row_hit; +reg soc_sdram_bankmachine4_row_open = 1'd0; +reg soc_sdram_bankmachine4_row_close = 1'd0; +reg soc_sdram_bankmachine4_row_col_n_addr_sel = 1'd0; +wire soc_sdram_bankmachine4_twtpcon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine4_twtpcon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine4_twtpcon_count = 3'd0; +wire soc_sdram_bankmachine4_trccon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine4_trccon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine4_trccon_count = 3'd0; +wire soc_sdram_bankmachine4_trascon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine4_trascon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine4_trascon_count = 3'd0; +wire soc_sdram_bankmachine5_req_valid; +wire soc_sdram_bankmachine5_req_ready; +wire soc_sdram_bankmachine5_req_we; +wire [20:0] soc_sdram_bankmachine5_req_addr; +wire soc_sdram_bankmachine5_req_lock; +reg soc_sdram_bankmachine5_req_wdata_ready = 1'd0; +reg soc_sdram_bankmachine5_req_rdata_valid = 1'd0; +wire soc_sdram_bankmachine5_refresh_req; +reg soc_sdram_bankmachine5_refresh_gnt = 1'd0; +reg soc_sdram_bankmachine5_cmd_valid = 1'd0; +reg soc_sdram_bankmachine5_cmd_ready = 1'd0; +reg [13:0] soc_sdram_bankmachine5_cmd_payload_a = 14'd0; +wire [2:0] soc_sdram_bankmachine5_cmd_payload_ba; +reg soc_sdram_bankmachine5_cmd_payload_cas = 1'd0; +reg soc_sdram_bankmachine5_cmd_payload_ras = 1'd0; +reg soc_sdram_bankmachine5_cmd_payload_we = 1'd0; +reg soc_sdram_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg soc_sdram_bankmachine5_cmd_payload_is_read = 1'd0; +reg soc_sdram_bankmachine5_cmd_payload_is_write = 1'd0; +reg soc_sdram_bankmachine5_auto_precharge = 1'd0; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready; +reg soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we; +wire [20:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +wire [23:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +wire [23:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +reg [4:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_level = 5'd0; +reg soc_sdram_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we; +wire [23:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read; +wire [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr; +wire [23:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +wire soc_sdram_bankmachine5_cmd_buffer_sink_valid; +wire soc_sdram_bankmachine5_cmd_buffer_sink_ready; +wire soc_sdram_bankmachine5_cmd_buffer_sink_first; +wire soc_sdram_bankmachine5_cmd_buffer_sink_last; +wire soc_sdram_bankmachine5_cmd_buffer_sink_payload_we; +wire [20:0] soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr; +reg soc_sdram_bankmachine5_cmd_buffer_source_valid = 1'd0; +wire soc_sdram_bankmachine5_cmd_buffer_source_ready; +reg soc_sdram_bankmachine5_cmd_buffer_source_first = 1'd0; +reg soc_sdram_bankmachine5_cmd_buffer_source_last = 1'd0; +reg soc_sdram_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_sdram_bankmachine5_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_sdram_bankmachine5_row = 14'd0; +reg soc_sdram_bankmachine5_row_opened = 1'd0; +wire soc_sdram_bankmachine5_row_hit; +reg soc_sdram_bankmachine5_row_open = 1'd0; +reg soc_sdram_bankmachine5_row_close = 1'd0; +reg soc_sdram_bankmachine5_row_col_n_addr_sel = 1'd0; +wire soc_sdram_bankmachine5_twtpcon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine5_twtpcon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine5_twtpcon_count = 3'd0; +wire soc_sdram_bankmachine5_trccon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine5_trccon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine5_trccon_count = 3'd0; +wire soc_sdram_bankmachine5_trascon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine5_trascon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine5_trascon_count = 3'd0; +wire soc_sdram_bankmachine6_req_valid; +wire soc_sdram_bankmachine6_req_ready; +wire soc_sdram_bankmachine6_req_we; +wire [20:0] soc_sdram_bankmachine6_req_addr; +wire soc_sdram_bankmachine6_req_lock; +reg soc_sdram_bankmachine6_req_wdata_ready = 1'd0; +reg soc_sdram_bankmachine6_req_rdata_valid = 1'd0; +wire soc_sdram_bankmachine6_refresh_req; +reg soc_sdram_bankmachine6_refresh_gnt = 1'd0; +reg soc_sdram_bankmachine6_cmd_valid = 1'd0; +reg soc_sdram_bankmachine6_cmd_ready = 1'd0; +reg [13:0] soc_sdram_bankmachine6_cmd_payload_a = 14'd0; +wire [2:0] soc_sdram_bankmachine6_cmd_payload_ba; +reg soc_sdram_bankmachine6_cmd_payload_cas = 1'd0; +reg soc_sdram_bankmachine6_cmd_payload_ras = 1'd0; +reg soc_sdram_bankmachine6_cmd_payload_we = 1'd0; +reg soc_sdram_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg soc_sdram_bankmachine6_cmd_payload_is_read = 1'd0; +reg soc_sdram_bankmachine6_cmd_payload_is_write = 1'd0; +reg soc_sdram_bankmachine6_auto_precharge = 1'd0; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready; +reg soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we; +wire [20:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +wire [23:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +wire [23:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +reg [4:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_level = 5'd0; +reg soc_sdram_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we; +wire [23:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read; +wire [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr; +wire [23:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +wire soc_sdram_bankmachine6_cmd_buffer_sink_valid; +wire soc_sdram_bankmachine6_cmd_buffer_sink_ready; +wire soc_sdram_bankmachine6_cmd_buffer_sink_first; +wire soc_sdram_bankmachine6_cmd_buffer_sink_last; +wire soc_sdram_bankmachine6_cmd_buffer_sink_payload_we; +wire [20:0] soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr; +reg soc_sdram_bankmachine6_cmd_buffer_source_valid = 1'd0; +wire soc_sdram_bankmachine6_cmd_buffer_source_ready; +reg soc_sdram_bankmachine6_cmd_buffer_source_first = 1'd0; +reg soc_sdram_bankmachine6_cmd_buffer_source_last = 1'd0; +reg soc_sdram_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_sdram_bankmachine6_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_sdram_bankmachine6_row = 14'd0; +reg soc_sdram_bankmachine6_row_opened = 1'd0; +wire soc_sdram_bankmachine6_row_hit; +reg soc_sdram_bankmachine6_row_open = 1'd0; +reg soc_sdram_bankmachine6_row_close = 1'd0; +reg soc_sdram_bankmachine6_row_col_n_addr_sel = 1'd0; +wire soc_sdram_bankmachine6_twtpcon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine6_twtpcon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine6_twtpcon_count = 3'd0; +wire soc_sdram_bankmachine6_trccon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine6_trccon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine6_trccon_count = 3'd0; +wire soc_sdram_bankmachine6_trascon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine6_trascon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine6_trascon_count = 3'd0; +wire soc_sdram_bankmachine7_req_valid; +wire soc_sdram_bankmachine7_req_ready; +wire soc_sdram_bankmachine7_req_we; +wire [20:0] soc_sdram_bankmachine7_req_addr; +wire soc_sdram_bankmachine7_req_lock; +reg soc_sdram_bankmachine7_req_wdata_ready = 1'd0; +reg soc_sdram_bankmachine7_req_rdata_valid = 1'd0; +wire soc_sdram_bankmachine7_refresh_req; +reg soc_sdram_bankmachine7_refresh_gnt = 1'd0; +reg soc_sdram_bankmachine7_cmd_valid = 1'd0; +reg soc_sdram_bankmachine7_cmd_ready = 1'd0; +reg [13:0] soc_sdram_bankmachine7_cmd_payload_a = 14'd0; +wire [2:0] soc_sdram_bankmachine7_cmd_payload_ba; +reg soc_sdram_bankmachine7_cmd_payload_cas = 1'd0; +reg soc_sdram_bankmachine7_cmd_payload_ras = 1'd0; +reg soc_sdram_bankmachine7_cmd_payload_we = 1'd0; +reg soc_sdram_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg soc_sdram_bankmachine7_cmd_payload_is_read = 1'd0; +reg soc_sdram_bankmachine7_cmd_payload_is_write = 1'd0; +reg soc_sdram_bankmachine7_auto_precharge = 1'd0; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready; +reg soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we; +wire [20:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +wire [23:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +wire [23:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +reg [4:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_level = 5'd0; +reg soc_sdram_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we; +wire [23:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read; +wire [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr; +wire [23:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +wire soc_sdram_bankmachine7_cmd_buffer_sink_valid; +wire soc_sdram_bankmachine7_cmd_buffer_sink_ready; +wire soc_sdram_bankmachine7_cmd_buffer_sink_first; +wire soc_sdram_bankmachine7_cmd_buffer_sink_last; +wire soc_sdram_bankmachine7_cmd_buffer_sink_payload_we; +wire [20:0] soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr; +reg soc_sdram_bankmachine7_cmd_buffer_source_valid = 1'd0; +wire soc_sdram_bankmachine7_cmd_buffer_source_ready; +reg soc_sdram_bankmachine7_cmd_buffer_source_first = 1'd0; +reg soc_sdram_bankmachine7_cmd_buffer_source_last = 1'd0; +reg soc_sdram_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_sdram_bankmachine7_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_sdram_bankmachine7_row = 14'd0; +reg soc_sdram_bankmachine7_row_opened = 1'd0; +wire soc_sdram_bankmachine7_row_hit; +reg soc_sdram_bankmachine7_row_open = 1'd0; +reg soc_sdram_bankmachine7_row_close = 1'd0; +reg soc_sdram_bankmachine7_row_col_n_addr_sel = 1'd0; +wire soc_sdram_bankmachine7_twtpcon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine7_twtpcon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine7_twtpcon_count = 3'd0; +wire soc_sdram_bankmachine7_trccon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine7_trccon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine7_trccon_count = 3'd0; +wire soc_sdram_bankmachine7_trascon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine7_trascon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine7_trascon_count = 3'd0; +wire soc_sdram_ras_allowed; +wire soc_sdram_cas_allowed; +reg soc_sdram_choose_cmd_want_reads = 1'd0; +reg soc_sdram_choose_cmd_want_writes = 1'd0; +reg soc_sdram_choose_cmd_want_cmds = 1'd0; +reg soc_sdram_choose_cmd_want_activates = 1'd0; +wire soc_sdram_choose_cmd_cmd_valid; +reg soc_sdram_choose_cmd_cmd_ready = 1'd0; +wire [13:0] soc_sdram_choose_cmd_cmd_payload_a; +wire [2:0] soc_sdram_choose_cmd_cmd_payload_ba; +reg soc_sdram_choose_cmd_cmd_payload_cas = 1'd0; +reg soc_sdram_choose_cmd_cmd_payload_ras = 1'd0; +reg soc_sdram_choose_cmd_cmd_payload_we = 1'd0; +wire soc_sdram_choose_cmd_cmd_payload_is_cmd; +wire soc_sdram_choose_cmd_cmd_payload_is_read; +wire soc_sdram_choose_cmd_cmd_payload_is_write; +reg [7:0] soc_sdram_choose_cmd_valids = 8'd0; +wire [7:0] soc_sdram_choose_cmd_request; +reg [2:0] soc_sdram_choose_cmd_grant = 3'd0; +wire soc_sdram_choose_cmd_ce; +reg soc_sdram_choose_req_want_reads = 1'd0; +reg soc_sdram_choose_req_want_writes = 1'd0; +reg soc_sdram_choose_req_want_cmds = 1'd0; +reg soc_sdram_choose_req_want_activates = 1'd0; +wire soc_sdram_choose_req_cmd_valid; +reg soc_sdram_choose_req_cmd_ready = 1'd0; +wire [13:0] soc_sdram_choose_req_cmd_payload_a; +wire [2:0] soc_sdram_choose_req_cmd_payload_ba; +reg soc_sdram_choose_req_cmd_payload_cas = 1'd0; +reg soc_sdram_choose_req_cmd_payload_ras = 1'd0; +reg soc_sdram_choose_req_cmd_payload_we = 1'd0; +wire soc_sdram_choose_req_cmd_payload_is_cmd; +wire soc_sdram_choose_req_cmd_payload_is_read; +wire soc_sdram_choose_req_cmd_payload_is_write; +reg [7:0] soc_sdram_choose_req_valids = 8'd0; +wire [7:0] soc_sdram_choose_req_request; +reg [2:0] soc_sdram_choose_req_grant = 3'd0; +wire soc_sdram_choose_req_ce; +reg [13:0] soc_sdram_nop_a = 14'd0; +reg [2:0] soc_sdram_nop_ba = 3'd0; +reg [1:0] soc_sdram_steerer_sel0 = 2'd0; +reg [1:0] soc_sdram_steerer_sel1 = 2'd0; +reg [1:0] soc_sdram_steerer_sel2 = 2'd0; +reg [1:0] soc_sdram_steerer_sel3 = 2'd0; +reg soc_sdram_steerer0 = 1'd1; +reg soc_sdram_steerer1 = 1'd1; +reg soc_sdram_steerer2 = 1'd1; +reg soc_sdram_steerer3 = 1'd1; +reg soc_sdram_steerer4 = 1'd1; +reg soc_sdram_steerer5 = 1'd1; +reg soc_sdram_steerer6 = 1'd1; +reg soc_sdram_steerer7 = 1'd1; +wire soc_sdram_trrdcon_valid; +(* dont_touch = "true" *) reg soc_sdram_trrdcon_ready = 1'd1; +reg soc_sdram_trrdcon_count = 1'd0; +wire soc_sdram_tfawcon_valid; +(* dont_touch = "true" *) reg soc_sdram_tfawcon_ready = 1'd1; +wire [2:0] soc_sdram_tfawcon_count; +reg [4:0] soc_sdram_tfawcon_window = 5'd0; +wire soc_sdram_tccdcon_valid; +(* dont_touch = "true" *) reg soc_sdram_tccdcon_ready = 1'd1; +reg soc_sdram_tccdcon_count = 1'd0; +wire soc_sdram_twtrcon_valid; +(* dont_touch = "true" *) reg soc_sdram_twtrcon_ready = 1'd1; +reg [2:0] soc_sdram_twtrcon_count = 3'd0; +wire soc_sdram_read_available; +wire soc_sdram_write_available; +reg soc_sdram_en0 = 1'd0; +wire soc_sdram_max_time0; +reg [4:0] soc_sdram_time0 = 5'd0; +reg soc_sdram_en1 = 1'd0; +wire soc_sdram_max_time1; +reg [3:0] soc_sdram_time1 = 4'd0; +wire soc_sdram_go_to_refresh; +reg soc_port_cmd_valid = 1'd0; +wire soc_port_cmd_ready; +reg soc_port_cmd_payload_we = 1'd0; +reg [23:0] soc_port_cmd_payload_addr = 24'd0; +wire soc_port_wdata_valid; +wire soc_port_wdata_ready; +wire soc_port_wdata_first; +wire soc_port_wdata_last; +wire [127:0] soc_port_wdata_payload_data; +wire [15:0] soc_port_wdata_payload_we; +wire soc_port_rdata_valid; +wire soc_port_rdata_ready; +reg soc_port_rdata_first = 1'd0; +reg soc_port_rdata_last = 1'd0; +wire [127:0] soc_port_rdata_payload_data; +wire [29:0] soc_wb_sdram_adr; +wire [31:0] soc_wb_sdram_dat_w; +reg [31:0] soc_wb_sdram_dat_r = 32'd0; +wire [3:0] soc_wb_sdram_sel; +wire soc_wb_sdram_cyc; +wire soc_wb_sdram_stb; +reg soc_wb_sdram_ack = 1'd0; +wire soc_wb_sdram_we; +wire [2:0] soc_wb_sdram_cti; +wire [1:0] soc_wb_sdram_bte; +reg soc_wb_sdram_err = 1'd0; +wire [29:0] soc_litedram_wb_adr; +reg [127:0] soc_litedram_wb_dat_w = 128'd0; +wire [127:0] soc_litedram_wb_dat_r; +reg [15:0] soc_litedram_wb_sel = 16'd0; +reg soc_litedram_wb_cyc = 1'd0; +reg soc_litedram_wb_stb = 1'd0; +reg soc_litedram_wb_ack = 1'd0; +reg soc_litedram_wb_we = 1'd0; +wire [2:0] soc_litedram_wb_cti; +reg soc_write = 1'd0; +reg soc_evict = 1'd0; +reg soc_refill = 1'd0; +reg soc_read = 1'd0; +wire [29:0] soc_address_d; +reg [29:0] soc_address_q = 30'd0; +reg soc_address_ce = 1'd0; +reg soc_address_reset = 1'd0; +reg [1:0] soc_counter = 2'd0; +reg soc_counter_ce = 1'd0; +reg soc_counter_reset = 1'd0; +wire [1:0] soc_counter_offset; +wire soc_counter_done; +wire [127:0] soc_cached_data; +wire [15:0] soc_cached_sel; +wire soc_end_of_burst; +wire soc_need_refill_d; +reg soc_need_refill_q = 1'd1; +reg soc_need_refill_ce = 1'd0; +wire soc_need_refill_reset; +reg [31:0] soc_cached_datas_flipflop0_d = 32'd0; +reg [31:0] soc_cached_datas_flipflop0_q = 32'd0; +reg soc_cached_datas_ce0 = 1'd0; +reg soc_cached_datas_reset0 = 1'd0; +reg [31:0] soc_cached_datas_flipflop1_d = 32'd0; +reg [31:0] soc_cached_datas_flipflop1_q = 32'd0; +reg soc_cached_datas_ce1 = 1'd0; +reg soc_cached_datas_reset1 = 1'd0; +reg [31:0] soc_cached_datas_flipflop2_d = 32'd0; +reg [31:0] soc_cached_datas_flipflop2_q = 32'd0; +reg soc_cached_datas_ce2 = 1'd0; +reg soc_cached_datas_reset2 = 1'd0; +reg [31:0] soc_cached_datas_flipflop3_d = 32'd0; +reg [31:0] soc_cached_datas_flipflop3_q = 32'd0; +reg soc_cached_datas_ce3 = 1'd0; +reg soc_cached_datas_reset3 = 1'd0; +wire [3:0] soc_cached_sels_flipflop0_d; +reg [3:0] soc_cached_sels_flipflop0_q = 4'd0; +reg soc_cached_sels_ce0 = 1'd0; +wire soc_cached_sels_reset0; +wire [3:0] soc_cached_sels_flipflop1_d; +reg [3:0] soc_cached_sels_flipflop1_q = 4'd0; +reg soc_cached_sels_ce1 = 1'd0; +wire soc_cached_sels_reset1; +wire [3:0] soc_cached_sels_flipflop2_d; +reg [3:0] soc_cached_sels_flipflop2_q = 4'd0; +reg soc_cached_sels_ce2 = 1'd0; +wire soc_cached_sels_reset2; +wire [3:0] soc_cached_sels_flipflop3_d; +reg [3:0] soc_cached_sels_flipflop3_q = 4'd0; +reg soc_cached_sels_ce3 = 1'd0; +wire soc_cached_sels_reset3; +reg soc_write_sel0 = 1'd0; +reg soc_write_sel1 = 1'd0; +reg soc_write_sel2 = 1'd0; +reg soc_write_sel3 = 1'd0; +wire soc_wdata_converter_sink_valid; +wire soc_wdata_converter_sink_ready; +reg soc_wdata_converter_sink_first = 1'd0; +reg soc_wdata_converter_sink_last = 1'd0; +wire [127:0] soc_wdata_converter_sink_payload_data; +wire [15:0] soc_wdata_converter_sink_payload_we; +wire soc_wdata_converter_source_valid; +wire soc_wdata_converter_source_ready; +wire soc_wdata_converter_source_first; +wire soc_wdata_converter_source_last; +wire [127:0] soc_wdata_converter_source_payload_data; +wire [15:0] soc_wdata_converter_source_payload_we; +wire soc_wdata_converter_converter_sink_valid; +wire soc_wdata_converter_converter_sink_ready; +wire soc_wdata_converter_converter_sink_first; +wire soc_wdata_converter_converter_sink_last; +wire [143:0] soc_wdata_converter_converter_sink_payload_data; +wire soc_wdata_converter_converter_source_valid; +wire soc_wdata_converter_converter_source_ready; +wire soc_wdata_converter_converter_source_first; +wire soc_wdata_converter_converter_source_last; +wire [143:0] soc_wdata_converter_converter_source_payload_data; +wire soc_wdata_converter_converter_source_payload_valid_token_count; +wire soc_wdata_converter_source_source_valid; +wire soc_wdata_converter_source_source_ready; +wire soc_wdata_converter_source_source_first; +wire soc_wdata_converter_source_source_last; +wire [143:0] soc_wdata_converter_source_source_payload_data; +wire soc_rdata_converter_sink_valid; +wire soc_rdata_converter_sink_ready; +wire soc_rdata_converter_sink_first; +wire soc_rdata_converter_sink_last; +wire [127:0] soc_rdata_converter_sink_payload_data; +wire soc_rdata_converter_source_valid; +wire soc_rdata_converter_source_ready; +wire soc_rdata_converter_source_first; +wire soc_rdata_converter_source_last; +wire [127:0] soc_rdata_converter_source_payload_data; +wire soc_rdata_converter_converter_sink_valid; +wire soc_rdata_converter_converter_sink_ready; +wire soc_rdata_converter_converter_sink_first; +wire soc_rdata_converter_converter_sink_last; +wire [127:0] soc_rdata_converter_converter_sink_payload_data; +wire soc_rdata_converter_converter_source_valid; +wire soc_rdata_converter_converter_source_ready; +wire soc_rdata_converter_converter_source_first; +wire soc_rdata_converter_converter_source_last; +wire [127:0] soc_rdata_converter_converter_source_payload_data; +wire soc_rdata_converter_converter_source_payload_valid_token_count; +wire soc_rdata_converter_source_source_valid; +wire soc_rdata_converter_source_source_ready; +wire soc_rdata_converter_source_source_first; +wire soc_rdata_converter_source_source_last; +wire [127:0] soc_rdata_converter_source_source_payload_data; +reg soc_count = 1'd0; +reg soc_init_done_storage = 1'd0; +reg soc_init_done_re = 1'd0; +reg soc_init_error_storage = 1'd0; +reg soc_init_error_re = 1'd0; +wire soc_cmd_valid; +wire soc_cmd_ready; +wire soc_cmd_payload_we; +wire [23:0] soc_cmd_payload_addr; +wire soc_wdata_valid; +wire soc_wdata_ready; +wire [127:0] soc_wdata_payload_data; +wire [15:0] soc_wdata_payload_we; +wire soc_rdata_valid; +wire soc_rdata_ready; +wire [127:0] soc_rdata_payload_data; +reg vns_wb2csr_state = 1'd0; +reg vns_wb2csr_next_state = 1'd0; +wire vns_pll_fb0; +wire vns_pll_fb1; +reg [1:0] vns_refresher_state = 2'd0; +reg [1:0] vns_refresher_next_state = 2'd0; +reg [3:0] vns_bankmachine0_state = 4'd0; +reg [3:0] vns_bankmachine0_next_state = 4'd0; +reg [3:0] vns_bankmachine1_state = 4'd0; +reg [3:0] vns_bankmachine1_next_state = 4'd0; +reg [3:0] vns_bankmachine2_state = 4'd0; +reg [3:0] vns_bankmachine2_next_state = 4'd0; +reg [3:0] vns_bankmachine3_state = 4'd0; +reg [3:0] vns_bankmachine3_next_state = 4'd0; +reg [3:0] vns_bankmachine4_state = 4'd0; +reg [3:0] vns_bankmachine4_next_state = 4'd0; +reg [3:0] vns_bankmachine5_state = 4'd0; +reg [3:0] vns_bankmachine5_next_state = 4'd0; +reg [3:0] vns_bankmachine6_state = 4'd0; +reg [3:0] vns_bankmachine6_next_state = 4'd0; +reg [3:0] vns_bankmachine7_state = 4'd0; +reg [3:0] vns_bankmachine7_next_state = 4'd0; +reg [3:0] vns_multiplexer_state = 4'd0; +reg [3:0] vns_multiplexer_next_state = 4'd0; +wire [1:0] vns_roundrobin0_request; +reg vns_roundrobin0_grant = 1'd0; +wire vns_roundrobin0_ce; +wire [1:0] vns_roundrobin1_request; +reg vns_roundrobin1_grant = 1'd0; +wire vns_roundrobin1_ce; +wire [1:0] vns_roundrobin2_request; +reg vns_roundrobin2_grant = 1'd0; +wire vns_roundrobin2_ce; +wire [1:0] vns_roundrobin3_request; +reg vns_roundrobin3_grant = 1'd0; +wire vns_roundrobin3_ce; +wire [1:0] vns_roundrobin4_request; +reg vns_roundrobin4_grant = 1'd0; +wire vns_roundrobin4_ce; +wire [1:0] vns_roundrobin5_request; +reg vns_roundrobin5_grant = 1'd0; +wire vns_roundrobin5_ce; +wire [1:0] vns_roundrobin6_request; +reg vns_roundrobin6_grant = 1'd0; +wire vns_roundrobin6_ce; +wire [1:0] vns_roundrobin7_request; +reg vns_roundrobin7_grant = 1'd0; +wire vns_roundrobin7_ce; +reg vns_locked0 = 1'd0; +reg vns_locked1 = 1'd0; +reg vns_locked2 = 1'd0; +reg vns_locked3 = 1'd0; +reg vns_locked4 = 1'd0; +reg vns_locked5 = 1'd0; +reg vns_locked6 = 1'd0; +reg vns_locked7 = 1'd0; +reg vns_locked8 = 1'd0; +reg vns_locked9 = 1'd0; +reg vns_locked10 = 1'd0; +reg vns_locked11 = 1'd0; +reg vns_locked12 = 1'd0; +reg vns_locked13 = 1'd0; +reg vns_locked14 = 1'd0; +reg vns_locked15 = 1'd0; +reg vns_new_master_wdata_ready0 = 1'd0; +reg vns_new_master_wdata_ready1 = 1'd0; +reg vns_new_master_wdata_ready2 = 1'd0; +reg vns_new_master_wdata_ready3 = 1'd0; +reg vns_new_master_wdata_ready4 = 1'd0; +reg vns_new_master_wdata_ready5 = 1'd0; +reg vns_new_master_rdata_valid0 = 1'd0; +reg vns_new_master_rdata_valid1 = 1'd0; +reg vns_new_master_rdata_valid2 = 1'd0; +reg vns_new_master_rdata_valid3 = 1'd0; +reg vns_new_master_rdata_valid4 = 1'd0; +reg vns_new_master_rdata_valid5 = 1'd0; +reg vns_new_master_rdata_valid6 = 1'd0; +reg vns_new_master_rdata_valid7 = 1'd0; +reg vns_new_master_rdata_valid8 = 1'd0; +reg vns_new_master_rdata_valid9 = 1'd0; +reg vns_new_master_rdata_valid10 = 1'd0; +reg vns_new_master_rdata_valid11 = 1'd0; +reg vns_new_master_rdata_valid12 = 1'd0; +reg vns_new_master_rdata_valid13 = 1'd0; +reg vns_new_master_rdata_valid14 = 1'd0; +reg vns_new_master_rdata_valid15 = 1'd0; +reg vns_new_master_rdata_valid16 = 1'd0; +reg vns_new_master_rdata_valid17 = 1'd0; +reg [2:0] vns_converter_state = 3'd0; +reg [2:0] vns_converter_next_state = 3'd0; +reg [1:0] vns_litedramwishbone2native_state = 2'd0; +reg [1:0] vns_litedramwishbone2native_next_state = 2'd0; +reg soc_count_next_value = 1'd0; +reg soc_count_next_value_ce = 1'd0; +wire [29:0] vns_shared_adr; +wire [31:0] vns_shared_dat_w; +reg [31:0] vns_shared_dat_r = 32'd0; +wire [3:0] vns_shared_sel; +wire vns_shared_cyc; +wire vns_shared_stb; +reg vns_shared_ack = 1'd0; +wire vns_shared_we; +wire [2:0] vns_shared_cti; +wire [1:0] vns_shared_bte; +wire vns_shared_err; +wire [1:0] vns_request; +reg vns_grant = 1'd0; +reg [3:0] vns_slave_sel = 4'd0; +reg [3:0] vns_slave_sel_r = 4'd0; +reg vns_error = 1'd0; +wire vns_wait; +wire vns_done; +reg [19:0] vns_count = 20'd1000000; +wire [13:0] vns_interface0_bank_bus_adr; +wire vns_interface0_bank_bus_we; +wire [7:0] vns_interface0_bank_bus_dat_w; +reg [7:0] vns_interface0_bank_bus_dat_r = 8'd0; +wire vns_csrbank0_reset0_re; +wire vns_csrbank0_reset0_r; +wire vns_csrbank0_reset0_we; +wire vns_csrbank0_reset0_w; +wire vns_csrbank0_scratch3_re; +wire [7:0] vns_csrbank0_scratch3_r; +wire vns_csrbank0_scratch3_we; +wire [7:0] vns_csrbank0_scratch3_w; +wire vns_csrbank0_scratch2_re; +wire [7:0] vns_csrbank0_scratch2_r; +wire vns_csrbank0_scratch2_we; +wire [7:0] vns_csrbank0_scratch2_w; +wire vns_csrbank0_scratch1_re; +wire [7:0] vns_csrbank0_scratch1_r; +wire vns_csrbank0_scratch1_we; +wire [7:0] vns_csrbank0_scratch1_w; +wire vns_csrbank0_scratch0_re; +wire [7:0] vns_csrbank0_scratch0_r; +wire vns_csrbank0_scratch0_we; +wire [7:0] vns_csrbank0_scratch0_w; +wire vns_csrbank0_bus_errors3_re; +wire [7:0] vns_csrbank0_bus_errors3_r; +wire vns_csrbank0_bus_errors3_we; +wire [7:0] vns_csrbank0_bus_errors3_w; +wire vns_csrbank0_bus_errors2_re; +wire [7:0] vns_csrbank0_bus_errors2_r; +wire vns_csrbank0_bus_errors2_we; +wire [7:0] vns_csrbank0_bus_errors2_w; +wire vns_csrbank0_bus_errors1_re; +wire [7:0] vns_csrbank0_bus_errors1_r; +wire vns_csrbank0_bus_errors1_we; +wire [7:0] vns_csrbank0_bus_errors1_w; +wire vns_csrbank0_bus_errors0_re; +wire [7:0] vns_csrbank0_bus_errors0_r; +wire vns_csrbank0_bus_errors0_we; +wire [7:0] vns_csrbank0_bus_errors0_w; +wire vns_csrbank0_sel; +wire [13:0] vns_interface1_bank_bus_adr; +wire vns_interface1_bank_bus_we; +wire [7:0] vns_interface1_bank_bus_dat_w; +reg [7:0] vns_interface1_bank_bus_dat_r = 8'd0; +wire vns_csrbank1_init_done0_re; +wire vns_csrbank1_init_done0_r; +wire vns_csrbank1_init_done0_we; +wire vns_csrbank1_init_done0_w; +wire vns_csrbank1_init_error0_re; +wire vns_csrbank1_init_error0_r; +wire vns_csrbank1_init_error0_we; +wire vns_csrbank1_init_error0_w; +wire vns_csrbank1_sel; +wire [13:0] vns_interface2_bank_bus_adr; +wire vns_interface2_bank_bus_we; +wire [7:0] vns_interface2_bank_bus_dat_w; +reg [7:0] vns_interface2_bank_bus_dat_r = 8'd0; +wire vns_csrbank2_half_sys8x_taps0_re; +wire [4:0] vns_csrbank2_half_sys8x_taps0_r; +wire vns_csrbank2_half_sys8x_taps0_we; +wire [4:0] vns_csrbank2_half_sys8x_taps0_w; +wire vns_csrbank2_wlevel_en0_re; +wire vns_csrbank2_wlevel_en0_r; +wire vns_csrbank2_wlevel_en0_we; +wire vns_csrbank2_wlevel_en0_w; +wire vns_csrbank2_dly_sel0_re; +wire [1:0] vns_csrbank2_dly_sel0_r; +wire vns_csrbank2_dly_sel0_we; +wire [1:0] vns_csrbank2_dly_sel0_w; +wire vns_csrbank2_sel; +wire [13:0] vns_interface3_bank_bus_adr; +wire vns_interface3_bank_bus_we; +wire [7:0] vns_interface3_bank_bus_dat_w; +reg [7:0] vns_interface3_bank_bus_dat_r = 8'd0; +wire vns_csrbank3_dfii_control0_re; +wire [3:0] vns_csrbank3_dfii_control0_r; +wire vns_csrbank3_dfii_control0_we; +wire [3:0] vns_csrbank3_dfii_control0_w; +wire vns_csrbank3_dfii_pi0_command0_re; +wire [5:0] vns_csrbank3_dfii_pi0_command0_r; +wire vns_csrbank3_dfii_pi0_command0_we; +wire [5:0] vns_csrbank3_dfii_pi0_command0_w; +wire vns_csrbank3_dfii_pi0_address1_re; +wire [5:0] vns_csrbank3_dfii_pi0_address1_r; +wire vns_csrbank3_dfii_pi0_address1_we; +wire [5:0] vns_csrbank3_dfii_pi0_address1_w; +wire vns_csrbank3_dfii_pi0_address0_re; +wire [7:0] vns_csrbank3_dfii_pi0_address0_r; +wire vns_csrbank3_dfii_pi0_address0_we; +wire [7:0] vns_csrbank3_dfii_pi0_address0_w; +wire vns_csrbank3_dfii_pi0_baddress0_re; +wire [2:0] vns_csrbank3_dfii_pi0_baddress0_r; +wire vns_csrbank3_dfii_pi0_baddress0_we; +wire [2:0] vns_csrbank3_dfii_pi0_baddress0_w; +wire vns_csrbank3_dfii_pi0_wrdata3_re; +wire [7:0] vns_csrbank3_dfii_pi0_wrdata3_r; +wire vns_csrbank3_dfii_pi0_wrdata3_we; +wire [7:0] vns_csrbank3_dfii_pi0_wrdata3_w; +wire vns_csrbank3_dfii_pi0_wrdata2_re; +wire [7:0] vns_csrbank3_dfii_pi0_wrdata2_r; +wire vns_csrbank3_dfii_pi0_wrdata2_we; +wire [7:0] vns_csrbank3_dfii_pi0_wrdata2_w; +wire vns_csrbank3_dfii_pi0_wrdata1_re; +wire [7:0] vns_csrbank3_dfii_pi0_wrdata1_r; +wire vns_csrbank3_dfii_pi0_wrdata1_we; +wire [7:0] vns_csrbank3_dfii_pi0_wrdata1_w; +wire vns_csrbank3_dfii_pi0_wrdata0_re; +wire [7:0] vns_csrbank3_dfii_pi0_wrdata0_r; +wire vns_csrbank3_dfii_pi0_wrdata0_we; +wire [7:0] vns_csrbank3_dfii_pi0_wrdata0_w; +wire vns_csrbank3_dfii_pi0_rddata3_re; +wire [7:0] vns_csrbank3_dfii_pi0_rddata3_r; +wire vns_csrbank3_dfii_pi0_rddata3_we; +wire [7:0] vns_csrbank3_dfii_pi0_rddata3_w; +wire vns_csrbank3_dfii_pi0_rddata2_re; +wire [7:0] vns_csrbank3_dfii_pi0_rddata2_r; +wire vns_csrbank3_dfii_pi0_rddata2_we; +wire [7:0] vns_csrbank3_dfii_pi0_rddata2_w; +wire vns_csrbank3_dfii_pi0_rddata1_re; +wire [7:0] vns_csrbank3_dfii_pi0_rddata1_r; +wire vns_csrbank3_dfii_pi0_rddata1_we; +wire [7:0] vns_csrbank3_dfii_pi0_rddata1_w; +wire vns_csrbank3_dfii_pi0_rddata0_re; +wire [7:0] vns_csrbank3_dfii_pi0_rddata0_r; +wire vns_csrbank3_dfii_pi0_rddata0_we; +wire [7:0] vns_csrbank3_dfii_pi0_rddata0_w; +wire vns_csrbank3_dfii_pi1_command0_re; +wire [5:0] vns_csrbank3_dfii_pi1_command0_r; +wire vns_csrbank3_dfii_pi1_command0_we; +wire [5:0] vns_csrbank3_dfii_pi1_command0_w; +wire vns_csrbank3_dfii_pi1_address1_re; +wire [5:0] vns_csrbank3_dfii_pi1_address1_r; +wire vns_csrbank3_dfii_pi1_address1_we; +wire [5:0] vns_csrbank3_dfii_pi1_address1_w; +wire vns_csrbank3_dfii_pi1_address0_re; +wire [7:0] vns_csrbank3_dfii_pi1_address0_r; +wire vns_csrbank3_dfii_pi1_address0_we; +wire [7:0] vns_csrbank3_dfii_pi1_address0_w; +wire vns_csrbank3_dfii_pi1_baddress0_re; +wire [2:0] vns_csrbank3_dfii_pi1_baddress0_r; +wire vns_csrbank3_dfii_pi1_baddress0_we; +wire [2:0] vns_csrbank3_dfii_pi1_baddress0_w; +wire vns_csrbank3_dfii_pi1_wrdata3_re; +wire [7:0] vns_csrbank3_dfii_pi1_wrdata3_r; +wire vns_csrbank3_dfii_pi1_wrdata3_we; +wire [7:0] vns_csrbank3_dfii_pi1_wrdata3_w; +wire vns_csrbank3_dfii_pi1_wrdata2_re; +wire [7:0] vns_csrbank3_dfii_pi1_wrdata2_r; +wire vns_csrbank3_dfii_pi1_wrdata2_we; +wire [7:0] vns_csrbank3_dfii_pi1_wrdata2_w; +wire vns_csrbank3_dfii_pi1_wrdata1_re; +wire [7:0] vns_csrbank3_dfii_pi1_wrdata1_r; +wire vns_csrbank3_dfii_pi1_wrdata1_we; +wire [7:0] vns_csrbank3_dfii_pi1_wrdata1_w; +wire vns_csrbank3_dfii_pi1_wrdata0_re; +wire [7:0] vns_csrbank3_dfii_pi1_wrdata0_r; +wire vns_csrbank3_dfii_pi1_wrdata0_we; +wire [7:0] vns_csrbank3_dfii_pi1_wrdata0_w; +wire vns_csrbank3_dfii_pi1_rddata3_re; +wire [7:0] vns_csrbank3_dfii_pi1_rddata3_r; +wire vns_csrbank3_dfii_pi1_rddata3_we; +wire [7:0] vns_csrbank3_dfii_pi1_rddata3_w; +wire vns_csrbank3_dfii_pi1_rddata2_re; +wire [7:0] vns_csrbank3_dfii_pi1_rddata2_r; +wire vns_csrbank3_dfii_pi1_rddata2_we; +wire [7:0] vns_csrbank3_dfii_pi1_rddata2_w; +wire vns_csrbank3_dfii_pi1_rddata1_re; +wire [7:0] vns_csrbank3_dfii_pi1_rddata1_r; +wire vns_csrbank3_dfii_pi1_rddata1_we; +wire [7:0] vns_csrbank3_dfii_pi1_rddata1_w; +wire vns_csrbank3_dfii_pi1_rddata0_re; +wire [7:0] vns_csrbank3_dfii_pi1_rddata0_r; +wire vns_csrbank3_dfii_pi1_rddata0_we; +wire [7:0] vns_csrbank3_dfii_pi1_rddata0_w; +wire vns_csrbank3_dfii_pi2_command0_re; +wire [5:0] vns_csrbank3_dfii_pi2_command0_r; +wire vns_csrbank3_dfii_pi2_command0_we; +wire [5:0] vns_csrbank3_dfii_pi2_command0_w; +wire vns_csrbank3_dfii_pi2_address1_re; +wire [5:0] vns_csrbank3_dfii_pi2_address1_r; +wire vns_csrbank3_dfii_pi2_address1_we; +wire [5:0] vns_csrbank3_dfii_pi2_address1_w; +wire vns_csrbank3_dfii_pi2_address0_re; +wire [7:0] vns_csrbank3_dfii_pi2_address0_r; +wire vns_csrbank3_dfii_pi2_address0_we; +wire [7:0] vns_csrbank3_dfii_pi2_address0_w; +wire vns_csrbank3_dfii_pi2_baddress0_re; +wire [2:0] vns_csrbank3_dfii_pi2_baddress0_r; +wire vns_csrbank3_dfii_pi2_baddress0_we; +wire [2:0] vns_csrbank3_dfii_pi2_baddress0_w; +wire vns_csrbank3_dfii_pi2_wrdata3_re; +wire [7:0] vns_csrbank3_dfii_pi2_wrdata3_r; +wire vns_csrbank3_dfii_pi2_wrdata3_we; +wire [7:0] vns_csrbank3_dfii_pi2_wrdata3_w; +wire vns_csrbank3_dfii_pi2_wrdata2_re; +wire [7:0] vns_csrbank3_dfii_pi2_wrdata2_r; +wire vns_csrbank3_dfii_pi2_wrdata2_we; +wire [7:0] vns_csrbank3_dfii_pi2_wrdata2_w; +wire vns_csrbank3_dfii_pi2_wrdata1_re; +wire [7:0] vns_csrbank3_dfii_pi2_wrdata1_r; +wire vns_csrbank3_dfii_pi2_wrdata1_we; +wire [7:0] vns_csrbank3_dfii_pi2_wrdata1_w; +wire vns_csrbank3_dfii_pi2_wrdata0_re; +wire [7:0] vns_csrbank3_dfii_pi2_wrdata0_r; +wire vns_csrbank3_dfii_pi2_wrdata0_we; +wire [7:0] vns_csrbank3_dfii_pi2_wrdata0_w; +wire vns_csrbank3_dfii_pi2_rddata3_re; +wire [7:0] vns_csrbank3_dfii_pi2_rddata3_r; +wire vns_csrbank3_dfii_pi2_rddata3_we; +wire [7:0] vns_csrbank3_dfii_pi2_rddata3_w; +wire vns_csrbank3_dfii_pi2_rddata2_re; +wire [7:0] vns_csrbank3_dfii_pi2_rddata2_r; +wire vns_csrbank3_dfii_pi2_rddata2_we; +wire [7:0] vns_csrbank3_dfii_pi2_rddata2_w; +wire vns_csrbank3_dfii_pi2_rddata1_re; +wire [7:0] vns_csrbank3_dfii_pi2_rddata1_r; +wire vns_csrbank3_dfii_pi2_rddata1_we; +wire [7:0] vns_csrbank3_dfii_pi2_rddata1_w; +wire vns_csrbank3_dfii_pi2_rddata0_re; +wire [7:0] vns_csrbank3_dfii_pi2_rddata0_r; +wire vns_csrbank3_dfii_pi2_rddata0_we; +wire [7:0] vns_csrbank3_dfii_pi2_rddata0_w; +wire vns_csrbank3_dfii_pi3_command0_re; +wire [5:0] vns_csrbank3_dfii_pi3_command0_r; +wire vns_csrbank3_dfii_pi3_command0_we; +wire [5:0] vns_csrbank3_dfii_pi3_command0_w; +wire vns_csrbank3_dfii_pi3_address1_re; +wire [5:0] vns_csrbank3_dfii_pi3_address1_r; +wire vns_csrbank3_dfii_pi3_address1_we; +wire [5:0] vns_csrbank3_dfii_pi3_address1_w; +wire vns_csrbank3_dfii_pi3_address0_re; +wire [7:0] vns_csrbank3_dfii_pi3_address0_r; +wire vns_csrbank3_dfii_pi3_address0_we; +wire [7:0] vns_csrbank3_dfii_pi3_address0_w; +wire vns_csrbank3_dfii_pi3_baddress0_re; +wire [2:0] vns_csrbank3_dfii_pi3_baddress0_r; +wire vns_csrbank3_dfii_pi3_baddress0_we; +wire [2:0] vns_csrbank3_dfii_pi3_baddress0_w; +wire vns_csrbank3_dfii_pi3_wrdata3_re; +wire [7:0] vns_csrbank3_dfii_pi3_wrdata3_r; +wire vns_csrbank3_dfii_pi3_wrdata3_we; +wire [7:0] vns_csrbank3_dfii_pi3_wrdata3_w; +wire vns_csrbank3_dfii_pi3_wrdata2_re; +wire [7:0] vns_csrbank3_dfii_pi3_wrdata2_r; +wire vns_csrbank3_dfii_pi3_wrdata2_we; +wire [7:0] vns_csrbank3_dfii_pi3_wrdata2_w; +wire vns_csrbank3_dfii_pi3_wrdata1_re; +wire [7:0] vns_csrbank3_dfii_pi3_wrdata1_r; +wire vns_csrbank3_dfii_pi3_wrdata1_we; +wire [7:0] vns_csrbank3_dfii_pi3_wrdata1_w; +wire vns_csrbank3_dfii_pi3_wrdata0_re; +wire [7:0] vns_csrbank3_dfii_pi3_wrdata0_r; +wire vns_csrbank3_dfii_pi3_wrdata0_we; +wire [7:0] vns_csrbank3_dfii_pi3_wrdata0_w; +wire vns_csrbank3_dfii_pi3_rddata3_re; +wire [7:0] vns_csrbank3_dfii_pi3_rddata3_r; +wire vns_csrbank3_dfii_pi3_rddata3_we; +wire [7:0] vns_csrbank3_dfii_pi3_rddata3_w; +wire vns_csrbank3_dfii_pi3_rddata2_re; +wire [7:0] vns_csrbank3_dfii_pi3_rddata2_r; +wire vns_csrbank3_dfii_pi3_rddata2_we; +wire [7:0] vns_csrbank3_dfii_pi3_rddata2_w; +wire vns_csrbank3_dfii_pi3_rddata1_re; +wire [7:0] vns_csrbank3_dfii_pi3_rddata1_r; +wire vns_csrbank3_dfii_pi3_rddata1_we; +wire [7:0] vns_csrbank3_dfii_pi3_rddata1_w; +wire vns_csrbank3_dfii_pi3_rddata0_re; +wire [7:0] vns_csrbank3_dfii_pi3_rddata0_r; +wire vns_csrbank3_dfii_pi3_rddata0_we; +wire [7:0] vns_csrbank3_dfii_pi3_rddata0_w; +wire vns_csrbank3_sel; +wire [13:0] vns_interface4_bank_bus_adr; +wire vns_interface4_bank_bus_we; +wire [7:0] vns_interface4_bank_bus_dat_w; +reg [7:0] vns_interface4_bank_bus_dat_r = 8'd0; +wire vns_csrbank4_load3_re; +wire [7:0] vns_csrbank4_load3_r; +wire vns_csrbank4_load3_we; +wire [7:0] vns_csrbank4_load3_w; +wire vns_csrbank4_load2_re; +wire [7:0] vns_csrbank4_load2_r; +wire vns_csrbank4_load2_we; +wire [7:0] vns_csrbank4_load2_w; +wire vns_csrbank4_load1_re; +wire [7:0] vns_csrbank4_load1_r; +wire vns_csrbank4_load1_we; +wire [7:0] vns_csrbank4_load1_w; +wire vns_csrbank4_load0_re; +wire [7:0] vns_csrbank4_load0_r; +wire vns_csrbank4_load0_we; +wire [7:0] vns_csrbank4_load0_w; +wire vns_csrbank4_reload3_re; +wire [7:0] vns_csrbank4_reload3_r; +wire vns_csrbank4_reload3_we; +wire [7:0] vns_csrbank4_reload3_w; +wire vns_csrbank4_reload2_re; +wire [7:0] vns_csrbank4_reload2_r; +wire vns_csrbank4_reload2_we; +wire [7:0] vns_csrbank4_reload2_w; +wire vns_csrbank4_reload1_re; +wire [7:0] vns_csrbank4_reload1_r; +wire vns_csrbank4_reload1_we; +wire [7:0] vns_csrbank4_reload1_w; +wire vns_csrbank4_reload0_re; +wire [7:0] vns_csrbank4_reload0_r; +wire vns_csrbank4_reload0_we; +wire [7:0] vns_csrbank4_reload0_w; +wire vns_csrbank4_en0_re; +wire vns_csrbank4_en0_r; +wire vns_csrbank4_en0_we; +wire vns_csrbank4_en0_w; +wire vns_csrbank4_update_value0_re; +wire vns_csrbank4_update_value0_r; +wire vns_csrbank4_update_value0_we; +wire vns_csrbank4_update_value0_w; +wire vns_csrbank4_value3_re; +wire [7:0] vns_csrbank4_value3_r; +wire vns_csrbank4_value3_we; +wire [7:0] vns_csrbank4_value3_w; +wire vns_csrbank4_value2_re; +wire [7:0] vns_csrbank4_value2_r; +wire vns_csrbank4_value2_we; +wire [7:0] vns_csrbank4_value2_w; +wire vns_csrbank4_value1_re; +wire [7:0] vns_csrbank4_value1_r; +wire vns_csrbank4_value1_we; +wire [7:0] vns_csrbank4_value1_w; +wire vns_csrbank4_value0_re; +wire [7:0] vns_csrbank4_value0_r; +wire vns_csrbank4_value0_we; +wire [7:0] vns_csrbank4_value0_w; +wire vns_csrbank4_ev_enable0_re; +wire vns_csrbank4_ev_enable0_r; +wire vns_csrbank4_ev_enable0_we; +wire vns_csrbank4_ev_enable0_w; +wire vns_csrbank4_sel; +wire [13:0] vns_interface5_bank_bus_adr; +wire vns_interface5_bank_bus_we; +wire [7:0] vns_interface5_bank_bus_dat_w; +reg [7:0] vns_interface5_bank_bus_dat_r = 8'd0; +wire vns_csrbank5_txfull_re; +wire vns_csrbank5_txfull_r; +wire vns_csrbank5_txfull_we; +wire vns_csrbank5_txfull_w; +wire vns_csrbank5_rxempty_re; +wire vns_csrbank5_rxempty_r; +wire vns_csrbank5_rxempty_we; +wire vns_csrbank5_rxempty_w; +wire vns_csrbank5_ev_enable0_re; +wire [1:0] vns_csrbank5_ev_enable0_r; +wire vns_csrbank5_ev_enable0_we; +wire [1:0] vns_csrbank5_ev_enable0_w; +wire vns_csrbank5_sel; +wire [13:0] vns_interface6_bank_bus_adr; +wire vns_interface6_bank_bus_we; +wire [7:0] vns_interface6_bank_bus_dat_w; +reg [7:0] vns_interface6_bank_bus_dat_r = 8'd0; +wire vns_csrbank6_tuning_word3_re; +wire [7:0] vns_csrbank6_tuning_word3_r; +wire vns_csrbank6_tuning_word3_we; +wire [7:0] vns_csrbank6_tuning_word3_w; +wire vns_csrbank6_tuning_word2_re; +wire [7:0] vns_csrbank6_tuning_word2_r; +wire vns_csrbank6_tuning_word2_we; +wire [7:0] vns_csrbank6_tuning_word2_w; +wire vns_csrbank6_tuning_word1_re; +wire [7:0] vns_csrbank6_tuning_word1_r; +wire vns_csrbank6_tuning_word1_we; +wire [7:0] vns_csrbank6_tuning_word1_w; +wire vns_csrbank6_tuning_word0_re; +wire [7:0] vns_csrbank6_tuning_word0_r; +wire vns_csrbank6_tuning_word0_we; +wire [7:0] vns_csrbank6_tuning_word0_w; +wire vns_csrbank6_sel; +wire [13:0] vns_adr; +wire vns_we; +wire [7:0] vns_dat_w; +wire [7:0] vns_dat_r; +reg vns_rhs_array_muxed0 = 1'd0; +reg [13:0] vns_rhs_array_muxed1 = 14'd0; +reg [2:0] vns_rhs_array_muxed2 = 3'd0; +reg vns_rhs_array_muxed3 = 1'd0; +reg vns_rhs_array_muxed4 = 1'd0; +reg vns_rhs_array_muxed5 = 1'd0; +reg vns_t_array_muxed0 = 1'd0; +reg vns_t_array_muxed1 = 1'd0; +reg vns_t_array_muxed2 = 1'd0; +reg vns_rhs_array_muxed6 = 1'd0; +reg [13:0] vns_rhs_array_muxed7 = 14'd0; +reg [2:0] vns_rhs_array_muxed8 = 3'd0; +reg vns_rhs_array_muxed9 = 1'd0; +reg vns_rhs_array_muxed10 = 1'd0; +reg vns_rhs_array_muxed11 = 1'd0; +reg vns_t_array_muxed3 = 1'd0; +reg vns_t_array_muxed4 = 1'd0; +reg vns_t_array_muxed5 = 1'd0; +reg [20:0] vns_rhs_array_muxed12 = 21'd0; +reg vns_rhs_array_muxed13 = 1'd0; +reg vns_rhs_array_muxed14 = 1'd0; +reg [20:0] vns_rhs_array_muxed15 = 21'd0; +reg vns_rhs_array_muxed16 = 1'd0; +reg vns_rhs_array_muxed17 = 1'd0; +reg [20:0] vns_rhs_array_muxed18 = 21'd0; +reg vns_rhs_array_muxed19 = 1'd0; +reg vns_rhs_array_muxed20 = 1'd0; +reg [20:0] vns_rhs_array_muxed21 = 21'd0; +reg vns_rhs_array_muxed22 = 1'd0; +reg vns_rhs_array_muxed23 = 1'd0; +reg [20:0] vns_rhs_array_muxed24 = 21'd0; +reg vns_rhs_array_muxed25 = 1'd0; +reg vns_rhs_array_muxed26 = 1'd0; +reg [20:0] vns_rhs_array_muxed27 = 21'd0; +reg vns_rhs_array_muxed28 = 1'd0; +reg vns_rhs_array_muxed29 = 1'd0; +reg [20:0] vns_rhs_array_muxed30 = 21'd0; +reg vns_rhs_array_muxed31 = 1'd0; +reg vns_rhs_array_muxed32 = 1'd0; +reg [20:0] vns_rhs_array_muxed33 = 21'd0; +reg vns_rhs_array_muxed34 = 1'd0; +reg vns_rhs_array_muxed35 = 1'd0; +reg [29:0] vns_rhs_array_muxed36 = 30'd0; +reg [31:0] vns_rhs_array_muxed37 = 32'd0; +reg [3:0] vns_rhs_array_muxed38 = 4'd0; +reg vns_rhs_array_muxed39 = 1'd0; +reg vns_rhs_array_muxed40 = 1'd0; +reg vns_rhs_array_muxed41 = 1'd0; +reg [2:0] vns_rhs_array_muxed42 = 3'd0; +reg [1:0] vns_rhs_array_muxed43 = 2'd0; +reg [2:0] vns_array_muxed0 = 3'd0; +reg [13:0] vns_array_muxed1 = 14'd0; +reg vns_array_muxed2 = 1'd0; +reg vns_array_muxed3 = 1'd0; +reg vns_array_muxed4 = 1'd0; +reg vns_array_muxed5 = 1'd0; +reg vns_array_muxed6 = 1'd0; +reg [2:0] vns_array_muxed7 = 3'd0; +reg [13:0] vns_array_muxed8 = 14'd0; +reg vns_array_muxed9 = 1'd0; +reg vns_array_muxed10 = 1'd0; +reg vns_array_muxed11 = 1'd0; +reg vns_array_muxed12 = 1'd0; +reg vns_array_muxed13 = 1'd0; +reg [2:0] vns_array_muxed14 = 3'd0; +reg [13:0] vns_array_muxed15 = 14'd0; +reg vns_array_muxed16 = 1'd0; +reg vns_array_muxed17 = 1'd0; +reg vns_array_muxed18 = 1'd0; +reg vns_array_muxed19 = 1'd0; +reg vns_array_muxed20 = 1'd0; +reg [2:0] vns_array_muxed21 = 3'd0; +reg [13:0] vns_array_muxed22 = 14'd0; +reg vns_array_muxed23 = 1'd0; +reg vns_array_muxed24 = 1'd0; +reg vns_array_muxed25 = 1'd0; +reg vns_array_muxed26 = 1'd0; +reg vns_array_muxed27 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg vns_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg vns_regs1 = 1'd0; +wire vns_xilinxasyncresetsynchronizerimpl0; +wire vns_xilinxasyncresetsynchronizerimpl0_rst_meta; +wire vns_xilinxasyncresetsynchronizerimpl1; +wire vns_xilinxasyncresetsynchronizerimpl1_rst_meta; +wire vns_xilinxasyncresetsynchronizerimpl1_expr; +wire vns_xilinxasyncresetsynchronizerimpl2; +wire vns_xilinxasyncresetsynchronizerimpl2_rst_meta; +wire vns_xilinxasyncresetsynchronizerimpl2_expr; +wire vns_xilinxasyncresetsynchronizerimpl3; +wire vns_xilinxasyncresetsynchronizerimpl3_rst_meta; + +// synthesis translate_off +reg dummy_s; +initial dummy_s <= 1'd0; +// synthesis translate_on +assign soc_litedramcore_cpu_reset = soc_litedramcore_soccontroller_reset; +assign init_done = soc_init_done_storage; +assign init_error = soc_init_error_storage; +assign user_clk = sys_clk; +assign user_rst = sys_rst; +assign soc_cmd_valid = user_port_native_0_cmd_valid; +assign user_port_native_0_cmd_ready = soc_cmd_ready; +assign soc_cmd_payload_we = user_port_native_0_cmd_we; +assign soc_cmd_payload_addr = user_port_native_0_cmd_addr; +assign soc_wdata_valid = user_port_native_0_wdata_valid; +assign user_port_native_0_wdata_ready = soc_wdata_ready; +assign soc_wdata_payload_we = user_port_native_0_wdata_we; +assign soc_wdata_payload_data = user_port_native_0_wdata_data; +assign user_port_native_0_rdata_valid = soc_rdata_valid; +assign soc_rdata_ready = user_port_native_0_rdata_ready; +assign user_port_native_0_rdata_data = soc_rdata_payload_data; +assign soc_litedramcore_soccontroller_bus_error = vns_error; + +// synthesis translate_off +reg dummy_d; +// synthesis translate_on +always @(*) begin + soc_litedramcore_cpu_interrupt <= 32'd0; + soc_litedramcore_cpu_interrupt[1] <= soc_litedramcore_timer_irq; + soc_litedramcore_cpu_interrupt[0] <= soc_litedramcore_uart_irq; +// synthesis translate_off + dummy_d = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_soccontroller_reset = soc_litedramcore_soccontroller_reset_re; +assign soc_litedramcore_soccontroller_bus_errors_status = soc_litedramcore_soccontroller_bus_errors; +assign soc_litedramcore_litedramcore_adr = soc_litedramcore_litedramcore_ram_bus_adr[12:0]; +assign soc_litedramcore_litedramcore_ram_bus_dat_r = soc_litedramcore_litedramcore_dat_r; + +// synthesis translate_off +reg dummy_d_1; +// synthesis translate_on +always @(*) begin + soc_litedramcore_ram_we <= 4'd0; + soc_litedramcore_ram_we[0] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[0]); + soc_litedramcore_ram_we[1] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[1]); + soc_litedramcore_ram_we[2] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[2]); + soc_litedramcore_ram_we[3] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[3]); +// synthesis translate_off + dummy_d_1 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_ram_adr = soc_litedramcore_ram_bus_ram_bus_adr[9:0]; +assign soc_litedramcore_ram_bus_ram_bus_dat_r = soc_litedramcore_ram_dat_r; +assign soc_litedramcore_ram_dat_w = soc_litedramcore_ram_bus_ram_bus_dat_w; +assign soc_litedramcore_uart_uart_sink_valid = soc_litedramcore_source_valid; +assign soc_litedramcore_source_ready = soc_litedramcore_uart_uart_sink_ready; +assign soc_litedramcore_uart_uart_sink_first = soc_litedramcore_source_first; +assign soc_litedramcore_uart_uart_sink_last = soc_litedramcore_source_last; +assign soc_litedramcore_uart_uart_sink_payload_data = soc_litedramcore_source_payload_data; +assign soc_litedramcore_sink_valid = soc_litedramcore_uart_uart_source_valid; +assign soc_litedramcore_uart_uart_source_ready = soc_litedramcore_sink_ready; +assign soc_litedramcore_sink_first = soc_litedramcore_uart_uart_source_first; +assign soc_litedramcore_sink_last = soc_litedramcore_uart_uart_source_last; +assign soc_litedramcore_sink_payload_data = soc_litedramcore_uart_uart_source_payload_data; +assign soc_litedramcore_uart_tx_fifo_sink_valid = soc_litedramcore_uart_rxtx_re; +assign soc_litedramcore_uart_tx_fifo_sink_payload_data = soc_litedramcore_uart_rxtx_r; +assign soc_litedramcore_uart_txfull_status = (~soc_litedramcore_uart_tx_fifo_sink_ready); +assign soc_litedramcore_uart_uart_source_valid = soc_litedramcore_uart_tx_fifo_source_valid; +assign soc_litedramcore_uart_tx_fifo_source_ready = soc_litedramcore_uart_uart_source_ready; +assign soc_litedramcore_uart_uart_source_first = soc_litedramcore_uart_tx_fifo_source_first; +assign soc_litedramcore_uart_uart_source_last = soc_litedramcore_uart_tx_fifo_source_last; +assign soc_litedramcore_uart_uart_source_payload_data = soc_litedramcore_uart_tx_fifo_source_payload_data; +assign soc_litedramcore_uart_tx_trigger = (~soc_litedramcore_uart_tx_fifo_sink_ready); +assign soc_litedramcore_uart_rx_fifo_sink_valid = soc_litedramcore_uart_uart_sink_valid; +assign soc_litedramcore_uart_uart_sink_ready = soc_litedramcore_uart_rx_fifo_sink_ready; +assign soc_litedramcore_uart_rx_fifo_sink_first = soc_litedramcore_uart_uart_sink_first; +assign soc_litedramcore_uart_rx_fifo_sink_last = soc_litedramcore_uart_uart_sink_last; +assign soc_litedramcore_uart_rx_fifo_sink_payload_data = soc_litedramcore_uart_uart_sink_payload_data; +assign soc_litedramcore_uart_rxempty_status = (~soc_litedramcore_uart_rx_fifo_source_valid); +assign soc_litedramcore_uart_rxtx_w = soc_litedramcore_uart_rx_fifo_source_payload_data; +assign soc_litedramcore_uart_rx_fifo_source_ready = (soc_litedramcore_uart_rx_clear | (1'd0 & soc_litedramcore_uart_rxtx_we)); +assign soc_litedramcore_uart_rx_trigger = (~soc_litedramcore_uart_rx_fifo_source_valid); + +// synthesis translate_off +reg dummy_d_2; +// synthesis translate_on +always @(*) begin + soc_litedramcore_uart_eventmanager_status_w <= 2'd0; + soc_litedramcore_uart_eventmanager_status_w[0] <= soc_litedramcore_uart_tx_status; + soc_litedramcore_uart_eventmanager_status_w[1] <= soc_litedramcore_uart_rx_status; +// synthesis translate_off + dummy_d_2 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_3; +// synthesis translate_on +always @(*) begin + soc_litedramcore_uart_tx_clear <= 1'd0; + if ((soc_litedramcore_uart_eventmanager_pending_re & soc_litedramcore_uart_eventmanager_pending_r[0])) begin + soc_litedramcore_uart_tx_clear <= 1'd1; + end +// synthesis translate_off + dummy_d_3 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_4; +// synthesis translate_on +always @(*) begin + soc_litedramcore_uart_eventmanager_pending_w <= 2'd0; + soc_litedramcore_uart_eventmanager_pending_w[0] <= soc_litedramcore_uart_tx_pending; + soc_litedramcore_uart_eventmanager_pending_w[1] <= soc_litedramcore_uart_rx_pending; +// synthesis translate_off + dummy_d_4 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_5; +// synthesis translate_on +always @(*) begin + soc_litedramcore_uart_rx_clear <= 1'd0; + if ((soc_litedramcore_uart_eventmanager_pending_re & soc_litedramcore_uart_eventmanager_pending_r[1])) begin + soc_litedramcore_uart_rx_clear <= 1'd1; + end +// synthesis translate_off + dummy_d_5 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_uart_irq = ((soc_litedramcore_uart_eventmanager_pending_w[0] & soc_litedramcore_uart_eventmanager_storage[0]) | (soc_litedramcore_uart_eventmanager_pending_w[1] & soc_litedramcore_uart_eventmanager_storage[1])); +assign soc_litedramcore_uart_tx_status = soc_litedramcore_uart_tx_trigger; +assign soc_litedramcore_uart_rx_status = soc_litedramcore_uart_rx_trigger; +assign soc_litedramcore_uart_tx_fifo_syncfifo_din = {soc_litedramcore_uart_tx_fifo_fifo_in_last, soc_litedramcore_uart_tx_fifo_fifo_in_first, soc_litedramcore_uart_tx_fifo_fifo_in_payload_data}; +assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout; +assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout; +assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout; +assign soc_litedramcore_uart_tx_fifo_sink_ready = soc_litedramcore_uart_tx_fifo_syncfifo_writable; +assign soc_litedramcore_uart_tx_fifo_syncfifo_we = soc_litedramcore_uart_tx_fifo_sink_valid; +assign soc_litedramcore_uart_tx_fifo_fifo_in_first = soc_litedramcore_uart_tx_fifo_sink_first; +assign soc_litedramcore_uart_tx_fifo_fifo_in_last = soc_litedramcore_uart_tx_fifo_sink_last; +assign soc_litedramcore_uart_tx_fifo_fifo_in_payload_data = soc_litedramcore_uart_tx_fifo_sink_payload_data; +assign soc_litedramcore_uart_tx_fifo_source_valid = soc_litedramcore_uart_tx_fifo_readable; +assign soc_litedramcore_uart_tx_fifo_source_first = soc_litedramcore_uart_tx_fifo_fifo_out_first; +assign soc_litedramcore_uart_tx_fifo_source_last = soc_litedramcore_uart_tx_fifo_fifo_out_last; +assign soc_litedramcore_uart_tx_fifo_source_payload_data = soc_litedramcore_uart_tx_fifo_fifo_out_payload_data; +assign soc_litedramcore_uart_tx_fifo_re = soc_litedramcore_uart_tx_fifo_source_ready; +assign soc_litedramcore_uart_tx_fifo_syncfifo_re = (soc_litedramcore_uart_tx_fifo_syncfifo_readable & ((~soc_litedramcore_uart_tx_fifo_readable) | soc_litedramcore_uart_tx_fifo_re)); +assign soc_litedramcore_uart_tx_fifo_level1 = (soc_litedramcore_uart_tx_fifo_level0 + soc_litedramcore_uart_tx_fifo_readable); + +// synthesis translate_off +reg dummy_d_6; +// synthesis translate_on +always @(*) begin + soc_litedramcore_uart_tx_fifo_wrport_adr <= 4'd0; + if (soc_litedramcore_uart_tx_fifo_replace) begin + soc_litedramcore_uart_tx_fifo_wrport_adr <= (soc_litedramcore_uart_tx_fifo_produce - 1'd1); + end else begin + soc_litedramcore_uart_tx_fifo_wrport_adr <= soc_litedramcore_uart_tx_fifo_produce; + end +// synthesis translate_off + dummy_d_6 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_uart_tx_fifo_wrport_dat_w = soc_litedramcore_uart_tx_fifo_syncfifo_din; +assign soc_litedramcore_uart_tx_fifo_wrport_we = (soc_litedramcore_uart_tx_fifo_syncfifo_we & (soc_litedramcore_uart_tx_fifo_syncfifo_writable | soc_litedramcore_uart_tx_fifo_replace)); +assign soc_litedramcore_uart_tx_fifo_do_read = (soc_litedramcore_uart_tx_fifo_syncfifo_readable & soc_litedramcore_uart_tx_fifo_syncfifo_re); +assign soc_litedramcore_uart_tx_fifo_rdport_adr = soc_litedramcore_uart_tx_fifo_consume; +assign soc_litedramcore_uart_tx_fifo_syncfifo_dout = soc_litedramcore_uart_tx_fifo_rdport_dat_r; +assign soc_litedramcore_uart_tx_fifo_rdport_re = soc_litedramcore_uart_tx_fifo_do_read; +assign soc_litedramcore_uart_tx_fifo_syncfifo_writable = (soc_litedramcore_uart_tx_fifo_level0 != 5'd16); +assign soc_litedramcore_uart_tx_fifo_syncfifo_readable = (soc_litedramcore_uart_tx_fifo_level0 != 1'd0); +assign soc_litedramcore_uart_rx_fifo_syncfifo_din = {soc_litedramcore_uart_rx_fifo_fifo_in_last, soc_litedramcore_uart_rx_fifo_fifo_in_first, soc_litedramcore_uart_rx_fifo_fifo_in_payload_data}; +assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout; +assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout; +assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout; +assign soc_litedramcore_uart_rx_fifo_sink_ready = soc_litedramcore_uart_rx_fifo_syncfifo_writable; +assign soc_litedramcore_uart_rx_fifo_syncfifo_we = soc_litedramcore_uart_rx_fifo_sink_valid; +assign soc_litedramcore_uart_rx_fifo_fifo_in_first = soc_litedramcore_uart_rx_fifo_sink_first; +assign soc_litedramcore_uart_rx_fifo_fifo_in_last = soc_litedramcore_uart_rx_fifo_sink_last; +assign soc_litedramcore_uart_rx_fifo_fifo_in_payload_data = soc_litedramcore_uart_rx_fifo_sink_payload_data; +assign soc_litedramcore_uart_rx_fifo_source_valid = soc_litedramcore_uart_rx_fifo_readable; +assign soc_litedramcore_uart_rx_fifo_source_first = soc_litedramcore_uart_rx_fifo_fifo_out_first; +assign soc_litedramcore_uart_rx_fifo_source_last = soc_litedramcore_uart_rx_fifo_fifo_out_last; +assign soc_litedramcore_uart_rx_fifo_source_payload_data = soc_litedramcore_uart_rx_fifo_fifo_out_payload_data; +assign soc_litedramcore_uart_rx_fifo_re = soc_litedramcore_uart_rx_fifo_source_ready; +assign soc_litedramcore_uart_rx_fifo_syncfifo_re = (soc_litedramcore_uart_rx_fifo_syncfifo_readable & ((~soc_litedramcore_uart_rx_fifo_readable) | soc_litedramcore_uart_rx_fifo_re)); +assign soc_litedramcore_uart_rx_fifo_level1 = (soc_litedramcore_uart_rx_fifo_level0 + soc_litedramcore_uart_rx_fifo_readable); + +// synthesis translate_off +reg dummy_d_7; +// synthesis translate_on +always @(*) begin + soc_litedramcore_uart_rx_fifo_wrport_adr <= 4'd0; + if (soc_litedramcore_uart_rx_fifo_replace) begin + soc_litedramcore_uart_rx_fifo_wrport_adr <= (soc_litedramcore_uart_rx_fifo_produce - 1'd1); + end else begin + soc_litedramcore_uart_rx_fifo_wrport_adr <= soc_litedramcore_uart_rx_fifo_produce; + end +// synthesis translate_off + dummy_d_7 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_uart_rx_fifo_wrport_dat_w = soc_litedramcore_uart_rx_fifo_syncfifo_din; +assign soc_litedramcore_uart_rx_fifo_wrport_we = (soc_litedramcore_uart_rx_fifo_syncfifo_we & (soc_litedramcore_uart_rx_fifo_syncfifo_writable | soc_litedramcore_uart_rx_fifo_replace)); +assign soc_litedramcore_uart_rx_fifo_do_read = (soc_litedramcore_uart_rx_fifo_syncfifo_readable & soc_litedramcore_uart_rx_fifo_syncfifo_re); +assign soc_litedramcore_uart_rx_fifo_rdport_adr = soc_litedramcore_uart_rx_fifo_consume; +assign soc_litedramcore_uart_rx_fifo_syncfifo_dout = soc_litedramcore_uart_rx_fifo_rdport_dat_r; +assign soc_litedramcore_uart_rx_fifo_rdport_re = soc_litedramcore_uart_rx_fifo_do_read; +assign soc_litedramcore_uart_rx_fifo_syncfifo_writable = (soc_litedramcore_uart_rx_fifo_level0 != 5'd16); +assign soc_litedramcore_uart_rx_fifo_syncfifo_readable = (soc_litedramcore_uart_rx_fifo_level0 != 1'd0); +assign soc_litedramcore_timer_zero_trigger = (soc_litedramcore_timer_value != 1'd0); +assign soc_litedramcore_timer_eventmanager_status_w = soc_litedramcore_timer_zero_status; + +// synthesis translate_off +reg dummy_d_8; +// synthesis translate_on +always @(*) begin + soc_litedramcore_timer_zero_clear <= 1'd0; + if ((soc_litedramcore_timer_eventmanager_pending_re & soc_litedramcore_timer_eventmanager_pending_r)) begin + soc_litedramcore_timer_zero_clear <= 1'd1; + end +// synthesis translate_off + dummy_d_8 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_timer_eventmanager_pending_w = soc_litedramcore_timer_zero_pending; +assign soc_litedramcore_timer_irq = (soc_litedramcore_timer_eventmanager_pending_w & soc_litedramcore_timer_eventmanager_storage); +assign soc_litedramcore_timer_zero_status = soc_litedramcore_timer_zero_trigger; +assign soc_litedramcore_interface_dat_w = soc_litedramcore_bus_wishbone_dat_w; +assign soc_litedramcore_bus_wishbone_dat_r = soc_litedramcore_interface_dat_r; + +// synthesis translate_off +reg dummy_d_9; +// synthesis translate_on +always @(*) begin + vns_wb2csr_next_state <= 1'd0; + vns_wb2csr_next_state <= vns_wb2csr_state; + case (vns_wb2csr_state) + 1'd1: begin + vns_wb2csr_next_state <= 1'd0; + end + default: begin + if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin + vns_wb2csr_next_state <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_9 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_10; +// synthesis translate_on +always @(*) begin + soc_litedramcore_interface_we <= 1'd0; + case (vns_wb2csr_state) + 1'd1: begin + end + default: begin + if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin + soc_litedramcore_interface_we <= soc_litedramcore_bus_wishbone_we; + end + end + endcase +// synthesis translate_off + dummy_d_10 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_11; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bus_wishbone_ack <= 1'd0; + case (vns_wb2csr_state) + 1'd1: begin + soc_litedramcore_bus_wishbone_ack <= 1'd1; + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_11 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_12; +// synthesis translate_on +always @(*) begin + soc_litedramcore_interface_adr <= 14'd0; + case (vns_wb2csr_state) + 1'd1: begin + end + default: begin + if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin + soc_litedramcore_interface_adr <= soc_litedramcore_bus_wishbone_adr; + end + end + endcase +// synthesis translate_off + dummy_d_12 = dummy_s; +// synthesis translate_on +end +assign soc_sys_pll_reset = rst; +assign pll_locked = soc_sys_pll_locked; +assign soc_iodelay_pll_reset = rst; +assign soc_s7pll0_clkin = clk; +assign sys_clk = soc_s7pll0_clkout_buf0; +assign sys4x_clk = soc_s7pll0_clkout_buf1; +assign sys4x_dqs_clk = soc_s7pll0_clkout_buf2; +assign soc_s7pll1_clkin = clk; +assign iodelay_clk = soc_s7pll1_clkout_buf; +assign soc_a7ddrphy_bitslip0_i = soc_a7ddrphy_dq_i_data0; + +// synthesis translate_off +reg dummy_d_13; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_dfi_p0_rddata <= 32'd0; + soc_a7ddrphy_dfi_p0_rddata[0] <= soc_a7ddrphy_bitslip0_o[0]; + soc_a7ddrphy_dfi_p0_rddata[16] <= soc_a7ddrphy_bitslip0_o[1]; + soc_a7ddrphy_dfi_p0_rddata[1] <= soc_a7ddrphy_bitslip1_o[0]; + soc_a7ddrphy_dfi_p0_rddata[17] <= soc_a7ddrphy_bitslip1_o[1]; + soc_a7ddrphy_dfi_p0_rddata[2] <= soc_a7ddrphy_bitslip2_o[0]; + soc_a7ddrphy_dfi_p0_rddata[18] <= soc_a7ddrphy_bitslip2_o[1]; + soc_a7ddrphy_dfi_p0_rddata[3] <= soc_a7ddrphy_bitslip3_o[0]; + soc_a7ddrphy_dfi_p0_rddata[19] <= soc_a7ddrphy_bitslip3_o[1]; + soc_a7ddrphy_dfi_p0_rddata[4] <= soc_a7ddrphy_bitslip4_o[0]; + soc_a7ddrphy_dfi_p0_rddata[20] <= soc_a7ddrphy_bitslip4_o[1]; + soc_a7ddrphy_dfi_p0_rddata[5] <= soc_a7ddrphy_bitslip5_o[0]; + soc_a7ddrphy_dfi_p0_rddata[21] <= soc_a7ddrphy_bitslip5_o[1]; + soc_a7ddrphy_dfi_p0_rddata[6] <= soc_a7ddrphy_bitslip6_o[0]; + soc_a7ddrphy_dfi_p0_rddata[22] <= soc_a7ddrphy_bitslip6_o[1]; + soc_a7ddrphy_dfi_p0_rddata[7] <= soc_a7ddrphy_bitslip7_o[0]; + soc_a7ddrphy_dfi_p0_rddata[23] <= soc_a7ddrphy_bitslip7_o[1]; + soc_a7ddrphy_dfi_p0_rddata[8] <= soc_a7ddrphy_bitslip8_o[0]; + soc_a7ddrphy_dfi_p0_rddata[24] <= soc_a7ddrphy_bitslip8_o[1]; + soc_a7ddrphy_dfi_p0_rddata[9] <= soc_a7ddrphy_bitslip9_o[0]; + soc_a7ddrphy_dfi_p0_rddata[25] <= soc_a7ddrphy_bitslip9_o[1]; + soc_a7ddrphy_dfi_p0_rddata[10] <= soc_a7ddrphy_bitslip10_o[0]; + soc_a7ddrphy_dfi_p0_rddata[26] <= soc_a7ddrphy_bitslip10_o[1]; + soc_a7ddrphy_dfi_p0_rddata[11] <= soc_a7ddrphy_bitslip11_o[0]; + soc_a7ddrphy_dfi_p0_rddata[27] <= soc_a7ddrphy_bitslip11_o[1]; + soc_a7ddrphy_dfi_p0_rddata[12] <= soc_a7ddrphy_bitslip12_o[0]; + soc_a7ddrphy_dfi_p0_rddata[28] <= soc_a7ddrphy_bitslip12_o[1]; + soc_a7ddrphy_dfi_p0_rddata[13] <= soc_a7ddrphy_bitslip13_o[0]; + soc_a7ddrphy_dfi_p0_rddata[29] <= soc_a7ddrphy_bitslip13_o[1]; + soc_a7ddrphy_dfi_p0_rddata[14] <= soc_a7ddrphy_bitslip14_o[0]; + soc_a7ddrphy_dfi_p0_rddata[30] <= soc_a7ddrphy_bitslip14_o[1]; + soc_a7ddrphy_dfi_p0_rddata[15] <= soc_a7ddrphy_bitslip15_o[0]; + soc_a7ddrphy_dfi_p0_rddata[31] <= soc_a7ddrphy_bitslip15_o[1]; +// synthesis translate_off + dummy_d_13 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_14; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_dfi_p1_rddata <= 32'd0; + soc_a7ddrphy_dfi_p1_rddata[0] <= soc_a7ddrphy_bitslip0_o[2]; + soc_a7ddrphy_dfi_p1_rddata[16] <= soc_a7ddrphy_bitslip0_o[3]; + soc_a7ddrphy_dfi_p1_rddata[1] <= soc_a7ddrphy_bitslip1_o[2]; + soc_a7ddrphy_dfi_p1_rddata[17] <= soc_a7ddrphy_bitslip1_o[3]; + soc_a7ddrphy_dfi_p1_rddata[2] <= soc_a7ddrphy_bitslip2_o[2]; + soc_a7ddrphy_dfi_p1_rddata[18] <= soc_a7ddrphy_bitslip2_o[3]; + soc_a7ddrphy_dfi_p1_rddata[3] <= soc_a7ddrphy_bitslip3_o[2]; + soc_a7ddrphy_dfi_p1_rddata[19] <= soc_a7ddrphy_bitslip3_o[3]; + soc_a7ddrphy_dfi_p1_rddata[4] <= soc_a7ddrphy_bitslip4_o[2]; + soc_a7ddrphy_dfi_p1_rddata[20] <= soc_a7ddrphy_bitslip4_o[3]; + soc_a7ddrphy_dfi_p1_rddata[5] <= soc_a7ddrphy_bitslip5_o[2]; + soc_a7ddrphy_dfi_p1_rddata[21] <= soc_a7ddrphy_bitslip5_o[3]; + soc_a7ddrphy_dfi_p1_rddata[6] <= soc_a7ddrphy_bitslip6_o[2]; + soc_a7ddrphy_dfi_p1_rddata[22] <= soc_a7ddrphy_bitslip6_o[3]; + soc_a7ddrphy_dfi_p1_rddata[7] <= soc_a7ddrphy_bitslip7_o[2]; + soc_a7ddrphy_dfi_p1_rddata[23] <= soc_a7ddrphy_bitslip7_o[3]; + soc_a7ddrphy_dfi_p1_rddata[8] <= soc_a7ddrphy_bitslip8_o[2]; + soc_a7ddrphy_dfi_p1_rddata[24] <= soc_a7ddrphy_bitslip8_o[3]; + soc_a7ddrphy_dfi_p1_rddata[9] <= soc_a7ddrphy_bitslip9_o[2]; + soc_a7ddrphy_dfi_p1_rddata[25] <= soc_a7ddrphy_bitslip9_o[3]; + soc_a7ddrphy_dfi_p1_rddata[10] <= soc_a7ddrphy_bitslip10_o[2]; + soc_a7ddrphy_dfi_p1_rddata[26] <= soc_a7ddrphy_bitslip10_o[3]; + soc_a7ddrphy_dfi_p1_rddata[11] <= soc_a7ddrphy_bitslip11_o[2]; + soc_a7ddrphy_dfi_p1_rddata[27] <= soc_a7ddrphy_bitslip11_o[3]; + soc_a7ddrphy_dfi_p1_rddata[12] <= soc_a7ddrphy_bitslip12_o[2]; + soc_a7ddrphy_dfi_p1_rddata[28] <= soc_a7ddrphy_bitslip12_o[3]; + soc_a7ddrphy_dfi_p1_rddata[13] <= soc_a7ddrphy_bitslip13_o[2]; + soc_a7ddrphy_dfi_p1_rddata[29] <= soc_a7ddrphy_bitslip13_o[3]; + soc_a7ddrphy_dfi_p1_rddata[14] <= soc_a7ddrphy_bitslip14_o[2]; + soc_a7ddrphy_dfi_p1_rddata[30] <= soc_a7ddrphy_bitslip14_o[3]; + soc_a7ddrphy_dfi_p1_rddata[15] <= soc_a7ddrphy_bitslip15_o[2]; + soc_a7ddrphy_dfi_p1_rddata[31] <= soc_a7ddrphy_bitslip15_o[3]; +// synthesis translate_off + dummy_d_14 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_15; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_dfi_p2_rddata <= 32'd0; + soc_a7ddrphy_dfi_p2_rddata[0] <= soc_a7ddrphy_bitslip0_o[4]; + soc_a7ddrphy_dfi_p2_rddata[16] <= soc_a7ddrphy_bitslip0_o[5]; + soc_a7ddrphy_dfi_p2_rddata[1] <= soc_a7ddrphy_bitslip1_o[4]; + soc_a7ddrphy_dfi_p2_rddata[17] <= soc_a7ddrphy_bitslip1_o[5]; + soc_a7ddrphy_dfi_p2_rddata[2] <= soc_a7ddrphy_bitslip2_o[4]; + soc_a7ddrphy_dfi_p2_rddata[18] <= soc_a7ddrphy_bitslip2_o[5]; + soc_a7ddrphy_dfi_p2_rddata[3] <= soc_a7ddrphy_bitslip3_o[4]; + soc_a7ddrphy_dfi_p2_rddata[19] <= soc_a7ddrphy_bitslip3_o[5]; + soc_a7ddrphy_dfi_p2_rddata[4] <= soc_a7ddrphy_bitslip4_o[4]; + soc_a7ddrphy_dfi_p2_rddata[20] <= soc_a7ddrphy_bitslip4_o[5]; + soc_a7ddrphy_dfi_p2_rddata[5] <= soc_a7ddrphy_bitslip5_o[4]; + soc_a7ddrphy_dfi_p2_rddata[21] <= soc_a7ddrphy_bitslip5_o[5]; + soc_a7ddrphy_dfi_p2_rddata[6] <= soc_a7ddrphy_bitslip6_o[4]; + soc_a7ddrphy_dfi_p2_rddata[22] <= soc_a7ddrphy_bitslip6_o[5]; + soc_a7ddrphy_dfi_p2_rddata[7] <= soc_a7ddrphy_bitslip7_o[4]; + soc_a7ddrphy_dfi_p2_rddata[23] <= soc_a7ddrphy_bitslip7_o[5]; + soc_a7ddrphy_dfi_p2_rddata[8] <= soc_a7ddrphy_bitslip8_o[4]; + soc_a7ddrphy_dfi_p2_rddata[24] <= soc_a7ddrphy_bitslip8_o[5]; + soc_a7ddrphy_dfi_p2_rddata[9] <= soc_a7ddrphy_bitslip9_o[4]; + soc_a7ddrphy_dfi_p2_rddata[25] <= soc_a7ddrphy_bitslip9_o[5]; + soc_a7ddrphy_dfi_p2_rddata[10] <= soc_a7ddrphy_bitslip10_o[4]; + soc_a7ddrphy_dfi_p2_rddata[26] <= soc_a7ddrphy_bitslip10_o[5]; + soc_a7ddrphy_dfi_p2_rddata[11] <= soc_a7ddrphy_bitslip11_o[4]; + soc_a7ddrphy_dfi_p2_rddata[27] <= soc_a7ddrphy_bitslip11_o[5]; + soc_a7ddrphy_dfi_p2_rddata[12] <= soc_a7ddrphy_bitslip12_o[4]; + soc_a7ddrphy_dfi_p2_rddata[28] <= soc_a7ddrphy_bitslip12_o[5]; + soc_a7ddrphy_dfi_p2_rddata[13] <= soc_a7ddrphy_bitslip13_o[4]; + soc_a7ddrphy_dfi_p2_rddata[29] <= soc_a7ddrphy_bitslip13_o[5]; + soc_a7ddrphy_dfi_p2_rddata[14] <= soc_a7ddrphy_bitslip14_o[4]; + soc_a7ddrphy_dfi_p2_rddata[30] <= soc_a7ddrphy_bitslip14_o[5]; + soc_a7ddrphy_dfi_p2_rddata[15] <= soc_a7ddrphy_bitslip15_o[4]; + soc_a7ddrphy_dfi_p2_rddata[31] <= soc_a7ddrphy_bitslip15_o[5]; +// synthesis translate_off + dummy_d_15 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_16; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_dfi_p3_rddata <= 32'd0; + soc_a7ddrphy_dfi_p3_rddata[0] <= soc_a7ddrphy_bitslip0_o[6]; + soc_a7ddrphy_dfi_p3_rddata[16] <= soc_a7ddrphy_bitslip0_o[7]; + soc_a7ddrphy_dfi_p3_rddata[1] <= soc_a7ddrphy_bitslip1_o[6]; + soc_a7ddrphy_dfi_p3_rddata[17] <= soc_a7ddrphy_bitslip1_o[7]; + soc_a7ddrphy_dfi_p3_rddata[2] <= soc_a7ddrphy_bitslip2_o[6]; + soc_a7ddrphy_dfi_p3_rddata[18] <= soc_a7ddrphy_bitslip2_o[7]; + soc_a7ddrphy_dfi_p3_rddata[3] <= soc_a7ddrphy_bitslip3_o[6]; + soc_a7ddrphy_dfi_p3_rddata[19] <= soc_a7ddrphy_bitslip3_o[7]; + soc_a7ddrphy_dfi_p3_rddata[4] <= soc_a7ddrphy_bitslip4_o[6]; + soc_a7ddrphy_dfi_p3_rddata[20] <= soc_a7ddrphy_bitslip4_o[7]; + soc_a7ddrphy_dfi_p3_rddata[5] <= soc_a7ddrphy_bitslip5_o[6]; + soc_a7ddrphy_dfi_p3_rddata[21] <= soc_a7ddrphy_bitslip5_o[7]; + soc_a7ddrphy_dfi_p3_rddata[6] <= soc_a7ddrphy_bitslip6_o[6]; + soc_a7ddrphy_dfi_p3_rddata[22] <= soc_a7ddrphy_bitslip6_o[7]; + soc_a7ddrphy_dfi_p3_rddata[7] <= soc_a7ddrphy_bitslip7_o[6]; + soc_a7ddrphy_dfi_p3_rddata[23] <= soc_a7ddrphy_bitslip7_o[7]; + soc_a7ddrphy_dfi_p3_rddata[8] <= soc_a7ddrphy_bitslip8_o[6]; + soc_a7ddrphy_dfi_p3_rddata[24] <= soc_a7ddrphy_bitslip8_o[7]; + soc_a7ddrphy_dfi_p3_rddata[9] <= soc_a7ddrphy_bitslip9_o[6]; + soc_a7ddrphy_dfi_p3_rddata[25] <= soc_a7ddrphy_bitslip9_o[7]; + soc_a7ddrphy_dfi_p3_rddata[10] <= soc_a7ddrphy_bitslip10_o[6]; + soc_a7ddrphy_dfi_p3_rddata[26] <= soc_a7ddrphy_bitslip10_o[7]; + soc_a7ddrphy_dfi_p3_rddata[11] <= soc_a7ddrphy_bitslip11_o[6]; + soc_a7ddrphy_dfi_p3_rddata[27] <= soc_a7ddrphy_bitslip11_o[7]; + soc_a7ddrphy_dfi_p3_rddata[12] <= soc_a7ddrphy_bitslip12_o[6]; + soc_a7ddrphy_dfi_p3_rddata[28] <= soc_a7ddrphy_bitslip12_o[7]; + soc_a7ddrphy_dfi_p3_rddata[13] <= soc_a7ddrphy_bitslip13_o[6]; + soc_a7ddrphy_dfi_p3_rddata[29] <= soc_a7ddrphy_bitslip13_o[7]; + soc_a7ddrphy_dfi_p3_rddata[14] <= soc_a7ddrphy_bitslip14_o[6]; + soc_a7ddrphy_dfi_p3_rddata[30] <= soc_a7ddrphy_bitslip14_o[7]; + soc_a7ddrphy_dfi_p3_rddata[15] <= soc_a7ddrphy_bitslip15_o[6]; + soc_a7ddrphy_dfi_p3_rddata[31] <= soc_a7ddrphy_bitslip15_o[7]; +// synthesis translate_off + dummy_d_16 = dummy_s; +// synthesis translate_on +end +assign soc_a7ddrphy_bitslip1_i = soc_a7ddrphy_dq_i_data1; +assign soc_a7ddrphy_bitslip2_i = soc_a7ddrphy_dq_i_data2; +assign soc_a7ddrphy_bitslip3_i = soc_a7ddrphy_dq_i_data3; +assign soc_a7ddrphy_bitslip4_i = soc_a7ddrphy_dq_i_data4; +assign soc_a7ddrphy_bitslip5_i = soc_a7ddrphy_dq_i_data5; +assign soc_a7ddrphy_bitslip6_i = soc_a7ddrphy_dq_i_data6; +assign soc_a7ddrphy_bitslip7_i = soc_a7ddrphy_dq_i_data7; +assign soc_a7ddrphy_bitslip8_i = soc_a7ddrphy_dq_i_data8; +assign soc_a7ddrphy_bitslip9_i = soc_a7ddrphy_dq_i_data9; +assign soc_a7ddrphy_bitslip10_i = soc_a7ddrphy_dq_i_data10; +assign soc_a7ddrphy_bitslip11_i = soc_a7ddrphy_dq_i_data11; +assign soc_a7ddrphy_bitslip12_i = soc_a7ddrphy_dq_i_data12; +assign soc_a7ddrphy_bitslip13_i = soc_a7ddrphy_dq_i_data13; +assign soc_a7ddrphy_bitslip14_i = soc_a7ddrphy_dq_i_data14; +assign soc_a7ddrphy_bitslip15_i = soc_a7ddrphy_dq_i_data15; +assign soc_a7ddrphy_rddata_en = {soc_a7ddrphy_rddata_en_last, soc_a7ddrphy_dfi_p2_rddata_en}; +assign soc_a7ddrphy_wrdata_en = {soc_a7ddrphy_wrdata_en_last, soc_a7ddrphy_dfi_p3_wrdata_en}; +assign soc_a7ddrphy_dq_oe = soc_a7ddrphy_wrdata_en[2]; + +// synthesis translate_off +reg dummy_d_17; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_dqs_oe <= 1'd0; + if (soc_a7ddrphy_wlevel_en_storage) begin + soc_a7ddrphy_dqs_oe <= 1'd1; + end else begin + soc_a7ddrphy_dqs_oe <= soc_a7ddrphy_dq_oe; + end +// synthesis translate_off + dummy_d_17 = dummy_s; +// synthesis translate_on +end +assign soc_a7ddrphy_dqspattern0 = (soc_a7ddrphy_wrdata_en[1] & (~soc_a7ddrphy_wrdata_en[2])); +assign soc_a7ddrphy_dqspattern1 = (soc_a7ddrphy_wrdata_en[3] & (~soc_a7ddrphy_wrdata_en[2])); + +// synthesis translate_off +reg dummy_d_18; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_dqspattern_o0 <= 8'd0; + soc_a7ddrphy_dqspattern_o0 <= 7'd85; + if (soc_a7ddrphy_dqspattern0) begin + soc_a7ddrphy_dqspattern_o0 <= 5'd21; + end + if (soc_a7ddrphy_dqspattern1) begin + soc_a7ddrphy_dqspattern_o0 <= 7'd84; + end + if (soc_a7ddrphy_wlevel_en_storage) begin + soc_a7ddrphy_dqspattern_o0 <= 1'd0; + if (soc_a7ddrphy_wlevel_strobe_re) begin + soc_a7ddrphy_dqspattern_o0 <= 1'd1; + end + end +// synthesis translate_off + dummy_d_18 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_19; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip0_o <= 8'd0; + case (soc_a7ddrphy_bitslip0_value) + 1'd0: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_19 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_20; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip1_o <= 8'd0; + case (soc_a7ddrphy_bitslip1_value) + 1'd0: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_20 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_21; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip2_o <= 8'd0; + case (soc_a7ddrphy_bitslip2_value) + 1'd0: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_21 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_22; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip3_o <= 8'd0; + case (soc_a7ddrphy_bitslip3_value) + 1'd0: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_22 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_23; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip4_o <= 8'd0; + case (soc_a7ddrphy_bitslip4_value) + 1'd0: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_23 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_24; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip5_o <= 8'd0; + case (soc_a7ddrphy_bitslip5_value) + 1'd0: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_24 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_25; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip6_o <= 8'd0; + case (soc_a7ddrphy_bitslip6_value) + 1'd0: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_25 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_26; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip7_o <= 8'd0; + case (soc_a7ddrphy_bitslip7_value) + 1'd0: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_26 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_27; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip8_o <= 8'd0; + case (soc_a7ddrphy_bitslip8_value) + 1'd0: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_27 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_28; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip9_o <= 8'd0; + case (soc_a7ddrphy_bitslip9_value) + 1'd0: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_28 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_29; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip10_o <= 8'd0; + case (soc_a7ddrphy_bitslip10_value) + 1'd0: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_29 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_30; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip11_o <= 8'd0; + case (soc_a7ddrphy_bitslip11_value) + 1'd0: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_30 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_31; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip12_o <= 8'd0; + case (soc_a7ddrphy_bitslip12_value) + 1'd0: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_31 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_32; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip13_o <= 8'd0; + case (soc_a7ddrphy_bitslip13_value) + 1'd0: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_32 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_33; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip14_o <= 8'd0; + case (soc_a7ddrphy_bitslip14_value) + 1'd0: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_33 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_34; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip15_o <= 8'd0; + case (soc_a7ddrphy_bitslip15_value) + 1'd0: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_34 = dummy_s; +// synthesis translate_on +end +assign soc_a7ddrphy_dfi_p0_address = soc_sdram_master_p0_address; +assign soc_a7ddrphy_dfi_p0_bank = soc_sdram_master_p0_bank; +assign soc_a7ddrphy_dfi_p0_cas_n = soc_sdram_master_p0_cas_n; +assign soc_a7ddrphy_dfi_p0_cs_n = soc_sdram_master_p0_cs_n; +assign soc_a7ddrphy_dfi_p0_ras_n = soc_sdram_master_p0_ras_n; +assign soc_a7ddrphy_dfi_p0_we_n = soc_sdram_master_p0_we_n; +assign soc_a7ddrphy_dfi_p0_cke = soc_sdram_master_p0_cke; +assign soc_a7ddrphy_dfi_p0_odt = soc_sdram_master_p0_odt; +assign soc_a7ddrphy_dfi_p0_reset_n = soc_sdram_master_p0_reset_n; +assign soc_a7ddrphy_dfi_p0_act_n = soc_sdram_master_p0_act_n; +assign soc_a7ddrphy_dfi_p0_wrdata = soc_sdram_master_p0_wrdata; +assign soc_a7ddrphy_dfi_p0_wrdata_en = soc_sdram_master_p0_wrdata_en; +assign soc_a7ddrphy_dfi_p0_wrdata_mask = soc_sdram_master_p0_wrdata_mask; +assign soc_a7ddrphy_dfi_p0_rddata_en = soc_sdram_master_p0_rddata_en; +assign soc_sdram_master_p0_rddata = soc_a7ddrphy_dfi_p0_rddata; +assign soc_sdram_master_p0_rddata_valid = soc_a7ddrphy_dfi_p0_rddata_valid; +assign soc_a7ddrphy_dfi_p1_address = soc_sdram_master_p1_address; +assign soc_a7ddrphy_dfi_p1_bank = soc_sdram_master_p1_bank; +assign soc_a7ddrphy_dfi_p1_cas_n = soc_sdram_master_p1_cas_n; +assign soc_a7ddrphy_dfi_p1_cs_n = soc_sdram_master_p1_cs_n; +assign soc_a7ddrphy_dfi_p1_ras_n = soc_sdram_master_p1_ras_n; +assign soc_a7ddrphy_dfi_p1_we_n = soc_sdram_master_p1_we_n; +assign soc_a7ddrphy_dfi_p1_cke = soc_sdram_master_p1_cke; +assign soc_a7ddrphy_dfi_p1_odt = soc_sdram_master_p1_odt; +assign soc_a7ddrphy_dfi_p1_reset_n = soc_sdram_master_p1_reset_n; +assign soc_a7ddrphy_dfi_p1_act_n = soc_sdram_master_p1_act_n; +assign soc_a7ddrphy_dfi_p1_wrdata = soc_sdram_master_p1_wrdata; +assign soc_a7ddrphy_dfi_p1_wrdata_en = soc_sdram_master_p1_wrdata_en; +assign soc_a7ddrphy_dfi_p1_wrdata_mask = soc_sdram_master_p1_wrdata_mask; +assign soc_a7ddrphy_dfi_p1_rddata_en = soc_sdram_master_p1_rddata_en; +assign soc_sdram_master_p1_rddata = soc_a7ddrphy_dfi_p1_rddata; +assign soc_sdram_master_p1_rddata_valid = soc_a7ddrphy_dfi_p1_rddata_valid; +assign soc_a7ddrphy_dfi_p2_address = soc_sdram_master_p2_address; +assign soc_a7ddrphy_dfi_p2_bank = soc_sdram_master_p2_bank; +assign soc_a7ddrphy_dfi_p2_cas_n = soc_sdram_master_p2_cas_n; +assign soc_a7ddrphy_dfi_p2_cs_n = soc_sdram_master_p2_cs_n; +assign soc_a7ddrphy_dfi_p2_ras_n = soc_sdram_master_p2_ras_n; +assign soc_a7ddrphy_dfi_p2_we_n = soc_sdram_master_p2_we_n; +assign soc_a7ddrphy_dfi_p2_cke = soc_sdram_master_p2_cke; +assign soc_a7ddrphy_dfi_p2_odt = soc_sdram_master_p2_odt; +assign soc_a7ddrphy_dfi_p2_reset_n = soc_sdram_master_p2_reset_n; +assign soc_a7ddrphy_dfi_p2_act_n = soc_sdram_master_p2_act_n; +assign soc_a7ddrphy_dfi_p2_wrdata = soc_sdram_master_p2_wrdata; +assign soc_a7ddrphy_dfi_p2_wrdata_en = soc_sdram_master_p2_wrdata_en; +assign soc_a7ddrphy_dfi_p2_wrdata_mask = soc_sdram_master_p2_wrdata_mask; +assign soc_a7ddrphy_dfi_p2_rddata_en = soc_sdram_master_p2_rddata_en; +assign soc_sdram_master_p2_rddata = soc_a7ddrphy_dfi_p2_rddata; +assign soc_sdram_master_p2_rddata_valid = soc_a7ddrphy_dfi_p2_rddata_valid; +assign soc_a7ddrphy_dfi_p3_address = soc_sdram_master_p3_address; +assign soc_a7ddrphy_dfi_p3_bank = soc_sdram_master_p3_bank; +assign soc_a7ddrphy_dfi_p3_cas_n = soc_sdram_master_p3_cas_n; +assign soc_a7ddrphy_dfi_p3_cs_n = soc_sdram_master_p3_cs_n; +assign soc_a7ddrphy_dfi_p3_ras_n = soc_sdram_master_p3_ras_n; +assign soc_a7ddrphy_dfi_p3_we_n = soc_sdram_master_p3_we_n; +assign soc_a7ddrphy_dfi_p3_cke = soc_sdram_master_p3_cke; +assign soc_a7ddrphy_dfi_p3_odt = soc_sdram_master_p3_odt; +assign soc_a7ddrphy_dfi_p3_reset_n = soc_sdram_master_p3_reset_n; +assign soc_a7ddrphy_dfi_p3_act_n = soc_sdram_master_p3_act_n; +assign soc_a7ddrphy_dfi_p3_wrdata = soc_sdram_master_p3_wrdata; +assign soc_a7ddrphy_dfi_p3_wrdata_en = soc_sdram_master_p3_wrdata_en; +assign soc_a7ddrphy_dfi_p3_wrdata_mask = soc_sdram_master_p3_wrdata_mask; +assign soc_a7ddrphy_dfi_p3_rddata_en = soc_sdram_master_p3_rddata_en; +assign soc_sdram_master_p3_rddata = soc_a7ddrphy_dfi_p3_rddata; +assign soc_sdram_master_p3_rddata_valid = soc_a7ddrphy_dfi_p3_rddata_valid; +assign soc_sdram_slave_p0_address = soc_sdram_dfi_p0_address; +assign soc_sdram_slave_p0_bank = soc_sdram_dfi_p0_bank; +assign soc_sdram_slave_p0_cas_n = soc_sdram_dfi_p0_cas_n; +assign soc_sdram_slave_p0_cs_n = soc_sdram_dfi_p0_cs_n; +assign soc_sdram_slave_p0_ras_n = soc_sdram_dfi_p0_ras_n; +assign soc_sdram_slave_p0_we_n = soc_sdram_dfi_p0_we_n; +assign soc_sdram_slave_p0_cke = soc_sdram_dfi_p0_cke; +assign soc_sdram_slave_p0_odt = soc_sdram_dfi_p0_odt; +assign soc_sdram_slave_p0_reset_n = soc_sdram_dfi_p0_reset_n; +assign soc_sdram_slave_p0_act_n = soc_sdram_dfi_p0_act_n; +assign soc_sdram_slave_p0_wrdata = soc_sdram_dfi_p0_wrdata; +assign soc_sdram_slave_p0_wrdata_en = soc_sdram_dfi_p0_wrdata_en; +assign soc_sdram_slave_p0_wrdata_mask = soc_sdram_dfi_p0_wrdata_mask; +assign soc_sdram_slave_p0_rddata_en = soc_sdram_dfi_p0_rddata_en; +assign soc_sdram_dfi_p0_rddata = soc_sdram_slave_p0_rddata; +assign soc_sdram_dfi_p0_rddata_valid = soc_sdram_slave_p0_rddata_valid; +assign soc_sdram_slave_p1_address = soc_sdram_dfi_p1_address; +assign soc_sdram_slave_p1_bank = soc_sdram_dfi_p1_bank; +assign soc_sdram_slave_p1_cas_n = soc_sdram_dfi_p1_cas_n; +assign soc_sdram_slave_p1_cs_n = soc_sdram_dfi_p1_cs_n; +assign soc_sdram_slave_p1_ras_n = soc_sdram_dfi_p1_ras_n; +assign soc_sdram_slave_p1_we_n = soc_sdram_dfi_p1_we_n; +assign soc_sdram_slave_p1_cke = soc_sdram_dfi_p1_cke; +assign soc_sdram_slave_p1_odt = soc_sdram_dfi_p1_odt; +assign soc_sdram_slave_p1_reset_n = soc_sdram_dfi_p1_reset_n; +assign soc_sdram_slave_p1_act_n = soc_sdram_dfi_p1_act_n; +assign soc_sdram_slave_p1_wrdata = soc_sdram_dfi_p1_wrdata; +assign soc_sdram_slave_p1_wrdata_en = soc_sdram_dfi_p1_wrdata_en; +assign soc_sdram_slave_p1_wrdata_mask = soc_sdram_dfi_p1_wrdata_mask; +assign soc_sdram_slave_p1_rddata_en = soc_sdram_dfi_p1_rddata_en; +assign soc_sdram_dfi_p1_rddata = soc_sdram_slave_p1_rddata; +assign soc_sdram_dfi_p1_rddata_valid = soc_sdram_slave_p1_rddata_valid; +assign soc_sdram_slave_p2_address = soc_sdram_dfi_p2_address; +assign soc_sdram_slave_p2_bank = soc_sdram_dfi_p2_bank; +assign soc_sdram_slave_p2_cas_n = soc_sdram_dfi_p2_cas_n; +assign soc_sdram_slave_p2_cs_n = soc_sdram_dfi_p2_cs_n; +assign soc_sdram_slave_p2_ras_n = soc_sdram_dfi_p2_ras_n; +assign soc_sdram_slave_p2_we_n = soc_sdram_dfi_p2_we_n; +assign soc_sdram_slave_p2_cke = soc_sdram_dfi_p2_cke; +assign soc_sdram_slave_p2_odt = soc_sdram_dfi_p2_odt; +assign soc_sdram_slave_p2_reset_n = soc_sdram_dfi_p2_reset_n; +assign soc_sdram_slave_p2_act_n = soc_sdram_dfi_p2_act_n; +assign soc_sdram_slave_p2_wrdata = soc_sdram_dfi_p2_wrdata; +assign soc_sdram_slave_p2_wrdata_en = soc_sdram_dfi_p2_wrdata_en; +assign soc_sdram_slave_p2_wrdata_mask = soc_sdram_dfi_p2_wrdata_mask; +assign soc_sdram_slave_p2_rddata_en = soc_sdram_dfi_p2_rddata_en; +assign soc_sdram_dfi_p2_rddata = soc_sdram_slave_p2_rddata; +assign soc_sdram_dfi_p2_rddata_valid = soc_sdram_slave_p2_rddata_valid; +assign soc_sdram_slave_p3_address = soc_sdram_dfi_p3_address; +assign soc_sdram_slave_p3_bank = soc_sdram_dfi_p3_bank; +assign soc_sdram_slave_p3_cas_n = soc_sdram_dfi_p3_cas_n; +assign soc_sdram_slave_p3_cs_n = soc_sdram_dfi_p3_cs_n; +assign soc_sdram_slave_p3_ras_n = soc_sdram_dfi_p3_ras_n; +assign soc_sdram_slave_p3_we_n = soc_sdram_dfi_p3_we_n; +assign soc_sdram_slave_p3_cke = soc_sdram_dfi_p3_cke; +assign soc_sdram_slave_p3_odt = soc_sdram_dfi_p3_odt; +assign soc_sdram_slave_p3_reset_n = soc_sdram_dfi_p3_reset_n; +assign soc_sdram_slave_p3_act_n = soc_sdram_dfi_p3_act_n; +assign soc_sdram_slave_p3_wrdata = soc_sdram_dfi_p3_wrdata; +assign soc_sdram_slave_p3_wrdata_en = soc_sdram_dfi_p3_wrdata_en; +assign soc_sdram_slave_p3_wrdata_mask = soc_sdram_dfi_p3_wrdata_mask; +assign soc_sdram_slave_p3_rddata_en = soc_sdram_dfi_p3_rddata_en; +assign soc_sdram_dfi_p3_rddata = soc_sdram_slave_p3_rddata; +assign soc_sdram_dfi_p3_rddata_valid = soc_sdram_slave_p3_rddata_valid; + +// synthesis translate_off +reg dummy_d_35; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_bank <= 3'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_bank <= soc_sdram_slave_p0_bank; + end else begin + soc_sdram_master_p0_bank <= soc_sdram_inti_p0_bank; + end +// synthesis translate_off + dummy_d_35 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_36; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_cas_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_cas_n <= soc_sdram_slave_p0_cas_n; + end else begin + soc_sdram_master_p0_cas_n <= soc_sdram_inti_p0_cas_n; + end +// synthesis translate_off + dummy_d_36 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_37; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_cs_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_cs_n <= soc_sdram_slave_p0_cs_n; + end else begin + soc_sdram_master_p0_cs_n <= soc_sdram_inti_p0_cs_n; + end +// synthesis translate_off + dummy_d_37 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_38; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_ras_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_ras_n <= soc_sdram_slave_p0_ras_n; + end else begin + soc_sdram_master_p0_ras_n <= soc_sdram_inti_p0_ras_n; + end +// synthesis translate_off + dummy_d_38 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_39; +// synthesis translate_on +always @(*) begin + soc_sdram_slave_p0_rddata <= 32'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_slave_p0_rddata <= soc_sdram_master_p0_rddata; + end else begin + end +// synthesis translate_off + dummy_d_39 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_40; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_we_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_we_n <= soc_sdram_slave_p0_we_n; + end else begin + soc_sdram_master_p0_we_n <= soc_sdram_inti_p0_we_n; + end +// synthesis translate_off + dummy_d_40 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_41; +// synthesis translate_on +always @(*) begin + soc_sdram_slave_p0_rddata_valid <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_slave_p0_rddata_valid <= soc_sdram_master_p0_rddata_valid; + end else begin + end +// synthesis translate_off + dummy_d_41 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_42; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_cke <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_cke <= soc_sdram_slave_p0_cke; + end else begin + soc_sdram_master_p0_cke <= soc_sdram_inti_p0_cke; + end +// synthesis translate_off + dummy_d_42 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_43; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_odt <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_odt <= soc_sdram_slave_p0_odt; + end else begin + soc_sdram_master_p0_odt <= soc_sdram_inti_p0_odt; + end +// synthesis translate_off + dummy_d_43 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_44; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_reset_n <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_reset_n <= soc_sdram_slave_p0_reset_n; + end else begin + soc_sdram_master_p0_reset_n <= soc_sdram_inti_p0_reset_n; + end +// synthesis translate_off + dummy_d_44 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_45; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_act_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_act_n <= soc_sdram_slave_p0_act_n; + end else begin + soc_sdram_master_p0_act_n <= soc_sdram_inti_p0_act_n; + end +// synthesis translate_off + dummy_d_45 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_46; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_wrdata <= 32'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_wrdata <= soc_sdram_slave_p0_wrdata; + end else begin + soc_sdram_master_p0_wrdata <= soc_sdram_inti_p0_wrdata; + end +// synthesis translate_off + dummy_d_46 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_47; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p1_rddata <= 32'd0; + if (soc_sdram_storage[0]) begin + end else begin + soc_sdram_inti_p1_rddata <= soc_sdram_master_p1_rddata; + end +// synthesis translate_off + dummy_d_47 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_48; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_wrdata_en <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_wrdata_en <= soc_sdram_slave_p0_wrdata_en; + end else begin + soc_sdram_master_p0_wrdata_en <= soc_sdram_inti_p0_wrdata_en; + end +// synthesis translate_off + dummy_d_48 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_49; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p1_rddata_valid <= 1'd0; + if (soc_sdram_storage[0]) begin + end else begin + soc_sdram_inti_p1_rddata_valid <= soc_sdram_master_p1_rddata_valid; + end +// synthesis translate_off + dummy_d_49 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_50; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_wrdata_mask <= 4'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_wrdata_mask <= soc_sdram_slave_p0_wrdata_mask; + end else begin + soc_sdram_master_p0_wrdata_mask <= soc_sdram_inti_p0_wrdata_mask; + end +// synthesis translate_off + dummy_d_50 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_51; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_rddata_en <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_rddata_en <= soc_sdram_slave_p0_rddata_en; + end else begin + soc_sdram_master_p0_rddata_en <= soc_sdram_inti_p0_rddata_en; + end +// synthesis translate_off + dummy_d_51 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_52; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_address <= 14'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_address <= soc_sdram_slave_p1_address; + end else begin + soc_sdram_master_p1_address <= soc_sdram_inti_p1_address; + end +// synthesis translate_off + dummy_d_52 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_53; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_bank <= 3'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_bank <= soc_sdram_slave_p1_bank; + end else begin + soc_sdram_master_p1_bank <= soc_sdram_inti_p1_bank; + end +// synthesis translate_off + dummy_d_53 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_54; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_cas_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_cas_n <= soc_sdram_slave_p1_cas_n; + end else begin + soc_sdram_master_p1_cas_n <= soc_sdram_inti_p1_cas_n; + end +// synthesis translate_off + dummy_d_54 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_55; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_cs_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_cs_n <= soc_sdram_slave_p1_cs_n; + end else begin + soc_sdram_master_p1_cs_n <= soc_sdram_inti_p1_cs_n; + end +// synthesis translate_off + dummy_d_55 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_56; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_ras_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_ras_n <= soc_sdram_slave_p1_ras_n; + end else begin + soc_sdram_master_p1_ras_n <= soc_sdram_inti_p1_ras_n; + end +// synthesis translate_off + dummy_d_56 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_57; +// synthesis translate_on +always @(*) begin + soc_sdram_slave_p1_rddata <= 32'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_slave_p1_rddata <= soc_sdram_master_p1_rddata; + end else begin + end +// synthesis translate_off + dummy_d_57 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_58; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_we_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_we_n <= soc_sdram_slave_p1_we_n; + end else begin + soc_sdram_master_p1_we_n <= soc_sdram_inti_p1_we_n; + end +// synthesis translate_off + dummy_d_58 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_59; +// synthesis translate_on +always @(*) begin + soc_sdram_slave_p1_rddata_valid <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_slave_p1_rddata_valid <= soc_sdram_master_p1_rddata_valid; + end else begin + end +// synthesis translate_off + dummy_d_59 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_60; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_cke <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_cke <= soc_sdram_slave_p1_cke; + end else begin + soc_sdram_master_p1_cke <= soc_sdram_inti_p1_cke; + end +// synthesis translate_off + dummy_d_60 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_61; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_odt <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_odt <= soc_sdram_slave_p1_odt; + end else begin + soc_sdram_master_p1_odt <= soc_sdram_inti_p1_odt; + end +// synthesis translate_off + dummy_d_61 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_62; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_reset_n <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_reset_n <= soc_sdram_slave_p1_reset_n; + end else begin + soc_sdram_master_p1_reset_n <= soc_sdram_inti_p1_reset_n; + end +// synthesis translate_off + dummy_d_62 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_63; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_act_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_act_n <= soc_sdram_slave_p1_act_n; + end else begin + soc_sdram_master_p1_act_n <= soc_sdram_inti_p1_act_n; + end +// synthesis translate_off + dummy_d_63 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_64; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_wrdata <= 32'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_wrdata <= soc_sdram_slave_p1_wrdata; + end else begin + soc_sdram_master_p1_wrdata <= soc_sdram_inti_p1_wrdata; + end +// synthesis translate_off + dummy_d_64 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_65; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p2_rddata <= 32'd0; + if (soc_sdram_storage[0]) begin + end else begin + soc_sdram_inti_p2_rddata <= soc_sdram_master_p2_rddata; + end +// synthesis translate_off + dummy_d_65 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_66; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_wrdata_en <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_wrdata_en <= soc_sdram_slave_p1_wrdata_en; + end else begin + soc_sdram_master_p1_wrdata_en <= soc_sdram_inti_p1_wrdata_en; + end +// synthesis translate_off + dummy_d_66 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_67; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p2_rddata_valid <= 1'd0; + if (soc_sdram_storage[0]) begin + end else begin + soc_sdram_inti_p2_rddata_valid <= soc_sdram_master_p2_rddata_valid; + end +// synthesis translate_off + dummy_d_67 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_68; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_wrdata_mask <= 4'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_wrdata_mask <= soc_sdram_slave_p1_wrdata_mask; + end else begin + soc_sdram_master_p1_wrdata_mask <= soc_sdram_inti_p1_wrdata_mask; + end +// synthesis translate_off + dummy_d_68 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_69; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_rddata_en <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_rddata_en <= soc_sdram_slave_p1_rddata_en; + end else begin + soc_sdram_master_p1_rddata_en <= soc_sdram_inti_p1_rddata_en; + end +// synthesis translate_off + dummy_d_69 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_70; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_address <= 14'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_address <= soc_sdram_slave_p2_address; + end else begin + soc_sdram_master_p2_address <= soc_sdram_inti_p2_address; + end +// synthesis translate_off + dummy_d_70 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_71; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_bank <= 3'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_bank <= soc_sdram_slave_p2_bank; + end else begin + soc_sdram_master_p2_bank <= soc_sdram_inti_p2_bank; + end +// synthesis translate_off + dummy_d_71 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_72; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_cas_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_cas_n <= soc_sdram_slave_p2_cas_n; + end else begin + soc_sdram_master_p2_cas_n <= soc_sdram_inti_p2_cas_n; + end +// synthesis translate_off + dummy_d_72 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_73; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_cs_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_cs_n <= soc_sdram_slave_p2_cs_n; + end else begin + soc_sdram_master_p2_cs_n <= soc_sdram_inti_p2_cs_n; + end +// synthesis translate_off + dummy_d_73 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_74; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_ras_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_ras_n <= soc_sdram_slave_p2_ras_n; + end else begin + soc_sdram_master_p2_ras_n <= soc_sdram_inti_p2_ras_n; + end +// synthesis translate_off + dummy_d_74 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_75; +// synthesis translate_on +always @(*) begin + soc_sdram_slave_p2_rddata <= 32'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_slave_p2_rddata <= soc_sdram_master_p2_rddata; + end else begin + end +// synthesis translate_off + dummy_d_75 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_76; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_we_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_we_n <= soc_sdram_slave_p2_we_n; + end else begin + soc_sdram_master_p2_we_n <= soc_sdram_inti_p2_we_n; + end +// synthesis translate_off + dummy_d_76 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_77; +// synthesis translate_on +always @(*) begin + soc_sdram_slave_p2_rddata_valid <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_slave_p2_rddata_valid <= soc_sdram_master_p2_rddata_valid; + end else begin + end +// synthesis translate_off + dummy_d_77 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_78; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_cke <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_cke <= soc_sdram_slave_p2_cke; + end else begin + soc_sdram_master_p2_cke <= soc_sdram_inti_p2_cke; + end +// synthesis translate_off + dummy_d_78 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_79; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_odt <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_odt <= soc_sdram_slave_p2_odt; + end else begin + soc_sdram_master_p2_odt <= soc_sdram_inti_p2_odt; + end +// synthesis translate_off + dummy_d_79 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_80; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_reset_n <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_reset_n <= soc_sdram_slave_p2_reset_n; + end else begin + soc_sdram_master_p2_reset_n <= soc_sdram_inti_p2_reset_n; + end +// synthesis translate_off + dummy_d_80 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_81; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_act_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_act_n <= soc_sdram_slave_p2_act_n; + end else begin + soc_sdram_master_p2_act_n <= soc_sdram_inti_p2_act_n; + end +// synthesis translate_off + dummy_d_81 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_82; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_wrdata <= 32'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_wrdata <= soc_sdram_slave_p2_wrdata; + end else begin + soc_sdram_master_p2_wrdata <= soc_sdram_inti_p2_wrdata; + end +// synthesis translate_off + dummy_d_82 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_83; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p3_rddata <= 32'd0; + if (soc_sdram_storage[0]) begin + end else begin + soc_sdram_inti_p3_rddata <= soc_sdram_master_p3_rddata; + end +// synthesis translate_off + dummy_d_83 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_84; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_wrdata_en <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_wrdata_en <= soc_sdram_slave_p2_wrdata_en; + end else begin + soc_sdram_master_p2_wrdata_en <= soc_sdram_inti_p2_wrdata_en; + end +// synthesis translate_off + dummy_d_84 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_85; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p3_rddata_valid <= 1'd0; + if (soc_sdram_storage[0]) begin + end else begin + soc_sdram_inti_p3_rddata_valid <= soc_sdram_master_p3_rddata_valid; + end +// synthesis translate_off + dummy_d_85 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_86; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_wrdata_mask <= 4'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_wrdata_mask <= soc_sdram_slave_p2_wrdata_mask; + end else begin + soc_sdram_master_p2_wrdata_mask <= soc_sdram_inti_p2_wrdata_mask; + end +// synthesis translate_off + dummy_d_86 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_87; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_rddata_en <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_rddata_en <= soc_sdram_slave_p2_rddata_en; + end else begin + soc_sdram_master_p2_rddata_en <= soc_sdram_inti_p2_rddata_en; + end +// synthesis translate_off + dummy_d_87 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_88; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_address <= 14'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_address <= soc_sdram_slave_p3_address; + end else begin + soc_sdram_master_p3_address <= soc_sdram_inti_p3_address; + end +// synthesis translate_off + dummy_d_88 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_89; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_bank <= 3'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_bank <= soc_sdram_slave_p3_bank; + end else begin + soc_sdram_master_p3_bank <= soc_sdram_inti_p3_bank; + end +// synthesis translate_off + dummy_d_89 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_90; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_cas_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_cas_n <= soc_sdram_slave_p3_cas_n; + end else begin + soc_sdram_master_p3_cas_n <= soc_sdram_inti_p3_cas_n; + end +// synthesis translate_off + dummy_d_90 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_91; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_cs_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_cs_n <= soc_sdram_slave_p3_cs_n; + end else begin + soc_sdram_master_p3_cs_n <= soc_sdram_inti_p3_cs_n; + end +// synthesis translate_off + dummy_d_91 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_92; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_ras_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_ras_n <= soc_sdram_slave_p3_ras_n; + end else begin + soc_sdram_master_p3_ras_n <= soc_sdram_inti_p3_ras_n; + end +// synthesis translate_off + dummy_d_92 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_93; +// synthesis translate_on +always @(*) begin + soc_sdram_slave_p3_rddata <= 32'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_slave_p3_rddata <= soc_sdram_master_p3_rddata; + end else begin + end +// synthesis translate_off + dummy_d_93 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_94; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_we_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_we_n <= soc_sdram_slave_p3_we_n; + end else begin + soc_sdram_master_p3_we_n <= soc_sdram_inti_p3_we_n; + end +// synthesis translate_off + dummy_d_94 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_95; +// synthesis translate_on +always @(*) begin + soc_sdram_slave_p3_rddata_valid <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_slave_p3_rddata_valid <= soc_sdram_master_p3_rddata_valid; + end else begin + end +// synthesis translate_off + dummy_d_95 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_96; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_cke <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_cke <= soc_sdram_slave_p3_cke; + end else begin + soc_sdram_master_p3_cke <= soc_sdram_inti_p3_cke; + end +// synthesis translate_off + dummy_d_96 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_97; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_odt <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_odt <= soc_sdram_slave_p3_odt; + end else begin + soc_sdram_master_p3_odt <= soc_sdram_inti_p3_odt; + end +// synthesis translate_off + dummy_d_97 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_98; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_reset_n <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_reset_n <= soc_sdram_slave_p3_reset_n; + end else begin + soc_sdram_master_p3_reset_n <= soc_sdram_inti_p3_reset_n; + end +// synthesis translate_off + dummy_d_98 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_99; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_act_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_act_n <= soc_sdram_slave_p3_act_n; + end else begin + soc_sdram_master_p3_act_n <= soc_sdram_inti_p3_act_n; + end +// synthesis translate_off + dummy_d_99 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_100; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_wrdata <= 32'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_wrdata <= soc_sdram_slave_p3_wrdata; + end else begin + soc_sdram_master_p3_wrdata <= soc_sdram_inti_p3_wrdata; + end +// synthesis translate_off + dummy_d_100 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_101; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p0_rddata <= 32'd0; + if (soc_sdram_storage[0]) begin + end else begin + soc_sdram_inti_p0_rddata <= soc_sdram_master_p0_rddata; + end +// synthesis translate_off + dummy_d_101 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_102; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_wrdata_en <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_wrdata_en <= soc_sdram_slave_p3_wrdata_en; + end else begin + soc_sdram_master_p3_wrdata_en <= soc_sdram_inti_p3_wrdata_en; + end +// synthesis translate_off + dummy_d_102 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_103; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p0_rddata_valid <= 1'd0; + if (soc_sdram_storage[0]) begin + end else begin + soc_sdram_inti_p0_rddata_valid <= soc_sdram_master_p0_rddata_valid; + end +// synthesis translate_off + dummy_d_103 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_104; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_wrdata_mask <= 4'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_wrdata_mask <= soc_sdram_slave_p3_wrdata_mask; + end else begin + soc_sdram_master_p3_wrdata_mask <= soc_sdram_inti_p3_wrdata_mask; + end +// synthesis translate_off + dummy_d_104 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_105; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_rddata_en <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_rddata_en <= soc_sdram_slave_p3_rddata_en; + end else begin + soc_sdram_master_p3_rddata_en <= soc_sdram_inti_p3_rddata_en; + end +// synthesis translate_off + dummy_d_105 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_106; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_address <= 14'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_address <= soc_sdram_slave_p0_address; + end else begin + soc_sdram_master_p0_address <= soc_sdram_inti_p0_address; + end +// synthesis translate_off + dummy_d_106 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_inti_p0_cke = soc_sdram_storage[1]; +assign soc_sdram_inti_p1_cke = soc_sdram_storage[1]; +assign soc_sdram_inti_p2_cke = soc_sdram_storage[1]; +assign soc_sdram_inti_p3_cke = soc_sdram_storage[1]; +assign soc_sdram_inti_p0_odt = soc_sdram_storage[2]; +assign soc_sdram_inti_p1_odt = soc_sdram_storage[2]; +assign soc_sdram_inti_p2_odt = soc_sdram_storage[2]; +assign soc_sdram_inti_p3_odt = soc_sdram_storage[2]; +assign soc_sdram_inti_p0_reset_n = soc_sdram_storage[3]; +assign soc_sdram_inti_p1_reset_n = soc_sdram_storage[3]; +assign soc_sdram_inti_p2_reset_n = soc_sdram_storage[3]; +assign soc_sdram_inti_p3_reset_n = soc_sdram_storage[3]; + +// synthesis translate_off +reg dummy_d_107; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p0_we_n <= 1'd1; + if (soc_sdram_phaseinjector0_command_issue_re) begin + soc_sdram_inti_p0_we_n <= (~soc_sdram_phaseinjector0_command_storage[1]); + end else begin + soc_sdram_inti_p0_we_n <= 1'd1; + end +// synthesis translate_off + dummy_d_107 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_108; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p0_cas_n <= 1'd1; + if (soc_sdram_phaseinjector0_command_issue_re) begin + soc_sdram_inti_p0_cas_n <= (~soc_sdram_phaseinjector0_command_storage[2]); + end else begin + soc_sdram_inti_p0_cas_n <= 1'd1; + end +// synthesis translate_off + dummy_d_108 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_109; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p0_cs_n <= 1'd1; + if (soc_sdram_phaseinjector0_command_issue_re) begin + soc_sdram_inti_p0_cs_n <= {1{(~soc_sdram_phaseinjector0_command_storage[0])}}; + end else begin + soc_sdram_inti_p0_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_109 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_110; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p0_ras_n <= 1'd1; + if (soc_sdram_phaseinjector0_command_issue_re) begin + soc_sdram_inti_p0_ras_n <= (~soc_sdram_phaseinjector0_command_storage[3]); + end else begin + soc_sdram_inti_p0_ras_n <= 1'd1; + end +// synthesis translate_off + dummy_d_110 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_inti_p0_address = soc_sdram_phaseinjector0_address_storage; +assign soc_sdram_inti_p0_bank = soc_sdram_phaseinjector0_baddress_storage; +assign soc_sdram_inti_p0_wrdata_en = (soc_sdram_phaseinjector0_command_issue_re & soc_sdram_phaseinjector0_command_storage[4]); +assign soc_sdram_inti_p0_rddata_en = (soc_sdram_phaseinjector0_command_issue_re & soc_sdram_phaseinjector0_command_storage[5]); +assign soc_sdram_inti_p0_wrdata = soc_sdram_phaseinjector0_wrdata_storage; +assign soc_sdram_inti_p0_wrdata_mask = 1'd0; + +// synthesis translate_off +reg dummy_d_111; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p1_we_n <= 1'd1; + if (soc_sdram_phaseinjector1_command_issue_re) begin + soc_sdram_inti_p1_we_n <= (~soc_sdram_phaseinjector1_command_storage[1]); + end else begin + soc_sdram_inti_p1_we_n <= 1'd1; + end +// synthesis translate_off + dummy_d_111 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_112; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p1_cas_n <= 1'd1; + if (soc_sdram_phaseinjector1_command_issue_re) begin + soc_sdram_inti_p1_cas_n <= (~soc_sdram_phaseinjector1_command_storage[2]); + end else begin + soc_sdram_inti_p1_cas_n <= 1'd1; + end +// synthesis translate_off + dummy_d_112 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_113; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p1_cs_n <= 1'd1; + if (soc_sdram_phaseinjector1_command_issue_re) begin + soc_sdram_inti_p1_cs_n <= {1{(~soc_sdram_phaseinjector1_command_storage[0])}}; + end else begin + soc_sdram_inti_p1_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_113 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_114; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p1_ras_n <= 1'd1; + if (soc_sdram_phaseinjector1_command_issue_re) begin + soc_sdram_inti_p1_ras_n <= (~soc_sdram_phaseinjector1_command_storage[3]); + end else begin + soc_sdram_inti_p1_ras_n <= 1'd1; + end +// synthesis translate_off + dummy_d_114 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_inti_p1_address = soc_sdram_phaseinjector1_address_storage; +assign soc_sdram_inti_p1_bank = soc_sdram_phaseinjector1_baddress_storage; +assign soc_sdram_inti_p1_wrdata_en = (soc_sdram_phaseinjector1_command_issue_re & soc_sdram_phaseinjector1_command_storage[4]); +assign soc_sdram_inti_p1_rddata_en = (soc_sdram_phaseinjector1_command_issue_re & soc_sdram_phaseinjector1_command_storage[5]); +assign soc_sdram_inti_p1_wrdata = soc_sdram_phaseinjector1_wrdata_storage; +assign soc_sdram_inti_p1_wrdata_mask = 1'd0; + +// synthesis translate_off +reg dummy_d_115; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p2_we_n <= 1'd1; + if (soc_sdram_phaseinjector2_command_issue_re) begin + soc_sdram_inti_p2_we_n <= (~soc_sdram_phaseinjector2_command_storage[1]); + end else begin + soc_sdram_inti_p2_we_n <= 1'd1; + end +// synthesis translate_off + dummy_d_115 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_116; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p2_cas_n <= 1'd1; + if (soc_sdram_phaseinjector2_command_issue_re) begin + soc_sdram_inti_p2_cas_n <= (~soc_sdram_phaseinjector2_command_storage[2]); + end else begin + soc_sdram_inti_p2_cas_n <= 1'd1; + end +// synthesis translate_off + dummy_d_116 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_117; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p2_cs_n <= 1'd1; + if (soc_sdram_phaseinjector2_command_issue_re) begin + soc_sdram_inti_p2_cs_n <= {1{(~soc_sdram_phaseinjector2_command_storage[0])}}; + end else begin + soc_sdram_inti_p2_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_117 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_118; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p2_ras_n <= 1'd1; + if (soc_sdram_phaseinjector2_command_issue_re) begin + soc_sdram_inti_p2_ras_n <= (~soc_sdram_phaseinjector2_command_storage[3]); + end else begin + soc_sdram_inti_p2_ras_n <= 1'd1; + end +// synthesis translate_off + dummy_d_118 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_inti_p2_address = soc_sdram_phaseinjector2_address_storage; +assign soc_sdram_inti_p2_bank = soc_sdram_phaseinjector2_baddress_storage; +assign soc_sdram_inti_p2_wrdata_en = (soc_sdram_phaseinjector2_command_issue_re & soc_sdram_phaseinjector2_command_storage[4]); +assign soc_sdram_inti_p2_rddata_en = (soc_sdram_phaseinjector2_command_issue_re & soc_sdram_phaseinjector2_command_storage[5]); +assign soc_sdram_inti_p2_wrdata = soc_sdram_phaseinjector2_wrdata_storage; +assign soc_sdram_inti_p2_wrdata_mask = 1'd0; + +// synthesis translate_off +reg dummy_d_119; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p3_we_n <= 1'd1; + if (soc_sdram_phaseinjector3_command_issue_re) begin + soc_sdram_inti_p3_we_n <= (~soc_sdram_phaseinjector3_command_storage[1]); + end else begin + soc_sdram_inti_p3_we_n <= 1'd1; + end +// synthesis translate_off + dummy_d_119 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_120; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p3_cas_n <= 1'd1; + if (soc_sdram_phaseinjector3_command_issue_re) begin + soc_sdram_inti_p3_cas_n <= (~soc_sdram_phaseinjector3_command_storage[2]); + end else begin + soc_sdram_inti_p3_cas_n <= 1'd1; + end +// synthesis translate_off + dummy_d_120 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_121; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p3_cs_n <= 1'd1; + if (soc_sdram_phaseinjector3_command_issue_re) begin + soc_sdram_inti_p3_cs_n <= {1{(~soc_sdram_phaseinjector3_command_storage[0])}}; + end else begin + soc_sdram_inti_p3_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_121 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_122; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p3_ras_n <= 1'd1; + if (soc_sdram_phaseinjector3_command_issue_re) begin + soc_sdram_inti_p3_ras_n <= (~soc_sdram_phaseinjector3_command_storage[3]); + end else begin + soc_sdram_inti_p3_ras_n <= 1'd1; + end +// synthesis translate_off + dummy_d_122 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_inti_p3_address = soc_sdram_phaseinjector3_address_storage; +assign soc_sdram_inti_p3_bank = soc_sdram_phaseinjector3_baddress_storage; +assign soc_sdram_inti_p3_wrdata_en = (soc_sdram_phaseinjector3_command_issue_re & soc_sdram_phaseinjector3_command_storage[4]); +assign soc_sdram_inti_p3_rddata_en = (soc_sdram_phaseinjector3_command_issue_re & soc_sdram_phaseinjector3_command_storage[5]); +assign soc_sdram_inti_p3_wrdata = soc_sdram_phaseinjector3_wrdata_storage; +assign soc_sdram_inti_p3_wrdata_mask = 1'd0; +assign soc_sdram_bankmachine0_req_valid = soc_sdram_interface_bank0_valid; +assign soc_sdram_interface_bank0_ready = soc_sdram_bankmachine0_req_ready; +assign soc_sdram_bankmachine0_req_we = soc_sdram_interface_bank0_we; +assign soc_sdram_bankmachine0_req_addr = soc_sdram_interface_bank0_addr; +assign soc_sdram_interface_bank0_lock = soc_sdram_bankmachine0_req_lock; +assign soc_sdram_interface_bank0_wdata_ready = soc_sdram_bankmachine0_req_wdata_ready; +assign soc_sdram_interface_bank0_rdata_valid = soc_sdram_bankmachine0_req_rdata_valid; +assign soc_sdram_bankmachine1_req_valid = soc_sdram_interface_bank1_valid; +assign soc_sdram_interface_bank1_ready = soc_sdram_bankmachine1_req_ready; +assign soc_sdram_bankmachine1_req_we = soc_sdram_interface_bank1_we; +assign soc_sdram_bankmachine1_req_addr = soc_sdram_interface_bank1_addr; +assign soc_sdram_interface_bank1_lock = soc_sdram_bankmachine1_req_lock; +assign soc_sdram_interface_bank1_wdata_ready = soc_sdram_bankmachine1_req_wdata_ready; +assign soc_sdram_interface_bank1_rdata_valid = soc_sdram_bankmachine1_req_rdata_valid; +assign soc_sdram_bankmachine2_req_valid = soc_sdram_interface_bank2_valid; +assign soc_sdram_interface_bank2_ready = soc_sdram_bankmachine2_req_ready; +assign soc_sdram_bankmachine2_req_we = soc_sdram_interface_bank2_we; +assign soc_sdram_bankmachine2_req_addr = soc_sdram_interface_bank2_addr; +assign soc_sdram_interface_bank2_lock = soc_sdram_bankmachine2_req_lock; +assign soc_sdram_interface_bank2_wdata_ready = soc_sdram_bankmachine2_req_wdata_ready; +assign soc_sdram_interface_bank2_rdata_valid = soc_sdram_bankmachine2_req_rdata_valid; +assign soc_sdram_bankmachine3_req_valid = soc_sdram_interface_bank3_valid; +assign soc_sdram_interface_bank3_ready = soc_sdram_bankmachine3_req_ready; +assign soc_sdram_bankmachine3_req_we = soc_sdram_interface_bank3_we; +assign soc_sdram_bankmachine3_req_addr = soc_sdram_interface_bank3_addr; +assign soc_sdram_interface_bank3_lock = soc_sdram_bankmachine3_req_lock; +assign soc_sdram_interface_bank3_wdata_ready = soc_sdram_bankmachine3_req_wdata_ready; +assign soc_sdram_interface_bank3_rdata_valid = soc_sdram_bankmachine3_req_rdata_valid; +assign soc_sdram_bankmachine4_req_valid = soc_sdram_interface_bank4_valid; +assign soc_sdram_interface_bank4_ready = soc_sdram_bankmachine4_req_ready; +assign soc_sdram_bankmachine4_req_we = soc_sdram_interface_bank4_we; +assign soc_sdram_bankmachine4_req_addr = soc_sdram_interface_bank4_addr; +assign soc_sdram_interface_bank4_lock = soc_sdram_bankmachine4_req_lock; +assign soc_sdram_interface_bank4_wdata_ready = soc_sdram_bankmachine4_req_wdata_ready; +assign soc_sdram_interface_bank4_rdata_valid = soc_sdram_bankmachine4_req_rdata_valid; +assign soc_sdram_bankmachine5_req_valid = soc_sdram_interface_bank5_valid; +assign soc_sdram_interface_bank5_ready = soc_sdram_bankmachine5_req_ready; +assign soc_sdram_bankmachine5_req_we = soc_sdram_interface_bank5_we; +assign soc_sdram_bankmachine5_req_addr = soc_sdram_interface_bank5_addr; +assign soc_sdram_interface_bank5_lock = soc_sdram_bankmachine5_req_lock; +assign soc_sdram_interface_bank5_wdata_ready = soc_sdram_bankmachine5_req_wdata_ready; +assign soc_sdram_interface_bank5_rdata_valid = soc_sdram_bankmachine5_req_rdata_valid; +assign soc_sdram_bankmachine6_req_valid = soc_sdram_interface_bank6_valid; +assign soc_sdram_interface_bank6_ready = soc_sdram_bankmachine6_req_ready; +assign soc_sdram_bankmachine6_req_we = soc_sdram_interface_bank6_we; +assign soc_sdram_bankmachine6_req_addr = soc_sdram_interface_bank6_addr; +assign soc_sdram_interface_bank6_lock = soc_sdram_bankmachine6_req_lock; +assign soc_sdram_interface_bank6_wdata_ready = soc_sdram_bankmachine6_req_wdata_ready; +assign soc_sdram_interface_bank6_rdata_valid = soc_sdram_bankmachine6_req_rdata_valid; +assign soc_sdram_bankmachine7_req_valid = soc_sdram_interface_bank7_valid; +assign soc_sdram_interface_bank7_ready = soc_sdram_bankmachine7_req_ready; +assign soc_sdram_bankmachine7_req_we = soc_sdram_interface_bank7_we; +assign soc_sdram_bankmachine7_req_addr = soc_sdram_interface_bank7_addr; +assign soc_sdram_interface_bank7_lock = soc_sdram_bankmachine7_req_lock; +assign soc_sdram_interface_bank7_wdata_ready = soc_sdram_bankmachine7_req_wdata_ready; +assign soc_sdram_interface_bank7_rdata_valid = soc_sdram_bankmachine7_req_rdata_valid; +assign soc_sdram_timer_wait = (~soc_sdram_timer_done0); +assign soc_sdram_postponer_req_i = soc_sdram_timer_done0; +assign soc_sdram_wants_refresh = soc_sdram_postponer_req_o; +assign soc_sdram_wants_zqcs = soc_sdram_zqcs_timer_done0; +assign soc_sdram_zqcs_timer_wait = (~soc_sdram_zqcs_executer_done); +assign soc_sdram_timer_done1 = (soc_sdram_timer_count1 == 1'd0); +assign soc_sdram_timer_done0 = soc_sdram_timer_done1; +assign soc_sdram_timer_count0 = soc_sdram_timer_count1; +assign soc_sdram_sequencer_start1 = (soc_sdram_sequencer_start0 | (soc_sdram_sequencer_count != 1'd0)); +assign soc_sdram_sequencer_done0 = (soc_sdram_sequencer_done1 & (soc_sdram_sequencer_count == 1'd0)); +assign soc_sdram_zqcs_timer_done1 = (soc_sdram_zqcs_timer_count1 == 1'd0); +assign soc_sdram_zqcs_timer_done0 = soc_sdram_zqcs_timer_done1; +assign soc_sdram_zqcs_timer_count0 = soc_sdram_zqcs_timer_count1; + +// synthesis translate_off +reg dummy_d_123; +// synthesis translate_on +always @(*) begin + vns_refresher_next_state <= 2'd0; + vns_refresher_next_state <= vns_refresher_state; + case (vns_refresher_state) + 1'd1: begin + if (soc_sdram_cmd_ready) begin + vns_refresher_next_state <= 2'd2; + end + end + 2'd2: begin + if (soc_sdram_sequencer_done0) begin + if (soc_sdram_wants_zqcs) begin + vns_refresher_next_state <= 2'd3; + end else begin + vns_refresher_next_state <= 1'd0; + end + end + end + 2'd3: begin + if (soc_sdram_zqcs_executer_done) begin + vns_refresher_next_state <= 1'd0; + end + end + default: begin + if (1'd1) begin + if (soc_sdram_wants_refresh) begin + vns_refresher_next_state <= 1'd1; + end + end + end + endcase +// synthesis translate_off + dummy_d_123 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_124; +// synthesis translate_on +always @(*) begin + soc_sdram_sequencer_start0 <= 1'd0; + case (vns_refresher_state) + 1'd1: begin + if (soc_sdram_cmd_ready) begin + soc_sdram_sequencer_start0 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_124 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_125; +// synthesis translate_on +always @(*) begin + soc_sdram_cmd_valid <= 1'd0; + case (vns_refresher_state) + 1'd1: begin + soc_sdram_cmd_valid <= 1'd1; + end + 2'd2: begin + soc_sdram_cmd_valid <= 1'd1; + if (soc_sdram_sequencer_done0) begin + if (soc_sdram_wants_zqcs) begin + end else begin + soc_sdram_cmd_valid <= 1'd0; + end + end + end + 2'd3: begin + soc_sdram_cmd_valid <= 1'd1; + if (soc_sdram_zqcs_executer_done) begin + soc_sdram_cmd_valid <= 1'd0; + end + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_125 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_126; +// synthesis translate_on +always @(*) begin + soc_sdram_zqcs_executer_start <= 1'd0; + case (vns_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (soc_sdram_sequencer_done0) begin + if (soc_sdram_wants_zqcs) begin + soc_sdram_zqcs_executer_start <= 1'd1; + end else begin + end + end + end + 2'd3: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_126 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_127; +// synthesis translate_on +always @(*) begin + soc_sdram_cmd_last <= 1'd0; + case (vns_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (soc_sdram_sequencer_done0) begin + if (soc_sdram_wants_zqcs) begin + end else begin + soc_sdram_cmd_last <= 1'd1; + end + end + end + 2'd3: begin + if (soc_sdram_zqcs_executer_done) begin + soc_sdram_cmd_last <= 1'd1; + end + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_127 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine0_req_valid; +assign soc_sdram_bankmachine0_req_ready = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine0_req_we; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine0_req_addr; +assign soc_sdram_bankmachine0_cmd_buffer_sink_valid = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine0_cmd_buffer_sink_ready; +assign soc_sdram_bankmachine0_cmd_buffer_sink_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first; +assign soc_sdram_bankmachine0_cmd_buffer_sink_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last; +assign soc_sdram_bankmachine0_cmd_buffer_sink_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we; +assign soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +assign soc_sdram_bankmachine0_cmd_buffer_source_ready = (soc_sdram_bankmachine0_req_wdata_ready | soc_sdram_bankmachine0_req_rdata_valid); +assign soc_sdram_bankmachine0_req_lock = (soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine0_cmd_buffer_source_valid); +assign soc_sdram_bankmachine0_row_hit = (soc_sdram_bankmachine0_row == soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]); +assign soc_sdram_bankmachine0_cmd_payload_ba = 1'd0; + +// synthesis translate_off +reg dummy_d_128; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_cmd_payload_a <= 14'd0; + if (soc_sdram_bankmachine0_row_col_n_addr_sel) begin + soc_sdram_bankmachine0_cmd_payload_a <= soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]; + end else begin + soc_sdram_bankmachine0_cmd_payload_a <= ((soc_sdram_bankmachine0_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_128 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine0_twtpcon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_cmd_payload_is_write); +assign soc_sdram_bankmachine0_trccon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_row_open); +assign soc_sdram_bankmachine0_trascon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_row_open); + +// synthesis translate_off +reg dummy_d_129; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_auto_precharge <= 1'd0; + if ((soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine0_cmd_buffer_source_valid)) begin + if ((soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin + soc_sdram_bankmachine0_auto_precharge <= (soc_sdram_bankmachine0_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_129 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_first; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_last; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_130; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_sdram_bankmachine0_cmd_buffer_lookahead_replace) begin + soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine0_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_130 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_sdram_bankmachine0_cmd_buffer_lookahead_replace)); +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine0_cmd_buffer_lookahead_consume; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_sdram_bankmachine0_cmd_buffer_lookahead_level != 5'd16); +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0); +assign soc_sdram_bankmachine0_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine0_cmd_buffer_source_valid) | soc_sdram_bankmachine0_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_131; +// synthesis translate_on +always @(*) begin + vns_bankmachine0_next_state <= 4'd0; + vns_bankmachine0_next_state <= vns_bankmachine0_state; + case (vns_bankmachine0_state) + 1'd1: begin + if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin + if (soc_sdram_bankmachine0_cmd_ready) begin + vns_bankmachine0_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin + vns_bankmachine0_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_sdram_bankmachine0_trccon_ready) begin + if (soc_sdram_bankmachine0_cmd_ready) begin + vns_bankmachine0_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_sdram_bankmachine0_refresh_req)) begin + vns_bankmachine0_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine0_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine0_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine0_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine0_next_state <= 1'd0; + end + default: begin + if (soc_sdram_bankmachine0_refresh_req) begin + vns_bankmachine0_next_state <= 3'd4; + end else begin + if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine0_row_opened) begin + if (soc_sdram_bankmachine0_row_hit) begin + if ((soc_sdram_bankmachine0_cmd_ready & soc_sdram_bankmachine0_auto_precharge)) begin + vns_bankmachine0_next_state <= 2'd2; + end + end else begin + vns_bankmachine0_next_state <= 1'd1; + end + end else begin + vns_bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_131 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_132; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_cmd_payload_we <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin + soc_sdram_bankmachine0_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine0_refresh_req) begin + end else begin + if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine0_row_opened) begin + if (soc_sdram_bankmachine0_row_hit) begin + if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_132 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_133; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine0_trccon_ready) begin + soc_sdram_bankmachine0_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_133 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_134; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin + soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine0_trccon_ready) begin + soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_134 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_135; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine0_refresh_req) begin + end else begin + if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine0_row_opened) begin + if (soc_sdram_bankmachine0_row_hit) begin + if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine0_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_135 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_136; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine0_refresh_req) begin + end else begin + if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine0_row_opened) begin + if (soc_sdram_bankmachine0_row_hit) begin + if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_136 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_137; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_req_wdata_ready <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine0_refresh_req) begin + end else begin + if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine0_row_opened) begin + if (soc_sdram_bankmachine0_row_hit) begin + if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine0_req_wdata_ready <= soc_sdram_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_137 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_138; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_req_rdata_valid <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine0_refresh_req) begin + end else begin + if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine0_row_opened) begin + if (soc_sdram_bankmachine0_row_hit) begin + if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine0_req_rdata_valid <= soc_sdram_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_138 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_139; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_refresh_gnt <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_sdram_bankmachine0_twtpcon_ready) begin + soc_sdram_bankmachine0_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_139 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_140; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_cmd_valid <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin + soc_sdram_bankmachine0_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine0_trccon_ready) begin + soc_sdram_bankmachine0_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine0_refresh_req) begin + end else begin + if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine0_row_opened) begin + if (soc_sdram_bankmachine0_row_hit) begin + soc_sdram_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_140 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_141; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_row_open <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine0_trccon_ready) begin + soc_sdram_bankmachine0_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_141 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_142; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_row_close <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + soc_sdram_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + soc_sdram_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_sdram_bankmachine0_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_142 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_143; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_cmd_payload_cas <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine0_refresh_req) begin + end else begin + if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine0_row_opened) begin + if (soc_sdram_bankmachine0_row_hit) begin + soc_sdram_bankmachine0_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_143 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_144; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_cmd_payload_ras <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin + soc_sdram_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine0_trccon_ready) begin + soc_sdram_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_144 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine1_req_valid; +assign soc_sdram_bankmachine1_req_ready = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine1_req_we; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine1_req_addr; +assign soc_sdram_bankmachine1_cmd_buffer_sink_valid = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine1_cmd_buffer_sink_ready; +assign soc_sdram_bankmachine1_cmd_buffer_sink_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first; +assign soc_sdram_bankmachine1_cmd_buffer_sink_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last; +assign soc_sdram_bankmachine1_cmd_buffer_sink_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we; +assign soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +assign soc_sdram_bankmachine1_cmd_buffer_source_ready = (soc_sdram_bankmachine1_req_wdata_ready | soc_sdram_bankmachine1_req_rdata_valid); +assign soc_sdram_bankmachine1_req_lock = (soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine1_cmd_buffer_source_valid); +assign soc_sdram_bankmachine1_row_hit = (soc_sdram_bankmachine1_row == soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]); +assign soc_sdram_bankmachine1_cmd_payload_ba = 1'd1; + +// synthesis translate_off +reg dummy_d_145; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_cmd_payload_a <= 14'd0; + if (soc_sdram_bankmachine1_row_col_n_addr_sel) begin + soc_sdram_bankmachine1_cmd_payload_a <= soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]; + end else begin + soc_sdram_bankmachine1_cmd_payload_a <= ((soc_sdram_bankmachine1_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_145 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine1_twtpcon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_cmd_payload_is_write); +assign soc_sdram_bankmachine1_trccon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_row_open); +assign soc_sdram_bankmachine1_trascon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_row_open); + +// synthesis translate_off +reg dummy_d_146; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_auto_precharge <= 1'd0; + if ((soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine1_cmd_buffer_source_valid)) begin + if ((soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin + soc_sdram_bankmachine1_auto_precharge <= (soc_sdram_bankmachine1_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_146 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_first; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_last; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_147; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_sdram_bankmachine1_cmd_buffer_lookahead_replace) begin + soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine1_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_147 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_sdram_bankmachine1_cmd_buffer_lookahead_replace)); +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine1_cmd_buffer_lookahead_consume; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_sdram_bankmachine1_cmd_buffer_lookahead_level != 5'd16); +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0); +assign soc_sdram_bankmachine1_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine1_cmd_buffer_source_valid) | soc_sdram_bankmachine1_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_148; +// synthesis translate_on +always @(*) begin + vns_bankmachine1_next_state <= 4'd0; + vns_bankmachine1_next_state <= vns_bankmachine1_state; + case (vns_bankmachine1_state) + 1'd1: begin + if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin + if (soc_sdram_bankmachine1_cmd_ready) begin + vns_bankmachine1_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin + vns_bankmachine1_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_sdram_bankmachine1_trccon_ready) begin + if (soc_sdram_bankmachine1_cmd_ready) begin + vns_bankmachine1_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_sdram_bankmachine1_refresh_req)) begin + vns_bankmachine1_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine1_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine1_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine1_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine1_next_state <= 1'd0; + end + default: begin + if (soc_sdram_bankmachine1_refresh_req) begin + vns_bankmachine1_next_state <= 3'd4; + end else begin + if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine1_row_opened) begin + if (soc_sdram_bankmachine1_row_hit) begin + if ((soc_sdram_bankmachine1_cmd_ready & soc_sdram_bankmachine1_auto_precharge)) begin + vns_bankmachine1_next_state <= 2'd2; + end + end else begin + vns_bankmachine1_next_state <= 1'd1; + end + end else begin + vns_bankmachine1_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_148 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_149; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_cmd_payload_we <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin + soc_sdram_bankmachine1_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine1_refresh_req) begin + end else begin + if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine1_row_opened) begin + if (soc_sdram_bankmachine1_row_hit) begin + if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_149 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_150; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine1_trccon_ready) begin + soc_sdram_bankmachine1_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_150 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_151; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin + soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine1_trccon_ready) begin + soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_151 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_152; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine1_refresh_req) begin + end else begin + if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine1_row_opened) begin + if (soc_sdram_bankmachine1_row_hit) begin + if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine1_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_152 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_153; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine1_refresh_req) begin + end else begin + if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine1_row_opened) begin + if (soc_sdram_bankmachine1_row_hit) begin + if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_153 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_154; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_req_wdata_ready <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine1_refresh_req) begin + end else begin + if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine1_row_opened) begin + if (soc_sdram_bankmachine1_row_hit) begin + if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine1_req_wdata_ready <= soc_sdram_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_154 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_155; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_req_rdata_valid <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine1_refresh_req) begin + end else begin + if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine1_row_opened) begin + if (soc_sdram_bankmachine1_row_hit) begin + if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine1_req_rdata_valid <= soc_sdram_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_155 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_156; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_refresh_gnt <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_sdram_bankmachine1_twtpcon_ready) begin + soc_sdram_bankmachine1_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_156 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_157; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_cmd_valid <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin + soc_sdram_bankmachine1_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine1_trccon_ready) begin + soc_sdram_bankmachine1_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine1_refresh_req) begin + end else begin + if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine1_row_opened) begin + if (soc_sdram_bankmachine1_row_hit) begin + soc_sdram_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_157 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_158; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_row_open <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine1_trccon_ready) begin + soc_sdram_bankmachine1_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_158 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_159; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_row_close <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + soc_sdram_bankmachine1_row_close <= 1'd1; + end + 2'd2: begin + soc_sdram_bankmachine1_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_sdram_bankmachine1_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_159 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_160; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_cmd_payload_cas <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine1_refresh_req) begin + end else begin + if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine1_row_opened) begin + if (soc_sdram_bankmachine1_row_hit) begin + soc_sdram_bankmachine1_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_160 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_161; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_cmd_payload_ras <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin + soc_sdram_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine1_trccon_ready) begin + soc_sdram_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_161 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine2_req_valid; +assign soc_sdram_bankmachine2_req_ready = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine2_req_we; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine2_req_addr; +assign soc_sdram_bankmachine2_cmd_buffer_sink_valid = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine2_cmd_buffer_sink_ready; +assign soc_sdram_bankmachine2_cmd_buffer_sink_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first; +assign soc_sdram_bankmachine2_cmd_buffer_sink_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last; +assign soc_sdram_bankmachine2_cmd_buffer_sink_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we; +assign soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +assign soc_sdram_bankmachine2_cmd_buffer_source_ready = (soc_sdram_bankmachine2_req_wdata_ready | soc_sdram_bankmachine2_req_rdata_valid); +assign soc_sdram_bankmachine2_req_lock = (soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine2_cmd_buffer_source_valid); +assign soc_sdram_bankmachine2_row_hit = (soc_sdram_bankmachine2_row == soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]); +assign soc_sdram_bankmachine2_cmd_payload_ba = 2'd2; + +// synthesis translate_off +reg dummy_d_162; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_cmd_payload_a <= 14'd0; + if (soc_sdram_bankmachine2_row_col_n_addr_sel) begin + soc_sdram_bankmachine2_cmd_payload_a <= soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]; + end else begin + soc_sdram_bankmachine2_cmd_payload_a <= ((soc_sdram_bankmachine2_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_162 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine2_twtpcon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_cmd_payload_is_write); +assign soc_sdram_bankmachine2_trccon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_row_open); +assign soc_sdram_bankmachine2_trascon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_row_open); + +// synthesis translate_off +reg dummy_d_163; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_auto_precharge <= 1'd0; + if ((soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine2_cmd_buffer_source_valid)) begin + if ((soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin + soc_sdram_bankmachine2_auto_precharge <= (soc_sdram_bankmachine2_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_163 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_first; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_last; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_164; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_sdram_bankmachine2_cmd_buffer_lookahead_replace) begin + soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine2_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_164 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_sdram_bankmachine2_cmd_buffer_lookahead_replace)); +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine2_cmd_buffer_lookahead_consume; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_sdram_bankmachine2_cmd_buffer_lookahead_level != 5'd16); +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0); +assign soc_sdram_bankmachine2_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine2_cmd_buffer_source_valid) | soc_sdram_bankmachine2_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_165; +// synthesis translate_on +always @(*) begin + vns_bankmachine2_next_state <= 4'd0; + vns_bankmachine2_next_state <= vns_bankmachine2_state; + case (vns_bankmachine2_state) + 1'd1: begin + if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin + if (soc_sdram_bankmachine2_cmd_ready) begin + vns_bankmachine2_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin + vns_bankmachine2_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_sdram_bankmachine2_trccon_ready) begin + if (soc_sdram_bankmachine2_cmd_ready) begin + vns_bankmachine2_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_sdram_bankmachine2_refresh_req)) begin + vns_bankmachine2_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine2_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine2_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine2_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine2_next_state <= 1'd0; + end + default: begin + if (soc_sdram_bankmachine2_refresh_req) begin + vns_bankmachine2_next_state <= 3'd4; + end else begin + if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine2_row_opened) begin + if (soc_sdram_bankmachine2_row_hit) begin + if ((soc_sdram_bankmachine2_cmd_ready & soc_sdram_bankmachine2_auto_precharge)) begin + vns_bankmachine2_next_state <= 2'd2; + end + end else begin + vns_bankmachine2_next_state <= 1'd1; + end + end else begin + vns_bankmachine2_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_165 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_166; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_cmd_payload_we <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin + soc_sdram_bankmachine2_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine2_refresh_req) begin + end else begin + if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine2_row_opened) begin + if (soc_sdram_bankmachine2_row_hit) begin + if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_166 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_167; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine2_trccon_ready) begin + soc_sdram_bankmachine2_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_167 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_168; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin + soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine2_trccon_ready) begin + soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_168 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_169; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine2_refresh_req) begin + end else begin + if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine2_row_opened) begin + if (soc_sdram_bankmachine2_row_hit) begin + if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine2_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_169 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_170; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine2_refresh_req) begin + end else begin + if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine2_row_opened) begin + if (soc_sdram_bankmachine2_row_hit) begin + if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine2_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_170 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_171; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_req_wdata_ready <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine2_refresh_req) begin + end else begin + if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine2_row_opened) begin + if (soc_sdram_bankmachine2_row_hit) begin + if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine2_req_wdata_ready <= soc_sdram_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_171 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_172; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_req_rdata_valid <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine2_refresh_req) begin + end else begin + if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine2_row_opened) begin + if (soc_sdram_bankmachine2_row_hit) begin + if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine2_req_rdata_valid <= soc_sdram_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_172 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_173; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_refresh_gnt <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_sdram_bankmachine2_twtpcon_ready) begin + soc_sdram_bankmachine2_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_173 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_174; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_cmd_valid <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin + soc_sdram_bankmachine2_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine2_trccon_ready) begin + soc_sdram_bankmachine2_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine2_refresh_req) begin + end else begin + if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine2_row_opened) begin + if (soc_sdram_bankmachine2_row_hit) begin + soc_sdram_bankmachine2_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_174 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_175; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_row_open <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine2_trccon_ready) begin + soc_sdram_bankmachine2_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_175 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_176; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_row_close <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + soc_sdram_bankmachine2_row_close <= 1'd1; + end + 2'd2: begin + soc_sdram_bankmachine2_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_sdram_bankmachine2_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_176 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_177; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_cmd_payload_cas <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine2_refresh_req) begin + end else begin + if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine2_row_opened) begin + if (soc_sdram_bankmachine2_row_hit) begin + soc_sdram_bankmachine2_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_177 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_178; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_cmd_payload_ras <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin + soc_sdram_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine2_trccon_ready) begin + soc_sdram_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_178 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine3_req_valid; +assign soc_sdram_bankmachine3_req_ready = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine3_req_we; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine3_req_addr; +assign soc_sdram_bankmachine3_cmd_buffer_sink_valid = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine3_cmd_buffer_sink_ready; +assign soc_sdram_bankmachine3_cmd_buffer_sink_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first; +assign soc_sdram_bankmachine3_cmd_buffer_sink_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last; +assign soc_sdram_bankmachine3_cmd_buffer_sink_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we; +assign soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +assign soc_sdram_bankmachine3_cmd_buffer_source_ready = (soc_sdram_bankmachine3_req_wdata_ready | soc_sdram_bankmachine3_req_rdata_valid); +assign soc_sdram_bankmachine3_req_lock = (soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine3_cmd_buffer_source_valid); +assign soc_sdram_bankmachine3_row_hit = (soc_sdram_bankmachine3_row == soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]); +assign soc_sdram_bankmachine3_cmd_payload_ba = 2'd3; + +// synthesis translate_off +reg dummy_d_179; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_cmd_payload_a <= 14'd0; + if (soc_sdram_bankmachine3_row_col_n_addr_sel) begin + soc_sdram_bankmachine3_cmd_payload_a <= soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]; + end else begin + soc_sdram_bankmachine3_cmd_payload_a <= ((soc_sdram_bankmachine3_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_179 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine3_twtpcon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_cmd_payload_is_write); +assign soc_sdram_bankmachine3_trccon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_row_open); +assign soc_sdram_bankmachine3_trascon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_row_open); + +// synthesis translate_off +reg dummy_d_180; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_auto_precharge <= 1'd0; + if ((soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine3_cmd_buffer_source_valid)) begin + if ((soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin + soc_sdram_bankmachine3_auto_precharge <= (soc_sdram_bankmachine3_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_180 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_first; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_last; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_181; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_sdram_bankmachine3_cmd_buffer_lookahead_replace) begin + soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine3_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_181 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_sdram_bankmachine3_cmd_buffer_lookahead_replace)); +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine3_cmd_buffer_lookahead_consume; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_sdram_bankmachine3_cmd_buffer_lookahead_level != 5'd16); +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0); +assign soc_sdram_bankmachine3_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine3_cmd_buffer_source_valid) | soc_sdram_bankmachine3_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_182; +// synthesis translate_on +always @(*) begin + vns_bankmachine3_next_state <= 4'd0; + vns_bankmachine3_next_state <= vns_bankmachine3_state; + case (vns_bankmachine3_state) + 1'd1: begin + if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin + if (soc_sdram_bankmachine3_cmd_ready) begin + vns_bankmachine3_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin + vns_bankmachine3_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_sdram_bankmachine3_trccon_ready) begin + if (soc_sdram_bankmachine3_cmd_ready) begin + vns_bankmachine3_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_sdram_bankmachine3_refresh_req)) begin + vns_bankmachine3_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine3_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine3_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine3_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine3_next_state <= 1'd0; + end + default: begin + if (soc_sdram_bankmachine3_refresh_req) begin + vns_bankmachine3_next_state <= 3'd4; + end else begin + if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine3_row_opened) begin + if (soc_sdram_bankmachine3_row_hit) begin + if ((soc_sdram_bankmachine3_cmd_ready & soc_sdram_bankmachine3_auto_precharge)) begin + vns_bankmachine3_next_state <= 2'd2; + end + end else begin + vns_bankmachine3_next_state <= 1'd1; + end + end else begin + vns_bankmachine3_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_182 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_183; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_cmd_payload_we <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin + soc_sdram_bankmachine3_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine3_refresh_req) begin + end else begin + if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine3_row_opened) begin + if (soc_sdram_bankmachine3_row_hit) begin + if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_183 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_184; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine3_trccon_ready) begin + soc_sdram_bankmachine3_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_184 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_185; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin + soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine3_trccon_ready) begin + soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_185 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_186; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine3_refresh_req) begin + end else begin + if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine3_row_opened) begin + if (soc_sdram_bankmachine3_row_hit) begin + if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine3_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_186 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_187; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine3_refresh_req) begin + end else begin + if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine3_row_opened) begin + if (soc_sdram_bankmachine3_row_hit) begin + if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine3_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_187 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_188; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_req_wdata_ready <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine3_refresh_req) begin + end else begin + if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine3_row_opened) begin + if (soc_sdram_bankmachine3_row_hit) begin + if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine3_req_wdata_ready <= soc_sdram_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_188 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_189; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_req_rdata_valid <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine3_refresh_req) begin + end else begin + if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine3_row_opened) begin + if (soc_sdram_bankmachine3_row_hit) begin + if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine3_req_rdata_valid <= soc_sdram_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_189 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_190; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_refresh_gnt <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_sdram_bankmachine3_twtpcon_ready) begin + soc_sdram_bankmachine3_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_190 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_191; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_cmd_valid <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin + soc_sdram_bankmachine3_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine3_trccon_ready) begin + soc_sdram_bankmachine3_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine3_refresh_req) begin + end else begin + if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine3_row_opened) begin + if (soc_sdram_bankmachine3_row_hit) begin + soc_sdram_bankmachine3_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_191 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_192; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_row_open <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine3_trccon_ready) begin + soc_sdram_bankmachine3_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_192 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_193; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_row_close <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + soc_sdram_bankmachine3_row_close <= 1'd1; + end + 2'd2: begin + soc_sdram_bankmachine3_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_sdram_bankmachine3_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_193 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_194; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_cmd_payload_cas <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine3_refresh_req) begin + end else begin + if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine3_row_opened) begin + if (soc_sdram_bankmachine3_row_hit) begin + soc_sdram_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_194 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_195; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_cmd_payload_ras <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin + soc_sdram_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine3_trccon_ready) begin + soc_sdram_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_195 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine4_req_valid; +assign soc_sdram_bankmachine4_req_ready = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine4_req_we; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine4_req_addr; +assign soc_sdram_bankmachine4_cmd_buffer_sink_valid = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine4_cmd_buffer_sink_ready; +assign soc_sdram_bankmachine4_cmd_buffer_sink_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first; +assign soc_sdram_bankmachine4_cmd_buffer_sink_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last; +assign soc_sdram_bankmachine4_cmd_buffer_sink_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we; +assign soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +assign soc_sdram_bankmachine4_cmd_buffer_source_ready = (soc_sdram_bankmachine4_req_wdata_ready | soc_sdram_bankmachine4_req_rdata_valid); +assign soc_sdram_bankmachine4_req_lock = (soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine4_cmd_buffer_source_valid); +assign soc_sdram_bankmachine4_row_hit = (soc_sdram_bankmachine4_row == soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]); +assign soc_sdram_bankmachine4_cmd_payload_ba = 3'd4; + +// synthesis translate_off +reg dummy_d_196; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_cmd_payload_a <= 14'd0; + if (soc_sdram_bankmachine4_row_col_n_addr_sel) begin + soc_sdram_bankmachine4_cmd_payload_a <= soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]; + end else begin + soc_sdram_bankmachine4_cmd_payload_a <= ((soc_sdram_bankmachine4_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_196 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine4_twtpcon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_cmd_payload_is_write); +assign soc_sdram_bankmachine4_trccon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_row_open); +assign soc_sdram_bankmachine4_trascon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_row_open); + +// synthesis translate_off +reg dummy_d_197; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_auto_precharge <= 1'd0; + if ((soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine4_cmd_buffer_source_valid)) begin + if ((soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin + soc_sdram_bankmachine4_auto_precharge <= (soc_sdram_bankmachine4_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_197 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_first; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_last; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_198; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_sdram_bankmachine4_cmd_buffer_lookahead_replace) begin + soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine4_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_198 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_sdram_bankmachine4_cmd_buffer_lookahead_replace)); +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine4_cmd_buffer_lookahead_consume; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_sdram_bankmachine4_cmd_buffer_lookahead_level != 5'd16); +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_sdram_bankmachine4_cmd_buffer_lookahead_level != 1'd0); +assign soc_sdram_bankmachine4_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine4_cmd_buffer_source_valid) | soc_sdram_bankmachine4_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_199; +// synthesis translate_on +always @(*) begin + vns_bankmachine4_next_state <= 4'd0; + vns_bankmachine4_next_state <= vns_bankmachine4_state; + case (vns_bankmachine4_state) + 1'd1: begin + if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin + if (soc_sdram_bankmachine4_cmd_ready) begin + vns_bankmachine4_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin + vns_bankmachine4_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_sdram_bankmachine4_trccon_ready) begin + if (soc_sdram_bankmachine4_cmd_ready) begin + vns_bankmachine4_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_sdram_bankmachine4_refresh_req)) begin + vns_bankmachine4_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine4_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine4_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine4_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine4_next_state <= 1'd0; + end + default: begin + if (soc_sdram_bankmachine4_refresh_req) begin + vns_bankmachine4_next_state <= 3'd4; + end else begin + if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine4_row_opened) begin + if (soc_sdram_bankmachine4_row_hit) begin + if ((soc_sdram_bankmachine4_cmd_ready & soc_sdram_bankmachine4_auto_precharge)) begin + vns_bankmachine4_next_state <= 2'd2; + end + end else begin + vns_bankmachine4_next_state <= 1'd1; + end + end else begin + vns_bankmachine4_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_199 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_200; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_cmd_payload_we <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin + soc_sdram_bankmachine4_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine4_refresh_req) begin + end else begin + if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine4_row_opened) begin + if (soc_sdram_bankmachine4_row_hit) begin + if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_200 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_201; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine4_trccon_ready) begin + soc_sdram_bankmachine4_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_201 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_202; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin + soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine4_trccon_ready) begin + soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_202 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_203; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine4_refresh_req) begin + end else begin + if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine4_row_opened) begin + if (soc_sdram_bankmachine4_row_hit) begin + if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine4_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_203 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_204; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine4_refresh_req) begin + end else begin + if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine4_row_opened) begin + if (soc_sdram_bankmachine4_row_hit) begin + if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine4_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_204 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_205; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_req_wdata_ready <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine4_refresh_req) begin + end else begin + if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine4_row_opened) begin + if (soc_sdram_bankmachine4_row_hit) begin + if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine4_req_wdata_ready <= soc_sdram_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_205 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_206; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_req_rdata_valid <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine4_refresh_req) begin + end else begin + if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine4_row_opened) begin + if (soc_sdram_bankmachine4_row_hit) begin + if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine4_req_rdata_valid <= soc_sdram_bankmachine4_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_206 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_207; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_refresh_gnt <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_sdram_bankmachine4_twtpcon_ready) begin + soc_sdram_bankmachine4_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_207 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_208; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_cmd_valid <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin + soc_sdram_bankmachine4_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine4_trccon_ready) begin + soc_sdram_bankmachine4_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine4_refresh_req) begin + end else begin + if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine4_row_opened) begin + if (soc_sdram_bankmachine4_row_hit) begin + soc_sdram_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_208 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_209; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_row_open <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine4_trccon_ready) begin + soc_sdram_bankmachine4_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_209 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_210; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_row_close <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + soc_sdram_bankmachine4_row_close <= 1'd1; + end + 2'd2: begin + soc_sdram_bankmachine4_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_sdram_bankmachine4_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_210 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_211; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_cmd_payload_cas <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine4_refresh_req) begin + end else begin + if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine4_row_opened) begin + if (soc_sdram_bankmachine4_row_hit) begin + soc_sdram_bankmachine4_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_211 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_212; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_cmd_payload_ras <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin + soc_sdram_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine4_trccon_ready) begin + soc_sdram_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_212 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine5_req_valid; +assign soc_sdram_bankmachine5_req_ready = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine5_req_we; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine5_req_addr; +assign soc_sdram_bankmachine5_cmd_buffer_sink_valid = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine5_cmd_buffer_sink_ready; +assign soc_sdram_bankmachine5_cmd_buffer_sink_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first; +assign soc_sdram_bankmachine5_cmd_buffer_sink_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last; +assign soc_sdram_bankmachine5_cmd_buffer_sink_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we; +assign soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +assign soc_sdram_bankmachine5_cmd_buffer_source_ready = (soc_sdram_bankmachine5_req_wdata_ready | soc_sdram_bankmachine5_req_rdata_valid); +assign soc_sdram_bankmachine5_req_lock = (soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine5_cmd_buffer_source_valid); +assign soc_sdram_bankmachine5_row_hit = (soc_sdram_bankmachine5_row == soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]); +assign soc_sdram_bankmachine5_cmd_payload_ba = 3'd5; + +// synthesis translate_off +reg dummy_d_213; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_cmd_payload_a <= 14'd0; + if (soc_sdram_bankmachine5_row_col_n_addr_sel) begin + soc_sdram_bankmachine5_cmd_payload_a <= soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]; + end else begin + soc_sdram_bankmachine5_cmd_payload_a <= ((soc_sdram_bankmachine5_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_213 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine5_twtpcon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_cmd_payload_is_write); +assign soc_sdram_bankmachine5_trccon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_row_open); +assign soc_sdram_bankmachine5_trascon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_row_open); + +// synthesis translate_off +reg dummy_d_214; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_auto_precharge <= 1'd0; + if ((soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine5_cmd_buffer_source_valid)) begin + if ((soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin + soc_sdram_bankmachine5_auto_precharge <= (soc_sdram_bankmachine5_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_214 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_first; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_last; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_215; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_sdram_bankmachine5_cmd_buffer_lookahead_replace) begin + soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine5_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_215 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_sdram_bankmachine5_cmd_buffer_lookahead_replace)); +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine5_cmd_buffer_lookahead_consume; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_sdram_bankmachine5_cmd_buffer_lookahead_level != 5'd16); +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_sdram_bankmachine5_cmd_buffer_lookahead_level != 1'd0); +assign soc_sdram_bankmachine5_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine5_cmd_buffer_source_valid) | soc_sdram_bankmachine5_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_216; +// synthesis translate_on +always @(*) begin + vns_bankmachine5_next_state <= 4'd0; + vns_bankmachine5_next_state <= vns_bankmachine5_state; + case (vns_bankmachine5_state) + 1'd1: begin + if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin + if (soc_sdram_bankmachine5_cmd_ready) begin + vns_bankmachine5_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin + vns_bankmachine5_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_sdram_bankmachine5_trccon_ready) begin + if (soc_sdram_bankmachine5_cmd_ready) begin + vns_bankmachine5_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_sdram_bankmachine5_refresh_req)) begin + vns_bankmachine5_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine5_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine5_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine5_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine5_next_state <= 1'd0; + end + default: begin + if (soc_sdram_bankmachine5_refresh_req) begin + vns_bankmachine5_next_state <= 3'd4; + end else begin + if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine5_row_opened) begin + if (soc_sdram_bankmachine5_row_hit) begin + if ((soc_sdram_bankmachine5_cmd_ready & soc_sdram_bankmachine5_auto_precharge)) begin + vns_bankmachine5_next_state <= 2'd2; + end + end else begin + vns_bankmachine5_next_state <= 1'd1; + end + end else begin + vns_bankmachine5_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_216 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_217; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_cmd_payload_we <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin + soc_sdram_bankmachine5_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine5_refresh_req) begin + end else begin + if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine5_row_opened) begin + if (soc_sdram_bankmachine5_row_hit) begin + if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine5_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_217 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_218; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine5_trccon_ready) begin + soc_sdram_bankmachine5_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_218 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_219; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin + soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine5_trccon_ready) begin + soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_219 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_220; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine5_refresh_req) begin + end else begin + if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine5_row_opened) begin + if (soc_sdram_bankmachine5_row_hit) begin + if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine5_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_220 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_221; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine5_refresh_req) begin + end else begin + if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine5_row_opened) begin + if (soc_sdram_bankmachine5_row_hit) begin + if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine5_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_221 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_222; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_req_wdata_ready <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine5_refresh_req) begin + end else begin + if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine5_row_opened) begin + if (soc_sdram_bankmachine5_row_hit) begin + if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine5_req_wdata_ready <= soc_sdram_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_222 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_223; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_req_rdata_valid <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine5_refresh_req) begin + end else begin + if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine5_row_opened) begin + if (soc_sdram_bankmachine5_row_hit) begin + if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine5_req_rdata_valid <= soc_sdram_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_223 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_224; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_refresh_gnt <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_sdram_bankmachine5_twtpcon_ready) begin + soc_sdram_bankmachine5_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_224 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_225; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_cmd_valid <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin + soc_sdram_bankmachine5_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine5_trccon_ready) begin + soc_sdram_bankmachine5_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine5_refresh_req) begin + end else begin + if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine5_row_opened) begin + if (soc_sdram_bankmachine5_row_hit) begin + soc_sdram_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_225 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_226; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_row_open <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine5_trccon_ready) begin + soc_sdram_bankmachine5_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_226 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_227; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_row_close <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + soc_sdram_bankmachine5_row_close <= 1'd1; + end + 2'd2: begin + soc_sdram_bankmachine5_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_sdram_bankmachine5_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_227 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_228; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_cmd_payload_cas <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine5_refresh_req) begin + end else begin + if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine5_row_opened) begin + if (soc_sdram_bankmachine5_row_hit) begin + soc_sdram_bankmachine5_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_228 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_229; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_cmd_payload_ras <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin + soc_sdram_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine5_trccon_ready) begin + soc_sdram_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_229 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine6_req_valid; +assign soc_sdram_bankmachine6_req_ready = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine6_req_we; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine6_req_addr; +assign soc_sdram_bankmachine6_cmd_buffer_sink_valid = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine6_cmd_buffer_sink_ready; +assign soc_sdram_bankmachine6_cmd_buffer_sink_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first; +assign soc_sdram_bankmachine6_cmd_buffer_sink_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last; +assign soc_sdram_bankmachine6_cmd_buffer_sink_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we; +assign soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +assign soc_sdram_bankmachine6_cmd_buffer_source_ready = (soc_sdram_bankmachine6_req_wdata_ready | soc_sdram_bankmachine6_req_rdata_valid); +assign soc_sdram_bankmachine6_req_lock = (soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine6_cmd_buffer_source_valid); +assign soc_sdram_bankmachine6_row_hit = (soc_sdram_bankmachine6_row == soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]); +assign soc_sdram_bankmachine6_cmd_payload_ba = 3'd6; + +// synthesis translate_off +reg dummy_d_230; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_cmd_payload_a <= 14'd0; + if (soc_sdram_bankmachine6_row_col_n_addr_sel) begin + soc_sdram_bankmachine6_cmd_payload_a <= soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]; + end else begin + soc_sdram_bankmachine6_cmd_payload_a <= ((soc_sdram_bankmachine6_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_230 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine6_twtpcon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_cmd_payload_is_write); +assign soc_sdram_bankmachine6_trccon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_row_open); +assign soc_sdram_bankmachine6_trascon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_row_open); + +// synthesis translate_off +reg dummy_d_231; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_auto_precharge <= 1'd0; + if ((soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine6_cmd_buffer_source_valid)) begin + if ((soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin + soc_sdram_bankmachine6_auto_precharge <= (soc_sdram_bankmachine6_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_231 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_first; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_last; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_232; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_sdram_bankmachine6_cmd_buffer_lookahead_replace) begin + soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine6_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_232 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_sdram_bankmachine6_cmd_buffer_lookahead_replace)); +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine6_cmd_buffer_lookahead_consume; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_sdram_bankmachine6_cmd_buffer_lookahead_level != 5'd16); +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_sdram_bankmachine6_cmd_buffer_lookahead_level != 1'd0); +assign soc_sdram_bankmachine6_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine6_cmd_buffer_source_valid) | soc_sdram_bankmachine6_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_233; +// synthesis translate_on +always @(*) begin + vns_bankmachine6_next_state <= 4'd0; + vns_bankmachine6_next_state <= vns_bankmachine6_state; + case (vns_bankmachine6_state) + 1'd1: begin + if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin + if (soc_sdram_bankmachine6_cmd_ready) begin + vns_bankmachine6_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin + vns_bankmachine6_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_sdram_bankmachine6_trccon_ready) begin + if (soc_sdram_bankmachine6_cmd_ready) begin + vns_bankmachine6_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_sdram_bankmachine6_refresh_req)) begin + vns_bankmachine6_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine6_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine6_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine6_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine6_next_state <= 1'd0; + end + default: begin + if (soc_sdram_bankmachine6_refresh_req) begin + vns_bankmachine6_next_state <= 3'd4; + end else begin + if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine6_row_opened) begin + if (soc_sdram_bankmachine6_row_hit) begin + if ((soc_sdram_bankmachine6_cmd_ready & soc_sdram_bankmachine6_auto_precharge)) begin + vns_bankmachine6_next_state <= 2'd2; + end + end else begin + vns_bankmachine6_next_state <= 1'd1; + end + end else begin + vns_bankmachine6_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_233 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_234; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_cmd_payload_we <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin + soc_sdram_bankmachine6_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine6_refresh_req) begin + end else begin + if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine6_row_opened) begin + if (soc_sdram_bankmachine6_row_hit) begin + if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_234 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_235; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine6_trccon_ready) begin + soc_sdram_bankmachine6_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_235 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_236; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin + soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine6_trccon_ready) begin + soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_236 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_237; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine6_refresh_req) begin + end else begin + if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine6_row_opened) begin + if (soc_sdram_bankmachine6_row_hit) begin + if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine6_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_237 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_238; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine6_refresh_req) begin + end else begin + if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine6_row_opened) begin + if (soc_sdram_bankmachine6_row_hit) begin + if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_238 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_239; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_req_wdata_ready <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine6_refresh_req) begin + end else begin + if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine6_row_opened) begin + if (soc_sdram_bankmachine6_row_hit) begin + if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine6_req_wdata_ready <= soc_sdram_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_239 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_240; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_req_rdata_valid <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine6_refresh_req) begin + end else begin + if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine6_row_opened) begin + if (soc_sdram_bankmachine6_row_hit) begin + if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine6_req_rdata_valid <= soc_sdram_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_240 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_241; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_refresh_gnt <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_sdram_bankmachine6_twtpcon_ready) begin + soc_sdram_bankmachine6_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_241 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_242; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_cmd_valid <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin + soc_sdram_bankmachine6_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine6_trccon_ready) begin + soc_sdram_bankmachine6_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine6_refresh_req) begin + end else begin + if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine6_row_opened) begin + if (soc_sdram_bankmachine6_row_hit) begin + soc_sdram_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_242 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_243; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_row_open <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine6_trccon_ready) begin + soc_sdram_bankmachine6_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_243 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_244; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_row_close <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + soc_sdram_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + soc_sdram_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_sdram_bankmachine6_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_244 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_245; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_cmd_payload_cas <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine6_refresh_req) begin + end else begin + if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine6_row_opened) begin + if (soc_sdram_bankmachine6_row_hit) begin + soc_sdram_bankmachine6_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_245 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_246; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_cmd_payload_ras <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin + soc_sdram_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine6_trccon_ready) begin + soc_sdram_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_246 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine7_req_valid; +assign soc_sdram_bankmachine7_req_ready = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine7_req_we; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine7_req_addr; +assign soc_sdram_bankmachine7_cmd_buffer_sink_valid = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine7_cmd_buffer_sink_ready; +assign soc_sdram_bankmachine7_cmd_buffer_sink_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first; +assign soc_sdram_bankmachine7_cmd_buffer_sink_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last; +assign soc_sdram_bankmachine7_cmd_buffer_sink_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we; +assign soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +assign soc_sdram_bankmachine7_cmd_buffer_source_ready = (soc_sdram_bankmachine7_req_wdata_ready | soc_sdram_bankmachine7_req_rdata_valid); +assign soc_sdram_bankmachine7_req_lock = (soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine7_cmd_buffer_source_valid); +assign soc_sdram_bankmachine7_row_hit = (soc_sdram_bankmachine7_row == soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]); +assign soc_sdram_bankmachine7_cmd_payload_ba = 3'd7; + +// synthesis translate_off +reg dummy_d_247; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_cmd_payload_a <= 14'd0; + if (soc_sdram_bankmachine7_row_col_n_addr_sel) begin + soc_sdram_bankmachine7_cmd_payload_a <= soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]; + end else begin + soc_sdram_bankmachine7_cmd_payload_a <= ((soc_sdram_bankmachine7_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_247 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine7_twtpcon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_cmd_payload_is_write); +assign soc_sdram_bankmachine7_trccon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_row_open); +assign soc_sdram_bankmachine7_trascon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_row_open); + +// synthesis translate_off +reg dummy_d_248; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_auto_precharge <= 1'd0; + if ((soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine7_cmd_buffer_source_valid)) begin + if ((soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin + soc_sdram_bankmachine7_auto_precharge <= (soc_sdram_bankmachine7_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_248 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_first; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_last; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_249; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_sdram_bankmachine7_cmd_buffer_lookahead_replace) begin + soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine7_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_249 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_sdram_bankmachine7_cmd_buffer_lookahead_replace)); +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine7_cmd_buffer_lookahead_consume; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_sdram_bankmachine7_cmd_buffer_lookahead_level != 5'd16); +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_sdram_bankmachine7_cmd_buffer_lookahead_level != 1'd0); +assign soc_sdram_bankmachine7_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine7_cmd_buffer_source_valid) | soc_sdram_bankmachine7_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_250; +// synthesis translate_on +always @(*) begin + vns_bankmachine7_next_state <= 4'd0; + vns_bankmachine7_next_state <= vns_bankmachine7_state; + case (vns_bankmachine7_state) + 1'd1: begin + if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin + if (soc_sdram_bankmachine7_cmd_ready) begin + vns_bankmachine7_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin + vns_bankmachine7_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_sdram_bankmachine7_trccon_ready) begin + if (soc_sdram_bankmachine7_cmd_ready) begin + vns_bankmachine7_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_sdram_bankmachine7_refresh_req)) begin + vns_bankmachine7_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine7_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine7_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine7_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine7_next_state <= 1'd0; + end + default: begin + if (soc_sdram_bankmachine7_refresh_req) begin + vns_bankmachine7_next_state <= 3'd4; + end else begin + if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine7_row_opened) begin + if (soc_sdram_bankmachine7_row_hit) begin + if ((soc_sdram_bankmachine7_cmd_ready & soc_sdram_bankmachine7_auto_precharge)) begin + vns_bankmachine7_next_state <= 2'd2; + end + end else begin + vns_bankmachine7_next_state <= 1'd1; + end + end else begin + vns_bankmachine7_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_250 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_251; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_cmd_payload_we <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin + soc_sdram_bankmachine7_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine7_refresh_req) begin + end else begin + if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine7_row_opened) begin + if (soc_sdram_bankmachine7_row_hit) begin + if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_251 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_252; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine7_trccon_ready) begin + soc_sdram_bankmachine7_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_252 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_253; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin + soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine7_trccon_ready) begin + soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_253 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_254; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine7_refresh_req) begin + end else begin + if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine7_row_opened) begin + if (soc_sdram_bankmachine7_row_hit) begin + if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine7_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_254 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_255; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine7_refresh_req) begin + end else begin + if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine7_row_opened) begin + if (soc_sdram_bankmachine7_row_hit) begin + if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_255 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_256; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_req_wdata_ready <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine7_refresh_req) begin + end else begin + if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine7_row_opened) begin + if (soc_sdram_bankmachine7_row_hit) begin + if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine7_req_wdata_ready <= soc_sdram_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_256 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_257; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_req_rdata_valid <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine7_refresh_req) begin + end else begin + if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine7_row_opened) begin + if (soc_sdram_bankmachine7_row_hit) begin + if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine7_req_rdata_valid <= soc_sdram_bankmachine7_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_257 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_258; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_refresh_gnt <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_sdram_bankmachine7_twtpcon_ready) begin + soc_sdram_bankmachine7_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_258 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_259; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_cmd_valid <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin + soc_sdram_bankmachine7_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine7_trccon_ready) begin + soc_sdram_bankmachine7_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine7_refresh_req) begin + end else begin + if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine7_row_opened) begin + if (soc_sdram_bankmachine7_row_hit) begin + soc_sdram_bankmachine7_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_259 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_260; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_row_open <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine7_trccon_ready) begin + soc_sdram_bankmachine7_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_260 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_261; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_row_close <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + soc_sdram_bankmachine7_row_close <= 1'd1; + end + 2'd2: begin + soc_sdram_bankmachine7_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_sdram_bankmachine7_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_261 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_262; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_cmd_payload_cas <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine7_refresh_req) begin + end else begin + if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine7_row_opened) begin + if (soc_sdram_bankmachine7_row_hit) begin + soc_sdram_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_262 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_263; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_cmd_payload_ras <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin + soc_sdram_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine7_trccon_ready) begin + soc_sdram_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_263 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_trrdcon_valid = ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & ((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))); +assign soc_sdram_tfawcon_valid = ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & ((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))); +assign soc_sdram_ras_allowed = (soc_sdram_trrdcon_ready & soc_sdram_tfawcon_ready); +assign soc_sdram_tccdcon_valid = ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_cmd_payload_is_write | soc_sdram_choose_req_cmd_payload_is_read)); +assign soc_sdram_cas_allowed = soc_sdram_tccdcon_ready; +assign soc_sdram_twtrcon_valid = ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write); +assign soc_sdram_read_available = ((((((((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_payload_is_read) | (soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_payload_is_read)) | (soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_payload_is_read)) | (soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_payload_is_read)) | (soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_payload_is_read)) | (soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_payload_is_read)) | (soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_payload_is_read)) | (soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_payload_is_read)); +assign soc_sdram_write_available = ((((((((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_payload_is_write) | (soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_payload_is_write)) | (soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_payload_is_write)) | (soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_payload_is_write)) | (soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_payload_is_write)) | (soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_payload_is_write)) | (soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_payload_is_write)) | (soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_payload_is_write)); +assign soc_sdram_max_time0 = (soc_sdram_time0 == 1'd0); +assign soc_sdram_max_time1 = (soc_sdram_time1 == 1'd0); +assign soc_sdram_bankmachine0_refresh_req = soc_sdram_cmd_valid; +assign soc_sdram_bankmachine1_refresh_req = soc_sdram_cmd_valid; +assign soc_sdram_bankmachine2_refresh_req = soc_sdram_cmd_valid; +assign soc_sdram_bankmachine3_refresh_req = soc_sdram_cmd_valid; +assign soc_sdram_bankmachine4_refresh_req = soc_sdram_cmd_valid; +assign soc_sdram_bankmachine5_refresh_req = soc_sdram_cmd_valid; +assign soc_sdram_bankmachine6_refresh_req = soc_sdram_cmd_valid; +assign soc_sdram_bankmachine7_refresh_req = soc_sdram_cmd_valid; +assign soc_sdram_go_to_refresh = (((((((soc_sdram_bankmachine0_refresh_gnt & soc_sdram_bankmachine1_refresh_gnt) & soc_sdram_bankmachine2_refresh_gnt) & soc_sdram_bankmachine3_refresh_gnt) & soc_sdram_bankmachine4_refresh_gnt) & soc_sdram_bankmachine5_refresh_gnt) & soc_sdram_bankmachine6_refresh_gnt) & soc_sdram_bankmachine7_refresh_gnt); +assign soc_sdram_interface_rdata = {soc_sdram_dfi_p3_rddata, soc_sdram_dfi_p2_rddata, soc_sdram_dfi_p1_rddata, soc_sdram_dfi_p0_rddata}; +assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata; +assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata; +assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata; +assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata; +assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we); +assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we); +assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we); +assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we); + +// synthesis translate_off +reg dummy_d_264; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_cmd_valids <= 8'd0; + soc_sdram_choose_cmd_valids[0] <= (soc_sdram_bankmachine0_cmd_valid & (((soc_sdram_bankmachine0_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine0_cmd_payload_ras & (~soc_sdram_bankmachine0_cmd_payload_cas)) & (~soc_sdram_bankmachine0_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine0_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine0_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); + soc_sdram_choose_cmd_valids[1] <= (soc_sdram_bankmachine1_cmd_valid & (((soc_sdram_bankmachine1_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine1_cmd_payload_ras & (~soc_sdram_bankmachine1_cmd_payload_cas)) & (~soc_sdram_bankmachine1_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine1_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine1_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); + soc_sdram_choose_cmd_valids[2] <= (soc_sdram_bankmachine2_cmd_valid & (((soc_sdram_bankmachine2_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine2_cmd_payload_ras & (~soc_sdram_bankmachine2_cmd_payload_cas)) & (~soc_sdram_bankmachine2_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine2_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine2_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); + soc_sdram_choose_cmd_valids[3] <= (soc_sdram_bankmachine3_cmd_valid & (((soc_sdram_bankmachine3_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine3_cmd_payload_ras & (~soc_sdram_bankmachine3_cmd_payload_cas)) & (~soc_sdram_bankmachine3_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine3_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine3_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); + soc_sdram_choose_cmd_valids[4] <= (soc_sdram_bankmachine4_cmd_valid & (((soc_sdram_bankmachine4_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine4_cmd_payload_ras & (~soc_sdram_bankmachine4_cmd_payload_cas)) & (~soc_sdram_bankmachine4_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine4_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine4_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); + soc_sdram_choose_cmd_valids[5] <= (soc_sdram_bankmachine5_cmd_valid & (((soc_sdram_bankmachine5_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine5_cmd_payload_ras & (~soc_sdram_bankmachine5_cmd_payload_cas)) & (~soc_sdram_bankmachine5_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine5_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine5_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); + soc_sdram_choose_cmd_valids[6] <= (soc_sdram_bankmachine6_cmd_valid & (((soc_sdram_bankmachine6_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine6_cmd_payload_ras & (~soc_sdram_bankmachine6_cmd_payload_cas)) & (~soc_sdram_bankmachine6_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine6_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine6_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); + soc_sdram_choose_cmd_valids[7] <= (soc_sdram_bankmachine7_cmd_valid & (((soc_sdram_bankmachine7_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine7_cmd_payload_ras & (~soc_sdram_bankmachine7_cmd_payload_cas)) & (~soc_sdram_bankmachine7_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine7_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine7_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); +// synthesis translate_off + dummy_d_264 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_choose_cmd_request = soc_sdram_choose_cmd_valids; +assign soc_sdram_choose_cmd_cmd_valid = vns_rhs_array_muxed0; +assign soc_sdram_choose_cmd_cmd_payload_a = vns_rhs_array_muxed1; +assign soc_sdram_choose_cmd_cmd_payload_ba = vns_rhs_array_muxed2; +assign soc_sdram_choose_cmd_cmd_payload_is_read = vns_rhs_array_muxed3; +assign soc_sdram_choose_cmd_cmd_payload_is_write = vns_rhs_array_muxed4; +assign soc_sdram_choose_cmd_cmd_payload_is_cmd = vns_rhs_array_muxed5; + +// synthesis translate_off +reg dummy_d_265; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_cmd_cmd_payload_cas <= 1'd0; + if (soc_sdram_choose_cmd_cmd_valid) begin + soc_sdram_choose_cmd_cmd_payload_cas <= vns_t_array_muxed0; + end +// synthesis translate_off + dummy_d_265 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_266; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_cmd_cmd_payload_ras <= 1'd0; + if (soc_sdram_choose_cmd_cmd_valid) begin + soc_sdram_choose_cmd_cmd_payload_ras <= vns_t_array_muxed1; + end +// synthesis translate_off + dummy_d_266 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_267; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_cmd_cmd_payload_we <= 1'd0; + if (soc_sdram_choose_cmd_cmd_valid) begin + soc_sdram_choose_cmd_cmd_payload_we <= vns_t_array_muxed2; + end +// synthesis translate_off + dummy_d_267 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_268; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_cmd_ready <= 1'd0; + if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 1'd0))) begin + soc_sdram_bankmachine0_cmd_ready <= 1'd1; + end + if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 1'd0))) begin + soc_sdram_bankmachine0_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_268 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_269; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_cmd_ready <= 1'd0; + if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 1'd1))) begin + soc_sdram_bankmachine1_cmd_ready <= 1'd1; + end + if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 1'd1))) begin + soc_sdram_bankmachine1_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_269 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_270; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_cmd_ready <= 1'd0; + if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 2'd2))) begin + soc_sdram_bankmachine2_cmd_ready <= 1'd1; + end + if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 2'd2))) begin + soc_sdram_bankmachine2_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_270 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_271; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_cmd_ready <= 1'd0; + if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 2'd3))) begin + soc_sdram_bankmachine3_cmd_ready <= 1'd1; + end + if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 2'd3))) begin + soc_sdram_bankmachine3_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_271 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_272; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_cmd_ready <= 1'd0; + if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd4))) begin + soc_sdram_bankmachine4_cmd_ready <= 1'd1; + end + if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd4))) begin + soc_sdram_bankmachine4_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_272 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_273; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_cmd_ready <= 1'd0; + if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd5))) begin + soc_sdram_bankmachine5_cmd_ready <= 1'd1; + end + if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd5))) begin + soc_sdram_bankmachine5_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_273 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_274; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_cmd_ready <= 1'd0; + if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd6))) begin + soc_sdram_bankmachine6_cmd_ready <= 1'd1; + end + if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd6))) begin + soc_sdram_bankmachine6_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_274 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_275; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_cmd_ready <= 1'd0; + if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd7))) begin + soc_sdram_bankmachine7_cmd_ready <= 1'd1; + end + if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd7))) begin + soc_sdram_bankmachine7_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_275 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_choose_cmd_ce = (soc_sdram_choose_cmd_cmd_ready | (~soc_sdram_choose_cmd_cmd_valid)); + +// synthesis translate_off +reg dummy_d_276; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_req_valids <= 8'd0; + soc_sdram_choose_req_valids[0] <= (soc_sdram_bankmachine0_cmd_valid & (((soc_sdram_bankmachine0_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine0_cmd_payload_ras & (~soc_sdram_bankmachine0_cmd_payload_cas)) & (~soc_sdram_bankmachine0_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine0_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine0_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); + soc_sdram_choose_req_valids[1] <= (soc_sdram_bankmachine1_cmd_valid & (((soc_sdram_bankmachine1_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine1_cmd_payload_ras & (~soc_sdram_bankmachine1_cmd_payload_cas)) & (~soc_sdram_bankmachine1_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine1_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine1_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); + soc_sdram_choose_req_valids[2] <= (soc_sdram_bankmachine2_cmd_valid & (((soc_sdram_bankmachine2_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine2_cmd_payload_ras & (~soc_sdram_bankmachine2_cmd_payload_cas)) & (~soc_sdram_bankmachine2_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine2_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine2_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); + soc_sdram_choose_req_valids[3] <= (soc_sdram_bankmachine3_cmd_valid & (((soc_sdram_bankmachine3_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine3_cmd_payload_ras & (~soc_sdram_bankmachine3_cmd_payload_cas)) & (~soc_sdram_bankmachine3_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine3_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine3_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); + soc_sdram_choose_req_valids[4] <= (soc_sdram_bankmachine4_cmd_valid & (((soc_sdram_bankmachine4_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine4_cmd_payload_ras & (~soc_sdram_bankmachine4_cmd_payload_cas)) & (~soc_sdram_bankmachine4_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine4_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine4_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); + soc_sdram_choose_req_valids[5] <= (soc_sdram_bankmachine5_cmd_valid & (((soc_sdram_bankmachine5_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine5_cmd_payload_ras & (~soc_sdram_bankmachine5_cmd_payload_cas)) & (~soc_sdram_bankmachine5_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine5_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine5_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); + soc_sdram_choose_req_valids[6] <= (soc_sdram_bankmachine6_cmd_valid & (((soc_sdram_bankmachine6_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine6_cmd_payload_ras & (~soc_sdram_bankmachine6_cmd_payload_cas)) & (~soc_sdram_bankmachine6_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine6_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine6_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); + soc_sdram_choose_req_valids[7] <= (soc_sdram_bankmachine7_cmd_valid & (((soc_sdram_bankmachine7_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine7_cmd_payload_ras & (~soc_sdram_bankmachine7_cmd_payload_cas)) & (~soc_sdram_bankmachine7_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine7_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine7_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); +// synthesis translate_off + dummy_d_276 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_choose_req_request = soc_sdram_choose_req_valids; +assign soc_sdram_choose_req_cmd_valid = vns_rhs_array_muxed6; +assign soc_sdram_choose_req_cmd_payload_a = vns_rhs_array_muxed7; +assign soc_sdram_choose_req_cmd_payload_ba = vns_rhs_array_muxed8; +assign soc_sdram_choose_req_cmd_payload_is_read = vns_rhs_array_muxed9; +assign soc_sdram_choose_req_cmd_payload_is_write = vns_rhs_array_muxed10; +assign soc_sdram_choose_req_cmd_payload_is_cmd = vns_rhs_array_muxed11; + +// synthesis translate_off +reg dummy_d_277; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_req_cmd_payload_cas <= 1'd0; + if (soc_sdram_choose_req_cmd_valid) begin + soc_sdram_choose_req_cmd_payload_cas <= vns_t_array_muxed3; + end +// synthesis translate_off + dummy_d_277 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_278; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_req_cmd_payload_ras <= 1'd0; + if (soc_sdram_choose_req_cmd_valid) begin + soc_sdram_choose_req_cmd_payload_ras <= vns_t_array_muxed4; + end +// synthesis translate_off + dummy_d_278 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_279; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_req_cmd_payload_we <= 1'd0; + if (soc_sdram_choose_req_cmd_valid) begin + soc_sdram_choose_req_cmd_payload_we <= vns_t_array_muxed5; + end +// synthesis translate_off + dummy_d_279 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_choose_req_ce = (soc_sdram_choose_req_cmd_ready | (~soc_sdram_choose_req_cmd_valid)); +assign soc_sdram_dfi_p0_reset_n = 1'd1; +assign soc_sdram_dfi_p0_cke = {1{soc_sdram_steerer0}}; +assign soc_sdram_dfi_p0_odt = {1{soc_sdram_steerer1}}; +assign soc_sdram_dfi_p1_reset_n = 1'd1; +assign soc_sdram_dfi_p1_cke = {1{soc_sdram_steerer2}}; +assign soc_sdram_dfi_p1_odt = {1{soc_sdram_steerer3}}; +assign soc_sdram_dfi_p2_reset_n = 1'd1; +assign soc_sdram_dfi_p2_cke = {1{soc_sdram_steerer4}}; +assign soc_sdram_dfi_p2_odt = {1{soc_sdram_steerer5}}; +assign soc_sdram_dfi_p3_reset_n = 1'd1; +assign soc_sdram_dfi_p3_cke = {1{soc_sdram_steerer6}}; +assign soc_sdram_dfi_p3_odt = {1{soc_sdram_steerer7}}; +assign soc_sdram_tfawcon_count = ((((soc_sdram_tfawcon_window[0] + soc_sdram_tfawcon_window[1]) + soc_sdram_tfawcon_window[2]) + soc_sdram_tfawcon_window[3]) + soc_sdram_tfawcon_window[4]); + +// synthesis translate_off +reg dummy_d_280; +// synthesis translate_on +always @(*) begin + vns_multiplexer_next_state <= 4'd0; + vns_multiplexer_next_state <= vns_multiplexer_state; + case (vns_multiplexer_state) + 1'd1: begin + if (soc_sdram_read_available) begin + if (((~soc_sdram_write_available) | soc_sdram_max_time1)) begin + vns_multiplexer_next_state <= 2'd3; + end + end + if (soc_sdram_go_to_refresh) begin + vns_multiplexer_next_state <= 2'd2; + end + end + 2'd2: begin + if (soc_sdram_cmd_last) begin + vns_multiplexer_next_state <= 1'd0; + end + end + 2'd3: begin + if (soc_sdram_twtrcon_ready) begin + vns_multiplexer_next_state <= 1'd0; + end + end + 3'd4: begin + vns_multiplexer_next_state <= 3'd5; + end + 3'd5: begin + vns_multiplexer_next_state <= 3'd6; + end + 3'd6: begin + vns_multiplexer_next_state <= 3'd7; + end + 3'd7: begin + vns_multiplexer_next_state <= 4'd8; + end + 4'd8: begin + vns_multiplexer_next_state <= 4'd9; + end + 4'd9: begin + vns_multiplexer_next_state <= 4'd10; + end + 4'd10: begin + vns_multiplexer_next_state <= 1'd1; + end + default: begin + if (soc_sdram_write_available) begin + if (((~soc_sdram_read_available) | soc_sdram_max_time0)) begin + vns_multiplexer_next_state <= 3'd4; + end + end + if (soc_sdram_go_to_refresh) begin + vns_multiplexer_next_state <= 2'd2; + end + end + endcase +// synthesis translate_off + dummy_d_280 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_281; +// synthesis translate_on +always @(*) begin + soc_sdram_steerer_sel0 <= 2'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_sdram_steerer_sel0 <= 1'd0; + end + 2'd2: begin + soc_sdram_steerer_sel0 <= 2'd3; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_sdram_steerer_sel0 <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_281 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_282; +// synthesis translate_on +always @(*) begin + soc_sdram_steerer_sel1 <= 2'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_sdram_steerer_sel1 <= 1'd0; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_sdram_steerer_sel1 <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_282 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_283; +// synthesis translate_on +always @(*) begin + soc_sdram_steerer_sel2 <= 2'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_sdram_steerer_sel2 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_sdram_steerer_sel2 <= 2'd2; + end + endcase +// synthesis translate_off + dummy_d_283 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_284; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_cmd_want_activates <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + soc_sdram_choose_cmd_want_activates <= soc_sdram_ras_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + soc_sdram_choose_cmd_want_activates <= soc_sdram_ras_allowed; + end + end + endcase +// synthesis translate_off + dummy_d_284 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_285; +// synthesis translate_on +always @(*) begin + soc_sdram_steerer_sel3 <= 2'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_sdram_steerer_sel3 <= 2'd2; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_sdram_steerer_sel3 <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_285 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_286; +// synthesis translate_on +always @(*) begin + soc_sdram_en0 <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_sdram_en0 <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_286 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_287; +// synthesis translate_on +always @(*) begin + soc_sdram_cmd_ready <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + soc_sdram_cmd_ready <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_287 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_288; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_cmd_cmd_ready <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + soc_sdram_choose_cmd_cmd_ready <= ((~((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))) | soc_sdram_ras_allowed); + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + soc_sdram_choose_cmd_cmd_ready <= ((~((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))) | soc_sdram_ras_allowed); + end + end + endcase +// synthesis translate_off + dummy_d_288 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_289; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_req_want_reads <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_sdram_choose_req_want_reads <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_289 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_290; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_req_want_writes <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_sdram_choose_req_want_writes <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_290 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_291; +// synthesis translate_on +always @(*) begin + soc_sdram_en1 <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_sdram_en1 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_291 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_292; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_req_cmd_ready <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + if (1'd0) begin + soc_sdram_choose_req_cmd_ready <= (soc_sdram_cas_allowed & ((~((soc_sdram_choose_req_cmd_payload_ras & (~soc_sdram_choose_req_cmd_payload_cas)) & (~soc_sdram_choose_req_cmd_payload_we))) | soc_sdram_ras_allowed)); + end else begin + soc_sdram_choose_req_cmd_ready <= soc_sdram_cas_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + soc_sdram_choose_req_cmd_ready <= (soc_sdram_cas_allowed & ((~((soc_sdram_choose_req_cmd_payload_ras & (~soc_sdram_choose_req_cmd_payload_cas)) & (~soc_sdram_choose_req_cmd_payload_we))) | soc_sdram_ras_allowed)); + end else begin + soc_sdram_choose_req_cmd_ready <= soc_sdram_cas_allowed; + end + end + endcase +// synthesis translate_off + dummy_d_292 = dummy_s; +// synthesis translate_on +end +assign vns_roundrobin0_request = {(((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; +assign vns_roundrobin0_ce = ((~soc_sdram_interface_bank0_valid) & (~soc_sdram_interface_bank0_lock)); +assign soc_sdram_interface_bank0_addr = vns_rhs_array_muxed12; +assign soc_sdram_interface_bank0_we = vns_rhs_array_muxed13; +assign soc_sdram_interface_bank0_valid = vns_rhs_array_muxed14; +assign vns_roundrobin1_request = {(((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; +assign vns_roundrobin1_ce = ((~soc_sdram_interface_bank1_valid) & (~soc_sdram_interface_bank1_lock)); +assign soc_sdram_interface_bank1_addr = vns_rhs_array_muxed15; +assign soc_sdram_interface_bank1_we = vns_rhs_array_muxed16; +assign soc_sdram_interface_bank1_valid = vns_rhs_array_muxed17; +assign vns_roundrobin2_request = {(((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; +assign vns_roundrobin2_ce = ((~soc_sdram_interface_bank2_valid) & (~soc_sdram_interface_bank2_lock)); +assign soc_sdram_interface_bank2_addr = vns_rhs_array_muxed18; +assign soc_sdram_interface_bank2_we = vns_rhs_array_muxed19; +assign soc_sdram_interface_bank2_valid = vns_rhs_array_muxed20; +assign vns_roundrobin3_request = {(((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; +assign vns_roundrobin3_ce = ((~soc_sdram_interface_bank3_valid) & (~soc_sdram_interface_bank3_lock)); +assign soc_sdram_interface_bank3_addr = vns_rhs_array_muxed21; +assign soc_sdram_interface_bank3_we = vns_rhs_array_muxed22; +assign soc_sdram_interface_bank3_valid = vns_rhs_array_muxed23; +assign vns_roundrobin4_request = {(((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; +assign vns_roundrobin4_ce = ((~soc_sdram_interface_bank4_valid) & (~soc_sdram_interface_bank4_lock)); +assign soc_sdram_interface_bank4_addr = vns_rhs_array_muxed24; +assign soc_sdram_interface_bank4_we = vns_rhs_array_muxed25; +assign soc_sdram_interface_bank4_valid = vns_rhs_array_muxed26; +assign vns_roundrobin5_request = {(((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; +assign vns_roundrobin5_ce = ((~soc_sdram_interface_bank5_valid) & (~soc_sdram_interface_bank5_lock)); +assign soc_sdram_interface_bank5_addr = vns_rhs_array_muxed27; +assign soc_sdram_interface_bank5_we = vns_rhs_array_muxed28; +assign soc_sdram_interface_bank5_valid = vns_rhs_array_muxed29; +assign vns_roundrobin6_request = {(((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; +assign vns_roundrobin6_ce = ((~soc_sdram_interface_bank6_valid) & (~soc_sdram_interface_bank6_lock)); +assign soc_sdram_interface_bank6_addr = vns_rhs_array_muxed30; +assign soc_sdram_interface_bank6_we = vns_rhs_array_muxed31; +assign soc_sdram_interface_bank6_valid = vns_rhs_array_muxed32; +assign vns_roundrobin7_request = {(((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_port_cmd_valid)}; +assign vns_roundrobin7_ce = ((~soc_sdram_interface_bank7_valid) & (~soc_sdram_interface_bank7_lock)); +assign soc_sdram_interface_bank7_addr = vns_rhs_array_muxed33; +assign soc_sdram_interface_bank7_we = vns_rhs_array_muxed34; +assign soc_sdram_interface_bank7_valid = vns_rhs_array_muxed35; +assign soc_port_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0)))))) & soc_sdram_interface_bank7_ready)); +assign soc_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1)))))) & soc_sdram_interface_bank7_ready)); +assign soc_port_wdata_ready = vns_new_master_wdata_ready2; +assign soc_wdata_ready = vns_new_master_wdata_ready5; +assign soc_port_rdata_valid = vns_new_master_rdata_valid8; +assign soc_rdata_valid = vns_new_master_rdata_valid17; + +// synthesis translate_off +reg dummy_d_293; +// synthesis translate_on +always @(*) begin + soc_sdram_interface_wdata <= 128'd0; + case ({vns_new_master_wdata_ready5, vns_new_master_wdata_ready2}) + 1'd1: begin + soc_sdram_interface_wdata <= soc_port_wdata_payload_data; + end + 2'd2: begin + soc_sdram_interface_wdata <= soc_wdata_payload_data; + end + default: begin + soc_sdram_interface_wdata <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_293 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_294; +// synthesis translate_on +always @(*) begin + soc_sdram_interface_wdata_we <= 16'd0; + case ({vns_new_master_wdata_ready5, vns_new_master_wdata_ready2}) + 1'd1: begin + soc_sdram_interface_wdata_we <= soc_port_wdata_payload_we; + end + 2'd2: begin + soc_sdram_interface_wdata_we <= soc_wdata_payload_we; + end + default: begin + soc_sdram_interface_wdata_we <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_294 = dummy_s; +// synthesis translate_on +end +assign soc_port_rdata_payload_data = soc_sdram_interface_rdata; +assign soc_rdata_payload_data = soc_sdram_interface_rdata; +assign soc_address_d = soc_wb_sdram_adr; +assign soc_counter_offset = soc_address_q; +assign soc_counter_done = ((soc_counter + soc_counter_offset) == 2'd3); +assign soc_end_of_burst = ((~soc_wb_sdram_cyc) | (((soc_wb_sdram_stb & soc_wb_sdram_cyc) & soc_wb_sdram_ack) & ((soc_wb_sdram_cti == 3'd7) | soc_counter_done))); +assign soc_need_refill_reset = soc_end_of_burst; +assign soc_need_refill_d = 1'd0; +assign soc_litedram_wb_cti = 3'd7; +assign soc_litedram_wb_adr = soc_address_q[29:2]; +assign soc_cached_sels_reset0 = soc_counter_reset; + +// synthesis translate_off +reg dummy_d_295; +// synthesis translate_on +always @(*) begin + soc_cached_datas_flipflop0_d <= 32'd0; + if (soc_write) begin + soc_cached_datas_flipflop0_d <= soc_wb_sdram_dat_w; + end else begin + soc_cached_datas_flipflop0_d <= soc_litedram_wb_dat_r[31:0]; + end +// synthesis translate_off + dummy_d_295 = dummy_s; +// synthesis translate_on +end +assign soc_cached_sels_flipflop0_d = soc_wb_sdram_sel; + +// synthesis translate_off +reg dummy_d_296; +// synthesis translate_on +always @(*) begin + soc_cached_datas_ce0 <= 1'd0; + if (((soc_write & soc_write_sel0) | soc_refill)) begin + soc_cached_datas_ce0 <= 1'd1; + end +// synthesis translate_off + dummy_d_296 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_297; +// synthesis translate_on +always @(*) begin + soc_cached_sels_ce0 <= 1'd0; + if (((soc_write & soc_write_sel0) | soc_refill)) begin + soc_cached_sels_ce0 <= 1'd1; + end +// synthesis translate_off + dummy_d_297 = dummy_s; +// synthesis translate_on +end +assign soc_cached_sels_reset1 = soc_counter_reset; + +// synthesis translate_off +reg dummy_d_298; +// synthesis translate_on +always @(*) begin + soc_cached_datas_flipflop1_d <= 32'd0; + if (soc_write) begin + soc_cached_datas_flipflop1_d <= soc_wb_sdram_dat_w; + end else begin + soc_cached_datas_flipflop1_d <= soc_litedram_wb_dat_r[63:32]; + end +// synthesis translate_off + dummy_d_298 = dummy_s; +// synthesis translate_on +end +assign soc_cached_sels_flipflop1_d = soc_wb_sdram_sel; + +// synthesis translate_off +reg dummy_d_299; +// synthesis translate_on +always @(*) begin + soc_cached_datas_ce1 <= 1'd0; + if (((soc_write & soc_write_sel1) | soc_refill)) begin + soc_cached_datas_ce1 <= 1'd1; + end +// synthesis translate_off + dummy_d_299 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_300; +// synthesis translate_on +always @(*) begin + soc_cached_sels_ce1 <= 1'd0; + if (((soc_write & soc_write_sel1) | soc_refill)) begin + soc_cached_sels_ce1 <= 1'd1; + end +// synthesis translate_off + dummy_d_300 = dummy_s; +// synthesis translate_on +end +assign soc_cached_sels_reset2 = soc_counter_reset; + +// synthesis translate_off +reg dummy_d_301; +// synthesis translate_on +always @(*) begin + soc_cached_datas_flipflop2_d <= 32'd0; + if (soc_write) begin + soc_cached_datas_flipflop2_d <= soc_wb_sdram_dat_w; + end else begin + soc_cached_datas_flipflop2_d <= soc_litedram_wb_dat_r[95:64]; + end +// synthesis translate_off + dummy_d_301 = dummy_s; +// synthesis translate_on +end +assign soc_cached_sels_flipflop2_d = soc_wb_sdram_sel; + +// synthesis translate_off +reg dummy_d_302; +// synthesis translate_on +always @(*) begin + soc_cached_datas_ce2 <= 1'd0; + if (((soc_write & soc_write_sel2) | soc_refill)) begin + soc_cached_datas_ce2 <= 1'd1; + end +// synthesis translate_off + dummy_d_302 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_303; +// synthesis translate_on +always @(*) begin + soc_cached_sels_ce2 <= 1'd0; + if (((soc_write & soc_write_sel2) | soc_refill)) begin + soc_cached_sels_ce2 <= 1'd1; + end +// synthesis translate_off + dummy_d_303 = dummy_s; +// synthesis translate_on +end +assign soc_cached_sels_reset3 = soc_counter_reset; + +// synthesis translate_off +reg dummy_d_304; +// synthesis translate_on +always @(*) begin + soc_cached_datas_flipflop3_d <= 32'd0; + if (soc_write) begin + soc_cached_datas_flipflop3_d <= soc_wb_sdram_dat_w; + end else begin + soc_cached_datas_flipflop3_d <= soc_litedram_wb_dat_r[127:96]; + end +// synthesis translate_off + dummy_d_304 = dummy_s; +// synthesis translate_on +end +assign soc_cached_sels_flipflop3_d = soc_wb_sdram_sel; + +// synthesis translate_off +reg dummy_d_305; +// synthesis translate_on +always @(*) begin + soc_cached_datas_ce3 <= 1'd0; + if (((soc_write & soc_write_sel3) | soc_refill)) begin + soc_cached_datas_ce3 <= 1'd1; + end +// synthesis translate_off + dummy_d_305 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_306; +// synthesis translate_on +always @(*) begin + soc_cached_sels_ce3 <= 1'd0; + if (((soc_write & soc_write_sel3) | soc_refill)) begin + soc_cached_sels_ce3 <= 1'd1; + end +// synthesis translate_off + dummy_d_306 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_307; +// synthesis translate_on +always @(*) begin + soc_write_sel2 <= 1'd0; + case ((soc_counter + soc_counter_offset)) + 1'd0: begin + end + 1'd1: begin + end + 2'd2: begin + soc_write_sel2 <= 1'd1; + end + 2'd3: begin + end + endcase +// synthesis translate_off + dummy_d_307 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_308; +// synthesis translate_on +always @(*) begin + soc_write_sel3 <= 1'd0; + case ((soc_counter + soc_counter_offset)) + 1'd0: begin + end + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + soc_write_sel3 <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_308 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_309; +// synthesis translate_on +always @(*) begin + soc_write_sel0 <= 1'd0; + case ((soc_counter + soc_counter_offset)) + 1'd0: begin + soc_write_sel0 <= 1'd1; + end + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + endcase +// synthesis translate_off + dummy_d_309 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_310; +// synthesis translate_on +always @(*) begin + soc_write_sel1 <= 1'd0; + case ((soc_counter + soc_counter_offset)) + 1'd0: begin + end + 1'd1: begin + soc_write_sel1 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + endcase +// synthesis translate_off + dummy_d_310 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_311; +// synthesis translate_on +always @(*) begin + soc_wb_sdram_dat_r <= 32'd0; + case (soc_address_q[1:0]) + 1'd0: begin + soc_wb_sdram_dat_r <= soc_cached_datas_flipflop0_q; + end + 1'd1: begin + soc_wb_sdram_dat_r <= soc_cached_datas_flipflop1_q; + end + 2'd2: begin + soc_wb_sdram_dat_r <= soc_cached_datas_flipflop2_q; + end + 2'd3: begin + soc_wb_sdram_dat_r <= soc_cached_datas_flipflop3_q; + end + endcase +// synthesis translate_off + dummy_d_311 = dummy_s; +// synthesis translate_on +end +assign soc_cached_data = {soc_cached_datas_flipflop3_q, soc_cached_datas_flipflop2_q, soc_cached_datas_flipflop1_q, soc_cached_datas_flipflop0_q}; +assign soc_cached_sel = {soc_cached_sels_flipflop3_q, soc_cached_sels_flipflop2_q, soc_cached_sels_flipflop1_q, soc_cached_sels_flipflop0_q}; + +// synthesis translate_off +reg dummy_d_312; +// synthesis translate_on +always @(*) begin + vns_converter_next_state <= 3'd0; + vns_converter_next_state <= vns_converter_state; + case (vns_converter_state) + 1'd1: begin + if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin + if (soc_counter_done) begin + vns_converter_next_state <= 2'd2; + end + end else begin + if ((~soc_wb_sdram_cyc)) begin + vns_converter_next_state <= 2'd2; + end + end + end + 2'd2: begin + if (soc_litedram_wb_ack) begin + vns_converter_next_state <= 1'd0; + end + end + 2'd3: begin + if (soc_litedram_wb_ack) begin + vns_converter_next_state <= 3'd4; + end + end + 3'd4: begin + vns_converter_next_state <= 1'd0; + end + default: begin + if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin + if (soc_wb_sdram_we) begin + vns_converter_next_state <= 1'd1; + end else begin + if (soc_need_refill_q) begin + vns_converter_next_state <= 2'd3; + end else begin + vns_converter_next_state <= 3'd4; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_312 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_313; +// synthesis translate_on +always @(*) begin + soc_address_ce <= 1'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + default: begin + if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin + soc_address_ce <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_313 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_314; +// synthesis translate_on +always @(*) begin + soc_litedram_wb_dat_w <= 128'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + soc_litedram_wb_dat_w <= soc_cached_data; + end + 2'd3: begin + end + 3'd4: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_314 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_315; +// synthesis translate_on +always @(*) begin + soc_litedram_wb_sel <= 16'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + soc_litedram_wb_sel <= soc_cached_sel; + end + 2'd3: begin + end + 3'd4: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_315 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_316; +// synthesis translate_on +always @(*) begin + soc_counter_ce <= 1'd0; + case (vns_converter_state) + 1'd1: begin + if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin + soc_counter_ce <= 1'd1; + end else begin + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_316 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_317; +// synthesis translate_on +always @(*) begin + soc_litedram_wb_cyc <= 1'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + soc_litedram_wb_cyc <= 1'd1; + end + 2'd3: begin + soc_litedram_wb_cyc <= 1'd1; + end + 3'd4: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_317 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_318; +// synthesis translate_on +always @(*) begin + soc_counter_reset <= 1'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + default: begin + soc_counter_reset <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_318 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_319; +// synthesis translate_on +always @(*) begin + soc_litedram_wb_stb <= 1'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + soc_litedram_wb_stb <= 1'd1; + end + 2'd3: begin + soc_litedram_wb_stb <= 1'd1; + end + 3'd4: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_319 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_320; +// synthesis translate_on +always @(*) begin + soc_need_refill_ce <= 1'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedram_wb_ack) begin + soc_need_refill_ce <= 1'd1; + end + end + 3'd4: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_320 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_321; +// synthesis translate_on +always @(*) begin + soc_litedram_wb_we <= 1'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + soc_litedram_wb_we <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_321 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_322; +// synthesis translate_on +always @(*) begin + soc_write <= 1'd0; + case (vns_converter_state) + 1'd1: begin + if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin + soc_write <= 1'd1; + end else begin + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_322 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_323; +// synthesis translate_on +always @(*) begin + soc_wb_sdram_ack <= 1'd0; + case (vns_converter_state) + 1'd1: begin + if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin + soc_wb_sdram_ack <= 1'd1; + end else begin + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin + soc_wb_sdram_ack <= 1'd1; + end + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_323 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_324; +// synthesis translate_on +always @(*) begin + soc_evict <= 1'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + soc_evict <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_324 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_325; +// synthesis translate_on +always @(*) begin + soc_refill <= 1'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + soc_refill <= 1'd1; + end + 3'd4: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_325 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_326; +// synthesis translate_on +always @(*) begin + soc_read <= 1'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + soc_read <= 1'd1; + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_326 = dummy_s; +// synthesis translate_on +end +assign soc_wdata_converter_sink_valid = ((soc_litedram_wb_cyc & soc_litedram_wb_stb) & soc_litedram_wb_we); +assign soc_wdata_converter_sink_payload_data = soc_litedram_wb_dat_w; +assign soc_wdata_converter_sink_payload_we = soc_litedram_wb_sel; +assign soc_port_wdata_valid = soc_wdata_converter_source_valid; +assign soc_wdata_converter_source_ready = soc_port_wdata_ready; +assign soc_port_wdata_first = soc_wdata_converter_source_first; +assign soc_port_wdata_last = soc_wdata_converter_source_last; +assign soc_port_wdata_payload_data = soc_wdata_converter_source_payload_data; +assign soc_port_wdata_payload_we = soc_wdata_converter_source_payload_we; +assign soc_rdata_converter_sink_valid = soc_port_rdata_valid; +assign soc_port_rdata_ready = soc_rdata_converter_sink_ready; +assign soc_rdata_converter_sink_first = soc_port_rdata_first; +assign soc_rdata_converter_sink_last = soc_port_rdata_last; +assign soc_rdata_converter_sink_payload_data = soc_port_rdata_payload_data; +assign soc_rdata_converter_source_ready = 1'd1; +assign soc_litedram_wb_dat_r = soc_rdata_converter_source_payload_data; +assign soc_wdata_converter_converter_sink_valid = soc_wdata_converter_sink_valid; +assign soc_wdata_converter_converter_sink_first = soc_wdata_converter_sink_first; +assign soc_wdata_converter_converter_sink_last = soc_wdata_converter_sink_last; +assign soc_wdata_converter_sink_ready = soc_wdata_converter_converter_sink_ready; +assign soc_wdata_converter_converter_sink_payload_data = {soc_wdata_converter_sink_payload_we, soc_wdata_converter_sink_payload_data}; +assign soc_wdata_converter_source_valid = soc_wdata_converter_source_source_valid; +assign soc_wdata_converter_source_first = soc_wdata_converter_source_source_first; +assign soc_wdata_converter_source_last = soc_wdata_converter_source_source_last; +assign soc_wdata_converter_source_source_ready = soc_wdata_converter_source_ready; +assign {soc_wdata_converter_source_payload_we, soc_wdata_converter_source_payload_data} = soc_wdata_converter_source_source_payload_data; +assign {soc_wdata_converter_source_payload_we, soc_wdata_converter_source_payload_data} = soc_wdata_converter_source_source_payload_data; +assign soc_wdata_converter_source_source_valid = soc_wdata_converter_converter_source_valid; +assign soc_wdata_converter_converter_source_ready = soc_wdata_converter_source_source_ready; +assign soc_wdata_converter_source_source_first = soc_wdata_converter_converter_source_first; +assign soc_wdata_converter_source_source_last = soc_wdata_converter_converter_source_last; +assign soc_wdata_converter_source_source_payload_data = soc_wdata_converter_converter_source_payload_data; +assign soc_wdata_converter_converter_source_valid = soc_wdata_converter_converter_sink_valid; +assign soc_wdata_converter_converter_sink_ready = soc_wdata_converter_converter_source_ready; +assign soc_wdata_converter_converter_source_first = soc_wdata_converter_converter_sink_first; +assign soc_wdata_converter_converter_source_last = soc_wdata_converter_converter_sink_last; +assign soc_wdata_converter_converter_source_payload_data = soc_wdata_converter_converter_sink_payload_data; +assign soc_wdata_converter_converter_source_payload_valid_token_count = 1'd1; +assign soc_rdata_converter_converter_sink_valid = soc_rdata_converter_sink_valid; +assign soc_rdata_converter_converter_sink_first = soc_rdata_converter_sink_first; +assign soc_rdata_converter_converter_sink_last = soc_rdata_converter_sink_last; +assign soc_rdata_converter_sink_ready = soc_rdata_converter_converter_sink_ready; +assign soc_rdata_converter_converter_sink_payload_data = {soc_rdata_converter_sink_payload_data}; +assign soc_rdata_converter_source_valid = soc_rdata_converter_source_source_valid; +assign soc_rdata_converter_source_first = soc_rdata_converter_source_source_first; +assign soc_rdata_converter_source_last = soc_rdata_converter_source_source_last; +assign soc_rdata_converter_source_source_ready = soc_rdata_converter_source_ready; +assign {soc_rdata_converter_source_payload_data} = soc_rdata_converter_source_source_payload_data; +assign soc_rdata_converter_source_source_valid = soc_rdata_converter_converter_source_valid; +assign soc_rdata_converter_converter_source_ready = soc_rdata_converter_source_source_ready; +assign soc_rdata_converter_source_source_first = soc_rdata_converter_converter_source_first; +assign soc_rdata_converter_source_source_last = soc_rdata_converter_converter_source_last; +assign soc_rdata_converter_source_source_payload_data = soc_rdata_converter_converter_source_payload_data; +assign soc_rdata_converter_converter_source_valid = soc_rdata_converter_converter_sink_valid; +assign soc_rdata_converter_converter_sink_ready = soc_rdata_converter_converter_source_ready; +assign soc_rdata_converter_converter_source_first = soc_rdata_converter_converter_sink_first; +assign soc_rdata_converter_converter_source_last = soc_rdata_converter_converter_sink_last; +assign soc_rdata_converter_converter_source_payload_data = soc_rdata_converter_converter_sink_payload_data; +assign soc_rdata_converter_converter_source_payload_valid_token_count = 1'd1; + +// synthesis translate_off +reg dummy_d_327; +// synthesis translate_on +always @(*) begin + vns_litedramwishbone2native_next_state <= 2'd0; + vns_litedramwishbone2native_next_state <= vns_litedramwishbone2native_state; + case (vns_litedramwishbone2native_state) + 1'd1: begin + if (soc_wdata_converter_sink_ready) begin + vns_litedramwishbone2native_next_state <= 1'd0; + end + end + 2'd2: begin + if (soc_rdata_converter_source_valid) begin + vns_litedramwishbone2native_next_state <= 1'd0; + end + end + default: begin + if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin + if ((soc_count == 1'd0)) begin + if (soc_litedram_wb_we) begin + vns_litedramwishbone2native_next_state <= 1'd1; + end else begin + vns_litedramwishbone2native_next_state <= 2'd2; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_327 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_328; +// synthesis translate_on +always @(*) begin + soc_count_next_value <= 1'd0; + case (vns_litedramwishbone2native_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin + soc_count_next_value <= (soc_count + 1'd1); + if ((soc_count == 1'd0)) begin + soc_count_next_value <= 1'd0; + end + end + end + endcase +// synthesis translate_off + dummy_d_328 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_329; +// synthesis translate_on +always @(*) begin + soc_count_next_value_ce <= 1'd0; + case (vns_litedramwishbone2native_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin + soc_count_next_value_ce <= 1'd1; + if ((soc_count == 1'd0)) begin + soc_count_next_value_ce <= 1'd1; + end + end + end + endcase +// synthesis translate_off + dummy_d_329 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_330; +// synthesis translate_on +always @(*) begin + soc_port_cmd_valid <= 1'd0; + case (vns_litedramwishbone2native_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + soc_port_cmd_valid <= (soc_litedram_wb_cyc & soc_litedram_wb_stb); + end + endcase +// synthesis translate_off + dummy_d_330 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_331; +// synthesis translate_on +always @(*) begin + soc_litedram_wb_ack <= 1'd0; + case (vns_litedramwishbone2native_state) + 1'd1: begin + if (soc_wdata_converter_sink_ready) begin + soc_litedram_wb_ack <= 1'd1; + end + end + 2'd2: begin + if (soc_rdata_converter_source_valid) begin + soc_litedram_wb_ack <= 1'd1; + end + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_331 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_332; +// synthesis translate_on +always @(*) begin + soc_port_cmd_payload_we <= 1'd0; + case (vns_litedramwishbone2native_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + soc_port_cmd_payload_we <= soc_litedram_wb_we; + end + endcase +// synthesis translate_off + dummy_d_332 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_333; +// synthesis translate_on +always @(*) begin + soc_port_cmd_payload_addr <= 24'd0; + case (vns_litedramwishbone2native_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + soc_port_cmd_payload_addr <= (((soc_litedram_wb_adr * 1'd1) + soc_count) - 27'd67108864); + end + endcase +// synthesis translate_off + dummy_d_333 = dummy_s; +// synthesis translate_on +end +assign vns_shared_adr = vns_rhs_array_muxed36; +assign vns_shared_dat_w = vns_rhs_array_muxed37; +assign vns_shared_sel = vns_rhs_array_muxed38; +assign vns_shared_cyc = vns_rhs_array_muxed39; +assign vns_shared_stb = vns_rhs_array_muxed40; +assign vns_shared_we = vns_rhs_array_muxed41; +assign vns_shared_cti = vns_rhs_array_muxed42; +assign vns_shared_bte = vns_rhs_array_muxed43; +assign soc_litedramcore_cpu_ibus_dat_r = vns_shared_dat_r; +assign soc_litedramcore_cpu_dbus_dat_r = vns_shared_dat_r; +assign soc_litedramcore_cpu_ibus_ack = (vns_shared_ack & (vns_grant == 1'd0)); +assign soc_litedramcore_cpu_dbus_ack = (vns_shared_ack & (vns_grant == 1'd1)); +assign soc_litedramcore_cpu_ibus_err = (vns_shared_err & (vns_grant == 1'd0)); +assign soc_litedramcore_cpu_dbus_err = (vns_shared_err & (vns_grant == 1'd1)); +assign vns_request = {soc_litedramcore_cpu_dbus_cyc, soc_litedramcore_cpu_ibus_cyc}; + +// synthesis translate_off +reg dummy_d_334; +// synthesis translate_on +always @(*) begin + vns_slave_sel <= 4'd0; + vns_slave_sel[0] <= (vns_shared_adr[29:13] == 1'd0); + vns_slave_sel[1] <= (vns_shared_adr[29:10] == 13'd4096); + vns_slave_sel[2] <= (vns_shared_adr[29:14] == 16'd33280); + vns_slave_sel[3] <= (vns_shared_adr[29:22] == 7'd64); +// synthesis translate_off + dummy_d_334 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_litedramcore_ram_bus_adr = vns_shared_adr; +assign soc_litedramcore_litedramcore_ram_bus_dat_w = vns_shared_dat_w; +assign soc_litedramcore_litedramcore_ram_bus_sel = vns_shared_sel; +assign soc_litedramcore_litedramcore_ram_bus_stb = vns_shared_stb; +assign soc_litedramcore_litedramcore_ram_bus_we = vns_shared_we; +assign soc_litedramcore_litedramcore_ram_bus_cti = vns_shared_cti; +assign soc_litedramcore_litedramcore_ram_bus_bte = vns_shared_bte; +assign soc_litedramcore_ram_bus_ram_bus_adr = vns_shared_adr; +assign soc_litedramcore_ram_bus_ram_bus_dat_w = vns_shared_dat_w; +assign soc_litedramcore_ram_bus_ram_bus_sel = vns_shared_sel; +assign soc_litedramcore_ram_bus_ram_bus_stb = vns_shared_stb; +assign soc_litedramcore_ram_bus_ram_bus_we = vns_shared_we; +assign soc_litedramcore_ram_bus_ram_bus_cti = vns_shared_cti; +assign soc_litedramcore_ram_bus_ram_bus_bte = vns_shared_bte; +assign soc_litedramcore_bus_wishbone_adr = vns_shared_adr; +assign soc_litedramcore_bus_wishbone_dat_w = vns_shared_dat_w; +assign soc_litedramcore_bus_wishbone_sel = vns_shared_sel; +assign soc_litedramcore_bus_wishbone_stb = vns_shared_stb; +assign soc_litedramcore_bus_wishbone_we = vns_shared_we; +assign soc_litedramcore_bus_wishbone_cti = vns_shared_cti; +assign soc_litedramcore_bus_wishbone_bte = vns_shared_bte; +assign soc_wb_sdram_adr = vns_shared_adr; +assign soc_wb_sdram_dat_w = vns_shared_dat_w; +assign soc_wb_sdram_sel = vns_shared_sel; +assign soc_wb_sdram_stb = vns_shared_stb; +assign soc_wb_sdram_we = vns_shared_we; +assign soc_wb_sdram_cti = vns_shared_cti; +assign soc_wb_sdram_bte = vns_shared_bte; +assign soc_litedramcore_litedramcore_ram_bus_cyc = (vns_shared_cyc & vns_slave_sel[0]); +assign soc_litedramcore_ram_bus_ram_bus_cyc = (vns_shared_cyc & vns_slave_sel[1]); +assign soc_litedramcore_bus_wishbone_cyc = (vns_shared_cyc & vns_slave_sel[2]); +assign soc_wb_sdram_cyc = (vns_shared_cyc & vns_slave_sel[3]); + +// synthesis translate_off +reg dummy_d_335; +// synthesis translate_on +always @(*) begin + vns_shared_ack <= 1'd0; + vns_shared_ack <= (((soc_litedramcore_litedramcore_ram_bus_ack | soc_litedramcore_ram_bus_ram_bus_ack) | soc_litedramcore_bus_wishbone_ack) | soc_wb_sdram_ack); + if (vns_done) begin + vns_shared_ack <= 1'd1; + end +// synthesis translate_off + dummy_d_335 = dummy_s; +// synthesis translate_on +end +assign vns_shared_err = (((soc_litedramcore_litedramcore_ram_bus_err | soc_litedramcore_ram_bus_ram_bus_err) | soc_litedramcore_bus_wishbone_err) | soc_wb_sdram_err); + +// synthesis translate_off +reg dummy_d_336; +// synthesis translate_on +always @(*) begin + vns_shared_dat_r <= 32'd0; + vns_shared_dat_r <= (((({32{vns_slave_sel_r[0]}} & soc_litedramcore_litedramcore_ram_bus_dat_r) | ({32{vns_slave_sel_r[1]}} & soc_litedramcore_ram_bus_ram_bus_dat_r)) | ({32{vns_slave_sel_r[2]}} & soc_litedramcore_bus_wishbone_dat_r)) | ({32{vns_slave_sel_r[3]}} & soc_wb_sdram_dat_r)); + if (vns_done) begin + vns_shared_dat_r <= 32'd4294967295; + end +// synthesis translate_off + dummy_d_336 = dummy_s; +// synthesis translate_on +end +assign vns_wait = ((vns_shared_stb & vns_shared_cyc) & (~vns_shared_ack)); + +// synthesis translate_off +reg dummy_d_337; +// synthesis translate_on +always @(*) begin + vns_error <= 1'd0; + if (vns_done) begin + vns_error <= 1'd1; + end +// synthesis translate_off + dummy_d_337 = dummy_s; +// synthesis translate_on +end +assign vns_done = (vns_count == 1'd0); +assign vns_csrbank0_sel = (vns_interface0_bank_bus_adr[13:9] == 1'd0); +assign vns_csrbank0_reset0_r = vns_interface0_bank_bus_dat_w[0]; +assign vns_csrbank0_reset0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 1'd0)); +assign vns_csrbank0_reset0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 1'd0)); +assign vns_csrbank0_scratch3_r = vns_interface0_bank_bus_dat_w[7:0]; +assign vns_csrbank0_scratch3_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 1'd1)); +assign vns_csrbank0_scratch3_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 1'd1)); +assign vns_csrbank0_scratch2_r = vns_interface0_bank_bus_dat_w[7:0]; +assign vns_csrbank0_scratch2_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 2'd2)); +assign vns_csrbank0_scratch2_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 2'd2)); +assign vns_csrbank0_scratch1_r = vns_interface0_bank_bus_dat_w[7:0]; +assign vns_csrbank0_scratch1_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 2'd3)); +assign vns_csrbank0_scratch1_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 2'd3)); +assign vns_csrbank0_scratch0_r = vns_interface0_bank_bus_dat_w[7:0]; +assign vns_csrbank0_scratch0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd4)); +assign vns_csrbank0_scratch0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd4)); +assign vns_csrbank0_bus_errors3_r = vns_interface0_bank_bus_dat_w[7:0]; +assign vns_csrbank0_bus_errors3_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd5)); +assign vns_csrbank0_bus_errors3_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd5)); +assign vns_csrbank0_bus_errors2_r = vns_interface0_bank_bus_dat_w[7:0]; +assign vns_csrbank0_bus_errors2_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd6)); +assign vns_csrbank0_bus_errors2_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd6)); +assign vns_csrbank0_bus_errors1_r = vns_interface0_bank_bus_dat_w[7:0]; +assign vns_csrbank0_bus_errors1_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd7)); +assign vns_csrbank0_bus_errors1_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd7)); +assign vns_csrbank0_bus_errors0_r = vns_interface0_bank_bus_dat_w[7:0]; +assign vns_csrbank0_bus_errors0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 4'd8)); +assign vns_csrbank0_bus_errors0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 4'd8)); +assign vns_csrbank0_reset0_w = soc_litedramcore_soccontroller_reset_storage; +assign vns_csrbank0_scratch3_w = soc_litedramcore_soccontroller_scratch_storage[31:24]; +assign vns_csrbank0_scratch2_w = soc_litedramcore_soccontroller_scratch_storage[23:16]; +assign vns_csrbank0_scratch1_w = soc_litedramcore_soccontroller_scratch_storage[15:8]; +assign vns_csrbank0_scratch0_w = soc_litedramcore_soccontroller_scratch_storage[7:0]; +assign vns_csrbank0_bus_errors3_w = soc_litedramcore_soccontroller_bus_errors_status[31:24]; +assign vns_csrbank0_bus_errors2_w = soc_litedramcore_soccontroller_bus_errors_status[23:16]; +assign vns_csrbank0_bus_errors1_w = soc_litedramcore_soccontroller_bus_errors_status[15:8]; +assign vns_csrbank0_bus_errors0_w = soc_litedramcore_soccontroller_bus_errors_status[7:0]; +assign soc_litedramcore_soccontroller_bus_errors_we = vns_csrbank0_bus_errors0_we; +assign vns_csrbank1_sel = (vns_interface1_bank_bus_adr[13:9] == 3'd7); +assign vns_csrbank1_init_done0_r = vns_interface1_bank_bus_dat_w[0]; +assign vns_csrbank1_init_done0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[0] == 1'd0)); +assign vns_csrbank1_init_done0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[0] == 1'd0)); +assign vns_csrbank1_init_error0_r = vns_interface1_bank_bus_dat_w[0]; +assign vns_csrbank1_init_error0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[0] == 1'd1)); +assign vns_csrbank1_init_error0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[0] == 1'd1)); +assign vns_csrbank1_init_done0_w = soc_init_done_storage; +assign vns_csrbank1_init_error0_w = soc_init_error_storage; +assign vns_csrbank2_sel = (vns_interface2_bank_bus_adr[13:9] == 3'd5); +assign vns_csrbank2_half_sys8x_taps0_r = vns_interface2_bank_bus_dat_w[4:0]; +assign vns_csrbank2_half_sys8x_taps0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 1'd0)); +assign vns_csrbank2_half_sys8x_taps0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 1'd0)); +assign vns_csrbank2_wlevel_en0_r = vns_interface2_bank_bus_dat_w[0]; +assign vns_csrbank2_wlevel_en0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 1'd1)); +assign vns_csrbank2_wlevel_en0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 1'd1)); +assign soc_a7ddrphy_wlevel_strobe_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_a7ddrphy_wlevel_strobe_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 2'd2)); +assign soc_a7ddrphy_wlevel_strobe_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 2'd2)); +assign soc_a7ddrphy_cdly_rst_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_a7ddrphy_cdly_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 2'd3)); +assign soc_a7ddrphy_cdly_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 2'd3)); +assign soc_a7ddrphy_cdly_inc_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_a7ddrphy_cdly_inc_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd4)); +assign soc_a7ddrphy_cdly_inc_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd4)); +assign vns_csrbank2_dly_sel0_r = vns_interface2_bank_bus_dat_w[1:0]; +assign vns_csrbank2_dly_sel0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd5)); +assign vns_csrbank2_dly_sel0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd5)); +assign soc_a7ddrphy_rdly_dq_rst_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_a7ddrphy_rdly_dq_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd6)); +assign soc_a7ddrphy_rdly_dq_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd6)); +assign soc_a7ddrphy_rdly_dq_inc_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_a7ddrphy_rdly_dq_inc_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd7)); +assign soc_a7ddrphy_rdly_dq_inc_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd7)); +assign soc_a7ddrphy_rdly_dq_bitslip_rst_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_a7ddrphy_rdly_dq_bitslip_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 4'd8)); +assign soc_a7ddrphy_rdly_dq_bitslip_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 4'd8)); +assign soc_a7ddrphy_rdly_dq_bitslip_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_a7ddrphy_rdly_dq_bitslip_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 4'd9)); +assign soc_a7ddrphy_rdly_dq_bitslip_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 4'd9)); +assign vns_csrbank2_half_sys8x_taps0_w = soc_a7ddrphy_half_sys8x_taps_storage[4:0]; +assign vns_csrbank2_wlevel_en0_w = soc_a7ddrphy_wlevel_en_storage; +assign vns_csrbank2_dly_sel0_w = soc_a7ddrphy_dly_sel_storage[1:0]; +assign vns_csrbank3_sel = (vns_interface3_bank_bus_adr[13:9] == 3'd6); +assign vns_csrbank3_dfii_control0_r = vns_interface3_bank_bus_dat_w[3:0]; +assign vns_csrbank3_dfii_control0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 1'd0)); +assign vns_csrbank3_dfii_control0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 1'd0)); +assign vns_csrbank3_dfii_pi0_command0_r = vns_interface3_bank_bus_dat_w[5:0]; +assign vns_csrbank3_dfii_pi0_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 1'd1)); +assign vns_csrbank3_dfii_pi0_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 1'd1)); +assign soc_sdram_phaseinjector0_command_issue_r = vns_interface3_bank_bus_dat_w[0]; +assign soc_sdram_phaseinjector0_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 2'd2)); +assign soc_sdram_phaseinjector0_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 2'd2)); +assign vns_csrbank3_dfii_pi0_address1_r = vns_interface3_bank_bus_dat_w[5:0]; +assign vns_csrbank3_dfii_pi0_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 2'd3)); +assign vns_csrbank3_dfii_pi0_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 2'd3)); +assign vns_csrbank3_dfii_pi0_address0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi0_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd4)); +assign vns_csrbank3_dfii_pi0_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd4)); +assign vns_csrbank3_dfii_pi0_baddress0_r = vns_interface3_bank_bus_dat_w[2:0]; +assign vns_csrbank3_dfii_pi0_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd5)); +assign vns_csrbank3_dfii_pi0_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd5)); +assign vns_csrbank3_dfii_pi0_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi0_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd6)); +assign vns_csrbank3_dfii_pi0_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd6)); +assign vns_csrbank3_dfii_pi0_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi0_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd7)); +assign vns_csrbank3_dfii_pi0_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd7)); +assign vns_csrbank3_dfii_pi0_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi0_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd8)); +assign vns_csrbank3_dfii_pi0_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd8)); +assign vns_csrbank3_dfii_pi0_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi0_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd9)); +assign vns_csrbank3_dfii_pi0_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd9)); +assign vns_csrbank3_dfii_pi0_rddata3_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi0_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd10)); +assign vns_csrbank3_dfii_pi0_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd10)); +assign vns_csrbank3_dfii_pi0_rddata2_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi0_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd11)); +assign vns_csrbank3_dfii_pi0_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd11)); +assign vns_csrbank3_dfii_pi0_rddata1_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi0_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd12)); +assign vns_csrbank3_dfii_pi0_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd12)); +assign vns_csrbank3_dfii_pi0_rddata0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi0_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd13)); +assign vns_csrbank3_dfii_pi0_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd13)); +assign vns_csrbank3_dfii_pi1_command0_r = vns_interface3_bank_bus_dat_w[5:0]; +assign vns_csrbank3_dfii_pi1_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd14)); +assign vns_csrbank3_dfii_pi1_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd14)); +assign soc_sdram_phaseinjector1_command_issue_r = vns_interface3_bank_bus_dat_w[0]; +assign soc_sdram_phaseinjector1_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd15)); +assign soc_sdram_phaseinjector1_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd15)); +assign vns_csrbank3_dfii_pi1_address1_r = vns_interface3_bank_bus_dat_w[5:0]; +assign vns_csrbank3_dfii_pi1_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd16)); +assign vns_csrbank3_dfii_pi1_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd16)); +assign vns_csrbank3_dfii_pi1_address0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi1_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd17)); +assign vns_csrbank3_dfii_pi1_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd17)); +assign vns_csrbank3_dfii_pi1_baddress0_r = vns_interface3_bank_bus_dat_w[2:0]; +assign vns_csrbank3_dfii_pi1_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd18)); +assign vns_csrbank3_dfii_pi1_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd18)); +assign vns_csrbank3_dfii_pi1_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi1_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd19)); +assign vns_csrbank3_dfii_pi1_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd19)); +assign vns_csrbank3_dfii_pi1_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi1_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd20)); +assign vns_csrbank3_dfii_pi1_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd20)); +assign vns_csrbank3_dfii_pi1_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi1_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd21)); +assign vns_csrbank3_dfii_pi1_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd21)); +assign vns_csrbank3_dfii_pi1_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi1_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd22)); +assign vns_csrbank3_dfii_pi1_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd22)); +assign vns_csrbank3_dfii_pi1_rddata3_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi1_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd23)); +assign vns_csrbank3_dfii_pi1_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd23)); +assign vns_csrbank3_dfii_pi1_rddata2_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi1_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd24)); +assign vns_csrbank3_dfii_pi1_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd24)); +assign vns_csrbank3_dfii_pi1_rddata1_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi1_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd25)); +assign vns_csrbank3_dfii_pi1_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd25)); +assign vns_csrbank3_dfii_pi1_rddata0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi1_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd26)); +assign vns_csrbank3_dfii_pi1_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd26)); +assign vns_csrbank3_dfii_pi2_command0_r = vns_interface3_bank_bus_dat_w[5:0]; +assign vns_csrbank3_dfii_pi2_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd27)); +assign vns_csrbank3_dfii_pi2_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd27)); +assign soc_sdram_phaseinjector2_command_issue_r = vns_interface3_bank_bus_dat_w[0]; +assign soc_sdram_phaseinjector2_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd28)); +assign soc_sdram_phaseinjector2_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd28)); +assign vns_csrbank3_dfii_pi2_address1_r = vns_interface3_bank_bus_dat_w[5:0]; +assign vns_csrbank3_dfii_pi2_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd29)); +assign vns_csrbank3_dfii_pi2_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd29)); +assign vns_csrbank3_dfii_pi2_address0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi2_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd30)); +assign vns_csrbank3_dfii_pi2_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd30)); +assign vns_csrbank3_dfii_pi2_baddress0_r = vns_interface3_bank_bus_dat_w[2:0]; +assign vns_csrbank3_dfii_pi2_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd31)); +assign vns_csrbank3_dfii_pi2_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd31)); +assign vns_csrbank3_dfii_pi2_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi2_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd32)); +assign vns_csrbank3_dfii_pi2_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd32)); +assign vns_csrbank3_dfii_pi2_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi2_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd33)); +assign vns_csrbank3_dfii_pi2_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd33)); +assign vns_csrbank3_dfii_pi2_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi2_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd34)); +assign vns_csrbank3_dfii_pi2_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd34)); +assign vns_csrbank3_dfii_pi2_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi2_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd35)); +assign vns_csrbank3_dfii_pi2_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd35)); +assign vns_csrbank3_dfii_pi2_rddata3_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi2_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd36)); +assign vns_csrbank3_dfii_pi2_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd36)); +assign vns_csrbank3_dfii_pi2_rddata2_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi2_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd37)); +assign vns_csrbank3_dfii_pi2_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd37)); +assign vns_csrbank3_dfii_pi2_rddata1_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi2_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd38)); +assign vns_csrbank3_dfii_pi2_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd38)); +assign vns_csrbank3_dfii_pi2_rddata0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi2_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd39)); +assign vns_csrbank3_dfii_pi2_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd39)); +assign vns_csrbank3_dfii_pi3_command0_r = vns_interface3_bank_bus_dat_w[5:0]; +assign vns_csrbank3_dfii_pi3_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd40)); +assign vns_csrbank3_dfii_pi3_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd40)); +assign soc_sdram_phaseinjector3_command_issue_r = vns_interface3_bank_bus_dat_w[0]; +assign soc_sdram_phaseinjector3_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd41)); +assign soc_sdram_phaseinjector3_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd41)); +assign vns_csrbank3_dfii_pi3_address1_r = vns_interface3_bank_bus_dat_w[5:0]; +assign vns_csrbank3_dfii_pi3_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd42)); +assign vns_csrbank3_dfii_pi3_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd42)); +assign vns_csrbank3_dfii_pi3_address0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi3_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd43)); +assign vns_csrbank3_dfii_pi3_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd43)); +assign vns_csrbank3_dfii_pi3_baddress0_r = vns_interface3_bank_bus_dat_w[2:0]; +assign vns_csrbank3_dfii_pi3_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd44)); +assign vns_csrbank3_dfii_pi3_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd44)); +assign vns_csrbank3_dfii_pi3_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi3_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd45)); +assign vns_csrbank3_dfii_pi3_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd45)); +assign vns_csrbank3_dfii_pi3_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi3_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd46)); +assign vns_csrbank3_dfii_pi3_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd46)); +assign vns_csrbank3_dfii_pi3_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi3_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd47)); +assign vns_csrbank3_dfii_pi3_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd47)); +assign vns_csrbank3_dfii_pi3_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi3_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd48)); +assign vns_csrbank3_dfii_pi3_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd48)); +assign vns_csrbank3_dfii_pi3_rddata3_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi3_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd49)); +assign vns_csrbank3_dfii_pi3_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd49)); +assign vns_csrbank3_dfii_pi3_rddata2_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi3_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd50)); +assign vns_csrbank3_dfii_pi3_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd50)); +assign vns_csrbank3_dfii_pi3_rddata1_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi3_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd51)); +assign vns_csrbank3_dfii_pi3_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd51)); +assign vns_csrbank3_dfii_pi3_rddata0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi3_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd52)); +assign vns_csrbank3_dfii_pi3_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd52)); +assign vns_csrbank3_dfii_control0_w = soc_sdram_storage[3:0]; +assign vns_csrbank3_dfii_pi0_command0_w = soc_sdram_phaseinjector0_command_storage[5:0]; +assign vns_csrbank3_dfii_pi0_address1_w = soc_sdram_phaseinjector0_address_storage[13:8]; +assign vns_csrbank3_dfii_pi0_address0_w = soc_sdram_phaseinjector0_address_storage[7:0]; +assign vns_csrbank3_dfii_pi0_baddress0_w = soc_sdram_phaseinjector0_baddress_storage[2:0]; +assign vns_csrbank3_dfii_pi0_wrdata3_w = soc_sdram_phaseinjector0_wrdata_storage[31:24]; +assign vns_csrbank3_dfii_pi0_wrdata2_w = soc_sdram_phaseinjector0_wrdata_storage[23:16]; +assign vns_csrbank3_dfii_pi0_wrdata1_w = soc_sdram_phaseinjector0_wrdata_storage[15:8]; +assign vns_csrbank3_dfii_pi0_wrdata0_w = soc_sdram_phaseinjector0_wrdata_storage[7:0]; +assign vns_csrbank3_dfii_pi0_rddata3_w = soc_sdram_phaseinjector0_status[31:24]; +assign vns_csrbank3_dfii_pi0_rddata2_w = soc_sdram_phaseinjector0_status[23:16]; +assign vns_csrbank3_dfii_pi0_rddata1_w = soc_sdram_phaseinjector0_status[15:8]; +assign vns_csrbank3_dfii_pi0_rddata0_w = soc_sdram_phaseinjector0_status[7:0]; +assign soc_sdram_phaseinjector0_we = vns_csrbank3_dfii_pi0_rddata0_we; +assign vns_csrbank3_dfii_pi1_command0_w = soc_sdram_phaseinjector1_command_storage[5:0]; +assign vns_csrbank3_dfii_pi1_address1_w = soc_sdram_phaseinjector1_address_storage[13:8]; +assign vns_csrbank3_dfii_pi1_address0_w = soc_sdram_phaseinjector1_address_storage[7:0]; +assign vns_csrbank3_dfii_pi1_baddress0_w = soc_sdram_phaseinjector1_baddress_storage[2:0]; +assign vns_csrbank3_dfii_pi1_wrdata3_w = soc_sdram_phaseinjector1_wrdata_storage[31:24]; +assign vns_csrbank3_dfii_pi1_wrdata2_w = soc_sdram_phaseinjector1_wrdata_storage[23:16]; +assign vns_csrbank3_dfii_pi1_wrdata1_w = soc_sdram_phaseinjector1_wrdata_storage[15:8]; +assign vns_csrbank3_dfii_pi1_wrdata0_w = soc_sdram_phaseinjector1_wrdata_storage[7:0]; +assign vns_csrbank3_dfii_pi1_rddata3_w = soc_sdram_phaseinjector1_status[31:24]; +assign vns_csrbank3_dfii_pi1_rddata2_w = soc_sdram_phaseinjector1_status[23:16]; +assign vns_csrbank3_dfii_pi1_rddata1_w = soc_sdram_phaseinjector1_status[15:8]; +assign vns_csrbank3_dfii_pi1_rddata0_w = soc_sdram_phaseinjector1_status[7:0]; +assign soc_sdram_phaseinjector1_we = vns_csrbank3_dfii_pi1_rddata0_we; +assign vns_csrbank3_dfii_pi2_command0_w = soc_sdram_phaseinjector2_command_storage[5:0]; +assign vns_csrbank3_dfii_pi2_address1_w = soc_sdram_phaseinjector2_address_storage[13:8]; +assign vns_csrbank3_dfii_pi2_address0_w = soc_sdram_phaseinjector2_address_storage[7:0]; +assign vns_csrbank3_dfii_pi2_baddress0_w = soc_sdram_phaseinjector2_baddress_storage[2:0]; +assign vns_csrbank3_dfii_pi2_wrdata3_w = soc_sdram_phaseinjector2_wrdata_storage[31:24]; +assign vns_csrbank3_dfii_pi2_wrdata2_w = soc_sdram_phaseinjector2_wrdata_storage[23:16]; +assign vns_csrbank3_dfii_pi2_wrdata1_w = soc_sdram_phaseinjector2_wrdata_storage[15:8]; +assign vns_csrbank3_dfii_pi2_wrdata0_w = soc_sdram_phaseinjector2_wrdata_storage[7:0]; +assign vns_csrbank3_dfii_pi2_rddata3_w = soc_sdram_phaseinjector2_status[31:24]; +assign vns_csrbank3_dfii_pi2_rddata2_w = soc_sdram_phaseinjector2_status[23:16]; +assign vns_csrbank3_dfii_pi2_rddata1_w = soc_sdram_phaseinjector2_status[15:8]; +assign vns_csrbank3_dfii_pi2_rddata0_w = soc_sdram_phaseinjector2_status[7:0]; +assign soc_sdram_phaseinjector2_we = vns_csrbank3_dfii_pi2_rddata0_we; +assign vns_csrbank3_dfii_pi3_command0_w = soc_sdram_phaseinjector3_command_storage[5:0]; +assign vns_csrbank3_dfii_pi3_address1_w = soc_sdram_phaseinjector3_address_storage[13:8]; +assign vns_csrbank3_dfii_pi3_address0_w = soc_sdram_phaseinjector3_address_storage[7:0]; +assign vns_csrbank3_dfii_pi3_baddress0_w = soc_sdram_phaseinjector3_baddress_storage[2:0]; +assign vns_csrbank3_dfii_pi3_wrdata3_w = soc_sdram_phaseinjector3_wrdata_storage[31:24]; +assign vns_csrbank3_dfii_pi3_wrdata2_w = soc_sdram_phaseinjector3_wrdata_storage[23:16]; +assign vns_csrbank3_dfii_pi3_wrdata1_w = soc_sdram_phaseinjector3_wrdata_storage[15:8]; +assign vns_csrbank3_dfii_pi3_wrdata0_w = soc_sdram_phaseinjector3_wrdata_storage[7:0]; +assign vns_csrbank3_dfii_pi3_rddata3_w = soc_sdram_phaseinjector3_status[31:24]; +assign vns_csrbank3_dfii_pi3_rddata2_w = soc_sdram_phaseinjector3_status[23:16]; +assign vns_csrbank3_dfii_pi3_rddata1_w = soc_sdram_phaseinjector3_status[15:8]; +assign vns_csrbank3_dfii_pi3_rddata0_w = soc_sdram_phaseinjector3_status[7:0]; +assign soc_sdram_phaseinjector3_we = vns_csrbank3_dfii_pi3_rddata0_we; +assign vns_csrbank4_sel = (vns_interface4_bank_bus_adr[13:9] == 3'd4); +assign vns_csrbank4_load3_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_load3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 1'd0)); +assign vns_csrbank4_load3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 1'd0)); +assign vns_csrbank4_load2_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_load2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 1'd1)); +assign vns_csrbank4_load2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 1'd1)); +assign vns_csrbank4_load1_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_load1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 2'd2)); +assign vns_csrbank4_load1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 2'd2)); +assign vns_csrbank4_load0_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_load0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 2'd3)); +assign vns_csrbank4_load0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 2'd3)); +assign vns_csrbank4_reload3_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_reload3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd4)); +assign vns_csrbank4_reload3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd4)); +assign vns_csrbank4_reload2_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_reload2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd5)); +assign vns_csrbank4_reload2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd5)); +assign vns_csrbank4_reload1_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_reload1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd6)); +assign vns_csrbank4_reload1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd6)); +assign vns_csrbank4_reload0_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_reload0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd7)); +assign vns_csrbank4_reload0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd7)); +assign vns_csrbank4_en0_r = vns_interface4_bank_bus_dat_w[0]; +assign vns_csrbank4_en0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd8)); +assign vns_csrbank4_en0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd8)); +assign vns_csrbank4_update_value0_r = vns_interface4_bank_bus_dat_w[0]; +assign vns_csrbank4_update_value0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd9)); +assign vns_csrbank4_update_value0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd9)); +assign vns_csrbank4_value3_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_value3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd10)); +assign vns_csrbank4_value3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd10)); +assign vns_csrbank4_value2_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_value2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd11)); +assign vns_csrbank4_value2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd11)); +assign vns_csrbank4_value1_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_value1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd12)); +assign vns_csrbank4_value1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd12)); +assign vns_csrbank4_value0_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_value0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd13)); +assign vns_csrbank4_value0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd13)); +assign soc_litedramcore_timer_eventmanager_status_r = vns_interface4_bank_bus_dat_w[0]; +assign soc_litedramcore_timer_eventmanager_status_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd14)); +assign soc_litedramcore_timer_eventmanager_status_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd14)); +assign soc_litedramcore_timer_eventmanager_pending_r = vns_interface4_bank_bus_dat_w[0]; +assign soc_litedramcore_timer_eventmanager_pending_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd15)); +assign soc_litedramcore_timer_eventmanager_pending_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd15)); +assign vns_csrbank4_ev_enable0_r = vns_interface4_bank_bus_dat_w[0]; +assign vns_csrbank4_ev_enable0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 5'd16)); +assign vns_csrbank4_ev_enable0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 5'd16)); +assign vns_csrbank4_load3_w = soc_litedramcore_timer_load_storage[31:24]; +assign vns_csrbank4_load2_w = soc_litedramcore_timer_load_storage[23:16]; +assign vns_csrbank4_load1_w = soc_litedramcore_timer_load_storage[15:8]; +assign vns_csrbank4_load0_w = soc_litedramcore_timer_load_storage[7:0]; +assign vns_csrbank4_reload3_w = soc_litedramcore_timer_reload_storage[31:24]; +assign vns_csrbank4_reload2_w = soc_litedramcore_timer_reload_storage[23:16]; +assign vns_csrbank4_reload1_w = soc_litedramcore_timer_reload_storage[15:8]; +assign vns_csrbank4_reload0_w = soc_litedramcore_timer_reload_storage[7:0]; +assign vns_csrbank4_en0_w = soc_litedramcore_timer_en_storage; +assign vns_csrbank4_update_value0_w = soc_litedramcore_timer_update_value_storage; +assign vns_csrbank4_value3_w = soc_litedramcore_timer_value_status[31:24]; +assign vns_csrbank4_value2_w = soc_litedramcore_timer_value_status[23:16]; +assign vns_csrbank4_value1_w = soc_litedramcore_timer_value_status[15:8]; +assign vns_csrbank4_value0_w = soc_litedramcore_timer_value_status[7:0]; +assign soc_litedramcore_timer_value_we = vns_csrbank4_value0_we; +assign vns_csrbank4_ev_enable0_w = soc_litedramcore_timer_eventmanager_storage; +assign vns_csrbank5_sel = (vns_interface5_bank_bus_adr[13:9] == 2'd3); +assign soc_litedramcore_uart_rxtx_r = vns_interface5_bank_bus_dat_w[7:0]; +assign soc_litedramcore_uart_rxtx_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 1'd0)); +assign soc_litedramcore_uart_rxtx_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 1'd0)); +assign vns_csrbank5_txfull_r = vns_interface5_bank_bus_dat_w[0]; +assign vns_csrbank5_txfull_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 1'd1)); +assign vns_csrbank5_txfull_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 1'd1)); +assign vns_csrbank5_rxempty_r = vns_interface5_bank_bus_dat_w[0]; +assign vns_csrbank5_rxempty_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 2'd2)); +assign vns_csrbank5_rxempty_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 2'd2)); +assign soc_litedramcore_uart_eventmanager_status_r = vns_interface5_bank_bus_dat_w[1:0]; +assign soc_litedramcore_uart_eventmanager_status_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 2'd3)); +assign soc_litedramcore_uart_eventmanager_status_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 2'd3)); +assign soc_litedramcore_uart_eventmanager_pending_r = vns_interface5_bank_bus_dat_w[1:0]; +assign soc_litedramcore_uart_eventmanager_pending_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 3'd4)); +assign soc_litedramcore_uart_eventmanager_pending_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 3'd4)); +assign vns_csrbank5_ev_enable0_r = vns_interface5_bank_bus_dat_w[1:0]; +assign vns_csrbank5_ev_enable0_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 3'd5)); +assign vns_csrbank5_ev_enable0_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 3'd5)); +assign vns_csrbank5_txfull_w = soc_litedramcore_uart_txfull_status; +assign soc_litedramcore_uart_txfull_we = vns_csrbank5_txfull_we; +assign vns_csrbank5_rxempty_w = soc_litedramcore_uart_rxempty_status; +assign soc_litedramcore_uart_rxempty_we = vns_csrbank5_rxempty_we; +assign vns_csrbank5_ev_enable0_w = soc_litedramcore_uart_eventmanager_storage[1:0]; +assign vns_csrbank6_sel = (vns_interface6_bank_bus_adr[13:9] == 2'd2); +assign vns_csrbank6_tuning_word3_r = vns_interface6_bank_bus_dat_w[7:0]; +assign vns_csrbank6_tuning_word3_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 1'd0)); +assign vns_csrbank6_tuning_word3_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 1'd0)); +assign vns_csrbank6_tuning_word2_r = vns_interface6_bank_bus_dat_w[7:0]; +assign vns_csrbank6_tuning_word2_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 1'd1)); +assign vns_csrbank6_tuning_word2_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 1'd1)); +assign vns_csrbank6_tuning_word1_r = vns_interface6_bank_bus_dat_w[7:0]; +assign vns_csrbank6_tuning_word1_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 2'd2)); +assign vns_csrbank6_tuning_word1_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 2'd2)); +assign vns_csrbank6_tuning_word0_r = vns_interface6_bank_bus_dat_w[7:0]; +assign vns_csrbank6_tuning_word0_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 2'd3)); +assign vns_csrbank6_tuning_word0_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 2'd3)); +assign vns_csrbank6_tuning_word3_w = soc_litedramcore_storage[31:24]; +assign vns_csrbank6_tuning_word2_w = soc_litedramcore_storage[23:16]; +assign vns_csrbank6_tuning_word1_w = soc_litedramcore_storage[15:8]; +assign vns_csrbank6_tuning_word0_w = soc_litedramcore_storage[7:0]; +assign vns_adr = soc_litedramcore_interface_adr; +assign vns_we = soc_litedramcore_interface_we; +assign vns_dat_w = soc_litedramcore_interface_dat_w; +assign soc_litedramcore_interface_dat_r = vns_dat_r; +assign vns_interface0_bank_bus_adr = vns_adr; +assign vns_interface1_bank_bus_adr = vns_adr; +assign vns_interface2_bank_bus_adr = vns_adr; +assign vns_interface3_bank_bus_adr = vns_adr; +assign vns_interface4_bank_bus_adr = vns_adr; +assign vns_interface5_bank_bus_adr = vns_adr; +assign vns_interface6_bank_bus_adr = vns_adr; +assign vns_interface0_bank_bus_we = vns_we; +assign vns_interface1_bank_bus_we = vns_we; +assign vns_interface2_bank_bus_we = vns_we; +assign vns_interface3_bank_bus_we = vns_we; +assign vns_interface4_bank_bus_we = vns_we; +assign vns_interface5_bank_bus_we = vns_we; +assign vns_interface6_bank_bus_we = vns_we; +assign vns_interface0_bank_bus_dat_w = vns_dat_w; +assign vns_interface1_bank_bus_dat_w = vns_dat_w; +assign vns_interface2_bank_bus_dat_w = vns_dat_w; +assign vns_interface3_bank_bus_dat_w = vns_dat_w; +assign vns_interface4_bank_bus_dat_w = vns_dat_w; +assign vns_interface5_bank_bus_dat_w = vns_dat_w; +assign vns_interface6_bank_bus_dat_w = vns_dat_w; +assign vns_dat_r = ((((((vns_interface0_bank_bus_dat_r | vns_interface1_bank_bus_dat_r) | vns_interface2_bank_bus_dat_r) | vns_interface3_bank_bus_dat_r) | vns_interface4_bank_bus_dat_r) | vns_interface5_bank_bus_dat_r) | vns_interface6_bank_bus_dat_r); + +// synthesis translate_off +reg dummy_d_338; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed0 <= 1'd0; + case (soc_sdram_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[0]; + end + 1'd1: begin + vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[1]; + end + 2'd2: begin + vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[2]; + end + 2'd3: begin + vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[3]; + end + 3'd4: begin + vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[4]; + end + 3'd5: begin + vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[5]; + end + 3'd6: begin + vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[6]; + end + default: begin + vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[7]; + end + endcase +// synthesis translate_off + dummy_d_338 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_339; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed1 <= 14'd0; + case (soc_sdram_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed1 <= soc_sdram_bankmachine0_cmd_payload_a; + end + 1'd1: begin + vns_rhs_array_muxed1 <= soc_sdram_bankmachine1_cmd_payload_a; + end + 2'd2: begin + vns_rhs_array_muxed1 <= soc_sdram_bankmachine2_cmd_payload_a; + end + 2'd3: begin + vns_rhs_array_muxed1 <= soc_sdram_bankmachine3_cmd_payload_a; + end + 3'd4: begin + vns_rhs_array_muxed1 <= soc_sdram_bankmachine4_cmd_payload_a; + end + 3'd5: begin + vns_rhs_array_muxed1 <= soc_sdram_bankmachine5_cmd_payload_a; + end + 3'd6: begin + vns_rhs_array_muxed1 <= soc_sdram_bankmachine6_cmd_payload_a; + end + default: begin + vns_rhs_array_muxed1 <= soc_sdram_bankmachine7_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_339 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_340; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed2 <= 3'd0; + case (soc_sdram_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed2 <= soc_sdram_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + vns_rhs_array_muxed2 <= soc_sdram_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + vns_rhs_array_muxed2 <= soc_sdram_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + vns_rhs_array_muxed2 <= soc_sdram_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + vns_rhs_array_muxed2 <= soc_sdram_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + vns_rhs_array_muxed2 <= soc_sdram_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + vns_rhs_array_muxed2 <= soc_sdram_bankmachine6_cmd_payload_ba; + end + default: begin + vns_rhs_array_muxed2 <= soc_sdram_bankmachine7_cmd_payload_ba; + end + endcase +// synthesis translate_off + dummy_d_340 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_341; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed3 <= 1'd0; + case (soc_sdram_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed3 <= soc_sdram_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + vns_rhs_array_muxed3 <= soc_sdram_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + vns_rhs_array_muxed3 <= soc_sdram_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + vns_rhs_array_muxed3 <= soc_sdram_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + vns_rhs_array_muxed3 <= soc_sdram_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + vns_rhs_array_muxed3 <= soc_sdram_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + vns_rhs_array_muxed3 <= soc_sdram_bankmachine6_cmd_payload_is_read; + end + default: begin + vns_rhs_array_muxed3 <= soc_sdram_bankmachine7_cmd_payload_is_read; + end + endcase +// synthesis translate_off + dummy_d_341 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_342; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed4 <= 1'd0; + case (soc_sdram_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed4 <= soc_sdram_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + vns_rhs_array_muxed4 <= soc_sdram_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + vns_rhs_array_muxed4 <= soc_sdram_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + vns_rhs_array_muxed4 <= soc_sdram_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + vns_rhs_array_muxed4 <= soc_sdram_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + vns_rhs_array_muxed4 <= soc_sdram_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + vns_rhs_array_muxed4 <= soc_sdram_bankmachine6_cmd_payload_is_write; + end + default: begin + vns_rhs_array_muxed4 <= soc_sdram_bankmachine7_cmd_payload_is_write; + end + endcase +// synthesis translate_off + dummy_d_342 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_343; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed5 <= 1'd0; + case (soc_sdram_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed5 <= soc_sdram_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + vns_rhs_array_muxed5 <= soc_sdram_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + vns_rhs_array_muxed5 <= soc_sdram_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + vns_rhs_array_muxed5 <= soc_sdram_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + vns_rhs_array_muxed5 <= soc_sdram_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + vns_rhs_array_muxed5 <= soc_sdram_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + vns_rhs_array_muxed5 <= soc_sdram_bankmachine6_cmd_payload_is_cmd; + end + default: begin + vns_rhs_array_muxed5 <= soc_sdram_bankmachine7_cmd_payload_is_cmd; + end + endcase +// synthesis translate_off + dummy_d_343 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_344; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed0 <= 1'd0; + case (soc_sdram_choose_cmd_grant) + 1'd0: begin + vns_t_array_muxed0 <= soc_sdram_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + vns_t_array_muxed0 <= soc_sdram_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + vns_t_array_muxed0 <= soc_sdram_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + vns_t_array_muxed0 <= soc_sdram_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + vns_t_array_muxed0 <= soc_sdram_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + vns_t_array_muxed0 <= soc_sdram_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + vns_t_array_muxed0 <= soc_sdram_bankmachine6_cmd_payload_cas; + end + default: begin + vns_t_array_muxed0 <= soc_sdram_bankmachine7_cmd_payload_cas; + end + endcase +// synthesis translate_off + dummy_d_344 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_345; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed1 <= 1'd0; + case (soc_sdram_choose_cmd_grant) + 1'd0: begin + vns_t_array_muxed1 <= soc_sdram_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + vns_t_array_muxed1 <= soc_sdram_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + vns_t_array_muxed1 <= soc_sdram_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + vns_t_array_muxed1 <= soc_sdram_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + vns_t_array_muxed1 <= soc_sdram_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + vns_t_array_muxed1 <= soc_sdram_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + vns_t_array_muxed1 <= soc_sdram_bankmachine6_cmd_payload_ras; + end + default: begin + vns_t_array_muxed1 <= soc_sdram_bankmachine7_cmd_payload_ras; + end + endcase +// synthesis translate_off + dummy_d_345 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_346; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed2 <= 1'd0; + case (soc_sdram_choose_cmd_grant) + 1'd0: begin + vns_t_array_muxed2 <= soc_sdram_bankmachine0_cmd_payload_we; + end + 1'd1: begin + vns_t_array_muxed2 <= soc_sdram_bankmachine1_cmd_payload_we; + end + 2'd2: begin + vns_t_array_muxed2 <= soc_sdram_bankmachine2_cmd_payload_we; + end + 2'd3: begin + vns_t_array_muxed2 <= soc_sdram_bankmachine3_cmd_payload_we; + end + 3'd4: begin + vns_t_array_muxed2 <= soc_sdram_bankmachine4_cmd_payload_we; + end + 3'd5: begin + vns_t_array_muxed2 <= soc_sdram_bankmachine5_cmd_payload_we; + end + 3'd6: begin + vns_t_array_muxed2 <= soc_sdram_bankmachine6_cmd_payload_we; + end + default: begin + vns_t_array_muxed2 <= soc_sdram_bankmachine7_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_346 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_347; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed6 <= 1'd0; + case (soc_sdram_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[0]; + end + 1'd1: begin + vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[1]; + end + 2'd2: begin + vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[2]; + end + 2'd3: begin + vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[3]; + end + 3'd4: begin + vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[4]; + end + 3'd5: begin + vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[5]; + end + 3'd6: begin + vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[6]; + end + default: begin + vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[7]; + end + endcase +// synthesis translate_off + dummy_d_347 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_348; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed7 <= 14'd0; + case (soc_sdram_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed7 <= soc_sdram_bankmachine0_cmd_payload_a; + end + 1'd1: begin + vns_rhs_array_muxed7 <= soc_sdram_bankmachine1_cmd_payload_a; + end + 2'd2: begin + vns_rhs_array_muxed7 <= soc_sdram_bankmachine2_cmd_payload_a; + end + 2'd3: begin + vns_rhs_array_muxed7 <= soc_sdram_bankmachine3_cmd_payload_a; + end + 3'd4: begin + vns_rhs_array_muxed7 <= soc_sdram_bankmachine4_cmd_payload_a; + end + 3'd5: begin + vns_rhs_array_muxed7 <= soc_sdram_bankmachine5_cmd_payload_a; + end + 3'd6: begin + vns_rhs_array_muxed7 <= soc_sdram_bankmachine6_cmd_payload_a; + end + default: begin + vns_rhs_array_muxed7 <= soc_sdram_bankmachine7_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_348 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_349; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed8 <= 3'd0; + case (soc_sdram_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed8 <= soc_sdram_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + vns_rhs_array_muxed8 <= soc_sdram_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + vns_rhs_array_muxed8 <= soc_sdram_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + vns_rhs_array_muxed8 <= soc_sdram_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + vns_rhs_array_muxed8 <= soc_sdram_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + vns_rhs_array_muxed8 <= soc_sdram_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + vns_rhs_array_muxed8 <= soc_sdram_bankmachine6_cmd_payload_ba; + end + default: begin + vns_rhs_array_muxed8 <= soc_sdram_bankmachine7_cmd_payload_ba; + end + endcase +// synthesis translate_off + dummy_d_349 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_350; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed9 <= 1'd0; + case (soc_sdram_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed9 <= soc_sdram_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + vns_rhs_array_muxed9 <= soc_sdram_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + vns_rhs_array_muxed9 <= soc_sdram_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + vns_rhs_array_muxed9 <= soc_sdram_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + vns_rhs_array_muxed9 <= soc_sdram_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + vns_rhs_array_muxed9 <= soc_sdram_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + vns_rhs_array_muxed9 <= soc_sdram_bankmachine6_cmd_payload_is_read; + end + default: begin + vns_rhs_array_muxed9 <= soc_sdram_bankmachine7_cmd_payload_is_read; + end + endcase +// synthesis translate_off + dummy_d_350 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_351; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed10 <= 1'd0; + case (soc_sdram_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed10 <= soc_sdram_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + vns_rhs_array_muxed10 <= soc_sdram_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + vns_rhs_array_muxed10 <= soc_sdram_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + vns_rhs_array_muxed10 <= soc_sdram_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + vns_rhs_array_muxed10 <= soc_sdram_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + vns_rhs_array_muxed10 <= soc_sdram_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + vns_rhs_array_muxed10 <= soc_sdram_bankmachine6_cmd_payload_is_write; + end + default: begin + vns_rhs_array_muxed10 <= soc_sdram_bankmachine7_cmd_payload_is_write; + end + endcase +// synthesis translate_off + dummy_d_351 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_352; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed11 <= 1'd0; + case (soc_sdram_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed11 <= soc_sdram_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + vns_rhs_array_muxed11 <= soc_sdram_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + vns_rhs_array_muxed11 <= soc_sdram_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + vns_rhs_array_muxed11 <= soc_sdram_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + vns_rhs_array_muxed11 <= soc_sdram_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + vns_rhs_array_muxed11 <= soc_sdram_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + vns_rhs_array_muxed11 <= soc_sdram_bankmachine6_cmd_payload_is_cmd; + end + default: begin + vns_rhs_array_muxed11 <= soc_sdram_bankmachine7_cmd_payload_is_cmd; + end + endcase +// synthesis translate_off + dummy_d_352 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_353; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed3 <= 1'd0; + case (soc_sdram_choose_req_grant) + 1'd0: begin + vns_t_array_muxed3 <= soc_sdram_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + vns_t_array_muxed3 <= soc_sdram_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + vns_t_array_muxed3 <= soc_sdram_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + vns_t_array_muxed3 <= soc_sdram_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + vns_t_array_muxed3 <= soc_sdram_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + vns_t_array_muxed3 <= soc_sdram_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + vns_t_array_muxed3 <= soc_sdram_bankmachine6_cmd_payload_cas; + end + default: begin + vns_t_array_muxed3 <= soc_sdram_bankmachine7_cmd_payload_cas; + end + endcase +// synthesis translate_off + dummy_d_353 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_354; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed4 <= 1'd0; + case (soc_sdram_choose_req_grant) + 1'd0: begin + vns_t_array_muxed4 <= soc_sdram_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + vns_t_array_muxed4 <= soc_sdram_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + vns_t_array_muxed4 <= soc_sdram_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + vns_t_array_muxed4 <= soc_sdram_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + vns_t_array_muxed4 <= soc_sdram_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + vns_t_array_muxed4 <= soc_sdram_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + vns_t_array_muxed4 <= soc_sdram_bankmachine6_cmd_payload_ras; + end + default: begin + vns_t_array_muxed4 <= soc_sdram_bankmachine7_cmd_payload_ras; + end + endcase +// synthesis translate_off + dummy_d_354 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_355; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed5 <= 1'd0; + case (soc_sdram_choose_req_grant) + 1'd0: begin + vns_t_array_muxed5 <= soc_sdram_bankmachine0_cmd_payload_we; + end + 1'd1: begin + vns_t_array_muxed5 <= soc_sdram_bankmachine1_cmd_payload_we; + end + 2'd2: begin + vns_t_array_muxed5 <= soc_sdram_bankmachine2_cmd_payload_we; + end + 2'd3: begin + vns_t_array_muxed5 <= soc_sdram_bankmachine3_cmd_payload_we; + end + 3'd4: begin + vns_t_array_muxed5 <= soc_sdram_bankmachine4_cmd_payload_we; + end + 3'd5: begin + vns_t_array_muxed5 <= soc_sdram_bankmachine5_cmd_payload_we; + end + 3'd6: begin + vns_t_array_muxed5 <= soc_sdram_bankmachine6_cmd_payload_we; + end + default: begin + vns_t_array_muxed5 <= soc_sdram_bankmachine7_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_355 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_356; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed12 <= 21'd0; + case (vns_roundrobin0_grant) + 1'd0: begin + vns_rhs_array_muxed12 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]}; + end + default: begin + vns_rhs_array_muxed12 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_356 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_357; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed13 <= 1'd0; + case (vns_roundrobin0_grant) + 1'd0: begin + vns_rhs_array_muxed13 <= soc_port_cmd_payload_we; + end + default: begin + vns_rhs_array_muxed13 <= soc_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_357 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_358; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed14 <= 1'd0; + case (vns_roundrobin0_grant) + 1'd0: begin + vns_rhs_array_muxed14 <= (((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); + end + default: begin + vns_rhs_array_muxed14 <= (((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_358 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_359; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed15 <= 21'd0; + case (vns_roundrobin1_grant) + 1'd0: begin + vns_rhs_array_muxed15 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]}; + end + default: begin + vns_rhs_array_muxed15 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_359 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_360; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed16 <= 1'd0; + case (vns_roundrobin1_grant) + 1'd0: begin + vns_rhs_array_muxed16 <= soc_port_cmd_payload_we; + end + default: begin + vns_rhs_array_muxed16 <= soc_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_360 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_361; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed17 <= 1'd0; + case (vns_roundrobin1_grant) + 1'd0: begin + vns_rhs_array_muxed17 <= (((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); + end + default: begin + vns_rhs_array_muxed17 <= (((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_361 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_362; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed18 <= 21'd0; + case (vns_roundrobin2_grant) + 1'd0: begin + vns_rhs_array_muxed18 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]}; + end + default: begin + vns_rhs_array_muxed18 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_362 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_363; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed19 <= 1'd0; + case (vns_roundrobin2_grant) + 1'd0: begin + vns_rhs_array_muxed19 <= soc_port_cmd_payload_we; + end + default: begin + vns_rhs_array_muxed19 <= soc_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_363 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_364; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed20 <= 1'd0; + case (vns_roundrobin2_grant) + 1'd0: begin + vns_rhs_array_muxed20 <= (((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); + end + default: begin + vns_rhs_array_muxed20 <= (((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_364 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_365; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed21 <= 21'd0; + case (vns_roundrobin3_grant) + 1'd0: begin + vns_rhs_array_muxed21 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]}; + end + default: begin + vns_rhs_array_muxed21 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_365 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_366; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed22 <= 1'd0; + case (vns_roundrobin3_grant) + 1'd0: begin + vns_rhs_array_muxed22 <= soc_port_cmd_payload_we; + end + default: begin + vns_rhs_array_muxed22 <= soc_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_366 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_367; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed23 <= 1'd0; + case (vns_roundrobin3_grant) + 1'd0: begin + vns_rhs_array_muxed23 <= (((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); + end + default: begin + vns_rhs_array_muxed23 <= (((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_367 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_368; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed24 <= 21'd0; + case (vns_roundrobin4_grant) + 1'd0: begin + vns_rhs_array_muxed24 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]}; + end + default: begin + vns_rhs_array_muxed24 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_368 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_369; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed25 <= 1'd0; + case (vns_roundrobin4_grant) + 1'd0: begin + vns_rhs_array_muxed25 <= soc_port_cmd_payload_we; + end + default: begin + vns_rhs_array_muxed25 <= soc_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_369 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_370; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed26 <= 1'd0; + case (vns_roundrobin4_grant) + 1'd0: begin + vns_rhs_array_muxed26 <= (((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); + end + default: begin + vns_rhs_array_muxed26 <= (((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_370 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_371; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed27 <= 21'd0; + case (vns_roundrobin5_grant) + 1'd0: begin + vns_rhs_array_muxed27 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]}; + end + default: begin + vns_rhs_array_muxed27 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_371 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_372; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed28 <= 1'd0; + case (vns_roundrobin5_grant) + 1'd0: begin + vns_rhs_array_muxed28 <= soc_port_cmd_payload_we; + end + default: begin + vns_rhs_array_muxed28 <= soc_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_372 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_373; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed29 <= 1'd0; + case (vns_roundrobin5_grant) + 1'd0: begin + vns_rhs_array_muxed29 <= (((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); + end + default: begin + vns_rhs_array_muxed29 <= (((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_373 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_374; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed30 <= 21'd0; + case (vns_roundrobin6_grant) + 1'd0: begin + vns_rhs_array_muxed30 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]}; + end + default: begin + vns_rhs_array_muxed30 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_374 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_375; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed31 <= 1'd0; + case (vns_roundrobin6_grant) + 1'd0: begin + vns_rhs_array_muxed31 <= soc_port_cmd_payload_we; + end + default: begin + vns_rhs_array_muxed31 <= soc_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_375 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_376; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed32 <= 1'd0; + case (vns_roundrobin6_grant) + 1'd0: begin + vns_rhs_array_muxed32 <= (((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); + end + default: begin + vns_rhs_array_muxed32 <= (((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_376 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_377; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed33 <= 21'd0; + case (vns_roundrobin7_grant) + 1'd0: begin + vns_rhs_array_muxed33 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]}; + end + default: begin + vns_rhs_array_muxed33 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_377 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_378; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed34 <= 1'd0; + case (vns_roundrobin7_grant) + 1'd0: begin + vns_rhs_array_muxed34 <= soc_port_cmd_payload_we; + end + default: begin + vns_rhs_array_muxed34 <= soc_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_378 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_379; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed35 <= 1'd0; + case (vns_roundrobin7_grant) + 1'd0: begin + vns_rhs_array_muxed35 <= (((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_port_cmd_valid); + end + default: begin + vns_rhs_array_muxed35 <= (((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))))) & soc_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_379 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_380; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed36 <= 30'd0; + case (vns_grant) + 1'd0: begin + vns_rhs_array_muxed36 <= soc_litedramcore_cpu_ibus_adr; + end + default: begin + vns_rhs_array_muxed36 <= soc_litedramcore_cpu_dbus_adr; + end + endcase +// synthesis translate_off + dummy_d_380 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_381; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed37 <= 32'd0; + case (vns_grant) + 1'd0: begin + vns_rhs_array_muxed37 <= soc_litedramcore_cpu_ibus_dat_w; + end + default: begin + vns_rhs_array_muxed37 <= soc_litedramcore_cpu_dbus_dat_w; + end + endcase +// synthesis translate_off + dummy_d_381 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_382; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed38 <= 4'd0; + case (vns_grant) + 1'd0: begin + vns_rhs_array_muxed38 <= soc_litedramcore_cpu_ibus_sel; + end + default: begin + vns_rhs_array_muxed38 <= soc_litedramcore_cpu_dbus_sel; + end + endcase +// synthesis translate_off + dummy_d_382 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_383; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed39 <= 1'd0; + case (vns_grant) + 1'd0: begin + vns_rhs_array_muxed39 <= soc_litedramcore_cpu_ibus_cyc; + end + default: begin + vns_rhs_array_muxed39 <= soc_litedramcore_cpu_dbus_cyc; + end + endcase +// synthesis translate_off + dummy_d_383 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_384; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed40 <= 1'd0; + case (vns_grant) + 1'd0: begin + vns_rhs_array_muxed40 <= soc_litedramcore_cpu_ibus_stb; + end + default: begin + vns_rhs_array_muxed40 <= soc_litedramcore_cpu_dbus_stb; + end + endcase +// synthesis translate_off + dummy_d_384 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_385; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed41 <= 1'd0; + case (vns_grant) + 1'd0: begin + vns_rhs_array_muxed41 <= soc_litedramcore_cpu_ibus_we; + end + default: begin + vns_rhs_array_muxed41 <= soc_litedramcore_cpu_dbus_we; + end + endcase +// synthesis translate_off + dummy_d_385 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_386; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed42 <= 3'd0; + case (vns_grant) + 1'd0: begin + vns_rhs_array_muxed42 <= soc_litedramcore_cpu_ibus_cti; + end + default: begin + vns_rhs_array_muxed42 <= soc_litedramcore_cpu_dbus_cti; + end + endcase +// synthesis translate_off + dummy_d_386 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_387; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed43 <= 2'd0; + case (vns_grant) + 1'd0: begin + vns_rhs_array_muxed43 <= soc_litedramcore_cpu_ibus_bte; + end + default: begin + vns_rhs_array_muxed43 <= soc_litedramcore_cpu_dbus_bte; + end + endcase +// synthesis translate_off + dummy_d_387 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_388; +// synthesis translate_on +always @(*) begin + vns_array_muxed0 <= 3'd0; + case (soc_sdram_steerer_sel0) + 1'd0: begin + vns_array_muxed0 <= soc_sdram_nop_ba[2:0]; + end + 1'd1: begin + vns_array_muxed0 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + vns_array_muxed0 <= soc_sdram_choose_req_cmd_payload_ba[2:0]; + end + default: begin + vns_array_muxed0 <= soc_sdram_cmd_payload_ba[2:0]; + end + endcase +// synthesis translate_off + dummy_d_388 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_389; +// synthesis translate_on +always @(*) begin + vns_array_muxed1 <= 14'd0; + case (soc_sdram_steerer_sel0) + 1'd0: begin + vns_array_muxed1 <= soc_sdram_nop_a; + end + 1'd1: begin + vns_array_muxed1 <= soc_sdram_choose_cmd_cmd_payload_a; + end + 2'd2: begin + vns_array_muxed1 <= soc_sdram_choose_req_cmd_payload_a; + end + default: begin + vns_array_muxed1 <= soc_sdram_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_389 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_390; +// synthesis translate_on +always @(*) begin + vns_array_muxed2 <= 1'd0; + case (soc_sdram_steerer_sel0) + 1'd0: begin + vns_array_muxed2 <= 1'd0; + end + 1'd1: begin + vns_array_muxed2 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + vns_array_muxed2 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas); + end + default: begin + vns_array_muxed2 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas); + end + endcase +// synthesis translate_off + dummy_d_390 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_391; +// synthesis translate_on +always @(*) begin + vns_array_muxed3 <= 1'd0; + case (soc_sdram_steerer_sel0) + 1'd0: begin + vns_array_muxed3 <= 1'd0; + end + 1'd1: begin + vns_array_muxed3 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + vns_array_muxed3 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras); + end + default: begin + vns_array_muxed3 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras); + end + endcase +// synthesis translate_off + dummy_d_391 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_392; +// synthesis translate_on +always @(*) begin + vns_array_muxed4 <= 1'd0; + case (soc_sdram_steerer_sel0) + 1'd0: begin + vns_array_muxed4 <= 1'd0; + end + 1'd1: begin + vns_array_muxed4 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we); + end + 2'd2: begin + vns_array_muxed4 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we); + end + default: begin + vns_array_muxed4 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we); + end + endcase +// synthesis translate_off + dummy_d_392 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_393; +// synthesis translate_on +always @(*) begin + vns_array_muxed5 <= 1'd0; + case (soc_sdram_steerer_sel0) + 1'd0: begin + vns_array_muxed5 <= 1'd0; + end + 1'd1: begin + vns_array_muxed5 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + vns_array_muxed5 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read); + end + default: begin + vns_array_muxed5 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read); + end + endcase +// synthesis translate_off + dummy_d_393 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_394; +// synthesis translate_on +always @(*) begin + vns_array_muxed6 <= 1'd0; + case (soc_sdram_steerer_sel0) + 1'd0: begin + vns_array_muxed6 <= 1'd0; + end + 1'd1: begin + vns_array_muxed6 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + vns_array_muxed6 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write); + end + default: begin + vns_array_muxed6 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write); + end + endcase +// synthesis translate_off + dummy_d_394 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_395; +// synthesis translate_on +always @(*) begin + vns_array_muxed7 <= 3'd0; + case (soc_sdram_steerer_sel1) + 1'd0: begin + vns_array_muxed7 <= soc_sdram_nop_ba[2:0]; + end + 1'd1: begin + vns_array_muxed7 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + vns_array_muxed7 <= soc_sdram_choose_req_cmd_payload_ba[2:0]; + end + default: begin + vns_array_muxed7 <= soc_sdram_cmd_payload_ba[2:0]; + end + endcase +// synthesis translate_off + dummy_d_395 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_396; +// synthesis translate_on +always @(*) begin + vns_array_muxed8 <= 14'd0; + case (soc_sdram_steerer_sel1) + 1'd0: begin + vns_array_muxed8 <= soc_sdram_nop_a; + end + 1'd1: begin + vns_array_muxed8 <= soc_sdram_choose_cmd_cmd_payload_a; + end + 2'd2: begin + vns_array_muxed8 <= soc_sdram_choose_req_cmd_payload_a; + end + default: begin + vns_array_muxed8 <= soc_sdram_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_396 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_397; +// synthesis translate_on +always @(*) begin + vns_array_muxed9 <= 1'd0; + case (soc_sdram_steerer_sel1) + 1'd0: begin + vns_array_muxed9 <= 1'd0; + end + 1'd1: begin + vns_array_muxed9 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + vns_array_muxed9 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas); + end + default: begin + vns_array_muxed9 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas); + end + endcase +// synthesis translate_off + dummy_d_397 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_398; +// synthesis translate_on +always @(*) begin + vns_array_muxed10 <= 1'd0; + case (soc_sdram_steerer_sel1) + 1'd0: begin + vns_array_muxed10 <= 1'd0; + end + 1'd1: begin + vns_array_muxed10 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + vns_array_muxed10 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras); + end + default: begin + vns_array_muxed10 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras); + end + endcase +// synthesis translate_off + dummy_d_398 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_399; +// synthesis translate_on +always @(*) begin + vns_array_muxed11 <= 1'd0; + case (soc_sdram_steerer_sel1) + 1'd0: begin + vns_array_muxed11 <= 1'd0; + end + 1'd1: begin + vns_array_muxed11 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we); + end + 2'd2: begin + vns_array_muxed11 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we); + end + default: begin + vns_array_muxed11 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we); + end + endcase +// synthesis translate_off + dummy_d_399 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_400; +// synthesis translate_on +always @(*) begin + vns_array_muxed12 <= 1'd0; + case (soc_sdram_steerer_sel1) + 1'd0: begin + vns_array_muxed12 <= 1'd0; + end + 1'd1: begin + vns_array_muxed12 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + vns_array_muxed12 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read); + end + default: begin + vns_array_muxed12 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read); + end + endcase +// synthesis translate_off + dummy_d_400 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_401; +// synthesis translate_on +always @(*) begin + vns_array_muxed13 <= 1'd0; + case (soc_sdram_steerer_sel1) + 1'd0: begin + vns_array_muxed13 <= 1'd0; + end + 1'd1: begin + vns_array_muxed13 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + vns_array_muxed13 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write); + end + default: begin + vns_array_muxed13 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write); + end + endcase +// synthesis translate_off + dummy_d_401 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_402; +// synthesis translate_on +always @(*) begin + vns_array_muxed14 <= 3'd0; + case (soc_sdram_steerer_sel2) + 1'd0: begin + vns_array_muxed14 <= soc_sdram_nop_ba[2:0]; + end + 1'd1: begin + vns_array_muxed14 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + vns_array_muxed14 <= soc_sdram_choose_req_cmd_payload_ba[2:0]; + end + default: begin + vns_array_muxed14 <= soc_sdram_cmd_payload_ba[2:0]; + end + endcase +// synthesis translate_off + dummy_d_402 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_403; +// synthesis translate_on +always @(*) begin + vns_array_muxed15 <= 14'd0; + case (soc_sdram_steerer_sel2) + 1'd0: begin + vns_array_muxed15 <= soc_sdram_nop_a; + end + 1'd1: begin + vns_array_muxed15 <= soc_sdram_choose_cmd_cmd_payload_a; + end + 2'd2: begin + vns_array_muxed15 <= soc_sdram_choose_req_cmd_payload_a; + end + default: begin + vns_array_muxed15 <= soc_sdram_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_403 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_404; +// synthesis translate_on +always @(*) begin + vns_array_muxed16 <= 1'd0; + case (soc_sdram_steerer_sel2) + 1'd0: begin + vns_array_muxed16 <= 1'd0; + end + 1'd1: begin + vns_array_muxed16 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + vns_array_muxed16 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas); + end + default: begin + vns_array_muxed16 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas); + end + endcase +// synthesis translate_off + dummy_d_404 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_405; +// synthesis translate_on +always @(*) begin + vns_array_muxed17 <= 1'd0; + case (soc_sdram_steerer_sel2) + 1'd0: begin + vns_array_muxed17 <= 1'd0; + end + 1'd1: begin + vns_array_muxed17 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + vns_array_muxed17 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras); + end + default: begin + vns_array_muxed17 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras); + end + endcase +// synthesis translate_off + dummy_d_405 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_406; +// synthesis translate_on +always @(*) begin + vns_array_muxed18 <= 1'd0; + case (soc_sdram_steerer_sel2) + 1'd0: begin + vns_array_muxed18 <= 1'd0; + end + 1'd1: begin + vns_array_muxed18 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we); + end + 2'd2: begin + vns_array_muxed18 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we); + end + default: begin + vns_array_muxed18 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we); + end + endcase +// synthesis translate_off + dummy_d_406 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_407; +// synthesis translate_on +always @(*) begin + vns_array_muxed19 <= 1'd0; + case (soc_sdram_steerer_sel2) + 1'd0: begin + vns_array_muxed19 <= 1'd0; + end + 1'd1: begin + vns_array_muxed19 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + vns_array_muxed19 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read); + end + default: begin + vns_array_muxed19 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read); + end + endcase +// synthesis translate_off + dummy_d_407 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_408; +// synthesis translate_on +always @(*) begin + vns_array_muxed20 <= 1'd0; + case (soc_sdram_steerer_sel2) + 1'd0: begin + vns_array_muxed20 <= 1'd0; + end + 1'd1: begin + vns_array_muxed20 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + vns_array_muxed20 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write); + end + default: begin + vns_array_muxed20 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write); + end + endcase +// synthesis translate_off + dummy_d_408 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_409; +// synthesis translate_on +always @(*) begin + vns_array_muxed21 <= 3'd0; + case (soc_sdram_steerer_sel3) + 1'd0: begin + vns_array_muxed21 <= soc_sdram_nop_ba[2:0]; + end + 1'd1: begin + vns_array_muxed21 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + vns_array_muxed21 <= soc_sdram_choose_req_cmd_payload_ba[2:0]; + end + default: begin + vns_array_muxed21 <= soc_sdram_cmd_payload_ba[2:0]; + end + endcase +// synthesis translate_off + dummy_d_409 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_410; +// synthesis translate_on +always @(*) begin + vns_array_muxed22 <= 14'd0; + case (soc_sdram_steerer_sel3) + 1'd0: begin + vns_array_muxed22 <= soc_sdram_nop_a; + end + 1'd1: begin + vns_array_muxed22 <= soc_sdram_choose_cmd_cmd_payload_a; + end + 2'd2: begin + vns_array_muxed22 <= soc_sdram_choose_req_cmd_payload_a; + end + default: begin + vns_array_muxed22 <= soc_sdram_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_410 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_411; +// synthesis translate_on +always @(*) begin + vns_array_muxed23 <= 1'd0; + case (soc_sdram_steerer_sel3) + 1'd0: begin + vns_array_muxed23 <= 1'd0; + end + 1'd1: begin + vns_array_muxed23 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + vns_array_muxed23 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas); + end + default: begin + vns_array_muxed23 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas); + end + endcase +// synthesis translate_off + dummy_d_411 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_412; +// synthesis translate_on +always @(*) begin + vns_array_muxed24 <= 1'd0; + case (soc_sdram_steerer_sel3) + 1'd0: begin + vns_array_muxed24 <= 1'd0; + end + 1'd1: begin + vns_array_muxed24 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + vns_array_muxed24 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras); + end + default: begin + vns_array_muxed24 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras); + end + endcase +// synthesis translate_off + dummy_d_412 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_413; +// synthesis translate_on +always @(*) begin + vns_array_muxed25 <= 1'd0; + case (soc_sdram_steerer_sel3) + 1'd0: begin + vns_array_muxed25 <= 1'd0; + end + 1'd1: begin + vns_array_muxed25 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we); + end + 2'd2: begin + vns_array_muxed25 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we); + end + default: begin + vns_array_muxed25 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we); + end + endcase +// synthesis translate_off + dummy_d_413 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_414; +// synthesis translate_on +always @(*) begin + vns_array_muxed26 <= 1'd0; + case (soc_sdram_steerer_sel3) + 1'd0: begin + vns_array_muxed26 <= 1'd0; + end + 1'd1: begin + vns_array_muxed26 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + vns_array_muxed26 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read); + end + default: begin + vns_array_muxed26 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read); + end + endcase +// synthesis translate_off + dummy_d_414 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_415; +// synthesis translate_on +always @(*) begin + vns_array_muxed27 <= 1'd0; + case (soc_sdram_steerer_sel3) + 1'd0: begin + vns_array_muxed27 <= 1'd0; + end + 1'd1: begin + vns_array_muxed27 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + vns_array_muxed27 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write); + end + default: begin + vns_array_muxed27 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write); + end + endcase +// synthesis translate_off + dummy_d_415 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_rx = vns_regs1; +assign vns_xilinxasyncresetsynchronizerimpl0 = ((~soc_sys_pll_locked) | soc_sys_pll_reset); +assign vns_xilinxasyncresetsynchronizerimpl1 = ((~soc_sys_pll_locked) | soc_sys_pll_reset); +assign vns_xilinxasyncresetsynchronizerimpl2 = ((~soc_sys_pll_locked) | soc_sys_pll_reset); +assign vns_xilinxasyncresetsynchronizerimpl3 = ((~soc_iodelay_pll_locked) | soc_iodelay_pll_reset); + +always @(posedge iodelay_clk) begin + if ((soc_reset_counter != 1'd0)) begin + soc_reset_counter <= (soc_reset_counter - 1'd1); + end else begin + soc_ic_reset <= 1'd0; + end + if (iodelay_rst) begin + soc_reset_counter <= 4'd15; + soc_ic_reset <= 1'd1; + end +end + +always @(posedge sys_clk) begin + if ((soc_litedramcore_soccontroller_bus_errors != 32'd4294967295)) begin + if (soc_litedramcore_soccontroller_bus_error) begin + soc_litedramcore_soccontroller_bus_errors <= (soc_litedramcore_soccontroller_bus_errors + 1'd1); + end + end + soc_litedramcore_litedramcore_ram_bus_ack <= 1'd0; + if (((soc_litedramcore_litedramcore_ram_bus_cyc & soc_litedramcore_litedramcore_ram_bus_stb) & (~soc_litedramcore_litedramcore_ram_bus_ack))) begin + soc_litedramcore_litedramcore_ram_bus_ack <= 1'd1; + end + soc_litedramcore_ram_bus_ram_bus_ack <= 1'd0; + if (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & (~soc_litedramcore_ram_bus_ram_bus_ack))) begin + soc_litedramcore_ram_bus_ram_bus_ack <= 1'd1; + end + soc_litedramcore_sink_ready <= 1'd0; + if (((soc_litedramcore_sink_valid & (~soc_litedramcore_tx_busy)) & (~soc_litedramcore_sink_ready))) begin + soc_litedramcore_tx_reg <= soc_litedramcore_sink_payload_data; + soc_litedramcore_tx_bitcount <= 1'd0; + soc_litedramcore_tx_busy <= 1'd1; + serial_tx <= 1'd0; + end else begin + if ((soc_litedramcore_uart_clk_txen & soc_litedramcore_tx_busy)) begin + soc_litedramcore_tx_bitcount <= (soc_litedramcore_tx_bitcount + 1'd1); + if ((soc_litedramcore_tx_bitcount == 4'd8)) begin + serial_tx <= 1'd1; + end else begin + if ((soc_litedramcore_tx_bitcount == 4'd9)) begin + serial_tx <= 1'd1; + soc_litedramcore_tx_busy <= 1'd0; + soc_litedramcore_sink_ready <= 1'd1; + end else begin + serial_tx <= soc_litedramcore_tx_reg[0]; + soc_litedramcore_tx_reg <= {1'd0, soc_litedramcore_tx_reg[7:1]}; + end + end + end + end + if (soc_litedramcore_tx_busy) begin + {soc_litedramcore_uart_clk_txen, soc_litedramcore_phase_accumulator_tx} <= (soc_litedramcore_phase_accumulator_tx + soc_litedramcore_storage); + end else begin + {soc_litedramcore_uart_clk_txen, soc_litedramcore_phase_accumulator_tx} <= 1'd0; + end + soc_litedramcore_source_valid <= 1'd0; + soc_litedramcore_rx_r <= soc_litedramcore_rx; + if ((~soc_litedramcore_rx_busy)) begin + if (((~soc_litedramcore_rx) & soc_litedramcore_rx_r)) begin + soc_litedramcore_rx_busy <= 1'd1; + soc_litedramcore_rx_bitcount <= 1'd0; + end + end else begin + if (soc_litedramcore_uart_clk_rxen) begin + soc_litedramcore_rx_bitcount <= (soc_litedramcore_rx_bitcount + 1'd1); + if ((soc_litedramcore_rx_bitcount == 1'd0)) begin + if (soc_litedramcore_rx) begin + soc_litedramcore_rx_busy <= 1'd0; + end + end else begin + if ((soc_litedramcore_rx_bitcount == 4'd9)) begin + soc_litedramcore_rx_busy <= 1'd0; + if (soc_litedramcore_rx) begin + soc_litedramcore_source_payload_data <= soc_litedramcore_rx_reg; + soc_litedramcore_source_valid <= 1'd1; + end + end else begin + soc_litedramcore_rx_reg <= {soc_litedramcore_rx, soc_litedramcore_rx_reg[7:1]}; + end + end + end + end + if (soc_litedramcore_rx_busy) begin + {soc_litedramcore_uart_clk_rxen, soc_litedramcore_phase_accumulator_rx} <= (soc_litedramcore_phase_accumulator_rx + soc_litedramcore_storage); + end else begin + {soc_litedramcore_uart_clk_rxen, soc_litedramcore_phase_accumulator_rx} <= 32'd2147483648; + end + if (soc_litedramcore_uart_tx_clear) begin + soc_litedramcore_uart_tx_pending <= 1'd0; + end + soc_litedramcore_uart_tx_old_trigger <= soc_litedramcore_uart_tx_trigger; + if (((~soc_litedramcore_uart_tx_trigger) & soc_litedramcore_uart_tx_old_trigger)) begin + soc_litedramcore_uart_tx_pending <= 1'd1; + end + if (soc_litedramcore_uart_rx_clear) begin + soc_litedramcore_uart_rx_pending <= 1'd0; + end + soc_litedramcore_uart_rx_old_trigger <= soc_litedramcore_uart_rx_trigger; + if (((~soc_litedramcore_uart_rx_trigger) & soc_litedramcore_uart_rx_old_trigger)) begin + soc_litedramcore_uart_rx_pending <= 1'd1; + end + if (soc_litedramcore_uart_tx_fifo_syncfifo_re) begin + soc_litedramcore_uart_tx_fifo_readable <= 1'd1; + end else begin + if (soc_litedramcore_uart_tx_fifo_re) begin + soc_litedramcore_uart_tx_fifo_readable <= 1'd0; + end + end + if (((soc_litedramcore_uart_tx_fifo_syncfifo_we & soc_litedramcore_uart_tx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_tx_fifo_replace))) begin + soc_litedramcore_uart_tx_fifo_produce <= (soc_litedramcore_uart_tx_fifo_produce + 1'd1); + end + if (soc_litedramcore_uart_tx_fifo_do_read) begin + soc_litedramcore_uart_tx_fifo_consume <= (soc_litedramcore_uart_tx_fifo_consume + 1'd1); + end + if (((soc_litedramcore_uart_tx_fifo_syncfifo_we & soc_litedramcore_uart_tx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_tx_fifo_replace))) begin + if ((~soc_litedramcore_uart_tx_fifo_do_read)) begin + soc_litedramcore_uart_tx_fifo_level0 <= (soc_litedramcore_uart_tx_fifo_level0 + 1'd1); + end + end else begin + if (soc_litedramcore_uart_tx_fifo_do_read) begin + soc_litedramcore_uart_tx_fifo_level0 <= (soc_litedramcore_uart_tx_fifo_level0 - 1'd1); + end + end + if (soc_litedramcore_uart_rx_fifo_syncfifo_re) begin + soc_litedramcore_uart_rx_fifo_readable <= 1'd1; + end else begin + if (soc_litedramcore_uart_rx_fifo_re) begin + soc_litedramcore_uart_rx_fifo_readable <= 1'd0; + end + end + if (((soc_litedramcore_uart_rx_fifo_syncfifo_we & soc_litedramcore_uart_rx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_rx_fifo_replace))) begin + soc_litedramcore_uart_rx_fifo_produce <= (soc_litedramcore_uart_rx_fifo_produce + 1'd1); + end + if (soc_litedramcore_uart_rx_fifo_do_read) begin + soc_litedramcore_uart_rx_fifo_consume <= (soc_litedramcore_uart_rx_fifo_consume + 1'd1); + end + if (((soc_litedramcore_uart_rx_fifo_syncfifo_we & soc_litedramcore_uart_rx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_rx_fifo_replace))) begin + if ((~soc_litedramcore_uart_rx_fifo_do_read)) begin + soc_litedramcore_uart_rx_fifo_level0 <= (soc_litedramcore_uart_rx_fifo_level0 + 1'd1); + end + end else begin + if (soc_litedramcore_uart_rx_fifo_do_read) begin + soc_litedramcore_uart_rx_fifo_level0 <= (soc_litedramcore_uart_rx_fifo_level0 - 1'd1); + end + end + if (soc_litedramcore_uart_reset) begin + soc_litedramcore_uart_tx_pending <= 1'd0; + soc_litedramcore_uart_tx_old_trigger <= 1'd0; + soc_litedramcore_uart_rx_pending <= 1'd0; + soc_litedramcore_uart_rx_old_trigger <= 1'd0; + soc_litedramcore_uart_tx_fifo_readable <= 1'd0; + soc_litedramcore_uart_tx_fifo_level0 <= 5'd0; + soc_litedramcore_uart_tx_fifo_produce <= 4'd0; + soc_litedramcore_uart_tx_fifo_consume <= 4'd0; + soc_litedramcore_uart_rx_fifo_readable <= 1'd0; + soc_litedramcore_uart_rx_fifo_level0 <= 5'd0; + soc_litedramcore_uart_rx_fifo_produce <= 4'd0; + soc_litedramcore_uart_rx_fifo_consume <= 4'd0; + end + if (soc_litedramcore_timer_en_storage) begin + if ((soc_litedramcore_timer_value == 1'd0)) begin + soc_litedramcore_timer_value <= soc_litedramcore_timer_reload_storage; + end else begin + soc_litedramcore_timer_value <= (soc_litedramcore_timer_value - 1'd1); + end + end else begin + soc_litedramcore_timer_value <= soc_litedramcore_timer_load_storage; + end + if (soc_litedramcore_timer_update_value_re) begin + soc_litedramcore_timer_value_status <= soc_litedramcore_timer_value; + end + if (soc_litedramcore_timer_zero_clear) begin + soc_litedramcore_timer_zero_pending <= 1'd0; + end + soc_litedramcore_timer_zero_old_trigger <= soc_litedramcore_timer_zero_trigger; + if (((~soc_litedramcore_timer_zero_trigger) & soc_litedramcore_timer_zero_old_trigger)) begin + soc_litedramcore_timer_zero_pending <= 1'd1; + end + vns_wb2csr_state <= vns_wb2csr_next_state; + soc_a7ddrphy_dqs_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dqs_oe) | soc_a7ddrphy_dqspattern1); + soc_a7ddrphy_dq_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dq_oe) | soc_a7ddrphy_dqspattern1); + soc_a7ddrphy_rddata_en_last <= soc_a7ddrphy_rddata_en; + soc_a7ddrphy_dfi_p0_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); + soc_a7ddrphy_dfi_p1_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); + soc_a7ddrphy_dfi_p2_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); + soc_a7ddrphy_dfi_p3_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); + soc_a7ddrphy_wrdata_en_last <= soc_a7ddrphy_wrdata_en; + soc_a7ddrphy_dqspattern_o1 <= soc_a7ddrphy_dqspattern_o0; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip0_value <= (soc_a7ddrphy_bitslip0_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip0_value <= 1'd0; + end + soc_a7ddrphy_bitslip0_r <= {soc_a7ddrphy_bitslip0_i, soc_a7ddrphy_bitslip0_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip1_value <= (soc_a7ddrphy_bitslip1_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip1_value <= 1'd0; + end + soc_a7ddrphy_bitslip1_r <= {soc_a7ddrphy_bitslip1_i, soc_a7ddrphy_bitslip1_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip2_value <= (soc_a7ddrphy_bitslip2_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip2_value <= 1'd0; + end + soc_a7ddrphy_bitslip2_r <= {soc_a7ddrphy_bitslip2_i, soc_a7ddrphy_bitslip2_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip3_value <= (soc_a7ddrphy_bitslip3_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip3_value <= 1'd0; + end + soc_a7ddrphy_bitslip3_r <= {soc_a7ddrphy_bitslip3_i, soc_a7ddrphy_bitslip3_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip4_value <= (soc_a7ddrphy_bitslip4_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip4_value <= 1'd0; + end + soc_a7ddrphy_bitslip4_r <= {soc_a7ddrphy_bitslip4_i, soc_a7ddrphy_bitslip4_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip5_value <= (soc_a7ddrphy_bitslip5_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip5_value <= 1'd0; + end + soc_a7ddrphy_bitslip5_r <= {soc_a7ddrphy_bitslip5_i, soc_a7ddrphy_bitslip5_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip6_value <= (soc_a7ddrphy_bitslip6_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip6_value <= 1'd0; + end + soc_a7ddrphy_bitslip6_r <= {soc_a7ddrphy_bitslip6_i, soc_a7ddrphy_bitslip6_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip7_value <= (soc_a7ddrphy_bitslip7_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip7_value <= 1'd0; + end + soc_a7ddrphy_bitslip7_r <= {soc_a7ddrphy_bitslip7_i, soc_a7ddrphy_bitslip7_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip8_value <= (soc_a7ddrphy_bitslip8_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip8_value <= 1'd0; + end + soc_a7ddrphy_bitslip8_r <= {soc_a7ddrphy_bitslip8_i, soc_a7ddrphy_bitslip8_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip9_value <= (soc_a7ddrphy_bitslip9_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip9_value <= 1'd0; + end + soc_a7ddrphy_bitslip9_r <= {soc_a7ddrphy_bitslip9_i, soc_a7ddrphy_bitslip9_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip10_value <= (soc_a7ddrphy_bitslip10_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip10_value <= 1'd0; + end + soc_a7ddrphy_bitslip10_r <= {soc_a7ddrphy_bitslip10_i, soc_a7ddrphy_bitslip10_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip11_value <= (soc_a7ddrphy_bitslip11_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip11_value <= 1'd0; + end + soc_a7ddrphy_bitslip11_r <= {soc_a7ddrphy_bitslip11_i, soc_a7ddrphy_bitslip11_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip12_value <= (soc_a7ddrphy_bitslip12_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip12_value <= 1'd0; + end + soc_a7ddrphy_bitslip12_r <= {soc_a7ddrphy_bitslip12_i, soc_a7ddrphy_bitslip12_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip13_value <= (soc_a7ddrphy_bitslip13_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip13_value <= 1'd0; + end + soc_a7ddrphy_bitslip13_r <= {soc_a7ddrphy_bitslip13_i, soc_a7ddrphy_bitslip13_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip14_value <= (soc_a7ddrphy_bitslip14_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip14_value <= 1'd0; + end + soc_a7ddrphy_bitslip14_r <= {soc_a7ddrphy_bitslip14_i, soc_a7ddrphy_bitslip14_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip15_value <= (soc_a7ddrphy_bitslip15_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip15_value <= 1'd0; + end + soc_a7ddrphy_bitslip15_r <= {soc_a7ddrphy_bitslip15_i, soc_a7ddrphy_bitslip15_r[15:8]}; + if (soc_sdram_inti_p0_rddata_valid) begin + soc_sdram_phaseinjector0_status <= soc_sdram_inti_p0_rddata; + end + if (soc_sdram_inti_p1_rddata_valid) begin + soc_sdram_phaseinjector1_status <= soc_sdram_inti_p1_rddata; + end + if (soc_sdram_inti_p2_rddata_valid) begin + soc_sdram_phaseinjector2_status <= soc_sdram_inti_p2_rddata; + end + if (soc_sdram_inti_p3_rddata_valid) begin + soc_sdram_phaseinjector3_status <= soc_sdram_inti_p3_rddata; + end + if ((soc_sdram_timer_wait & (~soc_sdram_timer_done0))) begin + soc_sdram_timer_count1 <= (soc_sdram_timer_count1 - 1'd1); + end else begin + soc_sdram_timer_count1 <= 10'd781; + end + soc_sdram_postponer_req_o <= 1'd0; + if (soc_sdram_postponer_req_i) begin + soc_sdram_postponer_count <= (soc_sdram_postponer_count - 1'd1); + if ((soc_sdram_postponer_count == 1'd0)) begin + soc_sdram_postponer_count <= 1'd0; + soc_sdram_postponer_req_o <= 1'd1; + end + end + if (soc_sdram_sequencer_start0) begin + soc_sdram_sequencer_count <= 1'd0; + end else begin + if (soc_sdram_sequencer_done1) begin + if ((soc_sdram_sequencer_count != 1'd0)) begin + soc_sdram_sequencer_count <= (soc_sdram_sequencer_count - 1'd1); + end + end + end + soc_sdram_cmd_payload_a <= 1'd0; + soc_sdram_cmd_payload_ba <= 1'd0; + soc_sdram_cmd_payload_cas <= 1'd0; + soc_sdram_cmd_payload_ras <= 1'd0; + soc_sdram_cmd_payload_we <= 1'd0; + soc_sdram_sequencer_done1 <= 1'd0; + if ((soc_sdram_sequencer_start1 & (soc_sdram_sequencer_counter == 1'd0))) begin + soc_sdram_cmd_payload_a <= 11'd1024; + soc_sdram_cmd_payload_ba <= 1'd0; + soc_sdram_cmd_payload_cas <= 1'd0; + soc_sdram_cmd_payload_ras <= 1'd1; + soc_sdram_cmd_payload_we <= 1'd1; + end + if ((soc_sdram_sequencer_counter == 2'd3)) begin + soc_sdram_cmd_payload_a <= 1'd0; + soc_sdram_cmd_payload_ba <= 1'd0; + soc_sdram_cmd_payload_cas <= 1'd1; + soc_sdram_cmd_payload_ras <= 1'd1; + soc_sdram_cmd_payload_we <= 1'd0; + end + if ((soc_sdram_sequencer_counter == 6'd35)) begin + soc_sdram_cmd_payload_a <= 1'd0; + soc_sdram_cmd_payload_ba <= 1'd0; + soc_sdram_cmd_payload_cas <= 1'd0; + soc_sdram_cmd_payload_ras <= 1'd0; + soc_sdram_cmd_payload_we <= 1'd0; + soc_sdram_sequencer_done1 <= 1'd1; + end + if ((soc_sdram_sequencer_counter == 6'd35)) begin + soc_sdram_sequencer_counter <= 1'd0; + end else begin + if ((soc_sdram_sequencer_counter != 1'd0)) begin + soc_sdram_sequencer_counter <= (soc_sdram_sequencer_counter + 1'd1); + end else begin + if (soc_sdram_sequencer_start1) begin + soc_sdram_sequencer_counter <= 1'd1; + end + end + end + if ((soc_sdram_zqcs_timer_wait & (~soc_sdram_zqcs_timer_done0))) begin + soc_sdram_zqcs_timer_count1 <= (soc_sdram_zqcs_timer_count1 - 1'd1); + end else begin + soc_sdram_zqcs_timer_count1 <= 27'd99999999; + end + soc_sdram_zqcs_executer_done <= 1'd0; + if ((soc_sdram_zqcs_executer_start & (soc_sdram_zqcs_executer_counter == 1'd0))) begin + soc_sdram_cmd_payload_a <= 11'd1024; + soc_sdram_cmd_payload_ba <= 1'd0; + soc_sdram_cmd_payload_cas <= 1'd0; + soc_sdram_cmd_payload_ras <= 1'd1; + soc_sdram_cmd_payload_we <= 1'd1; + end + if ((soc_sdram_zqcs_executer_counter == 2'd3)) begin + soc_sdram_cmd_payload_a <= 1'd0; + soc_sdram_cmd_payload_ba <= 1'd0; + soc_sdram_cmd_payload_cas <= 1'd0; + soc_sdram_cmd_payload_ras <= 1'd0; + soc_sdram_cmd_payload_we <= 1'd1; + end + if ((soc_sdram_zqcs_executer_counter == 5'd19)) begin + soc_sdram_cmd_payload_a <= 1'd0; + soc_sdram_cmd_payload_ba <= 1'd0; + soc_sdram_cmd_payload_cas <= 1'd0; + soc_sdram_cmd_payload_ras <= 1'd0; + soc_sdram_cmd_payload_we <= 1'd0; + soc_sdram_zqcs_executer_done <= 1'd1; + end + if ((soc_sdram_zqcs_executer_counter == 5'd19)) begin + soc_sdram_zqcs_executer_counter <= 1'd0; + end else begin + if ((soc_sdram_zqcs_executer_counter != 1'd0)) begin + soc_sdram_zqcs_executer_counter <= (soc_sdram_zqcs_executer_counter + 1'd1); + end else begin + if (soc_sdram_zqcs_executer_start) begin + soc_sdram_zqcs_executer_counter <= 1'd1; + end + end + end + vns_refresher_state <= vns_refresher_next_state; + if (soc_sdram_bankmachine0_row_close) begin + soc_sdram_bankmachine0_row_opened <= 1'd0; + end else begin + if (soc_sdram_bankmachine0_row_open) begin + soc_sdram_bankmachine0_row_opened <= 1'd1; + soc_sdram_bankmachine0_row <= soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin + soc_sdram_bankmachine0_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine0_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin + if ((~soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin + soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_sdram_bankmachine0_cmd_buffer_source_valid) | soc_sdram_bankmachine0_cmd_buffer_source_ready)) begin + soc_sdram_bankmachine0_cmd_buffer_source_valid <= soc_sdram_bankmachine0_cmd_buffer_sink_valid; + soc_sdram_bankmachine0_cmd_buffer_source_first <= soc_sdram_bankmachine0_cmd_buffer_sink_first; + soc_sdram_bankmachine0_cmd_buffer_source_last <= soc_sdram_bankmachine0_cmd_buffer_sink_last; + soc_sdram_bankmachine0_cmd_buffer_source_payload_we <= soc_sdram_bankmachine0_cmd_buffer_sink_payload_we; + soc_sdram_bankmachine0_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr; + end + if (soc_sdram_bankmachine0_twtpcon_valid) begin + soc_sdram_bankmachine0_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine0_twtpcon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine0_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine0_twtpcon_ready)) begin + soc_sdram_bankmachine0_twtpcon_count <= (soc_sdram_bankmachine0_twtpcon_count - 1'd1); + if ((soc_sdram_bankmachine0_twtpcon_count == 1'd1)) begin + soc_sdram_bankmachine0_twtpcon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine0_trccon_valid) begin + soc_sdram_bankmachine0_trccon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine0_trccon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine0_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine0_trccon_ready)) begin + soc_sdram_bankmachine0_trccon_count <= (soc_sdram_bankmachine0_trccon_count - 1'd1); + if ((soc_sdram_bankmachine0_trccon_count == 1'd1)) begin + soc_sdram_bankmachine0_trccon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine0_trascon_valid) begin + soc_sdram_bankmachine0_trascon_count <= 3'd4; + if (1'd0) begin + soc_sdram_bankmachine0_trascon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine0_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine0_trascon_ready)) begin + soc_sdram_bankmachine0_trascon_count <= (soc_sdram_bankmachine0_trascon_count - 1'd1); + if ((soc_sdram_bankmachine0_trascon_count == 1'd1)) begin + soc_sdram_bankmachine0_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine0_state <= vns_bankmachine0_next_state; + if (soc_sdram_bankmachine1_row_close) begin + soc_sdram_bankmachine1_row_opened <= 1'd0; + end else begin + if (soc_sdram_bankmachine1_row_open) begin + soc_sdram_bankmachine1_row_opened <= 1'd1; + soc_sdram_bankmachine1_row <= soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin + soc_sdram_bankmachine1_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine1_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin + if ((~soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin + soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_sdram_bankmachine1_cmd_buffer_source_valid) | soc_sdram_bankmachine1_cmd_buffer_source_ready)) begin + soc_sdram_bankmachine1_cmd_buffer_source_valid <= soc_sdram_bankmachine1_cmd_buffer_sink_valid; + soc_sdram_bankmachine1_cmd_buffer_source_first <= soc_sdram_bankmachine1_cmd_buffer_sink_first; + soc_sdram_bankmachine1_cmd_buffer_source_last <= soc_sdram_bankmachine1_cmd_buffer_sink_last; + soc_sdram_bankmachine1_cmd_buffer_source_payload_we <= soc_sdram_bankmachine1_cmd_buffer_sink_payload_we; + soc_sdram_bankmachine1_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr; + end + if (soc_sdram_bankmachine1_twtpcon_valid) begin + soc_sdram_bankmachine1_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine1_twtpcon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine1_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine1_twtpcon_ready)) begin + soc_sdram_bankmachine1_twtpcon_count <= (soc_sdram_bankmachine1_twtpcon_count - 1'd1); + if ((soc_sdram_bankmachine1_twtpcon_count == 1'd1)) begin + soc_sdram_bankmachine1_twtpcon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine1_trccon_valid) begin + soc_sdram_bankmachine1_trccon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine1_trccon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine1_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine1_trccon_ready)) begin + soc_sdram_bankmachine1_trccon_count <= (soc_sdram_bankmachine1_trccon_count - 1'd1); + if ((soc_sdram_bankmachine1_trccon_count == 1'd1)) begin + soc_sdram_bankmachine1_trccon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine1_trascon_valid) begin + soc_sdram_bankmachine1_trascon_count <= 3'd4; + if (1'd0) begin + soc_sdram_bankmachine1_trascon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine1_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine1_trascon_ready)) begin + soc_sdram_bankmachine1_trascon_count <= (soc_sdram_bankmachine1_trascon_count - 1'd1); + if ((soc_sdram_bankmachine1_trascon_count == 1'd1)) begin + soc_sdram_bankmachine1_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine1_state <= vns_bankmachine1_next_state; + if (soc_sdram_bankmachine2_row_close) begin + soc_sdram_bankmachine2_row_opened <= 1'd0; + end else begin + if (soc_sdram_bankmachine2_row_open) begin + soc_sdram_bankmachine2_row_opened <= 1'd1; + soc_sdram_bankmachine2_row <= soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin + soc_sdram_bankmachine2_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine2_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin + if ((~soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin + soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_sdram_bankmachine2_cmd_buffer_source_valid) | soc_sdram_bankmachine2_cmd_buffer_source_ready)) begin + soc_sdram_bankmachine2_cmd_buffer_source_valid <= soc_sdram_bankmachine2_cmd_buffer_sink_valid; + soc_sdram_bankmachine2_cmd_buffer_source_first <= soc_sdram_bankmachine2_cmd_buffer_sink_first; + soc_sdram_bankmachine2_cmd_buffer_source_last <= soc_sdram_bankmachine2_cmd_buffer_sink_last; + soc_sdram_bankmachine2_cmd_buffer_source_payload_we <= soc_sdram_bankmachine2_cmd_buffer_sink_payload_we; + soc_sdram_bankmachine2_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr; + end + if (soc_sdram_bankmachine2_twtpcon_valid) begin + soc_sdram_bankmachine2_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine2_twtpcon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine2_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine2_twtpcon_ready)) begin + soc_sdram_bankmachine2_twtpcon_count <= (soc_sdram_bankmachine2_twtpcon_count - 1'd1); + if ((soc_sdram_bankmachine2_twtpcon_count == 1'd1)) begin + soc_sdram_bankmachine2_twtpcon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine2_trccon_valid) begin + soc_sdram_bankmachine2_trccon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine2_trccon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine2_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine2_trccon_ready)) begin + soc_sdram_bankmachine2_trccon_count <= (soc_sdram_bankmachine2_trccon_count - 1'd1); + if ((soc_sdram_bankmachine2_trccon_count == 1'd1)) begin + soc_sdram_bankmachine2_trccon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine2_trascon_valid) begin + soc_sdram_bankmachine2_trascon_count <= 3'd4; + if (1'd0) begin + soc_sdram_bankmachine2_trascon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine2_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine2_trascon_ready)) begin + soc_sdram_bankmachine2_trascon_count <= (soc_sdram_bankmachine2_trascon_count - 1'd1); + if ((soc_sdram_bankmachine2_trascon_count == 1'd1)) begin + soc_sdram_bankmachine2_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine2_state <= vns_bankmachine2_next_state; + if (soc_sdram_bankmachine3_row_close) begin + soc_sdram_bankmachine3_row_opened <= 1'd0; + end else begin + if (soc_sdram_bankmachine3_row_open) begin + soc_sdram_bankmachine3_row_opened <= 1'd1; + soc_sdram_bankmachine3_row <= soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin + soc_sdram_bankmachine3_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine3_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin + if ((~soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin + soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_sdram_bankmachine3_cmd_buffer_source_valid) | soc_sdram_bankmachine3_cmd_buffer_source_ready)) begin + soc_sdram_bankmachine3_cmd_buffer_source_valid <= soc_sdram_bankmachine3_cmd_buffer_sink_valid; + soc_sdram_bankmachine3_cmd_buffer_source_first <= soc_sdram_bankmachine3_cmd_buffer_sink_first; + soc_sdram_bankmachine3_cmd_buffer_source_last <= soc_sdram_bankmachine3_cmd_buffer_sink_last; + soc_sdram_bankmachine3_cmd_buffer_source_payload_we <= soc_sdram_bankmachine3_cmd_buffer_sink_payload_we; + soc_sdram_bankmachine3_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr; + end + if (soc_sdram_bankmachine3_twtpcon_valid) begin + soc_sdram_bankmachine3_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine3_twtpcon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine3_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine3_twtpcon_ready)) begin + soc_sdram_bankmachine3_twtpcon_count <= (soc_sdram_bankmachine3_twtpcon_count - 1'd1); + if ((soc_sdram_bankmachine3_twtpcon_count == 1'd1)) begin + soc_sdram_bankmachine3_twtpcon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine3_trccon_valid) begin + soc_sdram_bankmachine3_trccon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine3_trccon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine3_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine3_trccon_ready)) begin + soc_sdram_bankmachine3_trccon_count <= (soc_sdram_bankmachine3_trccon_count - 1'd1); + if ((soc_sdram_bankmachine3_trccon_count == 1'd1)) begin + soc_sdram_bankmachine3_trccon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine3_trascon_valid) begin + soc_sdram_bankmachine3_trascon_count <= 3'd4; + if (1'd0) begin + soc_sdram_bankmachine3_trascon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine3_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine3_trascon_ready)) begin + soc_sdram_bankmachine3_trascon_count <= (soc_sdram_bankmachine3_trascon_count - 1'd1); + if ((soc_sdram_bankmachine3_trascon_count == 1'd1)) begin + soc_sdram_bankmachine3_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine3_state <= vns_bankmachine3_next_state; + if (soc_sdram_bankmachine4_row_close) begin + soc_sdram_bankmachine4_row_opened <= 1'd0; + end else begin + if (soc_sdram_bankmachine4_row_open) begin + soc_sdram_bankmachine4_row_opened <= 1'd1; + soc_sdram_bankmachine4_row <= soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin + soc_sdram_bankmachine4_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine4_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin + if ((~soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read)) begin + soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_sdram_bankmachine4_cmd_buffer_source_valid) | soc_sdram_bankmachine4_cmd_buffer_source_ready)) begin + soc_sdram_bankmachine4_cmd_buffer_source_valid <= soc_sdram_bankmachine4_cmd_buffer_sink_valid; + soc_sdram_bankmachine4_cmd_buffer_source_first <= soc_sdram_bankmachine4_cmd_buffer_sink_first; + soc_sdram_bankmachine4_cmd_buffer_source_last <= soc_sdram_bankmachine4_cmd_buffer_sink_last; + soc_sdram_bankmachine4_cmd_buffer_source_payload_we <= soc_sdram_bankmachine4_cmd_buffer_sink_payload_we; + soc_sdram_bankmachine4_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr; + end + if (soc_sdram_bankmachine4_twtpcon_valid) begin + soc_sdram_bankmachine4_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine4_twtpcon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine4_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine4_twtpcon_ready)) begin + soc_sdram_bankmachine4_twtpcon_count <= (soc_sdram_bankmachine4_twtpcon_count - 1'd1); + if ((soc_sdram_bankmachine4_twtpcon_count == 1'd1)) begin + soc_sdram_bankmachine4_twtpcon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine4_trccon_valid) begin + soc_sdram_bankmachine4_trccon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine4_trccon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine4_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine4_trccon_ready)) begin + soc_sdram_bankmachine4_trccon_count <= (soc_sdram_bankmachine4_trccon_count - 1'd1); + if ((soc_sdram_bankmachine4_trccon_count == 1'd1)) begin + soc_sdram_bankmachine4_trccon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine4_trascon_valid) begin + soc_sdram_bankmachine4_trascon_count <= 3'd4; + if (1'd0) begin + soc_sdram_bankmachine4_trascon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine4_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine4_trascon_ready)) begin + soc_sdram_bankmachine4_trascon_count <= (soc_sdram_bankmachine4_trascon_count - 1'd1); + if ((soc_sdram_bankmachine4_trascon_count == 1'd1)) begin + soc_sdram_bankmachine4_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine4_state <= vns_bankmachine4_next_state; + if (soc_sdram_bankmachine5_row_close) begin + soc_sdram_bankmachine5_row_opened <= 1'd0; + end else begin + if (soc_sdram_bankmachine5_row_open) begin + soc_sdram_bankmachine5_row_opened <= 1'd1; + soc_sdram_bankmachine5_row <= soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin + soc_sdram_bankmachine5_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine5_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin + if ((~soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read)) begin + soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_sdram_bankmachine5_cmd_buffer_source_valid) | soc_sdram_bankmachine5_cmd_buffer_source_ready)) begin + soc_sdram_bankmachine5_cmd_buffer_source_valid <= soc_sdram_bankmachine5_cmd_buffer_sink_valid; + soc_sdram_bankmachine5_cmd_buffer_source_first <= soc_sdram_bankmachine5_cmd_buffer_sink_first; + soc_sdram_bankmachine5_cmd_buffer_source_last <= soc_sdram_bankmachine5_cmd_buffer_sink_last; + soc_sdram_bankmachine5_cmd_buffer_source_payload_we <= soc_sdram_bankmachine5_cmd_buffer_sink_payload_we; + soc_sdram_bankmachine5_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr; + end + if (soc_sdram_bankmachine5_twtpcon_valid) begin + soc_sdram_bankmachine5_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine5_twtpcon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine5_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine5_twtpcon_ready)) begin + soc_sdram_bankmachine5_twtpcon_count <= (soc_sdram_bankmachine5_twtpcon_count - 1'd1); + if ((soc_sdram_bankmachine5_twtpcon_count == 1'd1)) begin + soc_sdram_bankmachine5_twtpcon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine5_trccon_valid) begin + soc_sdram_bankmachine5_trccon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine5_trccon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine5_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine5_trccon_ready)) begin + soc_sdram_bankmachine5_trccon_count <= (soc_sdram_bankmachine5_trccon_count - 1'd1); + if ((soc_sdram_bankmachine5_trccon_count == 1'd1)) begin + soc_sdram_bankmachine5_trccon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine5_trascon_valid) begin + soc_sdram_bankmachine5_trascon_count <= 3'd4; + if (1'd0) begin + soc_sdram_bankmachine5_trascon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine5_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine5_trascon_ready)) begin + soc_sdram_bankmachine5_trascon_count <= (soc_sdram_bankmachine5_trascon_count - 1'd1); + if ((soc_sdram_bankmachine5_trascon_count == 1'd1)) begin + soc_sdram_bankmachine5_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine5_state <= vns_bankmachine5_next_state; + if (soc_sdram_bankmachine6_row_close) begin + soc_sdram_bankmachine6_row_opened <= 1'd0; + end else begin + if (soc_sdram_bankmachine6_row_open) begin + soc_sdram_bankmachine6_row_opened <= 1'd1; + soc_sdram_bankmachine6_row <= soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin + soc_sdram_bankmachine6_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine6_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin + if ((~soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read)) begin + soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_sdram_bankmachine6_cmd_buffer_source_valid) | soc_sdram_bankmachine6_cmd_buffer_source_ready)) begin + soc_sdram_bankmachine6_cmd_buffer_source_valid <= soc_sdram_bankmachine6_cmd_buffer_sink_valid; + soc_sdram_bankmachine6_cmd_buffer_source_first <= soc_sdram_bankmachine6_cmd_buffer_sink_first; + soc_sdram_bankmachine6_cmd_buffer_source_last <= soc_sdram_bankmachine6_cmd_buffer_sink_last; + soc_sdram_bankmachine6_cmd_buffer_source_payload_we <= soc_sdram_bankmachine6_cmd_buffer_sink_payload_we; + soc_sdram_bankmachine6_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr; + end + if (soc_sdram_bankmachine6_twtpcon_valid) begin + soc_sdram_bankmachine6_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine6_twtpcon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine6_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine6_twtpcon_ready)) begin + soc_sdram_bankmachine6_twtpcon_count <= (soc_sdram_bankmachine6_twtpcon_count - 1'd1); + if ((soc_sdram_bankmachine6_twtpcon_count == 1'd1)) begin + soc_sdram_bankmachine6_twtpcon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine6_trccon_valid) begin + soc_sdram_bankmachine6_trccon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine6_trccon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine6_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine6_trccon_ready)) begin + soc_sdram_bankmachine6_trccon_count <= (soc_sdram_bankmachine6_trccon_count - 1'd1); + if ((soc_sdram_bankmachine6_trccon_count == 1'd1)) begin + soc_sdram_bankmachine6_trccon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine6_trascon_valid) begin + soc_sdram_bankmachine6_trascon_count <= 3'd4; + if (1'd0) begin + soc_sdram_bankmachine6_trascon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine6_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine6_trascon_ready)) begin + soc_sdram_bankmachine6_trascon_count <= (soc_sdram_bankmachine6_trascon_count - 1'd1); + if ((soc_sdram_bankmachine6_trascon_count == 1'd1)) begin + soc_sdram_bankmachine6_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine6_state <= vns_bankmachine6_next_state; + if (soc_sdram_bankmachine7_row_close) begin + soc_sdram_bankmachine7_row_opened <= 1'd0; + end else begin + if (soc_sdram_bankmachine7_row_open) begin + soc_sdram_bankmachine7_row_opened <= 1'd1; + soc_sdram_bankmachine7_row <= soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin + soc_sdram_bankmachine7_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine7_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin + if ((~soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read)) begin + soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_sdram_bankmachine7_cmd_buffer_source_valid) | soc_sdram_bankmachine7_cmd_buffer_source_ready)) begin + soc_sdram_bankmachine7_cmd_buffer_source_valid <= soc_sdram_bankmachine7_cmd_buffer_sink_valid; + soc_sdram_bankmachine7_cmd_buffer_source_first <= soc_sdram_bankmachine7_cmd_buffer_sink_first; + soc_sdram_bankmachine7_cmd_buffer_source_last <= soc_sdram_bankmachine7_cmd_buffer_sink_last; + soc_sdram_bankmachine7_cmd_buffer_source_payload_we <= soc_sdram_bankmachine7_cmd_buffer_sink_payload_we; + soc_sdram_bankmachine7_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr; + end + if (soc_sdram_bankmachine7_twtpcon_valid) begin + soc_sdram_bankmachine7_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine7_twtpcon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine7_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine7_twtpcon_ready)) begin + soc_sdram_bankmachine7_twtpcon_count <= (soc_sdram_bankmachine7_twtpcon_count - 1'd1); + if ((soc_sdram_bankmachine7_twtpcon_count == 1'd1)) begin + soc_sdram_bankmachine7_twtpcon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine7_trccon_valid) begin + soc_sdram_bankmachine7_trccon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine7_trccon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine7_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine7_trccon_ready)) begin + soc_sdram_bankmachine7_trccon_count <= (soc_sdram_bankmachine7_trccon_count - 1'd1); + if ((soc_sdram_bankmachine7_trccon_count == 1'd1)) begin + soc_sdram_bankmachine7_trccon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine7_trascon_valid) begin + soc_sdram_bankmachine7_trascon_count <= 3'd4; + if (1'd0) begin + soc_sdram_bankmachine7_trascon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine7_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine7_trascon_ready)) begin + soc_sdram_bankmachine7_trascon_count <= (soc_sdram_bankmachine7_trascon_count - 1'd1); + if ((soc_sdram_bankmachine7_trascon_count == 1'd1)) begin + soc_sdram_bankmachine7_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine7_state <= vns_bankmachine7_next_state; + if ((~soc_sdram_en0)) begin + soc_sdram_time0 <= 5'd31; + end else begin + if ((~soc_sdram_max_time0)) begin + soc_sdram_time0 <= (soc_sdram_time0 - 1'd1); + end + end + if ((~soc_sdram_en1)) begin + soc_sdram_time1 <= 4'd15; + end else begin + if ((~soc_sdram_max_time1)) begin + soc_sdram_time1 <= (soc_sdram_time1 - 1'd1); + end + end + if (soc_sdram_choose_cmd_ce) begin + case (soc_sdram_choose_cmd_grant) + 1'd0: begin + if (soc_sdram_choose_cmd_request[1]) begin + soc_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (soc_sdram_choose_cmd_request[2]) begin + soc_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (soc_sdram_choose_cmd_request[3]) begin + soc_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (soc_sdram_choose_cmd_request[4]) begin + soc_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (soc_sdram_choose_cmd_request[5]) begin + soc_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (soc_sdram_choose_cmd_request[6]) begin + soc_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (soc_sdram_choose_cmd_request[7]) begin + soc_sdram_choose_cmd_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (soc_sdram_choose_cmd_request[2]) begin + soc_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (soc_sdram_choose_cmd_request[3]) begin + soc_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (soc_sdram_choose_cmd_request[4]) begin + soc_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (soc_sdram_choose_cmd_request[5]) begin + soc_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (soc_sdram_choose_cmd_request[6]) begin + soc_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (soc_sdram_choose_cmd_request[7]) begin + soc_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (soc_sdram_choose_cmd_request[0]) begin + soc_sdram_choose_cmd_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (soc_sdram_choose_cmd_request[3]) begin + soc_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (soc_sdram_choose_cmd_request[4]) begin + soc_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (soc_sdram_choose_cmd_request[5]) begin + soc_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (soc_sdram_choose_cmd_request[6]) begin + soc_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (soc_sdram_choose_cmd_request[7]) begin + soc_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (soc_sdram_choose_cmd_request[0]) begin + soc_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (soc_sdram_choose_cmd_request[1]) begin + soc_sdram_choose_cmd_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (soc_sdram_choose_cmd_request[4]) begin + soc_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (soc_sdram_choose_cmd_request[5]) begin + soc_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (soc_sdram_choose_cmd_request[6]) begin + soc_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (soc_sdram_choose_cmd_request[7]) begin + soc_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (soc_sdram_choose_cmd_request[0]) begin + soc_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (soc_sdram_choose_cmd_request[1]) begin + soc_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (soc_sdram_choose_cmd_request[2]) begin + soc_sdram_choose_cmd_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (soc_sdram_choose_cmd_request[5]) begin + soc_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (soc_sdram_choose_cmd_request[6]) begin + soc_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (soc_sdram_choose_cmd_request[7]) begin + soc_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (soc_sdram_choose_cmd_request[0]) begin + soc_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (soc_sdram_choose_cmd_request[1]) begin + soc_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (soc_sdram_choose_cmd_request[2]) begin + soc_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (soc_sdram_choose_cmd_request[3]) begin + soc_sdram_choose_cmd_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (soc_sdram_choose_cmd_request[6]) begin + soc_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (soc_sdram_choose_cmd_request[7]) begin + soc_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (soc_sdram_choose_cmd_request[0]) begin + soc_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (soc_sdram_choose_cmd_request[1]) begin + soc_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (soc_sdram_choose_cmd_request[2]) begin + soc_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (soc_sdram_choose_cmd_request[3]) begin + soc_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (soc_sdram_choose_cmd_request[4]) begin + soc_sdram_choose_cmd_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (soc_sdram_choose_cmd_request[7]) begin + soc_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (soc_sdram_choose_cmd_request[0]) begin + soc_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (soc_sdram_choose_cmd_request[1]) begin + soc_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (soc_sdram_choose_cmd_request[2]) begin + soc_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (soc_sdram_choose_cmd_request[3]) begin + soc_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (soc_sdram_choose_cmd_request[4]) begin + soc_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (soc_sdram_choose_cmd_request[5]) begin + soc_sdram_choose_cmd_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (soc_sdram_choose_cmd_request[0]) begin + soc_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (soc_sdram_choose_cmd_request[1]) begin + soc_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (soc_sdram_choose_cmd_request[2]) begin + soc_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (soc_sdram_choose_cmd_request[3]) begin + soc_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (soc_sdram_choose_cmd_request[4]) begin + soc_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (soc_sdram_choose_cmd_request[5]) begin + soc_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (soc_sdram_choose_cmd_request[6]) begin + soc_sdram_choose_cmd_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + if (soc_sdram_choose_req_ce) begin + case (soc_sdram_choose_req_grant) + 1'd0: begin + if (soc_sdram_choose_req_request[1]) begin + soc_sdram_choose_req_grant <= 1'd1; + end else begin + if (soc_sdram_choose_req_request[2]) begin + soc_sdram_choose_req_grant <= 2'd2; + end else begin + if (soc_sdram_choose_req_request[3]) begin + soc_sdram_choose_req_grant <= 2'd3; + end else begin + if (soc_sdram_choose_req_request[4]) begin + soc_sdram_choose_req_grant <= 3'd4; + end else begin + if (soc_sdram_choose_req_request[5]) begin + soc_sdram_choose_req_grant <= 3'd5; + end else begin + if (soc_sdram_choose_req_request[6]) begin + soc_sdram_choose_req_grant <= 3'd6; + end else begin + if (soc_sdram_choose_req_request[7]) begin + soc_sdram_choose_req_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (soc_sdram_choose_req_request[2]) begin + soc_sdram_choose_req_grant <= 2'd2; + end else begin + if (soc_sdram_choose_req_request[3]) begin + soc_sdram_choose_req_grant <= 2'd3; + end else begin + if (soc_sdram_choose_req_request[4]) begin + soc_sdram_choose_req_grant <= 3'd4; + end else begin + if (soc_sdram_choose_req_request[5]) begin + soc_sdram_choose_req_grant <= 3'd5; + end else begin + if (soc_sdram_choose_req_request[6]) begin + soc_sdram_choose_req_grant <= 3'd6; + end else begin + if (soc_sdram_choose_req_request[7]) begin + soc_sdram_choose_req_grant <= 3'd7; + end else begin + if (soc_sdram_choose_req_request[0]) begin + soc_sdram_choose_req_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (soc_sdram_choose_req_request[3]) begin + soc_sdram_choose_req_grant <= 2'd3; + end else begin + if (soc_sdram_choose_req_request[4]) begin + soc_sdram_choose_req_grant <= 3'd4; + end else begin + if (soc_sdram_choose_req_request[5]) begin + soc_sdram_choose_req_grant <= 3'd5; + end else begin + if (soc_sdram_choose_req_request[6]) begin + soc_sdram_choose_req_grant <= 3'd6; + end else begin + if (soc_sdram_choose_req_request[7]) begin + soc_sdram_choose_req_grant <= 3'd7; + end else begin + if (soc_sdram_choose_req_request[0]) begin + soc_sdram_choose_req_grant <= 1'd0; + end else begin + if (soc_sdram_choose_req_request[1]) begin + soc_sdram_choose_req_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (soc_sdram_choose_req_request[4]) begin + soc_sdram_choose_req_grant <= 3'd4; + end else begin + if (soc_sdram_choose_req_request[5]) begin + soc_sdram_choose_req_grant <= 3'd5; + end else begin + if (soc_sdram_choose_req_request[6]) begin + soc_sdram_choose_req_grant <= 3'd6; + end else begin + if (soc_sdram_choose_req_request[7]) begin + soc_sdram_choose_req_grant <= 3'd7; + end else begin + if (soc_sdram_choose_req_request[0]) begin + soc_sdram_choose_req_grant <= 1'd0; + end else begin + if (soc_sdram_choose_req_request[1]) begin + soc_sdram_choose_req_grant <= 1'd1; + end else begin + if (soc_sdram_choose_req_request[2]) begin + soc_sdram_choose_req_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (soc_sdram_choose_req_request[5]) begin + soc_sdram_choose_req_grant <= 3'd5; + end else begin + if (soc_sdram_choose_req_request[6]) begin + soc_sdram_choose_req_grant <= 3'd6; + end else begin + if (soc_sdram_choose_req_request[7]) begin + soc_sdram_choose_req_grant <= 3'd7; + end else begin + if (soc_sdram_choose_req_request[0]) begin + soc_sdram_choose_req_grant <= 1'd0; + end else begin + if (soc_sdram_choose_req_request[1]) begin + soc_sdram_choose_req_grant <= 1'd1; + end else begin + if (soc_sdram_choose_req_request[2]) begin + soc_sdram_choose_req_grant <= 2'd2; + end else begin + if (soc_sdram_choose_req_request[3]) begin + soc_sdram_choose_req_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (soc_sdram_choose_req_request[6]) begin + soc_sdram_choose_req_grant <= 3'd6; + end else begin + if (soc_sdram_choose_req_request[7]) begin + soc_sdram_choose_req_grant <= 3'd7; + end else begin + if (soc_sdram_choose_req_request[0]) begin + soc_sdram_choose_req_grant <= 1'd0; + end else begin + if (soc_sdram_choose_req_request[1]) begin + soc_sdram_choose_req_grant <= 1'd1; + end else begin + if (soc_sdram_choose_req_request[2]) begin + soc_sdram_choose_req_grant <= 2'd2; + end else begin + if (soc_sdram_choose_req_request[3]) begin + soc_sdram_choose_req_grant <= 2'd3; + end else begin + if (soc_sdram_choose_req_request[4]) begin + soc_sdram_choose_req_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (soc_sdram_choose_req_request[7]) begin + soc_sdram_choose_req_grant <= 3'd7; + end else begin + if (soc_sdram_choose_req_request[0]) begin + soc_sdram_choose_req_grant <= 1'd0; + end else begin + if (soc_sdram_choose_req_request[1]) begin + soc_sdram_choose_req_grant <= 1'd1; + end else begin + if (soc_sdram_choose_req_request[2]) begin + soc_sdram_choose_req_grant <= 2'd2; + end else begin + if (soc_sdram_choose_req_request[3]) begin + soc_sdram_choose_req_grant <= 2'd3; + end else begin + if (soc_sdram_choose_req_request[4]) begin + soc_sdram_choose_req_grant <= 3'd4; + end else begin + if (soc_sdram_choose_req_request[5]) begin + soc_sdram_choose_req_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (soc_sdram_choose_req_request[0]) begin + soc_sdram_choose_req_grant <= 1'd0; + end else begin + if (soc_sdram_choose_req_request[1]) begin + soc_sdram_choose_req_grant <= 1'd1; + end else begin + if (soc_sdram_choose_req_request[2]) begin + soc_sdram_choose_req_grant <= 2'd2; + end else begin + if (soc_sdram_choose_req_request[3]) begin + soc_sdram_choose_req_grant <= 2'd3; + end else begin + if (soc_sdram_choose_req_request[4]) begin + soc_sdram_choose_req_grant <= 3'd4; + end else begin + if (soc_sdram_choose_req_request[5]) begin + soc_sdram_choose_req_grant <= 3'd5; + end else begin + if (soc_sdram_choose_req_request[6]) begin + soc_sdram_choose_req_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + soc_sdram_dfi_p0_cs_n <= 1'd0; + soc_sdram_dfi_p0_bank <= vns_array_muxed0; + soc_sdram_dfi_p0_address <= vns_array_muxed1; + soc_sdram_dfi_p0_cas_n <= (~vns_array_muxed2); + soc_sdram_dfi_p0_ras_n <= (~vns_array_muxed3); + soc_sdram_dfi_p0_we_n <= (~vns_array_muxed4); + soc_sdram_dfi_p0_rddata_en <= vns_array_muxed5; + soc_sdram_dfi_p0_wrdata_en <= vns_array_muxed6; + soc_sdram_dfi_p1_cs_n <= 1'd0; + soc_sdram_dfi_p1_bank <= vns_array_muxed7; + soc_sdram_dfi_p1_address <= vns_array_muxed8; + soc_sdram_dfi_p1_cas_n <= (~vns_array_muxed9); + soc_sdram_dfi_p1_ras_n <= (~vns_array_muxed10); + soc_sdram_dfi_p1_we_n <= (~vns_array_muxed11); + soc_sdram_dfi_p1_rddata_en <= vns_array_muxed12; + soc_sdram_dfi_p1_wrdata_en <= vns_array_muxed13; + soc_sdram_dfi_p2_cs_n <= 1'd0; + soc_sdram_dfi_p2_bank <= vns_array_muxed14; + soc_sdram_dfi_p2_address <= vns_array_muxed15; + soc_sdram_dfi_p2_cas_n <= (~vns_array_muxed16); + soc_sdram_dfi_p2_ras_n <= (~vns_array_muxed17); + soc_sdram_dfi_p2_we_n <= (~vns_array_muxed18); + soc_sdram_dfi_p2_rddata_en <= vns_array_muxed19; + soc_sdram_dfi_p2_wrdata_en <= vns_array_muxed20; + soc_sdram_dfi_p3_cs_n <= 1'd0; + soc_sdram_dfi_p3_bank <= vns_array_muxed21; + soc_sdram_dfi_p3_address <= vns_array_muxed22; + soc_sdram_dfi_p3_cas_n <= (~vns_array_muxed23); + soc_sdram_dfi_p3_ras_n <= (~vns_array_muxed24); + soc_sdram_dfi_p3_we_n <= (~vns_array_muxed25); + soc_sdram_dfi_p3_rddata_en <= vns_array_muxed26; + soc_sdram_dfi_p3_wrdata_en <= vns_array_muxed27; + if (soc_sdram_trrdcon_valid) begin + soc_sdram_trrdcon_count <= 1'd1; + if (1'd0) begin + soc_sdram_trrdcon_ready <= 1'd1; + end else begin + soc_sdram_trrdcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_trrdcon_ready)) begin + soc_sdram_trrdcon_count <= (soc_sdram_trrdcon_count - 1'd1); + if ((soc_sdram_trrdcon_count == 1'd1)) begin + soc_sdram_trrdcon_ready <= 1'd1; + end + end + end + soc_sdram_tfawcon_window <= {soc_sdram_tfawcon_window, soc_sdram_tfawcon_valid}; + if ((soc_sdram_tfawcon_count < 3'd4)) begin + if ((soc_sdram_tfawcon_count == 2'd3)) begin + soc_sdram_tfawcon_ready <= (~soc_sdram_tfawcon_valid); + end else begin + soc_sdram_tfawcon_ready <= 1'd1; + end + end + if (soc_sdram_tccdcon_valid) begin + soc_sdram_tccdcon_count <= 1'd0; + if (1'd1) begin + soc_sdram_tccdcon_ready <= 1'd1; + end else begin + soc_sdram_tccdcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_tccdcon_ready)) begin + soc_sdram_tccdcon_count <= (soc_sdram_tccdcon_count - 1'd1); + if ((soc_sdram_tccdcon_count == 1'd1)) begin + soc_sdram_tccdcon_ready <= 1'd1; + end + end + end + if (soc_sdram_twtrcon_valid) begin + soc_sdram_twtrcon_count <= 3'd4; + if (1'd0) begin + soc_sdram_twtrcon_ready <= 1'd1; + end else begin + soc_sdram_twtrcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_twtrcon_ready)) begin + soc_sdram_twtrcon_count <= (soc_sdram_twtrcon_count - 1'd1); + if ((soc_sdram_twtrcon_count == 1'd1)) begin + soc_sdram_twtrcon_ready <= 1'd1; + end + end + end + vns_multiplexer_state <= vns_multiplexer_next_state; + vns_new_master_wdata_ready0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_sdram_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd0) & soc_sdram_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd0) & soc_sdram_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd0) & soc_sdram_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd0) & soc_sdram_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd0) & soc_sdram_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd0) & soc_sdram_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd0) & soc_sdram_interface_bank7_wdata_ready)); + vns_new_master_wdata_ready1 <= vns_new_master_wdata_ready0; + vns_new_master_wdata_ready2 <= vns_new_master_wdata_ready1; + vns_new_master_wdata_ready3 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd1) & soc_sdram_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd1) & soc_sdram_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd1) & soc_sdram_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd1) & soc_sdram_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd1) & soc_sdram_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd1) & soc_sdram_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd1) & soc_sdram_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd1) & soc_sdram_interface_bank7_wdata_ready)); + vns_new_master_wdata_ready4 <= vns_new_master_wdata_ready3; + vns_new_master_wdata_ready5 <= vns_new_master_wdata_ready4; + vns_new_master_rdata_valid0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_sdram_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd0) & soc_sdram_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd0) & soc_sdram_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd0) & soc_sdram_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd0) & soc_sdram_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd0) & soc_sdram_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd0) & soc_sdram_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd0) & soc_sdram_interface_bank7_rdata_valid)); + vns_new_master_rdata_valid1 <= vns_new_master_rdata_valid0; + vns_new_master_rdata_valid2 <= vns_new_master_rdata_valid1; + vns_new_master_rdata_valid3 <= vns_new_master_rdata_valid2; + vns_new_master_rdata_valid4 <= vns_new_master_rdata_valid3; + vns_new_master_rdata_valid5 <= vns_new_master_rdata_valid4; + vns_new_master_rdata_valid6 <= vns_new_master_rdata_valid5; + vns_new_master_rdata_valid7 <= vns_new_master_rdata_valid6; + vns_new_master_rdata_valid8 <= vns_new_master_rdata_valid7; + vns_new_master_rdata_valid9 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd1) & soc_sdram_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd1) & soc_sdram_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd1) & soc_sdram_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd1) & soc_sdram_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd1) & soc_sdram_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd1) & soc_sdram_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd1) & soc_sdram_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd1) & soc_sdram_interface_bank7_rdata_valid)); + vns_new_master_rdata_valid10 <= vns_new_master_rdata_valid9; + vns_new_master_rdata_valid11 <= vns_new_master_rdata_valid10; + vns_new_master_rdata_valid12 <= vns_new_master_rdata_valid11; + vns_new_master_rdata_valid13 <= vns_new_master_rdata_valid12; + vns_new_master_rdata_valid14 <= vns_new_master_rdata_valid13; + vns_new_master_rdata_valid15 <= vns_new_master_rdata_valid14; + vns_new_master_rdata_valid16 <= vns_new_master_rdata_valid15; + vns_new_master_rdata_valid17 <= vns_new_master_rdata_valid16; + if (vns_roundrobin0_ce) begin + case (vns_roundrobin0_grant) + 1'd0: begin + if (vns_roundrobin0_request[1]) begin + vns_roundrobin0_grant <= 1'd1; + end + end + 1'd1: begin + if (vns_roundrobin0_request[0]) begin + vns_roundrobin0_grant <= 1'd0; + end + end + endcase + end + if (vns_roundrobin1_ce) begin + case (vns_roundrobin1_grant) + 1'd0: begin + if (vns_roundrobin1_request[1]) begin + vns_roundrobin1_grant <= 1'd1; + end + end + 1'd1: begin + if (vns_roundrobin1_request[0]) begin + vns_roundrobin1_grant <= 1'd0; + end + end + endcase + end + if (vns_roundrobin2_ce) begin + case (vns_roundrobin2_grant) + 1'd0: begin + if (vns_roundrobin2_request[1]) begin + vns_roundrobin2_grant <= 1'd1; + end + end + 1'd1: begin + if (vns_roundrobin2_request[0]) begin + vns_roundrobin2_grant <= 1'd0; + end + end + endcase + end + if (vns_roundrobin3_ce) begin + case (vns_roundrobin3_grant) + 1'd0: begin + if (vns_roundrobin3_request[1]) begin + vns_roundrobin3_grant <= 1'd1; + end + end + 1'd1: begin + if (vns_roundrobin3_request[0]) begin + vns_roundrobin3_grant <= 1'd0; + end + end + endcase + end + if (vns_roundrobin4_ce) begin + case (vns_roundrobin4_grant) + 1'd0: begin + if (vns_roundrobin4_request[1]) begin + vns_roundrobin4_grant <= 1'd1; + end + end + 1'd1: begin + if (vns_roundrobin4_request[0]) begin + vns_roundrobin4_grant <= 1'd0; + end + end + endcase + end + if (vns_roundrobin5_ce) begin + case (vns_roundrobin5_grant) + 1'd0: begin + if (vns_roundrobin5_request[1]) begin + vns_roundrobin5_grant <= 1'd1; + end + end + 1'd1: begin + if (vns_roundrobin5_request[0]) begin + vns_roundrobin5_grant <= 1'd0; + end + end + endcase + end + if (vns_roundrobin6_ce) begin + case (vns_roundrobin6_grant) + 1'd0: begin + if (vns_roundrobin6_request[1]) begin + vns_roundrobin6_grant <= 1'd1; + end + end + 1'd1: begin + if (vns_roundrobin6_request[0]) begin + vns_roundrobin6_grant <= 1'd0; + end + end + endcase + end + if (vns_roundrobin7_ce) begin + case (vns_roundrobin7_grant) + 1'd0: begin + if (vns_roundrobin7_request[1]) begin + vns_roundrobin7_grant <= 1'd1; + end + end + 1'd1: begin + if (vns_roundrobin7_request[0]) begin + vns_roundrobin7_grant <= 1'd0; + end + end + endcase + end + if (soc_counter_reset) begin + soc_counter <= 1'd0; + end else begin + if (soc_counter_ce) begin + soc_counter <= (soc_counter + 1'd1); + end + end + if (soc_address_ce) begin + soc_address_q <= soc_address_d; + end + if (soc_address_reset) begin + soc_address_q <= 30'd0; + end + if (soc_need_refill_ce) begin + soc_need_refill_q <= soc_need_refill_d; + end + if (soc_need_refill_reset) begin + soc_need_refill_q <= 1'd1; + end + vns_converter_state <= vns_converter_next_state; + if (soc_cached_datas_ce0) begin + soc_cached_datas_flipflop0_q <= soc_cached_datas_flipflop0_d; + end + if (soc_cached_datas_reset0) begin + soc_cached_datas_flipflop0_q <= 32'd0; + end + if (soc_cached_datas_ce1) begin + soc_cached_datas_flipflop1_q <= soc_cached_datas_flipflop1_d; + end + if (soc_cached_datas_reset1) begin + soc_cached_datas_flipflop1_q <= 32'd0; + end + if (soc_cached_datas_ce2) begin + soc_cached_datas_flipflop2_q <= soc_cached_datas_flipflop2_d; + end + if (soc_cached_datas_reset2) begin + soc_cached_datas_flipflop2_q <= 32'd0; + end + if (soc_cached_datas_ce3) begin + soc_cached_datas_flipflop3_q <= soc_cached_datas_flipflop3_d; + end + if (soc_cached_datas_reset3) begin + soc_cached_datas_flipflop3_q <= 32'd0; + end + if (soc_cached_sels_ce0) begin + soc_cached_sels_flipflop0_q <= soc_cached_sels_flipflop0_d; + end + if (soc_cached_sels_reset0) begin + soc_cached_sels_flipflop0_q <= 4'd0; + end + if (soc_cached_sels_ce1) begin + soc_cached_sels_flipflop1_q <= soc_cached_sels_flipflop1_d; + end + if (soc_cached_sels_reset1) begin + soc_cached_sels_flipflop1_q <= 4'd0; + end + if (soc_cached_sels_ce2) begin + soc_cached_sels_flipflop2_q <= soc_cached_sels_flipflop2_d; + end + if (soc_cached_sels_reset2) begin + soc_cached_sels_flipflop2_q <= 4'd0; + end + if (soc_cached_sels_ce3) begin + soc_cached_sels_flipflop3_q <= soc_cached_sels_flipflop3_d; + end + if (soc_cached_sels_reset3) begin + soc_cached_sels_flipflop3_q <= 4'd0; + end + vns_litedramwishbone2native_state <= vns_litedramwishbone2native_next_state; + if (soc_count_next_value_ce) begin + soc_count <= soc_count_next_value; + end + case (vns_grant) + 1'd0: begin + if ((~vns_request[0])) begin + if (vns_request[1]) begin + vns_grant <= 1'd1; + end + end + end + 1'd1: begin + if ((~vns_request[1])) begin + if (vns_request[0]) begin + vns_grant <= 1'd0; + end + end + end + endcase + vns_slave_sel_r <= vns_slave_sel; + if (vns_wait) begin + if ((~vns_done)) begin + vns_count <= (vns_count - 1'd1); + end + end else begin + vns_count <= 20'd1000000; + end + vns_interface0_bank_bus_dat_r <= 1'd0; + if (vns_csrbank0_sel) begin + case (vns_interface0_bank_bus_adr[3:0]) + 1'd0: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_reset0_w; + end + 1'd1: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch3_w; + end + 2'd2: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch2_w; + end + 2'd3: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch1_w; + end + 3'd4: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch0_w; + end + 3'd5: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors3_w; + end + 3'd6: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors2_w; + end + 3'd7: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors1_w; + end + 4'd8: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors0_w; + end + endcase + end + if (vns_csrbank0_reset0_re) begin + soc_litedramcore_soccontroller_reset_storage <= vns_csrbank0_reset0_r; + end + soc_litedramcore_soccontroller_reset_re <= vns_csrbank0_reset0_re; + if (vns_csrbank0_scratch3_re) begin + soc_litedramcore_soccontroller_scratch_storage[31:24] <= vns_csrbank0_scratch3_r; + end + if (vns_csrbank0_scratch2_re) begin + soc_litedramcore_soccontroller_scratch_storage[23:16] <= vns_csrbank0_scratch2_r; + end + if (vns_csrbank0_scratch1_re) begin + soc_litedramcore_soccontroller_scratch_storage[15:8] <= vns_csrbank0_scratch1_r; + end + if (vns_csrbank0_scratch0_re) begin + soc_litedramcore_soccontroller_scratch_storage[7:0] <= vns_csrbank0_scratch0_r; + end + soc_litedramcore_soccontroller_scratch_re <= vns_csrbank0_scratch0_re; + vns_interface1_bank_bus_dat_r <= 1'd0; + if (vns_csrbank1_sel) begin + case (vns_interface1_bank_bus_adr[0]) + 1'd0: begin + vns_interface1_bank_bus_dat_r <= vns_csrbank1_init_done0_w; + end + 1'd1: begin + vns_interface1_bank_bus_dat_r <= vns_csrbank1_init_error0_w; + end + endcase + end + if (vns_csrbank1_init_done0_re) begin + soc_init_done_storage <= vns_csrbank1_init_done0_r; + end + soc_init_done_re <= vns_csrbank1_init_done0_re; + if (vns_csrbank1_init_error0_re) begin + soc_init_error_storage <= vns_csrbank1_init_error0_r; + end + soc_init_error_re <= vns_csrbank1_init_error0_re; + vns_interface2_bank_bus_dat_r <= 1'd0; + if (vns_csrbank2_sel) begin + case (vns_interface2_bank_bus_adr[3:0]) + 1'd0: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_half_sys8x_taps0_w; + end + 1'd1: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_wlevel_en0_w; + end + 2'd2: begin + vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_wlevel_strobe_w; + end + 2'd3: begin + vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_cdly_rst_w; + end + 3'd4: begin + vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_cdly_inc_w; + end + 3'd5: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dly_sel0_w; + end + 3'd6: begin + vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_rst_w; + end + 3'd7: begin + vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_inc_w; + end + 4'd8: begin + vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_rst_w; + end + 4'd9: begin + vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_w; + end + endcase + end + if (vns_csrbank2_half_sys8x_taps0_re) begin + soc_a7ddrphy_half_sys8x_taps_storage[4:0] <= vns_csrbank2_half_sys8x_taps0_r; + end + soc_a7ddrphy_half_sys8x_taps_re <= vns_csrbank2_half_sys8x_taps0_re; + if (vns_csrbank2_wlevel_en0_re) begin + soc_a7ddrphy_wlevel_en_storage <= vns_csrbank2_wlevel_en0_r; + end + soc_a7ddrphy_wlevel_en_re <= vns_csrbank2_wlevel_en0_re; + if (vns_csrbank2_dly_sel0_re) begin + soc_a7ddrphy_dly_sel_storage[1:0] <= vns_csrbank2_dly_sel0_r; + end + soc_a7ddrphy_dly_sel_re <= vns_csrbank2_dly_sel0_re; + vns_interface3_bank_bus_dat_r <= 1'd0; + if (vns_csrbank3_sel) begin + case (vns_interface3_bank_bus_adr[5:0]) + 1'd0: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_control0_w; + end + 1'd1: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_command0_w; + end + 2'd2: begin + vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector0_command_issue_w; + end + 2'd3: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_address1_w; + end + 3'd4: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_address0_w; + end + 3'd5: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_baddress0_w; + end + 3'd6: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata3_w; + end + 3'd7: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata2_w; + end + 4'd8: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata1_w; + end + 4'd9: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata0_w; + end + 4'd10: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata3_w; + end + 4'd11: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata2_w; + end + 4'd12: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata1_w; + end + 4'd13: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata0_w; + end + 4'd14: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_command0_w; + end + 4'd15: begin + vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector1_command_issue_w; + end + 5'd16: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_address1_w; + end + 5'd17: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_address0_w; + end + 5'd18: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_baddress0_w; + end + 5'd19: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata3_w; + end + 5'd20: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata2_w; + end + 5'd21: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata1_w; + end + 5'd22: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata0_w; + end + 5'd23: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata3_w; + end + 5'd24: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata2_w; + end + 5'd25: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata1_w; + end + 5'd26: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata0_w; + end + 5'd27: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_command0_w; + end + 5'd28: begin + vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector2_command_issue_w; + end + 5'd29: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_address1_w; + end + 5'd30: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_address0_w; + end + 5'd31: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_baddress0_w; + end + 6'd32: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata3_w; + end + 6'd33: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata2_w; + end + 6'd34: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata1_w; + end + 6'd35: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata0_w; + end + 6'd36: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata3_w; + end + 6'd37: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata2_w; + end + 6'd38: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata1_w; + end + 6'd39: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata0_w; + end + 6'd40: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_command0_w; + end + 6'd41: begin + vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector3_command_issue_w; + end + 6'd42: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_address1_w; + end + 6'd43: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_address0_w; + end + 6'd44: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_baddress0_w; + end + 6'd45: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata3_w; + end + 6'd46: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata2_w; + end + 6'd47: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata1_w; + end + 6'd48: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata0_w; + end + 6'd49: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata3_w; + end + 6'd50: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata2_w; + end + 6'd51: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata1_w; + end + 6'd52: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata0_w; + end + endcase + end + if (vns_csrbank3_dfii_control0_re) begin + soc_sdram_storage[3:0] <= vns_csrbank3_dfii_control0_r; + end + soc_sdram_re <= vns_csrbank3_dfii_control0_re; + if (vns_csrbank3_dfii_pi0_command0_re) begin + soc_sdram_phaseinjector0_command_storage[5:0] <= vns_csrbank3_dfii_pi0_command0_r; + end + soc_sdram_phaseinjector0_command_re <= vns_csrbank3_dfii_pi0_command0_re; + if (vns_csrbank3_dfii_pi0_address1_re) begin + soc_sdram_phaseinjector0_address_storage[13:8] <= vns_csrbank3_dfii_pi0_address1_r; + end + if (vns_csrbank3_dfii_pi0_address0_re) begin + soc_sdram_phaseinjector0_address_storage[7:0] <= vns_csrbank3_dfii_pi0_address0_r; + end + soc_sdram_phaseinjector0_address_re <= vns_csrbank3_dfii_pi0_address0_re; + if (vns_csrbank3_dfii_pi0_baddress0_re) begin + soc_sdram_phaseinjector0_baddress_storage[2:0] <= vns_csrbank3_dfii_pi0_baddress0_r; + end + soc_sdram_phaseinjector0_baddress_re <= vns_csrbank3_dfii_pi0_baddress0_re; + if (vns_csrbank3_dfii_pi0_wrdata3_re) begin + soc_sdram_phaseinjector0_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi0_wrdata3_r; + end + if (vns_csrbank3_dfii_pi0_wrdata2_re) begin + soc_sdram_phaseinjector0_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi0_wrdata2_r; + end + if (vns_csrbank3_dfii_pi0_wrdata1_re) begin + soc_sdram_phaseinjector0_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi0_wrdata1_r; + end + if (vns_csrbank3_dfii_pi0_wrdata0_re) begin + soc_sdram_phaseinjector0_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi0_wrdata0_r; + end + soc_sdram_phaseinjector0_wrdata_re <= vns_csrbank3_dfii_pi0_wrdata0_re; + if (vns_csrbank3_dfii_pi1_command0_re) begin + soc_sdram_phaseinjector1_command_storage[5:0] <= vns_csrbank3_dfii_pi1_command0_r; + end + soc_sdram_phaseinjector1_command_re <= vns_csrbank3_dfii_pi1_command0_re; + if (vns_csrbank3_dfii_pi1_address1_re) begin + soc_sdram_phaseinjector1_address_storage[13:8] <= vns_csrbank3_dfii_pi1_address1_r; + end + if (vns_csrbank3_dfii_pi1_address0_re) begin + soc_sdram_phaseinjector1_address_storage[7:0] <= vns_csrbank3_dfii_pi1_address0_r; + end + soc_sdram_phaseinjector1_address_re <= vns_csrbank3_dfii_pi1_address0_re; + if (vns_csrbank3_dfii_pi1_baddress0_re) begin + soc_sdram_phaseinjector1_baddress_storage[2:0] <= vns_csrbank3_dfii_pi1_baddress0_r; + end + soc_sdram_phaseinjector1_baddress_re <= vns_csrbank3_dfii_pi1_baddress0_re; + if (vns_csrbank3_dfii_pi1_wrdata3_re) begin + soc_sdram_phaseinjector1_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi1_wrdata3_r; + end + if (vns_csrbank3_dfii_pi1_wrdata2_re) begin + soc_sdram_phaseinjector1_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi1_wrdata2_r; + end + if (vns_csrbank3_dfii_pi1_wrdata1_re) begin + soc_sdram_phaseinjector1_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi1_wrdata1_r; + end + if (vns_csrbank3_dfii_pi1_wrdata0_re) begin + soc_sdram_phaseinjector1_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi1_wrdata0_r; + end + soc_sdram_phaseinjector1_wrdata_re <= vns_csrbank3_dfii_pi1_wrdata0_re; + if (vns_csrbank3_dfii_pi2_command0_re) begin + soc_sdram_phaseinjector2_command_storage[5:0] <= vns_csrbank3_dfii_pi2_command0_r; + end + soc_sdram_phaseinjector2_command_re <= vns_csrbank3_dfii_pi2_command0_re; + if (vns_csrbank3_dfii_pi2_address1_re) begin + soc_sdram_phaseinjector2_address_storage[13:8] <= vns_csrbank3_dfii_pi2_address1_r; + end + if (vns_csrbank3_dfii_pi2_address0_re) begin + soc_sdram_phaseinjector2_address_storage[7:0] <= vns_csrbank3_dfii_pi2_address0_r; + end + soc_sdram_phaseinjector2_address_re <= vns_csrbank3_dfii_pi2_address0_re; + if (vns_csrbank3_dfii_pi2_baddress0_re) begin + soc_sdram_phaseinjector2_baddress_storage[2:0] <= vns_csrbank3_dfii_pi2_baddress0_r; + end + soc_sdram_phaseinjector2_baddress_re <= vns_csrbank3_dfii_pi2_baddress0_re; + if (vns_csrbank3_dfii_pi2_wrdata3_re) begin + soc_sdram_phaseinjector2_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi2_wrdata3_r; + end + if (vns_csrbank3_dfii_pi2_wrdata2_re) begin + soc_sdram_phaseinjector2_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi2_wrdata2_r; + end + if (vns_csrbank3_dfii_pi2_wrdata1_re) begin + soc_sdram_phaseinjector2_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi2_wrdata1_r; + end + if (vns_csrbank3_dfii_pi2_wrdata0_re) begin + soc_sdram_phaseinjector2_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi2_wrdata0_r; + end + soc_sdram_phaseinjector2_wrdata_re <= vns_csrbank3_dfii_pi2_wrdata0_re; + if (vns_csrbank3_dfii_pi3_command0_re) begin + soc_sdram_phaseinjector3_command_storage[5:0] <= vns_csrbank3_dfii_pi3_command0_r; + end + soc_sdram_phaseinjector3_command_re <= vns_csrbank3_dfii_pi3_command0_re; + if (vns_csrbank3_dfii_pi3_address1_re) begin + soc_sdram_phaseinjector3_address_storage[13:8] <= vns_csrbank3_dfii_pi3_address1_r; + end + if (vns_csrbank3_dfii_pi3_address0_re) begin + soc_sdram_phaseinjector3_address_storage[7:0] <= vns_csrbank3_dfii_pi3_address0_r; + end + soc_sdram_phaseinjector3_address_re <= vns_csrbank3_dfii_pi3_address0_re; + if (vns_csrbank3_dfii_pi3_baddress0_re) begin + soc_sdram_phaseinjector3_baddress_storage[2:0] <= vns_csrbank3_dfii_pi3_baddress0_r; + end + soc_sdram_phaseinjector3_baddress_re <= vns_csrbank3_dfii_pi3_baddress0_re; + if (vns_csrbank3_dfii_pi3_wrdata3_re) begin + soc_sdram_phaseinjector3_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi3_wrdata3_r; + end + if (vns_csrbank3_dfii_pi3_wrdata2_re) begin + soc_sdram_phaseinjector3_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi3_wrdata2_r; + end + if (vns_csrbank3_dfii_pi3_wrdata1_re) begin + soc_sdram_phaseinjector3_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi3_wrdata1_r; + end + if (vns_csrbank3_dfii_pi3_wrdata0_re) begin + soc_sdram_phaseinjector3_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi3_wrdata0_r; + end + soc_sdram_phaseinjector3_wrdata_re <= vns_csrbank3_dfii_pi3_wrdata0_re; + vns_interface4_bank_bus_dat_r <= 1'd0; + if (vns_csrbank4_sel) begin + case (vns_interface4_bank_bus_adr[4:0]) + 1'd0: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_load3_w; + end + 1'd1: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_load2_w; + end + 2'd2: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_load1_w; + end + 2'd3: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_load0_w; + end + 3'd4: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload3_w; + end + 3'd5: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload2_w; + end + 3'd6: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload1_w; + end + 3'd7: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload0_w; + end + 4'd8: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_en0_w; + end + 4'd9: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_update_value0_w; + end + 4'd10: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_value3_w; + end + 4'd11: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_value2_w; + end + 4'd12: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_value1_w; + end + 4'd13: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_value0_w; + end + 4'd14: begin + vns_interface4_bank_bus_dat_r <= soc_litedramcore_timer_eventmanager_status_w; + end + 4'd15: begin + vns_interface4_bank_bus_dat_r <= soc_litedramcore_timer_eventmanager_pending_w; + end + 5'd16: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_ev_enable0_w; + end + endcase + end + if (vns_csrbank4_load3_re) begin + soc_litedramcore_timer_load_storage[31:24] <= vns_csrbank4_load3_r; + end + if (vns_csrbank4_load2_re) begin + soc_litedramcore_timer_load_storage[23:16] <= vns_csrbank4_load2_r; + end + if (vns_csrbank4_load1_re) begin + soc_litedramcore_timer_load_storage[15:8] <= vns_csrbank4_load1_r; + end + if (vns_csrbank4_load0_re) begin + soc_litedramcore_timer_load_storage[7:0] <= vns_csrbank4_load0_r; + end + soc_litedramcore_timer_load_re <= vns_csrbank4_load0_re; + if (vns_csrbank4_reload3_re) begin + soc_litedramcore_timer_reload_storage[31:24] <= vns_csrbank4_reload3_r; + end + if (vns_csrbank4_reload2_re) begin + soc_litedramcore_timer_reload_storage[23:16] <= vns_csrbank4_reload2_r; + end + if (vns_csrbank4_reload1_re) begin + soc_litedramcore_timer_reload_storage[15:8] <= vns_csrbank4_reload1_r; + end + if (vns_csrbank4_reload0_re) begin + soc_litedramcore_timer_reload_storage[7:0] <= vns_csrbank4_reload0_r; + end + soc_litedramcore_timer_reload_re <= vns_csrbank4_reload0_re; + if (vns_csrbank4_en0_re) begin + soc_litedramcore_timer_en_storage <= vns_csrbank4_en0_r; + end + soc_litedramcore_timer_en_re <= vns_csrbank4_en0_re; + if (vns_csrbank4_update_value0_re) begin + soc_litedramcore_timer_update_value_storage <= vns_csrbank4_update_value0_r; + end + soc_litedramcore_timer_update_value_re <= vns_csrbank4_update_value0_re; + if (vns_csrbank4_ev_enable0_re) begin + soc_litedramcore_timer_eventmanager_storage <= vns_csrbank4_ev_enable0_r; + end + soc_litedramcore_timer_eventmanager_re <= vns_csrbank4_ev_enable0_re; + vns_interface5_bank_bus_dat_r <= 1'd0; + if (vns_csrbank5_sel) begin + case (vns_interface5_bank_bus_adr[2:0]) + 1'd0: begin + vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_rxtx_w; + end + 1'd1: begin + vns_interface5_bank_bus_dat_r <= vns_csrbank5_txfull_w; + end + 2'd2: begin + vns_interface5_bank_bus_dat_r <= vns_csrbank5_rxempty_w; + end + 2'd3: begin + vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_eventmanager_status_w; + end + 3'd4: begin + vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_eventmanager_pending_w; + end + 3'd5: begin + vns_interface5_bank_bus_dat_r <= vns_csrbank5_ev_enable0_w; + end + endcase + end + if (vns_csrbank5_ev_enable0_re) begin + soc_litedramcore_uart_eventmanager_storage[1:0] <= vns_csrbank5_ev_enable0_r; + end + soc_litedramcore_uart_eventmanager_re <= vns_csrbank5_ev_enable0_re; + vns_interface6_bank_bus_dat_r <= 1'd0; + if (vns_csrbank6_sel) begin + case (vns_interface6_bank_bus_adr[1:0]) + 1'd0: begin + vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word3_w; + end + 1'd1: begin + vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word2_w; + end + 2'd2: begin + vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word1_w; + end + 2'd3: begin + vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word0_w; + end + endcase + end + if (vns_csrbank6_tuning_word3_re) begin + soc_litedramcore_storage[31:24] <= vns_csrbank6_tuning_word3_r; + end + if (vns_csrbank6_tuning_word2_re) begin + soc_litedramcore_storage[23:16] <= vns_csrbank6_tuning_word2_r; + end + if (vns_csrbank6_tuning_word1_re) begin + soc_litedramcore_storage[15:8] <= vns_csrbank6_tuning_word1_r; + end + if (vns_csrbank6_tuning_word0_re) begin + soc_litedramcore_storage[7:0] <= vns_csrbank6_tuning_word0_r; + end + soc_litedramcore_re <= vns_csrbank6_tuning_word0_re; + if (sys_rst) begin + soc_litedramcore_soccontroller_reset_storage <= 1'd0; + soc_litedramcore_soccontroller_reset_re <= 1'd0; + soc_litedramcore_soccontroller_scratch_storage <= 32'd305419896; + soc_litedramcore_soccontroller_scratch_re <= 1'd0; + soc_litedramcore_soccontroller_bus_errors <= 32'd0; + soc_litedramcore_litedramcore_ram_bus_ack <= 1'd0; + soc_litedramcore_ram_bus_ram_bus_ack <= 1'd0; + serial_tx <= 1'd1; + soc_litedramcore_storage <= 32'd4947802; + soc_litedramcore_re <= 1'd0; + soc_litedramcore_sink_ready <= 1'd0; + soc_litedramcore_uart_clk_txen <= 1'd0; + soc_litedramcore_tx_busy <= 1'd0; + soc_litedramcore_source_valid <= 1'd0; + soc_litedramcore_uart_clk_rxen <= 1'd0; + soc_litedramcore_rx_r <= 1'd0; + soc_litedramcore_rx_busy <= 1'd0; + soc_litedramcore_uart_tx_pending <= 1'd0; + soc_litedramcore_uart_tx_old_trigger <= 1'd0; + soc_litedramcore_uart_rx_pending <= 1'd0; + soc_litedramcore_uart_rx_old_trigger <= 1'd0; + soc_litedramcore_uart_eventmanager_storage <= 2'd0; + soc_litedramcore_uart_eventmanager_re <= 1'd0; + soc_litedramcore_uart_tx_fifo_readable <= 1'd0; + soc_litedramcore_uart_tx_fifo_level0 <= 5'd0; + soc_litedramcore_uart_tx_fifo_produce <= 4'd0; + soc_litedramcore_uart_tx_fifo_consume <= 4'd0; + soc_litedramcore_uart_rx_fifo_readable <= 1'd0; + soc_litedramcore_uart_rx_fifo_level0 <= 5'd0; + soc_litedramcore_uart_rx_fifo_produce <= 4'd0; + soc_litedramcore_uart_rx_fifo_consume <= 4'd0; + soc_litedramcore_timer_load_storage <= 32'd0; + soc_litedramcore_timer_load_re <= 1'd0; + soc_litedramcore_timer_reload_storage <= 32'd0; + soc_litedramcore_timer_reload_re <= 1'd0; + soc_litedramcore_timer_en_storage <= 1'd0; + soc_litedramcore_timer_en_re <= 1'd0; + soc_litedramcore_timer_update_value_storage <= 1'd0; + soc_litedramcore_timer_update_value_re <= 1'd0; + soc_litedramcore_timer_value_status <= 32'd0; + soc_litedramcore_timer_zero_pending <= 1'd0; + soc_litedramcore_timer_zero_old_trigger <= 1'd0; + soc_litedramcore_timer_eventmanager_storage <= 1'd0; + soc_litedramcore_timer_eventmanager_re <= 1'd0; + soc_litedramcore_timer_value <= 32'd0; + soc_a7ddrphy_half_sys8x_taps_storage <= 5'd8; + soc_a7ddrphy_half_sys8x_taps_re <= 1'd0; + soc_a7ddrphy_wlevel_en_storage <= 1'd0; + soc_a7ddrphy_wlevel_en_re <= 1'd0; + soc_a7ddrphy_dly_sel_storage <= 2'd0; + soc_a7ddrphy_dly_sel_re <= 1'd0; + soc_a7ddrphy_dfi_p0_rddata_valid <= 1'd0; + soc_a7ddrphy_dfi_p1_rddata_valid <= 1'd0; + soc_a7ddrphy_dfi_p2_rddata_valid <= 1'd0; + soc_a7ddrphy_dfi_p3_rddata_valid <= 1'd0; + soc_a7ddrphy_dqs_oe_delayed <= 1'd0; + soc_a7ddrphy_dqspattern_o1 <= 8'd0; + soc_a7ddrphy_dq_oe_delayed <= 1'd0; + soc_a7ddrphy_bitslip0_value <= 3'd0; + soc_a7ddrphy_bitslip1_value <= 3'd0; + soc_a7ddrphy_bitslip2_value <= 3'd0; + soc_a7ddrphy_bitslip3_value <= 3'd0; + soc_a7ddrphy_bitslip4_value <= 3'd0; + soc_a7ddrphy_bitslip5_value <= 3'd0; + soc_a7ddrphy_bitslip6_value <= 3'd0; + soc_a7ddrphy_bitslip7_value <= 3'd0; + soc_a7ddrphy_bitslip8_value <= 3'd0; + soc_a7ddrphy_bitslip9_value <= 3'd0; + soc_a7ddrphy_bitslip10_value <= 3'd0; + soc_a7ddrphy_bitslip11_value <= 3'd0; + soc_a7ddrphy_bitslip12_value <= 3'd0; + soc_a7ddrphy_bitslip13_value <= 3'd0; + soc_a7ddrphy_bitslip14_value <= 3'd0; + soc_a7ddrphy_bitslip15_value <= 3'd0; + soc_a7ddrphy_rddata_en_last <= 8'd0; + soc_a7ddrphy_wrdata_en_last <= 4'd0; + soc_sdram_storage <= 4'd0; + soc_sdram_re <= 1'd0; + soc_sdram_phaseinjector0_command_storage <= 6'd0; + soc_sdram_phaseinjector0_command_re <= 1'd0; + soc_sdram_phaseinjector0_address_re <= 1'd0; + soc_sdram_phaseinjector0_baddress_re <= 1'd0; + soc_sdram_phaseinjector0_wrdata_re <= 1'd0; + soc_sdram_phaseinjector0_status <= 32'd0; + soc_sdram_phaseinjector1_command_storage <= 6'd0; + soc_sdram_phaseinjector1_command_re <= 1'd0; + soc_sdram_phaseinjector1_address_re <= 1'd0; + soc_sdram_phaseinjector1_baddress_re <= 1'd0; + soc_sdram_phaseinjector1_wrdata_re <= 1'd0; + soc_sdram_phaseinjector1_status <= 32'd0; + soc_sdram_phaseinjector2_command_storage <= 6'd0; + soc_sdram_phaseinjector2_command_re <= 1'd0; + soc_sdram_phaseinjector2_address_re <= 1'd0; + soc_sdram_phaseinjector2_baddress_re <= 1'd0; + soc_sdram_phaseinjector2_wrdata_re <= 1'd0; + soc_sdram_phaseinjector2_status <= 32'd0; + soc_sdram_phaseinjector3_command_storage <= 6'd0; + soc_sdram_phaseinjector3_command_re <= 1'd0; + soc_sdram_phaseinjector3_address_re <= 1'd0; + soc_sdram_phaseinjector3_baddress_re <= 1'd0; + soc_sdram_phaseinjector3_wrdata_re <= 1'd0; + soc_sdram_phaseinjector3_status <= 32'd0; + soc_sdram_dfi_p0_address <= 14'd0; + soc_sdram_dfi_p0_bank <= 3'd0; + soc_sdram_dfi_p0_cas_n <= 1'd1; + soc_sdram_dfi_p0_cs_n <= 1'd1; + soc_sdram_dfi_p0_ras_n <= 1'd1; + soc_sdram_dfi_p0_we_n <= 1'd1; + soc_sdram_dfi_p0_wrdata_en <= 1'd0; + soc_sdram_dfi_p0_rddata_en <= 1'd0; + soc_sdram_dfi_p1_address <= 14'd0; + soc_sdram_dfi_p1_bank <= 3'd0; + soc_sdram_dfi_p1_cas_n <= 1'd1; + soc_sdram_dfi_p1_cs_n <= 1'd1; + soc_sdram_dfi_p1_ras_n <= 1'd1; + soc_sdram_dfi_p1_we_n <= 1'd1; + soc_sdram_dfi_p1_wrdata_en <= 1'd0; + soc_sdram_dfi_p1_rddata_en <= 1'd0; + soc_sdram_dfi_p2_address <= 14'd0; + soc_sdram_dfi_p2_bank <= 3'd0; + soc_sdram_dfi_p2_cas_n <= 1'd1; + soc_sdram_dfi_p2_cs_n <= 1'd1; + soc_sdram_dfi_p2_ras_n <= 1'd1; + soc_sdram_dfi_p2_we_n <= 1'd1; + soc_sdram_dfi_p2_wrdata_en <= 1'd0; + soc_sdram_dfi_p2_rddata_en <= 1'd0; + soc_sdram_dfi_p3_address <= 14'd0; + soc_sdram_dfi_p3_bank <= 3'd0; + soc_sdram_dfi_p3_cas_n <= 1'd1; + soc_sdram_dfi_p3_cs_n <= 1'd1; + soc_sdram_dfi_p3_ras_n <= 1'd1; + soc_sdram_dfi_p3_we_n <= 1'd1; + soc_sdram_dfi_p3_wrdata_en <= 1'd0; + soc_sdram_dfi_p3_rddata_en <= 1'd0; + soc_sdram_timer_count1 <= 10'd781; + soc_sdram_postponer_req_o <= 1'd0; + soc_sdram_postponer_count <= 1'd0; + soc_sdram_sequencer_done1 <= 1'd0; + soc_sdram_sequencer_counter <= 6'd0; + soc_sdram_sequencer_count <= 1'd0; + soc_sdram_zqcs_timer_count1 <= 27'd99999999; + soc_sdram_zqcs_executer_done <= 1'd0; + soc_sdram_zqcs_executer_counter <= 5'd0; + soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; + soc_sdram_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; + soc_sdram_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; + soc_sdram_bankmachine0_cmd_buffer_source_valid <= 1'd0; + soc_sdram_bankmachine0_row <= 14'd0; + soc_sdram_bankmachine0_row_opened <= 1'd0; + soc_sdram_bankmachine0_twtpcon_ready <= 1'd1; + soc_sdram_bankmachine0_twtpcon_count <= 3'd0; + soc_sdram_bankmachine0_trccon_ready <= 1'd1; + soc_sdram_bankmachine0_trccon_count <= 3'd0; + soc_sdram_bankmachine0_trascon_ready <= 1'd1; + soc_sdram_bankmachine0_trascon_count <= 3'd0; + soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; + soc_sdram_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; + soc_sdram_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; + soc_sdram_bankmachine1_cmd_buffer_source_valid <= 1'd0; + soc_sdram_bankmachine1_row <= 14'd0; + soc_sdram_bankmachine1_row_opened <= 1'd0; + soc_sdram_bankmachine1_twtpcon_ready <= 1'd1; + soc_sdram_bankmachine1_twtpcon_count <= 3'd0; + soc_sdram_bankmachine1_trccon_ready <= 1'd1; + soc_sdram_bankmachine1_trccon_count <= 3'd0; + soc_sdram_bankmachine1_trascon_ready <= 1'd1; + soc_sdram_bankmachine1_trascon_count <= 3'd0; + soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; + soc_sdram_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; + soc_sdram_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; + soc_sdram_bankmachine2_cmd_buffer_source_valid <= 1'd0; + soc_sdram_bankmachine2_row <= 14'd0; + soc_sdram_bankmachine2_row_opened <= 1'd0; + soc_sdram_bankmachine2_twtpcon_ready <= 1'd1; + soc_sdram_bankmachine2_twtpcon_count <= 3'd0; + soc_sdram_bankmachine2_trccon_ready <= 1'd1; + soc_sdram_bankmachine2_trccon_count <= 3'd0; + soc_sdram_bankmachine2_trascon_ready <= 1'd1; + soc_sdram_bankmachine2_trascon_count <= 3'd0; + soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; + soc_sdram_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; + soc_sdram_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; + soc_sdram_bankmachine3_cmd_buffer_source_valid <= 1'd0; + soc_sdram_bankmachine3_row <= 14'd0; + soc_sdram_bankmachine3_row_opened <= 1'd0; + soc_sdram_bankmachine3_twtpcon_ready <= 1'd1; + soc_sdram_bankmachine3_twtpcon_count <= 3'd0; + soc_sdram_bankmachine3_trccon_ready <= 1'd1; + soc_sdram_bankmachine3_trccon_count <= 3'd0; + soc_sdram_bankmachine3_trascon_ready <= 1'd1; + soc_sdram_bankmachine3_trascon_count <= 3'd0; + soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; + soc_sdram_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; + soc_sdram_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; + soc_sdram_bankmachine4_cmd_buffer_source_valid <= 1'd0; + soc_sdram_bankmachine4_row <= 14'd0; + soc_sdram_bankmachine4_row_opened <= 1'd0; + soc_sdram_bankmachine4_twtpcon_ready <= 1'd1; + soc_sdram_bankmachine4_twtpcon_count <= 3'd0; + soc_sdram_bankmachine4_trccon_ready <= 1'd1; + soc_sdram_bankmachine4_trccon_count <= 3'd0; + soc_sdram_bankmachine4_trascon_ready <= 1'd1; + soc_sdram_bankmachine4_trascon_count <= 3'd0; + soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; + soc_sdram_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; + soc_sdram_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; + soc_sdram_bankmachine5_cmd_buffer_source_valid <= 1'd0; + soc_sdram_bankmachine5_row <= 14'd0; + soc_sdram_bankmachine5_row_opened <= 1'd0; + soc_sdram_bankmachine5_twtpcon_ready <= 1'd1; + soc_sdram_bankmachine5_twtpcon_count <= 3'd0; + soc_sdram_bankmachine5_trccon_ready <= 1'd1; + soc_sdram_bankmachine5_trccon_count <= 3'd0; + soc_sdram_bankmachine5_trascon_ready <= 1'd1; + soc_sdram_bankmachine5_trascon_count <= 3'd0; + soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; + soc_sdram_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; + soc_sdram_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; + soc_sdram_bankmachine6_cmd_buffer_source_valid <= 1'd0; + soc_sdram_bankmachine6_row <= 14'd0; + soc_sdram_bankmachine6_row_opened <= 1'd0; + soc_sdram_bankmachine6_twtpcon_ready <= 1'd1; + soc_sdram_bankmachine6_twtpcon_count <= 3'd0; + soc_sdram_bankmachine6_trccon_ready <= 1'd1; + soc_sdram_bankmachine6_trccon_count <= 3'd0; + soc_sdram_bankmachine6_trascon_ready <= 1'd1; + soc_sdram_bankmachine6_trascon_count <= 3'd0; + soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; + soc_sdram_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; + soc_sdram_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; + soc_sdram_bankmachine7_cmd_buffer_source_valid <= 1'd0; + soc_sdram_bankmachine7_row <= 14'd0; + soc_sdram_bankmachine7_row_opened <= 1'd0; + soc_sdram_bankmachine7_twtpcon_ready <= 1'd1; + soc_sdram_bankmachine7_twtpcon_count <= 3'd0; + soc_sdram_bankmachine7_trccon_ready <= 1'd1; + soc_sdram_bankmachine7_trccon_count <= 3'd0; + soc_sdram_bankmachine7_trascon_ready <= 1'd1; + soc_sdram_bankmachine7_trascon_count <= 3'd0; + soc_sdram_choose_cmd_grant <= 3'd0; + soc_sdram_choose_req_grant <= 3'd0; + soc_sdram_trrdcon_ready <= 1'd1; + soc_sdram_trrdcon_count <= 1'd0; + soc_sdram_tfawcon_ready <= 1'd1; + soc_sdram_tfawcon_window <= 5'd0; + soc_sdram_tccdcon_ready <= 1'd1; + soc_sdram_tccdcon_count <= 1'd0; + soc_sdram_twtrcon_ready <= 1'd1; + soc_sdram_twtrcon_count <= 3'd0; + soc_sdram_time0 <= 5'd0; + soc_sdram_time1 <= 4'd0; + soc_address_q <= 30'd0; + soc_counter <= 2'd0; + soc_need_refill_q <= 1'd1; + soc_cached_datas_flipflop0_q <= 32'd0; + soc_cached_datas_flipflop1_q <= 32'd0; + soc_cached_datas_flipflop2_q <= 32'd0; + soc_cached_datas_flipflop3_q <= 32'd0; + soc_cached_sels_flipflop0_q <= 4'd0; + soc_cached_sels_flipflop1_q <= 4'd0; + soc_cached_sels_flipflop2_q <= 4'd0; + soc_cached_sels_flipflop3_q <= 4'd0; + soc_count <= 1'd0; + soc_init_done_storage <= 1'd0; + soc_init_done_re <= 1'd0; + soc_init_error_storage <= 1'd0; + soc_init_error_re <= 1'd0; + vns_wb2csr_state <= 1'd0; + vns_refresher_state <= 2'd0; + vns_bankmachine0_state <= 4'd0; + vns_bankmachine1_state <= 4'd0; + vns_bankmachine2_state <= 4'd0; + vns_bankmachine3_state <= 4'd0; + vns_bankmachine4_state <= 4'd0; + vns_bankmachine5_state <= 4'd0; + vns_bankmachine6_state <= 4'd0; + vns_bankmachine7_state <= 4'd0; + vns_multiplexer_state <= 4'd0; + vns_roundrobin0_grant <= 1'd0; + vns_roundrobin1_grant <= 1'd0; + vns_roundrobin2_grant <= 1'd0; + vns_roundrobin3_grant <= 1'd0; + vns_roundrobin4_grant <= 1'd0; + vns_roundrobin5_grant <= 1'd0; + vns_roundrobin6_grant <= 1'd0; + vns_roundrobin7_grant <= 1'd0; + vns_new_master_wdata_ready0 <= 1'd0; + vns_new_master_wdata_ready1 <= 1'd0; + vns_new_master_wdata_ready2 <= 1'd0; + vns_new_master_wdata_ready3 <= 1'd0; + vns_new_master_wdata_ready4 <= 1'd0; + vns_new_master_wdata_ready5 <= 1'd0; + vns_new_master_rdata_valid0 <= 1'd0; + vns_new_master_rdata_valid1 <= 1'd0; + vns_new_master_rdata_valid2 <= 1'd0; + vns_new_master_rdata_valid3 <= 1'd0; + vns_new_master_rdata_valid4 <= 1'd0; + vns_new_master_rdata_valid5 <= 1'd0; + vns_new_master_rdata_valid6 <= 1'd0; + vns_new_master_rdata_valid7 <= 1'd0; + vns_new_master_rdata_valid8 <= 1'd0; + vns_new_master_rdata_valid9 <= 1'd0; + vns_new_master_rdata_valid10 <= 1'd0; + vns_new_master_rdata_valid11 <= 1'd0; + vns_new_master_rdata_valid12 <= 1'd0; + vns_new_master_rdata_valid13 <= 1'd0; + vns_new_master_rdata_valid14 <= 1'd0; + vns_new_master_rdata_valid15 <= 1'd0; + vns_new_master_rdata_valid16 <= 1'd0; + vns_new_master_rdata_valid17 <= 1'd0; + vns_converter_state <= 3'd0; + vns_litedramwishbone2native_state <= 2'd0; + vns_grant <= 1'd0; + vns_slave_sel_r <= 4'd0; + vns_count <= 20'd1000000; + end + vns_regs0 <= serial_rx; + vns_regs1 <= vns_regs0; +end + +reg [31:0] mem[0:6143]; +reg [31:0] memdat; +always @(posedge sys_clk) begin + memdat <= mem[soc_litedramcore_litedramcore_adr]; +end + +assign soc_litedramcore_litedramcore_dat_r = memdat; + +initial begin + $readmemh("litedram_core.init", mem); +end + +reg [31:0] mem_1[0:1023]; +reg [9:0] memadr; +always @(posedge sys_clk) begin + if (soc_litedramcore_ram_we[0]) + mem_1[soc_litedramcore_ram_adr][7:0] <= soc_litedramcore_ram_dat_w[7:0]; + if (soc_litedramcore_ram_we[1]) + mem_1[soc_litedramcore_ram_adr][15:8] <= soc_litedramcore_ram_dat_w[15:8]; + if (soc_litedramcore_ram_we[2]) + mem_1[soc_litedramcore_ram_adr][23:16] <= soc_litedramcore_ram_dat_w[23:16]; + if (soc_litedramcore_ram_we[3]) + mem_1[soc_litedramcore_ram_adr][31:24] <= soc_litedramcore_ram_dat_w[31:24]; + memadr <= soc_litedramcore_ram_adr; +end + +assign soc_litedramcore_ram_dat_r = mem_1[memadr]; + +initial begin + $readmemh("mem_1.init", mem_1); +end + +reg [9:0] storage[0:15]; +reg [9:0] memdat_1; +reg [9:0] memdat_2; +always @(posedge sys_clk) begin + if (soc_litedramcore_uart_tx_fifo_wrport_we) + storage[soc_litedramcore_uart_tx_fifo_wrport_adr] <= soc_litedramcore_uart_tx_fifo_wrport_dat_w; + memdat_1 <= storage[soc_litedramcore_uart_tx_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (soc_litedramcore_uart_tx_fifo_rdport_re) + memdat_2 <= storage[soc_litedramcore_uart_tx_fifo_rdport_adr]; +end + +assign soc_litedramcore_uart_tx_fifo_wrport_dat_r = memdat_1; +assign soc_litedramcore_uart_tx_fifo_rdport_dat_r = memdat_2; + +reg [9:0] storage_1[0:15]; +reg [9:0] memdat_3; +reg [9:0] memdat_4; +always @(posedge sys_clk) begin + if (soc_litedramcore_uart_rx_fifo_wrport_we) + storage_1[soc_litedramcore_uart_rx_fifo_wrport_adr] <= soc_litedramcore_uart_rx_fifo_wrport_dat_w; + memdat_3 <= storage_1[soc_litedramcore_uart_rx_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (soc_litedramcore_uart_rx_fifo_rdport_re) + memdat_4 <= storage_1[soc_litedramcore_uart_rx_fifo_rdport_adr]; +end + +assign soc_litedramcore_uart_rx_fifo_wrport_dat_r = memdat_3; +assign soc_litedramcore_uart_rx_fifo_rdport_dat_r = memdat_4; + +BUFG BUFG( + .I(soc_s7pll0_clkout0), + .O(soc_s7pll0_clkout_buf0) +); + +BUFG BUFG_1( + .I(soc_s7pll0_clkout1), + .O(soc_s7pll0_clkout_buf1) +); + +BUFG BUFG_2( + .I(soc_s7pll0_clkout2), + .O(soc_s7pll0_clkout_buf2) +); + +BUFG BUFG_3( + .I(soc_s7pll1_clkout), + .O(soc_s7pll1_clkout_buf) +); + +IDELAYCTRL IDELAYCTRL( + .REFCLK(iodelay_clk), + .RST(soc_ic_reset) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(1'd0), + .D2(1'd1), + .D3(1'd0), + .D4(1'd1), + .D5(1'd0), + .D6(1'd1), + .D7(1'd0), + .D8(1'd1), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_a7ddrphy_sd_clk_se_nodelay) +); + +OBUFDS OBUFDS( + .I(soc_a7ddrphy_sd_clk_se_nodelay), + .O(ddram_clk_p), + .OB(ddram_clk_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_1 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[0]), + .D2(soc_a7ddrphy_dfi_p0_address[0]), + .D3(soc_a7ddrphy_dfi_p1_address[0]), + .D4(soc_a7ddrphy_dfi_p1_address[0]), + .D5(soc_a7ddrphy_dfi_p2_address[0]), + .D6(soc_a7ddrphy_dfi_p2_address[0]), + .D7(soc_a7ddrphy_dfi_p3_address[0]), + .D8(soc_a7ddrphy_dfi_p3_address[0]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_2 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[1]), + .D2(soc_a7ddrphy_dfi_p0_address[1]), + .D3(soc_a7ddrphy_dfi_p1_address[1]), + .D4(soc_a7ddrphy_dfi_p1_address[1]), + .D5(soc_a7ddrphy_dfi_p2_address[1]), + .D6(soc_a7ddrphy_dfi_p2_address[1]), + .D7(soc_a7ddrphy_dfi_p3_address[1]), + .D8(soc_a7ddrphy_dfi_p3_address[1]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_3 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[2]), + .D2(soc_a7ddrphy_dfi_p0_address[2]), + .D3(soc_a7ddrphy_dfi_p1_address[2]), + .D4(soc_a7ddrphy_dfi_p1_address[2]), + .D5(soc_a7ddrphy_dfi_p2_address[2]), + .D6(soc_a7ddrphy_dfi_p2_address[2]), + .D7(soc_a7ddrphy_dfi_p3_address[2]), + .D8(soc_a7ddrphy_dfi_p3_address[2]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[2]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_4 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[3]), + .D2(soc_a7ddrphy_dfi_p0_address[3]), + .D3(soc_a7ddrphy_dfi_p1_address[3]), + .D4(soc_a7ddrphy_dfi_p1_address[3]), + .D5(soc_a7ddrphy_dfi_p2_address[3]), + .D6(soc_a7ddrphy_dfi_p2_address[3]), + .D7(soc_a7ddrphy_dfi_p3_address[3]), + .D8(soc_a7ddrphy_dfi_p3_address[3]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[3]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_5 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[4]), + .D2(soc_a7ddrphy_dfi_p0_address[4]), + .D3(soc_a7ddrphy_dfi_p1_address[4]), + .D4(soc_a7ddrphy_dfi_p1_address[4]), + .D5(soc_a7ddrphy_dfi_p2_address[4]), + .D6(soc_a7ddrphy_dfi_p2_address[4]), + .D7(soc_a7ddrphy_dfi_p3_address[4]), + .D8(soc_a7ddrphy_dfi_p3_address[4]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[4]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_6 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[5]), + .D2(soc_a7ddrphy_dfi_p0_address[5]), + .D3(soc_a7ddrphy_dfi_p1_address[5]), + .D4(soc_a7ddrphy_dfi_p1_address[5]), + .D5(soc_a7ddrphy_dfi_p2_address[5]), + .D6(soc_a7ddrphy_dfi_p2_address[5]), + .D7(soc_a7ddrphy_dfi_p3_address[5]), + .D8(soc_a7ddrphy_dfi_p3_address[5]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[5]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_7 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[6]), + .D2(soc_a7ddrphy_dfi_p0_address[6]), + .D3(soc_a7ddrphy_dfi_p1_address[6]), + .D4(soc_a7ddrphy_dfi_p1_address[6]), + .D5(soc_a7ddrphy_dfi_p2_address[6]), + .D6(soc_a7ddrphy_dfi_p2_address[6]), + .D7(soc_a7ddrphy_dfi_p3_address[6]), + .D8(soc_a7ddrphy_dfi_p3_address[6]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[6]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_8 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[7]), + .D2(soc_a7ddrphy_dfi_p0_address[7]), + .D3(soc_a7ddrphy_dfi_p1_address[7]), + .D4(soc_a7ddrphy_dfi_p1_address[7]), + .D5(soc_a7ddrphy_dfi_p2_address[7]), + .D6(soc_a7ddrphy_dfi_p2_address[7]), + .D7(soc_a7ddrphy_dfi_p3_address[7]), + .D8(soc_a7ddrphy_dfi_p3_address[7]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[7]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_9 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[8]), + .D2(soc_a7ddrphy_dfi_p0_address[8]), + .D3(soc_a7ddrphy_dfi_p1_address[8]), + .D4(soc_a7ddrphy_dfi_p1_address[8]), + .D5(soc_a7ddrphy_dfi_p2_address[8]), + .D6(soc_a7ddrphy_dfi_p2_address[8]), + .D7(soc_a7ddrphy_dfi_p3_address[8]), + .D8(soc_a7ddrphy_dfi_p3_address[8]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[8]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_10 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[9]), + .D2(soc_a7ddrphy_dfi_p0_address[9]), + .D3(soc_a7ddrphy_dfi_p1_address[9]), + .D4(soc_a7ddrphy_dfi_p1_address[9]), + .D5(soc_a7ddrphy_dfi_p2_address[9]), + .D6(soc_a7ddrphy_dfi_p2_address[9]), + .D7(soc_a7ddrphy_dfi_p3_address[9]), + .D8(soc_a7ddrphy_dfi_p3_address[9]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[9]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_11 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[10]), + .D2(soc_a7ddrphy_dfi_p0_address[10]), + .D3(soc_a7ddrphy_dfi_p1_address[10]), + .D4(soc_a7ddrphy_dfi_p1_address[10]), + .D5(soc_a7ddrphy_dfi_p2_address[10]), + .D6(soc_a7ddrphy_dfi_p2_address[10]), + .D7(soc_a7ddrphy_dfi_p3_address[10]), + .D8(soc_a7ddrphy_dfi_p3_address[10]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[10]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_12 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[11]), + .D2(soc_a7ddrphy_dfi_p0_address[11]), + .D3(soc_a7ddrphy_dfi_p1_address[11]), + .D4(soc_a7ddrphy_dfi_p1_address[11]), + .D5(soc_a7ddrphy_dfi_p2_address[11]), + .D6(soc_a7ddrphy_dfi_p2_address[11]), + .D7(soc_a7ddrphy_dfi_p3_address[11]), + .D8(soc_a7ddrphy_dfi_p3_address[11]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[11]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_13 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[12]), + .D2(soc_a7ddrphy_dfi_p0_address[12]), + .D3(soc_a7ddrphy_dfi_p1_address[12]), + .D4(soc_a7ddrphy_dfi_p1_address[12]), + .D5(soc_a7ddrphy_dfi_p2_address[12]), + .D6(soc_a7ddrphy_dfi_p2_address[12]), + .D7(soc_a7ddrphy_dfi_p3_address[12]), + .D8(soc_a7ddrphy_dfi_p3_address[12]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[12]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_14 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[13]), + .D2(soc_a7ddrphy_dfi_p0_address[13]), + .D3(soc_a7ddrphy_dfi_p1_address[13]), + .D4(soc_a7ddrphy_dfi_p1_address[13]), + .D5(soc_a7ddrphy_dfi_p2_address[13]), + .D6(soc_a7ddrphy_dfi_p2_address[13]), + .D7(soc_a7ddrphy_dfi_p3_address[13]), + .D8(soc_a7ddrphy_dfi_p3_address[13]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[13]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_15 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_bank[0]), + .D2(soc_a7ddrphy_dfi_p0_bank[0]), + .D3(soc_a7ddrphy_dfi_p1_bank[0]), + .D4(soc_a7ddrphy_dfi_p1_bank[0]), + .D5(soc_a7ddrphy_dfi_p2_bank[0]), + .D6(soc_a7ddrphy_dfi_p2_bank[0]), + .D7(soc_a7ddrphy_dfi_p3_bank[0]), + .D8(soc_a7ddrphy_dfi_p3_bank[0]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_ba[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_16 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_bank[1]), + .D2(soc_a7ddrphy_dfi_p0_bank[1]), + .D3(soc_a7ddrphy_dfi_p1_bank[1]), + .D4(soc_a7ddrphy_dfi_p1_bank[1]), + .D5(soc_a7ddrphy_dfi_p2_bank[1]), + .D6(soc_a7ddrphy_dfi_p2_bank[1]), + .D7(soc_a7ddrphy_dfi_p3_bank[1]), + .D8(soc_a7ddrphy_dfi_p3_bank[1]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_ba[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_17 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_bank[2]), + .D2(soc_a7ddrphy_dfi_p0_bank[2]), + .D3(soc_a7ddrphy_dfi_p1_bank[2]), + .D4(soc_a7ddrphy_dfi_p1_bank[2]), + .D5(soc_a7ddrphy_dfi_p2_bank[2]), + .D6(soc_a7ddrphy_dfi_p2_bank[2]), + .D7(soc_a7ddrphy_dfi_p3_bank[2]), + .D8(soc_a7ddrphy_dfi_p3_bank[2]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_ba[2]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_18 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_ras_n), + .D2(soc_a7ddrphy_dfi_p0_ras_n), + .D3(soc_a7ddrphy_dfi_p1_ras_n), + .D4(soc_a7ddrphy_dfi_p1_ras_n), + .D5(soc_a7ddrphy_dfi_p2_ras_n), + .D6(soc_a7ddrphy_dfi_p2_ras_n), + .D7(soc_a7ddrphy_dfi_p3_ras_n), + .D8(soc_a7ddrphy_dfi_p3_ras_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_ras_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_19 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_cas_n), + .D2(soc_a7ddrphy_dfi_p0_cas_n), + .D3(soc_a7ddrphy_dfi_p1_cas_n), + .D4(soc_a7ddrphy_dfi_p1_cas_n), + .D5(soc_a7ddrphy_dfi_p2_cas_n), + .D6(soc_a7ddrphy_dfi_p2_cas_n), + .D7(soc_a7ddrphy_dfi_p3_cas_n), + .D8(soc_a7ddrphy_dfi_p3_cas_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_cas_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_20 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_we_n), + .D2(soc_a7ddrphy_dfi_p0_we_n), + .D3(soc_a7ddrphy_dfi_p1_we_n), + .D4(soc_a7ddrphy_dfi_p1_we_n), + .D5(soc_a7ddrphy_dfi_p2_we_n), + .D6(soc_a7ddrphy_dfi_p2_we_n), + .D7(soc_a7ddrphy_dfi_p3_we_n), + .D8(soc_a7ddrphy_dfi_p3_we_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_we_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_21 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_cke), + .D2(soc_a7ddrphy_dfi_p0_cke), + .D3(soc_a7ddrphy_dfi_p1_cke), + .D4(soc_a7ddrphy_dfi_p1_cke), + .D5(soc_a7ddrphy_dfi_p2_cke), + .D6(soc_a7ddrphy_dfi_p2_cke), + .D7(soc_a7ddrphy_dfi_p3_cke), + .D8(soc_a7ddrphy_dfi_p3_cke), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_cke) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_22 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_odt), + .D2(soc_a7ddrphy_dfi_p0_odt), + .D3(soc_a7ddrphy_dfi_p1_odt), + .D4(soc_a7ddrphy_dfi_p1_odt), + .D5(soc_a7ddrphy_dfi_p2_odt), + .D6(soc_a7ddrphy_dfi_p2_odt), + .D7(soc_a7ddrphy_dfi_p3_odt), + .D8(soc_a7ddrphy_dfi_p3_odt), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_odt) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_23 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_reset_n), + .D2(soc_a7ddrphy_dfi_p0_reset_n), + .D3(soc_a7ddrphy_dfi_p1_reset_n), + .D4(soc_a7ddrphy_dfi_p1_reset_n), + .D5(soc_a7ddrphy_dfi_p2_reset_n), + .D6(soc_a7ddrphy_dfi_p2_reset_n), + .D7(soc_a7ddrphy_dfi_p3_reset_n), + .D8(soc_a7ddrphy_dfi_p3_reset_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_reset_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_24 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_cs_n), + .D2(soc_a7ddrphy_dfi_p0_cs_n), + .D3(soc_a7ddrphy_dfi_p1_cs_n), + .D4(soc_a7ddrphy_dfi_p1_cs_n), + .D5(soc_a7ddrphy_dfi_p2_cs_n), + .D6(soc_a7ddrphy_dfi_p2_cs_n), + .D7(soc_a7ddrphy_dfi_p3_cs_n), + .D8(soc_a7ddrphy_dfi_p3_cs_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_cs_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_25 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[0]), + .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[2]), + .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[0]), + .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[2]), + .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[0]), + .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[2]), + .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[0]), + .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[2]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_dm[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_26 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[1]), + .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[3]), + .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[1]), + .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[3]), + .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[1]), + .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[3]), + .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[1]), + .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[3]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_dm[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_27 ( + .CLK(sys4x_dqs_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dqspattern_o1[0]), + .D2(soc_a7ddrphy_dqspattern_o1[1]), + .D3(soc_a7ddrphy_dqspattern_o1[2]), + .D4(soc_a7ddrphy_dqspattern_o1[3]), + .D5(soc_a7ddrphy_dqspattern_o1[4]), + .D6(soc_a7ddrphy_dqspattern_o1[5]), + .D7(soc_a7ddrphy_dqspattern_o1[6]), + .D8(soc_a7ddrphy_dqspattern_o1[7]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dqs_oe_delayed)), + .TCE(1'd1), + .OFB(soc_a7ddrphy0), + .OQ(soc_a7ddrphy_dqs_o_no_delay0), + .TQ(soc_a7ddrphy_dqs_t0) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("FIXED"), + .IDELAY_VALUE(4'd8), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2 ( + .IDATAIN(soc_a7ddrphy_dqs_i[0]), + .DATAOUT(soc_a7ddrphy_dqs_i_delayed[0]) +); + +IOBUFDS IOBUFDS( + .I(soc_a7ddrphy_dqs_o_no_delay0), + .T(soc_a7ddrphy_dqs_t0), + .IO(ddram_dqs_p[0]), + .IOB(ddram_dqs_n[0]), + .O(soc_a7ddrphy_dqs_i[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_28 ( + .CLK(sys4x_dqs_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dqspattern_o1[0]), + .D2(soc_a7ddrphy_dqspattern_o1[1]), + .D3(soc_a7ddrphy_dqspattern_o1[2]), + .D4(soc_a7ddrphy_dqspattern_o1[3]), + .D5(soc_a7ddrphy_dqspattern_o1[4]), + .D6(soc_a7ddrphy_dqspattern_o1[5]), + .D7(soc_a7ddrphy_dqspattern_o1[6]), + .D8(soc_a7ddrphy_dqspattern_o1[7]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dqs_oe_delayed)), + .TCE(1'd1), + .OFB(soc_a7ddrphy1), + .OQ(soc_a7ddrphy_dqs_o_no_delay1), + .TQ(soc_a7ddrphy_dqs_t1) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("FIXED"), + .IDELAY_VALUE(4'd8), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_1 ( + .IDATAIN(soc_a7ddrphy_dqs_i[1]), + .DATAOUT(soc_a7ddrphy_dqs_i_delayed[1]) +); + +IOBUFDS IOBUFDS_1( + .I(soc_a7ddrphy_dqs_o_no_delay1), + .T(soc_a7ddrphy_dqs_t1), + .IO(ddram_dqs_p[1]), + .IOB(ddram_dqs_n[1]), + .O(soc_a7ddrphy_dqs_i[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_29 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[0]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[16]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[0]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[16]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[0]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[16]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[0]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[16]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay0), + .TQ(soc_a7ddrphy_dq_t0) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed0), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data0[7]), + .Q2(soc_a7ddrphy_dq_i_data0[6]), + .Q3(soc_a7ddrphy_dq_i_data0[5]), + .Q4(soc_a7ddrphy_dq_i_data0[4]), + .Q5(soc_a7ddrphy_dq_i_data0[3]), + .Q6(soc_a7ddrphy_dq_i_data0[2]), + .Q7(soc_a7ddrphy_dq_i_data0[1]), + .Q8(soc_a7ddrphy_dq_i_data0[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_2 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay0), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed0) +); + +IOBUF IOBUF( + .I(soc_a7ddrphy_dq_o_nodelay0), + .T(soc_a7ddrphy_dq_t0), + .IO(ddram_dq[0]), + .O(soc_a7ddrphy_dq_i_nodelay0) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_30 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[1]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[17]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[1]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[17]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[1]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[17]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[1]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[17]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay1), + .TQ(soc_a7ddrphy_dq_t1) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_1 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed1), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data1[7]), + .Q2(soc_a7ddrphy_dq_i_data1[6]), + .Q3(soc_a7ddrphy_dq_i_data1[5]), + .Q4(soc_a7ddrphy_dq_i_data1[4]), + .Q5(soc_a7ddrphy_dq_i_data1[3]), + .Q6(soc_a7ddrphy_dq_i_data1[2]), + .Q7(soc_a7ddrphy_dq_i_data1[1]), + .Q8(soc_a7ddrphy_dq_i_data1[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_3 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay1), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed1) +); + +IOBUF IOBUF_1( + .I(soc_a7ddrphy_dq_o_nodelay1), + .T(soc_a7ddrphy_dq_t1), + .IO(ddram_dq[1]), + .O(soc_a7ddrphy_dq_i_nodelay1) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_31 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[2]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[18]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[2]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[18]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[2]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[18]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[2]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[18]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay2), + .TQ(soc_a7ddrphy_dq_t2) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_2 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed2), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data2[7]), + .Q2(soc_a7ddrphy_dq_i_data2[6]), + .Q3(soc_a7ddrphy_dq_i_data2[5]), + .Q4(soc_a7ddrphy_dq_i_data2[4]), + .Q5(soc_a7ddrphy_dq_i_data2[3]), + .Q6(soc_a7ddrphy_dq_i_data2[2]), + .Q7(soc_a7ddrphy_dq_i_data2[1]), + .Q8(soc_a7ddrphy_dq_i_data2[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_4 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay2), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed2) +); + +IOBUF IOBUF_2( + .I(soc_a7ddrphy_dq_o_nodelay2), + .T(soc_a7ddrphy_dq_t2), + .IO(ddram_dq[2]), + .O(soc_a7ddrphy_dq_i_nodelay2) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_32 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[3]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[19]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[3]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[19]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[3]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[19]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[3]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[19]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay3), + .TQ(soc_a7ddrphy_dq_t3) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_3 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed3), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data3[7]), + .Q2(soc_a7ddrphy_dq_i_data3[6]), + .Q3(soc_a7ddrphy_dq_i_data3[5]), + .Q4(soc_a7ddrphy_dq_i_data3[4]), + .Q5(soc_a7ddrphy_dq_i_data3[3]), + .Q6(soc_a7ddrphy_dq_i_data3[2]), + .Q7(soc_a7ddrphy_dq_i_data3[1]), + .Q8(soc_a7ddrphy_dq_i_data3[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_5 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay3), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed3) +); + +IOBUF IOBUF_3( + .I(soc_a7ddrphy_dq_o_nodelay3), + .T(soc_a7ddrphy_dq_t3), + .IO(ddram_dq[3]), + .O(soc_a7ddrphy_dq_i_nodelay3) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_33 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[4]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[20]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[4]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[20]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[4]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[20]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[4]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[20]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay4), + .TQ(soc_a7ddrphy_dq_t4) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_4 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed4), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data4[7]), + .Q2(soc_a7ddrphy_dq_i_data4[6]), + .Q3(soc_a7ddrphy_dq_i_data4[5]), + .Q4(soc_a7ddrphy_dq_i_data4[4]), + .Q5(soc_a7ddrphy_dq_i_data4[3]), + .Q6(soc_a7ddrphy_dq_i_data4[2]), + .Q7(soc_a7ddrphy_dq_i_data4[1]), + .Q8(soc_a7ddrphy_dq_i_data4[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_6 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay4), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed4) +); + +IOBUF IOBUF_4( + .I(soc_a7ddrphy_dq_o_nodelay4), + .T(soc_a7ddrphy_dq_t4), + .IO(ddram_dq[4]), + .O(soc_a7ddrphy_dq_i_nodelay4) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_34 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[5]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[21]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[5]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[21]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[5]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[21]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[5]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[21]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay5), + .TQ(soc_a7ddrphy_dq_t5) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_5 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed5), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data5[7]), + .Q2(soc_a7ddrphy_dq_i_data5[6]), + .Q3(soc_a7ddrphy_dq_i_data5[5]), + .Q4(soc_a7ddrphy_dq_i_data5[4]), + .Q5(soc_a7ddrphy_dq_i_data5[3]), + .Q6(soc_a7ddrphy_dq_i_data5[2]), + .Q7(soc_a7ddrphy_dq_i_data5[1]), + .Q8(soc_a7ddrphy_dq_i_data5[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_7 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay5), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed5) +); + +IOBUF IOBUF_5( + .I(soc_a7ddrphy_dq_o_nodelay5), + .T(soc_a7ddrphy_dq_t5), + .IO(ddram_dq[5]), + .O(soc_a7ddrphy_dq_i_nodelay5) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_35 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[6]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[22]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[6]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[22]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[6]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[22]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[6]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[22]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay6), + .TQ(soc_a7ddrphy_dq_t6) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_6 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed6), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data6[7]), + .Q2(soc_a7ddrphy_dq_i_data6[6]), + .Q3(soc_a7ddrphy_dq_i_data6[5]), + .Q4(soc_a7ddrphy_dq_i_data6[4]), + .Q5(soc_a7ddrphy_dq_i_data6[3]), + .Q6(soc_a7ddrphy_dq_i_data6[2]), + .Q7(soc_a7ddrphy_dq_i_data6[1]), + .Q8(soc_a7ddrphy_dq_i_data6[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_8 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay6), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed6) +); + +IOBUF IOBUF_6( + .I(soc_a7ddrphy_dq_o_nodelay6), + .T(soc_a7ddrphy_dq_t6), + .IO(ddram_dq[6]), + .O(soc_a7ddrphy_dq_i_nodelay6) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_36 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[7]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[23]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[7]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[23]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[7]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[23]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[7]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[23]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay7), + .TQ(soc_a7ddrphy_dq_t7) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_7 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed7), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data7[7]), + .Q2(soc_a7ddrphy_dq_i_data7[6]), + .Q3(soc_a7ddrphy_dq_i_data7[5]), + .Q4(soc_a7ddrphy_dq_i_data7[4]), + .Q5(soc_a7ddrphy_dq_i_data7[3]), + .Q6(soc_a7ddrphy_dq_i_data7[2]), + .Q7(soc_a7ddrphy_dq_i_data7[1]), + .Q8(soc_a7ddrphy_dq_i_data7[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_9 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay7), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed7) +); + +IOBUF IOBUF_7( + .I(soc_a7ddrphy_dq_o_nodelay7), + .T(soc_a7ddrphy_dq_t7), + .IO(ddram_dq[7]), + .O(soc_a7ddrphy_dq_i_nodelay7) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_37 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[8]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[24]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[8]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[24]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[8]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[24]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[8]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[24]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay8), + .TQ(soc_a7ddrphy_dq_t8) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_8 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed8), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data8[7]), + .Q2(soc_a7ddrphy_dq_i_data8[6]), + .Q3(soc_a7ddrphy_dq_i_data8[5]), + .Q4(soc_a7ddrphy_dq_i_data8[4]), + .Q5(soc_a7ddrphy_dq_i_data8[3]), + .Q6(soc_a7ddrphy_dq_i_data8[2]), + .Q7(soc_a7ddrphy_dq_i_data8[1]), + .Q8(soc_a7ddrphy_dq_i_data8[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_10 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay8), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed8) +); + +IOBUF IOBUF_8( + .I(soc_a7ddrphy_dq_o_nodelay8), + .T(soc_a7ddrphy_dq_t8), + .IO(ddram_dq[8]), + .O(soc_a7ddrphy_dq_i_nodelay8) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_38 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[9]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[25]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[9]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[25]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[9]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[25]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[9]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[25]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay9), + .TQ(soc_a7ddrphy_dq_t9) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_9 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed9), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data9[7]), + .Q2(soc_a7ddrphy_dq_i_data9[6]), + .Q3(soc_a7ddrphy_dq_i_data9[5]), + .Q4(soc_a7ddrphy_dq_i_data9[4]), + .Q5(soc_a7ddrphy_dq_i_data9[3]), + .Q6(soc_a7ddrphy_dq_i_data9[2]), + .Q7(soc_a7ddrphy_dq_i_data9[1]), + .Q8(soc_a7ddrphy_dq_i_data9[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_11 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay9), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed9) +); + +IOBUF IOBUF_9( + .I(soc_a7ddrphy_dq_o_nodelay9), + .T(soc_a7ddrphy_dq_t9), + .IO(ddram_dq[9]), + .O(soc_a7ddrphy_dq_i_nodelay9) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_39 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[10]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[26]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[10]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[26]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[10]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[26]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[10]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[26]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay10), + .TQ(soc_a7ddrphy_dq_t10) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_10 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed10), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data10[7]), + .Q2(soc_a7ddrphy_dq_i_data10[6]), + .Q3(soc_a7ddrphy_dq_i_data10[5]), + .Q4(soc_a7ddrphy_dq_i_data10[4]), + .Q5(soc_a7ddrphy_dq_i_data10[3]), + .Q6(soc_a7ddrphy_dq_i_data10[2]), + .Q7(soc_a7ddrphy_dq_i_data10[1]), + .Q8(soc_a7ddrphy_dq_i_data10[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_12 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay10), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed10) +); + +IOBUF IOBUF_10( + .I(soc_a7ddrphy_dq_o_nodelay10), + .T(soc_a7ddrphy_dq_t10), + .IO(ddram_dq[10]), + .O(soc_a7ddrphy_dq_i_nodelay10) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_40 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[11]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[27]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[11]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[27]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[11]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[27]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[11]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[27]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay11), + .TQ(soc_a7ddrphy_dq_t11) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_11 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed11), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data11[7]), + .Q2(soc_a7ddrphy_dq_i_data11[6]), + .Q3(soc_a7ddrphy_dq_i_data11[5]), + .Q4(soc_a7ddrphy_dq_i_data11[4]), + .Q5(soc_a7ddrphy_dq_i_data11[3]), + .Q6(soc_a7ddrphy_dq_i_data11[2]), + .Q7(soc_a7ddrphy_dq_i_data11[1]), + .Q8(soc_a7ddrphy_dq_i_data11[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_13 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay11), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed11) +); + +IOBUF IOBUF_11( + .I(soc_a7ddrphy_dq_o_nodelay11), + .T(soc_a7ddrphy_dq_t11), + .IO(ddram_dq[11]), + .O(soc_a7ddrphy_dq_i_nodelay11) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_41 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[12]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[28]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[12]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[28]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[12]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[28]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[12]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[28]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay12), + .TQ(soc_a7ddrphy_dq_t12) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_12 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed12), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data12[7]), + .Q2(soc_a7ddrphy_dq_i_data12[6]), + .Q3(soc_a7ddrphy_dq_i_data12[5]), + .Q4(soc_a7ddrphy_dq_i_data12[4]), + .Q5(soc_a7ddrphy_dq_i_data12[3]), + .Q6(soc_a7ddrphy_dq_i_data12[2]), + .Q7(soc_a7ddrphy_dq_i_data12[1]), + .Q8(soc_a7ddrphy_dq_i_data12[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_14 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay12), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed12) +); + +IOBUF IOBUF_12( + .I(soc_a7ddrphy_dq_o_nodelay12), + .T(soc_a7ddrphy_dq_t12), + .IO(ddram_dq[12]), + .O(soc_a7ddrphy_dq_i_nodelay12) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_42 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[13]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[29]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[13]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[29]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[13]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[29]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[13]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[29]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay13), + .TQ(soc_a7ddrphy_dq_t13) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_13 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed13), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data13[7]), + .Q2(soc_a7ddrphy_dq_i_data13[6]), + .Q3(soc_a7ddrphy_dq_i_data13[5]), + .Q4(soc_a7ddrphy_dq_i_data13[4]), + .Q5(soc_a7ddrphy_dq_i_data13[3]), + .Q6(soc_a7ddrphy_dq_i_data13[2]), + .Q7(soc_a7ddrphy_dq_i_data13[1]), + .Q8(soc_a7ddrphy_dq_i_data13[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_15 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay13), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed13) +); + +IOBUF IOBUF_13( + .I(soc_a7ddrphy_dq_o_nodelay13), + .T(soc_a7ddrphy_dq_t13), + .IO(ddram_dq[13]), + .O(soc_a7ddrphy_dq_i_nodelay13) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_43 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[14]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[30]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[14]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[30]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[14]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[30]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[14]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[30]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay14), + .TQ(soc_a7ddrphy_dq_t14) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_14 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed14), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data14[7]), + .Q2(soc_a7ddrphy_dq_i_data14[6]), + .Q3(soc_a7ddrphy_dq_i_data14[5]), + .Q4(soc_a7ddrphy_dq_i_data14[4]), + .Q5(soc_a7ddrphy_dq_i_data14[3]), + .Q6(soc_a7ddrphy_dq_i_data14[2]), + .Q7(soc_a7ddrphy_dq_i_data14[1]), + .Q8(soc_a7ddrphy_dq_i_data14[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_16 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay14), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed14) +); + +IOBUF IOBUF_14( + .I(soc_a7ddrphy_dq_o_nodelay14), + .T(soc_a7ddrphy_dq_t14), + .IO(ddram_dq[14]), + .O(soc_a7ddrphy_dq_i_nodelay14) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_44 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[15]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[31]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[15]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[31]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[15]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[31]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[15]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[31]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay15), + .TQ(soc_a7ddrphy_dq_t15) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_15 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed15), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data15[7]), + .Q2(soc_a7ddrphy_dq_i_data15[6]), + .Q3(soc_a7ddrphy_dq_i_data15[5]), + .Q4(soc_a7ddrphy_dq_i_data15[4]), + .Q5(soc_a7ddrphy_dq_i_data15[3]), + .Q6(soc_a7ddrphy_dq_i_data15[2]), + .Q7(soc_a7ddrphy_dq_i_data15[1]), + .Q8(soc_a7ddrphy_dq_i_data15[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_17 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay15), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed15) +); + +IOBUF IOBUF_15( + .I(soc_a7ddrphy_dq_o_nodelay15), + .T(soc_a7ddrphy_dq_t15), + .IO(ddram_dq[15]), + .O(soc_a7ddrphy_dq_i_nodelay15) +); + +reg [23:0] storage_2[0:15]; +reg [23:0] memdat_5; +always @(posedge sys_clk) begin + if (soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we) + storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; + memdat_5 <= storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat_5; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_3[0:15]; +reg [23:0] memdat_6; +always @(posedge sys_clk) begin + if (soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we) + storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; + memdat_6 <= storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_6; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_4[0:15]; +reg [23:0] memdat_7; +always @(posedge sys_clk) begin + if (soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we) + storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; + memdat_7 <= storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_7; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_5[0:15]; +reg [23:0] memdat_8; +always @(posedge sys_clk) begin + if (soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we) + storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; + memdat_8 <= storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_8; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_6[0:15]; +reg [23:0] memdat_9; +always @(posedge sys_clk) begin + if (soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we) + storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; + memdat_9 <= storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_9; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_7[0:15]; +reg [23:0] memdat_10; +always @(posedge sys_clk) begin + if (soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we) + storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; + memdat_10 <= storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_10; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_8[0:15]; +reg [23:0] memdat_11; +always @(posedge sys_clk) begin + if (soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we) + storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; + memdat_11 <= storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_11; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_9[0:15]; +reg [23:0] memdat_12; +always @(posedge sys_clk) begin + if (soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we) + storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; + memdat_12 <= storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_12; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr]; + +VexRiscv VexRiscv( + .clk(sys_clk), + .dBusWishbone_ACK(soc_litedramcore_cpu_dbus_ack), + .dBusWishbone_DAT_MISO(soc_litedramcore_cpu_dbus_dat_r), + .dBusWishbone_ERR(soc_litedramcore_cpu_dbus_err), + .externalInterruptArray(soc_litedramcore_cpu_interrupt), + .externalResetVector(soc_litedramcore_vexriscv), + .iBusWishbone_ACK(soc_litedramcore_cpu_ibus_ack), + .iBusWishbone_DAT_MISO(soc_litedramcore_cpu_ibus_dat_r), + .iBusWishbone_ERR(soc_litedramcore_cpu_ibus_err), + .reset((sys_rst | soc_litedramcore_cpu_reset)), + .softwareInterrupt(1'd0), + .timerInterrupt(1'd0), + .dBusWishbone_ADR(soc_litedramcore_cpu_dbus_adr), + .dBusWishbone_BTE(soc_litedramcore_cpu_dbus_bte), + .dBusWishbone_CTI(soc_litedramcore_cpu_dbus_cti), + .dBusWishbone_CYC(soc_litedramcore_cpu_dbus_cyc), + .dBusWishbone_DAT_MOSI(soc_litedramcore_cpu_dbus_dat_w), + .dBusWishbone_SEL(soc_litedramcore_cpu_dbus_sel), + .dBusWishbone_STB(soc_litedramcore_cpu_dbus_stb), + .dBusWishbone_WE(soc_litedramcore_cpu_dbus_we), + .iBusWishbone_ADR(soc_litedramcore_cpu_ibus_adr), + .iBusWishbone_BTE(soc_litedramcore_cpu_ibus_bte), + .iBusWishbone_CTI(soc_litedramcore_cpu_ibus_cti), + .iBusWishbone_CYC(soc_litedramcore_cpu_ibus_cyc), + .iBusWishbone_DAT_MOSI(soc_litedramcore_cpu_ibus_dat_w), + .iBusWishbone_SEL(soc_litedramcore_cpu_ibus_sel), + .iBusWishbone_STB(soc_litedramcore_cpu_ibus_stb), + .iBusWishbone_WE(soc_litedramcore_cpu_ibus_we) +); + +PLLE2_ADV #( + .CLKFBOUT_MULT(5'd16), + .CLKIN1_PERIOD(10.0), + .CLKOUT0_DIVIDE(5'd16), + .CLKOUT0_PHASE(1'd0), + .CLKOUT1_DIVIDE(3'd4), + .CLKOUT1_PHASE(1'd0), + .CLKOUT2_DIVIDE(3'd4), + .CLKOUT2_PHASE(7'd90), + .DIVCLK_DIVIDE(1'd1), + .REF_JITTER1(0.01), + .STARTUP_WAIT("FALSE") +) PLLE2_ADV ( + .CLKFBIN(vns_pll_fb0), + .CLKIN1(soc_s7pll0_clkin), + .RST(soc_sys_pll_reset), + .CLKFBOUT(vns_pll_fb0), + .CLKOUT0(soc_s7pll0_clkout0), + .CLKOUT1(soc_s7pll0_clkout1), + .CLKOUT2(soc_s7pll0_clkout2), + .LOCKED(soc_sys_pll_locked) +); + +PLLE2_ADV #( + .CLKFBOUT_MULT(5'd16), + .CLKIN1_PERIOD(10.0), + .CLKOUT0_DIVIDE(4'd8), + .CLKOUT0_PHASE(1'd0), + .DIVCLK_DIVIDE(1'd1), + .REF_JITTER1(0.01), + .STARTUP_WAIT("FALSE") +) PLLE2_ADV_1 ( + .CLKFBIN(vns_pll_fb1), + .CLKIN1(soc_s7pll1_clkin), + .RST(soc_iodelay_pll_reset), + .CLKFBOUT(vns_pll_fb1), + .CLKOUT0(soc_s7pll1_clkout), + .LOCKED(soc_iodelay_pll_locked) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE ( + .C(sys_clk), + .CE(1'd1), + .D(1'd0), + .PRE(vns_xilinxasyncresetsynchronizerimpl0), + .Q(vns_xilinxasyncresetsynchronizerimpl0_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_1 ( + .C(sys_clk), + .CE(1'd1), + .D(vns_xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE(vns_xilinxasyncresetsynchronizerimpl0), + .Q(sys_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_2 ( + .C(sys4x_clk), + .CE(1'd1), + .D(1'd0), + .PRE(vns_xilinxasyncresetsynchronizerimpl1), + .Q(vns_xilinxasyncresetsynchronizerimpl1_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_3 ( + .C(sys4x_clk), + .CE(1'd1), + .D(vns_xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE(vns_xilinxasyncresetsynchronizerimpl1), + .Q(vns_xilinxasyncresetsynchronizerimpl1_expr) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_4 ( + .C(sys4x_dqs_clk), + .CE(1'd1), + .D(1'd0), + .PRE(vns_xilinxasyncresetsynchronizerimpl2), + .Q(vns_xilinxasyncresetsynchronizerimpl2_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_5 ( + .C(sys4x_dqs_clk), + .CE(1'd1), + .D(vns_xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE(vns_xilinxasyncresetsynchronizerimpl2), + .Q(vns_xilinxasyncresetsynchronizerimpl2_expr) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_6 ( + .C(iodelay_clk), + .CE(1'd1), + .D(1'd0), + .PRE(vns_xilinxasyncresetsynchronizerimpl3), + .Q(vns_xilinxasyncresetsynchronizerimpl3_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_7 ( + .C(iodelay_clk), + .CE(1'd1), + .D(vns_xilinxasyncresetsynchronizerimpl3_rst_meta), + .PRE(vns_xilinxasyncresetsynchronizerimpl3), + .Q(iodelay_rst) +); + +endmodule diff --git a/litedram/generated/nexys-video/init-cpu.txt b/litedram/generated/nexys-video/init-cpu.txt new file mode 100644 index 0000000..b0b6e79 --- /dev/null +++ b/litedram/generated/nexys-video/init-cpu.txt @@ -0,0 +1 @@ +vexriscv \ No newline at end of file diff --git a/litedram/generated/nexys-video/litedram-wrapper.vhdl b/litedram/generated/nexys-video/litedram-wrapper.vhdl new file mode 100644 index 0000000..0664866 --- /dev/null +++ b/litedram/generated/nexys-video/litedram-wrapper.vhdl @@ -0,0 +1,214 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; + +library work; +use work.wishbone_types.all; +use work.sim_console.all; + +entity litedram_wrapper is + generic ( + DRAM_ABITS : positive; + DRAM_ALINES : positive + ); + port( + -- LiteDRAM generates the system clock and reset + -- from the input clkin + clk_in : in std_ulogic; + rst : in std_ulogic; + system_clk : out std_ulogic; + system_reset : out std_ulogic; + core_alt_reset : out std_ulogic; + pll_locked : out std_ulogic; + + -- Wishbone ports: + wb_in : in wishbone_master_out; + wb_out : out wishbone_slave_out; + wb_is_csr : in std_ulogic; + wb_is_init : in std_ulogic; + + -- Init core serial debug + serial_tx : out std_ulogic; + serial_rx : in std_ulogic; + + -- Misc + init_done : out std_ulogic; + init_error : out std_ulogic; + + -- DRAM wires + ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic + ); +end entity litedram_wrapper; + +architecture behaviour of litedram_wrapper is + + component litedram_core port ( + clk : in std_ulogic; + rst : in std_ulogic; + serial_tx : out std_ulogic; + serial_rx : in std_ulogic; + pll_locked : out std_ulogic; + ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic; + init_done : out std_ulogic; + init_error : out std_ulogic; + user_clk : out std_ulogic; + user_rst : out std_ulogic; + user_port_native_0_cmd_valid : in std_ulogic; + user_port_native_0_cmd_ready : out std_ulogic; + user_port_native_0_cmd_we : in std_ulogic; + user_port_native_0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0); + user_port_native_0_wdata_valid : in std_ulogic; + user_port_native_0_wdata_ready : out std_ulogic; + user_port_native_0_wdata_we : in std_ulogic_vector(15 downto 0); + user_port_native_0_wdata_data : in std_ulogic_vector(127 downto 0); + user_port_native_0_rdata_valid : out std_ulogic; + user_port_native_0_rdata_ready : in std_ulogic; + user_port_native_0_rdata_data : out std_ulogic_vector(127 downto 0) + ); + end component; + + signal user_port0_cmd_valid : std_ulogic; + signal user_port0_cmd_ready : std_ulogic; + signal user_port0_cmd_we : std_ulogic; + signal user_port0_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0); + signal user_port0_wdata_valid : std_ulogic; + signal user_port0_wdata_ready : std_ulogic; + signal user_port0_wdata_we : std_ulogic_vector(15 downto 0); + signal user_port0_wdata_data : std_ulogic_vector(127 downto 0); + signal user_port0_rdata_valid : std_ulogic; + signal user_port0_rdata_ready : std_ulogic; + signal user_port0_rdata_data : std_ulogic_vector(127 downto 0); + + signal ad3 : std_ulogic; + + signal dram_user_reset : std_ulogic; + + type state_t is (CMD, MWRITE, MREAD); + signal state : state_t; + +begin + + -- Address bit 3 selects the top or bottom half of the data + -- bus (64-bit wishbone vs. 128-bit DRAM interface) + -- + ad3 <= wb_in.adr(3); + + -- DRAM interface signals + user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init) + when state = CMD else '0'; + user_port0_cmd_we <= wb_in.we when state = CMD else '0'; + user_port0_wdata_valid <= '1' when state = MWRITE else '0'; + user_port0_rdata_ready <= '1' when state = MREAD else '0'; + user_port0_cmd_addr <= wb_in.adr(DRAM_ABITS+3 downto 4); + user_port0_wdata_data <= wb_in.dat & wb_in.dat; + user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else + "00000000" & wb_in.sel; + + -- Wishbone out signals. CSR and init memory do nothing, just ack + wb_out.ack <= '1' when (wb_is_csr = '1' or wb_is_init = '1') else + user_port0_wdata_ready when state = MWRITE else + user_port0_rdata_valid when state = MREAD else '0'; + wb_out.dat <= (others => '0') when (wb_is_csr = '1' or wb_is_init = '1') else + user_port0_rdata_data(127 downto 64) when ad3 = '1' else + user_port0_rdata_data(63 downto 0); + wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack; + + -- Reset, lift it when init done, no alt core reset + system_reset <= dram_user_reset or not init_done; + core_alt_reset <= '0'; + + -- State machine + sm: process(system_clk) + begin + + if rising_edge(system_clk) then + if dram_user_reset = '1' then + state <= CMD; + else + case state is + when CMD => + if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then + state <= MWRITE when wb_in.we = '1' else MREAD; + end if; + when MWRITE => + if user_port0_wdata_ready = '1' then + state <= CMD; + end if; + when MREAD => + if user_port0_rdata_valid = '1' then + state <= CMD; + end if; + end case; + end if; + end if; + end process; + + litedram: litedram_core + port map( + clk => clk_in, + rst => rst, + serial_tx => serial_tx, + serial_rx => serial_rx, + pll_locked => pll_locked, + ddram_a => ddram_a, + ddram_ba => ddram_ba, + ddram_ras_n => ddram_ras_n, + ddram_cas_n => ddram_cas_n, + ddram_we_n => ddram_we_n, + ddram_cs_n => ddram_cs_n, + ddram_dm => ddram_dm, + ddram_dq => ddram_dq, + ddram_dqs_p => ddram_dqs_p, + ddram_dqs_n => ddram_dqs_n, + ddram_clk_p => ddram_clk_p, + ddram_clk_n => ddram_clk_n, + ddram_cke => ddram_cke, + ddram_odt => ddram_odt, + ddram_reset_n => ddram_reset_n, + init_done => init_done, + init_error => init_error, + user_clk => system_clk, + user_rst => dram_user_reset, + user_port_native_0_cmd_valid => user_port0_cmd_valid, + user_port_native_0_cmd_ready => user_port0_cmd_ready, + user_port_native_0_cmd_we => user_port0_cmd_we, + user_port_native_0_cmd_addr => user_port0_cmd_addr, + user_port_native_0_wdata_valid => user_port0_wdata_valid, + user_port_native_0_wdata_ready => user_port0_wdata_ready, + user_port_native_0_wdata_we => user_port0_wdata_we, + user_port_native_0_wdata_data => user_port0_wdata_data, + user_port_native_0_rdata_valid => user_port0_rdata_valid, + user_port_native_0_rdata_ready => user_port0_rdata_ready, + user_port_native_0_rdata_data => user_port0_rdata_data + ); + +end architecture behaviour; diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init new file mode 100644 index 0000000..b1daa3c --- /dev/null +++ b/litedram/generated/nexys-video/litedram_core.init @@ -0,0 +1,5817 @@ +b00006f +13 +13 +13 +13 +13 +13 +13 +fe112e23 +fe512c23 +fe612a23 +fe712823 +fea12623 +feb12423 +fec12223 +fed12023 +fce12e23 +fcf12c23 +fd012a23 +fd112823 +fdc12623 +fdd12423 +fde12223 +fdf12023 +fc010113 +94000ef +3c12083 +3812283 +3412303 +3012383 +2c12503 +2812583 +2412603 +2012683 +1c12703 +1812783 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+//-------------------------------------------------------------------------------- +// Auto-generated by Migen (dc9cfe6) & LiteX (79ee135f) on 2020-05-08 01:29:22 +//-------------------------------------------------------------------------------- +module litedram_core( + output reg serial_tx, + input wire serial_rx, + input wire clk, + input wire rst, + output wire pll_locked, + output wire [14:0] ddram_a, + output wire [2:0] ddram_ba, + output wire ddram_ras_n, + output wire ddram_cas_n, + output wire ddram_we_n, + output wire ddram_cs_n, + output wire [1:0] ddram_dm, + inout wire [15:0] ddram_dq, + inout wire [1:0] ddram_dqs_p, + inout wire [1:0] ddram_dqs_n, + output wire ddram_clk_p, + output wire ddram_clk_n, + output wire ddram_cke, + output wire ddram_odt, + output wire ddram_reset_n, + output wire init_done, + output wire init_error, + output wire user_clk, + output wire user_rst, + input wire user_port_native_0_cmd_valid, + output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_we, + input wire [24:0] user_port_native_0_cmd_addr, + input wire user_port_native_0_wdata_valid, + output wire user_port_native_0_wdata_ready, + input wire [15:0] user_port_native_0_wdata_we, + input wire [127:0] user_port_native_0_wdata_data, + output wire user_port_native_0_rdata_valid, + input wire user_port_native_0_rdata_ready, + output wire [127:0] user_port_native_0_rdata_data +); + +reg soc_litedramcore_soccontroller_reset_storage = 1'd0; +reg soc_litedramcore_soccontroller_reset_re = 1'd0; +reg [31:0] soc_litedramcore_soccontroller_scratch_storage = 32'd305419896; +reg soc_litedramcore_soccontroller_scratch_re = 1'd0; +wire [31:0] soc_litedramcore_soccontroller_bus_errors_status; +wire soc_litedramcore_soccontroller_bus_errors_we; +wire soc_litedramcore_soccontroller_reset; +wire soc_litedramcore_soccontroller_bus_error; +reg [31:0] soc_litedramcore_soccontroller_bus_errors = 32'd0; +wire soc_litedramcore_cpu_reset; +reg [31:0] soc_litedramcore_cpu_interrupt = 32'd0; +wire [29:0] soc_litedramcore_cpu_ibus_adr; +wire [31:0] soc_litedramcore_cpu_ibus_dat_w; +wire [31:0] soc_litedramcore_cpu_ibus_dat_r; +wire [3:0] soc_litedramcore_cpu_ibus_sel; +wire soc_litedramcore_cpu_ibus_cyc; +wire soc_litedramcore_cpu_ibus_stb; +wire soc_litedramcore_cpu_ibus_ack; +wire soc_litedramcore_cpu_ibus_we; +wire [2:0] soc_litedramcore_cpu_ibus_cti; +wire [1:0] soc_litedramcore_cpu_ibus_bte; +wire soc_litedramcore_cpu_ibus_err; +wire [29:0] soc_litedramcore_cpu_dbus_adr; +wire [31:0] soc_litedramcore_cpu_dbus_dat_w; +wire [31:0] soc_litedramcore_cpu_dbus_dat_r; +wire [3:0] soc_litedramcore_cpu_dbus_sel; +wire soc_litedramcore_cpu_dbus_cyc; +wire soc_litedramcore_cpu_dbus_stb; +wire soc_litedramcore_cpu_dbus_ack; +wire soc_litedramcore_cpu_dbus_we; +wire [2:0] soc_litedramcore_cpu_dbus_cti; +wire [1:0] soc_litedramcore_cpu_dbus_bte; +wire soc_litedramcore_cpu_dbus_err; +reg [31:0] soc_litedramcore_vexriscv = 32'd0; +wire [29:0] soc_litedramcore_litedramcore_ram_bus_adr; +wire [31:0] soc_litedramcore_litedramcore_ram_bus_dat_w; +wire [31:0] soc_litedramcore_litedramcore_ram_bus_dat_r; +wire [3:0] soc_litedramcore_litedramcore_ram_bus_sel; +wire soc_litedramcore_litedramcore_ram_bus_cyc; +wire soc_litedramcore_litedramcore_ram_bus_stb; +reg soc_litedramcore_litedramcore_ram_bus_ack = 1'd0; +wire soc_litedramcore_litedramcore_ram_bus_we; +wire [2:0] soc_litedramcore_litedramcore_ram_bus_cti; +wire [1:0] soc_litedramcore_litedramcore_ram_bus_bte; +reg soc_litedramcore_litedramcore_ram_bus_err = 1'd0; +wire [12:0] soc_litedramcore_litedramcore_adr; +wire [31:0] soc_litedramcore_litedramcore_dat_r; +wire [29:0] soc_litedramcore_ram_bus_ram_bus_adr; +wire [31:0] soc_litedramcore_ram_bus_ram_bus_dat_w; +wire [31:0] soc_litedramcore_ram_bus_ram_bus_dat_r; +wire [3:0] soc_litedramcore_ram_bus_ram_bus_sel; +wire soc_litedramcore_ram_bus_ram_bus_cyc; +wire soc_litedramcore_ram_bus_ram_bus_stb; +reg soc_litedramcore_ram_bus_ram_bus_ack = 1'd0; +wire soc_litedramcore_ram_bus_ram_bus_we; +wire [2:0] soc_litedramcore_ram_bus_ram_bus_cti; +wire [1:0] soc_litedramcore_ram_bus_ram_bus_bte; +reg soc_litedramcore_ram_bus_ram_bus_err = 1'd0; +wire [9:0] soc_litedramcore_ram_adr; +wire [31:0] soc_litedramcore_ram_dat_r; +reg [3:0] soc_litedramcore_ram_we = 4'd0; +wire [31:0] soc_litedramcore_ram_dat_w; +reg [31:0] soc_litedramcore_storage = 32'd4947802; +reg soc_litedramcore_re = 1'd0; +wire soc_litedramcore_sink_valid; +reg soc_litedramcore_sink_ready = 1'd0; +wire soc_litedramcore_sink_first; +wire soc_litedramcore_sink_last; +wire [7:0] soc_litedramcore_sink_payload_data; +reg soc_litedramcore_uart_clk_txen = 1'd0; +reg [31:0] soc_litedramcore_phase_accumulator_tx = 32'd0; +reg [7:0] soc_litedramcore_tx_reg = 8'd0; +reg [3:0] soc_litedramcore_tx_bitcount = 4'd0; +reg soc_litedramcore_tx_busy = 1'd0; +reg soc_litedramcore_source_valid = 1'd0; +wire soc_litedramcore_source_ready; +reg soc_litedramcore_source_first = 1'd0; +reg soc_litedramcore_source_last = 1'd0; +reg [7:0] soc_litedramcore_source_payload_data = 8'd0; +reg soc_litedramcore_uart_clk_rxen = 1'd0; +reg [31:0] soc_litedramcore_phase_accumulator_rx = 32'd0; +wire soc_litedramcore_rx; +reg soc_litedramcore_rx_r = 1'd0; +reg [7:0] soc_litedramcore_rx_reg = 8'd0; +reg [3:0] soc_litedramcore_rx_bitcount = 4'd0; +reg soc_litedramcore_rx_busy = 1'd0; +wire soc_litedramcore_uart_rxtx_re; +wire [7:0] soc_litedramcore_uart_rxtx_r; +wire soc_litedramcore_uart_rxtx_we; +wire [7:0] soc_litedramcore_uart_rxtx_w; +wire soc_litedramcore_uart_txfull_status; +wire soc_litedramcore_uart_txfull_we; +wire soc_litedramcore_uart_rxempty_status; +wire soc_litedramcore_uart_rxempty_we; +wire soc_litedramcore_uart_irq; +wire soc_litedramcore_uart_tx_status; +reg soc_litedramcore_uart_tx_pending = 1'd0; +wire soc_litedramcore_uart_tx_trigger; +reg soc_litedramcore_uart_tx_clear = 1'd0; +reg soc_litedramcore_uart_tx_old_trigger = 1'd0; +wire soc_litedramcore_uart_rx_status; +reg soc_litedramcore_uart_rx_pending = 1'd0; +wire soc_litedramcore_uart_rx_trigger; +reg soc_litedramcore_uart_rx_clear = 1'd0; +reg soc_litedramcore_uart_rx_old_trigger = 1'd0; +wire soc_litedramcore_uart_eventmanager_status_re; +wire [1:0] soc_litedramcore_uart_eventmanager_status_r; +wire soc_litedramcore_uart_eventmanager_status_we; +reg [1:0] soc_litedramcore_uart_eventmanager_status_w = 2'd0; +wire soc_litedramcore_uart_eventmanager_pending_re; +wire [1:0] soc_litedramcore_uart_eventmanager_pending_r; +wire soc_litedramcore_uart_eventmanager_pending_we; +reg [1:0] soc_litedramcore_uart_eventmanager_pending_w = 2'd0; +reg [1:0] soc_litedramcore_uart_eventmanager_storage = 2'd0; +reg soc_litedramcore_uart_eventmanager_re = 1'd0; +wire soc_litedramcore_uart_uart_sink_valid; +wire soc_litedramcore_uart_uart_sink_ready; +wire soc_litedramcore_uart_uart_sink_first; +wire soc_litedramcore_uart_uart_sink_last; +wire [7:0] soc_litedramcore_uart_uart_sink_payload_data; +wire soc_litedramcore_uart_uart_source_valid; +wire soc_litedramcore_uart_uart_source_ready; +wire soc_litedramcore_uart_uart_source_first; +wire soc_litedramcore_uart_uart_source_last; +wire [7:0] soc_litedramcore_uart_uart_source_payload_data; +wire soc_litedramcore_uart_tx_fifo_sink_valid; +wire soc_litedramcore_uart_tx_fifo_sink_ready; +reg soc_litedramcore_uart_tx_fifo_sink_first = 1'd0; +reg soc_litedramcore_uart_tx_fifo_sink_last = 1'd0; +wire [7:0] soc_litedramcore_uart_tx_fifo_sink_payload_data; +wire soc_litedramcore_uart_tx_fifo_source_valid; +wire soc_litedramcore_uart_tx_fifo_source_ready; +wire soc_litedramcore_uart_tx_fifo_source_first; +wire soc_litedramcore_uart_tx_fifo_source_last; +wire [7:0] soc_litedramcore_uart_tx_fifo_source_payload_data; +wire soc_litedramcore_uart_tx_fifo_re; +reg soc_litedramcore_uart_tx_fifo_readable = 1'd0; +wire soc_litedramcore_uart_tx_fifo_syncfifo_we; +wire soc_litedramcore_uart_tx_fifo_syncfifo_writable; +wire soc_litedramcore_uart_tx_fifo_syncfifo_re; +wire soc_litedramcore_uart_tx_fifo_syncfifo_readable; +wire [9:0] soc_litedramcore_uart_tx_fifo_syncfifo_din; +wire [9:0] soc_litedramcore_uart_tx_fifo_syncfifo_dout; +reg [4:0] soc_litedramcore_uart_tx_fifo_level0 = 5'd0; +reg soc_litedramcore_uart_tx_fifo_replace = 1'd0; +reg [3:0] soc_litedramcore_uart_tx_fifo_produce = 4'd0; +reg [3:0] soc_litedramcore_uart_tx_fifo_consume = 4'd0; +reg [3:0] soc_litedramcore_uart_tx_fifo_wrport_adr = 4'd0; +wire [9:0] soc_litedramcore_uart_tx_fifo_wrport_dat_r; +wire soc_litedramcore_uart_tx_fifo_wrport_we; +wire [9:0] soc_litedramcore_uart_tx_fifo_wrport_dat_w; +wire soc_litedramcore_uart_tx_fifo_do_read; +wire [3:0] soc_litedramcore_uart_tx_fifo_rdport_adr; +wire [9:0] soc_litedramcore_uart_tx_fifo_rdport_dat_r; +wire soc_litedramcore_uart_tx_fifo_rdport_re; +wire [4:0] soc_litedramcore_uart_tx_fifo_level1; +wire [7:0] soc_litedramcore_uart_tx_fifo_fifo_in_payload_data; +wire soc_litedramcore_uart_tx_fifo_fifo_in_first; +wire soc_litedramcore_uart_tx_fifo_fifo_in_last; +wire [7:0] soc_litedramcore_uart_tx_fifo_fifo_out_payload_data; +wire soc_litedramcore_uart_tx_fifo_fifo_out_first; +wire soc_litedramcore_uart_tx_fifo_fifo_out_last; +wire soc_litedramcore_uart_rx_fifo_sink_valid; +wire soc_litedramcore_uart_rx_fifo_sink_ready; +wire soc_litedramcore_uart_rx_fifo_sink_first; +wire soc_litedramcore_uart_rx_fifo_sink_last; +wire [7:0] soc_litedramcore_uart_rx_fifo_sink_payload_data; +wire soc_litedramcore_uart_rx_fifo_source_valid; +wire soc_litedramcore_uart_rx_fifo_source_ready; +wire soc_litedramcore_uart_rx_fifo_source_first; +wire soc_litedramcore_uart_rx_fifo_source_last; +wire [7:0] soc_litedramcore_uart_rx_fifo_source_payload_data; +wire soc_litedramcore_uart_rx_fifo_re; +reg soc_litedramcore_uart_rx_fifo_readable = 1'd0; +wire soc_litedramcore_uart_rx_fifo_syncfifo_we; +wire soc_litedramcore_uart_rx_fifo_syncfifo_writable; +wire soc_litedramcore_uart_rx_fifo_syncfifo_re; +wire soc_litedramcore_uart_rx_fifo_syncfifo_readable; +wire [9:0] soc_litedramcore_uart_rx_fifo_syncfifo_din; +wire [9:0] soc_litedramcore_uart_rx_fifo_syncfifo_dout; +reg [4:0] soc_litedramcore_uart_rx_fifo_level0 = 5'd0; +reg soc_litedramcore_uart_rx_fifo_replace = 1'd0; +reg [3:0] soc_litedramcore_uart_rx_fifo_produce = 4'd0; +reg [3:0] soc_litedramcore_uart_rx_fifo_consume = 4'd0; +reg [3:0] soc_litedramcore_uart_rx_fifo_wrport_adr = 4'd0; +wire [9:0] soc_litedramcore_uart_rx_fifo_wrport_dat_r; +wire soc_litedramcore_uart_rx_fifo_wrport_we; +wire [9:0] soc_litedramcore_uart_rx_fifo_wrport_dat_w; +wire soc_litedramcore_uart_rx_fifo_do_read; +wire [3:0] soc_litedramcore_uart_rx_fifo_rdport_adr; +wire [9:0] soc_litedramcore_uart_rx_fifo_rdport_dat_r; +wire soc_litedramcore_uart_rx_fifo_rdport_re; +wire [4:0] soc_litedramcore_uart_rx_fifo_level1; +wire [7:0] soc_litedramcore_uart_rx_fifo_fifo_in_payload_data; +wire soc_litedramcore_uart_rx_fifo_fifo_in_first; +wire soc_litedramcore_uart_rx_fifo_fifo_in_last; +wire [7:0] soc_litedramcore_uart_rx_fifo_fifo_out_payload_data; +wire soc_litedramcore_uart_rx_fifo_fifo_out_first; +wire soc_litedramcore_uart_rx_fifo_fifo_out_last; +reg soc_litedramcore_uart_reset = 1'd0; +reg [31:0] soc_litedramcore_timer_load_storage = 32'd0; +reg soc_litedramcore_timer_load_re = 1'd0; +reg [31:0] soc_litedramcore_timer_reload_storage = 32'd0; +reg soc_litedramcore_timer_reload_re = 1'd0; +reg soc_litedramcore_timer_en_storage = 1'd0; +reg soc_litedramcore_timer_en_re = 1'd0; +reg soc_litedramcore_timer_update_value_storage = 1'd0; +reg soc_litedramcore_timer_update_value_re = 1'd0; +reg [31:0] soc_litedramcore_timer_value_status = 32'd0; +wire soc_litedramcore_timer_value_we; +wire soc_litedramcore_timer_irq; +wire soc_litedramcore_timer_zero_status; +reg soc_litedramcore_timer_zero_pending = 1'd0; +wire soc_litedramcore_timer_zero_trigger; +reg soc_litedramcore_timer_zero_clear = 1'd0; +reg soc_litedramcore_timer_zero_old_trigger = 1'd0; +wire soc_litedramcore_timer_eventmanager_status_re; +wire soc_litedramcore_timer_eventmanager_status_r; +wire soc_litedramcore_timer_eventmanager_status_we; +wire soc_litedramcore_timer_eventmanager_status_w; +wire soc_litedramcore_timer_eventmanager_pending_re; +wire soc_litedramcore_timer_eventmanager_pending_r; +wire soc_litedramcore_timer_eventmanager_pending_we; +wire soc_litedramcore_timer_eventmanager_pending_w; +reg soc_litedramcore_timer_eventmanager_storage = 1'd0; +reg soc_litedramcore_timer_eventmanager_re = 1'd0; +reg [31:0] soc_litedramcore_timer_value = 32'd0; +reg [13:0] soc_litedramcore_interface_adr = 14'd0; +reg soc_litedramcore_interface_we = 1'd0; +wire [7:0] soc_litedramcore_interface_dat_w; +wire [7:0] soc_litedramcore_interface_dat_r; +wire [29:0] soc_litedramcore_bus_wishbone_adr; +wire [31:0] soc_litedramcore_bus_wishbone_dat_w; +wire [31:0] soc_litedramcore_bus_wishbone_dat_r; +wire [3:0] soc_litedramcore_bus_wishbone_sel; +wire soc_litedramcore_bus_wishbone_cyc; +wire soc_litedramcore_bus_wishbone_stb; +reg soc_litedramcore_bus_wishbone_ack = 1'd0; +wire soc_litedramcore_bus_wishbone_we; +wire [2:0] soc_litedramcore_bus_wishbone_cti; +wire [1:0] soc_litedramcore_bus_wishbone_bte; +reg soc_litedramcore_bus_wishbone_err = 1'd0; +wire sys_clk; +wire sys_rst; +wire sys4x_clk; +wire sys4x_dqs_clk; +wire iodelay_clk; +wire iodelay_rst; +wire soc_sys_pll_reset; +wire soc_sys_pll_locked; +wire soc_s7pll0_clkin; +wire soc_s7pll0_clkout0; +wire soc_s7pll0_clkout_buf0; +wire soc_s7pll0_clkout1; +wire soc_s7pll0_clkout_buf1; +wire soc_s7pll0_clkout2; +wire soc_s7pll0_clkout_buf2; +wire soc_iodelay_pll_reset; +wire soc_iodelay_pll_locked; +wire soc_s7pll1_clkin; +wire soc_s7pll1_clkout; +wire soc_s7pll1_clkout_buf; +reg [3:0] soc_reset_counter = 4'd15; +reg soc_ic_reset = 1'd1; +reg [4:0] soc_a7ddrphy_half_sys8x_taps_storage = 5'd8; +reg soc_a7ddrphy_half_sys8x_taps_re = 1'd0; +reg soc_a7ddrphy_wlevel_en_storage = 1'd0; +reg soc_a7ddrphy_wlevel_en_re = 1'd0; +wire soc_a7ddrphy_wlevel_strobe_re; +wire soc_a7ddrphy_wlevel_strobe_r; +wire soc_a7ddrphy_wlevel_strobe_we; +reg soc_a7ddrphy_wlevel_strobe_w = 1'd0; +wire soc_a7ddrphy_cdly_rst_re; +wire soc_a7ddrphy_cdly_rst_r; +wire soc_a7ddrphy_cdly_rst_we; +reg soc_a7ddrphy_cdly_rst_w = 1'd0; +wire soc_a7ddrphy_cdly_inc_re; +wire soc_a7ddrphy_cdly_inc_r; +wire soc_a7ddrphy_cdly_inc_we; +reg soc_a7ddrphy_cdly_inc_w = 1'd0; +reg [1:0] soc_a7ddrphy_dly_sel_storage = 2'd0; +reg soc_a7ddrphy_dly_sel_re = 1'd0; +wire soc_a7ddrphy_rdly_dq_rst_re; +wire soc_a7ddrphy_rdly_dq_rst_r; +wire soc_a7ddrphy_rdly_dq_rst_we; +reg soc_a7ddrphy_rdly_dq_rst_w = 1'd0; +wire soc_a7ddrphy_rdly_dq_inc_re; +wire soc_a7ddrphy_rdly_dq_inc_r; +wire soc_a7ddrphy_rdly_dq_inc_we; +reg soc_a7ddrphy_rdly_dq_inc_w = 1'd0; +wire soc_a7ddrphy_rdly_dq_bitslip_rst_re; +wire soc_a7ddrphy_rdly_dq_bitslip_rst_r; +wire soc_a7ddrphy_rdly_dq_bitslip_rst_we; +reg soc_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +wire soc_a7ddrphy_rdly_dq_bitslip_re; +wire soc_a7ddrphy_rdly_dq_bitslip_r; +wire soc_a7ddrphy_rdly_dq_bitslip_we; +reg soc_a7ddrphy_rdly_dq_bitslip_w = 1'd0; +wire [14:0] soc_a7ddrphy_dfi_p0_address; +wire [2:0] soc_a7ddrphy_dfi_p0_bank; +wire soc_a7ddrphy_dfi_p0_cas_n; +wire soc_a7ddrphy_dfi_p0_cs_n; +wire soc_a7ddrphy_dfi_p0_ras_n; +wire soc_a7ddrphy_dfi_p0_we_n; +wire soc_a7ddrphy_dfi_p0_cke; +wire soc_a7ddrphy_dfi_p0_odt; +wire soc_a7ddrphy_dfi_p0_reset_n; +wire soc_a7ddrphy_dfi_p0_act_n; +wire [31:0] soc_a7ddrphy_dfi_p0_wrdata; +wire soc_a7ddrphy_dfi_p0_wrdata_en; +wire [3:0] soc_a7ddrphy_dfi_p0_wrdata_mask; +wire soc_a7ddrphy_dfi_p0_rddata_en; +reg [31:0] soc_a7ddrphy_dfi_p0_rddata = 32'd0; +reg soc_a7ddrphy_dfi_p0_rddata_valid = 1'd0; +wire [14:0] soc_a7ddrphy_dfi_p1_address; +wire [2:0] soc_a7ddrphy_dfi_p1_bank; +wire soc_a7ddrphy_dfi_p1_cas_n; +wire soc_a7ddrphy_dfi_p1_cs_n; +wire soc_a7ddrphy_dfi_p1_ras_n; +wire soc_a7ddrphy_dfi_p1_we_n; +wire soc_a7ddrphy_dfi_p1_cke; +wire soc_a7ddrphy_dfi_p1_odt; +wire soc_a7ddrphy_dfi_p1_reset_n; +wire soc_a7ddrphy_dfi_p1_act_n; +wire [31:0] soc_a7ddrphy_dfi_p1_wrdata; +wire soc_a7ddrphy_dfi_p1_wrdata_en; +wire [3:0] soc_a7ddrphy_dfi_p1_wrdata_mask; +wire soc_a7ddrphy_dfi_p1_rddata_en; +reg [31:0] soc_a7ddrphy_dfi_p1_rddata = 32'd0; +reg soc_a7ddrphy_dfi_p1_rddata_valid = 1'd0; +wire [14:0] soc_a7ddrphy_dfi_p2_address; +wire [2:0] soc_a7ddrphy_dfi_p2_bank; +wire soc_a7ddrphy_dfi_p2_cas_n; +wire soc_a7ddrphy_dfi_p2_cs_n; +wire soc_a7ddrphy_dfi_p2_ras_n; +wire soc_a7ddrphy_dfi_p2_we_n; +wire soc_a7ddrphy_dfi_p2_cke; +wire soc_a7ddrphy_dfi_p2_odt; +wire soc_a7ddrphy_dfi_p2_reset_n; +wire soc_a7ddrphy_dfi_p2_act_n; +wire [31:0] soc_a7ddrphy_dfi_p2_wrdata; +wire soc_a7ddrphy_dfi_p2_wrdata_en; +wire [3:0] soc_a7ddrphy_dfi_p2_wrdata_mask; +wire soc_a7ddrphy_dfi_p2_rddata_en; +reg [31:0] soc_a7ddrphy_dfi_p2_rddata = 32'd0; +reg soc_a7ddrphy_dfi_p2_rddata_valid = 1'd0; +wire [14:0] soc_a7ddrphy_dfi_p3_address; +wire [2:0] soc_a7ddrphy_dfi_p3_bank; +wire soc_a7ddrphy_dfi_p3_cas_n; +wire soc_a7ddrphy_dfi_p3_cs_n; +wire soc_a7ddrphy_dfi_p3_ras_n; +wire soc_a7ddrphy_dfi_p3_we_n; +wire soc_a7ddrphy_dfi_p3_cke; +wire soc_a7ddrphy_dfi_p3_odt; +wire soc_a7ddrphy_dfi_p3_reset_n; +wire soc_a7ddrphy_dfi_p3_act_n; +wire [31:0] soc_a7ddrphy_dfi_p3_wrdata; +wire soc_a7ddrphy_dfi_p3_wrdata_en; +wire [3:0] soc_a7ddrphy_dfi_p3_wrdata_mask; +wire soc_a7ddrphy_dfi_p3_rddata_en; +reg [31:0] soc_a7ddrphy_dfi_p3_rddata = 32'd0; +reg soc_a7ddrphy_dfi_p3_rddata_valid = 1'd0; +wire soc_a7ddrphy_sd_clk_se_nodelay; +reg soc_a7ddrphy_dqs_oe = 1'd0; +reg soc_a7ddrphy_dqs_oe_delayed = 1'd0; +wire soc_a7ddrphy_dqspattern0; +wire soc_a7ddrphy_dqspattern1; +reg [7:0] soc_a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] soc_a7ddrphy_dqspattern_o1 = 8'd0; +wire [1:0] soc_a7ddrphy_dqs_i; +wire [1:0] soc_a7ddrphy_dqs_i_delayed; +wire soc_a7ddrphy_dqs_o_no_delay0; +wire soc_a7ddrphy_dqs_t0; +wire soc_a7ddrphy0; +wire soc_a7ddrphy_dqs_o_no_delay1; +wire soc_a7ddrphy_dqs_t1; +wire soc_a7ddrphy1; +wire soc_a7ddrphy_dq_oe; +reg soc_a7ddrphy_dq_oe_delayed = 1'd0; +wire soc_a7ddrphy_dq_o_nodelay0; +wire soc_a7ddrphy_dq_i_nodelay0; +wire soc_a7ddrphy_dq_i_delayed0; +wire soc_a7ddrphy_dq_t0; +wire [7:0] soc_a7ddrphy_dq_i_data0; +wire [7:0] soc_a7ddrphy_bitslip0_i; +reg [7:0] soc_a7ddrphy_bitslip0_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip0_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip0_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay1; +wire soc_a7ddrphy_dq_i_nodelay1; +wire soc_a7ddrphy_dq_i_delayed1; +wire soc_a7ddrphy_dq_t1; +wire [7:0] soc_a7ddrphy_dq_i_data1; +wire [7:0] soc_a7ddrphy_bitslip1_i; +reg [7:0] soc_a7ddrphy_bitslip1_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip1_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip1_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay2; +wire soc_a7ddrphy_dq_i_nodelay2; +wire soc_a7ddrphy_dq_i_delayed2; +wire soc_a7ddrphy_dq_t2; +wire [7:0] soc_a7ddrphy_dq_i_data2; +wire [7:0] soc_a7ddrphy_bitslip2_i; +reg [7:0] soc_a7ddrphy_bitslip2_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip2_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip2_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay3; +wire soc_a7ddrphy_dq_i_nodelay3; +wire soc_a7ddrphy_dq_i_delayed3; +wire soc_a7ddrphy_dq_t3; +wire [7:0] soc_a7ddrphy_dq_i_data3; +wire [7:0] soc_a7ddrphy_bitslip3_i; +reg [7:0] soc_a7ddrphy_bitslip3_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip3_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip3_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay4; +wire soc_a7ddrphy_dq_i_nodelay4; +wire soc_a7ddrphy_dq_i_delayed4; +wire soc_a7ddrphy_dq_t4; +wire [7:0] soc_a7ddrphy_dq_i_data4; +wire [7:0] soc_a7ddrphy_bitslip4_i; +reg [7:0] soc_a7ddrphy_bitslip4_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip4_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip4_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay5; +wire soc_a7ddrphy_dq_i_nodelay5; +wire soc_a7ddrphy_dq_i_delayed5; +wire soc_a7ddrphy_dq_t5; +wire [7:0] soc_a7ddrphy_dq_i_data5; +wire [7:0] soc_a7ddrphy_bitslip5_i; +reg [7:0] soc_a7ddrphy_bitslip5_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip5_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip5_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay6; +wire soc_a7ddrphy_dq_i_nodelay6; +wire soc_a7ddrphy_dq_i_delayed6; +wire soc_a7ddrphy_dq_t6; +wire [7:0] soc_a7ddrphy_dq_i_data6; +wire [7:0] soc_a7ddrphy_bitslip6_i; +reg [7:0] soc_a7ddrphy_bitslip6_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip6_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip6_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay7; +wire soc_a7ddrphy_dq_i_nodelay7; +wire soc_a7ddrphy_dq_i_delayed7; +wire soc_a7ddrphy_dq_t7; +wire [7:0] soc_a7ddrphy_dq_i_data7; +wire [7:0] soc_a7ddrphy_bitslip7_i; +reg [7:0] soc_a7ddrphy_bitslip7_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip7_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip7_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay8; +wire soc_a7ddrphy_dq_i_nodelay8; +wire soc_a7ddrphy_dq_i_delayed8; +wire soc_a7ddrphy_dq_t8; +wire [7:0] soc_a7ddrphy_dq_i_data8; +wire [7:0] soc_a7ddrphy_bitslip8_i; +reg [7:0] soc_a7ddrphy_bitslip8_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip8_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip8_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay9; +wire soc_a7ddrphy_dq_i_nodelay9; +wire soc_a7ddrphy_dq_i_delayed9; +wire soc_a7ddrphy_dq_t9; +wire [7:0] soc_a7ddrphy_dq_i_data9; +wire [7:0] soc_a7ddrphy_bitslip9_i; +reg [7:0] soc_a7ddrphy_bitslip9_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip9_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip9_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay10; +wire soc_a7ddrphy_dq_i_nodelay10; +wire soc_a7ddrphy_dq_i_delayed10; +wire soc_a7ddrphy_dq_t10; +wire [7:0] soc_a7ddrphy_dq_i_data10; +wire [7:0] soc_a7ddrphy_bitslip10_i; +reg [7:0] soc_a7ddrphy_bitslip10_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip10_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip10_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay11; +wire soc_a7ddrphy_dq_i_nodelay11; +wire soc_a7ddrphy_dq_i_delayed11; +wire soc_a7ddrphy_dq_t11; +wire [7:0] soc_a7ddrphy_dq_i_data11; +wire [7:0] soc_a7ddrphy_bitslip11_i; +reg [7:0] soc_a7ddrphy_bitslip11_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip11_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip11_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay12; +wire soc_a7ddrphy_dq_i_nodelay12; +wire soc_a7ddrphy_dq_i_delayed12; +wire soc_a7ddrphy_dq_t12; +wire [7:0] soc_a7ddrphy_dq_i_data12; +wire [7:0] soc_a7ddrphy_bitslip12_i; +reg [7:0] soc_a7ddrphy_bitslip12_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip12_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip12_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay13; +wire soc_a7ddrphy_dq_i_nodelay13; +wire soc_a7ddrphy_dq_i_delayed13; +wire soc_a7ddrphy_dq_t13; +wire [7:0] soc_a7ddrphy_dq_i_data13; +wire [7:0] soc_a7ddrphy_bitslip13_i; +reg [7:0] soc_a7ddrphy_bitslip13_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip13_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip13_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay14; +wire soc_a7ddrphy_dq_i_nodelay14; +wire soc_a7ddrphy_dq_i_delayed14; +wire soc_a7ddrphy_dq_t14; +wire [7:0] soc_a7ddrphy_dq_i_data14; +wire [7:0] soc_a7ddrphy_bitslip14_i; +reg [7:0] soc_a7ddrphy_bitslip14_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip14_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip14_r = 16'd0; +wire soc_a7ddrphy_dq_o_nodelay15; +wire soc_a7ddrphy_dq_i_nodelay15; +wire soc_a7ddrphy_dq_i_delayed15; +wire soc_a7ddrphy_dq_t15; +wire [7:0] soc_a7ddrphy_dq_i_data15; +wire [7:0] soc_a7ddrphy_bitslip15_i; +reg [7:0] soc_a7ddrphy_bitslip15_o = 8'd0; +reg [2:0] soc_a7ddrphy_bitslip15_value = 3'd0; +reg [15:0] soc_a7ddrphy_bitslip15_r = 16'd0; +wire [7:0] soc_a7ddrphy_rddata_en; +reg [7:0] soc_a7ddrphy_rddata_en_last = 8'd0; +wire [3:0] soc_a7ddrphy_wrdata_en; +reg [3:0] soc_a7ddrphy_wrdata_en_last = 4'd0; +wire [14:0] soc_sdram_inti_p0_address; +wire [2:0] soc_sdram_inti_p0_bank; +reg soc_sdram_inti_p0_cas_n = 1'd1; +reg soc_sdram_inti_p0_cs_n = 1'd1; +reg soc_sdram_inti_p0_ras_n = 1'd1; +reg soc_sdram_inti_p0_we_n = 1'd1; +wire soc_sdram_inti_p0_cke; +wire soc_sdram_inti_p0_odt; +wire soc_sdram_inti_p0_reset_n; +reg soc_sdram_inti_p0_act_n = 1'd1; +wire [31:0] soc_sdram_inti_p0_wrdata; +wire soc_sdram_inti_p0_wrdata_en; +wire [3:0] soc_sdram_inti_p0_wrdata_mask; +wire soc_sdram_inti_p0_rddata_en; +reg [31:0] soc_sdram_inti_p0_rddata = 32'd0; +reg soc_sdram_inti_p0_rddata_valid = 1'd0; +wire [14:0] soc_sdram_inti_p1_address; +wire [2:0] soc_sdram_inti_p1_bank; +reg soc_sdram_inti_p1_cas_n = 1'd1; +reg soc_sdram_inti_p1_cs_n = 1'd1; +reg soc_sdram_inti_p1_ras_n = 1'd1; +reg soc_sdram_inti_p1_we_n = 1'd1; +wire soc_sdram_inti_p1_cke; +wire soc_sdram_inti_p1_odt; +wire soc_sdram_inti_p1_reset_n; +reg soc_sdram_inti_p1_act_n = 1'd1; +wire [31:0] soc_sdram_inti_p1_wrdata; +wire soc_sdram_inti_p1_wrdata_en; +wire [3:0] soc_sdram_inti_p1_wrdata_mask; +wire soc_sdram_inti_p1_rddata_en; +reg [31:0] soc_sdram_inti_p1_rddata = 32'd0; +reg soc_sdram_inti_p1_rddata_valid = 1'd0; +wire [14:0] soc_sdram_inti_p2_address; +wire [2:0] soc_sdram_inti_p2_bank; +reg soc_sdram_inti_p2_cas_n = 1'd1; +reg soc_sdram_inti_p2_cs_n = 1'd1; +reg soc_sdram_inti_p2_ras_n = 1'd1; +reg soc_sdram_inti_p2_we_n = 1'd1; +wire soc_sdram_inti_p2_cke; +wire soc_sdram_inti_p2_odt; +wire soc_sdram_inti_p2_reset_n; +reg soc_sdram_inti_p2_act_n = 1'd1; +wire [31:0] soc_sdram_inti_p2_wrdata; +wire soc_sdram_inti_p2_wrdata_en; +wire [3:0] soc_sdram_inti_p2_wrdata_mask; +wire soc_sdram_inti_p2_rddata_en; +reg [31:0] soc_sdram_inti_p2_rddata = 32'd0; +reg soc_sdram_inti_p2_rddata_valid = 1'd0; +wire [14:0] soc_sdram_inti_p3_address; +wire [2:0] soc_sdram_inti_p3_bank; +reg soc_sdram_inti_p3_cas_n = 1'd1; +reg soc_sdram_inti_p3_cs_n = 1'd1; +reg soc_sdram_inti_p3_ras_n = 1'd1; +reg soc_sdram_inti_p3_we_n = 1'd1; +wire soc_sdram_inti_p3_cke; +wire soc_sdram_inti_p3_odt; +wire soc_sdram_inti_p3_reset_n; +reg soc_sdram_inti_p3_act_n = 1'd1; +wire [31:0] soc_sdram_inti_p3_wrdata; +wire soc_sdram_inti_p3_wrdata_en; +wire [3:0] soc_sdram_inti_p3_wrdata_mask; +wire soc_sdram_inti_p3_rddata_en; +reg [31:0] soc_sdram_inti_p3_rddata = 32'd0; +reg soc_sdram_inti_p3_rddata_valid = 1'd0; +wire [14:0] soc_sdram_slave_p0_address; +wire [2:0] soc_sdram_slave_p0_bank; +wire soc_sdram_slave_p0_cas_n; +wire soc_sdram_slave_p0_cs_n; +wire soc_sdram_slave_p0_ras_n; +wire soc_sdram_slave_p0_we_n; +wire soc_sdram_slave_p0_cke; +wire soc_sdram_slave_p0_odt; +wire soc_sdram_slave_p0_reset_n; +wire soc_sdram_slave_p0_act_n; +wire [31:0] soc_sdram_slave_p0_wrdata; +wire soc_sdram_slave_p0_wrdata_en; +wire [3:0] soc_sdram_slave_p0_wrdata_mask; +wire soc_sdram_slave_p0_rddata_en; +reg [31:0] soc_sdram_slave_p0_rddata = 32'd0; +reg soc_sdram_slave_p0_rddata_valid = 1'd0; +wire [14:0] soc_sdram_slave_p1_address; +wire [2:0] soc_sdram_slave_p1_bank; +wire soc_sdram_slave_p1_cas_n; +wire soc_sdram_slave_p1_cs_n; +wire soc_sdram_slave_p1_ras_n; +wire soc_sdram_slave_p1_we_n; +wire soc_sdram_slave_p1_cke; +wire soc_sdram_slave_p1_odt; +wire soc_sdram_slave_p1_reset_n; +wire soc_sdram_slave_p1_act_n; +wire [31:0] soc_sdram_slave_p1_wrdata; +wire soc_sdram_slave_p1_wrdata_en; +wire [3:0] soc_sdram_slave_p1_wrdata_mask; +wire soc_sdram_slave_p1_rddata_en; +reg [31:0] soc_sdram_slave_p1_rddata = 32'd0; +reg soc_sdram_slave_p1_rddata_valid = 1'd0; +wire [14:0] soc_sdram_slave_p2_address; +wire [2:0] soc_sdram_slave_p2_bank; +wire soc_sdram_slave_p2_cas_n; +wire soc_sdram_slave_p2_cs_n; +wire soc_sdram_slave_p2_ras_n; +wire soc_sdram_slave_p2_we_n; +wire soc_sdram_slave_p2_cke; +wire soc_sdram_slave_p2_odt; +wire soc_sdram_slave_p2_reset_n; +wire soc_sdram_slave_p2_act_n; +wire [31:0] soc_sdram_slave_p2_wrdata; +wire soc_sdram_slave_p2_wrdata_en; +wire [3:0] soc_sdram_slave_p2_wrdata_mask; +wire soc_sdram_slave_p2_rddata_en; +reg [31:0] soc_sdram_slave_p2_rddata = 32'd0; +reg soc_sdram_slave_p2_rddata_valid = 1'd0; +wire [14:0] soc_sdram_slave_p3_address; +wire [2:0] soc_sdram_slave_p3_bank; +wire soc_sdram_slave_p3_cas_n; +wire soc_sdram_slave_p3_cs_n; +wire soc_sdram_slave_p3_ras_n; +wire soc_sdram_slave_p3_we_n; +wire soc_sdram_slave_p3_cke; +wire soc_sdram_slave_p3_odt; +wire soc_sdram_slave_p3_reset_n; +wire soc_sdram_slave_p3_act_n; +wire [31:0] soc_sdram_slave_p3_wrdata; +wire soc_sdram_slave_p3_wrdata_en; +wire [3:0] soc_sdram_slave_p3_wrdata_mask; +wire soc_sdram_slave_p3_rddata_en; +reg [31:0] soc_sdram_slave_p3_rddata = 32'd0; +reg soc_sdram_slave_p3_rddata_valid = 1'd0; +reg [14:0] soc_sdram_master_p0_address = 15'd0; +reg [2:0] soc_sdram_master_p0_bank = 3'd0; +reg soc_sdram_master_p0_cas_n = 1'd1; +reg soc_sdram_master_p0_cs_n = 1'd1; +reg soc_sdram_master_p0_ras_n = 1'd1; +reg soc_sdram_master_p0_we_n = 1'd1; +reg soc_sdram_master_p0_cke = 1'd0; +reg soc_sdram_master_p0_odt = 1'd0; +reg soc_sdram_master_p0_reset_n = 1'd0; +reg soc_sdram_master_p0_act_n = 1'd1; +reg [31:0] soc_sdram_master_p0_wrdata = 32'd0; +reg soc_sdram_master_p0_wrdata_en = 1'd0; +reg [3:0] soc_sdram_master_p0_wrdata_mask = 4'd0; +reg soc_sdram_master_p0_rddata_en = 1'd0; +wire [31:0] soc_sdram_master_p0_rddata; +wire soc_sdram_master_p0_rddata_valid; +reg [14:0] soc_sdram_master_p1_address = 15'd0; +reg [2:0] soc_sdram_master_p1_bank = 3'd0; +reg soc_sdram_master_p1_cas_n = 1'd1; +reg soc_sdram_master_p1_cs_n = 1'd1; +reg soc_sdram_master_p1_ras_n = 1'd1; +reg soc_sdram_master_p1_we_n = 1'd1; +reg soc_sdram_master_p1_cke = 1'd0; +reg soc_sdram_master_p1_odt = 1'd0; +reg soc_sdram_master_p1_reset_n = 1'd0; +reg soc_sdram_master_p1_act_n = 1'd1; +reg [31:0] soc_sdram_master_p1_wrdata = 32'd0; +reg soc_sdram_master_p1_wrdata_en = 1'd0; +reg [3:0] soc_sdram_master_p1_wrdata_mask = 4'd0; +reg soc_sdram_master_p1_rddata_en = 1'd0; +wire [31:0] soc_sdram_master_p1_rddata; +wire soc_sdram_master_p1_rddata_valid; +reg [14:0] soc_sdram_master_p2_address = 15'd0; +reg [2:0] soc_sdram_master_p2_bank = 3'd0; +reg soc_sdram_master_p2_cas_n = 1'd1; +reg soc_sdram_master_p2_cs_n = 1'd1; +reg soc_sdram_master_p2_ras_n = 1'd1; +reg soc_sdram_master_p2_we_n = 1'd1; +reg soc_sdram_master_p2_cke = 1'd0; +reg soc_sdram_master_p2_odt = 1'd0; +reg soc_sdram_master_p2_reset_n = 1'd0; +reg soc_sdram_master_p2_act_n = 1'd1; +reg [31:0] soc_sdram_master_p2_wrdata = 32'd0; +reg soc_sdram_master_p2_wrdata_en = 1'd0; +reg [3:0] soc_sdram_master_p2_wrdata_mask = 4'd0; +reg soc_sdram_master_p2_rddata_en = 1'd0; +wire [31:0] soc_sdram_master_p2_rddata; +wire soc_sdram_master_p2_rddata_valid; +reg [14:0] soc_sdram_master_p3_address = 15'd0; +reg [2:0] soc_sdram_master_p3_bank = 3'd0; +reg soc_sdram_master_p3_cas_n = 1'd1; +reg soc_sdram_master_p3_cs_n = 1'd1; +reg soc_sdram_master_p3_ras_n = 1'd1; +reg soc_sdram_master_p3_we_n = 1'd1; +reg soc_sdram_master_p3_cke = 1'd0; +reg soc_sdram_master_p3_odt = 1'd0; +reg soc_sdram_master_p3_reset_n = 1'd0; +reg soc_sdram_master_p3_act_n = 1'd1; +reg [31:0] soc_sdram_master_p3_wrdata = 32'd0; +reg soc_sdram_master_p3_wrdata_en = 1'd0; +reg [3:0] soc_sdram_master_p3_wrdata_mask = 4'd0; +reg soc_sdram_master_p3_rddata_en = 1'd0; +wire [31:0] soc_sdram_master_p3_rddata; +wire soc_sdram_master_p3_rddata_valid; +reg [3:0] soc_sdram_storage = 4'd0; +reg soc_sdram_re = 1'd0; +reg [5:0] soc_sdram_phaseinjector0_command_storage = 6'd0; +reg soc_sdram_phaseinjector0_command_re = 1'd0; +wire soc_sdram_phaseinjector0_command_issue_re; +wire soc_sdram_phaseinjector0_command_issue_r; +wire soc_sdram_phaseinjector0_command_issue_we; +reg soc_sdram_phaseinjector0_command_issue_w = 1'd0; +reg [14:0] soc_sdram_phaseinjector0_address_storage = 15'd0; +reg soc_sdram_phaseinjector0_address_re = 1'd0; +reg [2:0] soc_sdram_phaseinjector0_baddress_storage = 3'd0; +reg soc_sdram_phaseinjector0_baddress_re = 1'd0; +reg [31:0] soc_sdram_phaseinjector0_wrdata_storage = 32'd0; +reg soc_sdram_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] soc_sdram_phaseinjector0_status = 32'd0; +wire soc_sdram_phaseinjector0_we; +reg [5:0] soc_sdram_phaseinjector1_command_storage = 6'd0; +reg soc_sdram_phaseinjector1_command_re = 1'd0; +wire soc_sdram_phaseinjector1_command_issue_re; +wire soc_sdram_phaseinjector1_command_issue_r; +wire soc_sdram_phaseinjector1_command_issue_we; +reg soc_sdram_phaseinjector1_command_issue_w = 1'd0; +reg [14:0] soc_sdram_phaseinjector1_address_storage = 15'd0; +reg soc_sdram_phaseinjector1_address_re = 1'd0; +reg [2:0] soc_sdram_phaseinjector1_baddress_storage = 3'd0; +reg soc_sdram_phaseinjector1_baddress_re = 1'd0; +reg [31:0] soc_sdram_phaseinjector1_wrdata_storage = 32'd0; +reg soc_sdram_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] soc_sdram_phaseinjector1_status = 32'd0; +wire soc_sdram_phaseinjector1_we; +reg [5:0] soc_sdram_phaseinjector2_command_storage = 6'd0; +reg soc_sdram_phaseinjector2_command_re = 1'd0; +wire soc_sdram_phaseinjector2_command_issue_re; +wire soc_sdram_phaseinjector2_command_issue_r; +wire soc_sdram_phaseinjector2_command_issue_we; +reg soc_sdram_phaseinjector2_command_issue_w = 1'd0; +reg [14:0] soc_sdram_phaseinjector2_address_storage = 15'd0; +reg soc_sdram_phaseinjector2_address_re = 1'd0; +reg [2:0] soc_sdram_phaseinjector2_baddress_storage = 3'd0; +reg soc_sdram_phaseinjector2_baddress_re = 1'd0; +reg [31:0] soc_sdram_phaseinjector2_wrdata_storage = 32'd0; +reg soc_sdram_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] soc_sdram_phaseinjector2_status = 32'd0; +wire soc_sdram_phaseinjector2_we; +reg [5:0] soc_sdram_phaseinjector3_command_storage = 6'd0; +reg soc_sdram_phaseinjector3_command_re = 1'd0; +wire soc_sdram_phaseinjector3_command_issue_re; +wire soc_sdram_phaseinjector3_command_issue_r; +wire soc_sdram_phaseinjector3_command_issue_we; +reg soc_sdram_phaseinjector3_command_issue_w = 1'd0; +reg [14:0] soc_sdram_phaseinjector3_address_storage = 15'd0; +reg soc_sdram_phaseinjector3_address_re = 1'd0; +reg [2:0] soc_sdram_phaseinjector3_baddress_storage = 3'd0; +reg soc_sdram_phaseinjector3_baddress_re = 1'd0; +reg [31:0] soc_sdram_phaseinjector3_wrdata_storage = 32'd0; +reg soc_sdram_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] soc_sdram_phaseinjector3_status = 32'd0; +wire soc_sdram_phaseinjector3_we; +wire soc_sdram_interface_bank0_valid; +wire soc_sdram_interface_bank0_ready; +wire soc_sdram_interface_bank0_we; +wire [21:0] soc_sdram_interface_bank0_addr; +wire soc_sdram_interface_bank0_lock; +wire soc_sdram_interface_bank0_wdata_ready; +wire soc_sdram_interface_bank0_rdata_valid; +wire soc_sdram_interface_bank1_valid; +wire soc_sdram_interface_bank1_ready; +wire soc_sdram_interface_bank1_we; +wire [21:0] soc_sdram_interface_bank1_addr; +wire soc_sdram_interface_bank1_lock; +wire soc_sdram_interface_bank1_wdata_ready; +wire soc_sdram_interface_bank1_rdata_valid; +wire soc_sdram_interface_bank2_valid; +wire soc_sdram_interface_bank2_ready; +wire soc_sdram_interface_bank2_we; +wire [21:0] soc_sdram_interface_bank2_addr; +wire soc_sdram_interface_bank2_lock; +wire soc_sdram_interface_bank2_wdata_ready; +wire soc_sdram_interface_bank2_rdata_valid; +wire soc_sdram_interface_bank3_valid; +wire soc_sdram_interface_bank3_ready; +wire soc_sdram_interface_bank3_we; +wire [21:0] soc_sdram_interface_bank3_addr; +wire soc_sdram_interface_bank3_lock; +wire soc_sdram_interface_bank3_wdata_ready; +wire soc_sdram_interface_bank3_rdata_valid; +wire soc_sdram_interface_bank4_valid; +wire soc_sdram_interface_bank4_ready; +wire soc_sdram_interface_bank4_we; +wire [21:0] soc_sdram_interface_bank4_addr; +wire soc_sdram_interface_bank4_lock; +wire soc_sdram_interface_bank4_wdata_ready; +wire soc_sdram_interface_bank4_rdata_valid; +wire soc_sdram_interface_bank5_valid; +wire soc_sdram_interface_bank5_ready; +wire soc_sdram_interface_bank5_we; +wire [21:0] soc_sdram_interface_bank5_addr; +wire soc_sdram_interface_bank5_lock; +wire soc_sdram_interface_bank5_wdata_ready; +wire soc_sdram_interface_bank5_rdata_valid; +wire soc_sdram_interface_bank6_valid; +wire soc_sdram_interface_bank6_ready; +wire soc_sdram_interface_bank6_we; +wire [21:0] soc_sdram_interface_bank6_addr; +wire soc_sdram_interface_bank6_lock; +wire soc_sdram_interface_bank6_wdata_ready; +wire soc_sdram_interface_bank6_rdata_valid; +wire soc_sdram_interface_bank7_valid; +wire soc_sdram_interface_bank7_ready; +wire soc_sdram_interface_bank7_we; +wire [21:0] soc_sdram_interface_bank7_addr; +wire soc_sdram_interface_bank7_lock; +wire soc_sdram_interface_bank7_wdata_ready; +wire soc_sdram_interface_bank7_rdata_valid; +reg [127:0] soc_sdram_interface_wdata = 128'd0; +reg [15:0] soc_sdram_interface_wdata_we = 16'd0; +wire [127:0] soc_sdram_interface_rdata; +reg [14:0] soc_sdram_dfi_p0_address = 15'd0; +reg [2:0] soc_sdram_dfi_p0_bank = 3'd0; +reg soc_sdram_dfi_p0_cas_n = 1'd1; +reg soc_sdram_dfi_p0_cs_n = 1'd1; +reg soc_sdram_dfi_p0_ras_n = 1'd1; +reg soc_sdram_dfi_p0_we_n = 1'd1; +wire soc_sdram_dfi_p0_cke; +wire soc_sdram_dfi_p0_odt; +wire soc_sdram_dfi_p0_reset_n; +reg soc_sdram_dfi_p0_act_n = 1'd1; +wire [31:0] soc_sdram_dfi_p0_wrdata; +reg soc_sdram_dfi_p0_wrdata_en = 1'd0; +wire [3:0] soc_sdram_dfi_p0_wrdata_mask; +reg soc_sdram_dfi_p0_rddata_en = 1'd0; +wire [31:0] soc_sdram_dfi_p0_rddata; +wire soc_sdram_dfi_p0_rddata_valid; +reg [14:0] soc_sdram_dfi_p1_address = 15'd0; +reg [2:0] soc_sdram_dfi_p1_bank = 3'd0; +reg soc_sdram_dfi_p1_cas_n = 1'd1; +reg soc_sdram_dfi_p1_cs_n = 1'd1; +reg soc_sdram_dfi_p1_ras_n = 1'd1; +reg soc_sdram_dfi_p1_we_n = 1'd1; +wire soc_sdram_dfi_p1_cke; +wire soc_sdram_dfi_p1_odt; +wire soc_sdram_dfi_p1_reset_n; +reg soc_sdram_dfi_p1_act_n = 1'd1; +wire [31:0] soc_sdram_dfi_p1_wrdata; +reg soc_sdram_dfi_p1_wrdata_en = 1'd0; +wire [3:0] soc_sdram_dfi_p1_wrdata_mask; +reg soc_sdram_dfi_p1_rddata_en = 1'd0; +wire [31:0] soc_sdram_dfi_p1_rddata; +wire soc_sdram_dfi_p1_rddata_valid; +reg [14:0] soc_sdram_dfi_p2_address = 15'd0; +reg [2:0] soc_sdram_dfi_p2_bank = 3'd0; +reg soc_sdram_dfi_p2_cas_n = 1'd1; +reg soc_sdram_dfi_p2_cs_n = 1'd1; +reg soc_sdram_dfi_p2_ras_n = 1'd1; +reg soc_sdram_dfi_p2_we_n = 1'd1; +wire soc_sdram_dfi_p2_cke; +wire soc_sdram_dfi_p2_odt; +wire soc_sdram_dfi_p2_reset_n; +reg soc_sdram_dfi_p2_act_n = 1'd1; +wire [31:0] soc_sdram_dfi_p2_wrdata; +reg soc_sdram_dfi_p2_wrdata_en = 1'd0; +wire [3:0] soc_sdram_dfi_p2_wrdata_mask; +reg soc_sdram_dfi_p2_rddata_en = 1'd0; +wire [31:0] soc_sdram_dfi_p2_rddata; +wire soc_sdram_dfi_p2_rddata_valid; +reg [14:0] soc_sdram_dfi_p3_address = 15'd0; +reg [2:0] soc_sdram_dfi_p3_bank = 3'd0; +reg soc_sdram_dfi_p3_cas_n = 1'd1; +reg soc_sdram_dfi_p3_cs_n = 1'd1; +reg soc_sdram_dfi_p3_ras_n = 1'd1; +reg soc_sdram_dfi_p3_we_n = 1'd1; +wire soc_sdram_dfi_p3_cke; +wire soc_sdram_dfi_p3_odt; +wire soc_sdram_dfi_p3_reset_n; +reg soc_sdram_dfi_p3_act_n = 1'd1; +wire [31:0] soc_sdram_dfi_p3_wrdata; +reg soc_sdram_dfi_p3_wrdata_en = 1'd0; +wire [3:0] soc_sdram_dfi_p3_wrdata_mask; +reg soc_sdram_dfi_p3_rddata_en = 1'd0; +wire [31:0] soc_sdram_dfi_p3_rddata; +wire soc_sdram_dfi_p3_rddata_valid; +reg soc_sdram_cmd_valid = 1'd0; +reg soc_sdram_cmd_ready = 1'd0; +reg soc_sdram_cmd_last = 1'd0; +reg [14:0] soc_sdram_cmd_payload_a = 15'd0; +reg [2:0] soc_sdram_cmd_payload_ba = 3'd0; +reg soc_sdram_cmd_payload_cas = 1'd0; +reg soc_sdram_cmd_payload_ras = 1'd0; +reg soc_sdram_cmd_payload_we = 1'd0; +reg soc_sdram_cmd_payload_is_read = 1'd0; +reg soc_sdram_cmd_payload_is_write = 1'd0; +wire soc_sdram_wants_refresh; +wire soc_sdram_wants_zqcs; +wire soc_sdram_timer_wait; +wire soc_sdram_timer_done0; +wire [9:0] soc_sdram_timer_count0; +wire soc_sdram_timer_done1; +reg [9:0] soc_sdram_timer_count1 = 10'd781; +wire soc_sdram_postponer_req_i; +reg soc_sdram_postponer_req_o = 1'd0; +reg soc_sdram_postponer_count = 1'd0; +reg soc_sdram_sequencer_start0 = 1'd0; +wire soc_sdram_sequencer_done0; +wire soc_sdram_sequencer_start1; +reg soc_sdram_sequencer_done1 = 1'd0; +reg [5:0] soc_sdram_sequencer_counter = 6'd0; +reg soc_sdram_sequencer_count = 1'd0; +wire soc_sdram_zqcs_timer_wait; +wire soc_sdram_zqcs_timer_done0; +wire [26:0] soc_sdram_zqcs_timer_count0; +wire soc_sdram_zqcs_timer_done1; +reg [26:0] soc_sdram_zqcs_timer_count1 = 27'd99999999; +reg soc_sdram_zqcs_executer_start = 1'd0; +reg soc_sdram_zqcs_executer_done = 1'd0; +reg [4:0] soc_sdram_zqcs_executer_counter = 5'd0; +wire soc_sdram_bankmachine0_req_valid; +wire soc_sdram_bankmachine0_req_ready; +wire soc_sdram_bankmachine0_req_we; +wire [21:0] soc_sdram_bankmachine0_req_addr; +wire soc_sdram_bankmachine0_req_lock; +reg soc_sdram_bankmachine0_req_wdata_ready = 1'd0; +reg soc_sdram_bankmachine0_req_rdata_valid = 1'd0; +wire soc_sdram_bankmachine0_refresh_req; +reg soc_sdram_bankmachine0_refresh_gnt = 1'd0; +reg soc_sdram_bankmachine0_cmd_valid = 1'd0; +reg soc_sdram_bankmachine0_cmd_ready = 1'd0; +reg [14:0] soc_sdram_bankmachine0_cmd_payload_a = 15'd0; +wire [2:0] soc_sdram_bankmachine0_cmd_payload_ba; +reg soc_sdram_bankmachine0_cmd_payload_cas = 1'd0; +reg soc_sdram_bankmachine0_cmd_payload_ras = 1'd0; +reg soc_sdram_bankmachine0_cmd_payload_we = 1'd0; +reg soc_sdram_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg soc_sdram_bankmachine0_cmd_payload_is_read = 1'd0; +reg soc_sdram_bankmachine0_cmd_payload_is_write = 1'd0; +reg soc_sdram_bankmachine0_auto_precharge = 1'd0; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready; +reg soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we; +wire [21:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +wire [24:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +wire [24:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +reg [4:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_level = 5'd0; +reg soc_sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we; +wire [24:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read; +wire [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr; +wire [24:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +wire soc_sdram_bankmachine0_cmd_buffer_sink_valid; +wire soc_sdram_bankmachine0_cmd_buffer_sink_ready; +wire soc_sdram_bankmachine0_cmd_buffer_sink_first; +wire soc_sdram_bankmachine0_cmd_buffer_sink_last; +wire soc_sdram_bankmachine0_cmd_buffer_sink_payload_we; +wire [21:0] soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr; +reg soc_sdram_bankmachine0_cmd_buffer_source_valid = 1'd0; +wire soc_sdram_bankmachine0_cmd_buffer_source_ready; +reg soc_sdram_bankmachine0_cmd_buffer_source_first = 1'd0; +reg soc_sdram_bankmachine0_cmd_buffer_source_last = 1'd0; +reg soc_sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] soc_sdram_bankmachine0_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] soc_sdram_bankmachine0_row = 15'd0; +reg soc_sdram_bankmachine0_row_opened = 1'd0; +wire soc_sdram_bankmachine0_row_hit; +reg soc_sdram_bankmachine0_row_open = 1'd0; +reg soc_sdram_bankmachine0_row_close = 1'd0; +reg soc_sdram_bankmachine0_row_col_n_addr_sel = 1'd0; +wire soc_sdram_bankmachine0_twtpcon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine0_twtpcon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine0_twtpcon_count = 3'd0; +wire soc_sdram_bankmachine0_trccon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine0_trccon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine0_trccon_count = 3'd0; +wire soc_sdram_bankmachine0_trascon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine0_trascon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine0_trascon_count = 3'd0; +wire soc_sdram_bankmachine1_req_valid; +wire soc_sdram_bankmachine1_req_ready; +wire soc_sdram_bankmachine1_req_we; +wire [21:0] soc_sdram_bankmachine1_req_addr; +wire soc_sdram_bankmachine1_req_lock; +reg soc_sdram_bankmachine1_req_wdata_ready = 1'd0; +reg soc_sdram_bankmachine1_req_rdata_valid = 1'd0; +wire soc_sdram_bankmachine1_refresh_req; +reg soc_sdram_bankmachine1_refresh_gnt = 1'd0; +reg soc_sdram_bankmachine1_cmd_valid = 1'd0; +reg soc_sdram_bankmachine1_cmd_ready = 1'd0; +reg [14:0] soc_sdram_bankmachine1_cmd_payload_a = 15'd0; +wire [2:0] soc_sdram_bankmachine1_cmd_payload_ba; +reg soc_sdram_bankmachine1_cmd_payload_cas = 1'd0; +reg soc_sdram_bankmachine1_cmd_payload_ras = 1'd0; +reg soc_sdram_bankmachine1_cmd_payload_we = 1'd0; +reg soc_sdram_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg soc_sdram_bankmachine1_cmd_payload_is_read = 1'd0; +reg soc_sdram_bankmachine1_cmd_payload_is_write = 1'd0; +reg soc_sdram_bankmachine1_auto_precharge = 1'd0; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready; +reg soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we; +wire [21:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +wire [24:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +wire [24:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +reg [4:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_level = 5'd0; +reg soc_sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we; +wire [24:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read; +wire [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr; +wire [24:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +wire soc_sdram_bankmachine1_cmd_buffer_sink_valid; +wire soc_sdram_bankmachine1_cmd_buffer_sink_ready; +wire soc_sdram_bankmachine1_cmd_buffer_sink_first; +wire soc_sdram_bankmachine1_cmd_buffer_sink_last; +wire soc_sdram_bankmachine1_cmd_buffer_sink_payload_we; +wire [21:0] soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr; +reg soc_sdram_bankmachine1_cmd_buffer_source_valid = 1'd0; +wire soc_sdram_bankmachine1_cmd_buffer_source_ready; +reg soc_sdram_bankmachine1_cmd_buffer_source_first = 1'd0; +reg soc_sdram_bankmachine1_cmd_buffer_source_last = 1'd0; +reg soc_sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] soc_sdram_bankmachine1_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] soc_sdram_bankmachine1_row = 15'd0; +reg soc_sdram_bankmachine1_row_opened = 1'd0; +wire soc_sdram_bankmachine1_row_hit; +reg soc_sdram_bankmachine1_row_open = 1'd0; +reg soc_sdram_bankmachine1_row_close = 1'd0; +reg soc_sdram_bankmachine1_row_col_n_addr_sel = 1'd0; +wire soc_sdram_bankmachine1_twtpcon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine1_twtpcon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine1_twtpcon_count = 3'd0; +wire soc_sdram_bankmachine1_trccon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine1_trccon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine1_trccon_count = 3'd0; +wire soc_sdram_bankmachine1_trascon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine1_trascon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine1_trascon_count = 3'd0; +wire soc_sdram_bankmachine2_req_valid; +wire soc_sdram_bankmachine2_req_ready; +wire soc_sdram_bankmachine2_req_we; +wire [21:0] soc_sdram_bankmachine2_req_addr; +wire soc_sdram_bankmachine2_req_lock; +reg soc_sdram_bankmachine2_req_wdata_ready = 1'd0; +reg soc_sdram_bankmachine2_req_rdata_valid = 1'd0; +wire soc_sdram_bankmachine2_refresh_req; +reg soc_sdram_bankmachine2_refresh_gnt = 1'd0; +reg soc_sdram_bankmachine2_cmd_valid = 1'd0; +reg soc_sdram_bankmachine2_cmd_ready = 1'd0; +reg [14:0] soc_sdram_bankmachine2_cmd_payload_a = 15'd0; +wire [2:0] soc_sdram_bankmachine2_cmd_payload_ba; +reg soc_sdram_bankmachine2_cmd_payload_cas = 1'd0; +reg soc_sdram_bankmachine2_cmd_payload_ras = 1'd0; +reg soc_sdram_bankmachine2_cmd_payload_we = 1'd0; +reg soc_sdram_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg soc_sdram_bankmachine2_cmd_payload_is_read = 1'd0; +reg soc_sdram_bankmachine2_cmd_payload_is_write = 1'd0; +reg soc_sdram_bankmachine2_auto_precharge = 1'd0; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready; +reg soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we; +wire [21:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +wire [24:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +wire [24:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +reg [4:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_level = 5'd0; +reg soc_sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we; +wire [24:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read; +wire [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr; +wire [24:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +wire soc_sdram_bankmachine2_cmd_buffer_sink_valid; +wire soc_sdram_bankmachine2_cmd_buffer_sink_ready; +wire soc_sdram_bankmachine2_cmd_buffer_sink_first; +wire soc_sdram_bankmachine2_cmd_buffer_sink_last; +wire soc_sdram_bankmachine2_cmd_buffer_sink_payload_we; +wire [21:0] soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr; +reg soc_sdram_bankmachine2_cmd_buffer_source_valid = 1'd0; +wire soc_sdram_bankmachine2_cmd_buffer_source_ready; +reg soc_sdram_bankmachine2_cmd_buffer_source_first = 1'd0; +reg soc_sdram_bankmachine2_cmd_buffer_source_last = 1'd0; +reg soc_sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] soc_sdram_bankmachine2_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] soc_sdram_bankmachine2_row = 15'd0; +reg soc_sdram_bankmachine2_row_opened = 1'd0; +wire soc_sdram_bankmachine2_row_hit; +reg soc_sdram_bankmachine2_row_open = 1'd0; +reg soc_sdram_bankmachine2_row_close = 1'd0; +reg soc_sdram_bankmachine2_row_col_n_addr_sel = 1'd0; +wire soc_sdram_bankmachine2_twtpcon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine2_twtpcon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine2_twtpcon_count = 3'd0; +wire soc_sdram_bankmachine2_trccon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine2_trccon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine2_trccon_count = 3'd0; +wire soc_sdram_bankmachine2_trascon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine2_trascon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine2_trascon_count = 3'd0; +wire soc_sdram_bankmachine3_req_valid; +wire soc_sdram_bankmachine3_req_ready; +wire soc_sdram_bankmachine3_req_we; +wire [21:0] soc_sdram_bankmachine3_req_addr; +wire soc_sdram_bankmachine3_req_lock; +reg soc_sdram_bankmachine3_req_wdata_ready = 1'd0; +reg soc_sdram_bankmachine3_req_rdata_valid = 1'd0; +wire soc_sdram_bankmachine3_refresh_req; +reg soc_sdram_bankmachine3_refresh_gnt = 1'd0; +reg soc_sdram_bankmachine3_cmd_valid = 1'd0; +reg soc_sdram_bankmachine3_cmd_ready = 1'd0; +reg [14:0] soc_sdram_bankmachine3_cmd_payload_a = 15'd0; +wire [2:0] soc_sdram_bankmachine3_cmd_payload_ba; +reg soc_sdram_bankmachine3_cmd_payload_cas = 1'd0; +reg soc_sdram_bankmachine3_cmd_payload_ras = 1'd0; +reg soc_sdram_bankmachine3_cmd_payload_we = 1'd0; +reg soc_sdram_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg soc_sdram_bankmachine3_cmd_payload_is_read = 1'd0; +reg soc_sdram_bankmachine3_cmd_payload_is_write = 1'd0; +reg soc_sdram_bankmachine3_auto_precharge = 1'd0; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready; +reg soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we; +wire [21:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +wire [24:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +wire [24:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +reg [4:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_level = 5'd0; +reg soc_sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we; +wire [24:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read; +wire [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr; +wire [24:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +wire soc_sdram_bankmachine3_cmd_buffer_sink_valid; +wire soc_sdram_bankmachine3_cmd_buffer_sink_ready; +wire soc_sdram_bankmachine3_cmd_buffer_sink_first; +wire soc_sdram_bankmachine3_cmd_buffer_sink_last; +wire soc_sdram_bankmachine3_cmd_buffer_sink_payload_we; +wire [21:0] soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr; +reg soc_sdram_bankmachine3_cmd_buffer_source_valid = 1'd0; +wire soc_sdram_bankmachine3_cmd_buffer_source_ready; +reg soc_sdram_bankmachine3_cmd_buffer_source_first = 1'd0; +reg soc_sdram_bankmachine3_cmd_buffer_source_last = 1'd0; +reg soc_sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] soc_sdram_bankmachine3_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] soc_sdram_bankmachine3_row = 15'd0; +reg soc_sdram_bankmachine3_row_opened = 1'd0; +wire soc_sdram_bankmachine3_row_hit; +reg soc_sdram_bankmachine3_row_open = 1'd0; +reg soc_sdram_bankmachine3_row_close = 1'd0; +reg soc_sdram_bankmachine3_row_col_n_addr_sel = 1'd0; +wire soc_sdram_bankmachine3_twtpcon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine3_twtpcon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine3_twtpcon_count = 3'd0; +wire soc_sdram_bankmachine3_trccon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine3_trccon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine3_trccon_count = 3'd0; +wire soc_sdram_bankmachine3_trascon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine3_trascon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine3_trascon_count = 3'd0; +wire soc_sdram_bankmachine4_req_valid; +wire soc_sdram_bankmachine4_req_ready; +wire soc_sdram_bankmachine4_req_we; +wire [21:0] soc_sdram_bankmachine4_req_addr; +wire soc_sdram_bankmachine4_req_lock; +reg soc_sdram_bankmachine4_req_wdata_ready = 1'd0; +reg soc_sdram_bankmachine4_req_rdata_valid = 1'd0; +wire soc_sdram_bankmachine4_refresh_req; +reg soc_sdram_bankmachine4_refresh_gnt = 1'd0; +reg soc_sdram_bankmachine4_cmd_valid = 1'd0; +reg soc_sdram_bankmachine4_cmd_ready = 1'd0; +reg [14:0] soc_sdram_bankmachine4_cmd_payload_a = 15'd0; +wire [2:0] soc_sdram_bankmachine4_cmd_payload_ba; +reg soc_sdram_bankmachine4_cmd_payload_cas = 1'd0; +reg soc_sdram_bankmachine4_cmd_payload_ras = 1'd0; +reg soc_sdram_bankmachine4_cmd_payload_we = 1'd0; +reg soc_sdram_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg soc_sdram_bankmachine4_cmd_payload_is_read = 1'd0; +reg soc_sdram_bankmachine4_cmd_payload_is_write = 1'd0; +reg soc_sdram_bankmachine4_auto_precharge = 1'd0; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready; +reg soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we; +wire [21:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +wire [24:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +wire [24:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +reg [4:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_level = 5'd0; +reg soc_sdram_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we; +wire [24:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read; +wire [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr; +wire [24:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +wire soc_sdram_bankmachine4_cmd_buffer_sink_valid; +wire soc_sdram_bankmachine4_cmd_buffer_sink_ready; +wire soc_sdram_bankmachine4_cmd_buffer_sink_first; +wire soc_sdram_bankmachine4_cmd_buffer_sink_last; +wire soc_sdram_bankmachine4_cmd_buffer_sink_payload_we; +wire [21:0] soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr; +reg soc_sdram_bankmachine4_cmd_buffer_source_valid = 1'd0; +wire soc_sdram_bankmachine4_cmd_buffer_source_ready; +reg soc_sdram_bankmachine4_cmd_buffer_source_first = 1'd0; +reg soc_sdram_bankmachine4_cmd_buffer_source_last = 1'd0; +reg soc_sdram_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] soc_sdram_bankmachine4_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] soc_sdram_bankmachine4_row = 15'd0; +reg soc_sdram_bankmachine4_row_opened = 1'd0; +wire soc_sdram_bankmachine4_row_hit; +reg soc_sdram_bankmachine4_row_open = 1'd0; +reg soc_sdram_bankmachine4_row_close = 1'd0; +reg soc_sdram_bankmachine4_row_col_n_addr_sel = 1'd0; +wire soc_sdram_bankmachine4_twtpcon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine4_twtpcon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine4_twtpcon_count = 3'd0; +wire soc_sdram_bankmachine4_trccon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine4_trccon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine4_trccon_count = 3'd0; +wire soc_sdram_bankmachine4_trascon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine4_trascon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine4_trascon_count = 3'd0; +wire soc_sdram_bankmachine5_req_valid; +wire soc_sdram_bankmachine5_req_ready; +wire soc_sdram_bankmachine5_req_we; +wire [21:0] soc_sdram_bankmachine5_req_addr; +wire soc_sdram_bankmachine5_req_lock; +reg soc_sdram_bankmachine5_req_wdata_ready = 1'd0; +reg soc_sdram_bankmachine5_req_rdata_valid = 1'd0; +wire soc_sdram_bankmachine5_refresh_req; +reg soc_sdram_bankmachine5_refresh_gnt = 1'd0; +reg soc_sdram_bankmachine5_cmd_valid = 1'd0; +reg soc_sdram_bankmachine5_cmd_ready = 1'd0; +reg [14:0] soc_sdram_bankmachine5_cmd_payload_a = 15'd0; +wire [2:0] soc_sdram_bankmachine5_cmd_payload_ba; +reg soc_sdram_bankmachine5_cmd_payload_cas = 1'd0; +reg soc_sdram_bankmachine5_cmd_payload_ras = 1'd0; +reg soc_sdram_bankmachine5_cmd_payload_we = 1'd0; +reg soc_sdram_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg soc_sdram_bankmachine5_cmd_payload_is_read = 1'd0; +reg soc_sdram_bankmachine5_cmd_payload_is_write = 1'd0; +reg soc_sdram_bankmachine5_auto_precharge = 1'd0; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready; +reg soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we; +wire [21:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +wire [24:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +wire [24:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +reg [4:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_level = 5'd0; +reg soc_sdram_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we; +wire [24:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read; +wire [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr; +wire [24:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +wire soc_sdram_bankmachine5_cmd_buffer_sink_valid; +wire soc_sdram_bankmachine5_cmd_buffer_sink_ready; +wire soc_sdram_bankmachine5_cmd_buffer_sink_first; +wire soc_sdram_bankmachine5_cmd_buffer_sink_last; +wire soc_sdram_bankmachine5_cmd_buffer_sink_payload_we; +wire [21:0] soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr; +reg soc_sdram_bankmachine5_cmd_buffer_source_valid = 1'd0; +wire soc_sdram_bankmachine5_cmd_buffer_source_ready; +reg soc_sdram_bankmachine5_cmd_buffer_source_first = 1'd0; +reg soc_sdram_bankmachine5_cmd_buffer_source_last = 1'd0; +reg soc_sdram_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] soc_sdram_bankmachine5_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] soc_sdram_bankmachine5_row = 15'd0; +reg soc_sdram_bankmachine5_row_opened = 1'd0; +wire soc_sdram_bankmachine5_row_hit; +reg soc_sdram_bankmachine5_row_open = 1'd0; +reg soc_sdram_bankmachine5_row_close = 1'd0; +reg soc_sdram_bankmachine5_row_col_n_addr_sel = 1'd0; +wire soc_sdram_bankmachine5_twtpcon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine5_twtpcon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine5_twtpcon_count = 3'd0; +wire soc_sdram_bankmachine5_trccon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine5_trccon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine5_trccon_count = 3'd0; +wire soc_sdram_bankmachine5_trascon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine5_trascon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine5_trascon_count = 3'd0; +wire soc_sdram_bankmachine6_req_valid; +wire soc_sdram_bankmachine6_req_ready; +wire soc_sdram_bankmachine6_req_we; +wire [21:0] soc_sdram_bankmachine6_req_addr; +wire soc_sdram_bankmachine6_req_lock; +reg soc_sdram_bankmachine6_req_wdata_ready = 1'd0; +reg soc_sdram_bankmachine6_req_rdata_valid = 1'd0; +wire soc_sdram_bankmachine6_refresh_req; +reg soc_sdram_bankmachine6_refresh_gnt = 1'd0; +reg soc_sdram_bankmachine6_cmd_valid = 1'd0; +reg soc_sdram_bankmachine6_cmd_ready = 1'd0; +reg [14:0] soc_sdram_bankmachine6_cmd_payload_a = 15'd0; +wire [2:0] soc_sdram_bankmachine6_cmd_payload_ba; +reg soc_sdram_bankmachine6_cmd_payload_cas = 1'd0; +reg soc_sdram_bankmachine6_cmd_payload_ras = 1'd0; +reg soc_sdram_bankmachine6_cmd_payload_we = 1'd0; +reg soc_sdram_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg soc_sdram_bankmachine6_cmd_payload_is_read = 1'd0; +reg soc_sdram_bankmachine6_cmd_payload_is_write = 1'd0; +reg soc_sdram_bankmachine6_auto_precharge = 1'd0; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready; +reg soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we; +wire [21:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +wire [24:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +wire [24:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +reg [4:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_level = 5'd0; +reg soc_sdram_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we; +wire [24:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read; +wire [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr; +wire [24:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +wire soc_sdram_bankmachine6_cmd_buffer_sink_valid; +wire soc_sdram_bankmachine6_cmd_buffer_sink_ready; +wire soc_sdram_bankmachine6_cmd_buffer_sink_first; +wire soc_sdram_bankmachine6_cmd_buffer_sink_last; +wire soc_sdram_bankmachine6_cmd_buffer_sink_payload_we; +wire [21:0] soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr; +reg soc_sdram_bankmachine6_cmd_buffer_source_valid = 1'd0; +wire soc_sdram_bankmachine6_cmd_buffer_source_ready; +reg soc_sdram_bankmachine6_cmd_buffer_source_first = 1'd0; +reg soc_sdram_bankmachine6_cmd_buffer_source_last = 1'd0; +reg soc_sdram_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] soc_sdram_bankmachine6_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] soc_sdram_bankmachine6_row = 15'd0; +reg soc_sdram_bankmachine6_row_opened = 1'd0; +wire soc_sdram_bankmachine6_row_hit; +reg soc_sdram_bankmachine6_row_open = 1'd0; +reg soc_sdram_bankmachine6_row_close = 1'd0; +reg soc_sdram_bankmachine6_row_col_n_addr_sel = 1'd0; +wire soc_sdram_bankmachine6_twtpcon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine6_twtpcon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine6_twtpcon_count = 3'd0; +wire soc_sdram_bankmachine6_trccon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine6_trccon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine6_trccon_count = 3'd0; +wire soc_sdram_bankmachine6_trascon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine6_trascon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine6_trascon_count = 3'd0; +wire soc_sdram_bankmachine7_req_valid; +wire soc_sdram_bankmachine7_req_ready; +wire soc_sdram_bankmachine7_req_we; +wire [21:0] soc_sdram_bankmachine7_req_addr; +wire soc_sdram_bankmachine7_req_lock; +reg soc_sdram_bankmachine7_req_wdata_ready = 1'd0; +reg soc_sdram_bankmachine7_req_rdata_valid = 1'd0; +wire soc_sdram_bankmachine7_refresh_req; +reg soc_sdram_bankmachine7_refresh_gnt = 1'd0; +reg soc_sdram_bankmachine7_cmd_valid = 1'd0; +reg soc_sdram_bankmachine7_cmd_ready = 1'd0; +reg [14:0] soc_sdram_bankmachine7_cmd_payload_a = 15'd0; +wire [2:0] soc_sdram_bankmachine7_cmd_payload_ba; +reg soc_sdram_bankmachine7_cmd_payload_cas = 1'd0; +reg soc_sdram_bankmachine7_cmd_payload_ras = 1'd0; +reg soc_sdram_bankmachine7_cmd_payload_we = 1'd0; +reg soc_sdram_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg soc_sdram_bankmachine7_cmd_payload_is_read = 1'd0; +reg soc_sdram_bankmachine7_cmd_payload_is_write = 1'd0; +reg soc_sdram_bankmachine7_auto_precharge = 1'd0; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready; +reg soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we; +wire [21:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +wire [24:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +wire [24:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +reg [4:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_level = 5'd0; +reg soc_sdram_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we; +wire [24:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read; +wire [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr; +wire [24:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +wire soc_sdram_bankmachine7_cmd_buffer_sink_valid; +wire soc_sdram_bankmachine7_cmd_buffer_sink_ready; +wire soc_sdram_bankmachine7_cmd_buffer_sink_first; +wire soc_sdram_bankmachine7_cmd_buffer_sink_last; +wire soc_sdram_bankmachine7_cmd_buffer_sink_payload_we; +wire [21:0] soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr; +reg soc_sdram_bankmachine7_cmd_buffer_source_valid = 1'd0; +wire soc_sdram_bankmachine7_cmd_buffer_source_ready; +reg soc_sdram_bankmachine7_cmd_buffer_source_first = 1'd0; +reg soc_sdram_bankmachine7_cmd_buffer_source_last = 1'd0; +reg soc_sdram_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] soc_sdram_bankmachine7_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] soc_sdram_bankmachine7_row = 15'd0; +reg soc_sdram_bankmachine7_row_opened = 1'd0; +wire soc_sdram_bankmachine7_row_hit; +reg soc_sdram_bankmachine7_row_open = 1'd0; +reg soc_sdram_bankmachine7_row_close = 1'd0; +reg soc_sdram_bankmachine7_row_col_n_addr_sel = 1'd0; +wire soc_sdram_bankmachine7_twtpcon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine7_twtpcon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine7_twtpcon_count = 3'd0; +wire soc_sdram_bankmachine7_trccon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine7_trccon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine7_trccon_count = 3'd0; +wire soc_sdram_bankmachine7_trascon_valid; +(* dont_touch = "true" *) reg soc_sdram_bankmachine7_trascon_ready = 1'd1; +reg [2:0] soc_sdram_bankmachine7_trascon_count = 3'd0; +wire soc_sdram_ras_allowed; +wire soc_sdram_cas_allowed; +reg soc_sdram_choose_cmd_want_reads = 1'd0; +reg soc_sdram_choose_cmd_want_writes = 1'd0; +reg soc_sdram_choose_cmd_want_cmds = 1'd0; +reg soc_sdram_choose_cmd_want_activates = 1'd0; +wire soc_sdram_choose_cmd_cmd_valid; +reg soc_sdram_choose_cmd_cmd_ready = 1'd0; +wire [14:0] soc_sdram_choose_cmd_cmd_payload_a; +wire [2:0] soc_sdram_choose_cmd_cmd_payload_ba; +reg soc_sdram_choose_cmd_cmd_payload_cas = 1'd0; +reg soc_sdram_choose_cmd_cmd_payload_ras = 1'd0; +reg soc_sdram_choose_cmd_cmd_payload_we = 1'd0; +wire soc_sdram_choose_cmd_cmd_payload_is_cmd; +wire soc_sdram_choose_cmd_cmd_payload_is_read; +wire soc_sdram_choose_cmd_cmd_payload_is_write; +reg [7:0] soc_sdram_choose_cmd_valids = 8'd0; +wire [7:0] soc_sdram_choose_cmd_request; +reg [2:0] soc_sdram_choose_cmd_grant = 3'd0; +wire soc_sdram_choose_cmd_ce; +reg soc_sdram_choose_req_want_reads = 1'd0; +reg soc_sdram_choose_req_want_writes = 1'd0; +reg soc_sdram_choose_req_want_cmds = 1'd0; +reg soc_sdram_choose_req_want_activates = 1'd0; +wire soc_sdram_choose_req_cmd_valid; +reg soc_sdram_choose_req_cmd_ready = 1'd0; +wire [14:0] soc_sdram_choose_req_cmd_payload_a; +wire [2:0] soc_sdram_choose_req_cmd_payload_ba; +reg soc_sdram_choose_req_cmd_payload_cas = 1'd0; +reg soc_sdram_choose_req_cmd_payload_ras = 1'd0; +reg soc_sdram_choose_req_cmd_payload_we = 1'd0; +wire soc_sdram_choose_req_cmd_payload_is_cmd; +wire soc_sdram_choose_req_cmd_payload_is_read; +wire soc_sdram_choose_req_cmd_payload_is_write; +reg [7:0] soc_sdram_choose_req_valids = 8'd0; +wire [7:0] soc_sdram_choose_req_request; +reg [2:0] soc_sdram_choose_req_grant = 3'd0; +wire soc_sdram_choose_req_ce; +reg [14:0] soc_sdram_nop_a = 15'd0; +reg [2:0] soc_sdram_nop_ba = 3'd0; +reg [1:0] soc_sdram_steerer_sel0 = 2'd0; +reg [1:0] soc_sdram_steerer_sel1 = 2'd0; +reg [1:0] soc_sdram_steerer_sel2 = 2'd0; +reg [1:0] soc_sdram_steerer_sel3 = 2'd0; +reg soc_sdram_steerer0 = 1'd1; +reg soc_sdram_steerer1 = 1'd1; +reg soc_sdram_steerer2 = 1'd1; +reg soc_sdram_steerer3 = 1'd1; +reg soc_sdram_steerer4 = 1'd1; +reg soc_sdram_steerer5 = 1'd1; +reg soc_sdram_steerer6 = 1'd1; +reg soc_sdram_steerer7 = 1'd1; +wire soc_sdram_trrdcon_valid; +(* dont_touch = "true" *) reg soc_sdram_trrdcon_ready = 1'd1; +reg soc_sdram_trrdcon_count = 1'd0; +wire soc_sdram_tfawcon_valid; +(* dont_touch = "true" *) reg soc_sdram_tfawcon_ready = 1'd1; +wire [2:0] soc_sdram_tfawcon_count; +reg [4:0] soc_sdram_tfawcon_window = 5'd0; +wire soc_sdram_tccdcon_valid; +(* dont_touch = "true" *) reg soc_sdram_tccdcon_ready = 1'd1; +reg soc_sdram_tccdcon_count = 1'd0; +wire soc_sdram_twtrcon_valid; +(* dont_touch = "true" *) reg soc_sdram_twtrcon_ready = 1'd1; +reg [2:0] soc_sdram_twtrcon_count = 3'd0; +wire soc_sdram_read_available; +wire soc_sdram_write_available; +reg soc_sdram_en0 = 1'd0; +wire soc_sdram_max_time0; +reg [4:0] soc_sdram_time0 = 5'd0; +reg soc_sdram_en1 = 1'd0; +wire soc_sdram_max_time1; +reg [3:0] soc_sdram_time1 = 4'd0; +wire soc_sdram_go_to_refresh; +reg soc_port_cmd_valid = 1'd0; +wire soc_port_cmd_ready; +reg soc_port_cmd_payload_we = 1'd0; +reg [24:0] soc_port_cmd_payload_addr = 25'd0; +wire soc_port_wdata_valid; +wire soc_port_wdata_ready; +wire soc_port_wdata_first; +wire soc_port_wdata_last; +wire [127:0] soc_port_wdata_payload_data; +wire [15:0] soc_port_wdata_payload_we; +wire soc_port_rdata_valid; +wire soc_port_rdata_ready; +reg soc_port_rdata_first = 1'd0; +reg soc_port_rdata_last = 1'd0; +wire [127:0] soc_port_rdata_payload_data; +wire [29:0] soc_wb_sdram_adr; +wire [31:0] soc_wb_sdram_dat_w; +reg [31:0] soc_wb_sdram_dat_r = 32'd0; +wire [3:0] soc_wb_sdram_sel; +wire soc_wb_sdram_cyc; +wire soc_wb_sdram_stb; +reg soc_wb_sdram_ack = 1'd0; +wire soc_wb_sdram_we; +wire [2:0] soc_wb_sdram_cti; +wire [1:0] soc_wb_sdram_bte; +reg soc_wb_sdram_err = 1'd0; +wire [29:0] soc_litedram_wb_adr; +reg [127:0] soc_litedram_wb_dat_w = 128'd0; +wire [127:0] soc_litedram_wb_dat_r; +reg [15:0] soc_litedram_wb_sel = 16'd0; +reg soc_litedram_wb_cyc = 1'd0; +reg soc_litedram_wb_stb = 1'd0; +reg soc_litedram_wb_ack = 1'd0; +reg soc_litedram_wb_we = 1'd0; +wire [2:0] soc_litedram_wb_cti; +reg soc_write = 1'd0; +reg soc_evict = 1'd0; +reg soc_refill = 1'd0; +reg soc_read = 1'd0; +wire [29:0] soc_address_d; +reg [29:0] soc_address_q = 30'd0; +reg soc_address_ce = 1'd0; +reg soc_address_reset = 1'd0; +reg [1:0] soc_counter = 2'd0; +reg soc_counter_ce = 1'd0; +reg soc_counter_reset = 1'd0; +wire [1:0] soc_counter_offset; +wire soc_counter_done; +wire [127:0] soc_cached_data; +wire [15:0] soc_cached_sel; +wire soc_end_of_burst; +wire soc_need_refill_d; +reg soc_need_refill_q = 1'd1; +reg soc_need_refill_ce = 1'd0; +wire soc_need_refill_reset; +reg [31:0] soc_cached_datas_flipflop0_d = 32'd0; +reg [31:0] soc_cached_datas_flipflop0_q = 32'd0; +reg soc_cached_datas_ce0 = 1'd0; +reg soc_cached_datas_reset0 = 1'd0; +reg [31:0] soc_cached_datas_flipflop1_d = 32'd0; +reg [31:0] soc_cached_datas_flipflop1_q = 32'd0; +reg soc_cached_datas_ce1 = 1'd0; +reg soc_cached_datas_reset1 = 1'd0; +reg [31:0] soc_cached_datas_flipflop2_d = 32'd0; +reg [31:0] soc_cached_datas_flipflop2_q = 32'd0; +reg soc_cached_datas_ce2 = 1'd0; +reg soc_cached_datas_reset2 = 1'd0; +reg [31:0] soc_cached_datas_flipflop3_d = 32'd0; +reg [31:0] soc_cached_datas_flipflop3_q = 32'd0; +reg soc_cached_datas_ce3 = 1'd0; +reg soc_cached_datas_reset3 = 1'd0; +wire [3:0] soc_cached_sels_flipflop0_d; +reg [3:0] soc_cached_sels_flipflop0_q = 4'd0; +reg soc_cached_sels_ce0 = 1'd0; +wire soc_cached_sels_reset0; +wire [3:0] soc_cached_sels_flipflop1_d; +reg [3:0] soc_cached_sels_flipflop1_q = 4'd0; +reg soc_cached_sels_ce1 = 1'd0; +wire soc_cached_sels_reset1; +wire [3:0] soc_cached_sels_flipflop2_d; +reg [3:0] soc_cached_sels_flipflop2_q = 4'd0; +reg soc_cached_sels_ce2 = 1'd0; +wire soc_cached_sels_reset2; +wire [3:0] soc_cached_sels_flipflop3_d; +reg [3:0] soc_cached_sels_flipflop3_q = 4'd0; +reg soc_cached_sels_ce3 = 1'd0; +wire soc_cached_sels_reset3; +reg soc_write_sel0 = 1'd0; +reg soc_write_sel1 = 1'd0; +reg soc_write_sel2 = 1'd0; +reg soc_write_sel3 = 1'd0; +wire soc_wdata_converter_sink_valid; +wire soc_wdata_converter_sink_ready; +reg soc_wdata_converter_sink_first = 1'd0; +reg soc_wdata_converter_sink_last = 1'd0; +wire [127:0] soc_wdata_converter_sink_payload_data; +wire [15:0] soc_wdata_converter_sink_payload_we; +wire soc_wdata_converter_source_valid; +wire soc_wdata_converter_source_ready; +wire soc_wdata_converter_source_first; +wire soc_wdata_converter_source_last; +wire [127:0] soc_wdata_converter_source_payload_data; +wire [15:0] soc_wdata_converter_source_payload_we; +wire soc_wdata_converter_converter_sink_valid; +wire soc_wdata_converter_converter_sink_ready; +wire soc_wdata_converter_converter_sink_first; +wire soc_wdata_converter_converter_sink_last; +wire [143:0] soc_wdata_converter_converter_sink_payload_data; +wire soc_wdata_converter_converter_source_valid; +wire soc_wdata_converter_converter_source_ready; +wire soc_wdata_converter_converter_source_first; +wire soc_wdata_converter_converter_source_last; +wire [143:0] soc_wdata_converter_converter_source_payload_data; +wire soc_wdata_converter_converter_source_payload_valid_token_count; +wire soc_wdata_converter_source_source_valid; +wire soc_wdata_converter_source_source_ready; +wire soc_wdata_converter_source_source_first; +wire soc_wdata_converter_source_source_last; +wire [143:0] soc_wdata_converter_source_source_payload_data; +wire soc_rdata_converter_sink_valid; +wire soc_rdata_converter_sink_ready; +wire soc_rdata_converter_sink_first; +wire soc_rdata_converter_sink_last; +wire [127:0] soc_rdata_converter_sink_payload_data; +wire soc_rdata_converter_source_valid; +wire soc_rdata_converter_source_ready; +wire soc_rdata_converter_source_first; +wire soc_rdata_converter_source_last; +wire [127:0] soc_rdata_converter_source_payload_data; +wire soc_rdata_converter_converter_sink_valid; +wire soc_rdata_converter_converter_sink_ready; +wire soc_rdata_converter_converter_sink_first; +wire soc_rdata_converter_converter_sink_last; +wire [127:0] soc_rdata_converter_converter_sink_payload_data; +wire soc_rdata_converter_converter_source_valid; +wire soc_rdata_converter_converter_source_ready; +wire soc_rdata_converter_converter_source_first; +wire soc_rdata_converter_converter_source_last; +wire [127:0] soc_rdata_converter_converter_source_payload_data; +wire soc_rdata_converter_converter_source_payload_valid_token_count; +wire soc_rdata_converter_source_source_valid; +wire soc_rdata_converter_source_source_ready; +wire soc_rdata_converter_source_source_first; +wire soc_rdata_converter_source_source_last; +wire [127:0] soc_rdata_converter_source_source_payload_data; +reg soc_count = 1'd0; +reg soc_init_done_storage = 1'd0; +reg soc_init_done_re = 1'd0; +reg soc_init_error_storage = 1'd0; +reg soc_init_error_re = 1'd0; +wire soc_cmd_valid; +wire soc_cmd_ready; +wire soc_cmd_payload_we; +wire [24:0] soc_cmd_payload_addr; +wire soc_wdata_valid; +wire soc_wdata_ready; +wire [127:0] soc_wdata_payload_data; +wire [15:0] soc_wdata_payload_we; +wire soc_rdata_valid; +wire soc_rdata_ready; +wire [127:0] soc_rdata_payload_data; +reg vns_wb2csr_state = 1'd0; +reg vns_wb2csr_next_state = 1'd0; +wire vns_pll_fb0; +wire vns_pll_fb1; +reg [1:0] vns_refresher_state = 2'd0; +reg [1:0] vns_refresher_next_state = 2'd0; +reg [3:0] vns_bankmachine0_state = 4'd0; +reg [3:0] vns_bankmachine0_next_state = 4'd0; +reg [3:0] vns_bankmachine1_state = 4'd0; +reg [3:0] vns_bankmachine1_next_state = 4'd0; +reg [3:0] vns_bankmachine2_state = 4'd0; +reg [3:0] vns_bankmachine2_next_state = 4'd0; +reg [3:0] vns_bankmachine3_state = 4'd0; +reg [3:0] vns_bankmachine3_next_state = 4'd0; +reg [3:0] vns_bankmachine4_state = 4'd0; +reg [3:0] vns_bankmachine4_next_state = 4'd0; +reg [3:0] vns_bankmachine5_state = 4'd0; +reg [3:0] vns_bankmachine5_next_state = 4'd0; +reg [3:0] vns_bankmachine6_state = 4'd0; +reg [3:0] vns_bankmachine6_next_state = 4'd0; +reg [3:0] vns_bankmachine7_state = 4'd0; +reg [3:0] vns_bankmachine7_next_state = 4'd0; +reg [3:0] vns_multiplexer_state = 4'd0; +reg [3:0] vns_multiplexer_next_state = 4'd0; +wire [1:0] vns_roundrobin0_request; +reg vns_roundrobin0_grant = 1'd0; +wire vns_roundrobin0_ce; +wire [1:0] vns_roundrobin1_request; +reg vns_roundrobin1_grant = 1'd0; +wire vns_roundrobin1_ce; +wire [1:0] vns_roundrobin2_request; +reg vns_roundrobin2_grant = 1'd0; +wire vns_roundrobin2_ce; +wire [1:0] vns_roundrobin3_request; +reg vns_roundrobin3_grant = 1'd0; +wire vns_roundrobin3_ce; +wire [1:0] vns_roundrobin4_request; +reg vns_roundrobin4_grant = 1'd0; +wire vns_roundrobin4_ce; +wire [1:0] vns_roundrobin5_request; +reg vns_roundrobin5_grant = 1'd0; +wire vns_roundrobin5_ce; +wire [1:0] vns_roundrobin6_request; +reg vns_roundrobin6_grant = 1'd0; +wire vns_roundrobin6_ce; +wire [1:0] vns_roundrobin7_request; +reg vns_roundrobin7_grant = 1'd0; +wire vns_roundrobin7_ce; +reg vns_locked0 = 1'd0; +reg vns_locked1 = 1'd0; +reg vns_locked2 = 1'd0; +reg vns_locked3 = 1'd0; +reg vns_locked4 = 1'd0; +reg vns_locked5 = 1'd0; +reg vns_locked6 = 1'd0; +reg vns_locked7 = 1'd0; +reg vns_locked8 = 1'd0; +reg vns_locked9 = 1'd0; +reg vns_locked10 = 1'd0; +reg vns_locked11 = 1'd0; +reg vns_locked12 = 1'd0; +reg vns_locked13 = 1'd0; +reg vns_locked14 = 1'd0; +reg vns_locked15 = 1'd0; +reg vns_new_master_wdata_ready0 = 1'd0; +reg vns_new_master_wdata_ready1 = 1'd0; +reg vns_new_master_wdata_ready2 = 1'd0; +reg vns_new_master_wdata_ready3 = 1'd0; +reg vns_new_master_wdata_ready4 = 1'd0; +reg vns_new_master_wdata_ready5 = 1'd0; +reg vns_new_master_rdata_valid0 = 1'd0; +reg vns_new_master_rdata_valid1 = 1'd0; +reg vns_new_master_rdata_valid2 = 1'd0; +reg vns_new_master_rdata_valid3 = 1'd0; +reg vns_new_master_rdata_valid4 = 1'd0; +reg vns_new_master_rdata_valid5 = 1'd0; +reg vns_new_master_rdata_valid6 = 1'd0; +reg vns_new_master_rdata_valid7 = 1'd0; +reg vns_new_master_rdata_valid8 = 1'd0; +reg vns_new_master_rdata_valid9 = 1'd0; +reg vns_new_master_rdata_valid10 = 1'd0; +reg vns_new_master_rdata_valid11 = 1'd0; +reg vns_new_master_rdata_valid12 = 1'd0; +reg vns_new_master_rdata_valid13 = 1'd0; +reg vns_new_master_rdata_valid14 = 1'd0; +reg vns_new_master_rdata_valid15 = 1'd0; +reg vns_new_master_rdata_valid16 = 1'd0; +reg vns_new_master_rdata_valid17 = 1'd0; +reg [2:0] vns_converter_state = 3'd0; +reg [2:0] vns_converter_next_state = 3'd0; +reg [1:0] vns_litedramwishbone2native_state = 2'd0; +reg [1:0] vns_litedramwishbone2native_next_state = 2'd0; +reg soc_count_next_value = 1'd0; +reg soc_count_next_value_ce = 1'd0; +wire [29:0] vns_shared_adr; +wire [31:0] vns_shared_dat_w; +reg [31:0] vns_shared_dat_r = 32'd0; +wire [3:0] vns_shared_sel; +wire vns_shared_cyc; +wire vns_shared_stb; +reg vns_shared_ack = 1'd0; +wire vns_shared_we; +wire [2:0] vns_shared_cti; +wire [1:0] vns_shared_bte; +wire vns_shared_err; +wire [1:0] vns_request; +reg vns_grant = 1'd0; +reg [3:0] vns_slave_sel = 4'd0; +reg [3:0] vns_slave_sel_r = 4'd0; +reg vns_error = 1'd0; +wire vns_wait; +wire vns_done; +reg [19:0] vns_count = 20'd1000000; +wire [13:0] vns_interface0_bank_bus_adr; +wire vns_interface0_bank_bus_we; +wire [7:0] vns_interface0_bank_bus_dat_w; +reg [7:0] vns_interface0_bank_bus_dat_r = 8'd0; +wire vns_csrbank0_reset0_re; +wire vns_csrbank0_reset0_r; +wire vns_csrbank0_reset0_we; +wire vns_csrbank0_reset0_w; +wire vns_csrbank0_scratch3_re; +wire [7:0] vns_csrbank0_scratch3_r; +wire vns_csrbank0_scratch3_we; +wire [7:0] vns_csrbank0_scratch3_w; +wire vns_csrbank0_scratch2_re; +wire [7:0] vns_csrbank0_scratch2_r; +wire vns_csrbank0_scratch2_we; +wire [7:0] vns_csrbank0_scratch2_w; +wire vns_csrbank0_scratch1_re; +wire [7:0] vns_csrbank0_scratch1_r; +wire vns_csrbank0_scratch1_we; +wire [7:0] vns_csrbank0_scratch1_w; +wire vns_csrbank0_scratch0_re; +wire [7:0] vns_csrbank0_scratch0_r; +wire vns_csrbank0_scratch0_we; +wire [7:0] vns_csrbank0_scratch0_w; +wire vns_csrbank0_bus_errors3_re; +wire [7:0] vns_csrbank0_bus_errors3_r; +wire vns_csrbank0_bus_errors3_we; +wire [7:0] vns_csrbank0_bus_errors3_w; +wire vns_csrbank0_bus_errors2_re; +wire [7:0] vns_csrbank0_bus_errors2_r; +wire vns_csrbank0_bus_errors2_we; +wire [7:0] vns_csrbank0_bus_errors2_w; +wire vns_csrbank0_bus_errors1_re; +wire [7:0] vns_csrbank0_bus_errors1_r; +wire vns_csrbank0_bus_errors1_we; +wire [7:0] vns_csrbank0_bus_errors1_w; +wire vns_csrbank0_bus_errors0_re; +wire [7:0] vns_csrbank0_bus_errors0_r; +wire vns_csrbank0_bus_errors0_we; +wire [7:0] vns_csrbank0_bus_errors0_w; +wire vns_csrbank0_sel; +wire [13:0] vns_interface1_bank_bus_adr; +wire vns_interface1_bank_bus_we; +wire [7:0] vns_interface1_bank_bus_dat_w; +reg [7:0] vns_interface1_bank_bus_dat_r = 8'd0; +wire vns_csrbank1_init_done0_re; +wire vns_csrbank1_init_done0_r; +wire vns_csrbank1_init_done0_we; +wire vns_csrbank1_init_done0_w; +wire vns_csrbank1_init_error0_re; +wire vns_csrbank1_init_error0_r; +wire vns_csrbank1_init_error0_we; +wire vns_csrbank1_init_error0_w; +wire vns_csrbank1_sel; +wire [13:0] vns_interface2_bank_bus_adr; +wire vns_interface2_bank_bus_we; +wire [7:0] vns_interface2_bank_bus_dat_w; +reg [7:0] vns_interface2_bank_bus_dat_r = 8'd0; +wire vns_csrbank2_half_sys8x_taps0_re; +wire [4:0] vns_csrbank2_half_sys8x_taps0_r; +wire vns_csrbank2_half_sys8x_taps0_we; +wire [4:0] vns_csrbank2_half_sys8x_taps0_w; +wire vns_csrbank2_wlevel_en0_re; +wire vns_csrbank2_wlevel_en0_r; +wire vns_csrbank2_wlevel_en0_we; +wire vns_csrbank2_wlevel_en0_w; +wire vns_csrbank2_dly_sel0_re; +wire [1:0] vns_csrbank2_dly_sel0_r; +wire vns_csrbank2_dly_sel0_we; +wire [1:0] vns_csrbank2_dly_sel0_w; +wire vns_csrbank2_sel; +wire [13:0] vns_interface3_bank_bus_adr; +wire vns_interface3_bank_bus_we; +wire [7:0] vns_interface3_bank_bus_dat_w; +reg [7:0] vns_interface3_bank_bus_dat_r = 8'd0; +wire vns_csrbank3_dfii_control0_re; +wire [3:0] vns_csrbank3_dfii_control0_r; +wire vns_csrbank3_dfii_control0_we; +wire [3:0] vns_csrbank3_dfii_control0_w; +wire vns_csrbank3_dfii_pi0_command0_re; +wire [5:0] vns_csrbank3_dfii_pi0_command0_r; +wire vns_csrbank3_dfii_pi0_command0_we; +wire [5:0] vns_csrbank3_dfii_pi0_command0_w; +wire vns_csrbank3_dfii_pi0_address1_re; +wire [6:0] vns_csrbank3_dfii_pi0_address1_r; +wire vns_csrbank3_dfii_pi0_address1_we; +wire [6:0] vns_csrbank3_dfii_pi0_address1_w; +wire vns_csrbank3_dfii_pi0_address0_re; +wire [7:0] vns_csrbank3_dfii_pi0_address0_r; +wire vns_csrbank3_dfii_pi0_address0_we; +wire [7:0] vns_csrbank3_dfii_pi0_address0_w; +wire vns_csrbank3_dfii_pi0_baddress0_re; +wire [2:0] vns_csrbank3_dfii_pi0_baddress0_r; +wire vns_csrbank3_dfii_pi0_baddress0_we; +wire [2:0] vns_csrbank3_dfii_pi0_baddress0_w; +wire vns_csrbank3_dfii_pi0_wrdata3_re; +wire [7:0] vns_csrbank3_dfii_pi0_wrdata3_r; +wire vns_csrbank3_dfii_pi0_wrdata3_we; +wire [7:0] vns_csrbank3_dfii_pi0_wrdata3_w; +wire vns_csrbank3_dfii_pi0_wrdata2_re; +wire [7:0] vns_csrbank3_dfii_pi0_wrdata2_r; +wire vns_csrbank3_dfii_pi0_wrdata2_we; +wire [7:0] vns_csrbank3_dfii_pi0_wrdata2_w; +wire vns_csrbank3_dfii_pi0_wrdata1_re; +wire [7:0] vns_csrbank3_dfii_pi0_wrdata1_r; +wire vns_csrbank3_dfii_pi0_wrdata1_we; +wire [7:0] vns_csrbank3_dfii_pi0_wrdata1_w; +wire vns_csrbank3_dfii_pi0_wrdata0_re; +wire [7:0] vns_csrbank3_dfii_pi0_wrdata0_r; +wire vns_csrbank3_dfii_pi0_wrdata0_we; +wire [7:0] vns_csrbank3_dfii_pi0_wrdata0_w; +wire vns_csrbank3_dfii_pi0_rddata3_re; +wire [7:0] vns_csrbank3_dfii_pi0_rddata3_r; +wire vns_csrbank3_dfii_pi0_rddata3_we; +wire [7:0] vns_csrbank3_dfii_pi0_rddata3_w; +wire vns_csrbank3_dfii_pi0_rddata2_re; +wire [7:0] vns_csrbank3_dfii_pi0_rddata2_r; +wire vns_csrbank3_dfii_pi0_rddata2_we; +wire [7:0] vns_csrbank3_dfii_pi0_rddata2_w; +wire vns_csrbank3_dfii_pi0_rddata1_re; +wire [7:0] vns_csrbank3_dfii_pi0_rddata1_r; +wire vns_csrbank3_dfii_pi0_rddata1_we; +wire [7:0] vns_csrbank3_dfii_pi0_rddata1_w; +wire vns_csrbank3_dfii_pi0_rddata0_re; +wire [7:0] vns_csrbank3_dfii_pi0_rddata0_r; +wire vns_csrbank3_dfii_pi0_rddata0_we; +wire [7:0] vns_csrbank3_dfii_pi0_rddata0_w; +wire vns_csrbank3_dfii_pi1_command0_re; +wire [5:0] vns_csrbank3_dfii_pi1_command0_r; +wire vns_csrbank3_dfii_pi1_command0_we; +wire [5:0] vns_csrbank3_dfii_pi1_command0_w; +wire vns_csrbank3_dfii_pi1_address1_re; +wire [6:0] vns_csrbank3_dfii_pi1_address1_r; +wire vns_csrbank3_dfii_pi1_address1_we; +wire [6:0] vns_csrbank3_dfii_pi1_address1_w; +wire vns_csrbank3_dfii_pi1_address0_re; +wire [7:0] vns_csrbank3_dfii_pi1_address0_r; +wire vns_csrbank3_dfii_pi1_address0_we; +wire [7:0] vns_csrbank3_dfii_pi1_address0_w; +wire vns_csrbank3_dfii_pi1_baddress0_re; +wire [2:0] vns_csrbank3_dfii_pi1_baddress0_r; +wire vns_csrbank3_dfii_pi1_baddress0_we; +wire [2:0] vns_csrbank3_dfii_pi1_baddress0_w; +wire vns_csrbank3_dfii_pi1_wrdata3_re; +wire [7:0] vns_csrbank3_dfii_pi1_wrdata3_r; +wire vns_csrbank3_dfii_pi1_wrdata3_we; +wire [7:0] vns_csrbank3_dfii_pi1_wrdata3_w; +wire vns_csrbank3_dfii_pi1_wrdata2_re; +wire [7:0] vns_csrbank3_dfii_pi1_wrdata2_r; +wire vns_csrbank3_dfii_pi1_wrdata2_we; +wire [7:0] vns_csrbank3_dfii_pi1_wrdata2_w; +wire vns_csrbank3_dfii_pi1_wrdata1_re; +wire [7:0] vns_csrbank3_dfii_pi1_wrdata1_r; +wire vns_csrbank3_dfii_pi1_wrdata1_we; +wire [7:0] vns_csrbank3_dfii_pi1_wrdata1_w; +wire vns_csrbank3_dfii_pi1_wrdata0_re; +wire [7:0] vns_csrbank3_dfii_pi1_wrdata0_r; +wire vns_csrbank3_dfii_pi1_wrdata0_we; +wire [7:0] vns_csrbank3_dfii_pi1_wrdata0_w; +wire vns_csrbank3_dfii_pi1_rddata3_re; +wire [7:0] vns_csrbank3_dfii_pi1_rddata3_r; +wire vns_csrbank3_dfii_pi1_rddata3_we; +wire [7:0] vns_csrbank3_dfii_pi1_rddata3_w; +wire vns_csrbank3_dfii_pi1_rddata2_re; +wire [7:0] vns_csrbank3_dfii_pi1_rddata2_r; +wire vns_csrbank3_dfii_pi1_rddata2_we; +wire [7:0] vns_csrbank3_dfii_pi1_rddata2_w; +wire vns_csrbank3_dfii_pi1_rddata1_re; +wire [7:0] vns_csrbank3_dfii_pi1_rddata1_r; +wire vns_csrbank3_dfii_pi1_rddata1_we; +wire [7:0] vns_csrbank3_dfii_pi1_rddata1_w; +wire vns_csrbank3_dfii_pi1_rddata0_re; +wire [7:0] vns_csrbank3_dfii_pi1_rddata0_r; +wire vns_csrbank3_dfii_pi1_rddata0_we; +wire [7:0] vns_csrbank3_dfii_pi1_rddata0_w; +wire vns_csrbank3_dfii_pi2_command0_re; +wire [5:0] vns_csrbank3_dfii_pi2_command0_r; +wire vns_csrbank3_dfii_pi2_command0_we; +wire [5:0] vns_csrbank3_dfii_pi2_command0_w; +wire vns_csrbank3_dfii_pi2_address1_re; +wire [6:0] vns_csrbank3_dfii_pi2_address1_r; +wire vns_csrbank3_dfii_pi2_address1_we; +wire [6:0] vns_csrbank3_dfii_pi2_address1_w; +wire vns_csrbank3_dfii_pi2_address0_re; +wire [7:0] vns_csrbank3_dfii_pi2_address0_r; +wire vns_csrbank3_dfii_pi2_address0_we; +wire [7:0] vns_csrbank3_dfii_pi2_address0_w; +wire vns_csrbank3_dfii_pi2_baddress0_re; +wire [2:0] vns_csrbank3_dfii_pi2_baddress0_r; +wire vns_csrbank3_dfii_pi2_baddress0_we; +wire [2:0] vns_csrbank3_dfii_pi2_baddress0_w; +wire vns_csrbank3_dfii_pi2_wrdata3_re; +wire [7:0] vns_csrbank3_dfii_pi2_wrdata3_r; +wire vns_csrbank3_dfii_pi2_wrdata3_we; +wire [7:0] vns_csrbank3_dfii_pi2_wrdata3_w; +wire vns_csrbank3_dfii_pi2_wrdata2_re; +wire [7:0] vns_csrbank3_dfii_pi2_wrdata2_r; +wire vns_csrbank3_dfii_pi2_wrdata2_we; +wire [7:0] vns_csrbank3_dfii_pi2_wrdata2_w; +wire vns_csrbank3_dfii_pi2_wrdata1_re; +wire [7:0] vns_csrbank3_dfii_pi2_wrdata1_r; +wire vns_csrbank3_dfii_pi2_wrdata1_we; +wire [7:0] vns_csrbank3_dfii_pi2_wrdata1_w; +wire vns_csrbank3_dfii_pi2_wrdata0_re; +wire [7:0] vns_csrbank3_dfii_pi2_wrdata0_r; +wire vns_csrbank3_dfii_pi2_wrdata0_we; +wire [7:0] vns_csrbank3_dfii_pi2_wrdata0_w; +wire vns_csrbank3_dfii_pi2_rddata3_re; +wire [7:0] vns_csrbank3_dfii_pi2_rddata3_r; +wire vns_csrbank3_dfii_pi2_rddata3_we; +wire [7:0] vns_csrbank3_dfii_pi2_rddata3_w; +wire vns_csrbank3_dfii_pi2_rddata2_re; +wire [7:0] vns_csrbank3_dfii_pi2_rddata2_r; +wire vns_csrbank3_dfii_pi2_rddata2_we; +wire [7:0] vns_csrbank3_dfii_pi2_rddata2_w; +wire vns_csrbank3_dfii_pi2_rddata1_re; +wire [7:0] vns_csrbank3_dfii_pi2_rddata1_r; +wire vns_csrbank3_dfii_pi2_rddata1_we; +wire [7:0] vns_csrbank3_dfii_pi2_rddata1_w; +wire vns_csrbank3_dfii_pi2_rddata0_re; +wire [7:0] vns_csrbank3_dfii_pi2_rddata0_r; +wire vns_csrbank3_dfii_pi2_rddata0_we; +wire [7:0] vns_csrbank3_dfii_pi2_rddata0_w; +wire vns_csrbank3_dfii_pi3_command0_re; +wire [5:0] vns_csrbank3_dfii_pi3_command0_r; +wire vns_csrbank3_dfii_pi3_command0_we; +wire [5:0] vns_csrbank3_dfii_pi3_command0_w; +wire vns_csrbank3_dfii_pi3_address1_re; +wire [6:0] vns_csrbank3_dfii_pi3_address1_r; +wire vns_csrbank3_dfii_pi3_address1_we; +wire [6:0] vns_csrbank3_dfii_pi3_address1_w; +wire vns_csrbank3_dfii_pi3_address0_re; +wire [7:0] vns_csrbank3_dfii_pi3_address0_r; +wire vns_csrbank3_dfii_pi3_address0_we; +wire [7:0] vns_csrbank3_dfii_pi3_address0_w; +wire vns_csrbank3_dfii_pi3_baddress0_re; +wire [2:0] vns_csrbank3_dfii_pi3_baddress0_r; +wire vns_csrbank3_dfii_pi3_baddress0_we; +wire [2:0] vns_csrbank3_dfii_pi3_baddress0_w; +wire vns_csrbank3_dfii_pi3_wrdata3_re; +wire [7:0] vns_csrbank3_dfii_pi3_wrdata3_r; +wire vns_csrbank3_dfii_pi3_wrdata3_we; +wire [7:0] vns_csrbank3_dfii_pi3_wrdata3_w; +wire vns_csrbank3_dfii_pi3_wrdata2_re; +wire [7:0] vns_csrbank3_dfii_pi3_wrdata2_r; +wire vns_csrbank3_dfii_pi3_wrdata2_we; +wire [7:0] vns_csrbank3_dfii_pi3_wrdata2_w; +wire vns_csrbank3_dfii_pi3_wrdata1_re; +wire [7:0] vns_csrbank3_dfii_pi3_wrdata1_r; +wire vns_csrbank3_dfii_pi3_wrdata1_we; +wire [7:0] vns_csrbank3_dfii_pi3_wrdata1_w; +wire vns_csrbank3_dfii_pi3_wrdata0_re; +wire [7:0] vns_csrbank3_dfii_pi3_wrdata0_r; +wire vns_csrbank3_dfii_pi3_wrdata0_we; +wire [7:0] vns_csrbank3_dfii_pi3_wrdata0_w; +wire vns_csrbank3_dfii_pi3_rddata3_re; +wire [7:0] vns_csrbank3_dfii_pi3_rddata3_r; +wire vns_csrbank3_dfii_pi3_rddata3_we; +wire [7:0] vns_csrbank3_dfii_pi3_rddata3_w; +wire vns_csrbank3_dfii_pi3_rddata2_re; +wire [7:0] vns_csrbank3_dfii_pi3_rddata2_r; +wire vns_csrbank3_dfii_pi3_rddata2_we; +wire [7:0] vns_csrbank3_dfii_pi3_rddata2_w; +wire vns_csrbank3_dfii_pi3_rddata1_re; +wire [7:0] vns_csrbank3_dfii_pi3_rddata1_r; +wire vns_csrbank3_dfii_pi3_rddata1_we; +wire [7:0] vns_csrbank3_dfii_pi3_rddata1_w; +wire vns_csrbank3_dfii_pi3_rddata0_re; +wire [7:0] vns_csrbank3_dfii_pi3_rddata0_r; +wire vns_csrbank3_dfii_pi3_rddata0_we; +wire [7:0] vns_csrbank3_dfii_pi3_rddata0_w; +wire vns_csrbank3_sel; +wire [13:0] vns_interface4_bank_bus_adr; +wire vns_interface4_bank_bus_we; +wire [7:0] vns_interface4_bank_bus_dat_w; +reg [7:0] vns_interface4_bank_bus_dat_r = 8'd0; +wire vns_csrbank4_load3_re; +wire [7:0] vns_csrbank4_load3_r; +wire vns_csrbank4_load3_we; +wire [7:0] vns_csrbank4_load3_w; +wire vns_csrbank4_load2_re; +wire [7:0] vns_csrbank4_load2_r; +wire vns_csrbank4_load2_we; +wire [7:0] vns_csrbank4_load2_w; +wire vns_csrbank4_load1_re; +wire [7:0] vns_csrbank4_load1_r; +wire vns_csrbank4_load1_we; +wire [7:0] vns_csrbank4_load1_w; +wire vns_csrbank4_load0_re; +wire [7:0] vns_csrbank4_load0_r; +wire vns_csrbank4_load0_we; +wire [7:0] vns_csrbank4_load0_w; +wire vns_csrbank4_reload3_re; +wire [7:0] vns_csrbank4_reload3_r; +wire vns_csrbank4_reload3_we; +wire [7:0] vns_csrbank4_reload3_w; +wire vns_csrbank4_reload2_re; +wire [7:0] vns_csrbank4_reload2_r; +wire vns_csrbank4_reload2_we; +wire [7:0] vns_csrbank4_reload2_w; +wire vns_csrbank4_reload1_re; +wire [7:0] vns_csrbank4_reload1_r; +wire vns_csrbank4_reload1_we; +wire [7:0] vns_csrbank4_reload1_w; +wire vns_csrbank4_reload0_re; +wire [7:0] vns_csrbank4_reload0_r; +wire vns_csrbank4_reload0_we; +wire [7:0] vns_csrbank4_reload0_w; +wire vns_csrbank4_en0_re; +wire vns_csrbank4_en0_r; +wire vns_csrbank4_en0_we; +wire vns_csrbank4_en0_w; +wire vns_csrbank4_update_value0_re; +wire vns_csrbank4_update_value0_r; +wire vns_csrbank4_update_value0_we; +wire vns_csrbank4_update_value0_w; +wire vns_csrbank4_value3_re; +wire [7:0] vns_csrbank4_value3_r; +wire vns_csrbank4_value3_we; +wire [7:0] vns_csrbank4_value3_w; +wire vns_csrbank4_value2_re; +wire [7:0] vns_csrbank4_value2_r; +wire vns_csrbank4_value2_we; +wire [7:0] vns_csrbank4_value2_w; +wire vns_csrbank4_value1_re; +wire [7:0] vns_csrbank4_value1_r; +wire vns_csrbank4_value1_we; +wire [7:0] vns_csrbank4_value1_w; +wire vns_csrbank4_value0_re; +wire [7:0] vns_csrbank4_value0_r; +wire vns_csrbank4_value0_we; +wire [7:0] vns_csrbank4_value0_w; +wire vns_csrbank4_ev_enable0_re; +wire vns_csrbank4_ev_enable0_r; +wire vns_csrbank4_ev_enable0_we; +wire vns_csrbank4_ev_enable0_w; +wire vns_csrbank4_sel; +wire [13:0] vns_interface5_bank_bus_adr; +wire vns_interface5_bank_bus_we; +wire [7:0] vns_interface5_bank_bus_dat_w; +reg [7:0] vns_interface5_bank_bus_dat_r = 8'd0; +wire vns_csrbank5_txfull_re; +wire vns_csrbank5_txfull_r; +wire vns_csrbank5_txfull_we; +wire vns_csrbank5_txfull_w; +wire vns_csrbank5_rxempty_re; +wire vns_csrbank5_rxempty_r; +wire vns_csrbank5_rxempty_we; +wire vns_csrbank5_rxempty_w; +wire vns_csrbank5_ev_enable0_re; +wire [1:0] vns_csrbank5_ev_enable0_r; +wire vns_csrbank5_ev_enable0_we; +wire [1:0] vns_csrbank5_ev_enable0_w; +wire vns_csrbank5_sel; +wire [13:0] vns_interface6_bank_bus_adr; +wire vns_interface6_bank_bus_we; +wire [7:0] vns_interface6_bank_bus_dat_w; +reg [7:0] vns_interface6_bank_bus_dat_r = 8'd0; +wire vns_csrbank6_tuning_word3_re; +wire [7:0] vns_csrbank6_tuning_word3_r; +wire vns_csrbank6_tuning_word3_we; +wire [7:0] vns_csrbank6_tuning_word3_w; +wire vns_csrbank6_tuning_word2_re; +wire [7:0] vns_csrbank6_tuning_word2_r; +wire vns_csrbank6_tuning_word2_we; +wire [7:0] vns_csrbank6_tuning_word2_w; +wire vns_csrbank6_tuning_word1_re; +wire [7:0] vns_csrbank6_tuning_word1_r; +wire vns_csrbank6_tuning_word1_we; +wire [7:0] vns_csrbank6_tuning_word1_w; +wire vns_csrbank6_tuning_word0_re; +wire [7:0] vns_csrbank6_tuning_word0_r; +wire vns_csrbank6_tuning_word0_we; +wire [7:0] vns_csrbank6_tuning_word0_w; +wire vns_csrbank6_sel; +wire [13:0] vns_adr; +wire vns_we; +wire [7:0] vns_dat_w; +wire [7:0] vns_dat_r; +reg vns_rhs_array_muxed0 = 1'd0; +reg [14:0] vns_rhs_array_muxed1 = 15'd0; +reg [2:0] vns_rhs_array_muxed2 = 3'd0; +reg vns_rhs_array_muxed3 = 1'd0; +reg vns_rhs_array_muxed4 = 1'd0; +reg vns_rhs_array_muxed5 = 1'd0; +reg vns_t_array_muxed0 = 1'd0; +reg vns_t_array_muxed1 = 1'd0; +reg vns_t_array_muxed2 = 1'd0; +reg vns_rhs_array_muxed6 = 1'd0; +reg [14:0] vns_rhs_array_muxed7 = 15'd0; +reg [2:0] vns_rhs_array_muxed8 = 3'd0; +reg vns_rhs_array_muxed9 = 1'd0; +reg vns_rhs_array_muxed10 = 1'd0; +reg vns_rhs_array_muxed11 = 1'd0; +reg vns_t_array_muxed3 = 1'd0; +reg vns_t_array_muxed4 = 1'd0; +reg vns_t_array_muxed5 = 1'd0; +reg [21:0] vns_rhs_array_muxed12 = 22'd0; +reg vns_rhs_array_muxed13 = 1'd0; +reg vns_rhs_array_muxed14 = 1'd0; +reg [21:0] vns_rhs_array_muxed15 = 22'd0; +reg vns_rhs_array_muxed16 = 1'd0; +reg vns_rhs_array_muxed17 = 1'd0; +reg [21:0] vns_rhs_array_muxed18 = 22'd0; +reg vns_rhs_array_muxed19 = 1'd0; +reg vns_rhs_array_muxed20 = 1'd0; +reg [21:0] vns_rhs_array_muxed21 = 22'd0; +reg vns_rhs_array_muxed22 = 1'd0; +reg vns_rhs_array_muxed23 = 1'd0; +reg [21:0] vns_rhs_array_muxed24 = 22'd0; +reg vns_rhs_array_muxed25 = 1'd0; +reg vns_rhs_array_muxed26 = 1'd0; +reg [21:0] vns_rhs_array_muxed27 = 22'd0; +reg vns_rhs_array_muxed28 = 1'd0; +reg vns_rhs_array_muxed29 = 1'd0; +reg [21:0] vns_rhs_array_muxed30 = 22'd0; +reg vns_rhs_array_muxed31 = 1'd0; +reg vns_rhs_array_muxed32 = 1'd0; +reg [21:0] vns_rhs_array_muxed33 = 22'd0; +reg vns_rhs_array_muxed34 = 1'd0; +reg vns_rhs_array_muxed35 = 1'd0; +reg [29:0] vns_rhs_array_muxed36 = 30'd0; +reg [31:0] vns_rhs_array_muxed37 = 32'd0; +reg [3:0] vns_rhs_array_muxed38 = 4'd0; +reg vns_rhs_array_muxed39 = 1'd0; +reg vns_rhs_array_muxed40 = 1'd0; +reg vns_rhs_array_muxed41 = 1'd0; +reg [2:0] vns_rhs_array_muxed42 = 3'd0; +reg [1:0] vns_rhs_array_muxed43 = 2'd0; +reg [2:0] vns_array_muxed0 = 3'd0; +reg [14:0] vns_array_muxed1 = 15'd0; +reg vns_array_muxed2 = 1'd0; +reg vns_array_muxed3 = 1'd0; +reg vns_array_muxed4 = 1'd0; +reg vns_array_muxed5 = 1'd0; +reg vns_array_muxed6 = 1'd0; +reg [2:0] vns_array_muxed7 = 3'd0; +reg [14:0] vns_array_muxed8 = 15'd0; +reg vns_array_muxed9 = 1'd0; +reg vns_array_muxed10 = 1'd0; +reg vns_array_muxed11 = 1'd0; +reg vns_array_muxed12 = 1'd0; +reg vns_array_muxed13 = 1'd0; +reg [2:0] vns_array_muxed14 = 3'd0; +reg [14:0] vns_array_muxed15 = 15'd0; +reg vns_array_muxed16 = 1'd0; +reg vns_array_muxed17 = 1'd0; +reg vns_array_muxed18 = 1'd0; +reg vns_array_muxed19 = 1'd0; +reg vns_array_muxed20 = 1'd0; +reg [2:0] vns_array_muxed21 = 3'd0; +reg [14:0] vns_array_muxed22 = 15'd0; +reg vns_array_muxed23 = 1'd0; +reg vns_array_muxed24 = 1'd0; +reg vns_array_muxed25 = 1'd0; +reg vns_array_muxed26 = 1'd0; +reg vns_array_muxed27 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg vns_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg vns_regs1 = 1'd0; +wire vns_xilinxasyncresetsynchronizerimpl0; +wire vns_xilinxasyncresetsynchronizerimpl0_rst_meta; +wire vns_xilinxasyncresetsynchronizerimpl1; +wire vns_xilinxasyncresetsynchronizerimpl1_rst_meta; +wire vns_xilinxasyncresetsynchronizerimpl1_expr; +wire vns_xilinxasyncresetsynchronizerimpl2; +wire vns_xilinxasyncresetsynchronizerimpl2_rst_meta; +wire vns_xilinxasyncresetsynchronizerimpl2_expr; +wire vns_xilinxasyncresetsynchronizerimpl3; +wire vns_xilinxasyncresetsynchronizerimpl3_rst_meta; + +// synthesis translate_off +reg dummy_s; +initial dummy_s <= 1'd0; +// synthesis translate_on +assign soc_litedramcore_cpu_reset = soc_litedramcore_soccontroller_reset; +assign init_done = soc_init_done_storage; +assign init_error = soc_init_error_storage; +assign user_clk = sys_clk; +assign user_rst = sys_rst; +assign soc_cmd_valid = user_port_native_0_cmd_valid; +assign user_port_native_0_cmd_ready = soc_cmd_ready; +assign soc_cmd_payload_we = user_port_native_0_cmd_we; +assign soc_cmd_payload_addr = user_port_native_0_cmd_addr; +assign soc_wdata_valid = user_port_native_0_wdata_valid; +assign user_port_native_0_wdata_ready = soc_wdata_ready; +assign soc_wdata_payload_we = user_port_native_0_wdata_we; +assign soc_wdata_payload_data = user_port_native_0_wdata_data; +assign user_port_native_0_rdata_valid = soc_rdata_valid; +assign soc_rdata_ready = user_port_native_0_rdata_ready; +assign user_port_native_0_rdata_data = soc_rdata_payload_data; +assign soc_litedramcore_soccontroller_bus_error = vns_error; + +// synthesis translate_off +reg dummy_d; +// synthesis translate_on +always @(*) begin + soc_litedramcore_cpu_interrupt <= 32'd0; + soc_litedramcore_cpu_interrupt[1] <= soc_litedramcore_timer_irq; + soc_litedramcore_cpu_interrupt[0] <= soc_litedramcore_uart_irq; +// synthesis translate_off + dummy_d = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_soccontroller_reset = soc_litedramcore_soccontroller_reset_re; +assign soc_litedramcore_soccontroller_bus_errors_status = soc_litedramcore_soccontroller_bus_errors; +assign soc_litedramcore_litedramcore_adr = soc_litedramcore_litedramcore_ram_bus_adr[12:0]; +assign soc_litedramcore_litedramcore_ram_bus_dat_r = soc_litedramcore_litedramcore_dat_r; + +// synthesis translate_off +reg dummy_d_1; +// synthesis translate_on +always @(*) begin + soc_litedramcore_ram_we <= 4'd0; + soc_litedramcore_ram_we[0] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[0]); + soc_litedramcore_ram_we[1] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[1]); + soc_litedramcore_ram_we[2] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[2]); + soc_litedramcore_ram_we[3] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[3]); +// synthesis translate_off + dummy_d_1 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_ram_adr = soc_litedramcore_ram_bus_ram_bus_adr[9:0]; +assign soc_litedramcore_ram_bus_ram_bus_dat_r = soc_litedramcore_ram_dat_r; +assign soc_litedramcore_ram_dat_w = soc_litedramcore_ram_bus_ram_bus_dat_w; +assign soc_litedramcore_uart_uart_sink_valid = soc_litedramcore_source_valid; +assign soc_litedramcore_source_ready = soc_litedramcore_uart_uart_sink_ready; +assign soc_litedramcore_uart_uart_sink_first = soc_litedramcore_source_first; +assign soc_litedramcore_uart_uart_sink_last = soc_litedramcore_source_last; +assign soc_litedramcore_uart_uart_sink_payload_data = soc_litedramcore_source_payload_data; +assign soc_litedramcore_sink_valid = soc_litedramcore_uart_uart_source_valid; +assign soc_litedramcore_uart_uart_source_ready = soc_litedramcore_sink_ready; +assign soc_litedramcore_sink_first = soc_litedramcore_uart_uart_source_first; +assign soc_litedramcore_sink_last = soc_litedramcore_uart_uart_source_last; +assign soc_litedramcore_sink_payload_data = soc_litedramcore_uart_uart_source_payload_data; +assign soc_litedramcore_uart_tx_fifo_sink_valid = soc_litedramcore_uart_rxtx_re; +assign soc_litedramcore_uart_tx_fifo_sink_payload_data = soc_litedramcore_uart_rxtx_r; +assign soc_litedramcore_uart_txfull_status = (~soc_litedramcore_uart_tx_fifo_sink_ready); +assign soc_litedramcore_uart_uart_source_valid = soc_litedramcore_uart_tx_fifo_source_valid; +assign soc_litedramcore_uart_tx_fifo_source_ready = soc_litedramcore_uart_uart_source_ready; +assign soc_litedramcore_uart_uart_source_first = soc_litedramcore_uart_tx_fifo_source_first; +assign soc_litedramcore_uart_uart_source_last = soc_litedramcore_uart_tx_fifo_source_last; +assign soc_litedramcore_uart_uart_source_payload_data = soc_litedramcore_uart_tx_fifo_source_payload_data; +assign soc_litedramcore_uart_tx_trigger = (~soc_litedramcore_uart_tx_fifo_sink_ready); +assign soc_litedramcore_uart_rx_fifo_sink_valid = soc_litedramcore_uart_uart_sink_valid; +assign soc_litedramcore_uart_uart_sink_ready = soc_litedramcore_uart_rx_fifo_sink_ready; +assign soc_litedramcore_uart_rx_fifo_sink_first = soc_litedramcore_uart_uart_sink_first; +assign soc_litedramcore_uart_rx_fifo_sink_last = soc_litedramcore_uart_uart_sink_last; +assign soc_litedramcore_uart_rx_fifo_sink_payload_data = soc_litedramcore_uart_uart_sink_payload_data; +assign soc_litedramcore_uart_rxempty_status = (~soc_litedramcore_uart_rx_fifo_source_valid); +assign soc_litedramcore_uart_rxtx_w = soc_litedramcore_uart_rx_fifo_source_payload_data; +assign soc_litedramcore_uart_rx_fifo_source_ready = (soc_litedramcore_uart_rx_clear | (1'd0 & soc_litedramcore_uart_rxtx_we)); +assign soc_litedramcore_uart_rx_trigger = (~soc_litedramcore_uart_rx_fifo_source_valid); + +// synthesis translate_off +reg dummy_d_2; +// synthesis translate_on +always @(*) begin + soc_litedramcore_uart_eventmanager_status_w <= 2'd0; + soc_litedramcore_uart_eventmanager_status_w[0] <= soc_litedramcore_uart_tx_status; + soc_litedramcore_uart_eventmanager_status_w[1] <= soc_litedramcore_uart_rx_status; +// synthesis translate_off + dummy_d_2 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_3; +// synthesis translate_on +always @(*) begin + soc_litedramcore_uart_tx_clear <= 1'd0; + if ((soc_litedramcore_uart_eventmanager_pending_re & soc_litedramcore_uart_eventmanager_pending_r[0])) begin + soc_litedramcore_uart_tx_clear <= 1'd1; + end +// synthesis translate_off + dummy_d_3 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_4; +// synthesis translate_on +always @(*) begin + soc_litedramcore_uart_eventmanager_pending_w <= 2'd0; + soc_litedramcore_uart_eventmanager_pending_w[0] <= soc_litedramcore_uart_tx_pending; + soc_litedramcore_uart_eventmanager_pending_w[1] <= soc_litedramcore_uart_rx_pending; +// synthesis translate_off + dummy_d_4 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_5; +// synthesis translate_on +always @(*) begin + soc_litedramcore_uart_rx_clear <= 1'd0; + if ((soc_litedramcore_uart_eventmanager_pending_re & soc_litedramcore_uart_eventmanager_pending_r[1])) begin + soc_litedramcore_uart_rx_clear <= 1'd1; + end +// synthesis translate_off + dummy_d_5 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_uart_irq = ((soc_litedramcore_uart_eventmanager_pending_w[0] & soc_litedramcore_uart_eventmanager_storage[0]) | (soc_litedramcore_uart_eventmanager_pending_w[1] & soc_litedramcore_uart_eventmanager_storage[1])); +assign soc_litedramcore_uart_tx_status = soc_litedramcore_uart_tx_trigger; +assign soc_litedramcore_uart_rx_status = soc_litedramcore_uart_rx_trigger; +assign soc_litedramcore_uart_tx_fifo_syncfifo_din = {soc_litedramcore_uart_tx_fifo_fifo_in_last, soc_litedramcore_uart_tx_fifo_fifo_in_first, soc_litedramcore_uart_tx_fifo_fifo_in_payload_data}; +assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout; +assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout; +assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout; +assign soc_litedramcore_uart_tx_fifo_sink_ready = soc_litedramcore_uart_tx_fifo_syncfifo_writable; +assign soc_litedramcore_uart_tx_fifo_syncfifo_we = soc_litedramcore_uart_tx_fifo_sink_valid; +assign soc_litedramcore_uart_tx_fifo_fifo_in_first = soc_litedramcore_uart_tx_fifo_sink_first; +assign soc_litedramcore_uart_tx_fifo_fifo_in_last = soc_litedramcore_uart_tx_fifo_sink_last; +assign soc_litedramcore_uart_tx_fifo_fifo_in_payload_data = soc_litedramcore_uart_tx_fifo_sink_payload_data; +assign soc_litedramcore_uart_tx_fifo_source_valid = soc_litedramcore_uart_tx_fifo_readable; +assign soc_litedramcore_uart_tx_fifo_source_first = soc_litedramcore_uart_tx_fifo_fifo_out_first; +assign soc_litedramcore_uart_tx_fifo_source_last = soc_litedramcore_uart_tx_fifo_fifo_out_last; +assign soc_litedramcore_uart_tx_fifo_source_payload_data = soc_litedramcore_uart_tx_fifo_fifo_out_payload_data; +assign soc_litedramcore_uart_tx_fifo_re = soc_litedramcore_uart_tx_fifo_source_ready; +assign soc_litedramcore_uart_tx_fifo_syncfifo_re = (soc_litedramcore_uart_tx_fifo_syncfifo_readable & ((~soc_litedramcore_uart_tx_fifo_readable) | soc_litedramcore_uart_tx_fifo_re)); +assign soc_litedramcore_uart_tx_fifo_level1 = (soc_litedramcore_uart_tx_fifo_level0 + soc_litedramcore_uart_tx_fifo_readable); + +// synthesis translate_off +reg dummy_d_6; +// synthesis translate_on +always @(*) begin + soc_litedramcore_uart_tx_fifo_wrport_adr <= 4'd0; + if (soc_litedramcore_uart_tx_fifo_replace) begin + soc_litedramcore_uart_tx_fifo_wrport_adr <= (soc_litedramcore_uart_tx_fifo_produce - 1'd1); + end else begin + soc_litedramcore_uart_tx_fifo_wrport_adr <= soc_litedramcore_uart_tx_fifo_produce; + end +// synthesis translate_off + dummy_d_6 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_uart_tx_fifo_wrport_dat_w = soc_litedramcore_uart_tx_fifo_syncfifo_din; +assign soc_litedramcore_uart_tx_fifo_wrport_we = (soc_litedramcore_uart_tx_fifo_syncfifo_we & (soc_litedramcore_uart_tx_fifo_syncfifo_writable | soc_litedramcore_uart_tx_fifo_replace)); +assign soc_litedramcore_uart_tx_fifo_do_read = (soc_litedramcore_uart_tx_fifo_syncfifo_readable & soc_litedramcore_uart_tx_fifo_syncfifo_re); +assign soc_litedramcore_uart_tx_fifo_rdport_adr = soc_litedramcore_uart_tx_fifo_consume; +assign soc_litedramcore_uart_tx_fifo_syncfifo_dout = soc_litedramcore_uart_tx_fifo_rdport_dat_r; +assign soc_litedramcore_uart_tx_fifo_rdport_re = soc_litedramcore_uart_tx_fifo_do_read; +assign soc_litedramcore_uart_tx_fifo_syncfifo_writable = (soc_litedramcore_uart_tx_fifo_level0 != 5'd16); +assign soc_litedramcore_uart_tx_fifo_syncfifo_readable = (soc_litedramcore_uart_tx_fifo_level0 != 1'd0); +assign soc_litedramcore_uart_rx_fifo_syncfifo_din = {soc_litedramcore_uart_rx_fifo_fifo_in_last, soc_litedramcore_uart_rx_fifo_fifo_in_first, soc_litedramcore_uart_rx_fifo_fifo_in_payload_data}; +assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout; +assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout; +assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout; +assign soc_litedramcore_uart_rx_fifo_sink_ready = soc_litedramcore_uart_rx_fifo_syncfifo_writable; +assign soc_litedramcore_uart_rx_fifo_syncfifo_we = soc_litedramcore_uart_rx_fifo_sink_valid; +assign soc_litedramcore_uart_rx_fifo_fifo_in_first = soc_litedramcore_uart_rx_fifo_sink_first; +assign soc_litedramcore_uart_rx_fifo_fifo_in_last = soc_litedramcore_uart_rx_fifo_sink_last; +assign soc_litedramcore_uart_rx_fifo_fifo_in_payload_data = soc_litedramcore_uart_rx_fifo_sink_payload_data; +assign soc_litedramcore_uart_rx_fifo_source_valid = soc_litedramcore_uart_rx_fifo_readable; +assign soc_litedramcore_uart_rx_fifo_source_first = soc_litedramcore_uart_rx_fifo_fifo_out_first; +assign soc_litedramcore_uart_rx_fifo_source_last = soc_litedramcore_uart_rx_fifo_fifo_out_last; +assign soc_litedramcore_uart_rx_fifo_source_payload_data = soc_litedramcore_uart_rx_fifo_fifo_out_payload_data; +assign soc_litedramcore_uart_rx_fifo_re = soc_litedramcore_uart_rx_fifo_source_ready; +assign soc_litedramcore_uart_rx_fifo_syncfifo_re = (soc_litedramcore_uart_rx_fifo_syncfifo_readable & ((~soc_litedramcore_uart_rx_fifo_readable) | soc_litedramcore_uart_rx_fifo_re)); +assign soc_litedramcore_uart_rx_fifo_level1 = (soc_litedramcore_uart_rx_fifo_level0 + soc_litedramcore_uart_rx_fifo_readable); + +// synthesis translate_off +reg dummy_d_7; +// synthesis translate_on +always @(*) begin + soc_litedramcore_uart_rx_fifo_wrport_adr <= 4'd0; + if (soc_litedramcore_uart_rx_fifo_replace) begin + soc_litedramcore_uart_rx_fifo_wrport_adr <= (soc_litedramcore_uart_rx_fifo_produce - 1'd1); + end else begin + soc_litedramcore_uart_rx_fifo_wrport_adr <= soc_litedramcore_uart_rx_fifo_produce; + end +// synthesis translate_off + dummy_d_7 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_uart_rx_fifo_wrport_dat_w = soc_litedramcore_uart_rx_fifo_syncfifo_din; +assign soc_litedramcore_uart_rx_fifo_wrport_we = (soc_litedramcore_uart_rx_fifo_syncfifo_we & (soc_litedramcore_uart_rx_fifo_syncfifo_writable | soc_litedramcore_uart_rx_fifo_replace)); +assign soc_litedramcore_uart_rx_fifo_do_read = (soc_litedramcore_uart_rx_fifo_syncfifo_readable & soc_litedramcore_uart_rx_fifo_syncfifo_re); +assign soc_litedramcore_uart_rx_fifo_rdport_adr = soc_litedramcore_uart_rx_fifo_consume; +assign soc_litedramcore_uart_rx_fifo_syncfifo_dout = soc_litedramcore_uart_rx_fifo_rdport_dat_r; +assign soc_litedramcore_uart_rx_fifo_rdport_re = soc_litedramcore_uart_rx_fifo_do_read; +assign soc_litedramcore_uart_rx_fifo_syncfifo_writable = (soc_litedramcore_uart_rx_fifo_level0 != 5'd16); +assign soc_litedramcore_uart_rx_fifo_syncfifo_readable = (soc_litedramcore_uart_rx_fifo_level0 != 1'd0); +assign soc_litedramcore_timer_zero_trigger = (soc_litedramcore_timer_value != 1'd0); +assign soc_litedramcore_timer_eventmanager_status_w = soc_litedramcore_timer_zero_status; + +// synthesis translate_off +reg dummy_d_8; +// synthesis translate_on +always @(*) begin + soc_litedramcore_timer_zero_clear <= 1'd0; + if ((soc_litedramcore_timer_eventmanager_pending_re & soc_litedramcore_timer_eventmanager_pending_r)) begin + soc_litedramcore_timer_zero_clear <= 1'd1; + end +// synthesis translate_off + dummy_d_8 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_timer_eventmanager_pending_w = soc_litedramcore_timer_zero_pending; +assign soc_litedramcore_timer_irq = (soc_litedramcore_timer_eventmanager_pending_w & soc_litedramcore_timer_eventmanager_storage); +assign soc_litedramcore_timer_zero_status = soc_litedramcore_timer_zero_trigger; +assign soc_litedramcore_interface_dat_w = soc_litedramcore_bus_wishbone_dat_w; +assign soc_litedramcore_bus_wishbone_dat_r = soc_litedramcore_interface_dat_r; + +// synthesis translate_off +reg dummy_d_9; +// synthesis translate_on +always @(*) begin + vns_wb2csr_next_state <= 1'd0; + vns_wb2csr_next_state <= vns_wb2csr_state; + case (vns_wb2csr_state) + 1'd1: begin + vns_wb2csr_next_state <= 1'd0; + end + default: begin + if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin + vns_wb2csr_next_state <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_9 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_10; +// synthesis translate_on +always @(*) begin + soc_litedramcore_interface_adr <= 14'd0; + case (vns_wb2csr_state) + 1'd1: begin + end + default: begin + if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin + soc_litedramcore_interface_adr <= soc_litedramcore_bus_wishbone_adr; + end + end + endcase +// synthesis translate_off + dummy_d_10 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_11; +// synthesis translate_on +always @(*) begin + soc_litedramcore_interface_we <= 1'd0; + case (vns_wb2csr_state) + 1'd1: begin + end + default: begin + if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin + soc_litedramcore_interface_we <= soc_litedramcore_bus_wishbone_we; + end + end + endcase +// synthesis translate_off + dummy_d_11 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_12; +// synthesis translate_on +always @(*) begin + soc_litedramcore_bus_wishbone_ack <= 1'd0; + case (vns_wb2csr_state) + 1'd1: begin + soc_litedramcore_bus_wishbone_ack <= 1'd1; + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_12 = dummy_s; +// synthesis translate_on +end +assign soc_sys_pll_reset = rst; +assign pll_locked = soc_sys_pll_locked; +assign soc_iodelay_pll_reset = rst; +assign soc_s7pll0_clkin = clk; +assign sys_clk = soc_s7pll0_clkout_buf0; +assign sys4x_clk = soc_s7pll0_clkout_buf1; +assign sys4x_dqs_clk = soc_s7pll0_clkout_buf2; +assign soc_s7pll1_clkin = clk; +assign iodelay_clk = soc_s7pll1_clkout_buf; +assign soc_a7ddrphy_bitslip0_i = soc_a7ddrphy_dq_i_data0; + +// synthesis translate_off +reg dummy_d_13; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_dfi_p0_rddata <= 32'd0; + soc_a7ddrphy_dfi_p0_rddata[0] <= soc_a7ddrphy_bitslip0_o[0]; + soc_a7ddrphy_dfi_p0_rddata[16] <= soc_a7ddrphy_bitslip0_o[1]; + soc_a7ddrphy_dfi_p0_rddata[1] <= soc_a7ddrphy_bitslip1_o[0]; + soc_a7ddrphy_dfi_p0_rddata[17] <= soc_a7ddrphy_bitslip1_o[1]; + soc_a7ddrphy_dfi_p0_rddata[2] <= soc_a7ddrphy_bitslip2_o[0]; + soc_a7ddrphy_dfi_p0_rddata[18] <= soc_a7ddrphy_bitslip2_o[1]; + soc_a7ddrphy_dfi_p0_rddata[3] <= soc_a7ddrphy_bitslip3_o[0]; + soc_a7ddrphy_dfi_p0_rddata[19] <= soc_a7ddrphy_bitslip3_o[1]; + soc_a7ddrphy_dfi_p0_rddata[4] <= soc_a7ddrphy_bitslip4_o[0]; + soc_a7ddrphy_dfi_p0_rddata[20] <= soc_a7ddrphy_bitslip4_o[1]; + soc_a7ddrphy_dfi_p0_rddata[5] <= soc_a7ddrphy_bitslip5_o[0]; + soc_a7ddrphy_dfi_p0_rddata[21] <= soc_a7ddrphy_bitslip5_o[1]; + soc_a7ddrphy_dfi_p0_rddata[6] <= soc_a7ddrphy_bitslip6_o[0]; + soc_a7ddrphy_dfi_p0_rddata[22] <= soc_a7ddrphy_bitslip6_o[1]; + soc_a7ddrphy_dfi_p0_rddata[7] <= soc_a7ddrphy_bitslip7_o[0]; + soc_a7ddrphy_dfi_p0_rddata[23] <= soc_a7ddrphy_bitslip7_o[1]; + soc_a7ddrphy_dfi_p0_rddata[8] <= soc_a7ddrphy_bitslip8_o[0]; + soc_a7ddrphy_dfi_p0_rddata[24] <= soc_a7ddrphy_bitslip8_o[1]; + soc_a7ddrphy_dfi_p0_rddata[9] <= soc_a7ddrphy_bitslip9_o[0]; + soc_a7ddrphy_dfi_p0_rddata[25] <= soc_a7ddrphy_bitslip9_o[1]; + soc_a7ddrphy_dfi_p0_rddata[10] <= soc_a7ddrphy_bitslip10_o[0]; + soc_a7ddrphy_dfi_p0_rddata[26] <= soc_a7ddrphy_bitslip10_o[1]; + soc_a7ddrphy_dfi_p0_rddata[11] <= soc_a7ddrphy_bitslip11_o[0]; + soc_a7ddrphy_dfi_p0_rddata[27] <= soc_a7ddrphy_bitslip11_o[1]; + soc_a7ddrphy_dfi_p0_rddata[12] <= soc_a7ddrphy_bitslip12_o[0]; + soc_a7ddrphy_dfi_p0_rddata[28] <= soc_a7ddrphy_bitslip12_o[1]; + soc_a7ddrphy_dfi_p0_rddata[13] <= soc_a7ddrphy_bitslip13_o[0]; + soc_a7ddrphy_dfi_p0_rddata[29] <= soc_a7ddrphy_bitslip13_o[1]; + soc_a7ddrphy_dfi_p0_rddata[14] <= soc_a7ddrphy_bitslip14_o[0]; + soc_a7ddrphy_dfi_p0_rddata[30] <= soc_a7ddrphy_bitslip14_o[1]; + soc_a7ddrphy_dfi_p0_rddata[15] <= soc_a7ddrphy_bitslip15_o[0]; + soc_a7ddrphy_dfi_p0_rddata[31] <= soc_a7ddrphy_bitslip15_o[1]; +// synthesis translate_off + dummy_d_13 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_14; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_dfi_p1_rddata <= 32'd0; + soc_a7ddrphy_dfi_p1_rddata[0] <= soc_a7ddrphy_bitslip0_o[2]; + soc_a7ddrphy_dfi_p1_rddata[16] <= soc_a7ddrphy_bitslip0_o[3]; + soc_a7ddrphy_dfi_p1_rddata[1] <= soc_a7ddrphy_bitslip1_o[2]; + soc_a7ddrphy_dfi_p1_rddata[17] <= soc_a7ddrphy_bitslip1_o[3]; + soc_a7ddrphy_dfi_p1_rddata[2] <= soc_a7ddrphy_bitslip2_o[2]; + soc_a7ddrphy_dfi_p1_rddata[18] <= soc_a7ddrphy_bitslip2_o[3]; + soc_a7ddrphy_dfi_p1_rddata[3] <= soc_a7ddrphy_bitslip3_o[2]; + soc_a7ddrphy_dfi_p1_rddata[19] <= soc_a7ddrphy_bitslip3_o[3]; + soc_a7ddrphy_dfi_p1_rddata[4] <= soc_a7ddrphy_bitslip4_o[2]; + soc_a7ddrphy_dfi_p1_rddata[20] <= soc_a7ddrphy_bitslip4_o[3]; + soc_a7ddrphy_dfi_p1_rddata[5] <= soc_a7ddrphy_bitslip5_o[2]; + soc_a7ddrphy_dfi_p1_rddata[21] <= soc_a7ddrphy_bitslip5_o[3]; + soc_a7ddrphy_dfi_p1_rddata[6] <= soc_a7ddrphy_bitslip6_o[2]; + soc_a7ddrphy_dfi_p1_rddata[22] <= soc_a7ddrphy_bitslip6_o[3]; + soc_a7ddrphy_dfi_p1_rddata[7] <= soc_a7ddrphy_bitslip7_o[2]; + soc_a7ddrphy_dfi_p1_rddata[23] <= soc_a7ddrphy_bitslip7_o[3]; + soc_a7ddrphy_dfi_p1_rddata[8] <= soc_a7ddrphy_bitslip8_o[2]; + soc_a7ddrphy_dfi_p1_rddata[24] <= soc_a7ddrphy_bitslip8_o[3]; + soc_a7ddrphy_dfi_p1_rddata[9] <= soc_a7ddrphy_bitslip9_o[2]; + soc_a7ddrphy_dfi_p1_rddata[25] <= soc_a7ddrphy_bitslip9_o[3]; + soc_a7ddrphy_dfi_p1_rddata[10] <= soc_a7ddrphy_bitslip10_o[2]; + soc_a7ddrphy_dfi_p1_rddata[26] <= soc_a7ddrphy_bitslip10_o[3]; + soc_a7ddrphy_dfi_p1_rddata[11] <= soc_a7ddrphy_bitslip11_o[2]; + soc_a7ddrphy_dfi_p1_rddata[27] <= soc_a7ddrphy_bitslip11_o[3]; + soc_a7ddrphy_dfi_p1_rddata[12] <= soc_a7ddrphy_bitslip12_o[2]; + soc_a7ddrphy_dfi_p1_rddata[28] <= soc_a7ddrphy_bitslip12_o[3]; + soc_a7ddrphy_dfi_p1_rddata[13] <= soc_a7ddrphy_bitslip13_o[2]; + soc_a7ddrphy_dfi_p1_rddata[29] <= soc_a7ddrphy_bitslip13_o[3]; + soc_a7ddrphy_dfi_p1_rddata[14] <= soc_a7ddrphy_bitslip14_o[2]; + soc_a7ddrphy_dfi_p1_rddata[30] <= soc_a7ddrphy_bitslip14_o[3]; + soc_a7ddrphy_dfi_p1_rddata[15] <= soc_a7ddrphy_bitslip15_o[2]; + soc_a7ddrphy_dfi_p1_rddata[31] <= soc_a7ddrphy_bitslip15_o[3]; +// synthesis translate_off + dummy_d_14 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_15; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_dfi_p2_rddata <= 32'd0; + soc_a7ddrphy_dfi_p2_rddata[0] <= soc_a7ddrphy_bitslip0_o[4]; + soc_a7ddrphy_dfi_p2_rddata[16] <= soc_a7ddrphy_bitslip0_o[5]; + soc_a7ddrphy_dfi_p2_rddata[1] <= soc_a7ddrphy_bitslip1_o[4]; + soc_a7ddrphy_dfi_p2_rddata[17] <= soc_a7ddrphy_bitslip1_o[5]; + soc_a7ddrphy_dfi_p2_rddata[2] <= soc_a7ddrphy_bitslip2_o[4]; + soc_a7ddrphy_dfi_p2_rddata[18] <= soc_a7ddrphy_bitslip2_o[5]; + soc_a7ddrphy_dfi_p2_rddata[3] <= soc_a7ddrphy_bitslip3_o[4]; + soc_a7ddrphy_dfi_p2_rddata[19] <= soc_a7ddrphy_bitslip3_o[5]; + soc_a7ddrphy_dfi_p2_rddata[4] <= soc_a7ddrphy_bitslip4_o[4]; + soc_a7ddrphy_dfi_p2_rddata[20] <= soc_a7ddrphy_bitslip4_o[5]; + soc_a7ddrphy_dfi_p2_rddata[5] <= soc_a7ddrphy_bitslip5_o[4]; + soc_a7ddrphy_dfi_p2_rddata[21] <= soc_a7ddrphy_bitslip5_o[5]; + soc_a7ddrphy_dfi_p2_rddata[6] <= soc_a7ddrphy_bitslip6_o[4]; + soc_a7ddrphy_dfi_p2_rddata[22] <= soc_a7ddrphy_bitslip6_o[5]; + soc_a7ddrphy_dfi_p2_rddata[7] <= soc_a7ddrphy_bitslip7_o[4]; + soc_a7ddrphy_dfi_p2_rddata[23] <= soc_a7ddrphy_bitslip7_o[5]; + soc_a7ddrphy_dfi_p2_rddata[8] <= soc_a7ddrphy_bitslip8_o[4]; + soc_a7ddrphy_dfi_p2_rddata[24] <= soc_a7ddrphy_bitslip8_o[5]; + soc_a7ddrphy_dfi_p2_rddata[9] <= soc_a7ddrphy_bitslip9_o[4]; + soc_a7ddrphy_dfi_p2_rddata[25] <= soc_a7ddrphy_bitslip9_o[5]; + soc_a7ddrphy_dfi_p2_rddata[10] <= soc_a7ddrphy_bitslip10_o[4]; + soc_a7ddrphy_dfi_p2_rddata[26] <= soc_a7ddrphy_bitslip10_o[5]; + soc_a7ddrphy_dfi_p2_rddata[11] <= soc_a7ddrphy_bitslip11_o[4]; + soc_a7ddrphy_dfi_p2_rddata[27] <= soc_a7ddrphy_bitslip11_o[5]; + soc_a7ddrphy_dfi_p2_rddata[12] <= soc_a7ddrphy_bitslip12_o[4]; + soc_a7ddrphy_dfi_p2_rddata[28] <= soc_a7ddrphy_bitslip12_o[5]; + soc_a7ddrphy_dfi_p2_rddata[13] <= soc_a7ddrphy_bitslip13_o[4]; + soc_a7ddrphy_dfi_p2_rddata[29] <= soc_a7ddrphy_bitslip13_o[5]; + soc_a7ddrphy_dfi_p2_rddata[14] <= soc_a7ddrphy_bitslip14_o[4]; + soc_a7ddrphy_dfi_p2_rddata[30] <= soc_a7ddrphy_bitslip14_o[5]; + soc_a7ddrphy_dfi_p2_rddata[15] <= soc_a7ddrphy_bitslip15_o[4]; + soc_a7ddrphy_dfi_p2_rddata[31] <= soc_a7ddrphy_bitslip15_o[5]; +// synthesis translate_off + dummy_d_15 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_16; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_dfi_p3_rddata <= 32'd0; + soc_a7ddrphy_dfi_p3_rddata[0] <= soc_a7ddrphy_bitslip0_o[6]; + soc_a7ddrphy_dfi_p3_rddata[16] <= soc_a7ddrphy_bitslip0_o[7]; + soc_a7ddrphy_dfi_p3_rddata[1] <= soc_a7ddrphy_bitslip1_o[6]; + soc_a7ddrphy_dfi_p3_rddata[17] <= soc_a7ddrphy_bitslip1_o[7]; + soc_a7ddrphy_dfi_p3_rddata[2] <= soc_a7ddrphy_bitslip2_o[6]; + soc_a7ddrphy_dfi_p3_rddata[18] <= soc_a7ddrphy_bitslip2_o[7]; + soc_a7ddrphy_dfi_p3_rddata[3] <= soc_a7ddrphy_bitslip3_o[6]; + soc_a7ddrphy_dfi_p3_rddata[19] <= soc_a7ddrphy_bitslip3_o[7]; + soc_a7ddrphy_dfi_p3_rddata[4] <= soc_a7ddrphy_bitslip4_o[6]; + soc_a7ddrphy_dfi_p3_rddata[20] <= soc_a7ddrphy_bitslip4_o[7]; + soc_a7ddrphy_dfi_p3_rddata[5] <= soc_a7ddrphy_bitslip5_o[6]; + soc_a7ddrphy_dfi_p3_rddata[21] <= soc_a7ddrphy_bitslip5_o[7]; + soc_a7ddrphy_dfi_p3_rddata[6] <= soc_a7ddrphy_bitslip6_o[6]; + soc_a7ddrphy_dfi_p3_rddata[22] <= soc_a7ddrphy_bitslip6_o[7]; + soc_a7ddrphy_dfi_p3_rddata[7] <= soc_a7ddrphy_bitslip7_o[6]; + soc_a7ddrphy_dfi_p3_rddata[23] <= soc_a7ddrphy_bitslip7_o[7]; + soc_a7ddrphy_dfi_p3_rddata[8] <= soc_a7ddrphy_bitslip8_o[6]; + soc_a7ddrphy_dfi_p3_rddata[24] <= soc_a7ddrphy_bitslip8_o[7]; + soc_a7ddrphy_dfi_p3_rddata[9] <= soc_a7ddrphy_bitslip9_o[6]; + soc_a7ddrphy_dfi_p3_rddata[25] <= soc_a7ddrphy_bitslip9_o[7]; + soc_a7ddrphy_dfi_p3_rddata[10] <= soc_a7ddrphy_bitslip10_o[6]; + soc_a7ddrphy_dfi_p3_rddata[26] <= soc_a7ddrphy_bitslip10_o[7]; + soc_a7ddrphy_dfi_p3_rddata[11] <= soc_a7ddrphy_bitslip11_o[6]; + soc_a7ddrphy_dfi_p3_rddata[27] <= soc_a7ddrphy_bitslip11_o[7]; + soc_a7ddrphy_dfi_p3_rddata[12] <= soc_a7ddrphy_bitslip12_o[6]; + soc_a7ddrphy_dfi_p3_rddata[28] <= soc_a7ddrphy_bitslip12_o[7]; + soc_a7ddrphy_dfi_p3_rddata[13] <= soc_a7ddrphy_bitslip13_o[6]; + soc_a7ddrphy_dfi_p3_rddata[29] <= soc_a7ddrphy_bitslip13_o[7]; + soc_a7ddrphy_dfi_p3_rddata[14] <= soc_a7ddrphy_bitslip14_o[6]; + soc_a7ddrphy_dfi_p3_rddata[30] <= soc_a7ddrphy_bitslip14_o[7]; + soc_a7ddrphy_dfi_p3_rddata[15] <= soc_a7ddrphy_bitslip15_o[6]; + soc_a7ddrphy_dfi_p3_rddata[31] <= soc_a7ddrphy_bitslip15_o[7]; +// synthesis translate_off + dummy_d_16 = dummy_s; +// synthesis translate_on +end +assign soc_a7ddrphy_bitslip1_i = soc_a7ddrphy_dq_i_data1; +assign soc_a7ddrphy_bitslip2_i = soc_a7ddrphy_dq_i_data2; +assign soc_a7ddrphy_bitslip3_i = soc_a7ddrphy_dq_i_data3; +assign soc_a7ddrphy_bitslip4_i = soc_a7ddrphy_dq_i_data4; +assign soc_a7ddrphy_bitslip5_i = soc_a7ddrphy_dq_i_data5; +assign soc_a7ddrphy_bitslip6_i = soc_a7ddrphy_dq_i_data6; +assign soc_a7ddrphy_bitslip7_i = soc_a7ddrphy_dq_i_data7; +assign soc_a7ddrphy_bitslip8_i = soc_a7ddrphy_dq_i_data8; +assign soc_a7ddrphy_bitslip9_i = soc_a7ddrphy_dq_i_data9; +assign soc_a7ddrphy_bitslip10_i = soc_a7ddrphy_dq_i_data10; +assign soc_a7ddrphy_bitslip11_i = soc_a7ddrphy_dq_i_data11; +assign soc_a7ddrphy_bitslip12_i = soc_a7ddrphy_dq_i_data12; +assign soc_a7ddrphy_bitslip13_i = soc_a7ddrphy_dq_i_data13; +assign soc_a7ddrphy_bitslip14_i = soc_a7ddrphy_dq_i_data14; +assign soc_a7ddrphy_bitslip15_i = soc_a7ddrphy_dq_i_data15; +assign soc_a7ddrphy_rddata_en = {soc_a7ddrphy_rddata_en_last, soc_a7ddrphy_dfi_p2_rddata_en}; +assign soc_a7ddrphy_wrdata_en = {soc_a7ddrphy_wrdata_en_last, soc_a7ddrphy_dfi_p3_wrdata_en}; +assign soc_a7ddrphy_dq_oe = soc_a7ddrphy_wrdata_en[2]; + +// synthesis translate_off +reg dummy_d_17; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_dqs_oe <= 1'd0; + if (soc_a7ddrphy_wlevel_en_storage) begin + soc_a7ddrphy_dqs_oe <= 1'd1; + end else begin + soc_a7ddrphy_dqs_oe <= soc_a7ddrphy_dq_oe; + end +// synthesis translate_off + dummy_d_17 = dummy_s; +// synthesis translate_on +end +assign soc_a7ddrphy_dqspattern0 = (soc_a7ddrphy_wrdata_en[1] & (~soc_a7ddrphy_wrdata_en[2])); +assign soc_a7ddrphy_dqspattern1 = (soc_a7ddrphy_wrdata_en[3] & (~soc_a7ddrphy_wrdata_en[2])); + +// synthesis translate_off +reg dummy_d_18; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_dqspattern_o0 <= 8'd0; + soc_a7ddrphy_dqspattern_o0 <= 7'd85; + if (soc_a7ddrphy_dqspattern0) begin + soc_a7ddrphy_dqspattern_o0 <= 5'd21; + end + if (soc_a7ddrphy_dqspattern1) begin + soc_a7ddrphy_dqspattern_o0 <= 7'd84; + end + if (soc_a7ddrphy_wlevel_en_storage) begin + soc_a7ddrphy_dqspattern_o0 <= 1'd0; + if (soc_a7ddrphy_wlevel_strobe_re) begin + soc_a7ddrphy_dqspattern_o0 <= 1'd1; + end + end +// synthesis translate_off + dummy_d_18 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_19; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip0_o <= 8'd0; + case (soc_a7ddrphy_bitslip0_value) + 1'd0: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_19 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_20; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip1_o <= 8'd0; + case (soc_a7ddrphy_bitslip1_value) + 1'd0: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_20 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_21; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip2_o <= 8'd0; + case (soc_a7ddrphy_bitslip2_value) + 1'd0: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_21 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_22; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip3_o <= 8'd0; + case (soc_a7ddrphy_bitslip3_value) + 1'd0: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_22 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_23; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip4_o <= 8'd0; + case (soc_a7ddrphy_bitslip4_value) + 1'd0: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_23 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_24; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip5_o <= 8'd0; + case (soc_a7ddrphy_bitslip5_value) + 1'd0: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_24 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_25; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip6_o <= 8'd0; + case (soc_a7ddrphy_bitslip6_value) + 1'd0: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_25 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_26; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip7_o <= 8'd0; + case (soc_a7ddrphy_bitslip7_value) + 1'd0: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_26 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_27; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip8_o <= 8'd0; + case (soc_a7ddrphy_bitslip8_value) + 1'd0: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_27 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_28; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip9_o <= 8'd0; + case (soc_a7ddrphy_bitslip9_value) + 1'd0: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_28 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_29; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip10_o <= 8'd0; + case (soc_a7ddrphy_bitslip10_value) + 1'd0: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_29 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_30; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip11_o <= 8'd0; + case (soc_a7ddrphy_bitslip11_value) + 1'd0: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_30 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_31; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip12_o <= 8'd0; + case (soc_a7ddrphy_bitslip12_value) + 1'd0: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_31 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_32; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip13_o <= 8'd0; + case (soc_a7ddrphy_bitslip13_value) + 1'd0: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_32 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_33; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip14_o <= 8'd0; + case (soc_a7ddrphy_bitslip14_value) + 1'd0: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_33 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_34; +// synthesis translate_on +always @(*) begin + soc_a7ddrphy_bitslip15_o <= 8'd0; + case (soc_a7ddrphy_bitslip15_value) + 1'd0: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[7:0]; + end + 1'd1: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[8:1]; + end + 2'd2: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[9:2]; + end + 2'd3: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[10:3]; + end + 3'd4: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[11:4]; + end + 3'd5: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[12:5]; + end + 3'd6: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[13:6]; + end + 3'd7: begin + soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[14:7]; + end + endcase +// synthesis translate_off + dummy_d_34 = dummy_s; +// synthesis translate_on +end +assign soc_a7ddrphy_dfi_p0_address = soc_sdram_master_p0_address; +assign soc_a7ddrphy_dfi_p0_bank = soc_sdram_master_p0_bank; +assign soc_a7ddrphy_dfi_p0_cas_n = soc_sdram_master_p0_cas_n; +assign soc_a7ddrphy_dfi_p0_cs_n = soc_sdram_master_p0_cs_n; +assign soc_a7ddrphy_dfi_p0_ras_n = soc_sdram_master_p0_ras_n; +assign soc_a7ddrphy_dfi_p0_we_n = soc_sdram_master_p0_we_n; +assign soc_a7ddrphy_dfi_p0_cke = soc_sdram_master_p0_cke; +assign soc_a7ddrphy_dfi_p0_odt = soc_sdram_master_p0_odt; +assign soc_a7ddrphy_dfi_p0_reset_n = soc_sdram_master_p0_reset_n; +assign soc_a7ddrphy_dfi_p0_act_n = soc_sdram_master_p0_act_n; +assign soc_a7ddrphy_dfi_p0_wrdata = soc_sdram_master_p0_wrdata; +assign soc_a7ddrphy_dfi_p0_wrdata_en = soc_sdram_master_p0_wrdata_en; +assign soc_a7ddrphy_dfi_p0_wrdata_mask = soc_sdram_master_p0_wrdata_mask; +assign soc_a7ddrphy_dfi_p0_rddata_en = soc_sdram_master_p0_rddata_en; +assign soc_sdram_master_p0_rddata = soc_a7ddrphy_dfi_p0_rddata; +assign soc_sdram_master_p0_rddata_valid = soc_a7ddrphy_dfi_p0_rddata_valid; +assign soc_a7ddrphy_dfi_p1_address = soc_sdram_master_p1_address; +assign soc_a7ddrphy_dfi_p1_bank = soc_sdram_master_p1_bank; +assign soc_a7ddrphy_dfi_p1_cas_n = soc_sdram_master_p1_cas_n; +assign soc_a7ddrphy_dfi_p1_cs_n = soc_sdram_master_p1_cs_n; +assign soc_a7ddrphy_dfi_p1_ras_n = soc_sdram_master_p1_ras_n; +assign soc_a7ddrphy_dfi_p1_we_n = soc_sdram_master_p1_we_n; +assign soc_a7ddrphy_dfi_p1_cke = soc_sdram_master_p1_cke; +assign soc_a7ddrphy_dfi_p1_odt = soc_sdram_master_p1_odt; +assign soc_a7ddrphy_dfi_p1_reset_n = soc_sdram_master_p1_reset_n; +assign soc_a7ddrphy_dfi_p1_act_n = soc_sdram_master_p1_act_n; +assign soc_a7ddrphy_dfi_p1_wrdata = soc_sdram_master_p1_wrdata; +assign soc_a7ddrphy_dfi_p1_wrdata_en = soc_sdram_master_p1_wrdata_en; +assign soc_a7ddrphy_dfi_p1_wrdata_mask = soc_sdram_master_p1_wrdata_mask; +assign soc_a7ddrphy_dfi_p1_rddata_en = soc_sdram_master_p1_rddata_en; +assign soc_sdram_master_p1_rddata = soc_a7ddrphy_dfi_p1_rddata; +assign soc_sdram_master_p1_rddata_valid = soc_a7ddrphy_dfi_p1_rddata_valid; +assign soc_a7ddrphy_dfi_p2_address = soc_sdram_master_p2_address; +assign soc_a7ddrphy_dfi_p2_bank = soc_sdram_master_p2_bank; +assign soc_a7ddrphy_dfi_p2_cas_n = soc_sdram_master_p2_cas_n; +assign soc_a7ddrphy_dfi_p2_cs_n = soc_sdram_master_p2_cs_n; +assign soc_a7ddrphy_dfi_p2_ras_n = soc_sdram_master_p2_ras_n; +assign soc_a7ddrphy_dfi_p2_we_n = soc_sdram_master_p2_we_n; +assign soc_a7ddrphy_dfi_p2_cke = soc_sdram_master_p2_cke; +assign soc_a7ddrphy_dfi_p2_odt = soc_sdram_master_p2_odt; +assign soc_a7ddrphy_dfi_p2_reset_n = soc_sdram_master_p2_reset_n; +assign soc_a7ddrphy_dfi_p2_act_n = soc_sdram_master_p2_act_n; +assign soc_a7ddrphy_dfi_p2_wrdata = soc_sdram_master_p2_wrdata; +assign soc_a7ddrphy_dfi_p2_wrdata_en = soc_sdram_master_p2_wrdata_en; +assign soc_a7ddrphy_dfi_p2_wrdata_mask = soc_sdram_master_p2_wrdata_mask; +assign soc_a7ddrphy_dfi_p2_rddata_en = soc_sdram_master_p2_rddata_en; +assign soc_sdram_master_p2_rddata = soc_a7ddrphy_dfi_p2_rddata; +assign soc_sdram_master_p2_rddata_valid = soc_a7ddrphy_dfi_p2_rddata_valid; +assign soc_a7ddrphy_dfi_p3_address = soc_sdram_master_p3_address; +assign soc_a7ddrphy_dfi_p3_bank = soc_sdram_master_p3_bank; +assign soc_a7ddrphy_dfi_p3_cas_n = soc_sdram_master_p3_cas_n; +assign soc_a7ddrphy_dfi_p3_cs_n = soc_sdram_master_p3_cs_n; +assign soc_a7ddrphy_dfi_p3_ras_n = soc_sdram_master_p3_ras_n; +assign soc_a7ddrphy_dfi_p3_we_n = soc_sdram_master_p3_we_n; +assign soc_a7ddrphy_dfi_p3_cke = soc_sdram_master_p3_cke; +assign soc_a7ddrphy_dfi_p3_odt = soc_sdram_master_p3_odt; +assign soc_a7ddrphy_dfi_p3_reset_n = soc_sdram_master_p3_reset_n; +assign soc_a7ddrphy_dfi_p3_act_n = soc_sdram_master_p3_act_n; +assign soc_a7ddrphy_dfi_p3_wrdata = soc_sdram_master_p3_wrdata; +assign soc_a7ddrphy_dfi_p3_wrdata_en = soc_sdram_master_p3_wrdata_en; +assign soc_a7ddrphy_dfi_p3_wrdata_mask = soc_sdram_master_p3_wrdata_mask; +assign soc_a7ddrphy_dfi_p3_rddata_en = soc_sdram_master_p3_rddata_en; +assign soc_sdram_master_p3_rddata = soc_a7ddrphy_dfi_p3_rddata; +assign soc_sdram_master_p3_rddata_valid = soc_a7ddrphy_dfi_p3_rddata_valid; +assign soc_sdram_slave_p0_address = soc_sdram_dfi_p0_address; +assign soc_sdram_slave_p0_bank = soc_sdram_dfi_p0_bank; +assign soc_sdram_slave_p0_cas_n = soc_sdram_dfi_p0_cas_n; +assign soc_sdram_slave_p0_cs_n = soc_sdram_dfi_p0_cs_n; +assign soc_sdram_slave_p0_ras_n = soc_sdram_dfi_p0_ras_n; +assign soc_sdram_slave_p0_we_n = soc_sdram_dfi_p0_we_n; +assign soc_sdram_slave_p0_cke = soc_sdram_dfi_p0_cke; +assign soc_sdram_slave_p0_odt = soc_sdram_dfi_p0_odt; +assign soc_sdram_slave_p0_reset_n = soc_sdram_dfi_p0_reset_n; +assign soc_sdram_slave_p0_act_n = soc_sdram_dfi_p0_act_n; +assign soc_sdram_slave_p0_wrdata = soc_sdram_dfi_p0_wrdata; +assign soc_sdram_slave_p0_wrdata_en = soc_sdram_dfi_p0_wrdata_en; +assign soc_sdram_slave_p0_wrdata_mask = soc_sdram_dfi_p0_wrdata_mask; +assign soc_sdram_slave_p0_rddata_en = soc_sdram_dfi_p0_rddata_en; +assign soc_sdram_dfi_p0_rddata = soc_sdram_slave_p0_rddata; +assign soc_sdram_dfi_p0_rddata_valid = soc_sdram_slave_p0_rddata_valid; +assign soc_sdram_slave_p1_address = soc_sdram_dfi_p1_address; +assign soc_sdram_slave_p1_bank = soc_sdram_dfi_p1_bank; +assign soc_sdram_slave_p1_cas_n = soc_sdram_dfi_p1_cas_n; +assign soc_sdram_slave_p1_cs_n = soc_sdram_dfi_p1_cs_n; +assign soc_sdram_slave_p1_ras_n = soc_sdram_dfi_p1_ras_n; +assign soc_sdram_slave_p1_we_n = soc_sdram_dfi_p1_we_n; +assign soc_sdram_slave_p1_cke = soc_sdram_dfi_p1_cke; +assign soc_sdram_slave_p1_odt = soc_sdram_dfi_p1_odt; +assign soc_sdram_slave_p1_reset_n = soc_sdram_dfi_p1_reset_n; +assign soc_sdram_slave_p1_act_n = soc_sdram_dfi_p1_act_n; +assign soc_sdram_slave_p1_wrdata = soc_sdram_dfi_p1_wrdata; +assign soc_sdram_slave_p1_wrdata_en = soc_sdram_dfi_p1_wrdata_en; +assign soc_sdram_slave_p1_wrdata_mask = soc_sdram_dfi_p1_wrdata_mask; +assign soc_sdram_slave_p1_rddata_en = soc_sdram_dfi_p1_rddata_en; +assign soc_sdram_dfi_p1_rddata = soc_sdram_slave_p1_rddata; +assign soc_sdram_dfi_p1_rddata_valid = soc_sdram_slave_p1_rddata_valid; +assign soc_sdram_slave_p2_address = soc_sdram_dfi_p2_address; +assign soc_sdram_slave_p2_bank = soc_sdram_dfi_p2_bank; +assign soc_sdram_slave_p2_cas_n = soc_sdram_dfi_p2_cas_n; +assign soc_sdram_slave_p2_cs_n = soc_sdram_dfi_p2_cs_n; +assign soc_sdram_slave_p2_ras_n = soc_sdram_dfi_p2_ras_n; +assign soc_sdram_slave_p2_we_n = soc_sdram_dfi_p2_we_n; +assign soc_sdram_slave_p2_cke = soc_sdram_dfi_p2_cke; +assign soc_sdram_slave_p2_odt = soc_sdram_dfi_p2_odt; +assign soc_sdram_slave_p2_reset_n = soc_sdram_dfi_p2_reset_n; +assign soc_sdram_slave_p2_act_n = soc_sdram_dfi_p2_act_n; +assign soc_sdram_slave_p2_wrdata = soc_sdram_dfi_p2_wrdata; +assign soc_sdram_slave_p2_wrdata_en = soc_sdram_dfi_p2_wrdata_en; +assign soc_sdram_slave_p2_wrdata_mask = soc_sdram_dfi_p2_wrdata_mask; +assign soc_sdram_slave_p2_rddata_en = soc_sdram_dfi_p2_rddata_en; +assign soc_sdram_dfi_p2_rddata = soc_sdram_slave_p2_rddata; +assign soc_sdram_dfi_p2_rddata_valid = soc_sdram_slave_p2_rddata_valid; +assign soc_sdram_slave_p3_address = soc_sdram_dfi_p3_address; +assign soc_sdram_slave_p3_bank = soc_sdram_dfi_p3_bank; +assign soc_sdram_slave_p3_cas_n = soc_sdram_dfi_p3_cas_n; +assign soc_sdram_slave_p3_cs_n = soc_sdram_dfi_p3_cs_n; +assign soc_sdram_slave_p3_ras_n = soc_sdram_dfi_p3_ras_n; +assign soc_sdram_slave_p3_we_n = soc_sdram_dfi_p3_we_n; +assign soc_sdram_slave_p3_cke = soc_sdram_dfi_p3_cke; +assign soc_sdram_slave_p3_odt = soc_sdram_dfi_p3_odt; +assign soc_sdram_slave_p3_reset_n = soc_sdram_dfi_p3_reset_n; +assign soc_sdram_slave_p3_act_n = soc_sdram_dfi_p3_act_n; +assign soc_sdram_slave_p3_wrdata = soc_sdram_dfi_p3_wrdata; +assign soc_sdram_slave_p3_wrdata_en = soc_sdram_dfi_p3_wrdata_en; +assign soc_sdram_slave_p3_wrdata_mask = soc_sdram_dfi_p3_wrdata_mask; +assign soc_sdram_slave_p3_rddata_en = soc_sdram_dfi_p3_rddata_en; +assign soc_sdram_dfi_p3_rddata = soc_sdram_slave_p3_rddata; +assign soc_sdram_dfi_p3_rddata_valid = soc_sdram_slave_p3_rddata_valid; + +// synthesis translate_off +reg dummy_d_35; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_cas_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_cas_n <= soc_sdram_slave_p2_cas_n; + end else begin + soc_sdram_master_p2_cas_n <= soc_sdram_inti_p2_cas_n; + end +// synthesis translate_off + dummy_d_35 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_36; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_cs_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_cs_n <= soc_sdram_slave_p2_cs_n; + end else begin + soc_sdram_master_p2_cs_n <= soc_sdram_inti_p2_cs_n; + end +// synthesis translate_off + dummy_d_36 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_37; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_ras_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_ras_n <= soc_sdram_slave_p2_ras_n; + end else begin + soc_sdram_master_p2_ras_n <= soc_sdram_inti_p2_ras_n; + end +// synthesis translate_off + dummy_d_37 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_38; +// synthesis translate_on +always @(*) begin + soc_sdram_slave_p2_rddata <= 32'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_slave_p2_rddata <= soc_sdram_master_p2_rddata; + end else begin + end +// synthesis translate_off + dummy_d_38 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_39; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_we_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_we_n <= soc_sdram_slave_p2_we_n; + end else begin + soc_sdram_master_p2_we_n <= soc_sdram_inti_p2_we_n; + end +// synthesis translate_off + dummy_d_39 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_40; +// synthesis translate_on +always @(*) begin + soc_sdram_slave_p2_rddata_valid <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_slave_p2_rddata_valid <= soc_sdram_master_p2_rddata_valid; + end else begin + end +// synthesis translate_off + dummy_d_40 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_41; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_cke <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_cke <= soc_sdram_slave_p2_cke; + end else begin + soc_sdram_master_p2_cke <= soc_sdram_inti_p2_cke; + end +// synthesis translate_off + dummy_d_41 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_42; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_odt <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_odt <= soc_sdram_slave_p2_odt; + end else begin + soc_sdram_master_p2_odt <= soc_sdram_inti_p2_odt; + end +// synthesis translate_off + dummy_d_42 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_43; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_reset_n <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_reset_n <= soc_sdram_slave_p2_reset_n; + end else begin + soc_sdram_master_p2_reset_n <= soc_sdram_inti_p2_reset_n; + end +// synthesis translate_off + dummy_d_43 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_44; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_act_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_act_n <= soc_sdram_slave_p2_act_n; + end else begin + soc_sdram_master_p2_act_n <= soc_sdram_inti_p2_act_n; + end +// synthesis translate_off + dummy_d_44 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_45; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_wrdata <= 32'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_wrdata <= soc_sdram_slave_p2_wrdata; + end else begin + soc_sdram_master_p2_wrdata <= soc_sdram_inti_p2_wrdata; + end +// synthesis translate_off + dummy_d_45 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_46; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p3_rddata <= 32'd0; + if (soc_sdram_storage[0]) begin + end else begin + soc_sdram_inti_p3_rddata <= soc_sdram_master_p3_rddata; + end +// synthesis translate_off + dummy_d_46 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_47; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_wrdata_en <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_wrdata_en <= soc_sdram_slave_p2_wrdata_en; + end else begin + soc_sdram_master_p2_wrdata_en <= soc_sdram_inti_p2_wrdata_en; + end +// synthesis translate_off + dummy_d_47 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_48; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p3_rddata_valid <= 1'd0; + if (soc_sdram_storage[0]) begin + end else begin + soc_sdram_inti_p3_rddata_valid <= soc_sdram_master_p3_rddata_valid; + end +// synthesis translate_off + dummy_d_48 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_49; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_wrdata_mask <= 4'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_wrdata_mask <= soc_sdram_slave_p2_wrdata_mask; + end else begin + soc_sdram_master_p2_wrdata_mask <= soc_sdram_inti_p2_wrdata_mask; + end +// synthesis translate_off + dummy_d_49 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_50; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_rddata_en <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_rddata_en <= soc_sdram_slave_p2_rddata_en; + end else begin + soc_sdram_master_p2_rddata_en <= soc_sdram_inti_p2_rddata_en; + end +// synthesis translate_off + dummy_d_50 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_51; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_address <= 15'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_address <= soc_sdram_slave_p3_address; + end else begin + soc_sdram_master_p3_address <= soc_sdram_inti_p3_address; + end +// synthesis translate_off + dummy_d_51 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_52; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_bank <= 3'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_bank <= soc_sdram_slave_p3_bank; + end else begin + soc_sdram_master_p3_bank <= soc_sdram_inti_p3_bank; + end +// synthesis translate_off + dummy_d_52 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_53; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_cas_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_cas_n <= soc_sdram_slave_p3_cas_n; + end else begin + soc_sdram_master_p3_cas_n <= soc_sdram_inti_p3_cas_n; + end +// synthesis translate_off + dummy_d_53 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_54; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_cs_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_cs_n <= soc_sdram_slave_p3_cs_n; + end else begin + soc_sdram_master_p3_cs_n <= soc_sdram_inti_p3_cs_n; + end +// synthesis translate_off + dummy_d_54 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_55; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_ras_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_ras_n <= soc_sdram_slave_p3_ras_n; + end else begin + soc_sdram_master_p3_ras_n <= soc_sdram_inti_p3_ras_n; + end +// synthesis translate_off + dummy_d_55 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_56; +// synthesis translate_on +always @(*) begin + soc_sdram_slave_p3_rddata <= 32'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_slave_p3_rddata <= soc_sdram_master_p3_rddata; + end else begin + end +// synthesis translate_off + dummy_d_56 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_57; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_we_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_we_n <= soc_sdram_slave_p3_we_n; + end else begin + soc_sdram_master_p3_we_n <= soc_sdram_inti_p3_we_n; + end +// synthesis translate_off + dummy_d_57 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_58; +// synthesis translate_on +always @(*) begin + soc_sdram_slave_p3_rddata_valid <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_slave_p3_rddata_valid <= soc_sdram_master_p3_rddata_valid; + end else begin + end +// synthesis translate_off + dummy_d_58 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_59; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_cke <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_cke <= soc_sdram_slave_p3_cke; + end else begin + soc_sdram_master_p3_cke <= soc_sdram_inti_p3_cke; + end +// synthesis translate_off + dummy_d_59 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_60; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_odt <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_odt <= soc_sdram_slave_p3_odt; + end else begin + soc_sdram_master_p3_odt <= soc_sdram_inti_p3_odt; + end +// synthesis translate_off + dummy_d_60 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_61; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_reset_n <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_reset_n <= soc_sdram_slave_p3_reset_n; + end else begin + soc_sdram_master_p3_reset_n <= soc_sdram_inti_p3_reset_n; + end +// synthesis translate_off + dummy_d_61 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_62; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_act_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_act_n <= soc_sdram_slave_p3_act_n; + end else begin + soc_sdram_master_p3_act_n <= soc_sdram_inti_p3_act_n; + end +// synthesis translate_off + dummy_d_62 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_63; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_wrdata <= 32'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_wrdata <= soc_sdram_slave_p3_wrdata; + end else begin + soc_sdram_master_p3_wrdata <= soc_sdram_inti_p3_wrdata; + end +// synthesis translate_off + dummy_d_63 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_64; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p0_rddata <= 32'd0; + if (soc_sdram_storage[0]) begin + end else begin + soc_sdram_inti_p0_rddata <= soc_sdram_master_p0_rddata; + end +// synthesis translate_off + dummy_d_64 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_65; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_wrdata_en <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_wrdata_en <= soc_sdram_slave_p3_wrdata_en; + end else begin + soc_sdram_master_p3_wrdata_en <= soc_sdram_inti_p3_wrdata_en; + end +// synthesis translate_off + dummy_d_65 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_66; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p0_rddata_valid <= 1'd0; + if (soc_sdram_storage[0]) begin + end else begin + soc_sdram_inti_p0_rddata_valid <= soc_sdram_master_p0_rddata_valid; + end +// synthesis translate_off + dummy_d_66 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_67; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_wrdata_mask <= 4'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_wrdata_mask <= soc_sdram_slave_p3_wrdata_mask; + end else begin + soc_sdram_master_p3_wrdata_mask <= soc_sdram_inti_p3_wrdata_mask; + end +// synthesis translate_off + dummy_d_67 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_68; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p3_rddata_en <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p3_rddata_en <= soc_sdram_slave_p3_rddata_en; + end else begin + soc_sdram_master_p3_rddata_en <= soc_sdram_inti_p3_rddata_en; + end +// synthesis translate_off + dummy_d_68 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_69; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_address <= 15'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_address <= soc_sdram_slave_p0_address; + end else begin + soc_sdram_master_p0_address <= soc_sdram_inti_p0_address; + end +// synthesis translate_off + dummy_d_69 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_70; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_bank <= 3'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_bank <= soc_sdram_slave_p0_bank; + end else begin + soc_sdram_master_p0_bank <= soc_sdram_inti_p0_bank; + end +// synthesis translate_off + dummy_d_70 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_71; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_cas_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_cas_n <= soc_sdram_slave_p0_cas_n; + end else begin + soc_sdram_master_p0_cas_n <= soc_sdram_inti_p0_cas_n; + end +// synthesis translate_off + dummy_d_71 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_72; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_cs_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_cs_n <= soc_sdram_slave_p0_cs_n; + end else begin + soc_sdram_master_p0_cs_n <= soc_sdram_inti_p0_cs_n; + end +// synthesis translate_off + dummy_d_72 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_73; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_ras_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_ras_n <= soc_sdram_slave_p0_ras_n; + end else begin + soc_sdram_master_p0_ras_n <= soc_sdram_inti_p0_ras_n; + end +// synthesis translate_off + dummy_d_73 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_74; +// synthesis translate_on +always @(*) begin + soc_sdram_slave_p0_rddata <= 32'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_slave_p0_rddata <= soc_sdram_master_p0_rddata; + end else begin + end +// synthesis translate_off + dummy_d_74 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_75; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_we_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_we_n <= soc_sdram_slave_p0_we_n; + end else begin + soc_sdram_master_p0_we_n <= soc_sdram_inti_p0_we_n; + end +// synthesis translate_off + dummy_d_75 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_76; +// synthesis translate_on +always @(*) begin + soc_sdram_slave_p0_rddata_valid <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_slave_p0_rddata_valid <= soc_sdram_master_p0_rddata_valid; + end else begin + end +// synthesis translate_off + dummy_d_76 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_77; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_cke <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_cke <= soc_sdram_slave_p0_cke; + end else begin + soc_sdram_master_p0_cke <= soc_sdram_inti_p0_cke; + end +// synthesis translate_off + dummy_d_77 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_78; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_odt <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_odt <= soc_sdram_slave_p0_odt; + end else begin + soc_sdram_master_p0_odt <= soc_sdram_inti_p0_odt; + end +// synthesis translate_off + dummy_d_78 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_79; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_reset_n <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_reset_n <= soc_sdram_slave_p0_reset_n; + end else begin + soc_sdram_master_p0_reset_n <= soc_sdram_inti_p0_reset_n; + end +// synthesis translate_off + dummy_d_79 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_80; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_act_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_act_n <= soc_sdram_slave_p0_act_n; + end else begin + soc_sdram_master_p0_act_n <= soc_sdram_inti_p0_act_n; + end +// synthesis translate_off + dummy_d_80 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_81; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_wrdata <= 32'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_wrdata <= soc_sdram_slave_p0_wrdata; + end else begin + soc_sdram_master_p0_wrdata <= soc_sdram_inti_p0_wrdata; + end +// synthesis translate_off + dummy_d_81 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_82; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p1_rddata <= 32'd0; + if (soc_sdram_storage[0]) begin + end else begin + soc_sdram_inti_p1_rddata <= soc_sdram_master_p1_rddata; + end +// synthesis translate_off + dummy_d_82 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_83; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_wrdata_en <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_wrdata_en <= soc_sdram_slave_p0_wrdata_en; + end else begin + soc_sdram_master_p0_wrdata_en <= soc_sdram_inti_p0_wrdata_en; + end +// synthesis translate_off + dummy_d_83 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_84; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p1_rddata_valid <= 1'd0; + if (soc_sdram_storage[0]) begin + end else begin + soc_sdram_inti_p1_rddata_valid <= soc_sdram_master_p1_rddata_valid; + end +// synthesis translate_off + dummy_d_84 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_85; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_wrdata_mask <= 4'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_wrdata_mask <= soc_sdram_slave_p0_wrdata_mask; + end else begin + soc_sdram_master_p0_wrdata_mask <= soc_sdram_inti_p0_wrdata_mask; + end +// synthesis translate_off + dummy_d_85 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_86; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p0_rddata_en <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p0_rddata_en <= soc_sdram_slave_p0_rddata_en; + end else begin + soc_sdram_master_p0_rddata_en <= soc_sdram_inti_p0_rddata_en; + end +// synthesis translate_off + dummy_d_86 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_87; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_address <= 15'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_address <= soc_sdram_slave_p1_address; + end else begin + soc_sdram_master_p1_address <= soc_sdram_inti_p1_address; + end +// synthesis translate_off + dummy_d_87 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_88; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_bank <= 3'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_bank <= soc_sdram_slave_p1_bank; + end else begin + soc_sdram_master_p1_bank <= soc_sdram_inti_p1_bank; + end +// synthesis translate_off + dummy_d_88 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_89; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_cas_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_cas_n <= soc_sdram_slave_p1_cas_n; + end else begin + soc_sdram_master_p1_cas_n <= soc_sdram_inti_p1_cas_n; + end +// synthesis translate_off + dummy_d_89 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_90; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_cs_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_cs_n <= soc_sdram_slave_p1_cs_n; + end else begin + soc_sdram_master_p1_cs_n <= soc_sdram_inti_p1_cs_n; + end +// synthesis translate_off + dummy_d_90 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_91; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_ras_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_ras_n <= soc_sdram_slave_p1_ras_n; + end else begin + soc_sdram_master_p1_ras_n <= soc_sdram_inti_p1_ras_n; + end +// synthesis translate_off + dummy_d_91 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_92; +// synthesis translate_on +always @(*) begin + soc_sdram_slave_p1_rddata <= 32'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_slave_p1_rddata <= soc_sdram_master_p1_rddata; + end else begin + end +// synthesis translate_off + dummy_d_92 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_93; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_we_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_we_n <= soc_sdram_slave_p1_we_n; + end else begin + soc_sdram_master_p1_we_n <= soc_sdram_inti_p1_we_n; + end +// synthesis translate_off + dummy_d_93 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_94; +// synthesis translate_on +always @(*) begin + soc_sdram_slave_p1_rddata_valid <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_slave_p1_rddata_valid <= soc_sdram_master_p1_rddata_valid; + end else begin + end +// synthesis translate_off + dummy_d_94 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_95; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_cke <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_cke <= soc_sdram_slave_p1_cke; + end else begin + soc_sdram_master_p1_cke <= soc_sdram_inti_p1_cke; + end +// synthesis translate_off + dummy_d_95 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_96; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_odt <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_odt <= soc_sdram_slave_p1_odt; + end else begin + soc_sdram_master_p1_odt <= soc_sdram_inti_p1_odt; + end +// synthesis translate_off + dummy_d_96 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_97; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_reset_n <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_reset_n <= soc_sdram_slave_p1_reset_n; + end else begin + soc_sdram_master_p1_reset_n <= soc_sdram_inti_p1_reset_n; + end +// synthesis translate_off + dummy_d_97 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_98; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_act_n <= 1'd1; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_act_n <= soc_sdram_slave_p1_act_n; + end else begin + soc_sdram_master_p1_act_n <= soc_sdram_inti_p1_act_n; + end +// synthesis translate_off + dummy_d_98 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_99; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_wrdata <= 32'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_wrdata <= soc_sdram_slave_p1_wrdata; + end else begin + soc_sdram_master_p1_wrdata <= soc_sdram_inti_p1_wrdata; + end +// synthesis translate_off + dummy_d_99 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_100; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p2_rddata <= 32'd0; + if (soc_sdram_storage[0]) begin + end else begin + soc_sdram_inti_p2_rddata <= soc_sdram_master_p2_rddata; + end +// synthesis translate_off + dummy_d_100 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_101; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_wrdata_en <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_wrdata_en <= soc_sdram_slave_p1_wrdata_en; + end else begin + soc_sdram_master_p1_wrdata_en <= soc_sdram_inti_p1_wrdata_en; + end +// synthesis translate_off + dummy_d_101 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_102; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p2_rddata_valid <= 1'd0; + if (soc_sdram_storage[0]) begin + end else begin + soc_sdram_inti_p2_rddata_valid <= soc_sdram_master_p2_rddata_valid; + end +// synthesis translate_off + dummy_d_102 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_103; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_wrdata_mask <= 4'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_wrdata_mask <= soc_sdram_slave_p1_wrdata_mask; + end else begin + soc_sdram_master_p1_wrdata_mask <= soc_sdram_inti_p1_wrdata_mask; + end +// synthesis translate_off + dummy_d_103 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_104; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p1_rddata_en <= 1'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p1_rddata_en <= soc_sdram_slave_p1_rddata_en; + end else begin + soc_sdram_master_p1_rddata_en <= soc_sdram_inti_p1_rddata_en; + end +// synthesis translate_off + dummy_d_104 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_105; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_address <= 15'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_address <= soc_sdram_slave_p2_address; + end else begin + soc_sdram_master_p2_address <= soc_sdram_inti_p2_address; + end +// synthesis translate_off + dummy_d_105 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_106; +// synthesis translate_on +always @(*) begin + soc_sdram_master_p2_bank <= 3'd0; + if (soc_sdram_storage[0]) begin + soc_sdram_master_p2_bank <= soc_sdram_slave_p2_bank; + end else begin + soc_sdram_master_p2_bank <= soc_sdram_inti_p2_bank; + end +// synthesis translate_off + dummy_d_106 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_inti_p0_cke = soc_sdram_storage[1]; +assign soc_sdram_inti_p1_cke = soc_sdram_storage[1]; +assign soc_sdram_inti_p2_cke = soc_sdram_storage[1]; +assign soc_sdram_inti_p3_cke = soc_sdram_storage[1]; +assign soc_sdram_inti_p0_odt = soc_sdram_storage[2]; +assign soc_sdram_inti_p1_odt = soc_sdram_storage[2]; +assign soc_sdram_inti_p2_odt = soc_sdram_storage[2]; +assign soc_sdram_inti_p3_odt = soc_sdram_storage[2]; +assign soc_sdram_inti_p0_reset_n = soc_sdram_storage[3]; +assign soc_sdram_inti_p1_reset_n = soc_sdram_storage[3]; +assign soc_sdram_inti_p2_reset_n = soc_sdram_storage[3]; +assign soc_sdram_inti_p3_reset_n = soc_sdram_storage[3]; + +// synthesis translate_off +reg dummy_d_107; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p0_cas_n <= 1'd1; + if (soc_sdram_phaseinjector0_command_issue_re) begin + soc_sdram_inti_p0_cas_n <= (~soc_sdram_phaseinjector0_command_storage[2]); + end else begin + soc_sdram_inti_p0_cas_n <= 1'd1; + end +// synthesis translate_off + dummy_d_107 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_108; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p0_cs_n <= 1'd1; + if (soc_sdram_phaseinjector0_command_issue_re) begin + soc_sdram_inti_p0_cs_n <= {1{(~soc_sdram_phaseinjector0_command_storage[0])}}; + end else begin + soc_sdram_inti_p0_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_108 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_109; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p0_ras_n <= 1'd1; + if (soc_sdram_phaseinjector0_command_issue_re) begin + soc_sdram_inti_p0_ras_n <= (~soc_sdram_phaseinjector0_command_storage[3]); + end else begin + soc_sdram_inti_p0_ras_n <= 1'd1; + end +// synthesis translate_off + dummy_d_109 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_110; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p0_we_n <= 1'd1; + if (soc_sdram_phaseinjector0_command_issue_re) begin + soc_sdram_inti_p0_we_n <= (~soc_sdram_phaseinjector0_command_storage[1]); + end else begin + soc_sdram_inti_p0_we_n <= 1'd1; + end +// synthesis translate_off + dummy_d_110 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_inti_p0_address = soc_sdram_phaseinjector0_address_storage; +assign soc_sdram_inti_p0_bank = soc_sdram_phaseinjector0_baddress_storage; +assign soc_sdram_inti_p0_wrdata_en = (soc_sdram_phaseinjector0_command_issue_re & soc_sdram_phaseinjector0_command_storage[4]); +assign soc_sdram_inti_p0_rddata_en = (soc_sdram_phaseinjector0_command_issue_re & soc_sdram_phaseinjector0_command_storage[5]); +assign soc_sdram_inti_p0_wrdata = soc_sdram_phaseinjector0_wrdata_storage; +assign soc_sdram_inti_p0_wrdata_mask = 1'd0; + +// synthesis translate_off +reg dummy_d_111; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p1_cas_n <= 1'd1; + if (soc_sdram_phaseinjector1_command_issue_re) begin + soc_sdram_inti_p1_cas_n <= (~soc_sdram_phaseinjector1_command_storage[2]); + end else begin + soc_sdram_inti_p1_cas_n <= 1'd1; + end +// synthesis translate_off + dummy_d_111 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_112; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p1_cs_n <= 1'd1; + if (soc_sdram_phaseinjector1_command_issue_re) begin + soc_sdram_inti_p1_cs_n <= {1{(~soc_sdram_phaseinjector1_command_storage[0])}}; + end else begin + soc_sdram_inti_p1_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_112 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_113; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p1_ras_n <= 1'd1; + if (soc_sdram_phaseinjector1_command_issue_re) begin + soc_sdram_inti_p1_ras_n <= (~soc_sdram_phaseinjector1_command_storage[3]); + end else begin + soc_sdram_inti_p1_ras_n <= 1'd1; + end +// synthesis translate_off + dummy_d_113 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_114; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p1_we_n <= 1'd1; + if (soc_sdram_phaseinjector1_command_issue_re) begin + soc_sdram_inti_p1_we_n <= (~soc_sdram_phaseinjector1_command_storage[1]); + end else begin + soc_sdram_inti_p1_we_n <= 1'd1; + end +// synthesis translate_off + dummy_d_114 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_inti_p1_address = soc_sdram_phaseinjector1_address_storage; +assign soc_sdram_inti_p1_bank = soc_sdram_phaseinjector1_baddress_storage; +assign soc_sdram_inti_p1_wrdata_en = (soc_sdram_phaseinjector1_command_issue_re & soc_sdram_phaseinjector1_command_storage[4]); +assign soc_sdram_inti_p1_rddata_en = (soc_sdram_phaseinjector1_command_issue_re & soc_sdram_phaseinjector1_command_storage[5]); +assign soc_sdram_inti_p1_wrdata = soc_sdram_phaseinjector1_wrdata_storage; +assign soc_sdram_inti_p1_wrdata_mask = 1'd0; + +// synthesis translate_off +reg dummy_d_115; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p2_cas_n <= 1'd1; + if (soc_sdram_phaseinjector2_command_issue_re) begin + soc_sdram_inti_p2_cas_n <= (~soc_sdram_phaseinjector2_command_storage[2]); + end else begin + soc_sdram_inti_p2_cas_n <= 1'd1; + end +// synthesis translate_off + dummy_d_115 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_116; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p2_cs_n <= 1'd1; + if (soc_sdram_phaseinjector2_command_issue_re) begin + soc_sdram_inti_p2_cs_n <= {1{(~soc_sdram_phaseinjector2_command_storage[0])}}; + end else begin + soc_sdram_inti_p2_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_116 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_117; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p2_ras_n <= 1'd1; + if (soc_sdram_phaseinjector2_command_issue_re) begin + soc_sdram_inti_p2_ras_n <= (~soc_sdram_phaseinjector2_command_storage[3]); + end else begin + soc_sdram_inti_p2_ras_n <= 1'd1; + end +// synthesis translate_off + dummy_d_117 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_118; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p2_we_n <= 1'd1; + if (soc_sdram_phaseinjector2_command_issue_re) begin + soc_sdram_inti_p2_we_n <= (~soc_sdram_phaseinjector2_command_storage[1]); + end else begin + soc_sdram_inti_p2_we_n <= 1'd1; + end +// synthesis translate_off + dummy_d_118 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_inti_p2_address = soc_sdram_phaseinjector2_address_storage; +assign soc_sdram_inti_p2_bank = soc_sdram_phaseinjector2_baddress_storage; +assign soc_sdram_inti_p2_wrdata_en = (soc_sdram_phaseinjector2_command_issue_re & soc_sdram_phaseinjector2_command_storage[4]); +assign soc_sdram_inti_p2_rddata_en = (soc_sdram_phaseinjector2_command_issue_re & soc_sdram_phaseinjector2_command_storage[5]); +assign soc_sdram_inti_p2_wrdata = soc_sdram_phaseinjector2_wrdata_storage; +assign soc_sdram_inti_p2_wrdata_mask = 1'd0; + +// synthesis translate_off +reg dummy_d_119; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p3_cas_n <= 1'd1; + if (soc_sdram_phaseinjector3_command_issue_re) begin + soc_sdram_inti_p3_cas_n <= (~soc_sdram_phaseinjector3_command_storage[2]); + end else begin + soc_sdram_inti_p3_cas_n <= 1'd1; + end +// synthesis translate_off + dummy_d_119 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_120; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p3_cs_n <= 1'd1; + if (soc_sdram_phaseinjector3_command_issue_re) begin + soc_sdram_inti_p3_cs_n <= {1{(~soc_sdram_phaseinjector3_command_storage[0])}}; + end else begin + soc_sdram_inti_p3_cs_n <= {1{1'd1}}; + end +// synthesis translate_off + dummy_d_120 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_121; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p3_ras_n <= 1'd1; + if (soc_sdram_phaseinjector3_command_issue_re) begin + soc_sdram_inti_p3_ras_n <= (~soc_sdram_phaseinjector3_command_storage[3]); + end else begin + soc_sdram_inti_p3_ras_n <= 1'd1; + end +// synthesis translate_off + dummy_d_121 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_122; +// synthesis translate_on +always @(*) begin + soc_sdram_inti_p3_we_n <= 1'd1; + if (soc_sdram_phaseinjector3_command_issue_re) begin + soc_sdram_inti_p3_we_n <= (~soc_sdram_phaseinjector3_command_storage[1]); + end else begin + soc_sdram_inti_p3_we_n <= 1'd1; + end +// synthesis translate_off + dummy_d_122 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_inti_p3_address = soc_sdram_phaseinjector3_address_storage; +assign soc_sdram_inti_p3_bank = soc_sdram_phaseinjector3_baddress_storage; +assign soc_sdram_inti_p3_wrdata_en = (soc_sdram_phaseinjector3_command_issue_re & soc_sdram_phaseinjector3_command_storage[4]); +assign soc_sdram_inti_p3_rddata_en = (soc_sdram_phaseinjector3_command_issue_re & soc_sdram_phaseinjector3_command_storage[5]); +assign soc_sdram_inti_p3_wrdata = soc_sdram_phaseinjector3_wrdata_storage; +assign soc_sdram_inti_p3_wrdata_mask = 1'd0; +assign soc_sdram_bankmachine0_req_valid = soc_sdram_interface_bank0_valid; +assign soc_sdram_interface_bank0_ready = soc_sdram_bankmachine0_req_ready; +assign soc_sdram_bankmachine0_req_we = soc_sdram_interface_bank0_we; +assign soc_sdram_bankmachine0_req_addr = soc_sdram_interface_bank0_addr; +assign soc_sdram_interface_bank0_lock = soc_sdram_bankmachine0_req_lock; +assign soc_sdram_interface_bank0_wdata_ready = soc_sdram_bankmachine0_req_wdata_ready; +assign soc_sdram_interface_bank0_rdata_valid = soc_sdram_bankmachine0_req_rdata_valid; +assign soc_sdram_bankmachine1_req_valid = soc_sdram_interface_bank1_valid; +assign soc_sdram_interface_bank1_ready = soc_sdram_bankmachine1_req_ready; +assign soc_sdram_bankmachine1_req_we = soc_sdram_interface_bank1_we; +assign soc_sdram_bankmachine1_req_addr = soc_sdram_interface_bank1_addr; +assign soc_sdram_interface_bank1_lock = soc_sdram_bankmachine1_req_lock; +assign soc_sdram_interface_bank1_wdata_ready = soc_sdram_bankmachine1_req_wdata_ready; +assign soc_sdram_interface_bank1_rdata_valid = soc_sdram_bankmachine1_req_rdata_valid; +assign soc_sdram_bankmachine2_req_valid = soc_sdram_interface_bank2_valid; +assign soc_sdram_interface_bank2_ready = soc_sdram_bankmachine2_req_ready; +assign soc_sdram_bankmachine2_req_we = soc_sdram_interface_bank2_we; +assign soc_sdram_bankmachine2_req_addr = soc_sdram_interface_bank2_addr; +assign soc_sdram_interface_bank2_lock = soc_sdram_bankmachine2_req_lock; +assign soc_sdram_interface_bank2_wdata_ready = soc_sdram_bankmachine2_req_wdata_ready; +assign soc_sdram_interface_bank2_rdata_valid = soc_sdram_bankmachine2_req_rdata_valid; +assign soc_sdram_bankmachine3_req_valid = soc_sdram_interface_bank3_valid; +assign soc_sdram_interface_bank3_ready = soc_sdram_bankmachine3_req_ready; +assign soc_sdram_bankmachine3_req_we = soc_sdram_interface_bank3_we; +assign soc_sdram_bankmachine3_req_addr = soc_sdram_interface_bank3_addr; +assign soc_sdram_interface_bank3_lock = soc_sdram_bankmachine3_req_lock; +assign soc_sdram_interface_bank3_wdata_ready = soc_sdram_bankmachine3_req_wdata_ready; +assign soc_sdram_interface_bank3_rdata_valid = soc_sdram_bankmachine3_req_rdata_valid; +assign soc_sdram_bankmachine4_req_valid = soc_sdram_interface_bank4_valid; +assign soc_sdram_interface_bank4_ready = soc_sdram_bankmachine4_req_ready; +assign soc_sdram_bankmachine4_req_we = soc_sdram_interface_bank4_we; +assign soc_sdram_bankmachine4_req_addr = soc_sdram_interface_bank4_addr; +assign soc_sdram_interface_bank4_lock = soc_sdram_bankmachine4_req_lock; +assign soc_sdram_interface_bank4_wdata_ready = soc_sdram_bankmachine4_req_wdata_ready; +assign soc_sdram_interface_bank4_rdata_valid = soc_sdram_bankmachine4_req_rdata_valid; +assign soc_sdram_bankmachine5_req_valid = soc_sdram_interface_bank5_valid; +assign soc_sdram_interface_bank5_ready = soc_sdram_bankmachine5_req_ready; +assign soc_sdram_bankmachine5_req_we = soc_sdram_interface_bank5_we; +assign soc_sdram_bankmachine5_req_addr = soc_sdram_interface_bank5_addr; +assign soc_sdram_interface_bank5_lock = soc_sdram_bankmachine5_req_lock; +assign soc_sdram_interface_bank5_wdata_ready = soc_sdram_bankmachine5_req_wdata_ready; +assign soc_sdram_interface_bank5_rdata_valid = soc_sdram_bankmachine5_req_rdata_valid; +assign soc_sdram_bankmachine6_req_valid = soc_sdram_interface_bank6_valid; +assign soc_sdram_interface_bank6_ready = soc_sdram_bankmachine6_req_ready; +assign soc_sdram_bankmachine6_req_we = soc_sdram_interface_bank6_we; +assign soc_sdram_bankmachine6_req_addr = soc_sdram_interface_bank6_addr; +assign soc_sdram_interface_bank6_lock = soc_sdram_bankmachine6_req_lock; +assign soc_sdram_interface_bank6_wdata_ready = soc_sdram_bankmachine6_req_wdata_ready; +assign soc_sdram_interface_bank6_rdata_valid = soc_sdram_bankmachine6_req_rdata_valid; +assign soc_sdram_bankmachine7_req_valid = soc_sdram_interface_bank7_valid; +assign soc_sdram_interface_bank7_ready = soc_sdram_bankmachine7_req_ready; +assign soc_sdram_bankmachine7_req_we = soc_sdram_interface_bank7_we; +assign soc_sdram_bankmachine7_req_addr = soc_sdram_interface_bank7_addr; +assign soc_sdram_interface_bank7_lock = soc_sdram_bankmachine7_req_lock; +assign soc_sdram_interface_bank7_wdata_ready = soc_sdram_bankmachine7_req_wdata_ready; +assign soc_sdram_interface_bank7_rdata_valid = soc_sdram_bankmachine7_req_rdata_valid; +assign soc_sdram_timer_wait = (~soc_sdram_timer_done0); +assign soc_sdram_postponer_req_i = soc_sdram_timer_done0; +assign soc_sdram_wants_refresh = soc_sdram_postponer_req_o; +assign soc_sdram_wants_zqcs = soc_sdram_zqcs_timer_done0; +assign soc_sdram_zqcs_timer_wait = (~soc_sdram_zqcs_executer_done); +assign soc_sdram_timer_done1 = (soc_sdram_timer_count1 == 1'd0); +assign soc_sdram_timer_done0 = soc_sdram_timer_done1; +assign soc_sdram_timer_count0 = soc_sdram_timer_count1; +assign soc_sdram_sequencer_start1 = (soc_sdram_sequencer_start0 | (soc_sdram_sequencer_count != 1'd0)); +assign soc_sdram_sequencer_done0 = (soc_sdram_sequencer_done1 & (soc_sdram_sequencer_count == 1'd0)); +assign soc_sdram_zqcs_timer_done1 = (soc_sdram_zqcs_timer_count1 == 1'd0); +assign soc_sdram_zqcs_timer_done0 = soc_sdram_zqcs_timer_done1; +assign soc_sdram_zqcs_timer_count0 = soc_sdram_zqcs_timer_count1; + +// synthesis translate_off +reg dummy_d_123; +// synthesis translate_on +always @(*) begin + vns_refresher_next_state <= 2'd0; + vns_refresher_next_state <= vns_refresher_state; + case (vns_refresher_state) + 1'd1: begin + if (soc_sdram_cmd_ready) begin + vns_refresher_next_state <= 2'd2; + end + end + 2'd2: begin + if (soc_sdram_sequencer_done0) begin + if (soc_sdram_wants_zqcs) begin + vns_refresher_next_state <= 2'd3; + end else begin + vns_refresher_next_state <= 1'd0; + end + end + end + 2'd3: begin + if (soc_sdram_zqcs_executer_done) begin + vns_refresher_next_state <= 1'd0; + end + end + default: begin + if (1'd1) begin + if (soc_sdram_wants_refresh) begin + vns_refresher_next_state <= 1'd1; + end + end + end + endcase +// synthesis translate_off + dummy_d_123 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_124; +// synthesis translate_on +always @(*) begin + soc_sdram_sequencer_start0 <= 1'd0; + case (vns_refresher_state) + 1'd1: begin + if (soc_sdram_cmd_ready) begin + soc_sdram_sequencer_start0 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_124 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_125; +// synthesis translate_on +always @(*) begin + soc_sdram_cmd_valid <= 1'd0; + case (vns_refresher_state) + 1'd1: begin + soc_sdram_cmd_valid <= 1'd1; + end + 2'd2: begin + soc_sdram_cmd_valid <= 1'd1; + if (soc_sdram_sequencer_done0) begin + if (soc_sdram_wants_zqcs) begin + end else begin + soc_sdram_cmd_valid <= 1'd0; + end + end + end + 2'd3: begin + soc_sdram_cmd_valid <= 1'd1; + if (soc_sdram_zqcs_executer_done) begin + soc_sdram_cmd_valid <= 1'd0; + end + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_125 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_126; +// synthesis translate_on +always @(*) begin + soc_sdram_zqcs_executer_start <= 1'd0; + case (vns_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (soc_sdram_sequencer_done0) begin + if (soc_sdram_wants_zqcs) begin + soc_sdram_zqcs_executer_start <= 1'd1; + end else begin + end + end + end + 2'd3: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_126 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_127; +// synthesis translate_on +always @(*) begin + soc_sdram_cmd_last <= 1'd0; + case (vns_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (soc_sdram_sequencer_done0) begin + if (soc_sdram_wants_zqcs) begin + end else begin + soc_sdram_cmd_last <= 1'd1; + end + end + end + 2'd3: begin + if (soc_sdram_zqcs_executer_done) begin + soc_sdram_cmd_last <= 1'd1; + end + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_127 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine0_req_valid; +assign soc_sdram_bankmachine0_req_ready = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine0_req_we; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine0_req_addr; +assign soc_sdram_bankmachine0_cmd_buffer_sink_valid = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine0_cmd_buffer_sink_ready; +assign soc_sdram_bankmachine0_cmd_buffer_sink_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first; +assign soc_sdram_bankmachine0_cmd_buffer_sink_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last; +assign soc_sdram_bankmachine0_cmd_buffer_sink_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we; +assign soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +assign soc_sdram_bankmachine0_cmd_buffer_source_ready = (soc_sdram_bankmachine0_req_wdata_ready | soc_sdram_bankmachine0_req_rdata_valid); +assign soc_sdram_bankmachine0_req_lock = (soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine0_cmd_buffer_source_valid); +assign soc_sdram_bankmachine0_row_hit = (soc_sdram_bankmachine0_row == soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:7]); +assign soc_sdram_bankmachine0_cmd_payload_ba = 1'd0; + +// synthesis translate_off +reg dummy_d_128; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_cmd_payload_a <= 15'd0; + if (soc_sdram_bankmachine0_row_col_n_addr_sel) begin + soc_sdram_bankmachine0_cmd_payload_a <= soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:7]; + end else begin + soc_sdram_bankmachine0_cmd_payload_a <= ((soc_sdram_bankmachine0_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_128 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine0_twtpcon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_cmd_payload_is_write); +assign soc_sdram_bankmachine0_trccon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_row_open); +assign soc_sdram_bankmachine0_trascon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_row_open); + +// synthesis translate_off +reg dummy_d_129; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_auto_precharge <= 1'd0; + if ((soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine0_cmd_buffer_source_valid)) begin + if ((soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin + soc_sdram_bankmachine0_auto_precharge <= (soc_sdram_bankmachine0_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_129 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_first; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_last; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_130; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_sdram_bankmachine0_cmd_buffer_lookahead_replace) begin + soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine0_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_130 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_sdram_bankmachine0_cmd_buffer_lookahead_replace)); +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine0_cmd_buffer_lookahead_consume; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_sdram_bankmachine0_cmd_buffer_lookahead_level != 5'd16); +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0); +assign soc_sdram_bankmachine0_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine0_cmd_buffer_source_valid) | soc_sdram_bankmachine0_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_131; +// synthesis translate_on +always @(*) begin + vns_bankmachine0_next_state <= 4'd0; + vns_bankmachine0_next_state <= vns_bankmachine0_state; + case (vns_bankmachine0_state) + 1'd1: begin + if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin + if (soc_sdram_bankmachine0_cmd_ready) begin + vns_bankmachine0_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin + vns_bankmachine0_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_sdram_bankmachine0_trccon_ready) begin + if (soc_sdram_bankmachine0_cmd_ready) begin + vns_bankmachine0_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_sdram_bankmachine0_refresh_req)) begin + vns_bankmachine0_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine0_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine0_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine0_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine0_next_state <= 1'd0; + end + default: begin + if (soc_sdram_bankmachine0_refresh_req) begin + vns_bankmachine0_next_state <= 3'd4; + end else begin + if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine0_row_opened) begin + if (soc_sdram_bankmachine0_row_hit) begin + if ((soc_sdram_bankmachine0_cmd_ready & soc_sdram_bankmachine0_auto_precharge)) begin + vns_bankmachine0_next_state <= 2'd2; + end + end else begin + vns_bankmachine0_next_state <= 1'd1; + end + end else begin + vns_bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_131 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_132; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_cmd_payload_we <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin + soc_sdram_bankmachine0_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine0_refresh_req) begin + end else begin + if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine0_row_opened) begin + if (soc_sdram_bankmachine0_row_hit) begin + if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_132 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_133; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine0_trccon_ready) begin + soc_sdram_bankmachine0_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_133 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_134; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin + soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine0_trccon_ready) begin + soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_134 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_135; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine0_refresh_req) begin + end else begin + if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine0_row_opened) begin + if (soc_sdram_bankmachine0_row_hit) begin + if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine0_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_135 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_136; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine0_refresh_req) begin + end else begin + if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine0_row_opened) begin + if (soc_sdram_bankmachine0_row_hit) begin + if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_136 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_137; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_req_wdata_ready <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine0_refresh_req) begin + end else begin + if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine0_row_opened) begin + if (soc_sdram_bankmachine0_row_hit) begin + if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine0_req_wdata_ready <= soc_sdram_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_137 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_138; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_req_rdata_valid <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine0_refresh_req) begin + end else begin + if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine0_row_opened) begin + if (soc_sdram_bankmachine0_row_hit) begin + if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine0_req_rdata_valid <= soc_sdram_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_138 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_139; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_refresh_gnt <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_sdram_bankmachine0_twtpcon_ready) begin + soc_sdram_bankmachine0_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_139 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_140; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_cmd_valid <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin + soc_sdram_bankmachine0_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine0_trccon_ready) begin + soc_sdram_bankmachine0_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine0_refresh_req) begin + end else begin + if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine0_row_opened) begin + if (soc_sdram_bankmachine0_row_hit) begin + soc_sdram_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_140 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_141; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_row_open <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine0_trccon_ready) begin + soc_sdram_bankmachine0_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_141 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_142; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_row_close <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + soc_sdram_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + soc_sdram_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_sdram_bankmachine0_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_142 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_143; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_cmd_payload_cas <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine0_refresh_req) begin + end else begin + if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine0_row_opened) begin + if (soc_sdram_bankmachine0_row_hit) begin + soc_sdram_bankmachine0_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_143 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_144; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_cmd_payload_ras <= 1'd0; + case (vns_bankmachine0_state) + 1'd1: begin + if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin + soc_sdram_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine0_trccon_ready) begin + soc_sdram_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_144 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine1_req_valid; +assign soc_sdram_bankmachine1_req_ready = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine1_req_we; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine1_req_addr; +assign soc_sdram_bankmachine1_cmd_buffer_sink_valid = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine1_cmd_buffer_sink_ready; +assign soc_sdram_bankmachine1_cmd_buffer_sink_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first; +assign soc_sdram_bankmachine1_cmd_buffer_sink_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last; +assign soc_sdram_bankmachine1_cmd_buffer_sink_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we; +assign soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +assign soc_sdram_bankmachine1_cmd_buffer_source_ready = (soc_sdram_bankmachine1_req_wdata_ready | soc_sdram_bankmachine1_req_rdata_valid); +assign soc_sdram_bankmachine1_req_lock = (soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine1_cmd_buffer_source_valid); +assign soc_sdram_bankmachine1_row_hit = (soc_sdram_bankmachine1_row == soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:7]); +assign soc_sdram_bankmachine1_cmd_payload_ba = 1'd1; + +// synthesis translate_off +reg dummy_d_145; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_cmd_payload_a <= 15'd0; + if (soc_sdram_bankmachine1_row_col_n_addr_sel) begin + soc_sdram_bankmachine1_cmd_payload_a <= soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:7]; + end else begin + soc_sdram_bankmachine1_cmd_payload_a <= ((soc_sdram_bankmachine1_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_145 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine1_twtpcon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_cmd_payload_is_write); +assign soc_sdram_bankmachine1_trccon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_row_open); +assign soc_sdram_bankmachine1_trascon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_row_open); + +// synthesis translate_off +reg dummy_d_146; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_auto_precharge <= 1'd0; + if ((soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine1_cmd_buffer_source_valid)) begin + if ((soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin + soc_sdram_bankmachine1_auto_precharge <= (soc_sdram_bankmachine1_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_146 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_first; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_last; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_147; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_sdram_bankmachine1_cmd_buffer_lookahead_replace) begin + soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine1_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_147 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_sdram_bankmachine1_cmd_buffer_lookahead_replace)); +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine1_cmd_buffer_lookahead_consume; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_sdram_bankmachine1_cmd_buffer_lookahead_level != 5'd16); +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0); +assign soc_sdram_bankmachine1_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine1_cmd_buffer_source_valid) | soc_sdram_bankmachine1_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_148; +// synthesis translate_on +always @(*) begin + vns_bankmachine1_next_state <= 4'd0; + vns_bankmachine1_next_state <= vns_bankmachine1_state; + case (vns_bankmachine1_state) + 1'd1: begin + if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin + if (soc_sdram_bankmachine1_cmd_ready) begin + vns_bankmachine1_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin + vns_bankmachine1_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_sdram_bankmachine1_trccon_ready) begin + if (soc_sdram_bankmachine1_cmd_ready) begin + vns_bankmachine1_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_sdram_bankmachine1_refresh_req)) begin + vns_bankmachine1_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine1_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine1_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine1_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine1_next_state <= 1'd0; + end + default: begin + if (soc_sdram_bankmachine1_refresh_req) begin + vns_bankmachine1_next_state <= 3'd4; + end else begin + if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine1_row_opened) begin + if (soc_sdram_bankmachine1_row_hit) begin + if ((soc_sdram_bankmachine1_cmd_ready & soc_sdram_bankmachine1_auto_precharge)) begin + vns_bankmachine1_next_state <= 2'd2; + end + end else begin + vns_bankmachine1_next_state <= 1'd1; + end + end else begin + vns_bankmachine1_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_148 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_149; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_cmd_payload_we <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin + soc_sdram_bankmachine1_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine1_refresh_req) begin + end else begin + if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine1_row_opened) begin + if (soc_sdram_bankmachine1_row_hit) begin + if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_149 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_150; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine1_trccon_ready) begin + soc_sdram_bankmachine1_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_150 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_151; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin + soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine1_trccon_ready) begin + soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_151 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_152; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine1_refresh_req) begin + end else begin + if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine1_row_opened) begin + if (soc_sdram_bankmachine1_row_hit) begin + if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine1_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_152 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_153; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine1_refresh_req) begin + end else begin + if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine1_row_opened) begin + if (soc_sdram_bankmachine1_row_hit) begin + if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_153 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_154; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_req_wdata_ready <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine1_refresh_req) begin + end else begin + if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine1_row_opened) begin + if (soc_sdram_bankmachine1_row_hit) begin + if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine1_req_wdata_ready <= soc_sdram_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_154 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_155; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_req_rdata_valid <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine1_refresh_req) begin + end else begin + if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine1_row_opened) begin + if (soc_sdram_bankmachine1_row_hit) begin + if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine1_req_rdata_valid <= soc_sdram_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_155 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_156; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_refresh_gnt <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_sdram_bankmachine1_twtpcon_ready) begin + soc_sdram_bankmachine1_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_156 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_157; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_cmd_valid <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin + soc_sdram_bankmachine1_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine1_trccon_ready) begin + soc_sdram_bankmachine1_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine1_refresh_req) begin + end else begin + if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine1_row_opened) begin + if (soc_sdram_bankmachine1_row_hit) begin + soc_sdram_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_157 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_158; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_row_open <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine1_trccon_ready) begin + soc_sdram_bankmachine1_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_158 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_159; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_row_close <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + soc_sdram_bankmachine1_row_close <= 1'd1; + end + 2'd2: begin + soc_sdram_bankmachine1_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_sdram_bankmachine1_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_159 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_160; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_cmd_payload_cas <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine1_refresh_req) begin + end else begin + if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine1_row_opened) begin + if (soc_sdram_bankmachine1_row_hit) begin + soc_sdram_bankmachine1_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_160 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_161; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_cmd_payload_ras <= 1'd0; + case (vns_bankmachine1_state) + 1'd1: begin + if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin + soc_sdram_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine1_trccon_ready) begin + soc_sdram_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_161 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine2_req_valid; +assign soc_sdram_bankmachine2_req_ready = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine2_req_we; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine2_req_addr; +assign soc_sdram_bankmachine2_cmd_buffer_sink_valid = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine2_cmd_buffer_sink_ready; +assign soc_sdram_bankmachine2_cmd_buffer_sink_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first; +assign soc_sdram_bankmachine2_cmd_buffer_sink_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last; +assign soc_sdram_bankmachine2_cmd_buffer_sink_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we; +assign soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +assign soc_sdram_bankmachine2_cmd_buffer_source_ready = (soc_sdram_bankmachine2_req_wdata_ready | soc_sdram_bankmachine2_req_rdata_valid); +assign soc_sdram_bankmachine2_req_lock = (soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine2_cmd_buffer_source_valid); +assign soc_sdram_bankmachine2_row_hit = (soc_sdram_bankmachine2_row == soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:7]); +assign soc_sdram_bankmachine2_cmd_payload_ba = 2'd2; + +// synthesis translate_off +reg dummy_d_162; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_cmd_payload_a <= 15'd0; + if (soc_sdram_bankmachine2_row_col_n_addr_sel) begin + soc_sdram_bankmachine2_cmd_payload_a <= soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:7]; + end else begin + soc_sdram_bankmachine2_cmd_payload_a <= ((soc_sdram_bankmachine2_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_162 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine2_twtpcon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_cmd_payload_is_write); +assign soc_sdram_bankmachine2_trccon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_row_open); +assign soc_sdram_bankmachine2_trascon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_row_open); + +// synthesis translate_off +reg dummy_d_163; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_auto_precharge <= 1'd0; + if ((soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine2_cmd_buffer_source_valid)) begin + if ((soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin + soc_sdram_bankmachine2_auto_precharge <= (soc_sdram_bankmachine2_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_163 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_first; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_last; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_164; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_sdram_bankmachine2_cmd_buffer_lookahead_replace) begin + soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine2_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_164 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_sdram_bankmachine2_cmd_buffer_lookahead_replace)); +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine2_cmd_buffer_lookahead_consume; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_sdram_bankmachine2_cmd_buffer_lookahead_level != 5'd16); +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0); +assign soc_sdram_bankmachine2_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine2_cmd_buffer_source_valid) | soc_sdram_bankmachine2_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_165; +// synthesis translate_on +always @(*) begin + vns_bankmachine2_next_state <= 4'd0; + vns_bankmachine2_next_state <= vns_bankmachine2_state; + case (vns_bankmachine2_state) + 1'd1: begin + if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin + if (soc_sdram_bankmachine2_cmd_ready) begin + vns_bankmachine2_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin + vns_bankmachine2_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_sdram_bankmachine2_trccon_ready) begin + if (soc_sdram_bankmachine2_cmd_ready) begin + vns_bankmachine2_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_sdram_bankmachine2_refresh_req)) begin + vns_bankmachine2_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine2_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine2_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine2_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine2_next_state <= 1'd0; + end + default: begin + if (soc_sdram_bankmachine2_refresh_req) begin + vns_bankmachine2_next_state <= 3'd4; + end else begin + if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine2_row_opened) begin + if (soc_sdram_bankmachine2_row_hit) begin + if ((soc_sdram_bankmachine2_cmd_ready & soc_sdram_bankmachine2_auto_precharge)) begin + vns_bankmachine2_next_state <= 2'd2; + end + end else begin + vns_bankmachine2_next_state <= 1'd1; + end + end else begin + vns_bankmachine2_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_165 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_166; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_cmd_payload_we <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin + soc_sdram_bankmachine2_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine2_refresh_req) begin + end else begin + if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine2_row_opened) begin + if (soc_sdram_bankmachine2_row_hit) begin + if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_166 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_167; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine2_trccon_ready) begin + soc_sdram_bankmachine2_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_167 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_168; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin + soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine2_trccon_ready) begin + soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_168 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_169; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine2_refresh_req) begin + end else begin + if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine2_row_opened) begin + if (soc_sdram_bankmachine2_row_hit) begin + if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine2_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_169 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_170; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine2_refresh_req) begin + end else begin + if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine2_row_opened) begin + if (soc_sdram_bankmachine2_row_hit) begin + if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine2_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_170 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_171; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_req_wdata_ready <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine2_refresh_req) begin + end else begin + if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine2_row_opened) begin + if (soc_sdram_bankmachine2_row_hit) begin + if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine2_req_wdata_ready <= soc_sdram_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_171 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_172; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_req_rdata_valid <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine2_refresh_req) begin + end else begin + if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine2_row_opened) begin + if (soc_sdram_bankmachine2_row_hit) begin + if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine2_req_rdata_valid <= soc_sdram_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_172 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_173; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_refresh_gnt <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_sdram_bankmachine2_twtpcon_ready) begin + soc_sdram_bankmachine2_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_173 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_174; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_cmd_valid <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin + soc_sdram_bankmachine2_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine2_trccon_ready) begin + soc_sdram_bankmachine2_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine2_refresh_req) begin + end else begin + if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine2_row_opened) begin + if (soc_sdram_bankmachine2_row_hit) begin + soc_sdram_bankmachine2_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_174 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_175; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_row_open <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine2_trccon_ready) begin + soc_sdram_bankmachine2_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_175 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_176; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_row_close <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + soc_sdram_bankmachine2_row_close <= 1'd1; + end + 2'd2: begin + soc_sdram_bankmachine2_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_sdram_bankmachine2_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_176 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_177; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_cmd_payload_cas <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine2_refresh_req) begin + end else begin + if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine2_row_opened) begin + if (soc_sdram_bankmachine2_row_hit) begin + soc_sdram_bankmachine2_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_177 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_178; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_cmd_payload_ras <= 1'd0; + case (vns_bankmachine2_state) + 1'd1: begin + if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin + soc_sdram_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine2_trccon_ready) begin + soc_sdram_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_178 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine3_req_valid; +assign soc_sdram_bankmachine3_req_ready = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine3_req_we; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine3_req_addr; +assign soc_sdram_bankmachine3_cmd_buffer_sink_valid = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine3_cmd_buffer_sink_ready; +assign soc_sdram_bankmachine3_cmd_buffer_sink_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first; +assign soc_sdram_bankmachine3_cmd_buffer_sink_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last; +assign soc_sdram_bankmachine3_cmd_buffer_sink_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we; +assign soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +assign soc_sdram_bankmachine3_cmd_buffer_source_ready = (soc_sdram_bankmachine3_req_wdata_ready | soc_sdram_bankmachine3_req_rdata_valid); +assign soc_sdram_bankmachine3_req_lock = (soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine3_cmd_buffer_source_valid); +assign soc_sdram_bankmachine3_row_hit = (soc_sdram_bankmachine3_row == soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:7]); +assign soc_sdram_bankmachine3_cmd_payload_ba = 2'd3; + +// synthesis translate_off +reg dummy_d_179; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_cmd_payload_a <= 15'd0; + if (soc_sdram_bankmachine3_row_col_n_addr_sel) begin + soc_sdram_bankmachine3_cmd_payload_a <= soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:7]; + end else begin + soc_sdram_bankmachine3_cmd_payload_a <= ((soc_sdram_bankmachine3_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_179 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine3_twtpcon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_cmd_payload_is_write); +assign soc_sdram_bankmachine3_trccon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_row_open); +assign soc_sdram_bankmachine3_trascon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_row_open); + +// synthesis translate_off +reg dummy_d_180; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_auto_precharge <= 1'd0; + if ((soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine3_cmd_buffer_source_valid)) begin + if ((soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin + soc_sdram_bankmachine3_auto_precharge <= (soc_sdram_bankmachine3_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_180 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_first; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_last; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_181; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_sdram_bankmachine3_cmd_buffer_lookahead_replace) begin + soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine3_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_181 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_sdram_bankmachine3_cmd_buffer_lookahead_replace)); +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine3_cmd_buffer_lookahead_consume; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_sdram_bankmachine3_cmd_buffer_lookahead_level != 5'd16); +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0); +assign soc_sdram_bankmachine3_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine3_cmd_buffer_source_valid) | soc_sdram_bankmachine3_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_182; +// synthesis translate_on +always @(*) begin + vns_bankmachine3_next_state <= 4'd0; + vns_bankmachine3_next_state <= vns_bankmachine3_state; + case (vns_bankmachine3_state) + 1'd1: begin + if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin + if (soc_sdram_bankmachine3_cmd_ready) begin + vns_bankmachine3_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin + vns_bankmachine3_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_sdram_bankmachine3_trccon_ready) begin + if (soc_sdram_bankmachine3_cmd_ready) begin + vns_bankmachine3_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_sdram_bankmachine3_refresh_req)) begin + vns_bankmachine3_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine3_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine3_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine3_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine3_next_state <= 1'd0; + end + default: begin + if (soc_sdram_bankmachine3_refresh_req) begin + vns_bankmachine3_next_state <= 3'd4; + end else begin + if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine3_row_opened) begin + if (soc_sdram_bankmachine3_row_hit) begin + if ((soc_sdram_bankmachine3_cmd_ready & soc_sdram_bankmachine3_auto_precharge)) begin + vns_bankmachine3_next_state <= 2'd2; + end + end else begin + vns_bankmachine3_next_state <= 1'd1; + end + end else begin + vns_bankmachine3_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_182 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_183; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_cmd_payload_we <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin + soc_sdram_bankmachine3_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine3_refresh_req) begin + end else begin + if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine3_row_opened) begin + if (soc_sdram_bankmachine3_row_hit) begin + if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_183 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_184; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine3_trccon_ready) begin + soc_sdram_bankmachine3_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_184 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_185; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin + soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine3_trccon_ready) begin + soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_185 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_186; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine3_refresh_req) begin + end else begin + if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine3_row_opened) begin + if (soc_sdram_bankmachine3_row_hit) begin + if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine3_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_186 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_187; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine3_refresh_req) begin + end else begin + if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine3_row_opened) begin + if (soc_sdram_bankmachine3_row_hit) begin + if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine3_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_187 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_188; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_req_wdata_ready <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine3_refresh_req) begin + end else begin + if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine3_row_opened) begin + if (soc_sdram_bankmachine3_row_hit) begin + if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine3_req_wdata_ready <= soc_sdram_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_188 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_189; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_req_rdata_valid <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine3_refresh_req) begin + end else begin + if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine3_row_opened) begin + if (soc_sdram_bankmachine3_row_hit) begin + if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine3_req_rdata_valid <= soc_sdram_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_189 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_190; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_refresh_gnt <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_sdram_bankmachine3_twtpcon_ready) begin + soc_sdram_bankmachine3_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_190 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_191; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_cmd_valid <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin + soc_sdram_bankmachine3_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine3_trccon_ready) begin + soc_sdram_bankmachine3_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine3_refresh_req) begin + end else begin + if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine3_row_opened) begin + if (soc_sdram_bankmachine3_row_hit) begin + soc_sdram_bankmachine3_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_191 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_192; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_row_open <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine3_trccon_ready) begin + soc_sdram_bankmachine3_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_192 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_193; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_row_close <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + soc_sdram_bankmachine3_row_close <= 1'd1; + end + 2'd2: begin + soc_sdram_bankmachine3_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_sdram_bankmachine3_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_193 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_194; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_cmd_payload_cas <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine3_refresh_req) begin + end else begin + if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine3_row_opened) begin + if (soc_sdram_bankmachine3_row_hit) begin + soc_sdram_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_194 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_195; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_cmd_payload_ras <= 1'd0; + case (vns_bankmachine3_state) + 1'd1: begin + if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin + soc_sdram_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine3_trccon_ready) begin + soc_sdram_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_195 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine4_req_valid; +assign soc_sdram_bankmachine4_req_ready = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine4_req_we; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine4_req_addr; +assign soc_sdram_bankmachine4_cmd_buffer_sink_valid = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine4_cmd_buffer_sink_ready; +assign soc_sdram_bankmachine4_cmd_buffer_sink_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first; +assign soc_sdram_bankmachine4_cmd_buffer_sink_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last; +assign soc_sdram_bankmachine4_cmd_buffer_sink_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we; +assign soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +assign soc_sdram_bankmachine4_cmd_buffer_source_ready = (soc_sdram_bankmachine4_req_wdata_ready | soc_sdram_bankmachine4_req_rdata_valid); +assign soc_sdram_bankmachine4_req_lock = (soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine4_cmd_buffer_source_valid); +assign soc_sdram_bankmachine4_row_hit = (soc_sdram_bankmachine4_row == soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[21:7]); +assign soc_sdram_bankmachine4_cmd_payload_ba = 3'd4; + +// synthesis translate_off +reg dummy_d_196; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_cmd_payload_a <= 15'd0; + if (soc_sdram_bankmachine4_row_col_n_addr_sel) begin + soc_sdram_bankmachine4_cmd_payload_a <= soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[21:7]; + end else begin + soc_sdram_bankmachine4_cmd_payload_a <= ((soc_sdram_bankmachine4_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_196 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine4_twtpcon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_cmd_payload_is_write); +assign soc_sdram_bankmachine4_trccon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_row_open); +assign soc_sdram_bankmachine4_trascon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_row_open); + +// synthesis translate_off +reg dummy_d_197; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_auto_precharge <= 1'd0; + if ((soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine4_cmd_buffer_source_valid)) begin + if ((soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin + soc_sdram_bankmachine4_auto_precharge <= (soc_sdram_bankmachine4_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_197 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_first; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_last; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_198; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_sdram_bankmachine4_cmd_buffer_lookahead_replace) begin + soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine4_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_198 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_sdram_bankmachine4_cmd_buffer_lookahead_replace)); +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine4_cmd_buffer_lookahead_consume; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_sdram_bankmachine4_cmd_buffer_lookahead_level != 5'd16); +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_sdram_bankmachine4_cmd_buffer_lookahead_level != 1'd0); +assign soc_sdram_bankmachine4_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine4_cmd_buffer_source_valid) | soc_sdram_bankmachine4_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_199; +// synthesis translate_on +always @(*) begin + vns_bankmachine4_next_state <= 4'd0; + vns_bankmachine4_next_state <= vns_bankmachine4_state; + case (vns_bankmachine4_state) + 1'd1: begin + if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin + if (soc_sdram_bankmachine4_cmd_ready) begin + vns_bankmachine4_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin + vns_bankmachine4_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_sdram_bankmachine4_trccon_ready) begin + if (soc_sdram_bankmachine4_cmd_ready) begin + vns_bankmachine4_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_sdram_bankmachine4_refresh_req)) begin + vns_bankmachine4_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine4_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine4_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine4_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine4_next_state <= 1'd0; + end + default: begin + if (soc_sdram_bankmachine4_refresh_req) begin + vns_bankmachine4_next_state <= 3'd4; + end else begin + if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine4_row_opened) begin + if (soc_sdram_bankmachine4_row_hit) begin + if ((soc_sdram_bankmachine4_cmd_ready & soc_sdram_bankmachine4_auto_precharge)) begin + vns_bankmachine4_next_state <= 2'd2; + end + end else begin + vns_bankmachine4_next_state <= 1'd1; + end + end else begin + vns_bankmachine4_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_199 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_200; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_cmd_payload_we <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin + soc_sdram_bankmachine4_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine4_refresh_req) begin + end else begin + if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine4_row_opened) begin + if (soc_sdram_bankmachine4_row_hit) begin + if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_200 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_201; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine4_trccon_ready) begin + soc_sdram_bankmachine4_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_201 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_202; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin + soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine4_trccon_ready) begin + soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_202 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_203; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine4_refresh_req) begin + end else begin + if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine4_row_opened) begin + if (soc_sdram_bankmachine4_row_hit) begin + if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine4_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_203 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_204; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine4_refresh_req) begin + end else begin + if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine4_row_opened) begin + if (soc_sdram_bankmachine4_row_hit) begin + if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine4_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_204 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_205; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_req_wdata_ready <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine4_refresh_req) begin + end else begin + if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine4_row_opened) begin + if (soc_sdram_bankmachine4_row_hit) begin + if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine4_req_wdata_ready <= soc_sdram_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_205 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_206; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_req_rdata_valid <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine4_refresh_req) begin + end else begin + if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine4_row_opened) begin + if (soc_sdram_bankmachine4_row_hit) begin + if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine4_req_rdata_valid <= soc_sdram_bankmachine4_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_206 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_207; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_refresh_gnt <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_sdram_bankmachine4_twtpcon_ready) begin + soc_sdram_bankmachine4_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_207 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_208; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_cmd_valid <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin + soc_sdram_bankmachine4_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine4_trccon_ready) begin + soc_sdram_bankmachine4_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine4_refresh_req) begin + end else begin + if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine4_row_opened) begin + if (soc_sdram_bankmachine4_row_hit) begin + soc_sdram_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_208 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_209; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_row_open <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine4_trccon_ready) begin + soc_sdram_bankmachine4_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_209 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_210; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_row_close <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + soc_sdram_bankmachine4_row_close <= 1'd1; + end + 2'd2: begin + soc_sdram_bankmachine4_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_sdram_bankmachine4_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_210 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_211; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_cmd_payload_cas <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine4_refresh_req) begin + end else begin + if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine4_row_opened) begin + if (soc_sdram_bankmachine4_row_hit) begin + soc_sdram_bankmachine4_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_211 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_212; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_cmd_payload_ras <= 1'd0; + case (vns_bankmachine4_state) + 1'd1: begin + if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin + soc_sdram_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine4_trccon_ready) begin + soc_sdram_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_212 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine5_req_valid; +assign soc_sdram_bankmachine5_req_ready = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine5_req_we; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine5_req_addr; +assign soc_sdram_bankmachine5_cmd_buffer_sink_valid = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine5_cmd_buffer_sink_ready; +assign soc_sdram_bankmachine5_cmd_buffer_sink_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first; +assign soc_sdram_bankmachine5_cmd_buffer_sink_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last; +assign soc_sdram_bankmachine5_cmd_buffer_sink_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we; +assign soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +assign soc_sdram_bankmachine5_cmd_buffer_source_ready = (soc_sdram_bankmachine5_req_wdata_ready | soc_sdram_bankmachine5_req_rdata_valid); +assign soc_sdram_bankmachine5_req_lock = (soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine5_cmd_buffer_source_valid); +assign soc_sdram_bankmachine5_row_hit = (soc_sdram_bankmachine5_row == soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[21:7]); +assign soc_sdram_bankmachine5_cmd_payload_ba = 3'd5; + +// synthesis translate_off +reg dummy_d_213; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_cmd_payload_a <= 15'd0; + if (soc_sdram_bankmachine5_row_col_n_addr_sel) begin + soc_sdram_bankmachine5_cmd_payload_a <= soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[21:7]; + end else begin + soc_sdram_bankmachine5_cmd_payload_a <= ((soc_sdram_bankmachine5_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_213 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine5_twtpcon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_cmd_payload_is_write); +assign soc_sdram_bankmachine5_trccon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_row_open); +assign soc_sdram_bankmachine5_trascon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_row_open); + +// synthesis translate_off +reg dummy_d_214; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_auto_precharge <= 1'd0; + if ((soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine5_cmd_buffer_source_valid)) begin + if ((soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin + soc_sdram_bankmachine5_auto_precharge <= (soc_sdram_bankmachine5_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_214 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_first; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_last; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_215; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_sdram_bankmachine5_cmd_buffer_lookahead_replace) begin + soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine5_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_215 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_sdram_bankmachine5_cmd_buffer_lookahead_replace)); +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine5_cmd_buffer_lookahead_consume; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_sdram_bankmachine5_cmd_buffer_lookahead_level != 5'd16); +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_sdram_bankmachine5_cmd_buffer_lookahead_level != 1'd0); +assign soc_sdram_bankmachine5_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine5_cmd_buffer_source_valid) | soc_sdram_bankmachine5_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_216; +// synthesis translate_on +always @(*) begin + vns_bankmachine5_next_state <= 4'd0; + vns_bankmachine5_next_state <= vns_bankmachine5_state; + case (vns_bankmachine5_state) + 1'd1: begin + if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin + if (soc_sdram_bankmachine5_cmd_ready) begin + vns_bankmachine5_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin + vns_bankmachine5_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_sdram_bankmachine5_trccon_ready) begin + if (soc_sdram_bankmachine5_cmd_ready) begin + vns_bankmachine5_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_sdram_bankmachine5_refresh_req)) begin + vns_bankmachine5_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine5_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine5_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine5_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine5_next_state <= 1'd0; + end + default: begin + if (soc_sdram_bankmachine5_refresh_req) begin + vns_bankmachine5_next_state <= 3'd4; + end else begin + if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine5_row_opened) begin + if (soc_sdram_bankmachine5_row_hit) begin + if ((soc_sdram_bankmachine5_cmd_ready & soc_sdram_bankmachine5_auto_precharge)) begin + vns_bankmachine5_next_state <= 2'd2; + end + end else begin + vns_bankmachine5_next_state <= 1'd1; + end + end else begin + vns_bankmachine5_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_216 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_217; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_cmd_payload_we <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin + soc_sdram_bankmachine5_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine5_refresh_req) begin + end else begin + if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine5_row_opened) begin + if (soc_sdram_bankmachine5_row_hit) begin + if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine5_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_217 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_218; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine5_trccon_ready) begin + soc_sdram_bankmachine5_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_218 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_219; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin + soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine5_trccon_ready) begin + soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_219 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_220; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine5_refresh_req) begin + end else begin + if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine5_row_opened) begin + if (soc_sdram_bankmachine5_row_hit) begin + if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine5_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_220 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_221; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine5_refresh_req) begin + end else begin + if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine5_row_opened) begin + if (soc_sdram_bankmachine5_row_hit) begin + if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine5_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_221 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_222; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_req_wdata_ready <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine5_refresh_req) begin + end else begin + if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine5_row_opened) begin + if (soc_sdram_bankmachine5_row_hit) begin + if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine5_req_wdata_ready <= soc_sdram_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_222 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_223; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_req_rdata_valid <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine5_refresh_req) begin + end else begin + if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine5_row_opened) begin + if (soc_sdram_bankmachine5_row_hit) begin + if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine5_req_rdata_valid <= soc_sdram_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_223 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_224; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_refresh_gnt <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_sdram_bankmachine5_twtpcon_ready) begin + soc_sdram_bankmachine5_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_224 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_225; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_cmd_valid <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin + soc_sdram_bankmachine5_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine5_trccon_ready) begin + soc_sdram_bankmachine5_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine5_refresh_req) begin + end else begin + if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine5_row_opened) begin + if (soc_sdram_bankmachine5_row_hit) begin + soc_sdram_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_225 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_226; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_row_open <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine5_trccon_ready) begin + soc_sdram_bankmachine5_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_226 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_227; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_row_close <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + soc_sdram_bankmachine5_row_close <= 1'd1; + end + 2'd2: begin + soc_sdram_bankmachine5_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_sdram_bankmachine5_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_227 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_228; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_cmd_payload_cas <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine5_refresh_req) begin + end else begin + if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine5_row_opened) begin + if (soc_sdram_bankmachine5_row_hit) begin + soc_sdram_bankmachine5_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_228 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_229; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_cmd_payload_ras <= 1'd0; + case (vns_bankmachine5_state) + 1'd1: begin + if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin + soc_sdram_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine5_trccon_ready) begin + soc_sdram_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_229 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine6_req_valid; +assign soc_sdram_bankmachine6_req_ready = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine6_req_we; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine6_req_addr; +assign soc_sdram_bankmachine6_cmd_buffer_sink_valid = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine6_cmd_buffer_sink_ready; +assign soc_sdram_bankmachine6_cmd_buffer_sink_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first; +assign soc_sdram_bankmachine6_cmd_buffer_sink_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last; +assign soc_sdram_bankmachine6_cmd_buffer_sink_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we; +assign soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +assign soc_sdram_bankmachine6_cmd_buffer_source_ready = (soc_sdram_bankmachine6_req_wdata_ready | soc_sdram_bankmachine6_req_rdata_valid); +assign soc_sdram_bankmachine6_req_lock = (soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine6_cmd_buffer_source_valid); +assign soc_sdram_bankmachine6_row_hit = (soc_sdram_bankmachine6_row == soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[21:7]); +assign soc_sdram_bankmachine6_cmd_payload_ba = 3'd6; + +// synthesis translate_off +reg dummy_d_230; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_cmd_payload_a <= 15'd0; + if (soc_sdram_bankmachine6_row_col_n_addr_sel) begin + soc_sdram_bankmachine6_cmd_payload_a <= soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[21:7]; + end else begin + soc_sdram_bankmachine6_cmd_payload_a <= ((soc_sdram_bankmachine6_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_230 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine6_twtpcon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_cmd_payload_is_write); +assign soc_sdram_bankmachine6_trccon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_row_open); +assign soc_sdram_bankmachine6_trascon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_row_open); + +// synthesis translate_off +reg dummy_d_231; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_auto_precharge <= 1'd0; + if ((soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine6_cmd_buffer_source_valid)) begin + if ((soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin + soc_sdram_bankmachine6_auto_precharge <= (soc_sdram_bankmachine6_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_231 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_first; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_last; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_232; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_sdram_bankmachine6_cmd_buffer_lookahead_replace) begin + soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine6_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_232 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_sdram_bankmachine6_cmd_buffer_lookahead_replace)); +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine6_cmd_buffer_lookahead_consume; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_sdram_bankmachine6_cmd_buffer_lookahead_level != 5'd16); +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_sdram_bankmachine6_cmd_buffer_lookahead_level != 1'd0); +assign soc_sdram_bankmachine6_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine6_cmd_buffer_source_valid) | soc_sdram_bankmachine6_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_233; +// synthesis translate_on +always @(*) begin + vns_bankmachine6_next_state <= 4'd0; + vns_bankmachine6_next_state <= vns_bankmachine6_state; + case (vns_bankmachine6_state) + 1'd1: begin + if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin + if (soc_sdram_bankmachine6_cmd_ready) begin + vns_bankmachine6_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin + vns_bankmachine6_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_sdram_bankmachine6_trccon_ready) begin + if (soc_sdram_bankmachine6_cmd_ready) begin + vns_bankmachine6_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_sdram_bankmachine6_refresh_req)) begin + vns_bankmachine6_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine6_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine6_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine6_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine6_next_state <= 1'd0; + end + default: begin + if (soc_sdram_bankmachine6_refresh_req) begin + vns_bankmachine6_next_state <= 3'd4; + end else begin + if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine6_row_opened) begin + if (soc_sdram_bankmachine6_row_hit) begin + if ((soc_sdram_bankmachine6_cmd_ready & soc_sdram_bankmachine6_auto_precharge)) begin + vns_bankmachine6_next_state <= 2'd2; + end + end else begin + vns_bankmachine6_next_state <= 1'd1; + end + end else begin + vns_bankmachine6_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_233 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_234; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_cmd_payload_we <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin + soc_sdram_bankmachine6_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine6_refresh_req) begin + end else begin + if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine6_row_opened) begin + if (soc_sdram_bankmachine6_row_hit) begin + if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_234 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_235; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine6_trccon_ready) begin + soc_sdram_bankmachine6_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_235 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_236; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin + soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine6_trccon_ready) begin + soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_236 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_237; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine6_refresh_req) begin + end else begin + if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine6_row_opened) begin + if (soc_sdram_bankmachine6_row_hit) begin + if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine6_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_237 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_238; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine6_refresh_req) begin + end else begin + if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine6_row_opened) begin + if (soc_sdram_bankmachine6_row_hit) begin + if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_238 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_239; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_req_wdata_ready <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine6_refresh_req) begin + end else begin + if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine6_row_opened) begin + if (soc_sdram_bankmachine6_row_hit) begin + if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine6_req_wdata_ready <= soc_sdram_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_239 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_240; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_req_rdata_valid <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine6_refresh_req) begin + end else begin + if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine6_row_opened) begin + if (soc_sdram_bankmachine6_row_hit) begin + if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine6_req_rdata_valid <= soc_sdram_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_240 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_241; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_refresh_gnt <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_sdram_bankmachine6_twtpcon_ready) begin + soc_sdram_bankmachine6_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_241 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_242; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_cmd_valid <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin + soc_sdram_bankmachine6_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine6_trccon_ready) begin + soc_sdram_bankmachine6_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine6_refresh_req) begin + end else begin + if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine6_row_opened) begin + if (soc_sdram_bankmachine6_row_hit) begin + soc_sdram_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_242 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_243; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_row_open <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine6_trccon_ready) begin + soc_sdram_bankmachine6_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_243 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_244; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_row_close <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + soc_sdram_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + soc_sdram_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_sdram_bankmachine6_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_244 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_245; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_cmd_payload_cas <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine6_refresh_req) begin + end else begin + if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine6_row_opened) begin + if (soc_sdram_bankmachine6_row_hit) begin + soc_sdram_bankmachine6_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_245 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_246; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_cmd_payload_ras <= 1'd0; + case (vns_bankmachine6_state) + 1'd1: begin + if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin + soc_sdram_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine6_trccon_ready) begin + soc_sdram_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_246 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine7_req_valid; +assign soc_sdram_bankmachine7_req_ready = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine7_req_we; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine7_req_addr; +assign soc_sdram_bankmachine7_cmd_buffer_sink_valid = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine7_cmd_buffer_sink_ready; +assign soc_sdram_bankmachine7_cmd_buffer_sink_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first; +assign soc_sdram_bankmachine7_cmd_buffer_sink_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last; +assign soc_sdram_bankmachine7_cmd_buffer_sink_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we; +assign soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +assign soc_sdram_bankmachine7_cmd_buffer_source_ready = (soc_sdram_bankmachine7_req_wdata_ready | soc_sdram_bankmachine7_req_rdata_valid); +assign soc_sdram_bankmachine7_req_lock = (soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine7_cmd_buffer_source_valid); +assign soc_sdram_bankmachine7_row_hit = (soc_sdram_bankmachine7_row == soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[21:7]); +assign soc_sdram_bankmachine7_cmd_payload_ba = 3'd7; + +// synthesis translate_off +reg dummy_d_247; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_cmd_payload_a <= 15'd0; + if (soc_sdram_bankmachine7_row_col_n_addr_sel) begin + soc_sdram_bankmachine7_cmd_payload_a <= soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[21:7]; + end else begin + soc_sdram_bankmachine7_cmd_payload_a <= ((soc_sdram_bankmachine7_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_247 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine7_twtpcon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_cmd_payload_is_write); +assign soc_sdram_bankmachine7_trccon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_row_open); +assign soc_sdram_bankmachine7_trascon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_row_open); + +// synthesis translate_off +reg dummy_d_248; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_auto_precharge <= 1'd0; + if ((soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine7_cmd_buffer_source_valid)) begin + if ((soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin + soc_sdram_bankmachine7_auto_precharge <= (soc_sdram_bankmachine7_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_248 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_first; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_last; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_249; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (soc_sdram_bankmachine7_cmd_buffer_lookahead_replace) begin + soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); + end else begin + soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine7_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_249 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_sdram_bankmachine7_cmd_buffer_lookahead_replace)); +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine7_cmd_buffer_lookahead_consume; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_sdram_bankmachine7_cmd_buffer_lookahead_level != 5'd16); +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_sdram_bankmachine7_cmd_buffer_lookahead_level != 1'd0); +assign soc_sdram_bankmachine7_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine7_cmd_buffer_source_valid) | soc_sdram_bankmachine7_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_250; +// synthesis translate_on +always @(*) begin + vns_bankmachine7_next_state <= 4'd0; + vns_bankmachine7_next_state <= vns_bankmachine7_state; + case (vns_bankmachine7_state) + 1'd1: begin + if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin + if (soc_sdram_bankmachine7_cmd_ready) begin + vns_bankmachine7_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin + vns_bankmachine7_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_sdram_bankmachine7_trccon_ready) begin + if (soc_sdram_bankmachine7_cmd_ready) begin + vns_bankmachine7_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_sdram_bankmachine7_refresh_req)) begin + vns_bankmachine7_next_state <= 1'd0; + end + end + 3'd5: begin + vns_bankmachine7_next_state <= 3'd6; + end + 3'd6: begin + vns_bankmachine7_next_state <= 2'd3; + end + 3'd7: begin + vns_bankmachine7_next_state <= 4'd8; + end + 4'd8: begin + vns_bankmachine7_next_state <= 1'd0; + end + default: begin + if (soc_sdram_bankmachine7_refresh_req) begin + vns_bankmachine7_next_state <= 3'd4; + end else begin + if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine7_row_opened) begin + if (soc_sdram_bankmachine7_row_hit) begin + if ((soc_sdram_bankmachine7_cmd_ready & soc_sdram_bankmachine7_auto_precharge)) begin + vns_bankmachine7_next_state <= 2'd2; + end + end else begin + vns_bankmachine7_next_state <= 1'd1; + end + end else begin + vns_bankmachine7_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_250 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_251; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_cmd_payload_we <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin + soc_sdram_bankmachine7_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine7_refresh_req) begin + end else begin + if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine7_row_opened) begin + if (soc_sdram_bankmachine7_row_hit) begin + if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_251 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_252; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine7_trccon_ready) begin + soc_sdram_bankmachine7_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_252 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_253; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin + soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine7_trccon_ready) begin + soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_253 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_254; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_cmd_payload_is_read <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine7_refresh_req) begin + end else begin + if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine7_row_opened) begin + if (soc_sdram_bankmachine7_row_hit) begin + if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine7_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_254 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_255; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_cmd_payload_is_write <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine7_refresh_req) begin + end else begin + if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine7_row_opened) begin + if (soc_sdram_bankmachine7_row_hit) begin + if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_255 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_256; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_req_wdata_ready <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine7_refresh_req) begin + end else begin + if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine7_row_opened) begin + if (soc_sdram_bankmachine7_row_hit) begin + if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin + soc_sdram_bankmachine7_req_wdata_ready <= soc_sdram_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_256 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_257; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_req_rdata_valid <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine7_refresh_req) begin + end else begin + if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine7_row_opened) begin + if (soc_sdram_bankmachine7_row_hit) begin + if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + soc_sdram_bankmachine7_req_rdata_valid <= soc_sdram_bankmachine7_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_257 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_258; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_refresh_gnt <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_sdram_bankmachine7_twtpcon_ready) begin + soc_sdram_bankmachine7_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_258 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_259; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_cmd_valid <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin + soc_sdram_bankmachine7_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine7_trccon_ready) begin + soc_sdram_bankmachine7_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine7_refresh_req) begin + end else begin + if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine7_row_opened) begin + if (soc_sdram_bankmachine7_row_hit) begin + soc_sdram_bankmachine7_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_259 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_260; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_row_open <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine7_trccon_ready) begin + soc_sdram_bankmachine7_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_260 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_261; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_row_close <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + soc_sdram_bankmachine7_row_close <= 1'd1; + end + 2'd2: begin + soc_sdram_bankmachine7_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_sdram_bankmachine7_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_261 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_262; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_cmd_payload_cas <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_sdram_bankmachine7_refresh_req) begin + end else begin + if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin + if (soc_sdram_bankmachine7_row_opened) begin + if (soc_sdram_bankmachine7_row_hit) begin + soc_sdram_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +// synthesis translate_off + dummy_d_262 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_263; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_cmd_payload_ras <= 1'd0; + case (vns_bankmachine7_state) + 1'd1: begin + if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin + soc_sdram_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_sdram_bankmachine7_trccon_ready) begin + soc_sdram_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_263 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_trrdcon_valid = ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & ((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))); +assign soc_sdram_tfawcon_valid = ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & ((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))); +assign soc_sdram_ras_allowed = (soc_sdram_trrdcon_ready & soc_sdram_tfawcon_ready); +assign soc_sdram_tccdcon_valid = ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_cmd_payload_is_write | soc_sdram_choose_req_cmd_payload_is_read)); +assign soc_sdram_cas_allowed = soc_sdram_tccdcon_ready; +assign soc_sdram_twtrcon_valid = ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write); +assign soc_sdram_read_available = ((((((((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_payload_is_read) | (soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_payload_is_read)) | (soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_payload_is_read)) | (soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_payload_is_read)) | (soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_payload_is_read)) | (soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_payload_is_read)) | (soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_payload_is_read)) | (soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_payload_is_read)); +assign soc_sdram_write_available = ((((((((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_payload_is_write) | (soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_payload_is_write)) | (soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_payload_is_write)) | (soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_payload_is_write)) | (soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_payload_is_write)) | (soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_payload_is_write)) | (soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_payload_is_write)) | (soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_payload_is_write)); +assign soc_sdram_max_time0 = (soc_sdram_time0 == 1'd0); +assign soc_sdram_max_time1 = (soc_sdram_time1 == 1'd0); +assign soc_sdram_bankmachine0_refresh_req = soc_sdram_cmd_valid; +assign soc_sdram_bankmachine1_refresh_req = soc_sdram_cmd_valid; +assign soc_sdram_bankmachine2_refresh_req = soc_sdram_cmd_valid; +assign soc_sdram_bankmachine3_refresh_req = soc_sdram_cmd_valid; +assign soc_sdram_bankmachine4_refresh_req = soc_sdram_cmd_valid; +assign soc_sdram_bankmachine5_refresh_req = soc_sdram_cmd_valid; +assign soc_sdram_bankmachine6_refresh_req = soc_sdram_cmd_valid; +assign soc_sdram_bankmachine7_refresh_req = soc_sdram_cmd_valid; +assign soc_sdram_go_to_refresh = (((((((soc_sdram_bankmachine0_refresh_gnt & soc_sdram_bankmachine1_refresh_gnt) & soc_sdram_bankmachine2_refresh_gnt) & soc_sdram_bankmachine3_refresh_gnt) & soc_sdram_bankmachine4_refresh_gnt) & soc_sdram_bankmachine5_refresh_gnt) & soc_sdram_bankmachine6_refresh_gnt) & soc_sdram_bankmachine7_refresh_gnt); +assign soc_sdram_interface_rdata = {soc_sdram_dfi_p3_rddata, soc_sdram_dfi_p2_rddata, soc_sdram_dfi_p1_rddata, soc_sdram_dfi_p0_rddata}; +assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata; +assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata; +assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata; +assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata; +assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we); +assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we); +assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we); +assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we); + +// synthesis translate_off +reg dummy_d_264; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_cmd_valids <= 8'd0; + soc_sdram_choose_cmd_valids[0] <= (soc_sdram_bankmachine0_cmd_valid & (((soc_sdram_bankmachine0_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine0_cmd_payload_ras & (~soc_sdram_bankmachine0_cmd_payload_cas)) & (~soc_sdram_bankmachine0_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine0_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine0_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); + soc_sdram_choose_cmd_valids[1] <= (soc_sdram_bankmachine1_cmd_valid & (((soc_sdram_bankmachine1_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine1_cmd_payload_ras & (~soc_sdram_bankmachine1_cmd_payload_cas)) & (~soc_sdram_bankmachine1_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine1_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine1_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); + soc_sdram_choose_cmd_valids[2] <= (soc_sdram_bankmachine2_cmd_valid & (((soc_sdram_bankmachine2_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine2_cmd_payload_ras & (~soc_sdram_bankmachine2_cmd_payload_cas)) & (~soc_sdram_bankmachine2_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine2_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine2_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); + soc_sdram_choose_cmd_valids[3] <= (soc_sdram_bankmachine3_cmd_valid & (((soc_sdram_bankmachine3_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine3_cmd_payload_ras & (~soc_sdram_bankmachine3_cmd_payload_cas)) & (~soc_sdram_bankmachine3_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine3_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine3_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); + soc_sdram_choose_cmd_valids[4] <= (soc_sdram_bankmachine4_cmd_valid & (((soc_sdram_bankmachine4_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine4_cmd_payload_ras & (~soc_sdram_bankmachine4_cmd_payload_cas)) & (~soc_sdram_bankmachine4_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine4_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine4_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); + soc_sdram_choose_cmd_valids[5] <= (soc_sdram_bankmachine5_cmd_valid & (((soc_sdram_bankmachine5_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine5_cmd_payload_ras & (~soc_sdram_bankmachine5_cmd_payload_cas)) & (~soc_sdram_bankmachine5_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine5_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine5_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); + soc_sdram_choose_cmd_valids[6] <= (soc_sdram_bankmachine6_cmd_valid & (((soc_sdram_bankmachine6_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine6_cmd_payload_ras & (~soc_sdram_bankmachine6_cmd_payload_cas)) & (~soc_sdram_bankmachine6_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine6_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine6_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); + soc_sdram_choose_cmd_valids[7] <= (soc_sdram_bankmachine7_cmd_valid & (((soc_sdram_bankmachine7_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine7_cmd_payload_ras & (~soc_sdram_bankmachine7_cmd_payload_cas)) & (~soc_sdram_bankmachine7_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine7_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine7_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); +// synthesis translate_off + dummy_d_264 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_choose_cmd_request = soc_sdram_choose_cmd_valids; +assign soc_sdram_choose_cmd_cmd_valid = vns_rhs_array_muxed0; +assign soc_sdram_choose_cmd_cmd_payload_a = vns_rhs_array_muxed1; +assign soc_sdram_choose_cmd_cmd_payload_ba = vns_rhs_array_muxed2; +assign soc_sdram_choose_cmd_cmd_payload_is_read = vns_rhs_array_muxed3; +assign soc_sdram_choose_cmd_cmd_payload_is_write = vns_rhs_array_muxed4; +assign soc_sdram_choose_cmd_cmd_payload_is_cmd = vns_rhs_array_muxed5; + +// synthesis translate_off +reg dummy_d_265; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_cmd_cmd_payload_cas <= 1'd0; + if (soc_sdram_choose_cmd_cmd_valid) begin + soc_sdram_choose_cmd_cmd_payload_cas <= vns_t_array_muxed0; + end +// synthesis translate_off + dummy_d_265 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_266; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_cmd_cmd_payload_ras <= 1'd0; + if (soc_sdram_choose_cmd_cmd_valid) begin + soc_sdram_choose_cmd_cmd_payload_ras <= vns_t_array_muxed1; + end +// synthesis translate_off + dummy_d_266 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_267; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_cmd_cmd_payload_we <= 1'd0; + if (soc_sdram_choose_cmd_cmd_valid) begin + soc_sdram_choose_cmd_cmd_payload_we <= vns_t_array_muxed2; + end +// synthesis translate_off + dummy_d_267 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_268; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine0_cmd_ready <= 1'd0; + if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 1'd0))) begin + soc_sdram_bankmachine0_cmd_ready <= 1'd1; + end + if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 1'd0))) begin + soc_sdram_bankmachine0_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_268 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_269; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine1_cmd_ready <= 1'd0; + if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 1'd1))) begin + soc_sdram_bankmachine1_cmd_ready <= 1'd1; + end + if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 1'd1))) begin + soc_sdram_bankmachine1_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_269 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_270; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine2_cmd_ready <= 1'd0; + if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 2'd2))) begin + soc_sdram_bankmachine2_cmd_ready <= 1'd1; + end + if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 2'd2))) begin + soc_sdram_bankmachine2_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_270 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_271; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine3_cmd_ready <= 1'd0; + if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 2'd3))) begin + soc_sdram_bankmachine3_cmd_ready <= 1'd1; + end + if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 2'd3))) begin + soc_sdram_bankmachine3_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_271 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_272; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine4_cmd_ready <= 1'd0; + if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd4))) begin + soc_sdram_bankmachine4_cmd_ready <= 1'd1; + end + if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd4))) begin + soc_sdram_bankmachine4_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_272 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_273; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine5_cmd_ready <= 1'd0; + if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd5))) begin + soc_sdram_bankmachine5_cmd_ready <= 1'd1; + end + if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd5))) begin + soc_sdram_bankmachine5_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_273 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_274; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine6_cmd_ready <= 1'd0; + if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd6))) begin + soc_sdram_bankmachine6_cmd_ready <= 1'd1; + end + if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd6))) begin + soc_sdram_bankmachine6_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_274 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_275; +// synthesis translate_on +always @(*) begin + soc_sdram_bankmachine7_cmd_ready <= 1'd0; + if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd7))) begin + soc_sdram_bankmachine7_cmd_ready <= 1'd1; + end + if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd7))) begin + soc_sdram_bankmachine7_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_275 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_choose_cmd_ce = (soc_sdram_choose_cmd_cmd_ready | (~soc_sdram_choose_cmd_cmd_valid)); + +// synthesis translate_off +reg dummy_d_276; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_req_valids <= 8'd0; + soc_sdram_choose_req_valids[0] <= (soc_sdram_bankmachine0_cmd_valid & (((soc_sdram_bankmachine0_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine0_cmd_payload_ras & (~soc_sdram_bankmachine0_cmd_payload_cas)) & (~soc_sdram_bankmachine0_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine0_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine0_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); + soc_sdram_choose_req_valids[1] <= (soc_sdram_bankmachine1_cmd_valid & (((soc_sdram_bankmachine1_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine1_cmd_payload_ras & (~soc_sdram_bankmachine1_cmd_payload_cas)) & (~soc_sdram_bankmachine1_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine1_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine1_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); + soc_sdram_choose_req_valids[2] <= (soc_sdram_bankmachine2_cmd_valid & (((soc_sdram_bankmachine2_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine2_cmd_payload_ras & (~soc_sdram_bankmachine2_cmd_payload_cas)) & (~soc_sdram_bankmachine2_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine2_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine2_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); + soc_sdram_choose_req_valids[3] <= (soc_sdram_bankmachine3_cmd_valid & (((soc_sdram_bankmachine3_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine3_cmd_payload_ras & (~soc_sdram_bankmachine3_cmd_payload_cas)) & (~soc_sdram_bankmachine3_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine3_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine3_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); + soc_sdram_choose_req_valids[4] <= (soc_sdram_bankmachine4_cmd_valid & (((soc_sdram_bankmachine4_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine4_cmd_payload_ras & (~soc_sdram_bankmachine4_cmd_payload_cas)) & (~soc_sdram_bankmachine4_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine4_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine4_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); + soc_sdram_choose_req_valids[5] <= (soc_sdram_bankmachine5_cmd_valid & (((soc_sdram_bankmachine5_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine5_cmd_payload_ras & (~soc_sdram_bankmachine5_cmd_payload_cas)) & (~soc_sdram_bankmachine5_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine5_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine5_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); + soc_sdram_choose_req_valids[6] <= (soc_sdram_bankmachine6_cmd_valid & (((soc_sdram_bankmachine6_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine6_cmd_payload_ras & (~soc_sdram_bankmachine6_cmd_payload_cas)) & (~soc_sdram_bankmachine6_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine6_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine6_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); + soc_sdram_choose_req_valids[7] <= (soc_sdram_bankmachine7_cmd_valid & (((soc_sdram_bankmachine7_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine7_cmd_payload_ras & (~soc_sdram_bankmachine7_cmd_payload_cas)) & (~soc_sdram_bankmachine7_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine7_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine7_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); +// synthesis translate_off + dummy_d_276 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_choose_req_request = soc_sdram_choose_req_valids; +assign soc_sdram_choose_req_cmd_valid = vns_rhs_array_muxed6; +assign soc_sdram_choose_req_cmd_payload_a = vns_rhs_array_muxed7; +assign soc_sdram_choose_req_cmd_payload_ba = vns_rhs_array_muxed8; +assign soc_sdram_choose_req_cmd_payload_is_read = vns_rhs_array_muxed9; +assign soc_sdram_choose_req_cmd_payload_is_write = vns_rhs_array_muxed10; +assign soc_sdram_choose_req_cmd_payload_is_cmd = vns_rhs_array_muxed11; + +// synthesis translate_off +reg dummy_d_277; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_req_cmd_payload_cas <= 1'd0; + if (soc_sdram_choose_req_cmd_valid) begin + soc_sdram_choose_req_cmd_payload_cas <= vns_t_array_muxed3; + end +// synthesis translate_off + dummy_d_277 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_278; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_req_cmd_payload_ras <= 1'd0; + if (soc_sdram_choose_req_cmd_valid) begin + soc_sdram_choose_req_cmd_payload_ras <= vns_t_array_muxed4; + end +// synthesis translate_off + dummy_d_278 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_279; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_req_cmd_payload_we <= 1'd0; + if (soc_sdram_choose_req_cmd_valid) begin + soc_sdram_choose_req_cmd_payload_we <= vns_t_array_muxed5; + end +// synthesis translate_off + dummy_d_279 = dummy_s; +// synthesis translate_on +end +assign soc_sdram_choose_req_ce = (soc_sdram_choose_req_cmd_ready | (~soc_sdram_choose_req_cmd_valid)); +assign soc_sdram_dfi_p0_reset_n = 1'd1; +assign soc_sdram_dfi_p0_cke = {1{soc_sdram_steerer0}}; +assign soc_sdram_dfi_p0_odt = {1{soc_sdram_steerer1}}; +assign soc_sdram_dfi_p1_reset_n = 1'd1; +assign soc_sdram_dfi_p1_cke = {1{soc_sdram_steerer2}}; +assign soc_sdram_dfi_p1_odt = {1{soc_sdram_steerer3}}; +assign soc_sdram_dfi_p2_reset_n = 1'd1; +assign soc_sdram_dfi_p2_cke = {1{soc_sdram_steerer4}}; +assign soc_sdram_dfi_p2_odt = {1{soc_sdram_steerer5}}; +assign soc_sdram_dfi_p3_reset_n = 1'd1; +assign soc_sdram_dfi_p3_cke = {1{soc_sdram_steerer6}}; +assign soc_sdram_dfi_p3_odt = {1{soc_sdram_steerer7}}; +assign soc_sdram_tfawcon_count = ((((soc_sdram_tfawcon_window[0] + soc_sdram_tfawcon_window[1]) + soc_sdram_tfawcon_window[2]) + soc_sdram_tfawcon_window[3]) + soc_sdram_tfawcon_window[4]); + +// synthesis translate_off +reg dummy_d_280; +// synthesis translate_on +always @(*) begin + vns_multiplexer_next_state <= 4'd0; + vns_multiplexer_next_state <= vns_multiplexer_state; + case (vns_multiplexer_state) + 1'd1: begin + if (soc_sdram_read_available) begin + if (((~soc_sdram_write_available) | soc_sdram_max_time1)) begin + vns_multiplexer_next_state <= 2'd3; + end + end + if (soc_sdram_go_to_refresh) begin + vns_multiplexer_next_state <= 2'd2; + end + end + 2'd2: begin + if (soc_sdram_cmd_last) begin + vns_multiplexer_next_state <= 1'd0; + end + end + 2'd3: begin + if (soc_sdram_twtrcon_ready) begin + vns_multiplexer_next_state <= 1'd0; + end + end + 3'd4: begin + vns_multiplexer_next_state <= 3'd5; + end + 3'd5: begin + vns_multiplexer_next_state <= 3'd6; + end + 3'd6: begin + vns_multiplexer_next_state <= 3'd7; + end + 3'd7: begin + vns_multiplexer_next_state <= 4'd8; + end + 4'd8: begin + vns_multiplexer_next_state <= 4'd9; + end + 4'd9: begin + vns_multiplexer_next_state <= 4'd10; + end + 4'd10: begin + vns_multiplexer_next_state <= 1'd1; + end + default: begin + if (soc_sdram_write_available) begin + if (((~soc_sdram_read_available) | soc_sdram_max_time0)) begin + vns_multiplexer_next_state <= 3'd4; + end + end + if (soc_sdram_go_to_refresh) begin + vns_multiplexer_next_state <= 2'd2; + end + end + endcase +// synthesis translate_off + dummy_d_280 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_281; +// synthesis translate_on +always @(*) begin + soc_sdram_steerer_sel0 <= 2'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_sdram_steerer_sel0 <= 1'd0; + end + 2'd2: begin + soc_sdram_steerer_sel0 <= 2'd3; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_sdram_steerer_sel0 <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_281 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_282; +// synthesis translate_on +always @(*) begin + soc_sdram_steerer_sel1 <= 2'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_sdram_steerer_sel1 <= 1'd0; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_sdram_steerer_sel1 <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_282 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_283; +// synthesis translate_on +always @(*) begin + soc_sdram_steerer_sel2 <= 2'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_sdram_steerer_sel2 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_sdram_steerer_sel2 <= 2'd2; + end + endcase +// synthesis translate_off + dummy_d_283 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_284; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_cmd_want_activates <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + soc_sdram_choose_cmd_want_activates <= soc_sdram_ras_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + soc_sdram_choose_cmd_want_activates <= soc_sdram_ras_allowed; + end + end + endcase +// synthesis translate_off + dummy_d_284 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_285; +// synthesis translate_on +always @(*) begin + soc_sdram_steerer_sel3 <= 2'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_sdram_steerer_sel3 <= 2'd2; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_sdram_steerer_sel3 <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_285 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_286; +// synthesis translate_on +always @(*) begin + soc_sdram_en0 <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_sdram_en0 <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_286 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_287; +// synthesis translate_on +always @(*) begin + soc_sdram_cmd_ready <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + soc_sdram_cmd_ready <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_287 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_288; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_cmd_cmd_ready <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + soc_sdram_choose_cmd_cmd_ready <= ((~((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))) | soc_sdram_ras_allowed); + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + soc_sdram_choose_cmd_cmd_ready <= ((~((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))) | soc_sdram_ras_allowed); + end + end + endcase +// synthesis translate_off + dummy_d_288 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_289; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_req_want_reads <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_sdram_choose_req_want_reads <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_289 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_290; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_req_want_writes <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_sdram_choose_req_want_writes <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_290 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_291; +// synthesis translate_on +always @(*) begin + soc_sdram_choose_req_cmd_ready <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + if (1'd0) begin + soc_sdram_choose_req_cmd_ready <= (soc_sdram_cas_allowed & ((~((soc_sdram_choose_req_cmd_payload_ras & (~soc_sdram_choose_req_cmd_payload_cas)) & (~soc_sdram_choose_req_cmd_payload_we))) | soc_sdram_ras_allowed)); + end else begin + soc_sdram_choose_req_cmd_ready <= soc_sdram_cas_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + soc_sdram_choose_req_cmd_ready <= (soc_sdram_cas_allowed & ((~((soc_sdram_choose_req_cmd_payload_ras & (~soc_sdram_choose_req_cmd_payload_cas)) & (~soc_sdram_choose_req_cmd_payload_we))) | soc_sdram_ras_allowed)); + end else begin + soc_sdram_choose_req_cmd_ready <= soc_sdram_cas_allowed; + end + end + endcase +// synthesis translate_off + dummy_d_291 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_292; +// synthesis translate_on +always @(*) begin + soc_sdram_en1 <= 1'd0; + case (vns_multiplexer_state) + 1'd1: begin + soc_sdram_en1 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_292 = dummy_s; +// synthesis translate_on +end +assign vns_roundrobin0_request = {(((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; +assign vns_roundrobin0_ce = ((~soc_sdram_interface_bank0_valid) & (~soc_sdram_interface_bank0_lock)); +assign soc_sdram_interface_bank0_addr = vns_rhs_array_muxed12; +assign soc_sdram_interface_bank0_we = vns_rhs_array_muxed13; +assign soc_sdram_interface_bank0_valid = vns_rhs_array_muxed14; +assign vns_roundrobin1_request = {(((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; +assign vns_roundrobin1_ce = ((~soc_sdram_interface_bank1_valid) & (~soc_sdram_interface_bank1_lock)); +assign soc_sdram_interface_bank1_addr = vns_rhs_array_muxed15; +assign soc_sdram_interface_bank1_we = vns_rhs_array_muxed16; +assign soc_sdram_interface_bank1_valid = vns_rhs_array_muxed17; +assign vns_roundrobin2_request = {(((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; +assign vns_roundrobin2_ce = ((~soc_sdram_interface_bank2_valid) & (~soc_sdram_interface_bank2_lock)); +assign soc_sdram_interface_bank2_addr = vns_rhs_array_muxed18; +assign soc_sdram_interface_bank2_we = vns_rhs_array_muxed19; +assign soc_sdram_interface_bank2_valid = vns_rhs_array_muxed20; +assign vns_roundrobin3_request = {(((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; +assign vns_roundrobin3_ce = ((~soc_sdram_interface_bank3_valid) & (~soc_sdram_interface_bank3_lock)); +assign soc_sdram_interface_bank3_addr = vns_rhs_array_muxed21; +assign soc_sdram_interface_bank3_we = vns_rhs_array_muxed22; +assign soc_sdram_interface_bank3_valid = vns_rhs_array_muxed23; +assign vns_roundrobin4_request = {(((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; +assign vns_roundrobin4_ce = ((~soc_sdram_interface_bank4_valid) & (~soc_sdram_interface_bank4_lock)); +assign soc_sdram_interface_bank4_addr = vns_rhs_array_muxed24; +assign soc_sdram_interface_bank4_we = vns_rhs_array_muxed25; +assign soc_sdram_interface_bank4_valid = vns_rhs_array_muxed26; +assign vns_roundrobin5_request = {(((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; +assign vns_roundrobin5_ce = ((~soc_sdram_interface_bank5_valid) & (~soc_sdram_interface_bank5_lock)); +assign soc_sdram_interface_bank5_addr = vns_rhs_array_muxed27; +assign soc_sdram_interface_bank5_we = vns_rhs_array_muxed28; +assign soc_sdram_interface_bank5_valid = vns_rhs_array_muxed29; +assign vns_roundrobin6_request = {(((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; +assign vns_roundrobin6_ce = ((~soc_sdram_interface_bank6_valid) & (~soc_sdram_interface_bank6_lock)); +assign soc_sdram_interface_bank6_addr = vns_rhs_array_muxed30; +assign soc_sdram_interface_bank6_we = vns_rhs_array_muxed31; +assign soc_sdram_interface_bank6_valid = vns_rhs_array_muxed32; +assign vns_roundrobin7_request = {(((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_port_cmd_valid)}; +assign vns_roundrobin7_ce = ((~soc_sdram_interface_bank7_valid) & (~soc_sdram_interface_bank7_lock)); +assign soc_sdram_interface_bank7_addr = vns_rhs_array_muxed33; +assign soc_sdram_interface_bank7_we = vns_rhs_array_muxed34; +assign soc_sdram_interface_bank7_valid = vns_rhs_array_muxed35; +assign soc_port_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0)))))) & soc_sdram_interface_bank7_ready)); +assign soc_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1)))))) & soc_sdram_interface_bank7_ready)); +assign soc_port_wdata_ready = vns_new_master_wdata_ready2; +assign soc_wdata_ready = vns_new_master_wdata_ready5; +assign soc_port_rdata_valid = vns_new_master_rdata_valid8; +assign soc_rdata_valid = vns_new_master_rdata_valid17; + +// synthesis translate_off +reg dummy_d_293; +// synthesis translate_on +always @(*) begin + soc_sdram_interface_wdata_we <= 16'd0; + case ({vns_new_master_wdata_ready5, vns_new_master_wdata_ready2}) + 1'd1: begin + soc_sdram_interface_wdata_we <= soc_port_wdata_payload_we; + end + 2'd2: begin + soc_sdram_interface_wdata_we <= soc_wdata_payload_we; + end + default: begin + soc_sdram_interface_wdata_we <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_293 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_294; +// synthesis translate_on +always @(*) begin + soc_sdram_interface_wdata <= 128'd0; + case ({vns_new_master_wdata_ready5, vns_new_master_wdata_ready2}) + 1'd1: begin + soc_sdram_interface_wdata <= soc_port_wdata_payload_data; + end + 2'd2: begin + soc_sdram_interface_wdata <= soc_wdata_payload_data; + end + default: begin + soc_sdram_interface_wdata <= 1'd0; + end + endcase +// synthesis translate_off + dummy_d_294 = dummy_s; +// synthesis translate_on +end +assign soc_port_rdata_payload_data = soc_sdram_interface_rdata; +assign soc_rdata_payload_data = soc_sdram_interface_rdata; +assign soc_address_d = soc_wb_sdram_adr; +assign soc_counter_offset = soc_address_q; +assign soc_counter_done = ((soc_counter + soc_counter_offset) == 2'd3); +assign soc_end_of_burst = ((~soc_wb_sdram_cyc) | (((soc_wb_sdram_stb & soc_wb_sdram_cyc) & soc_wb_sdram_ack) & ((soc_wb_sdram_cti == 3'd7) | soc_counter_done))); +assign soc_need_refill_reset = soc_end_of_burst; +assign soc_need_refill_d = 1'd0; +assign soc_litedram_wb_cti = 3'd7; +assign soc_litedram_wb_adr = soc_address_q[29:2]; +assign soc_cached_sels_reset0 = soc_counter_reset; + +// synthesis translate_off +reg dummy_d_295; +// synthesis translate_on +always @(*) begin + soc_cached_datas_flipflop0_d <= 32'd0; + if (soc_write) begin + soc_cached_datas_flipflop0_d <= soc_wb_sdram_dat_w; + end else begin + soc_cached_datas_flipflop0_d <= soc_litedram_wb_dat_r[31:0]; + end +// synthesis translate_off + dummy_d_295 = dummy_s; +// synthesis translate_on +end +assign soc_cached_sels_flipflop0_d = soc_wb_sdram_sel; + +// synthesis translate_off +reg dummy_d_296; +// synthesis translate_on +always @(*) begin + soc_cached_sels_ce0 <= 1'd0; + if (((soc_write & soc_write_sel0) | soc_refill)) begin + soc_cached_sels_ce0 <= 1'd1; + end +// synthesis translate_off + dummy_d_296 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_297; +// synthesis translate_on +always @(*) begin + soc_cached_datas_ce0 <= 1'd0; + if (((soc_write & soc_write_sel0) | soc_refill)) begin + soc_cached_datas_ce0 <= 1'd1; + end +// synthesis translate_off + dummy_d_297 = dummy_s; +// synthesis translate_on +end +assign soc_cached_sels_reset1 = soc_counter_reset; + +// synthesis translate_off +reg dummy_d_298; +// synthesis translate_on +always @(*) begin + soc_cached_datas_flipflop1_d <= 32'd0; + if (soc_write) begin + soc_cached_datas_flipflop1_d <= soc_wb_sdram_dat_w; + end else begin + soc_cached_datas_flipflop1_d <= soc_litedram_wb_dat_r[63:32]; + end +// synthesis translate_off + dummy_d_298 = dummy_s; +// synthesis translate_on +end +assign soc_cached_sels_flipflop1_d = soc_wb_sdram_sel; + +// synthesis translate_off +reg dummy_d_299; +// synthesis translate_on +always @(*) begin + soc_cached_sels_ce1 <= 1'd0; + if (((soc_write & soc_write_sel1) | soc_refill)) begin + soc_cached_sels_ce1 <= 1'd1; + end +// synthesis translate_off + dummy_d_299 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_300; +// synthesis translate_on +always @(*) begin + soc_cached_datas_ce1 <= 1'd0; + if (((soc_write & soc_write_sel1) | soc_refill)) begin + soc_cached_datas_ce1 <= 1'd1; + end +// synthesis translate_off + dummy_d_300 = dummy_s; +// synthesis translate_on +end +assign soc_cached_sels_reset2 = soc_counter_reset; + +// synthesis translate_off +reg dummy_d_301; +// synthesis translate_on +always @(*) begin + soc_cached_datas_flipflop2_d <= 32'd0; + if (soc_write) begin + soc_cached_datas_flipflop2_d <= soc_wb_sdram_dat_w; + end else begin + soc_cached_datas_flipflop2_d <= soc_litedram_wb_dat_r[95:64]; + end +// synthesis translate_off + dummy_d_301 = dummy_s; +// synthesis translate_on +end +assign soc_cached_sels_flipflop2_d = soc_wb_sdram_sel; + +// synthesis translate_off +reg dummy_d_302; +// synthesis translate_on +always @(*) begin + soc_cached_sels_ce2 <= 1'd0; + if (((soc_write & soc_write_sel2) | soc_refill)) begin + soc_cached_sels_ce2 <= 1'd1; + end +// synthesis translate_off + dummy_d_302 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_303; +// synthesis translate_on +always @(*) begin + soc_cached_datas_ce2 <= 1'd0; + if (((soc_write & soc_write_sel2) | soc_refill)) begin + soc_cached_datas_ce2 <= 1'd1; + end +// synthesis translate_off + dummy_d_303 = dummy_s; +// synthesis translate_on +end +assign soc_cached_sels_reset3 = soc_counter_reset; + +// synthesis translate_off +reg dummy_d_304; +// synthesis translate_on +always @(*) begin + soc_cached_datas_flipflop3_d <= 32'd0; + if (soc_write) begin + soc_cached_datas_flipflop3_d <= soc_wb_sdram_dat_w; + end else begin + soc_cached_datas_flipflop3_d <= soc_litedram_wb_dat_r[127:96]; + end +// synthesis translate_off + dummy_d_304 = dummy_s; +// synthesis translate_on +end +assign soc_cached_sels_flipflop3_d = soc_wb_sdram_sel; + +// synthesis translate_off +reg dummy_d_305; +// synthesis translate_on +always @(*) begin + soc_cached_sels_ce3 <= 1'd0; + if (((soc_write & soc_write_sel3) | soc_refill)) begin + soc_cached_sels_ce3 <= 1'd1; + end +// synthesis translate_off + dummy_d_305 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_306; +// synthesis translate_on +always @(*) begin + soc_cached_datas_ce3 <= 1'd0; + if (((soc_write & soc_write_sel3) | soc_refill)) begin + soc_cached_datas_ce3 <= 1'd1; + end +// synthesis translate_off + dummy_d_306 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_307; +// synthesis translate_on +always @(*) begin + soc_write_sel1 <= 1'd0; + case ((soc_counter + soc_counter_offset)) + 1'd0: begin + end + 1'd1: begin + soc_write_sel1 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + endcase +// synthesis translate_off + dummy_d_307 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_308; +// synthesis translate_on +always @(*) begin + soc_write_sel0 <= 1'd0; + case ((soc_counter + soc_counter_offset)) + 1'd0: begin + soc_write_sel0 <= 1'd1; + end + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + endcase +// synthesis translate_off + dummy_d_308 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_309; +// synthesis translate_on +always @(*) begin + soc_write_sel2 <= 1'd0; + case ((soc_counter + soc_counter_offset)) + 1'd0: begin + end + 1'd1: begin + end + 2'd2: begin + soc_write_sel2 <= 1'd1; + end + 2'd3: begin + end + endcase +// synthesis translate_off + dummy_d_309 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_310; +// synthesis translate_on +always @(*) begin + soc_write_sel3 <= 1'd0; + case ((soc_counter + soc_counter_offset)) + 1'd0: begin + end + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + soc_write_sel3 <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_310 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_311; +// synthesis translate_on +always @(*) begin + soc_wb_sdram_dat_r <= 32'd0; + case (soc_address_q[1:0]) + 1'd0: begin + soc_wb_sdram_dat_r <= soc_cached_datas_flipflop0_q; + end + 1'd1: begin + soc_wb_sdram_dat_r <= soc_cached_datas_flipflop1_q; + end + 2'd2: begin + soc_wb_sdram_dat_r <= soc_cached_datas_flipflop2_q; + end + 2'd3: begin + soc_wb_sdram_dat_r <= soc_cached_datas_flipflop3_q; + end + endcase +// synthesis translate_off + dummy_d_311 = dummy_s; +// synthesis translate_on +end +assign soc_cached_data = {soc_cached_datas_flipflop3_q, soc_cached_datas_flipflop2_q, soc_cached_datas_flipflop1_q, soc_cached_datas_flipflop0_q}; +assign soc_cached_sel = {soc_cached_sels_flipflop3_q, soc_cached_sels_flipflop2_q, soc_cached_sels_flipflop1_q, soc_cached_sels_flipflop0_q}; + +// synthesis translate_off +reg dummy_d_312; +// synthesis translate_on +always @(*) begin + vns_converter_next_state <= 3'd0; + vns_converter_next_state <= vns_converter_state; + case (vns_converter_state) + 1'd1: begin + if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin + if (soc_counter_done) begin + vns_converter_next_state <= 2'd2; + end + end else begin + if ((~soc_wb_sdram_cyc)) begin + vns_converter_next_state <= 2'd2; + end + end + end + 2'd2: begin + if (soc_litedram_wb_ack) begin + vns_converter_next_state <= 1'd0; + end + end + 2'd3: begin + if (soc_litedram_wb_ack) begin + vns_converter_next_state <= 3'd4; + end + end + 3'd4: begin + vns_converter_next_state <= 1'd0; + end + default: begin + if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin + if (soc_wb_sdram_we) begin + vns_converter_next_state <= 1'd1; + end else begin + if (soc_need_refill_q) begin + vns_converter_next_state <= 2'd3; + end else begin + vns_converter_next_state <= 3'd4; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_312 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_313; +// synthesis translate_on +always @(*) begin + soc_address_ce <= 1'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + default: begin + if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin + soc_address_ce <= 1'd1; + end + end + endcase +// synthesis translate_off + dummy_d_313 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_314; +// synthesis translate_on +always @(*) begin + soc_litedram_wb_dat_w <= 128'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + soc_litedram_wb_dat_w <= soc_cached_data; + end + 2'd3: begin + end + 3'd4: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_314 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_315; +// synthesis translate_on +always @(*) begin + soc_litedram_wb_sel <= 16'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + soc_litedram_wb_sel <= soc_cached_sel; + end + 2'd3: begin + end + 3'd4: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_315 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_316; +// synthesis translate_on +always @(*) begin + soc_counter_ce <= 1'd0; + case (vns_converter_state) + 1'd1: begin + if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin + soc_counter_ce <= 1'd1; + end else begin + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_316 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_317; +// synthesis translate_on +always @(*) begin + soc_litedram_wb_cyc <= 1'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + soc_litedram_wb_cyc <= 1'd1; + end + 2'd3: begin + soc_litedram_wb_cyc <= 1'd1; + end + 3'd4: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_317 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_318; +// synthesis translate_on +always @(*) begin + soc_counter_reset <= 1'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + default: begin + soc_counter_reset <= 1'd1; + end + endcase +// synthesis translate_off + dummy_d_318 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_319; +// synthesis translate_on +always @(*) begin + soc_litedram_wb_stb <= 1'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + soc_litedram_wb_stb <= 1'd1; + end + 2'd3: begin + soc_litedram_wb_stb <= 1'd1; + end + 3'd4: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_319 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_320; +// synthesis translate_on +always @(*) begin + soc_need_refill_ce <= 1'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedram_wb_ack) begin + soc_need_refill_ce <= 1'd1; + end + end + 3'd4: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_320 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_321; +// synthesis translate_on +always @(*) begin + soc_litedram_wb_we <= 1'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + soc_litedram_wb_we <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_321 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_322; +// synthesis translate_on +always @(*) begin + soc_write <= 1'd0; + case (vns_converter_state) + 1'd1: begin + if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin + soc_write <= 1'd1; + end else begin + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_322 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_323; +// synthesis translate_on +always @(*) begin + soc_wb_sdram_ack <= 1'd0; + case (vns_converter_state) + 1'd1: begin + if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin + soc_wb_sdram_ack <= 1'd1; + end else begin + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin + soc_wb_sdram_ack <= 1'd1; + end + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_323 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_324; +// synthesis translate_on +always @(*) begin + soc_evict <= 1'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + soc_evict <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_324 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_325; +// synthesis translate_on +always @(*) begin + soc_refill <= 1'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + soc_refill <= 1'd1; + end + 3'd4: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_325 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_326; +// synthesis translate_on +always @(*) begin + soc_read <= 1'd0; + case (vns_converter_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + soc_read <= 1'd1; + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_326 = dummy_s; +// synthesis translate_on +end +assign soc_wdata_converter_sink_valid = ((soc_litedram_wb_cyc & soc_litedram_wb_stb) & soc_litedram_wb_we); +assign soc_wdata_converter_sink_payload_data = soc_litedram_wb_dat_w; +assign soc_wdata_converter_sink_payload_we = soc_litedram_wb_sel; +assign soc_port_wdata_valid = soc_wdata_converter_source_valid; +assign soc_wdata_converter_source_ready = soc_port_wdata_ready; +assign soc_port_wdata_first = soc_wdata_converter_source_first; +assign soc_port_wdata_last = soc_wdata_converter_source_last; +assign soc_port_wdata_payload_data = soc_wdata_converter_source_payload_data; +assign soc_port_wdata_payload_we = soc_wdata_converter_source_payload_we; +assign soc_rdata_converter_sink_valid = soc_port_rdata_valid; +assign soc_port_rdata_ready = soc_rdata_converter_sink_ready; +assign soc_rdata_converter_sink_first = soc_port_rdata_first; +assign soc_rdata_converter_sink_last = soc_port_rdata_last; +assign soc_rdata_converter_sink_payload_data = soc_port_rdata_payload_data; +assign soc_rdata_converter_source_ready = 1'd1; +assign soc_litedram_wb_dat_r = soc_rdata_converter_source_payload_data; +assign soc_wdata_converter_converter_sink_valid = soc_wdata_converter_sink_valid; +assign soc_wdata_converter_converter_sink_first = soc_wdata_converter_sink_first; +assign soc_wdata_converter_converter_sink_last = soc_wdata_converter_sink_last; +assign soc_wdata_converter_sink_ready = soc_wdata_converter_converter_sink_ready; +assign soc_wdata_converter_converter_sink_payload_data = {soc_wdata_converter_sink_payload_we, soc_wdata_converter_sink_payload_data}; +assign soc_wdata_converter_source_valid = soc_wdata_converter_source_source_valid; +assign soc_wdata_converter_source_first = soc_wdata_converter_source_source_first; +assign soc_wdata_converter_source_last = soc_wdata_converter_source_source_last; +assign soc_wdata_converter_source_source_ready = soc_wdata_converter_source_ready; +assign {soc_wdata_converter_source_payload_we, soc_wdata_converter_source_payload_data} = soc_wdata_converter_source_source_payload_data; +assign {soc_wdata_converter_source_payload_we, soc_wdata_converter_source_payload_data} = soc_wdata_converter_source_source_payload_data; +assign soc_wdata_converter_source_source_valid = soc_wdata_converter_converter_source_valid; +assign soc_wdata_converter_converter_source_ready = soc_wdata_converter_source_source_ready; +assign soc_wdata_converter_source_source_first = soc_wdata_converter_converter_source_first; +assign soc_wdata_converter_source_source_last = soc_wdata_converter_converter_source_last; +assign soc_wdata_converter_source_source_payload_data = soc_wdata_converter_converter_source_payload_data; +assign soc_wdata_converter_converter_source_valid = soc_wdata_converter_converter_sink_valid; +assign soc_wdata_converter_converter_sink_ready = soc_wdata_converter_converter_source_ready; +assign soc_wdata_converter_converter_source_first = soc_wdata_converter_converter_sink_first; +assign soc_wdata_converter_converter_source_last = soc_wdata_converter_converter_sink_last; +assign soc_wdata_converter_converter_source_payload_data = soc_wdata_converter_converter_sink_payload_data; +assign soc_wdata_converter_converter_source_payload_valid_token_count = 1'd1; +assign soc_rdata_converter_converter_sink_valid = soc_rdata_converter_sink_valid; +assign soc_rdata_converter_converter_sink_first = soc_rdata_converter_sink_first; +assign soc_rdata_converter_converter_sink_last = soc_rdata_converter_sink_last; +assign soc_rdata_converter_sink_ready = soc_rdata_converter_converter_sink_ready; +assign soc_rdata_converter_converter_sink_payload_data = {soc_rdata_converter_sink_payload_data}; +assign soc_rdata_converter_source_valid = soc_rdata_converter_source_source_valid; +assign soc_rdata_converter_source_first = soc_rdata_converter_source_source_first; +assign soc_rdata_converter_source_last = soc_rdata_converter_source_source_last; +assign soc_rdata_converter_source_source_ready = soc_rdata_converter_source_ready; +assign {soc_rdata_converter_source_payload_data} = soc_rdata_converter_source_source_payload_data; +assign soc_rdata_converter_source_source_valid = soc_rdata_converter_converter_source_valid; +assign soc_rdata_converter_converter_source_ready = soc_rdata_converter_source_source_ready; +assign soc_rdata_converter_source_source_first = soc_rdata_converter_converter_source_first; +assign soc_rdata_converter_source_source_last = soc_rdata_converter_converter_source_last; +assign soc_rdata_converter_source_source_payload_data = soc_rdata_converter_converter_source_payload_data; +assign soc_rdata_converter_converter_source_valid = soc_rdata_converter_converter_sink_valid; +assign soc_rdata_converter_converter_sink_ready = soc_rdata_converter_converter_source_ready; +assign soc_rdata_converter_converter_source_first = soc_rdata_converter_converter_sink_first; +assign soc_rdata_converter_converter_source_last = soc_rdata_converter_converter_sink_last; +assign soc_rdata_converter_converter_source_payload_data = soc_rdata_converter_converter_sink_payload_data; +assign soc_rdata_converter_converter_source_payload_valid_token_count = 1'd1; + +// synthesis translate_off +reg dummy_d_327; +// synthesis translate_on +always @(*) begin + vns_litedramwishbone2native_next_state <= 2'd0; + vns_litedramwishbone2native_next_state <= vns_litedramwishbone2native_state; + case (vns_litedramwishbone2native_state) + 1'd1: begin + if (soc_wdata_converter_sink_ready) begin + vns_litedramwishbone2native_next_state <= 1'd0; + end + end + 2'd2: begin + if (soc_rdata_converter_source_valid) begin + vns_litedramwishbone2native_next_state <= 1'd0; + end + end + default: begin + if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin + if ((soc_count == 1'd0)) begin + if (soc_litedram_wb_we) begin + vns_litedramwishbone2native_next_state <= 1'd1; + end else begin + vns_litedramwishbone2native_next_state <= 2'd2; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_327 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_328; +// synthesis translate_on +always @(*) begin + soc_count_next_value_ce <= 1'd0; + case (vns_litedramwishbone2native_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin + soc_count_next_value_ce <= 1'd1; + if ((soc_count == 1'd0)) begin + soc_count_next_value_ce <= 1'd1; + end + end + end + endcase +// synthesis translate_off + dummy_d_328 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_329; +// synthesis translate_on +always @(*) begin + soc_port_cmd_valid <= 1'd0; + case (vns_litedramwishbone2native_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + soc_port_cmd_valid <= (soc_litedram_wb_cyc & soc_litedram_wb_stb); + end + endcase +// synthesis translate_off + dummy_d_329 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_330; +// synthesis translate_on +always @(*) begin + soc_litedram_wb_ack <= 1'd0; + case (vns_litedramwishbone2native_state) + 1'd1: begin + if (soc_wdata_converter_sink_ready) begin + soc_litedram_wb_ack <= 1'd1; + end + end + 2'd2: begin + if (soc_rdata_converter_source_valid) begin + soc_litedram_wb_ack <= 1'd1; + end + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_330 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_331; +// synthesis translate_on +always @(*) begin + soc_port_cmd_payload_we <= 1'd0; + case (vns_litedramwishbone2native_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + soc_port_cmd_payload_we <= soc_litedram_wb_we; + end + endcase +// synthesis translate_off + dummy_d_331 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_332; +// synthesis translate_on +always @(*) begin + soc_port_cmd_payload_addr <= 25'd0; + case (vns_litedramwishbone2native_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + soc_port_cmd_payload_addr <= (((soc_litedram_wb_adr * 1'd1) + soc_count) - 27'd67108864); + end + endcase +// synthesis translate_off + dummy_d_332 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_333; +// synthesis translate_on +always @(*) begin + soc_count_next_value <= 1'd0; + case (vns_litedramwishbone2native_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin + soc_count_next_value <= (soc_count + 1'd1); + if ((soc_count == 1'd0)) begin + soc_count_next_value <= 1'd0; + end + end + end + endcase +// synthesis translate_off + dummy_d_333 = dummy_s; +// synthesis translate_on +end +assign vns_shared_adr = vns_rhs_array_muxed36; +assign vns_shared_dat_w = vns_rhs_array_muxed37; +assign vns_shared_sel = vns_rhs_array_muxed38; +assign vns_shared_cyc = vns_rhs_array_muxed39; +assign vns_shared_stb = vns_rhs_array_muxed40; +assign vns_shared_we = vns_rhs_array_muxed41; +assign vns_shared_cti = vns_rhs_array_muxed42; +assign vns_shared_bte = vns_rhs_array_muxed43; +assign soc_litedramcore_cpu_ibus_dat_r = vns_shared_dat_r; +assign soc_litedramcore_cpu_dbus_dat_r = vns_shared_dat_r; +assign soc_litedramcore_cpu_ibus_ack = (vns_shared_ack & (vns_grant == 1'd0)); +assign soc_litedramcore_cpu_dbus_ack = (vns_shared_ack & (vns_grant == 1'd1)); +assign soc_litedramcore_cpu_ibus_err = (vns_shared_err & (vns_grant == 1'd0)); +assign soc_litedramcore_cpu_dbus_err = (vns_shared_err & (vns_grant == 1'd1)); +assign vns_request = {soc_litedramcore_cpu_dbus_cyc, soc_litedramcore_cpu_ibus_cyc}; + +// synthesis translate_off +reg dummy_d_334; +// synthesis translate_on +always @(*) begin + vns_slave_sel <= 4'd0; + vns_slave_sel[0] <= (vns_shared_adr[29:13] == 1'd0); + vns_slave_sel[1] <= (vns_shared_adr[29:10] == 13'd4096); + vns_slave_sel[2] <= (vns_shared_adr[29:14] == 16'd33280); + vns_slave_sel[3] <= (vns_shared_adr[29:22] == 7'd64); +// synthesis translate_off + dummy_d_334 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_litedramcore_ram_bus_adr = vns_shared_adr; +assign soc_litedramcore_litedramcore_ram_bus_dat_w = vns_shared_dat_w; +assign soc_litedramcore_litedramcore_ram_bus_sel = vns_shared_sel; +assign soc_litedramcore_litedramcore_ram_bus_stb = vns_shared_stb; +assign soc_litedramcore_litedramcore_ram_bus_we = vns_shared_we; +assign soc_litedramcore_litedramcore_ram_bus_cti = vns_shared_cti; +assign soc_litedramcore_litedramcore_ram_bus_bte = vns_shared_bte; +assign soc_litedramcore_ram_bus_ram_bus_adr = vns_shared_adr; +assign soc_litedramcore_ram_bus_ram_bus_dat_w = vns_shared_dat_w; +assign soc_litedramcore_ram_bus_ram_bus_sel = vns_shared_sel; +assign soc_litedramcore_ram_bus_ram_bus_stb = vns_shared_stb; +assign soc_litedramcore_ram_bus_ram_bus_we = vns_shared_we; +assign soc_litedramcore_ram_bus_ram_bus_cti = vns_shared_cti; +assign soc_litedramcore_ram_bus_ram_bus_bte = vns_shared_bte; +assign soc_litedramcore_bus_wishbone_adr = vns_shared_adr; +assign soc_litedramcore_bus_wishbone_dat_w = vns_shared_dat_w; +assign soc_litedramcore_bus_wishbone_sel = vns_shared_sel; +assign soc_litedramcore_bus_wishbone_stb = vns_shared_stb; +assign soc_litedramcore_bus_wishbone_we = vns_shared_we; +assign soc_litedramcore_bus_wishbone_cti = vns_shared_cti; +assign soc_litedramcore_bus_wishbone_bte = vns_shared_bte; +assign soc_wb_sdram_adr = vns_shared_adr; +assign soc_wb_sdram_dat_w = vns_shared_dat_w; +assign soc_wb_sdram_sel = vns_shared_sel; +assign soc_wb_sdram_stb = vns_shared_stb; +assign soc_wb_sdram_we = vns_shared_we; +assign soc_wb_sdram_cti = vns_shared_cti; +assign soc_wb_sdram_bte = vns_shared_bte; +assign soc_litedramcore_litedramcore_ram_bus_cyc = (vns_shared_cyc & vns_slave_sel[0]); +assign soc_litedramcore_ram_bus_ram_bus_cyc = (vns_shared_cyc & vns_slave_sel[1]); +assign soc_litedramcore_bus_wishbone_cyc = (vns_shared_cyc & vns_slave_sel[2]); +assign soc_wb_sdram_cyc = (vns_shared_cyc & vns_slave_sel[3]); + +// synthesis translate_off +reg dummy_d_335; +// synthesis translate_on +always @(*) begin + vns_shared_ack <= 1'd0; + vns_shared_ack <= (((soc_litedramcore_litedramcore_ram_bus_ack | soc_litedramcore_ram_bus_ram_bus_ack) | soc_litedramcore_bus_wishbone_ack) | soc_wb_sdram_ack); + if (vns_done) begin + vns_shared_ack <= 1'd1; + end +// synthesis translate_off + dummy_d_335 = dummy_s; +// synthesis translate_on +end +assign vns_shared_err = (((soc_litedramcore_litedramcore_ram_bus_err | soc_litedramcore_ram_bus_ram_bus_err) | soc_litedramcore_bus_wishbone_err) | soc_wb_sdram_err); + +// synthesis translate_off +reg dummy_d_336; +// synthesis translate_on +always @(*) begin + vns_shared_dat_r <= 32'd0; + vns_shared_dat_r <= (((({32{vns_slave_sel_r[0]}} & soc_litedramcore_litedramcore_ram_bus_dat_r) | ({32{vns_slave_sel_r[1]}} & soc_litedramcore_ram_bus_ram_bus_dat_r)) | ({32{vns_slave_sel_r[2]}} & soc_litedramcore_bus_wishbone_dat_r)) | ({32{vns_slave_sel_r[3]}} & soc_wb_sdram_dat_r)); + if (vns_done) begin + vns_shared_dat_r <= 32'd4294967295; + end +// synthesis translate_off + dummy_d_336 = dummy_s; +// synthesis translate_on +end +assign vns_wait = ((vns_shared_stb & vns_shared_cyc) & (~vns_shared_ack)); + +// synthesis translate_off +reg dummy_d_337; +// synthesis translate_on +always @(*) begin + vns_error <= 1'd0; + if (vns_done) begin + vns_error <= 1'd1; + end +// synthesis translate_off + dummy_d_337 = dummy_s; +// synthesis translate_on +end +assign vns_done = (vns_count == 1'd0); +assign vns_csrbank0_sel = (vns_interface0_bank_bus_adr[13:9] == 1'd0); +assign vns_csrbank0_reset0_r = vns_interface0_bank_bus_dat_w[0]; +assign vns_csrbank0_reset0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 1'd0)); +assign vns_csrbank0_reset0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 1'd0)); +assign vns_csrbank0_scratch3_r = vns_interface0_bank_bus_dat_w[7:0]; +assign vns_csrbank0_scratch3_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 1'd1)); +assign vns_csrbank0_scratch3_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 1'd1)); +assign vns_csrbank0_scratch2_r = vns_interface0_bank_bus_dat_w[7:0]; +assign vns_csrbank0_scratch2_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 2'd2)); +assign vns_csrbank0_scratch2_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 2'd2)); +assign vns_csrbank0_scratch1_r = vns_interface0_bank_bus_dat_w[7:0]; +assign vns_csrbank0_scratch1_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 2'd3)); +assign vns_csrbank0_scratch1_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 2'd3)); +assign vns_csrbank0_scratch0_r = vns_interface0_bank_bus_dat_w[7:0]; +assign vns_csrbank0_scratch0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd4)); +assign vns_csrbank0_scratch0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd4)); +assign vns_csrbank0_bus_errors3_r = vns_interface0_bank_bus_dat_w[7:0]; +assign vns_csrbank0_bus_errors3_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd5)); +assign vns_csrbank0_bus_errors3_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd5)); +assign vns_csrbank0_bus_errors2_r = vns_interface0_bank_bus_dat_w[7:0]; +assign vns_csrbank0_bus_errors2_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd6)); +assign vns_csrbank0_bus_errors2_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd6)); +assign vns_csrbank0_bus_errors1_r = vns_interface0_bank_bus_dat_w[7:0]; +assign vns_csrbank0_bus_errors1_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd7)); +assign vns_csrbank0_bus_errors1_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd7)); +assign vns_csrbank0_bus_errors0_r = vns_interface0_bank_bus_dat_w[7:0]; +assign vns_csrbank0_bus_errors0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 4'd8)); +assign vns_csrbank0_bus_errors0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 4'd8)); +assign vns_csrbank0_reset0_w = soc_litedramcore_soccontroller_reset_storage; +assign vns_csrbank0_scratch3_w = soc_litedramcore_soccontroller_scratch_storage[31:24]; +assign vns_csrbank0_scratch2_w = soc_litedramcore_soccontroller_scratch_storage[23:16]; +assign vns_csrbank0_scratch1_w = soc_litedramcore_soccontroller_scratch_storage[15:8]; +assign vns_csrbank0_scratch0_w = soc_litedramcore_soccontroller_scratch_storage[7:0]; +assign vns_csrbank0_bus_errors3_w = soc_litedramcore_soccontroller_bus_errors_status[31:24]; +assign vns_csrbank0_bus_errors2_w = soc_litedramcore_soccontroller_bus_errors_status[23:16]; +assign vns_csrbank0_bus_errors1_w = soc_litedramcore_soccontroller_bus_errors_status[15:8]; +assign vns_csrbank0_bus_errors0_w = soc_litedramcore_soccontroller_bus_errors_status[7:0]; +assign soc_litedramcore_soccontroller_bus_errors_we = vns_csrbank0_bus_errors0_we; +assign vns_csrbank1_sel = (vns_interface1_bank_bus_adr[13:9] == 3'd7); +assign vns_csrbank1_init_done0_r = vns_interface1_bank_bus_dat_w[0]; +assign vns_csrbank1_init_done0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[0] == 1'd0)); +assign vns_csrbank1_init_done0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[0] == 1'd0)); +assign vns_csrbank1_init_error0_r = vns_interface1_bank_bus_dat_w[0]; +assign vns_csrbank1_init_error0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[0] == 1'd1)); +assign vns_csrbank1_init_error0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[0] == 1'd1)); +assign vns_csrbank1_init_done0_w = soc_init_done_storage; +assign vns_csrbank1_init_error0_w = soc_init_error_storage; +assign vns_csrbank2_sel = (vns_interface2_bank_bus_adr[13:9] == 3'd5); +assign vns_csrbank2_half_sys8x_taps0_r = vns_interface2_bank_bus_dat_w[4:0]; +assign vns_csrbank2_half_sys8x_taps0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 1'd0)); +assign vns_csrbank2_half_sys8x_taps0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 1'd0)); +assign vns_csrbank2_wlevel_en0_r = vns_interface2_bank_bus_dat_w[0]; +assign vns_csrbank2_wlevel_en0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 1'd1)); +assign vns_csrbank2_wlevel_en0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 1'd1)); +assign soc_a7ddrphy_wlevel_strobe_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_a7ddrphy_wlevel_strobe_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 2'd2)); +assign soc_a7ddrphy_wlevel_strobe_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 2'd2)); +assign soc_a7ddrphy_cdly_rst_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_a7ddrphy_cdly_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 2'd3)); +assign soc_a7ddrphy_cdly_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 2'd3)); +assign soc_a7ddrphy_cdly_inc_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_a7ddrphy_cdly_inc_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd4)); +assign soc_a7ddrphy_cdly_inc_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd4)); +assign vns_csrbank2_dly_sel0_r = vns_interface2_bank_bus_dat_w[1:0]; +assign vns_csrbank2_dly_sel0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd5)); +assign vns_csrbank2_dly_sel0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd5)); +assign soc_a7ddrphy_rdly_dq_rst_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_a7ddrphy_rdly_dq_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd6)); +assign soc_a7ddrphy_rdly_dq_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd6)); +assign soc_a7ddrphy_rdly_dq_inc_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_a7ddrphy_rdly_dq_inc_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd7)); +assign soc_a7ddrphy_rdly_dq_inc_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd7)); +assign soc_a7ddrphy_rdly_dq_bitslip_rst_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_a7ddrphy_rdly_dq_bitslip_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 4'd8)); +assign soc_a7ddrphy_rdly_dq_bitslip_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 4'd8)); +assign soc_a7ddrphy_rdly_dq_bitslip_r = vns_interface2_bank_bus_dat_w[0]; +assign soc_a7ddrphy_rdly_dq_bitslip_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 4'd9)); +assign soc_a7ddrphy_rdly_dq_bitslip_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 4'd9)); +assign vns_csrbank2_half_sys8x_taps0_w = soc_a7ddrphy_half_sys8x_taps_storage[4:0]; +assign vns_csrbank2_wlevel_en0_w = soc_a7ddrphy_wlevel_en_storage; +assign vns_csrbank2_dly_sel0_w = soc_a7ddrphy_dly_sel_storage[1:0]; +assign vns_csrbank3_sel = (vns_interface3_bank_bus_adr[13:9] == 3'd6); +assign vns_csrbank3_dfii_control0_r = vns_interface3_bank_bus_dat_w[3:0]; +assign vns_csrbank3_dfii_control0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 1'd0)); +assign vns_csrbank3_dfii_control0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 1'd0)); +assign vns_csrbank3_dfii_pi0_command0_r = vns_interface3_bank_bus_dat_w[5:0]; +assign vns_csrbank3_dfii_pi0_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 1'd1)); +assign vns_csrbank3_dfii_pi0_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 1'd1)); +assign soc_sdram_phaseinjector0_command_issue_r = vns_interface3_bank_bus_dat_w[0]; +assign soc_sdram_phaseinjector0_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 2'd2)); +assign soc_sdram_phaseinjector0_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 2'd2)); +assign vns_csrbank3_dfii_pi0_address1_r = vns_interface3_bank_bus_dat_w[6:0]; +assign vns_csrbank3_dfii_pi0_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 2'd3)); +assign vns_csrbank3_dfii_pi0_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 2'd3)); +assign vns_csrbank3_dfii_pi0_address0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi0_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd4)); +assign vns_csrbank3_dfii_pi0_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd4)); +assign vns_csrbank3_dfii_pi0_baddress0_r = vns_interface3_bank_bus_dat_w[2:0]; +assign vns_csrbank3_dfii_pi0_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd5)); +assign vns_csrbank3_dfii_pi0_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd5)); +assign vns_csrbank3_dfii_pi0_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi0_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd6)); +assign vns_csrbank3_dfii_pi0_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd6)); +assign vns_csrbank3_dfii_pi0_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi0_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd7)); +assign vns_csrbank3_dfii_pi0_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd7)); +assign vns_csrbank3_dfii_pi0_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi0_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd8)); +assign vns_csrbank3_dfii_pi0_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd8)); +assign vns_csrbank3_dfii_pi0_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi0_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd9)); +assign vns_csrbank3_dfii_pi0_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd9)); +assign vns_csrbank3_dfii_pi0_rddata3_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi0_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd10)); +assign vns_csrbank3_dfii_pi0_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd10)); +assign vns_csrbank3_dfii_pi0_rddata2_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi0_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd11)); +assign vns_csrbank3_dfii_pi0_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd11)); +assign vns_csrbank3_dfii_pi0_rddata1_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi0_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd12)); +assign vns_csrbank3_dfii_pi0_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd12)); +assign vns_csrbank3_dfii_pi0_rddata0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi0_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd13)); +assign vns_csrbank3_dfii_pi0_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd13)); +assign vns_csrbank3_dfii_pi1_command0_r = vns_interface3_bank_bus_dat_w[5:0]; +assign vns_csrbank3_dfii_pi1_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd14)); +assign vns_csrbank3_dfii_pi1_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd14)); +assign soc_sdram_phaseinjector1_command_issue_r = vns_interface3_bank_bus_dat_w[0]; +assign soc_sdram_phaseinjector1_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd15)); +assign soc_sdram_phaseinjector1_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd15)); +assign vns_csrbank3_dfii_pi1_address1_r = vns_interface3_bank_bus_dat_w[6:0]; +assign vns_csrbank3_dfii_pi1_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd16)); +assign vns_csrbank3_dfii_pi1_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd16)); +assign vns_csrbank3_dfii_pi1_address0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi1_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd17)); +assign vns_csrbank3_dfii_pi1_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd17)); +assign vns_csrbank3_dfii_pi1_baddress0_r = vns_interface3_bank_bus_dat_w[2:0]; +assign vns_csrbank3_dfii_pi1_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd18)); +assign vns_csrbank3_dfii_pi1_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd18)); +assign vns_csrbank3_dfii_pi1_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi1_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd19)); +assign vns_csrbank3_dfii_pi1_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd19)); +assign vns_csrbank3_dfii_pi1_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi1_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd20)); +assign vns_csrbank3_dfii_pi1_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd20)); +assign vns_csrbank3_dfii_pi1_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi1_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd21)); +assign vns_csrbank3_dfii_pi1_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd21)); +assign vns_csrbank3_dfii_pi1_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi1_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd22)); +assign vns_csrbank3_dfii_pi1_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd22)); +assign vns_csrbank3_dfii_pi1_rddata3_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi1_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd23)); +assign vns_csrbank3_dfii_pi1_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd23)); +assign vns_csrbank3_dfii_pi1_rddata2_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi1_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd24)); +assign vns_csrbank3_dfii_pi1_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd24)); +assign vns_csrbank3_dfii_pi1_rddata1_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi1_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd25)); +assign vns_csrbank3_dfii_pi1_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd25)); +assign vns_csrbank3_dfii_pi1_rddata0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi1_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd26)); +assign vns_csrbank3_dfii_pi1_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd26)); +assign vns_csrbank3_dfii_pi2_command0_r = vns_interface3_bank_bus_dat_w[5:0]; +assign vns_csrbank3_dfii_pi2_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd27)); +assign vns_csrbank3_dfii_pi2_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd27)); +assign soc_sdram_phaseinjector2_command_issue_r = vns_interface3_bank_bus_dat_w[0]; +assign soc_sdram_phaseinjector2_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd28)); +assign soc_sdram_phaseinjector2_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd28)); +assign vns_csrbank3_dfii_pi2_address1_r = vns_interface3_bank_bus_dat_w[6:0]; +assign vns_csrbank3_dfii_pi2_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd29)); +assign vns_csrbank3_dfii_pi2_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd29)); +assign vns_csrbank3_dfii_pi2_address0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi2_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd30)); +assign vns_csrbank3_dfii_pi2_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd30)); +assign vns_csrbank3_dfii_pi2_baddress0_r = vns_interface3_bank_bus_dat_w[2:0]; +assign vns_csrbank3_dfii_pi2_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd31)); +assign vns_csrbank3_dfii_pi2_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd31)); +assign vns_csrbank3_dfii_pi2_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi2_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd32)); +assign vns_csrbank3_dfii_pi2_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd32)); +assign vns_csrbank3_dfii_pi2_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi2_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd33)); +assign vns_csrbank3_dfii_pi2_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd33)); +assign vns_csrbank3_dfii_pi2_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi2_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd34)); +assign vns_csrbank3_dfii_pi2_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd34)); +assign vns_csrbank3_dfii_pi2_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi2_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd35)); +assign vns_csrbank3_dfii_pi2_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd35)); +assign vns_csrbank3_dfii_pi2_rddata3_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi2_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd36)); +assign vns_csrbank3_dfii_pi2_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd36)); +assign vns_csrbank3_dfii_pi2_rddata2_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi2_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd37)); +assign vns_csrbank3_dfii_pi2_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd37)); +assign vns_csrbank3_dfii_pi2_rddata1_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi2_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd38)); +assign vns_csrbank3_dfii_pi2_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd38)); +assign vns_csrbank3_dfii_pi2_rddata0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi2_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd39)); +assign vns_csrbank3_dfii_pi2_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd39)); +assign vns_csrbank3_dfii_pi3_command0_r = vns_interface3_bank_bus_dat_w[5:0]; +assign vns_csrbank3_dfii_pi3_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd40)); +assign vns_csrbank3_dfii_pi3_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd40)); +assign soc_sdram_phaseinjector3_command_issue_r = vns_interface3_bank_bus_dat_w[0]; +assign soc_sdram_phaseinjector3_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd41)); +assign soc_sdram_phaseinjector3_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd41)); +assign vns_csrbank3_dfii_pi3_address1_r = vns_interface3_bank_bus_dat_w[6:0]; +assign vns_csrbank3_dfii_pi3_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd42)); +assign vns_csrbank3_dfii_pi3_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd42)); +assign vns_csrbank3_dfii_pi3_address0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi3_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd43)); +assign vns_csrbank3_dfii_pi3_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd43)); +assign vns_csrbank3_dfii_pi3_baddress0_r = vns_interface3_bank_bus_dat_w[2:0]; +assign vns_csrbank3_dfii_pi3_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd44)); +assign vns_csrbank3_dfii_pi3_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd44)); +assign vns_csrbank3_dfii_pi3_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi3_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd45)); +assign vns_csrbank3_dfii_pi3_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd45)); +assign vns_csrbank3_dfii_pi3_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi3_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd46)); +assign vns_csrbank3_dfii_pi3_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd46)); +assign vns_csrbank3_dfii_pi3_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi3_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd47)); +assign vns_csrbank3_dfii_pi3_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd47)); +assign vns_csrbank3_dfii_pi3_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi3_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd48)); +assign vns_csrbank3_dfii_pi3_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd48)); +assign vns_csrbank3_dfii_pi3_rddata3_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi3_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd49)); +assign vns_csrbank3_dfii_pi3_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd49)); +assign vns_csrbank3_dfii_pi3_rddata2_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi3_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd50)); +assign vns_csrbank3_dfii_pi3_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd50)); +assign vns_csrbank3_dfii_pi3_rddata1_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi3_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd51)); +assign vns_csrbank3_dfii_pi3_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd51)); +assign vns_csrbank3_dfii_pi3_rddata0_r = vns_interface3_bank_bus_dat_w[7:0]; +assign vns_csrbank3_dfii_pi3_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd52)); +assign vns_csrbank3_dfii_pi3_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd52)); +assign vns_csrbank3_dfii_control0_w = soc_sdram_storage[3:0]; +assign vns_csrbank3_dfii_pi0_command0_w = soc_sdram_phaseinjector0_command_storage[5:0]; +assign vns_csrbank3_dfii_pi0_address1_w = soc_sdram_phaseinjector0_address_storage[14:8]; +assign vns_csrbank3_dfii_pi0_address0_w = soc_sdram_phaseinjector0_address_storage[7:0]; +assign vns_csrbank3_dfii_pi0_baddress0_w = soc_sdram_phaseinjector0_baddress_storage[2:0]; +assign vns_csrbank3_dfii_pi0_wrdata3_w = soc_sdram_phaseinjector0_wrdata_storage[31:24]; +assign vns_csrbank3_dfii_pi0_wrdata2_w = soc_sdram_phaseinjector0_wrdata_storage[23:16]; +assign vns_csrbank3_dfii_pi0_wrdata1_w = soc_sdram_phaseinjector0_wrdata_storage[15:8]; +assign vns_csrbank3_dfii_pi0_wrdata0_w = soc_sdram_phaseinjector0_wrdata_storage[7:0]; +assign vns_csrbank3_dfii_pi0_rddata3_w = soc_sdram_phaseinjector0_status[31:24]; +assign vns_csrbank3_dfii_pi0_rddata2_w = soc_sdram_phaseinjector0_status[23:16]; +assign vns_csrbank3_dfii_pi0_rddata1_w = soc_sdram_phaseinjector0_status[15:8]; +assign vns_csrbank3_dfii_pi0_rddata0_w = soc_sdram_phaseinjector0_status[7:0]; +assign soc_sdram_phaseinjector0_we = vns_csrbank3_dfii_pi0_rddata0_we; +assign vns_csrbank3_dfii_pi1_command0_w = soc_sdram_phaseinjector1_command_storage[5:0]; +assign vns_csrbank3_dfii_pi1_address1_w = soc_sdram_phaseinjector1_address_storage[14:8]; +assign vns_csrbank3_dfii_pi1_address0_w = soc_sdram_phaseinjector1_address_storage[7:0]; +assign vns_csrbank3_dfii_pi1_baddress0_w = soc_sdram_phaseinjector1_baddress_storage[2:0]; +assign vns_csrbank3_dfii_pi1_wrdata3_w = soc_sdram_phaseinjector1_wrdata_storage[31:24]; +assign vns_csrbank3_dfii_pi1_wrdata2_w = soc_sdram_phaseinjector1_wrdata_storage[23:16]; +assign vns_csrbank3_dfii_pi1_wrdata1_w = soc_sdram_phaseinjector1_wrdata_storage[15:8]; +assign vns_csrbank3_dfii_pi1_wrdata0_w = soc_sdram_phaseinjector1_wrdata_storage[7:0]; +assign vns_csrbank3_dfii_pi1_rddata3_w = soc_sdram_phaseinjector1_status[31:24]; +assign vns_csrbank3_dfii_pi1_rddata2_w = soc_sdram_phaseinjector1_status[23:16]; +assign vns_csrbank3_dfii_pi1_rddata1_w = soc_sdram_phaseinjector1_status[15:8]; +assign vns_csrbank3_dfii_pi1_rddata0_w = soc_sdram_phaseinjector1_status[7:0]; +assign soc_sdram_phaseinjector1_we = vns_csrbank3_dfii_pi1_rddata0_we; +assign vns_csrbank3_dfii_pi2_command0_w = soc_sdram_phaseinjector2_command_storage[5:0]; +assign vns_csrbank3_dfii_pi2_address1_w = soc_sdram_phaseinjector2_address_storage[14:8]; +assign vns_csrbank3_dfii_pi2_address0_w = soc_sdram_phaseinjector2_address_storage[7:0]; +assign vns_csrbank3_dfii_pi2_baddress0_w = soc_sdram_phaseinjector2_baddress_storage[2:0]; +assign vns_csrbank3_dfii_pi2_wrdata3_w = soc_sdram_phaseinjector2_wrdata_storage[31:24]; +assign vns_csrbank3_dfii_pi2_wrdata2_w = soc_sdram_phaseinjector2_wrdata_storage[23:16]; +assign vns_csrbank3_dfii_pi2_wrdata1_w = soc_sdram_phaseinjector2_wrdata_storage[15:8]; +assign vns_csrbank3_dfii_pi2_wrdata0_w = soc_sdram_phaseinjector2_wrdata_storage[7:0]; +assign vns_csrbank3_dfii_pi2_rddata3_w = soc_sdram_phaseinjector2_status[31:24]; +assign vns_csrbank3_dfii_pi2_rddata2_w = soc_sdram_phaseinjector2_status[23:16]; +assign vns_csrbank3_dfii_pi2_rddata1_w = soc_sdram_phaseinjector2_status[15:8]; +assign vns_csrbank3_dfii_pi2_rddata0_w = soc_sdram_phaseinjector2_status[7:0]; +assign soc_sdram_phaseinjector2_we = vns_csrbank3_dfii_pi2_rddata0_we; +assign vns_csrbank3_dfii_pi3_command0_w = soc_sdram_phaseinjector3_command_storage[5:0]; +assign vns_csrbank3_dfii_pi3_address1_w = soc_sdram_phaseinjector3_address_storage[14:8]; +assign vns_csrbank3_dfii_pi3_address0_w = soc_sdram_phaseinjector3_address_storage[7:0]; +assign vns_csrbank3_dfii_pi3_baddress0_w = soc_sdram_phaseinjector3_baddress_storage[2:0]; +assign vns_csrbank3_dfii_pi3_wrdata3_w = soc_sdram_phaseinjector3_wrdata_storage[31:24]; +assign vns_csrbank3_dfii_pi3_wrdata2_w = soc_sdram_phaseinjector3_wrdata_storage[23:16]; +assign vns_csrbank3_dfii_pi3_wrdata1_w = soc_sdram_phaseinjector3_wrdata_storage[15:8]; +assign vns_csrbank3_dfii_pi3_wrdata0_w = soc_sdram_phaseinjector3_wrdata_storage[7:0]; +assign vns_csrbank3_dfii_pi3_rddata3_w = soc_sdram_phaseinjector3_status[31:24]; +assign vns_csrbank3_dfii_pi3_rddata2_w = soc_sdram_phaseinjector3_status[23:16]; +assign vns_csrbank3_dfii_pi3_rddata1_w = soc_sdram_phaseinjector3_status[15:8]; +assign vns_csrbank3_dfii_pi3_rddata0_w = soc_sdram_phaseinjector3_status[7:0]; +assign soc_sdram_phaseinjector3_we = vns_csrbank3_dfii_pi3_rddata0_we; +assign vns_csrbank4_sel = (vns_interface4_bank_bus_adr[13:9] == 3'd4); +assign vns_csrbank4_load3_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_load3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 1'd0)); +assign vns_csrbank4_load3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 1'd0)); +assign vns_csrbank4_load2_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_load2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 1'd1)); +assign vns_csrbank4_load2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 1'd1)); +assign vns_csrbank4_load1_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_load1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 2'd2)); +assign vns_csrbank4_load1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 2'd2)); +assign vns_csrbank4_load0_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_load0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 2'd3)); +assign vns_csrbank4_load0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 2'd3)); +assign vns_csrbank4_reload3_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_reload3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd4)); +assign vns_csrbank4_reload3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd4)); +assign vns_csrbank4_reload2_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_reload2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd5)); +assign vns_csrbank4_reload2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd5)); +assign vns_csrbank4_reload1_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_reload1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd6)); +assign vns_csrbank4_reload1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd6)); +assign vns_csrbank4_reload0_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_reload0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd7)); +assign vns_csrbank4_reload0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd7)); +assign vns_csrbank4_en0_r = vns_interface4_bank_bus_dat_w[0]; +assign vns_csrbank4_en0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd8)); +assign vns_csrbank4_en0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd8)); +assign vns_csrbank4_update_value0_r = vns_interface4_bank_bus_dat_w[0]; +assign vns_csrbank4_update_value0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd9)); +assign vns_csrbank4_update_value0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd9)); +assign vns_csrbank4_value3_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_value3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd10)); +assign vns_csrbank4_value3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd10)); +assign vns_csrbank4_value2_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_value2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd11)); +assign vns_csrbank4_value2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd11)); +assign vns_csrbank4_value1_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_value1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd12)); +assign vns_csrbank4_value1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd12)); +assign vns_csrbank4_value0_r = vns_interface4_bank_bus_dat_w[7:0]; +assign vns_csrbank4_value0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd13)); +assign vns_csrbank4_value0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd13)); +assign soc_litedramcore_timer_eventmanager_status_r = vns_interface4_bank_bus_dat_w[0]; +assign soc_litedramcore_timer_eventmanager_status_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd14)); +assign soc_litedramcore_timer_eventmanager_status_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd14)); +assign soc_litedramcore_timer_eventmanager_pending_r = vns_interface4_bank_bus_dat_w[0]; +assign soc_litedramcore_timer_eventmanager_pending_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd15)); +assign soc_litedramcore_timer_eventmanager_pending_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd15)); +assign vns_csrbank4_ev_enable0_r = vns_interface4_bank_bus_dat_w[0]; +assign vns_csrbank4_ev_enable0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 5'd16)); +assign vns_csrbank4_ev_enable0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 5'd16)); +assign vns_csrbank4_load3_w = soc_litedramcore_timer_load_storage[31:24]; +assign vns_csrbank4_load2_w = soc_litedramcore_timer_load_storage[23:16]; +assign vns_csrbank4_load1_w = soc_litedramcore_timer_load_storage[15:8]; +assign vns_csrbank4_load0_w = soc_litedramcore_timer_load_storage[7:0]; +assign vns_csrbank4_reload3_w = soc_litedramcore_timer_reload_storage[31:24]; +assign vns_csrbank4_reload2_w = soc_litedramcore_timer_reload_storage[23:16]; +assign vns_csrbank4_reload1_w = soc_litedramcore_timer_reload_storage[15:8]; +assign vns_csrbank4_reload0_w = soc_litedramcore_timer_reload_storage[7:0]; +assign vns_csrbank4_en0_w = soc_litedramcore_timer_en_storage; +assign vns_csrbank4_update_value0_w = soc_litedramcore_timer_update_value_storage; +assign vns_csrbank4_value3_w = soc_litedramcore_timer_value_status[31:24]; +assign vns_csrbank4_value2_w = soc_litedramcore_timer_value_status[23:16]; +assign vns_csrbank4_value1_w = soc_litedramcore_timer_value_status[15:8]; +assign vns_csrbank4_value0_w = soc_litedramcore_timer_value_status[7:0]; +assign soc_litedramcore_timer_value_we = vns_csrbank4_value0_we; +assign vns_csrbank4_ev_enable0_w = soc_litedramcore_timer_eventmanager_storage; +assign vns_csrbank5_sel = (vns_interface5_bank_bus_adr[13:9] == 2'd3); +assign soc_litedramcore_uart_rxtx_r = vns_interface5_bank_bus_dat_w[7:0]; +assign soc_litedramcore_uart_rxtx_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 1'd0)); +assign soc_litedramcore_uart_rxtx_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 1'd0)); +assign vns_csrbank5_txfull_r = vns_interface5_bank_bus_dat_w[0]; +assign vns_csrbank5_txfull_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 1'd1)); +assign vns_csrbank5_txfull_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 1'd1)); +assign vns_csrbank5_rxempty_r = vns_interface5_bank_bus_dat_w[0]; +assign vns_csrbank5_rxempty_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 2'd2)); +assign vns_csrbank5_rxempty_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 2'd2)); +assign soc_litedramcore_uart_eventmanager_status_r = vns_interface5_bank_bus_dat_w[1:0]; +assign soc_litedramcore_uart_eventmanager_status_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 2'd3)); +assign soc_litedramcore_uart_eventmanager_status_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 2'd3)); +assign soc_litedramcore_uart_eventmanager_pending_r = vns_interface5_bank_bus_dat_w[1:0]; +assign soc_litedramcore_uart_eventmanager_pending_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 3'd4)); +assign soc_litedramcore_uart_eventmanager_pending_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 3'd4)); +assign vns_csrbank5_ev_enable0_r = vns_interface5_bank_bus_dat_w[1:0]; +assign vns_csrbank5_ev_enable0_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 3'd5)); +assign vns_csrbank5_ev_enable0_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 3'd5)); +assign vns_csrbank5_txfull_w = soc_litedramcore_uart_txfull_status; +assign soc_litedramcore_uart_txfull_we = vns_csrbank5_txfull_we; +assign vns_csrbank5_rxempty_w = soc_litedramcore_uart_rxempty_status; +assign soc_litedramcore_uart_rxempty_we = vns_csrbank5_rxempty_we; +assign vns_csrbank5_ev_enable0_w = soc_litedramcore_uart_eventmanager_storage[1:0]; +assign vns_csrbank6_sel = (vns_interface6_bank_bus_adr[13:9] == 2'd2); +assign vns_csrbank6_tuning_word3_r = vns_interface6_bank_bus_dat_w[7:0]; +assign vns_csrbank6_tuning_word3_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 1'd0)); +assign vns_csrbank6_tuning_word3_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 1'd0)); +assign vns_csrbank6_tuning_word2_r = vns_interface6_bank_bus_dat_w[7:0]; +assign vns_csrbank6_tuning_word2_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 1'd1)); +assign vns_csrbank6_tuning_word2_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 1'd1)); +assign vns_csrbank6_tuning_word1_r = vns_interface6_bank_bus_dat_w[7:0]; +assign vns_csrbank6_tuning_word1_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 2'd2)); +assign vns_csrbank6_tuning_word1_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 2'd2)); +assign vns_csrbank6_tuning_word0_r = vns_interface6_bank_bus_dat_w[7:0]; +assign vns_csrbank6_tuning_word0_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 2'd3)); +assign vns_csrbank6_tuning_word0_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 2'd3)); +assign vns_csrbank6_tuning_word3_w = soc_litedramcore_storage[31:24]; +assign vns_csrbank6_tuning_word2_w = soc_litedramcore_storage[23:16]; +assign vns_csrbank6_tuning_word1_w = soc_litedramcore_storage[15:8]; +assign vns_csrbank6_tuning_word0_w = soc_litedramcore_storage[7:0]; +assign vns_adr = soc_litedramcore_interface_adr; +assign vns_we = soc_litedramcore_interface_we; +assign vns_dat_w = soc_litedramcore_interface_dat_w; +assign soc_litedramcore_interface_dat_r = vns_dat_r; +assign vns_interface0_bank_bus_adr = vns_adr; +assign vns_interface1_bank_bus_adr = vns_adr; +assign vns_interface2_bank_bus_adr = vns_adr; +assign vns_interface3_bank_bus_adr = vns_adr; +assign vns_interface4_bank_bus_adr = vns_adr; +assign vns_interface5_bank_bus_adr = vns_adr; +assign vns_interface6_bank_bus_adr = vns_adr; +assign vns_interface0_bank_bus_we = vns_we; +assign vns_interface1_bank_bus_we = vns_we; +assign vns_interface2_bank_bus_we = vns_we; +assign vns_interface3_bank_bus_we = vns_we; +assign vns_interface4_bank_bus_we = vns_we; +assign vns_interface5_bank_bus_we = vns_we; +assign vns_interface6_bank_bus_we = vns_we; +assign vns_interface0_bank_bus_dat_w = vns_dat_w; +assign vns_interface1_bank_bus_dat_w = vns_dat_w; +assign vns_interface2_bank_bus_dat_w = vns_dat_w; +assign vns_interface3_bank_bus_dat_w = vns_dat_w; +assign vns_interface4_bank_bus_dat_w = vns_dat_w; +assign vns_interface5_bank_bus_dat_w = vns_dat_w; +assign vns_interface6_bank_bus_dat_w = vns_dat_w; +assign vns_dat_r = ((((((vns_interface0_bank_bus_dat_r | vns_interface1_bank_bus_dat_r) | vns_interface2_bank_bus_dat_r) | vns_interface3_bank_bus_dat_r) | vns_interface4_bank_bus_dat_r) | vns_interface5_bank_bus_dat_r) | vns_interface6_bank_bus_dat_r); + +// synthesis translate_off +reg dummy_d_338; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed0 <= 1'd0; + case (soc_sdram_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[0]; + end + 1'd1: begin + vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[1]; + end + 2'd2: begin + vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[2]; + end + 2'd3: begin + vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[3]; + end + 3'd4: begin + vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[4]; + end + 3'd5: begin + vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[5]; + end + 3'd6: begin + vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[6]; + end + default: begin + vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[7]; + end + endcase +// synthesis translate_off + dummy_d_338 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_339; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed1 <= 15'd0; + case (soc_sdram_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed1 <= soc_sdram_bankmachine0_cmd_payload_a; + end + 1'd1: begin + vns_rhs_array_muxed1 <= soc_sdram_bankmachine1_cmd_payload_a; + end + 2'd2: begin + vns_rhs_array_muxed1 <= soc_sdram_bankmachine2_cmd_payload_a; + end + 2'd3: begin + vns_rhs_array_muxed1 <= soc_sdram_bankmachine3_cmd_payload_a; + end + 3'd4: begin + vns_rhs_array_muxed1 <= soc_sdram_bankmachine4_cmd_payload_a; + end + 3'd5: begin + vns_rhs_array_muxed1 <= soc_sdram_bankmachine5_cmd_payload_a; + end + 3'd6: begin + vns_rhs_array_muxed1 <= soc_sdram_bankmachine6_cmd_payload_a; + end + default: begin + vns_rhs_array_muxed1 <= soc_sdram_bankmachine7_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_339 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_340; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed2 <= 3'd0; + case (soc_sdram_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed2 <= soc_sdram_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + vns_rhs_array_muxed2 <= soc_sdram_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + vns_rhs_array_muxed2 <= soc_sdram_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + vns_rhs_array_muxed2 <= soc_sdram_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + vns_rhs_array_muxed2 <= soc_sdram_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + vns_rhs_array_muxed2 <= soc_sdram_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + vns_rhs_array_muxed2 <= soc_sdram_bankmachine6_cmd_payload_ba; + end + default: begin + vns_rhs_array_muxed2 <= soc_sdram_bankmachine7_cmd_payload_ba; + end + endcase +// synthesis translate_off + dummy_d_340 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_341; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed3 <= 1'd0; + case (soc_sdram_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed3 <= soc_sdram_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + vns_rhs_array_muxed3 <= soc_sdram_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + vns_rhs_array_muxed3 <= soc_sdram_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + vns_rhs_array_muxed3 <= soc_sdram_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + vns_rhs_array_muxed3 <= soc_sdram_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + vns_rhs_array_muxed3 <= soc_sdram_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + vns_rhs_array_muxed3 <= soc_sdram_bankmachine6_cmd_payload_is_read; + end + default: begin + vns_rhs_array_muxed3 <= soc_sdram_bankmachine7_cmd_payload_is_read; + end + endcase +// synthesis translate_off + dummy_d_341 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_342; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed4 <= 1'd0; + case (soc_sdram_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed4 <= soc_sdram_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + vns_rhs_array_muxed4 <= soc_sdram_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + vns_rhs_array_muxed4 <= soc_sdram_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + vns_rhs_array_muxed4 <= soc_sdram_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + vns_rhs_array_muxed4 <= soc_sdram_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + vns_rhs_array_muxed4 <= soc_sdram_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + vns_rhs_array_muxed4 <= soc_sdram_bankmachine6_cmd_payload_is_write; + end + default: begin + vns_rhs_array_muxed4 <= soc_sdram_bankmachine7_cmd_payload_is_write; + end + endcase +// synthesis translate_off + dummy_d_342 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_343; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed5 <= 1'd0; + case (soc_sdram_choose_cmd_grant) + 1'd0: begin + vns_rhs_array_muxed5 <= soc_sdram_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + vns_rhs_array_muxed5 <= soc_sdram_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + vns_rhs_array_muxed5 <= soc_sdram_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + vns_rhs_array_muxed5 <= soc_sdram_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + vns_rhs_array_muxed5 <= soc_sdram_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + vns_rhs_array_muxed5 <= soc_sdram_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + vns_rhs_array_muxed5 <= soc_sdram_bankmachine6_cmd_payload_is_cmd; + end + default: begin + vns_rhs_array_muxed5 <= soc_sdram_bankmachine7_cmd_payload_is_cmd; + end + endcase +// synthesis translate_off + dummy_d_343 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_344; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed0 <= 1'd0; + case (soc_sdram_choose_cmd_grant) + 1'd0: begin + vns_t_array_muxed0 <= soc_sdram_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + vns_t_array_muxed0 <= soc_sdram_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + vns_t_array_muxed0 <= soc_sdram_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + vns_t_array_muxed0 <= soc_sdram_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + vns_t_array_muxed0 <= soc_sdram_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + vns_t_array_muxed0 <= soc_sdram_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + vns_t_array_muxed0 <= soc_sdram_bankmachine6_cmd_payload_cas; + end + default: begin + vns_t_array_muxed0 <= soc_sdram_bankmachine7_cmd_payload_cas; + end + endcase +// synthesis translate_off + dummy_d_344 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_345; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed1 <= 1'd0; + case (soc_sdram_choose_cmd_grant) + 1'd0: begin + vns_t_array_muxed1 <= soc_sdram_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + vns_t_array_muxed1 <= soc_sdram_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + vns_t_array_muxed1 <= soc_sdram_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + vns_t_array_muxed1 <= soc_sdram_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + vns_t_array_muxed1 <= soc_sdram_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + vns_t_array_muxed1 <= soc_sdram_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + vns_t_array_muxed1 <= soc_sdram_bankmachine6_cmd_payload_ras; + end + default: begin + vns_t_array_muxed1 <= soc_sdram_bankmachine7_cmd_payload_ras; + end + endcase +// synthesis translate_off + dummy_d_345 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_346; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed2 <= 1'd0; + case (soc_sdram_choose_cmd_grant) + 1'd0: begin + vns_t_array_muxed2 <= soc_sdram_bankmachine0_cmd_payload_we; + end + 1'd1: begin + vns_t_array_muxed2 <= soc_sdram_bankmachine1_cmd_payload_we; + end + 2'd2: begin + vns_t_array_muxed2 <= soc_sdram_bankmachine2_cmd_payload_we; + end + 2'd3: begin + vns_t_array_muxed2 <= soc_sdram_bankmachine3_cmd_payload_we; + end + 3'd4: begin + vns_t_array_muxed2 <= soc_sdram_bankmachine4_cmd_payload_we; + end + 3'd5: begin + vns_t_array_muxed2 <= soc_sdram_bankmachine5_cmd_payload_we; + end + 3'd6: begin + vns_t_array_muxed2 <= soc_sdram_bankmachine6_cmd_payload_we; + end + default: begin + vns_t_array_muxed2 <= soc_sdram_bankmachine7_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_346 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_347; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed6 <= 1'd0; + case (soc_sdram_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[0]; + end + 1'd1: begin + vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[1]; + end + 2'd2: begin + vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[2]; + end + 2'd3: begin + vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[3]; + end + 3'd4: begin + vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[4]; + end + 3'd5: begin + vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[5]; + end + 3'd6: begin + vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[6]; + end + default: begin + vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[7]; + end + endcase +// synthesis translate_off + dummy_d_347 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_348; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed7 <= 15'd0; + case (soc_sdram_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed7 <= soc_sdram_bankmachine0_cmd_payload_a; + end + 1'd1: begin + vns_rhs_array_muxed7 <= soc_sdram_bankmachine1_cmd_payload_a; + end + 2'd2: begin + vns_rhs_array_muxed7 <= soc_sdram_bankmachine2_cmd_payload_a; + end + 2'd3: begin + vns_rhs_array_muxed7 <= soc_sdram_bankmachine3_cmd_payload_a; + end + 3'd4: begin + vns_rhs_array_muxed7 <= soc_sdram_bankmachine4_cmd_payload_a; + end + 3'd5: begin + vns_rhs_array_muxed7 <= soc_sdram_bankmachine5_cmd_payload_a; + end + 3'd6: begin + vns_rhs_array_muxed7 <= soc_sdram_bankmachine6_cmd_payload_a; + end + default: begin + vns_rhs_array_muxed7 <= soc_sdram_bankmachine7_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_348 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_349; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed8 <= 3'd0; + case (soc_sdram_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed8 <= soc_sdram_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + vns_rhs_array_muxed8 <= soc_sdram_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + vns_rhs_array_muxed8 <= soc_sdram_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + vns_rhs_array_muxed8 <= soc_sdram_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + vns_rhs_array_muxed8 <= soc_sdram_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + vns_rhs_array_muxed8 <= soc_sdram_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + vns_rhs_array_muxed8 <= soc_sdram_bankmachine6_cmd_payload_ba; + end + default: begin + vns_rhs_array_muxed8 <= soc_sdram_bankmachine7_cmd_payload_ba; + end + endcase +// synthesis translate_off + dummy_d_349 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_350; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed9 <= 1'd0; + case (soc_sdram_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed9 <= soc_sdram_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + vns_rhs_array_muxed9 <= soc_sdram_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + vns_rhs_array_muxed9 <= soc_sdram_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + vns_rhs_array_muxed9 <= soc_sdram_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + vns_rhs_array_muxed9 <= soc_sdram_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + vns_rhs_array_muxed9 <= soc_sdram_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + vns_rhs_array_muxed9 <= soc_sdram_bankmachine6_cmd_payload_is_read; + end + default: begin + vns_rhs_array_muxed9 <= soc_sdram_bankmachine7_cmd_payload_is_read; + end + endcase +// synthesis translate_off + dummy_d_350 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_351; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed10 <= 1'd0; + case (soc_sdram_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed10 <= soc_sdram_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + vns_rhs_array_muxed10 <= soc_sdram_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + vns_rhs_array_muxed10 <= soc_sdram_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + vns_rhs_array_muxed10 <= soc_sdram_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + vns_rhs_array_muxed10 <= soc_sdram_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + vns_rhs_array_muxed10 <= soc_sdram_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + vns_rhs_array_muxed10 <= soc_sdram_bankmachine6_cmd_payload_is_write; + end + default: begin + vns_rhs_array_muxed10 <= soc_sdram_bankmachine7_cmd_payload_is_write; + end + endcase +// synthesis translate_off + dummy_d_351 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_352; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed11 <= 1'd0; + case (soc_sdram_choose_req_grant) + 1'd0: begin + vns_rhs_array_muxed11 <= soc_sdram_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + vns_rhs_array_muxed11 <= soc_sdram_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + vns_rhs_array_muxed11 <= soc_sdram_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + vns_rhs_array_muxed11 <= soc_sdram_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + vns_rhs_array_muxed11 <= soc_sdram_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + vns_rhs_array_muxed11 <= soc_sdram_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + vns_rhs_array_muxed11 <= soc_sdram_bankmachine6_cmd_payload_is_cmd; + end + default: begin + vns_rhs_array_muxed11 <= soc_sdram_bankmachine7_cmd_payload_is_cmd; + end + endcase +// synthesis translate_off + dummy_d_352 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_353; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed3 <= 1'd0; + case (soc_sdram_choose_req_grant) + 1'd0: begin + vns_t_array_muxed3 <= soc_sdram_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + vns_t_array_muxed3 <= soc_sdram_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + vns_t_array_muxed3 <= soc_sdram_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + vns_t_array_muxed3 <= soc_sdram_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + vns_t_array_muxed3 <= soc_sdram_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + vns_t_array_muxed3 <= soc_sdram_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + vns_t_array_muxed3 <= soc_sdram_bankmachine6_cmd_payload_cas; + end + default: begin + vns_t_array_muxed3 <= soc_sdram_bankmachine7_cmd_payload_cas; + end + endcase +// synthesis translate_off + dummy_d_353 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_354; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed4 <= 1'd0; + case (soc_sdram_choose_req_grant) + 1'd0: begin + vns_t_array_muxed4 <= soc_sdram_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + vns_t_array_muxed4 <= soc_sdram_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + vns_t_array_muxed4 <= soc_sdram_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + vns_t_array_muxed4 <= soc_sdram_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + vns_t_array_muxed4 <= soc_sdram_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + vns_t_array_muxed4 <= soc_sdram_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + vns_t_array_muxed4 <= soc_sdram_bankmachine6_cmd_payload_ras; + end + default: begin + vns_t_array_muxed4 <= soc_sdram_bankmachine7_cmd_payload_ras; + end + endcase +// synthesis translate_off + dummy_d_354 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_355; +// synthesis translate_on +always @(*) begin + vns_t_array_muxed5 <= 1'd0; + case (soc_sdram_choose_req_grant) + 1'd0: begin + vns_t_array_muxed5 <= soc_sdram_bankmachine0_cmd_payload_we; + end + 1'd1: begin + vns_t_array_muxed5 <= soc_sdram_bankmachine1_cmd_payload_we; + end + 2'd2: begin + vns_t_array_muxed5 <= soc_sdram_bankmachine2_cmd_payload_we; + end + 2'd3: begin + vns_t_array_muxed5 <= soc_sdram_bankmachine3_cmd_payload_we; + end + 3'd4: begin + vns_t_array_muxed5 <= soc_sdram_bankmachine4_cmd_payload_we; + end + 3'd5: begin + vns_t_array_muxed5 <= soc_sdram_bankmachine5_cmd_payload_we; + end + 3'd6: begin + vns_t_array_muxed5 <= soc_sdram_bankmachine6_cmd_payload_we; + end + default: begin + vns_t_array_muxed5 <= soc_sdram_bankmachine7_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_355 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_356; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed12 <= 22'd0; + case (vns_roundrobin0_grant) + 1'd0: begin + vns_rhs_array_muxed12 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]}; + end + default: begin + vns_rhs_array_muxed12 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_356 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_357; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed13 <= 1'd0; + case (vns_roundrobin0_grant) + 1'd0: begin + vns_rhs_array_muxed13 <= soc_port_cmd_payload_we; + end + default: begin + vns_rhs_array_muxed13 <= soc_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_357 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_358; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed14 <= 1'd0; + case (vns_roundrobin0_grant) + 1'd0: begin + vns_rhs_array_muxed14 <= (((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); + end + default: begin + vns_rhs_array_muxed14 <= (((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_358 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_359; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed15 <= 22'd0; + case (vns_roundrobin1_grant) + 1'd0: begin + vns_rhs_array_muxed15 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]}; + end + default: begin + vns_rhs_array_muxed15 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_359 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_360; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed16 <= 1'd0; + case (vns_roundrobin1_grant) + 1'd0: begin + vns_rhs_array_muxed16 <= soc_port_cmd_payload_we; + end + default: begin + vns_rhs_array_muxed16 <= soc_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_360 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_361; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed17 <= 1'd0; + case (vns_roundrobin1_grant) + 1'd0: begin + vns_rhs_array_muxed17 <= (((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); + end + default: begin + vns_rhs_array_muxed17 <= (((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_361 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_362; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed18 <= 22'd0; + case (vns_roundrobin2_grant) + 1'd0: begin + vns_rhs_array_muxed18 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]}; + end + default: begin + vns_rhs_array_muxed18 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_362 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_363; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed19 <= 1'd0; + case (vns_roundrobin2_grant) + 1'd0: begin + vns_rhs_array_muxed19 <= soc_port_cmd_payload_we; + end + default: begin + vns_rhs_array_muxed19 <= soc_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_363 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_364; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed20 <= 1'd0; + case (vns_roundrobin2_grant) + 1'd0: begin + vns_rhs_array_muxed20 <= (((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); + end + default: begin + vns_rhs_array_muxed20 <= (((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_364 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_365; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed21 <= 22'd0; + case (vns_roundrobin3_grant) + 1'd0: begin + vns_rhs_array_muxed21 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]}; + end + default: begin + vns_rhs_array_muxed21 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_365 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_366; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed22 <= 1'd0; + case (vns_roundrobin3_grant) + 1'd0: begin + vns_rhs_array_muxed22 <= soc_port_cmd_payload_we; + end + default: begin + vns_rhs_array_muxed22 <= soc_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_366 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_367; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed23 <= 1'd0; + case (vns_roundrobin3_grant) + 1'd0: begin + vns_rhs_array_muxed23 <= (((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); + end + default: begin + vns_rhs_array_muxed23 <= (((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_367 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_368; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed24 <= 22'd0; + case (vns_roundrobin4_grant) + 1'd0: begin + vns_rhs_array_muxed24 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]}; + end + default: begin + vns_rhs_array_muxed24 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_368 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_369; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed25 <= 1'd0; + case (vns_roundrobin4_grant) + 1'd0: begin + vns_rhs_array_muxed25 <= soc_port_cmd_payload_we; + end + default: begin + vns_rhs_array_muxed25 <= soc_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_369 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_370; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed26 <= 1'd0; + case (vns_roundrobin4_grant) + 1'd0: begin + vns_rhs_array_muxed26 <= (((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); + end + default: begin + vns_rhs_array_muxed26 <= (((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_370 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_371; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed27 <= 22'd0; + case (vns_roundrobin5_grant) + 1'd0: begin + vns_rhs_array_muxed27 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]}; + end + default: begin + vns_rhs_array_muxed27 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_371 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_372; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed28 <= 1'd0; + case (vns_roundrobin5_grant) + 1'd0: begin + vns_rhs_array_muxed28 <= soc_port_cmd_payload_we; + end + default: begin + vns_rhs_array_muxed28 <= soc_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_372 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_373; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed29 <= 1'd0; + case (vns_roundrobin5_grant) + 1'd0: begin + vns_rhs_array_muxed29 <= (((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); + end + default: begin + vns_rhs_array_muxed29 <= (((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_373 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_374; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed30 <= 22'd0; + case (vns_roundrobin6_grant) + 1'd0: begin + vns_rhs_array_muxed30 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]}; + end + default: begin + vns_rhs_array_muxed30 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_374 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_375; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed31 <= 1'd0; + case (vns_roundrobin6_grant) + 1'd0: begin + vns_rhs_array_muxed31 <= soc_port_cmd_payload_we; + end + default: begin + vns_rhs_array_muxed31 <= soc_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_375 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_376; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed32 <= 1'd0; + case (vns_roundrobin6_grant) + 1'd0: begin + vns_rhs_array_muxed32 <= (((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); + end + default: begin + vns_rhs_array_muxed32 <= (((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_376 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_377; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed33 <= 22'd0; + case (vns_roundrobin7_grant) + 1'd0: begin + vns_rhs_array_muxed33 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]}; + end + default: begin + vns_rhs_array_muxed33 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]}; + end + endcase +// synthesis translate_off + dummy_d_377 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_378; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed34 <= 1'd0; + case (vns_roundrobin7_grant) + 1'd0: begin + vns_rhs_array_muxed34 <= soc_port_cmd_payload_we; + end + default: begin + vns_rhs_array_muxed34 <= soc_cmd_payload_we; + end + endcase +// synthesis translate_off + dummy_d_378 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_379; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed35 <= 1'd0; + case (vns_roundrobin7_grant) + 1'd0: begin + vns_rhs_array_muxed35 <= (((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_port_cmd_valid); + end + default: begin + vns_rhs_array_muxed35 <= (((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))))) & soc_cmd_valid); + end + endcase +// synthesis translate_off + dummy_d_379 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_380; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed36 <= 30'd0; + case (vns_grant) + 1'd0: begin + vns_rhs_array_muxed36 <= soc_litedramcore_cpu_ibus_adr; + end + default: begin + vns_rhs_array_muxed36 <= soc_litedramcore_cpu_dbus_adr; + end + endcase +// synthesis translate_off + dummy_d_380 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_381; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed37 <= 32'd0; + case (vns_grant) + 1'd0: begin + vns_rhs_array_muxed37 <= soc_litedramcore_cpu_ibus_dat_w; + end + default: begin + vns_rhs_array_muxed37 <= soc_litedramcore_cpu_dbus_dat_w; + end + endcase +// synthesis translate_off + dummy_d_381 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_382; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed38 <= 4'd0; + case (vns_grant) + 1'd0: begin + vns_rhs_array_muxed38 <= soc_litedramcore_cpu_ibus_sel; + end + default: begin + vns_rhs_array_muxed38 <= soc_litedramcore_cpu_dbus_sel; + end + endcase +// synthesis translate_off + dummy_d_382 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_383; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed39 <= 1'd0; + case (vns_grant) + 1'd0: begin + vns_rhs_array_muxed39 <= soc_litedramcore_cpu_ibus_cyc; + end + default: begin + vns_rhs_array_muxed39 <= soc_litedramcore_cpu_dbus_cyc; + end + endcase +// synthesis translate_off + dummy_d_383 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_384; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed40 <= 1'd0; + case (vns_grant) + 1'd0: begin + vns_rhs_array_muxed40 <= soc_litedramcore_cpu_ibus_stb; + end + default: begin + vns_rhs_array_muxed40 <= soc_litedramcore_cpu_dbus_stb; + end + endcase +// synthesis translate_off + dummy_d_384 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_385; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed41 <= 1'd0; + case (vns_grant) + 1'd0: begin + vns_rhs_array_muxed41 <= soc_litedramcore_cpu_ibus_we; + end + default: begin + vns_rhs_array_muxed41 <= soc_litedramcore_cpu_dbus_we; + end + endcase +// synthesis translate_off + dummy_d_385 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_386; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed42 <= 3'd0; + case (vns_grant) + 1'd0: begin + vns_rhs_array_muxed42 <= soc_litedramcore_cpu_ibus_cti; + end + default: begin + vns_rhs_array_muxed42 <= soc_litedramcore_cpu_dbus_cti; + end + endcase +// synthesis translate_off + dummy_d_386 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_387; +// synthesis translate_on +always @(*) begin + vns_rhs_array_muxed43 <= 2'd0; + case (vns_grant) + 1'd0: begin + vns_rhs_array_muxed43 <= soc_litedramcore_cpu_ibus_bte; + end + default: begin + vns_rhs_array_muxed43 <= soc_litedramcore_cpu_dbus_bte; + end + endcase +// synthesis translate_off + dummy_d_387 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_388; +// synthesis translate_on +always @(*) begin + vns_array_muxed0 <= 3'd0; + case (soc_sdram_steerer_sel0) + 1'd0: begin + vns_array_muxed0 <= soc_sdram_nop_ba[2:0]; + end + 1'd1: begin + vns_array_muxed0 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + vns_array_muxed0 <= soc_sdram_choose_req_cmd_payload_ba[2:0]; + end + default: begin + vns_array_muxed0 <= soc_sdram_cmd_payload_ba[2:0]; + end + endcase +// synthesis translate_off + dummy_d_388 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_389; +// synthesis translate_on +always @(*) begin + vns_array_muxed1 <= 15'd0; + case (soc_sdram_steerer_sel0) + 1'd0: begin + vns_array_muxed1 <= soc_sdram_nop_a; + end + 1'd1: begin + vns_array_muxed1 <= soc_sdram_choose_cmd_cmd_payload_a; + end + 2'd2: begin + vns_array_muxed1 <= soc_sdram_choose_req_cmd_payload_a; + end + default: begin + vns_array_muxed1 <= soc_sdram_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_389 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_390; +// synthesis translate_on +always @(*) begin + vns_array_muxed2 <= 1'd0; + case (soc_sdram_steerer_sel0) + 1'd0: begin + vns_array_muxed2 <= 1'd0; + end + 1'd1: begin + vns_array_muxed2 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + vns_array_muxed2 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas); + end + default: begin + vns_array_muxed2 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas); + end + endcase +// synthesis translate_off + dummy_d_390 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_391; +// synthesis translate_on +always @(*) begin + vns_array_muxed3 <= 1'd0; + case (soc_sdram_steerer_sel0) + 1'd0: begin + vns_array_muxed3 <= 1'd0; + end + 1'd1: begin + vns_array_muxed3 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + vns_array_muxed3 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras); + end + default: begin + vns_array_muxed3 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras); + end + endcase +// synthesis translate_off + dummy_d_391 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_392; +// synthesis translate_on +always @(*) begin + vns_array_muxed4 <= 1'd0; + case (soc_sdram_steerer_sel0) + 1'd0: begin + vns_array_muxed4 <= 1'd0; + end + 1'd1: begin + vns_array_muxed4 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we); + end + 2'd2: begin + vns_array_muxed4 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we); + end + default: begin + vns_array_muxed4 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we); + end + endcase +// synthesis translate_off + dummy_d_392 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_393; +// synthesis translate_on +always @(*) begin + vns_array_muxed5 <= 1'd0; + case (soc_sdram_steerer_sel0) + 1'd0: begin + vns_array_muxed5 <= 1'd0; + end + 1'd1: begin + vns_array_muxed5 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + vns_array_muxed5 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read); + end + default: begin + vns_array_muxed5 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read); + end + endcase +// synthesis translate_off + dummy_d_393 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_394; +// synthesis translate_on +always @(*) begin + vns_array_muxed6 <= 1'd0; + case (soc_sdram_steerer_sel0) + 1'd0: begin + vns_array_muxed6 <= 1'd0; + end + 1'd1: begin + vns_array_muxed6 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + vns_array_muxed6 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write); + end + default: begin + vns_array_muxed6 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write); + end + endcase +// synthesis translate_off + dummy_d_394 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_395; +// synthesis translate_on +always @(*) begin + vns_array_muxed7 <= 3'd0; + case (soc_sdram_steerer_sel1) + 1'd0: begin + vns_array_muxed7 <= soc_sdram_nop_ba[2:0]; + end + 1'd1: begin + vns_array_muxed7 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + vns_array_muxed7 <= soc_sdram_choose_req_cmd_payload_ba[2:0]; + end + default: begin + vns_array_muxed7 <= soc_sdram_cmd_payload_ba[2:0]; + end + endcase +// synthesis translate_off + dummy_d_395 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_396; +// synthesis translate_on +always @(*) begin + vns_array_muxed8 <= 15'd0; + case (soc_sdram_steerer_sel1) + 1'd0: begin + vns_array_muxed8 <= soc_sdram_nop_a; + end + 1'd1: begin + vns_array_muxed8 <= soc_sdram_choose_cmd_cmd_payload_a; + end + 2'd2: begin + vns_array_muxed8 <= soc_sdram_choose_req_cmd_payload_a; + end + default: begin + vns_array_muxed8 <= soc_sdram_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_396 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_397; +// synthesis translate_on +always @(*) begin + vns_array_muxed9 <= 1'd0; + case (soc_sdram_steerer_sel1) + 1'd0: begin + vns_array_muxed9 <= 1'd0; + end + 1'd1: begin + vns_array_muxed9 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + vns_array_muxed9 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas); + end + default: begin + vns_array_muxed9 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas); + end + endcase +// synthesis translate_off + dummy_d_397 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_398; +// synthesis translate_on +always @(*) begin + vns_array_muxed10 <= 1'd0; + case (soc_sdram_steerer_sel1) + 1'd0: begin + vns_array_muxed10 <= 1'd0; + end + 1'd1: begin + vns_array_muxed10 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + vns_array_muxed10 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras); + end + default: begin + vns_array_muxed10 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras); + end + endcase +// synthesis translate_off + dummy_d_398 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_399; +// synthesis translate_on +always @(*) begin + vns_array_muxed11 <= 1'd0; + case (soc_sdram_steerer_sel1) + 1'd0: begin + vns_array_muxed11 <= 1'd0; + end + 1'd1: begin + vns_array_muxed11 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we); + end + 2'd2: begin + vns_array_muxed11 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we); + end + default: begin + vns_array_muxed11 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we); + end + endcase +// synthesis translate_off + dummy_d_399 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_400; +// synthesis translate_on +always @(*) begin + vns_array_muxed12 <= 1'd0; + case (soc_sdram_steerer_sel1) + 1'd0: begin + vns_array_muxed12 <= 1'd0; + end + 1'd1: begin + vns_array_muxed12 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + vns_array_muxed12 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read); + end + default: begin + vns_array_muxed12 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read); + end + endcase +// synthesis translate_off + dummy_d_400 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_401; +// synthesis translate_on +always @(*) begin + vns_array_muxed13 <= 1'd0; + case (soc_sdram_steerer_sel1) + 1'd0: begin + vns_array_muxed13 <= 1'd0; + end + 1'd1: begin + vns_array_muxed13 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + vns_array_muxed13 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write); + end + default: begin + vns_array_muxed13 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write); + end + endcase +// synthesis translate_off + dummy_d_401 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_402; +// synthesis translate_on +always @(*) begin + vns_array_muxed14 <= 3'd0; + case (soc_sdram_steerer_sel2) + 1'd0: begin + vns_array_muxed14 <= soc_sdram_nop_ba[2:0]; + end + 1'd1: begin + vns_array_muxed14 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + vns_array_muxed14 <= soc_sdram_choose_req_cmd_payload_ba[2:0]; + end + default: begin + vns_array_muxed14 <= soc_sdram_cmd_payload_ba[2:0]; + end + endcase +// synthesis translate_off + dummy_d_402 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_403; +// synthesis translate_on +always @(*) begin + vns_array_muxed15 <= 15'd0; + case (soc_sdram_steerer_sel2) + 1'd0: begin + vns_array_muxed15 <= soc_sdram_nop_a; + end + 1'd1: begin + vns_array_muxed15 <= soc_sdram_choose_cmd_cmd_payload_a; + end + 2'd2: begin + vns_array_muxed15 <= soc_sdram_choose_req_cmd_payload_a; + end + default: begin + vns_array_muxed15 <= soc_sdram_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_403 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_404; +// synthesis translate_on +always @(*) begin + vns_array_muxed16 <= 1'd0; + case (soc_sdram_steerer_sel2) + 1'd0: begin + vns_array_muxed16 <= 1'd0; + end + 1'd1: begin + vns_array_muxed16 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + vns_array_muxed16 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas); + end + default: begin + vns_array_muxed16 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas); + end + endcase +// synthesis translate_off + dummy_d_404 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_405; +// synthesis translate_on +always @(*) begin + vns_array_muxed17 <= 1'd0; + case (soc_sdram_steerer_sel2) + 1'd0: begin + vns_array_muxed17 <= 1'd0; + end + 1'd1: begin + vns_array_muxed17 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + vns_array_muxed17 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras); + end + default: begin + vns_array_muxed17 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras); + end + endcase +// synthesis translate_off + dummy_d_405 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_406; +// synthesis translate_on +always @(*) begin + vns_array_muxed18 <= 1'd0; + case (soc_sdram_steerer_sel2) + 1'd0: begin + vns_array_muxed18 <= 1'd0; + end + 1'd1: begin + vns_array_muxed18 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we); + end + 2'd2: begin + vns_array_muxed18 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we); + end + default: begin + vns_array_muxed18 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we); + end + endcase +// synthesis translate_off + dummy_d_406 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_407; +// synthesis translate_on +always @(*) begin + vns_array_muxed19 <= 1'd0; + case (soc_sdram_steerer_sel2) + 1'd0: begin + vns_array_muxed19 <= 1'd0; + end + 1'd1: begin + vns_array_muxed19 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + vns_array_muxed19 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read); + end + default: begin + vns_array_muxed19 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read); + end + endcase +// synthesis translate_off + dummy_d_407 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_408; +// synthesis translate_on +always @(*) begin + vns_array_muxed20 <= 1'd0; + case (soc_sdram_steerer_sel2) + 1'd0: begin + vns_array_muxed20 <= 1'd0; + end + 1'd1: begin + vns_array_muxed20 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + vns_array_muxed20 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write); + end + default: begin + vns_array_muxed20 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write); + end + endcase +// synthesis translate_off + dummy_d_408 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_409; +// synthesis translate_on +always @(*) begin + vns_array_muxed21 <= 3'd0; + case (soc_sdram_steerer_sel3) + 1'd0: begin + vns_array_muxed21 <= soc_sdram_nop_ba[2:0]; + end + 1'd1: begin + vns_array_muxed21 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + vns_array_muxed21 <= soc_sdram_choose_req_cmd_payload_ba[2:0]; + end + default: begin + vns_array_muxed21 <= soc_sdram_cmd_payload_ba[2:0]; + end + endcase +// synthesis translate_off + dummy_d_409 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_410; +// synthesis translate_on +always @(*) begin + vns_array_muxed22 <= 15'd0; + case (soc_sdram_steerer_sel3) + 1'd0: begin + vns_array_muxed22 <= soc_sdram_nop_a; + end + 1'd1: begin + vns_array_muxed22 <= soc_sdram_choose_cmd_cmd_payload_a; + end + 2'd2: begin + vns_array_muxed22 <= soc_sdram_choose_req_cmd_payload_a; + end + default: begin + vns_array_muxed22 <= soc_sdram_cmd_payload_a; + end + endcase +// synthesis translate_off + dummy_d_410 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_411; +// synthesis translate_on +always @(*) begin + vns_array_muxed23 <= 1'd0; + case (soc_sdram_steerer_sel3) + 1'd0: begin + vns_array_muxed23 <= 1'd0; + end + 1'd1: begin + vns_array_muxed23 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + vns_array_muxed23 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas); + end + default: begin + vns_array_muxed23 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas); + end + endcase +// synthesis translate_off + dummy_d_411 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_412; +// synthesis translate_on +always @(*) begin + vns_array_muxed24 <= 1'd0; + case (soc_sdram_steerer_sel3) + 1'd0: begin + vns_array_muxed24 <= 1'd0; + end + 1'd1: begin + vns_array_muxed24 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + vns_array_muxed24 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras); + end + default: begin + vns_array_muxed24 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras); + end + endcase +// synthesis translate_off + dummy_d_412 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_413; +// synthesis translate_on +always @(*) begin + vns_array_muxed25 <= 1'd0; + case (soc_sdram_steerer_sel3) + 1'd0: begin + vns_array_muxed25 <= 1'd0; + end + 1'd1: begin + vns_array_muxed25 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we); + end + 2'd2: begin + vns_array_muxed25 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we); + end + default: begin + vns_array_muxed25 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we); + end + endcase +// synthesis translate_off + dummy_d_413 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_414; +// synthesis translate_on +always @(*) begin + vns_array_muxed26 <= 1'd0; + case (soc_sdram_steerer_sel3) + 1'd0: begin + vns_array_muxed26 <= 1'd0; + end + 1'd1: begin + vns_array_muxed26 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + vns_array_muxed26 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read); + end + default: begin + vns_array_muxed26 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read); + end + endcase +// synthesis translate_off + dummy_d_414 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_415; +// synthesis translate_on +always @(*) begin + vns_array_muxed27 <= 1'd0; + case (soc_sdram_steerer_sel3) + 1'd0: begin + vns_array_muxed27 <= 1'd0; + end + 1'd1: begin + vns_array_muxed27 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + vns_array_muxed27 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write); + end + default: begin + vns_array_muxed27 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write); + end + endcase +// synthesis translate_off + dummy_d_415 = dummy_s; +// synthesis translate_on +end +assign soc_litedramcore_rx = vns_regs1; +assign vns_xilinxasyncresetsynchronizerimpl0 = ((~soc_sys_pll_locked) | soc_sys_pll_reset); +assign vns_xilinxasyncresetsynchronizerimpl1 = ((~soc_sys_pll_locked) | soc_sys_pll_reset); +assign vns_xilinxasyncresetsynchronizerimpl2 = ((~soc_sys_pll_locked) | soc_sys_pll_reset); +assign vns_xilinxasyncresetsynchronizerimpl3 = ((~soc_iodelay_pll_locked) | soc_iodelay_pll_reset); + +always @(posedge iodelay_clk) begin + if ((soc_reset_counter != 1'd0)) begin + soc_reset_counter <= (soc_reset_counter - 1'd1); + end else begin + soc_ic_reset <= 1'd0; + end + if (iodelay_rst) begin + soc_reset_counter <= 4'd15; + soc_ic_reset <= 1'd1; + end +end + +always @(posedge sys_clk) begin + if ((soc_litedramcore_soccontroller_bus_errors != 32'd4294967295)) begin + if (soc_litedramcore_soccontroller_bus_error) begin + soc_litedramcore_soccontroller_bus_errors <= (soc_litedramcore_soccontroller_bus_errors + 1'd1); + end + end + soc_litedramcore_litedramcore_ram_bus_ack <= 1'd0; + if (((soc_litedramcore_litedramcore_ram_bus_cyc & soc_litedramcore_litedramcore_ram_bus_stb) & (~soc_litedramcore_litedramcore_ram_bus_ack))) begin + soc_litedramcore_litedramcore_ram_bus_ack <= 1'd1; + end + soc_litedramcore_ram_bus_ram_bus_ack <= 1'd0; + if (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & (~soc_litedramcore_ram_bus_ram_bus_ack))) begin + soc_litedramcore_ram_bus_ram_bus_ack <= 1'd1; + end + soc_litedramcore_sink_ready <= 1'd0; + if (((soc_litedramcore_sink_valid & (~soc_litedramcore_tx_busy)) & (~soc_litedramcore_sink_ready))) begin + soc_litedramcore_tx_reg <= soc_litedramcore_sink_payload_data; + soc_litedramcore_tx_bitcount <= 1'd0; + soc_litedramcore_tx_busy <= 1'd1; + serial_tx <= 1'd0; + end else begin + if ((soc_litedramcore_uart_clk_txen & soc_litedramcore_tx_busy)) begin + soc_litedramcore_tx_bitcount <= (soc_litedramcore_tx_bitcount + 1'd1); + if ((soc_litedramcore_tx_bitcount == 4'd8)) begin + serial_tx <= 1'd1; + end else begin + if ((soc_litedramcore_tx_bitcount == 4'd9)) begin + serial_tx <= 1'd1; + soc_litedramcore_tx_busy <= 1'd0; + soc_litedramcore_sink_ready <= 1'd1; + end else begin + serial_tx <= soc_litedramcore_tx_reg[0]; + soc_litedramcore_tx_reg <= {1'd0, soc_litedramcore_tx_reg[7:1]}; + end + end + end + end + if (soc_litedramcore_tx_busy) begin + {soc_litedramcore_uart_clk_txen, soc_litedramcore_phase_accumulator_tx} <= (soc_litedramcore_phase_accumulator_tx + soc_litedramcore_storage); + end else begin + {soc_litedramcore_uart_clk_txen, soc_litedramcore_phase_accumulator_tx} <= 1'd0; + end + soc_litedramcore_source_valid <= 1'd0; + soc_litedramcore_rx_r <= soc_litedramcore_rx; + if ((~soc_litedramcore_rx_busy)) begin + if (((~soc_litedramcore_rx) & soc_litedramcore_rx_r)) begin + soc_litedramcore_rx_busy <= 1'd1; + soc_litedramcore_rx_bitcount <= 1'd0; + end + end else begin + if (soc_litedramcore_uart_clk_rxen) begin + soc_litedramcore_rx_bitcount <= (soc_litedramcore_rx_bitcount + 1'd1); + if ((soc_litedramcore_rx_bitcount == 1'd0)) begin + if (soc_litedramcore_rx) begin + soc_litedramcore_rx_busy <= 1'd0; + end + end else begin + if ((soc_litedramcore_rx_bitcount == 4'd9)) begin + soc_litedramcore_rx_busy <= 1'd0; + if (soc_litedramcore_rx) begin + soc_litedramcore_source_payload_data <= soc_litedramcore_rx_reg; + soc_litedramcore_source_valid <= 1'd1; + end + end else begin + soc_litedramcore_rx_reg <= {soc_litedramcore_rx, soc_litedramcore_rx_reg[7:1]}; + end + end + end + end + if (soc_litedramcore_rx_busy) begin + {soc_litedramcore_uart_clk_rxen, soc_litedramcore_phase_accumulator_rx} <= (soc_litedramcore_phase_accumulator_rx + soc_litedramcore_storage); + end else begin + {soc_litedramcore_uart_clk_rxen, soc_litedramcore_phase_accumulator_rx} <= 32'd2147483648; + end + if (soc_litedramcore_uart_tx_clear) begin + soc_litedramcore_uart_tx_pending <= 1'd0; + end + soc_litedramcore_uart_tx_old_trigger <= soc_litedramcore_uart_tx_trigger; + if (((~soc_litedramcore_uart_tx_trigger) & soc_litedramcore_uart_tx_old_trigger)) begin + soc_litedramcore_uart_tx_pending <= 1'd1; + end + if (soc_litedramcore_uart_rx_clear) begin + soc_litedramcore_uart_rx_pending <= 1'd0; + end + soc_litedramcore_uart_rx_old_trigger <= soc_litedramcore_uart_rx_trigger; + if (((~soc_litedramcore_uart_rx_trigger) & soc_litedramcore_uart_rx_old_trigger)) begin + soc_litedramcore_uart_rx_pending <= 1'd1; + end + if (soc_litedramcore_uart_tx_fifo_syncfifo_re) begin + soc_litedramcore_uart_tx_fifo_readable <= 1'd1; + end else begin + if (soc_litedramcore_uart_tx_fifo_re) begin + soc_litedramcore_uart_tx_fifo_readable <= 1'd0; + end + end + if (((soc_litedramcore_uart_tx_fifo_syncfifo_we & soc_litedramcore_uart_tx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_tx_fifo_replace))) begin + soc_litedramcore_uart_tx_fifo_produce <= (soc_litedramcore_uart_tx_fifo_produce + 1'd1); + end + if (soc_litedramcore_uart_tx_fifo_do_read) begin + soc_litedramcore_uart_tx_fifo_consume <= (soc_litedramcore_uart_tx_fifo_consume + 1'd1); + end + if (((soc_litedramcore_uart_tx_fifo_syncfifo_we & soc_litedramcore_uart_tx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_tx_fifo_replace))) begin + if ((~soc_litedramcore_uart_tx_fifo_do_read)) begin + soc_litedramcore_uart_tx_fifo_level0 <= (soc_litedramcore_uart_tx_fifo_level0 + 1'd1); + end + end else begin + if (soc_litedramcore_uart_tx_fifo_do_read) begin + soc_litedramcore_uart_tx_fifo_level0 <= (soc_litedramcore_uart_tx_fifo_level0 - 1'd1); + end + end + if (soc_litedramcore_uart_rx_fifo_syncfifo_re) begin + soc_litedramcore_uart_rx_fifo_readable <= 1'd1; + end else begin + if (soc_litedramcore_uart_rx_fifo_re) begin + soc_litedramcore_uart_rx_fifo_readable <= 1'd0; + end + end + if (((soc_litedramcore_uart_rx_fifo_syncfifo_we & soc_litedramcore_uart_rx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_rx_fifo_replace))) begin + soc_litedramcore_uart_rx_fifo_produce <= (soc_litedramcore_uart_rx_fifo_produce + 1'd1); + end + if (soc_litedramcore_uart_rx_fifo_do_read) begin + soc_litedramcore_uart_rx_fifo_consume <= (soc_litedramcore_uart_rx_fifo_consume + 1'd1); + end + if (((soc_litedramcore_uart_rx_fifo_syncfifo_we & soc_litedramcore_uart_rx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_rx_fifo_replace))) begin + if ((~soc_litedramcore_uart_rx_fifo_do_read)) begin + soc_litedramcore_uart_rx_fifo_level0 <= (soc_litedramcore_uart_rx_fifo_level0 + 1'd1); + end + end else begin + if (soc_litedramcore_uart_rx_fifo_do_read) begin + soc_litedramcore_uart_rx_fifo_level0 <= (soc_litedramcore_uart_rx_fifo_level0 - 1'd1); + end + end + if (soc_litedramcore_uart_reset) begin + soc_litedramcore_uart_tx_pending <= 1'd0; + soc_litedramcore_uart_tx_old_trigger <= 1'd0; + soc_litedramcore_uart_rx_pending <= 1'd0; + soc_litedramcore_uart_rx_old_trigger <= 1'd0; + soc_litedramcore_uart_tx_fifo_readable <= 1'd0; + soc_litedramcore_uart_tx_fifo_level0 <= 5'd0; + soc_litedramcore_uart_tx_fifo_produce <= 4'd0; + soc_litedramcore_uart_tx_fifo_consume <= 4'd0; + soc_litedramcore_uart_rx_fifo_readable <= 1'd0; + soc_litedramcore_uart_rx_fifo_level0 <= 5'd0; + soc_litedramcore_uart_rx_fifo_produce <= 4'd0; + soc_litedramcore_uart_rx_fifo_consume <= 4'd0; + end + if (soc_litedramcore_timer_en_storage) begin + if ((soc_litedramcore_timer_value == 1'd0)) begin + soc_litedramcore_timer_value <= soc_litedramcore_timer_reload_storage; + end else begin + soc_litedramcore_timer_value <= (soc_litedramcore_timer_value - 1'd1); + end + end else begin + soc_litedramcore_timer_value <= soc_litedramcore_timer_load_storage; + end + if (soc_litedramcore_timer_update_value_re) begin + soc_litedramcore_timer_value_status <= soc_litedramcore_timer_value; + end + if (soc_litedramcore_timer_zero_clear) begin + soc_litedramcore_timer_zero_pending <= 1'd0; + end + soc_litedramcore_timer_zero_old_trigger <= soc_litedramcore_timer_zero_trigger; + if (((~soc_litedramcore_timer_zero_trigger) & soc_litedramcore_timer_zero_old_trigger)) begin + soc_litedramcore_timer_zero_pending <= 1'd1; + end + vns_wb2csr_state <= vns_wb2csr_next_state; + soc_a7ddrphy_dqs_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dqs_oe) | soc_a7ddrphy_dqspattern1); + soc_a7ddrphy_dq_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dq_oe) | soc_a7ddrphy_dqspattern1); + soc_a7ddrphy_rddata_en_last <= soc_a7ddrphy_rddata_en; + soc_a7ddrphy_dfi_p0_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); + soc_a7ddrphy_dfi_p1_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); + soc_a7ddrphy_dfi_p2_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); + soc_a7ddrphy_dfi_p3_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); + soc_a7ddrphy_wrdata_en_last <= soc_a7ddrphy_wrdata_en; + soc_a7ddrphy_dqspattern_o1 <= soc_a7ddrphy_dqspattern_o0; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip0_value <= (soc_a7ddrphy_bitslip0_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip0_value <= 1'd0; + end + soc_a7ddrphy_bitslip0_r <= {soc_a7ddrphy_bitslip0_i, soc_a7ddrphy_bitslip0_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip1_value <= (soc_a7ddrphy_bitslip1_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip1_value <= 1'd0; + end + soc_a7ddrphy_bitslip1_r <= {soc_a7ddrphy_bitslip1_i, soc_a7ddrphy_bitslip1_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip2_value <= (soc_a7ddrphy_bitslip2_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip2_value <= 1'd0; + end + soc_a7ddrphy_bitslip2_r <= {soc_a7ddrphy_bitslip2_i, soc_a7ddrphy_bitslip2_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip3_value <= (soc_a7ddrphy_bitslip3_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip3_value <= 1'd0; + end + soc_a7ddrphy_bitslip3_r <= {soc_a7ddrphy_bitslip3_i, soc_a7ddrphy_bitslip3_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip4_value <= (soc_a7ddrphy_bitslip4_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip4_value <= 1'd0; + end + soc_a7ddrphy_bitslip4_r <= {soc_a7ddrphy_bitslip4_i, soc_a7ddrphy_bitslip4_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip5_value <= (soc_a7ddrphy_bitslip5_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip5_value <= 1'd0; + end + soc_a7ddrphy_bitslip5_r <= {soc_a7ddrphy_bitslip5_i, soc_a7ddrphy_bitslip5_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip6_value <= (soc_a7ddrphy_bitslip6_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip6_value <= 1'd0; + end + soc_a7ddrphy_bitslip6_r <= {soc_a7ddrphy_bitslip6_i, soc_a7ddrphy_bitslip6_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip7_value <= (soc_a7ddrphy_bitslip7_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip7_value <= 1'd0; + end + soc_a7ddrphy_bitslip7_r <= {soc_a7ddrphy_bitslip7_i, soc_a7ddrphy_bitslip7_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip8_value <= (soc_a7ddrphy_bitslip8_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip8_value <= 1'd0; + end + soc_a7ddrphy_bitslip8_r <= {soc_a7ddrphy_bitslip8_i, soc_a7ddrphy_bitslip8_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip9_value <= (soc_a7ddrphy_bitslip9_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip9_value <= 1'd0; + end + soc_a7ddrphy_bitslip9_r <= {soc_a7ddrphy_bitslip9_i, soc_a7ddrphy_bitslip9_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip10_value <= (soc_a7ddrphy_bitslip10_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip10_value <= 1'd0; + end + soc_a7ddrphy_bitslip10_r <= {soc_a7ddrphy_bitslip10_i, soc_a7ddrphy_bitslip10_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip11_value <= (soc_a7ddrphy_bitslip11_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip11_value <= 1'd0; + end + soc_a7ddrphy_bitslip11_r <= {soc_a7ddrphy_bitslip11_i, soc_a7ddrphy_bitslip11_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip12_value <= (soc_a7ddrphy_bitslip12_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip12_value <= 1'd0; + end + soc_a7ddrphy_bitslip12_r <= {soc_a7ddrphy_bitslip12_i, soc_a7ddrphy_bitslip12_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip13_value <= (soc_a7ddrphy_bitslip13_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip13_value <= 1'd0; + end + soc_a7ddrphy_bitslip13_r <= {soc_a7ddrphy_bitslip13_i, soc_a7ddrphy_bitslip13_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip14_value <= (soc_a7ddrphy_bitslip14_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip14_value <= 1'd0; + end + soc_a7ddrphy_bitslip14_r <= {soc_a7ddrphy_bitslip14_i, soc_a7ddrphy_bitslip14_r[15:8]}; + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin + soc_a7ddrphy_bitslip15_value <= (soc_a7ddrphy_bitslip15_value + 1'd1); + end + if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin + soc_a7ddrphy_bitslip15_value <= 1'd0; + end + soc_a7ddrphy_bitslip15_r <= {soc_a7ddrphy_bitslip15_i, soc_a7ddrphy_bitslip15_r[15:8]}; + if (soc_sdram_inti_p0_rddata_valid) begin + soc_sdram_phaseinjector0_status <= soc_sdram_inti_p0_rddata; + end + if (soc_sdram_inti_p1_rddata_valid) begin + soc_sdram_phaseinjector1_status <= soc_sdram_inti_p1_rddata; + end + if (soc_sdram_inti_p2_rddata_valid) begin + soc_sdram_phaseinjector2_status <= soc_sdram_inti_p2_rddata; + end + if (soc_sdram_inti_p3_rddata_valid) begin + soc_sdram_phaseinjector3_status <= soc_sdram_inti_p3_rddata; + end + if ((soc_sdram_timer_wait & (~soc_sdram_timer_done0))) begin + soc_sdram_timer_count1 <= (soc_sdram_timer_count1 - 1'd1); + end else begin + soc_sdram_timer_count1 <= 10'd781; + end + soc_sdram_postponer_req_o <= 1'd0; + if (soc_sdram_postponer_req_i) begin + soc_sdram_postponer_count <= (soc_sdram_postponer_count - 1'd1); + if ((soc_sdram_postponer_count == 1'd0)) begin + soc_sdram_postponer_count <= 1'd0; + soc_sdram_postponer_req_o <= 1'd1; + end + end + if (soc_sdram_sequencer_start0) begin + soc_sdram_sequencer_count <= 1'd0; + end else begin + if (soc_sdram_sequencer_done1) begin + if ((soc_sdram_sequencer_count != 1'd0)) begin + soc_sdram_sequencer_count <= (soc_sdram_sequencer_count - 1'd1); + end + end + end + soc_sdram_cmd_payload_a <= 1'd0; + soc_sdram_cmd_payload_ba <= 1'd0; + soc_sdram_cmd_payload_cas <= 1'd0; + soc_sdram_cmd_payload_ras <= 1'd0; + soc_sdram_cmd_payload_we <= 1'd0; + soc_sdram_sequencer_done1 <= 1'd0; + if ((soc_sdram_sequencer_start1 & (soc_sdram_sequencer_counter == 1'd0))) begin + soc_sdram_cmd_payload_a <= 11'd1024; + soc_sdram_cmd_payload_ba <= 1'd0; + soc_sdram_cmd_payload_cas <= 1'd0; + soc_sdram_cmd_payload_ras <= 1'd1; + soc_sdram_cmd_payload_we <= 1'd1; + end + if ((soc_sdram_sequencer_counter == 2'd3)) begin + soc_sdram_cmd_payload_a <= 1'd0; + soc_sdram_cmd_payload_ba <= 1'd0; + soc_sdram_cmd_payload_cas <= 1'd1; + soc_sdram_cmd_payload_ras <= 1'd1; + soc_sdram_cmd_payload_we <= 1'd0; + end + if ((soc_sdram_sequencer_counter == 6'd55)) begin + soc_sdram_cmd_payload_a <= 1'd0; + soc_sdram_cmd_payload_ba <= 1'd0; + soc_sdram_cmd_payload_cas <= 1'd0; + soc_sdram_cmd_payload_ras <= 1'd0; + soc_sdram_cmd_payload_we <= 1'd0; + soc_sdram_sequencer_done1 <= 1'd1; + end + if ((soc_sdram_sequencer_counter == 6'd55)) begin + soc_sdram_sequencer_counter <= 1'd0; + end else begin + if ((soc_sdram_sequencer_counter != 1'd0)) begin + soc_sdram_sequencer_counter <= (soc_sdram_sequencer_counter + 1'd1); + end else begin + if (soc_sdram_sequencer_start1) begin + soc_sdram_sequencer_counter <= 1'd1; + end + end + end + if ((soc_sdram_zqcs_timer_wait & (~soc_sdram_zqcs_timer_done0))) begin + soc_sdram_zqcs_timer_count1 <= (soc_sdram_zqcs_timer_count1 - 1'd1); + end else begin + soc_sdram_zqcs_timer_count1 <= 27'd99999999; + end + soc_sdram_zqcs_executer_done <= 1'd0; + if ((soc_sdram_zqcs_executer_start & (soc_sdram_zqcs_executer_counter == 1'd0))) begin + soc_sdram_cmd_payload_a <= 11'd1024; + soc_sdram_cmd_payload_ba <= 1'd0; + soc_sdram_cmd_payload_cas <= 1'd0; + soc_sdram_cmd_payload_ras <= 1'd1; + soc_sdram_cmd_payload_we <= 1'd1; + end + if ((soc_sdram_zqcs_executer_counter == 2'd3)) begin + soc_sdram_cmd_payload_a <= 1'd0; + soc_sdram_cmd_payload_ba <= 1'd0; + soc_sdram_cmd_payload_cas <= 1'd0; + soc_sdram_cmd_payload_ras <= 1'd0; + soc_sdram_cmd_payload_we <= 1'd1; + end + if ((soc_sdram_zqcs_executer_counter == 5'd19)) begin + soc_sdram_cmd_payload_a <= 1'd0; + soc_sdram_cmd_payload_ba <= 1'd0; + soc_sdram_cmd_payload_cas <= 1'd0; + soc_sdram_cmd_payload_ras <= 1'd0; + soc_sdram_cmd_payload_we <= 1'd0; + soc_sdram_zqcs_executer_done <= 1'd1; + end + if ((soc_sdram_zqcs_executer_counter == 5'd19)) begin + soc_sdram_zqcs_executer_counter <= 1'd0; + end else begin + if ((soc_sdram_zqcs_executer_counter != 1'd0)) begin + soc_sdram_zqcs_executer_counter <= (soc_sdram_zqcs_executer_counter + 1'd1); + end else begin + if (soc_sdram_zqcs_executer_start) begin + soc_sdram_zqcs_executer_counter <= 1'd1; + end + end + end + vns_refresher_state <= vns_refresher_next_state; + if (soc_sdram_bankmachine0_row_close) begin + soc_sdram_bankmachine0_row_opened <= 1'd0; + end else begin + if (soc_sdram_bankmachine0_row_open) begin + soc_sdram_bankmachine0_row_opened <= 1'd1; + soc_sdram_bankmachine0_row <= soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin + soc_sdram_bankmachine0_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine0_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin + if ((~soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin + soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_sdram_bankmachine0_cmd_buffer_source_valid) | soc_sdram_bankmachine0_cmd_buffer_source_ready)) begin + soc_sdram_bankmachine0_cmd_buffer_source_valid <= soc_sdram_bankmachine0_cmd_buffer_sink_valid; + soc_sdram_bankmachine0_cmd_buffer_source_first <= soc_sdram_bankmachine0_cmd_buffer_sink_first; + soc_sdram_bankmachine0_cmd_buffer_source_last <= soc_sdram_bankmachine0_cmd_buffer_sink_last; + soc_sdram_bankmachine0_cmd_buffer_source_payload_we <= soc_sdram_bankmachine0_cmd_buffer_sink_payload_we; + soc_sdram_bankmachine0_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr; + end + if (soc_sdram_bankmachine0_twtpcon_valid) begin + soc_sdram_bankmachine0_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine0_twtpcon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine0_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine0_twtpcon_ready)) begin + soc_sdram_bankmachine0_twtpcon_count <= (soc_sdram_bankmachine0_twtpcon_count - 1'd1); + if ((soc_sdram_bankmachine0_twtpcon_count == 1'd1)) begin + soc_sdram_bankmachine0_twtpcon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine0_trccon_valid) begin + soc_sdram_bankmachine0_trccon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine0_trccon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine0_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine0_trccon_ready)) begin + soc_sdram_bankmachine0_trccon_count <= (soc_sdram_bankmachine0_trccon_count - 1'd1); + if ((soc_sdram_bankmachine0_trccon_count == 1'd1)) begin + soc_sdram_bankmachine0_trccon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine0_trascon_valid) begin + soc_sdram_bankmachine0_trascon_count <= 3'd4; + if (1'd0) begin + soc_sdram_bankmachine0_trascon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine0_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine0_trascon_ready)) begin + soc_sdram_bankmachine0_trascon_count <= (soc_sdram_bankmachine0_trascon_count - 1'd1); + if ((soc_sdram_bankmachine0_trascon_count == 1'd1)) begin + soc_sdram_bankmachine0_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine0_state <= vns_bankmachine0_next_state; + if (soc_sdram_bankmachine1_row_close) begin + soc_sdram_bankmachine1_row_opened <= 1'd0; + end else begin + if (soc_sdram_bankmachine1_row_open) begin + soc_sdram_bankmachine1_row_opened <= 1'd1; + soc_sdram_bankmachine1_row <= soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin + soc_sdram_bankmachine1_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine1_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin + if ((~soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin + soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_sdram_bankmachine1_cmd_buffer_source_valid) | soc_sdram_bankmachine1_cmd_buffer_source_ready)) begin + soc_sdram_bankmachine1_cmd_buffer_source_valid <= soc_sdram_bankmachine1_cmd_buffer_sink_valid; + soc_sdram_bankmachine1_cmd_buffer_source_first <= soc_sdram_bankmachine1_cmd_buffer_sink_first; + soc_sdram_bankmachine1_cmd_buffer_source_last <= soc_sdram_bankmachine1_cmd_buffer_sink_last; + soc_sdram_bankmachine1_cmd_buffer_source_payload_we <= soc_sdram_bankmachine1_cmd_buffer_sink_payload_we; + soc_sdram_bankmachine1_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr; + end + if (soc_sdram_bankmachine1_twtpcon_valid) begin + soc_sdram_bankmachine1_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine1_twtpcon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine1_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine1_twtpcon_ready)) begin + soc_sdram_bankmachine1_twtpcon_count <= (soc_sdram_bankmachine1_twtpcon_count - 1'd1); + if ((soc_sdram_bankmachine1_twtpcon_count == 1'd1)) begin + soc_sdram_bankmachine1_twtpcon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine1_trccon_valid) begin + soc_sdram_bankmachine1_trccon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine1_trccon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine1_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine1_trccon_ready)) begin + soc_sdram_bankmachine1_trccon_count <= (soc_sdram_bankmachine1_trccon_count - 1'd1); + if ((soc_sdram_bankmachine1_trccon_count == 1'd1)) begin + soc_sdram_bankmachine1_trccon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine1_trascon_valid) begin + soc_sdram_bankmachine1_trascon_count <= 3'd4; + if (1'd0) begin + soc_sdram_bankmachine1_trascon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine1_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine1_trascon_ready)) begin + soc_sdram_bankmachine1_trascon_count <= (soc_sdram_bankmachine1_trascon_count - 1'd1); + if ((soc_sdram_bankmachine1_trascon_count == 1'd1)) begin + soc_sdram_bankmachine1_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine1_state <= vns_bankmachine1_next_state; + if (soc_sdram_bankmachine2_row_close) begin + soc_sdram_bankmachine2_row_opened <= 1'd0; + end else begin + if (soc_sdram_bankmachine2_row_open) begin + soc_sdram_bankmachine2_row_opened <= 1'd1; + soc_sdram_bankmachine2_row <= soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin + soc_sdram_bankmachine2_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine2_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin + if ((~soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin + soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_sdram_bankmachine2_cmd_buffer_source_valid) | soc_sdram_bankmachine2_cmd_buffer_source_ready)) begin + soc_sdram_bankmachine2_cmd_buffer_source_valid <= soc_sdram_bankmachine2_cmd_buffer_sink_valid; + soc_sdram_bankmachine2_cmd_buffer_source_first <= soc_sdram_bankmachine2_cmd_buffer_sink_first; + soc_sdram_bankmachine2_cmd_buffer_source_last <= soc_sdram_bankmachine2_cmd_buffer_sink_last; + soc_sdram_bankmachine2_cmd_buffer_source_payload_we <= soc_sdram_bankmachine2_cmd_buffer_sink_payload_we; + soc_sdram_bankmachine2_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr; + end + if (soc_sdram_bankmachine2_twtpcon_valid) begin + soc_sdram_bankmachine2_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine2_twtpcon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine2_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine2_twtpcon_ready)) begin + soc_sdram_bankmachine2_twtpcon_count <= (soc_sdram_bankmachine2_twtpcon_count - 1'd1); + if ((soc_sdram_bankmachine2_twtpcon_count == 1'd1)) begin + soc_sdram_bankmachine2_twtpcon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine2_trccon_valid) begin + soc_sdram_bankmachine2_trccon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine2_trccon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine2_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine2_trccon_ready)) begin + soc_sdram_bankmachine2_trccon_count <= (soc_sdram_bankmachine2_trccon_count - 1'd1); + if ((soc_sdram_bankmachine2_trccon_count == 1'd1)) begin + soc_sdram_bankmachine2_trccon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine2_trascon_valid) begin + soc_sdram_bankmachine2_trascon_count <= 3'd4; + if (1'd0) begin + soc_sdram_bankmachine2_trascon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine2_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine2_trascon_ready)) begin + soc_sdram_bankmachine2_trascon_count <= (soc_sdram_bankmachine2_trascon_count - 1'd1); + if ((soc_sdram_bankmachine2_trascon_count == 1'd1)) begin + soc_sdram_bankmachine2_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine2_state <= vns_bankmachine2_next_state; + if (soc_sdram_bankmachine3_row_close) begin + soc_sdram_bankmachine3_row_opened <= 1'd0; + end else begin + if (soc_sdram_bankmachine3_row_open) begin + soc_sdram_bankmachine3_row_opened <= 1'd1; + soc_sdram_bankmachine3_row <= soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin + soc_sdram_bankmachine3_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine3_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin + if ((~soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin + soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_sdram_bankmachine3_cmd_buffer_source_valid) | soc_sdram_bankmachine3_cmd_buffer_source_ready)) begin + soc_sdram_bankmachine3_cmd_buffer_source_valid <= soc_sdram_bankmachine3_cmd_buffer_sink_valid; + soc_sdram_bankmachine3_cmd_buffer_source_first <= soc_sdram_bankmachine3_cmd_buffer_sink_first; + soc_sdram_bankmachine3_cmd_buffer_source_last <= soc_sdram_bankmachine3_cmd_buffer_sink_last; + soc_sdram_bankmachine3_cmd_buffer_source_payload_we <= soc_sdram_bankmachine3_cmd_buffer_sink_payload_we; + soc_sdram_bankmachine3_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr; + end + if (soc_sdram_bankmachine3_twtpcon_valid) begin + soc_sdram_bankmachine3_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine3_twtpcon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine3_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine3_twtpcon_ready)) begin + soc_sdram_bankmachine3_twtpcon_count <= (soc_sdram_bankmachine3_twtpcon_count - 1'd1); + if ((soc_sdram_bankmachine3_twtpcon_count == 1'd1)) begin + soc_sdram_bankmachine3_twtpcon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine3_trccon_valid) begin + soc_sdram_bankmachine3_trccon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine3_trccon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine3_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine3_trccon_ready)) begin + soc_sdram_bankmachine3_trccon_count <= (soc_sdram_bankmachine3_trccon_count - 1'd1); + if ((soc_sdram_bankmachine3_trccon_count == 1'd1)) begin + soc_sdram_bankmachine3_trccon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine3_trascon_valid) begin + soc_sdram_bankmachine3_trascon_count <= 3'd4; + if (1'd0) begin + soc_sdram_bankmachine3_trascon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine3_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine3_trascon_ready)) begin + soc_sdram_bankmachine3_trascon_count <= (soc_sdram_bankmachine3_trascon_count - 1'd1); + if ((soc_sdram_bankmachine3_trascon_count == 1'd1)) begin + soc_sdram_bankmachine3_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine3_state <= vns_bankmachine3_next_state; + if (soc_sdram_bankmachine4_row_close) begin + soc_sdram_bankmachine4_row_opened <= 1'd0; + end else begin + if (soc_sdram_bankmachine4_row_open) begin + soc_sdram_bankmachine4_row_opened <= 1'd1; + soc_sdram_bankmachine4_row <= soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin + soc_sdram_bankmachine4_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine4_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin + if ((~soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read)) begin + soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_sdram_bankmachine4_cmd_buffer_source_valid) | soc_sdram_bankmachine4_cmd_buffer_source_ready)) begin + soc_sdram_bankmachine4_cmd_buffer_source_valid <= soc_sdram_bankmachine4_cmd_buffer_sink_valid; + soc_sdram_bankmachine4_cmd_buffer_source_first <= soc_sdram_bankmachine4_cmd_buffer_sink_first; + soc_sdram_bankmachine4_cmd_buffer_source_last <= soc_sdram_bankmachine4_cmd_buffer_sink_last; + soc_sdram_bankmachine4_cmd_buffer_source_payload_we <= soc_sdram_bankmachine4_cmd_buffer_sink_payload_we; + soc_sdram_bankmachine4_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr; + end + if (soc_sdram_bankmachine4_twtpcon_valid) begin + soc_sdram_bankmachine4_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine4_twtpcon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine4_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine4_twtpcon_ready)) begin + soc_sdram_bankmachine4_twtpcon_count <= (soc_sdram_bankmachine4_twtpcon_count - 1'd1); + if ((soc_sdram_bankmachine4_twtpcon_count == 1'd1)) begin + soc_sdram_bankmachine4_twtpcon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine4_trccon_valid) begin + soc_sdram_bankmachine4_trccon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine4_trccon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine4_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine4_trccon_ready)) begin + soc_sdram_bankmachine4_trccon_count <= (soc_sdram_bankmachine4_trccon_count - 1'd1); + if ((soc_sdram_bankmachine4_trccon_count == 1'd1)) begin + soc_sdram_bankmachine4_trccon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine4_trascon_valid) begin + soc_sdram_bankmachine4_trascon_count <= 3'd4; + if (1'd0) begin + soc_sdram_bankmachine4_trascon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine4_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine4_trascon_ready)) begin + soc_sdram_bankmachine4_trascon_count <= (soc_sdram_bankmachine4_trascon_count - 1'd1); + if ((soc_sdram_bankmachine4_trascon_count == 1'd1)) begin + soc_sdram_bankmachine4_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine4_state <= vns_bankmachine4_next_state; + if (soc_sdram_bankmachine5_row_close) begin + soc_sdram_bankmachine5_row_opened <= 1'd0; + end else begin + if (soc_sdram_bankmachine5_row_open) begin + soc_sdram_bankmachine5_row_opened <= 1'd1; + soc_sdram_bankmachine5_row <= soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin + soc_sdram_bankmachine5_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine5_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin + if ((~soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read)) begin + soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_sdram_bankmachine5_cmd_buffer_source_valid) | soc_sdram_bankmachine5_cmd_buffer_source_ready)) begin + soc_sdram_bankmachine5_cmd_buffer_source_valid <= soc_sdram_bankmachine5_cmd_buffer_sink_valid; + soc_sdram_bankmachine5_cmd_buffer_source_first <= soc_sdram_bankmachine5_cmd_buffer_sink_first; + soc_sdram_bankmachine5_cmd_buffer_source_last <= soc_sdram_bankmachine5_cmd_buffer_sink_last; + soc_sdram_bankmachine5_cmd_buffer_source_payload_we <= soc_sdram_bankmachine5_cmd_buffer_sink_payload_we; + soc_sdram_bankmachine5_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr; + end + if (soc_sdram_bankmachine5_twtpcon_valid) begin + soc_sdram_bankmachine5_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine5_twtpcon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine5_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine5_twtpcon_ready)) begin + soc_sdram_bankmachine5_twtpcon_count <= (soc_sdram_bankmachine5_twtpcon_count - 1'd1); + if ((soc_sdram_bankmachine5_twtpcon_count == 1'd1)) begin + soc_sdram_bankmachine5_twtpcon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine5_trccon_valid) begin + soc_sdram_bankmachine5_trccon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine5_trccon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine5_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine5_trccon_ready)) begin + soc_sdram_bankmachine5_trccon_count <= (soc_sdram_bankmachine5_trccon_count - 1'd1); + if ((soc_sdram_bankmachine5_trccon_count == 1'd1)) begin + soc_sdram_bankmachine5_trccon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine5_trascon_valid) begin + soc_sdram_bankmachine5_trascon_count <= 3'd4; + if (1'd0) begin + soc_sdram_bankmachine5_trascon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine5_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine5_trascon_ready)) begin + soc_sdram_bankmachine5_trascon_count <= (soc_sdram_bankmachine5_trascon_count - 1'd1); + if ((soc_sdram_bankmachine5_trascon_count == 1'd1)) begin + soc_sdram_bankmachine5_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine5_state <= vns_bankmachine5_next_state; + if (soc_sdram_bankmachine6_row_close) begin + soc_sdram_bankmachine6_row_opened <= 1'd0; + end else begin + if (soc_sdram_bankmachine6_row_open) begin + soc_sdram_bankmachine6_row_opened <= 1'd1; + soc_sdram_bankmachine6_row <= soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin + soc_sdram_bankmachine6_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine6_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin + if ((~soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read)) begin + soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_sdram_bankmachine6_cmd_buffer_source_valid) | soc_sdram_bankmachine6_cmd_buffer_source_ready)) begin + soc_sdram_bankmachine6_cmd_buffer_source_valid <= soc_sdram_bankmachine6_cmd_buffer_sink_valid; + soc_sdram_bankmachine6_cmd_buffer_source_first <= soc_sdram_bankmachine6_cmd_buffer_sink_first; + soc_sdram_bankmachine6_cmd_buffer_source_last <= soc_sdram_bankmachine6_cmd_buffer_sink_last; + soc_sdram_bankmachine6_cmd_buffer_source_payload_we <= soc_sdram_bankmachine6_cmd_buffer_sink_payload_we; + soc_sdram_bankmachine6_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr; + end + if (soc_sdram_bankmachine6_twtpcon_valid) begin + soc_sdram_bankmachine6_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine6_twtpcon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine6_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine6_twtpcon_ready)) begin + soc_sdram_bankmachine6_twtpcon_count <= (soc_sdram_bankmachine6_twtpcon_count - 1'd1); + if ((soc_sdram_bankmachine6_twtpcon_count == 1'd1)) begin + soc_sdram_bankmachine6_twtpcon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine6_trccon_valid) begin + soc_sdram_bankmachine6_trccon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine6_trccon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine6_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine6_trccon_ready)) begin + soc_sdram_bankmachine6_trccon_count <= (soc_sdram_bankmachine6_trccon_count - 1'd1); + if ((soc_sdram_bankmachine6_trccon_count == 1'd1)) begin + soc_sdram_bankmachine6_trccon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine6_trascon_valid) begin + soc_sdram_bankmachine6_trascon_count <= 3'd4; + if (1'd0) begin + soc_sdram_bankmachine6_trascon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine6_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine6_trascon_ready)) begin + soc_sdram_bankmachine6_trascon_count <= (soc_sdram_bankmachine6_trascon_count - 1'd1); + if ((soc_sdram_bankmachine6_trascon_count == 1'd1)) begin + soc_sdram_bankmachine6_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine6_state <= vns_bankmachine6_next_state; + if (soc_sdram_bankmachine7_row_close) begin + soc_sdram_bankmachine7_row_opened <= 1'd0; + end else begin + if (soc_sdram_bankmachine7_row_open) begin + soc_sdram_bankmachine7_row_opened <= 1'd1; + soc_sdram_bankmachine7_row <= soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin + soc_sdram_bankmachine7_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); + end + if (soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine7_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); + end + if (((soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin + if ((~soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read)) begin + soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin + soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~soc_sdram_bankmachine7_cmd_buffer_source_valid) | soc_sdram_bankmachine7_cmd_buffer_source_ready)) begin + soc_sdram_bankmachine7_cmd_buffer_source_valid <= soc_sdram_bankmachine7_cmd_buffer_sink_valid; + soc_sdram_bankmachine7_cmd_buffer_source_first <= soc_sdram_bankmachine7_cmd_buffer_sink_first; + soc_sdram_bankmachine7_cmd_buffer_source_last <= soc_sdram_bankmachine7_cmd_buffer_sink_last; + soc_sdram_bankmachine7_cmd_buffer_source_payload_we <= soc_sdram_bankmachine7_cmd_buffer_sink_payload_we; + soc_sdram_bankmachine7_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr; + end + if (soc_sdram_bankmachine7_twtpcon_valid) begin + soc_sdram_bankmachine7_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine7_twtpcon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine7_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine7_twtpcon_ready)) begin + soc_sdram_bankmachine7_twtpcon_count <= (soc_sdram_bankmachine7_twtpcon_count - 1'd1); + if ((soc_sdram_bankmachine7_twtpcon_count == 1'd1)) begin + soc_sdram_bankmachine7_twtpcon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine7_trccon_valid) begin + soc_sdram_bankmachine7_trccon_count <= 3'd5; + if (1'd0) begin + soc_sdram_bankmachine7_trccon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine7_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine7_trccon_ready)) begin + soc_sdram_bankmachine7_trccon_count <= (soc_sdram_bankmachine7_trccon_count - 1'd1); + if ((soc_sdram_bankmachine7_trccon_count == 1'd1)) begin + soc_sdram_bankmachine7_trccon_ready <= 1'd1; + end + end + end + if (soc_sdram_bankmachine7_trascon_valid) begin + soc_sdram_bankmachine7_trascon_count <= 3'd4; + if (1'd0) begin + soc_sdram_bankmachine7_trascon_ready <= 1'd1; + end else begin + soc_sdram_bankmachine7_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_bankmachine7_trascon_ready)) begin + soc_sdram_bankmachine7_trascon_count <= (soc_sdram_bankmachine7_trascon_count - 1'd1); + if ((soc_sdram_bankmachine7_trascon_count == 1'd1)) begin + soc_sdram_bankmachine7_trascon_ready <= 1'd1; + end + end + end + vns_bankmachine7_state <= vns_bankmachine7_next_state; + if ((~soc_sdram_en0)) begin + soc_sdram_time0 <= 5'd31; + end else begin + if ((~soc_sdram_max_time0)) begin + soc_sdram_time0 <= (soc_sdram_time0 - 1'd1); + end + end + if ((~soc_sdram_en1)) begin + soc_sdram_time1 <= 4'd15; + end else begin + if ((~soc_sdram_max_time1)) begin + soc_sdram_time1 <= (soc_sdram_time1 - 1'd1); + end + end + if (soc_sdram_choose_cmd_ce) begin + case (soc_sdram_choose_cmd_grant) + 1'd0: begin + if (soc_sdram_choose_cmd_request[1]) begin + soc_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (soc_sdram_choose_cmd_request[2]) begin + soc_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (soc_sdram_choose_cmd_request[3]) begin + soc_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (soc_sdram_choose_cmd_request[4]) begin + soc_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (soc_sdram_choose_cmd_request[5]) begin + soc_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (soc_sdram_choose_cmd_request[6]) begin + soc_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (soc_sdram_choose_cmd_request[7]) begin + soc_sdram_choose_cmd_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (soc_sdram_choose_cmd_request[2]) begin + soc_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (soc_sdram_choose_cmd_request[3]) begin + soc_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (soc_sdram_choose_cmd_request[4]) begin + soc_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (soc_sdram_choose_cmd_request[5]) begin + soc_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (soc_sdram_choose_cmd_request[6]) begin + soc_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (soc_sdram_choose_cmd_request[7]) begin + soc_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (soc_sdram_choose_cmd_request[0]) begin + soc_sdram_choose_cmd_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (soc_sdram_choose_cmd_request[3]) begin + soc_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (soc_sdram_choose_cmd_request[4]) begin + soc_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (soc_sdram_choose_cmd_request[5]) begin + soc_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (soc_sdram_choose_cmd_request[6]) begin + soc_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (soc_sdram_choose_cmd_request[7]) begin + soc_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (soc_sdram_choose_cmd_request[0]) begin + soc_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (soc_sdram_choose_cmd_request[1]) begin + soc_sdram_choose_cmd_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (soc_sdram_choose_cmd_request[4]) begin + soc_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (soc_sdram_choose_cmd_request[5]) begin + soc_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (soc_sdram_choose_cmd_request[6]) begin + soc_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (soc_sdram_choose_cmd_request[7]) begin + soc_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (soc_sdram_choose_cmd_request[0]) begin + soc_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (soc_sdram_choose_cmd_request[1]) begin + soc_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (soc_sdram_choose_cmd_request[2]) begin + soc_sdram_choose_cmd_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (soc_sdram_choose_cmd_request[5]) begin + soc_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (soc_sdram_choose_cmd_request[6]) begin + soc_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (soc_sdram_choose_cmd_request[7]) begin + soc_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (soc_sdram_choose_cmd_request[0]) begin + soc_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (soc_sdram_choose_cmd_request[1]) begin + soc_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (soc_sdram_choose_cmd_request[2]) begin + soc_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (soc_sdram_choose_cmd_request[3]) begin + soc_sdram_choose_cmd_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (soc_sdram_choose_cmd_request[6]) begin + soc_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (soc_sdram_choose_cmd_request[7]) begin + soc_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (soc_sdram_choose_cmd_request[0]) begin + soc_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (soc_sdram_choose_cmd_request[1]) begin + soc_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (soc_sdram_choose_cmd_request[2]) begin + soc_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (soc_sdram_choose_cmd_request[3]) begin + soc_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (soc_sdram_choose_cmd_request[4]) begin + soc_sdram_choose_cmd_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (soc_sdram_choose_cmd_request[7]) begin + soc_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (soc_sdram_choose_cmd_request[0]) begin + soc_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (soc_sdram_choose_cmd_request[1]) begin + soc_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (soc_sdram_choose_cmd_request[2]) begin + soc_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (soc_sdram_choose_cmd_request[3]) begin + soc_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (soc_sdram_choose_cmd_request[4]) begin + soc_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (soc_sdram_choose_cmd_request[5]) begin + soc_sdram_choose_cmd_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (soc_sdram_choose_cmd_request[0]) begin + soc_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (soc_sdram_choose_cmd_request[1]) begin + soc_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (soc_sdram_choose_cmd_request[2]) begin + soc_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (soc_sdram_choose_cmd_request[3]) begin + soc_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (soc_sdram_choose_cmd_request[4]) begin + soc_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (soc_sdram_choose_cmd_request[5]) begin + soc_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (soc_sdram_choose_cmd_request[6]) begin + soc_sdram_choose_cmd_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + if (soc_sdram_choose_req_ce) begin + case (soc_sdram_choose_req_grant) + 1'd0: begin + if (soc_sdram_choose_req_request[1]) begin + soc_sdram_choose_req_grant <= 1'd1; + end else begin + if (soc_sdram_choose_req_request[2]) begin + soc_sdram_choose_req_grant <= 2'd2; + end else begin + if (soc_sdram_choose_req_request[3]) begin + soc_sdram_choose_req_grant <= 2'd3; + end else begin + if (soc_sdram_choose_req_request[4]) begin + soc_sdram_choose_req_grant <= 3'd4; + end else begin + if (soc_sdram_choose_req_request[5]) begin + soc_sdram_choose_req_grant <= 3'd5; + end else begin + if (soc_sdram_choose_req_request[6]) begin + soc_sdram_choose_req_grant <= 3'd6; + end else begin + if (soc_sdram_choose_req_request[7]) begin + soc_sdram_choose_req_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (soc_sdram_choose_req_request[2]) begin + soc_sdram_choose_req_grant <= 2'd2; + end else begin + if (soc_sdram_choose_req_request[3]) begin + soc_sdram_choose_req_grant <= 2'd3; + end else begin + if (soc_sdram_choose_req_request[4]) begin + soc_sdram_choose_req_grant <= 3'd4; + end else begin + if (soc_sdram_choose_req_request[5]) begin + soc_sdram_choose_req_grant <= 3'd5; + end else begin + if (soc_sdram_choose_req_request[6]) begin + soc_sdram_choose_req_grant <= 3'd6; + end else begin + if (soc_sdram_choose_req_request[7]) begin + soc_sdram_choose_req_grant <= 3'd7; + end else begin + if (soc_sdram_choose_req_request[0]) begin + soc_sdram_choose_req_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (soc_sdram_choose_req_request[3]) begin + soc_sdram_choose_req_grant <= 2'd3; + end else begin + if (soc_sdram_choose_req_request[4]) begin + soc_sdram_choose_req_grant <= 3'd4; + end else begin + if (soc_sdram_choose_req_request[5]) begin + soc_sdram_choose_req_grant <= 3'd5; + end else begin + if (soc_sdram_choose_req_request[6]) begin + soc_sdram_choose_req_grant <= 3'd6; + end else begin + if (soc_sdram_choose_req_request[7]) begin + soc_sdram_choose_req_grant <= 3'd7; + end else begin + if (soc_sdram_choose_req_request[0]) begin + soc_sdram_choose_req_grant <= 1'd0; + end else begin + if (soc_sdram_choose_req_request[1]) begin + soc_sdram_choose_req_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (soc_sdram_choose_req_request[4]) begin + soc_sdram_choose_req_grant <= 3'd4; + end else begin + if (soc_sdram_choose_req_request[5]) begin + soc_sdram_choose_req_grant <= 3'd5; + end else begin + if (soc_sdram_choose_req_request[6]) begin + soc_sdram_choose_req_grant <= 3'd6; + end else begin + if (soc_sdram_choose_req_request[7]) begin + soc_sdram_choose_req_grant <= 3'd7; + end else begin + if (soc_sdram_choose_req_request[0]) begin + soc_sdram_choose_req_grant <= 1'd0; + end else begin + if (soc_sdram_choose_req_request[1]) begin + soc_sdram_choose_req_grant <= 1'd1; + end else begin + if (soc_sdram_choose_req_request[2]) begin + soc_sdram_choose_req_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (soc_sdram_choose_req_request[5]) begin + soc_sdram_choose_req_grant <= 3'd5; + end else begin + if (soc_sdram_choose_req_request[6]) begin + soc_sdram_choose_req_grant <= 3'd6; + end else begin + if (soc_sdram_choose_req_request[7]) begin + soc_sdram_choose_req_grant <= 3'd7; + end else begin + if (soc_sdram_choose_req_request[0]) begin + soc_sdram_choose_req_grant <= 1'd0; + end else begin + if (soc_sdram_choose_req_request[1]) begin + soc_sdram_choose_req_grant <= 1'd1; + end else begin + if (soc_sdram_choose_req_request[2]) begin + soc_sdram_choose_req_grant <= 2'd2; + end else begin + if (soc_sdram_choose_req_request[3]) begin + soc_sdram_choose_req_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (soc_sdram_choose_req_request[6]) begin + soc_sdram_choose_req_grant <= 3'd6; + end else begin + if (soc_sdram_choose_req_request[7]) begin + soc_sdram_choose_req_grant <= 3'd7; + end else begin + if (soc_sdram_choose_req_request[0]) begin + soc_sdram_choose_req_grant <= 1'd0; + end else begin + if (soc_sdram_choose_req_request[1]) begin + soc_sdram_choose_req_grant <= 1'd1; + end else begin + if (soc_sdram_choose_req_request[2]) begin + soc_sdram_choose_req_grant <= 2'd2; + end else begin + if (soc_sdram_choose_req_request[3]) begin + soc_sdram_choose_req_grant <= 2'd3; + end else begin + if (soc_sdram_choose_req_request[4]) begin + soc_sdram_choose_req_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (soc_sdram_choose_req_request[7]) begin + soc_sdram_choose_req_grant <= 3'd7; + end else begin + if (soc_sdram_choose_req_request[0]) begin + soc_sdram_choose_req_grant <= 1'd0; + end else begin + if (soc_sdram_choose_req_request[1]) begin + soc_sdram_choose_req_grant <= 1'd1; + end else begin + if (soc_sdram_choose_req_request[2]) begin + soc_sdram_choose_req_grant <= 2'd2; + end else begin + if (soc_sdram_choose_req_request[3]) begin + soc_sdram_choose_req_grant <= 2'd3; + end else begin + if (soc_sdram_choose_req_request[4]) begin + soc_sdram_choose_req_grant <= 3'd4; + end else begin + if (soc_sdram_choose_req_request[5]) begin + soc_sdram_choose_req_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (soc_sdram_choose_req_request[0]) begin + soc_sdram_choose_req_grant <= 1'd0; + end else begin + if (soc_sdram_choose_req_request[1]) begin + soc_sdram_choose_req_grant <= 1'd1; + end else begin + if (soc_sdram_choose_req_request[2]) begin + soc_sdram_choose_req_grant <= 2'd2; + end else begin + if (soc_sdram_choose_req_request[3]) begin + soc_sdram_choose_req_grant <= 2'd3; + end else begin + if (soc_sdram_choose_req_request[4]) begin + soc_sdram_choose_req_grant <= 3'd4; + end else begin + if (soc_sdram_choose_req_request[5]) begin + soc_sdram_choose_req_grant <= 3'd5; + end else begin + if (soc_sdram_choose_req_request[6]) begin + soc_sdram_choose_req_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + soc_sdram_dfi_p0_cs_n <= 1'd0; + soc_sdram_dfi_p0_bank <= vns_array_muxed0; + soc_sdram_dfi_p0_address <= vns_array_muxed1; + soc_sdram_dfi_p0_cas_n <= (~vns_array_muxed2); + soc_sdram_dfi_p0_ras_n <= (~vns_array_muxed3); + soc_sdram_dfi_p0_we_n <= (~vns_array_muxed4); + soc_sdram_dfi_p0_rddata_en <= vns_array_muxed5; + soc_sdram_dfi_p0_wrdata_en <= vns_array_muxed6; + soc_sdram_dfi_p1_cs_n <= 1'd0; + soc_sdram_dfi_p1_bank <= vns_array_muxed7; + soc_sdram_dfi_p1_address <= vns_array_muxed8; + soc_sdram_dfi_p1_cas_n <= (~vns_array_muxed9); + soc_sdram_dfi_p1_ras_n <= (~vns_array_muxed10); + soc_sdram_dfi_p1_we_n <= (~vns_array_muxed11); + soc_sdram_dfi_p1_rddata_en <= vns_array_muxed12; + soc_sdram_dfi_p1_wrdata_en <= vns_array_muxed13; + soc_sdram_dfi_p2_cs_n <= 1'd0; + soc_sdram_dfi_p2_bank <= vns_array_muxed14; + soc_sdram_dfi_p2_address <= vns_array_muxed15; + soc_sdram_dfi_p2_cas_n <= (~vns_array_muxed16); + soc_sdram_dfi_p2_ras_n <= (~vns_array_muxed17); + soc_sdram_dfi_p2_we_n <= (~vns_array_muxed18); + soc_sdram_dfi_p2_rddata_en <= vns_array_muxed19; + soc_sdram_dfi_p2_wrdata_en <= vns_array_muxed20; + soc_sdram_dfi_p3_cs_n <= 1'd0; + soc_sdram_dfi_p3_bank <= vns_array_muxed21; + soc_sdram_dfi_p3_address <= vns_array_muxed22; + soc_sdram_dfi_p3_cas_n <= (~vns_array_muxed23); + soc_sdram_dfi_p3_ras_n <= (~vns_array_muxed24); + soc_sdram_dfi_p3_we_n <= (~vns_array_muxed25); + soc_sdram_dfi_p3_rddata_en <= vns_array_muxed26; + soc_sdram_dfi_p3_wrdata_en <= vns_array_muxed27; + if (soc_sdram_trrdcon_valid) begin + soc_sdram_trrdcon_count <= 1'd1; + if (1'd0) begin + soc_sdram_trrdcon_ready <= 1'd1; + end else begin + soc_sdram_trrdcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_trrdcon_ready)) begin + soc_sdram_trrdcon_count <= (soc_sdram_trrdcon_count - 1'd1); + if ((soc_sdram_trrdcon_count == 1'd1)) begin + soc_sdram_trrdcon_ready <= 1'd1; + end + end + end + soc_sdram_tfawcon_window <= {soc_sdram_tfawcon_window, soc_sdram_tfawcon_valid}; + if ((soc_sdram_tfawcon_count < 3'd4)) begin + if ((soc_sdram_tfawcon_count == 2'd3)) begin + soc_sdram_tfawcon_ready <= (~soc_sdram_tfawcon_valid); + end else begin + soc_sdram_tfawcon_ready <= 1'd1; + end + end + if (soc_sdram_tccdcon_valid) begin + soc_sdram_tccdcon_count <= 1'd0; + if (1'd1) begin + soc_sdram_tccdcon_ready <= 1'd1; + end else begin + soc_sdram_tccdcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_tccdcon_ready)) begin + soc_sdram_tccdcon_count <= (soc_sdram_tccdcon_count - 1'd1); + if ((soc_sdram_tccdcon_count == 1'd1)) begin + soc_sdram_tccdcon_ready <= 1'd1; + end + end + end + if (soc_sdram_twtrcon_valid) begin + soc_sdram_twtrcon_count <= 3'd4; + if (1'd0) begin + soc_sdram_twtrcon_ready <= 1'd1; + end else begin + soc_sdram_twtrcon_ready <= 1'd0; + end + end else begin + if ((~soc_sdram_twtrcon_ready)) begin + soc_sdram_twtrcon_count <= (soc_sdram_twtrcon_count - 1'd1); + if ((soc_sdram_twtrcon_count == 1'd1)) begin + soc_sdram_twtrcon_ready <= 1'd1; + end + end + end + vns_multiplexer_state <= vns_multiplexer_next_state; + vns_new_master_wdata_ready0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_sdram_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd0) & soc_sdram_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd0) & soc_sdram_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd0) & soc_sdram_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd0) & soc_sdram_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd0) & soc_sdram_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd0) & soc_sdram_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd0) & soc_sdram_interface_bank7_wdata_ready)); + vns_new_master_wdata_ready1 <= vns_new_master_wdata_ready0; + vns_new_master_wdata_ready2 <= vns_new_master_wdata_ready1; + vns_new_master_wdata_ready3 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd1) & soc_sdram_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd1) & soc_sdram_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd1) & soc_sdram_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd1) & soc_sdram_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd1) & soc_sdram_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd1) & soc_sdram_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd1) & soc_sdram_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd1) & soc_sdram_interface_bank7_wdata_ready)); + vns_new_master_wdata_ready4 <= vns_new_master_wdata_ready3; + vns_new_master_wdata_ready5 <= vns_new_master_wdata_ready4; + vns_new_master_rdata_valid0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_sdram_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd0) & soc_sdram_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd0) & soc_sdram_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd0) & soc_sdram_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd0) & soc_sdram_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd0) & soc_sdram_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd0) & soc_sdram_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd0) & soc_sdram_interface_bank7_rdata_valid)); + vns_new_master_rdata_valid1 <= vns_new_master_rdata_valid0; + vns_new_master_rdata_valid2 <= vns_new_master_rdata_valid1; + vns_new_master_rdata_valid3 <= vns_new_master_rdata_valid2; + vns_new_master_rdata_valid4 <= vns_new_master_rdata_valid3; + vns_new_master_rdata_valid5 <= vns_new_master_rdata_valid4; + vns_new_master_rdata_valid6 <= vns_new_master_rdata_valid5; + vns_new_master_rdata_valid7 <= vns_new_master_rdata_valid6; + vns_new_master_rdata_valid8 <= vns_new_master_rdata_valid7; + vns_new_master_rdata_valid9 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd1) & soc_sdram_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd1) & soc_sdram_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd1) & soc_sdram_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd1) & soc_sdram_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd1) & soc_sdram_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd1) & soc_sdram_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd1) & soc_sdram_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd1) & soc_sdram_interface_bank7_rdata_valid)); + vns_new_master_rdata_valid10 <= vns_new_master_rdata_valid9; + vns_new_master_rdata_valid11 <= vns_new_master_rdata_valid10; + vns_new_master_rdata_valid12 <= vns_new_master_rdata_valid11; + vns_new_master_rdata_valid13 <= vns_new_master_rdata_valid12; + vns_new_master_rdata_valid14 <= vns_new_master_rdata_valid13; + vns_new_master_rdata_valid15 <= vns_new_master_rdata_valid14; + vns_new_master_rdata_valid16 <= vns_new_master_rdata_valid15; + vns_new_master_rdata_valid17 <= vns_new_master_rdata_valid16; + if (vns_roundrobin0_ce) begin + case (vns_roundrobin0_grant) + 1'd0: begin + if (vns_roundrobin0_request[1]) begin + vns_roundrobin0_grant <= 1'd1; + end + end + 1'd1: begin + if (vns_roundrobin0_request[0]) begin + vns_roundrobin0_grant <= 1'd0; + end + end + endcase + end + if (vns_roundrobin1_ce) begin + case (vns_roundrobin1_grant) + 1'd0: begin + if (vns_roundrobin1_request[1]) begin + vns_roundrobin1_grant <= 1'd1; + end + end + 1'd1: begin + if (vns_roundrobin1_request[0]) begin + vns_roundrobin1_grant <= 1'd0; + end + end + endcase + end + if (vns_roundrobin2_ce) begin + case (vns_roundrobin2_grant) + 1'd0: begin + if (vns_roundrobin2_request[1]) begin + vns_roundrobin2_grant <= 1'd1; + end + end + 1'd1: begin + if (vns_roundrobin2_request[0]) begin + vns_roundrobin2_grant <= 1'd0; + end + end + endcase + end + if (vns_roundrobin3_ce) begin + case (vns_roundrobin3_grant) + 1'd0: begin + if (vns_roundrobin3_request[1]) begin + vns_roundrobin3_grant <= 1'd1; + end + end + 1'd1: begin + if (vns_roundrobin3_request[0]) begin + vns_roundrobin3_grant <= 1'd0; + end + end + endcase + end + if (vns_roundrobin4_ce) begin + case (vns_roundrobin4_grant) + 1'd0: begin + if (vns_roundrobin4_request[1]) begin + vns_roundrobin4_grant <= 1'd1; + end + end + 1'd1: begin + if (vns_roundrobin4_request[0]) begin + vns_roundrobin4_grant <= 1'd0; + end + end + endcase + end + if (vns_roundrobin5_ce) begin + case (vns_roundrobin5_grant) + 1'd0: begin + if (vns_roundrobin5_request[1]) begin + vns_roundrobin5_grant <= 1'd1; + end + end + 1'd1: begin + if (vns_roundrobin5_request[0]) begin + vns_roundrobin5_grant <= 1'd0; + end + end + endcase + end + if (vns_roundrobin6_ce) begin + case (vns_roundrobin6_grant) + 1'd0: begin + if (vns_roundrobin6_request[1]) begin + vns_roundrobin6_grant <= 1'd1; + end + end + 1'd1: begin + if (vns_roundrobin6_request[0]) begin + vns_roundrobin6_grant <= 1'd0; + end + end + endcase + end + if (vns_roundrobin7_ce) begin + case (vns_roundrobin7_grant) + 1'd0: begin + if (vns_roundrobin7_request[1]) begin + vns_roundrobin7_grant <= 1'd1; + end + end + 1'd1: begin + if (vns_roundrobin7_request[0]) begin + vns_roundrobin7_grant <= 1'd0; + end + end + endcase + end + if (soc_counter_reset) begin + soc_counter <= 1'd0; + end else begin + if (soc_counter_ce) begin + soc_counter <= (soc_counter + 1'd1); + end + end + if (soc_address_ce) begin + soc_address_q <= soc_address_d; + end + if (soc_address_reset) begin + soc_address_q <= 30'd0; + end + if (soc_need_refill_ce) begin + soc_need_refill_q <= soc_need_refill_d; + end + if (soc_need_refill_reset) begin + soc_need_refill_q <= 1'd1; + end + vns_converter_state <= vns_converter_next_state; + if (soc_cached_datas_ce0) begin + soc_cached_datas_flipflop0_q <= soc_cached_datas_flipflop0_d; + end + if (soc_cached_datas_reset0) begin + soc_cached_datas_flipflop0_q <= 32'd0; + end + if (soc_cached_datas_ce1) begin + soc_cached_datas_flipflop1_q <= soc_cached_datas_flipflop1_d; + end + if (soc_cached_datas_reset1) begin + soc_cached_datas_flipflop1_q <= 32'd0; + end + if (soc_cached_datas_ce2) begin + soc_cached_datas_flipflop2_q <= soc_cached_datas_flipflop2_d; + end + if (soc_cached_datas_reset2) begin + soc_cached_datas_flipflop2_q <= 32'd0; + end + if (soc_cached_datas_ce3) begin + soc_cached_datas_flipflop3_q <= soc_cached_datas_flipflop3_d; + end + if (soc_cached_datas_reset3) begin + soc_cached_datas_flipflop3_q <= 32'd0; + end + if (soc_cached_sels_ce0) begin + soc_cached_sels_flipflop0_q <= soc_cached_sels_flipflop0_d; + end + if (soc_cached_sels_reset0) begin + soc_cached_sels_flipflop0_q <= 4'd0; + end + if (soc_cached_sels_ce1) begin + soc_cached_sels_flipflop1_q <= soc_cached_sels_flipflop1_d; + end + if (soc_cached_sels_reset1) begin + soc_cached_sels_flipflop1_q <= 4'd0; + end + if (soc_cached_sels_ce2) begin + soc_cached_sels_flipflop2_q <= soc_cached_sels_flipflop2_d; + end + if (soc_cached_sels_reset2) begin + soc_cached_sels_flipflop2_q <= 4'd0; + end + if (soc_cached_sels_ce3) begin + soc_cached_sels_flipflop3_q <= soc_cached_sels_flipflop3_d; + end + if (soc_cached_sels_reset3) begin + soc_cached_sels_flipflop3_q <= 4'd0; + end + vns_litedramwishbone2native_state <= vns_litedramwishbone2native_next_state; + if (soc_count_next_value_ce) begin + soc_count <= soc_count_next_value; + end + case (vns_grant) + 1'd0: begin + if ((~vns_request[0])) begin + if (vns_request[1]) begin + vns_grant <= 1'd1; + end + end + end + 1'd1: begin + if ((~vns_request[1])) begin + if (vns_request[0]) begin + vns_grant <= 1'd0; + end + end + end + endcase + vns_slave_sel_r <= vns_slave_sel; + if (vns_wait) begin + if ((~vns_done)) begin + vns_count <= (vns_count - 1'd1); + end + end else begin + vns_count <= 20'd1000000; + end + vns_interface0_bank_bus_dat_r <= 1'd0; + if (vns_csrbank0_sel) begin + case (vns_interface0_bank_bus_adr[3:0]) + 1'd0: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_reset0_w; + end + 1'd1: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch3_w; + end + 2'd2: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch2_w; + end + 2'd3: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch1_w; + end + 3'd4: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch0_w; + end + 3'd5: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors3_w; + end + 3'd6: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors2_w; + end + 3'd7: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors1_w; + end + 4'd8: begin + vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors0_w; + end + endcase + end + if (vns_csrbank0_reset0_re) begin + soc_litedramcore_soccontroller_reset_storage <= vns_csrbank0_reset0_r; + end + soc_litedramcore_soccontroller_reset_re <= vns_csrbank0_reset0_re; + if (vns_csrbank0_scratch3_re) begin + soc_litedramcore_soccontroller_scratch_storage[31:24] <= vns_csrbank0_scratch3_r; + end + if (vns_csrbank0_scratch2_re) begin + soc_litedramcore_soccontroller_scratch_storage[23:16] <= vns_csrbank0_scratch2_r; + end + if (vns_csrbank0_scratch1_re) begin + soc_litedramcore_soccontroller_scratch_storage[15:8] <= vns_csrbank0_scratch1_r; + end + if (vns_csrbank0_scratch0_re) begin + soc_litedramcore_soccontroller_scratch_storage[7:0] <= vns_csrbank0_scratch0_r; + end + soc_litedramcore_soccontroller_scratch_re <= vns_csrbank0_scratch0_re; + vns_interface1_bank_bus_dat_r <= 1'd0; + if (vns_csrbank1_sel) begin + case (vns_interface1_bank_bus_adr[0]) + 1'd0: begin + vns_interface1_bank_bus_dat_r <= vns_csrbank1_init_done0_w; + end + 1'd1: begin + vns_interface1_bank_bus_dat_r <= vns_csrbank1_init_error0_w; + end + endcase + end + if (vns_csrbank1_init_done0_re) begin + soc_init_done_storage <= vns_csrbank1_init_done0_r; + end + soc_init_done_re <= vns_csrbank1_init_done0_re; + if (vns_csrbank1_init_error0_re) begin + soc_init_error_storage <= vns_csrbank1_init_error0_r; + end + soc_init_error_re <= vns_csrbank1_init_error0_re; + vns_interface2_bank_bus_dat_r <= 1'd0; + if (vns_csrbank2_sel) begin + case (vns_interface2_bank_bus_adr[3:0]) + 1'd0: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_half_sys8x_taps0_w; + end + 1'd1: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_wlevel_en0_w; + end + 2'd2: begin + vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_wlevel_strobe_w; + end + 2'd3: begin + vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_cdly_rst_w; + end + 3'd4: begin + vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_cdly_inc_w; + end + 3'd5: begin + vns_interface2_bank_bus_dat_r <= vns_csrbank2_dly_sel0_w; + end + 3'd6: begin + vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_rst_w; + end + 3'd7: begin + vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_inc_w; + end + 4'd8: begin + vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_rst_w; + end + 4'd9: begin + vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_w; + end + endcase + end + if (vns_csrbank2_half_sys8x_taps0_re) begin + soc_a7ddrphy_half_sys8x_taps_storage[4:0] <= vns_csrbank2_half_sys8x_taps0_r; + end + soc_a7ddrphy_half_sys8x_taps_re <= vns_csrbank2_half_sys8x_taps0_re; + if (vns_csrbank2_wlevel_en0_re) begin + soc_a7ddrphy_wlevel_en_storage <= vns_csrbank2_wlevel_en0_r; + end + soc_a7ddrphy_wlevel_en_re <= vns_csrbank2_wlevel_en0_re; + if (vns_csrbank2_dly_sel0_re) begin + soc_a7ddrphy_dly_sel_storage[1:0] <= vns_csrbank2_dly_sel0_r; + end + soc_a7ddrphy_dly_sel_re <= vns_csrbank2_dly_sel0_re; + vns_interface3_bank_bus_dat_r <= 1'd0; + if (vns_csrbank3_sel) begin + case (vns_interface3_bank_bus_adr[5:0]) + 1'd0: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_control0_w; + end + 1'd1: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_command0_w; + end + 2'd2: begin + vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector0_command_issue_w; + end + 2'd3: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_address1_w; + end + 3'd4: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_address0_w; + end + 3'd5: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_baddress0_w; + end + 3'd6: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata3_w; + end + 3'd7: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata2_w; + end + 4'd8: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata1_w; + end + 4'd9: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata0_w; + end + 4'd10: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata3_w; + end + 4'd11: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata2_w; + end + 4'd12: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata1_w; + end + 4'd13: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata0_w; + end + 4'd14: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_command0_w; + end + 4'd15: begin + vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector1_command_issue_w; + end + 5'd16: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_address1_w; + end + 5'd17: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_address0_w; + end + 5'd18: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_baddress0_w; + end + 5'd19: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata3_w; + end + 5'd20: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata2_w; + end + 5'd21: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata1_w; + end + 5'd22: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata0_w; + end + 5'd23: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata3_w; + end + 5'd24: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata2_w; + end + 5'd25: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata1_w; + end + 5'd26: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata0_w; + end + 5'd27: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_command0_w; + end + 5'd28: begin + vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector2_command_issue_w; + end + 5'd29: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_address1_w; + end + 5'd30: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_address0_w; + end + 5'd31: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_baddress0_w; + end + 6'd32: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata3_w; + end + 6'd33: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata2_w; + end + 6'd34: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata1_w; + end + 6'd35: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata0_w; + end + 6'd36: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata3_w; + end + 6'd37: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata2_w; + end + 6'd38: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata1_w; + end + 6'd39: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata0_w; + end + 6'd40: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_command0_w; + end + 6'd41: begin + vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector3_command_issue_w; + end + 6'd42: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_address1_w; + end + 6'd43: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_address0_w; + end + 6'd44: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_baddress0_w; + end + 6'd45: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata3_w; + end + 6'd46: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata2_w; + end + 6'd47: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata1_w; + end + 6'd48: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata0_w; + end + 6'd49: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata3_w; + end + 6'd50: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata2_w; + end + 6'd51: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata1_w; + end + 6'd52: begin + vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata0_w; + end + endcase + end + if (vns_csrbank3_dfii_control0_re) begin + soc_sdram_storage[3:0] <= vns_csrbank3_dfii_control0_r; + end + soc_sdram_re <= vns_csrbank3_dfii_control0_re; + if (vns_csrbank3_dfii_pi0_command0_re) begin + soc_sdram_phaseinjector0_command_storage[5:0] <= vns_csrbank3_dfii_pi0_command0_r; + end + soc_sdram_phaseinjector0_command_re <= vns_csrbank3_dfii_pi0_command0_re; + if (vns_csrbank3_dfii_pi0_address1_re) begin + soc_sdram_phaseinjector0_address_storage[14:8] <= vns_csrbank3_dfii_pi0_address1_r; + end + if (vns_csrbank3_dfii_pi0_address0_re) begin + soc_sdram_phaseinjector0_address_storage[7:0] <= vns_csrbank3_dfii_pi0_address0_r; + end + soc_sdram_phaseinjector0_address_re <= vns_csrbank3_dfii_pi0_address0_re; + if (vns_csrbank3_dfii_pi0_baddress0_re) begin + soc_sdram_phaseinjector0_baddress_storage[2:0] <= vns_csrbank3_dfii_pi0_baddress0_r; + end + soc_sdram_phaseinjector0_baddress_re <= vns_csrbank3_dfii_pi0_baddress0_re; + if (vns_csrbank3_dfii_pi0_wrdata3_re) begin + soc_sdram_phaseinjector0_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi0_wrdata3_r; + end + if (vns_csrbank3_dfii_pi0_wrdata2_re) begin + soc_sdram_phaseinjector0_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi0_wrdata2_r; + end + if (vns_csrbank3_dfii_pi0_wrdata1_re) begin + soc_sdram_phaseinjector0_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi0_wrdata1_r; + end + if (vns_csrbank3_dfii_pi0_wrdata0_re) begin + soc_sdram_phaseinjector0_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi0_wrdata0_r; + end + soc_sdram_phaseinjector0_wrdata_re <= vns_csrbank3_dfii_pi0_wrdata0_re; + if (vns_csrbank3_dfii_pi1_command0_re) begin + soc_sdram_phaseinjector1_command_storage[5:0] <= vns_csrbank3_dfii_pi1_command0_r; + end + soc_sdram_phaseinjector1_command_re <= vns_csrbank3_dfii_pi1_command0_re; + if (vns_csrbank3_dfii_pi1_address1_re) begin + soc_sdram_phaseinjector1_address_storage[14:8] <= vns_csrbank3_dfii_pi1_address1_r; + end + if (vns_csrbank3_dfii_pi1_address0_re) begin + soc_sdram_phaseinjector1_address_storage[7:0] <= vns_csrbank3_dfii_pi1_address0_r; + end + soc_sdram_phaseinjector1_address_re <= vns_csrbank3_dfii_pi1_address0_re; + if (vns_csrbank3_dfii_pi1_baddress0_re) begin + soc_sdram_phaseinjector1_baddress_storage[2:0] <= vns_csrbank3_dfii_pi1_baddress0_r; + end + soc_sdram_phaseinjector1_baddress_re <= vns_csrbank3_dfii_pi1_baddress0_re; + if (vns_csrbank3_dfii_pi1_wrdata3_re) begin + soc_sdram_phaseinjector1_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi1_wrdata3_r; + end + if (vns_csrbank3_dfii_pi1_wrdata2_re) begin + soc_sdram_phaseinjector1_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi1_wrdata2_r; + end + if (vns_csrbank3_dfii_pi1_wrdata1_re) begin + soc_sdram_phaseinjector1_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi1_wrdata1_r; + end + if (vns_csrbank3_dfii_pi1_wrdata0_re) begin + soc_sdram_phaseinjector1_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi1_wrdata0_r; + end + soc_sdram_phaseinjector1_wrdata_re <= vns_csrbank3_dfii_pi1_wrdata0_re; + if (vns_csrbank3_dfii_pi2_command0_re) begin + soc_sdram_phaseinjector2_command_storage[5:0] <= vns_csrbank3_dfii_pi2_command0_r; + end + soc_sdram_phaseinjector2_command_re <= vns_csrbank3_dfii_pi2_command0_re; + if (vns_csrbank3_dfii_pi2_address1_re) begin + soc_sdram_phaseinjector2_address_storage[14:8] <= vns_csrbank3_dfii_pi2_address1_r; + end + if (vns_csrbank3_dfii_pi2_address0_re) begin + soc_sdram_phaseinjector2_address_storage[7:0] <= vns_csrbank3_dfii_pi2_address0_r; + end + soc_sdram_phaseinjector2_address_re <= vns_csrbank3_dfii_pi2_address0_re; + if (vns_csrbank3_dfii_pi2_baddress0_re) begin + soc_sdram_phaseinjector2_baddress_storage[2:0] <= vns_csrbank3_dfii_pi2_baddress0_r; + end + soc_sdram_phaseinjector2_baddress_re <= vns_csrbank3_dfii_pi2_baddress0_re; + if (vns_csrbank3_dfii_pi2_wrdata3_re) begin + soc_sdram_phaseinjector2_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi2_wrdata3_r; + end + if (vns_csrbank3_dfii_pi2_wrdata2_re) begin + soc_sdram_phaseinjector2_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi2_wrdata2_r; + end + if (vns_csrbank3_dfii_pi2_wrdata1_re) begin + soc_sdram_phaseinjector2_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi2_wrdata1_r; + end + if (vns_csrbank3_dfii_pi2_wrdata0_re) begin + soc_sdram_phaseinjector2_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi2_wrdata0_r; + end + soc_sdram_phaseinjector2_wrdata_re <= vns_csrbank3_dfii_pi2_wrdata0_re; + if (vns_csrbank3_dfii_pi3_command0_re) begin + soc_sdram_phaseinjector3_command_storage[5:0] <= vns_csrbank3_dfii_pi3_command0_r; + end + soc_sdram_phaseinjector3_command_re <= vns_csrbank3_dfii_pi3_command0_re; + if (vns_csrbank3_dfii_pi3_address1_re) begin + soc_sdram_phaseinjector3_address_storage[14:8] <= vns_csrbank3_dfii_pi3_address1_r; + end + if (vns_csrbank3_dfii_pi3_address0_re) begin + soc_sdram_phaseinjector3_address_storage[7:0] <= vns_csrbank3_dfii_pi3_address0_r; + end + soc_sdram_phaseinjector3_address_re <= vns_csrbank3_dfii_pi3_address0_re; + if (vns_csrbank3_dfii_pi3_baddress0_re) begin + soc_sdram_phaseinjector3_baddress_storage[2:0] <= vns_csrbank3_dfii_pi3_baddress0_r; + end + soc_sdram_phaseinjector3_baddress_re <= vns_csrbank3_dfii_pi3_baddress0_re; + if (vns_csrbank3_dfii_pi3_wrdata3_re) begin + soc_sdram_phaseinjector3_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi3_wrdata3_r; + end + if (vns_csrbank3_dfii_pi3_wrdata2_re) begin + soc_sdram_phaseinjector3_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi3_wrdata2_r; + end + if (vns_csrbank3_dfii_pi3_wrdata1_re) begin + soc_sdram_phaseinjector3_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi3_wrdata1_r; + end + if (vns_csrbank3_dfii_pi3_wrdata0_re) begin + soc_sdram_phaseinjector3_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi3_wrdata0_r; + end + soc_sdram_phaseinjector3_wrdata_re <= vns_csrbank3_dfii_pi3_wrdata0_re; + vns_interface4_bank_bus_dat_r <= 1'd0; + if (vns_csrbank4_sel) begin + case (vns_interface4_bank_bus_adr[4:0]) + 1'd0: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_load3_w; + end + 1'd1: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_load2_w; + end + 2'd2: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_load1_w; + end + 2'd3: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_load0_w; + end + 3'd4: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload3_w; + end + 3'd5: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload2_w; + end + 3'd6: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload1_w; + end + 3'd7: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload0_w; + end + 4'd8: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_en0_w; + end + 4'd9: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_update_value0_w; + end + 4'd10: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_value3_w; + end + 4'd11: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_value2_w; + end + 4'd12: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_value1_w; + end + 4'd13: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_value0_w; + end + 4'd14: begin + vns_interface4_bank_bus_dat_r <= soc_litedramcore_timer_eventmanager_status_w; + end + 4'd15: begin + vns_interface4_bank_bus_dat_r <= soc_litedramcore_timer_eventmanager_pending_w; + end + 5'd16: begin + vns_interface4_bank_bus_dat_r <= vns_csrbank4_ev_enable0_w; + end + endcase + end + if (vns_csrbank4_load3_re) begin + soc_litedramcore_timer_load_storage[31:24] <= vns_csrbank4_load3_r; + end + if (vns_csrbank4_load2_re) begin + soc_litedramcore_timer_load_storage[23:16] <= vns_csrbank4_load2_r; + end + if (vns_csrbank4_load1_re) begin + soc_litedramcore_timer_load_storage[15:8] <= vns_csrbank4_load1_r; + end + if (vns_csrbank4_load0_re) begin + soc_litedramcore_timer_load_storage[7:0] <= vns_csrbank4_load0_r; + end + soc_litedramcore_timer_load_re <= vns_csrbank4_load0_re; + if (vns_csrbank4_reload3_re) begin + soc_litedramcore_timer_reload_storage[31:24] <= vns_csrbank4_reload3_r; + end + if (vns_csrbank4_reload2_re) begin + soc_litedramcore_timer_reload_storage[23:16] <= vns_csrbank4_reload2_r; + end + if (vns_csrbank4_reload1_re) begin + soc_litedramcore_timer_reload_storage[15:8] <= vns_csrbank4_reload1_r; + end + if (vns_csrbank4_reload0_re) begin + soc_litedramcore_timer_reload_storage[7:0] <= vns_csrbank4_reload0_r; + end + soc_litedramcore_timer_reload_re <= vns_csrbank4_reload0_re; + if (vns_csrbank4_en0_re) begin + soc_litedramcore_timer_en_storage <= vns_csrbank4_en0_r; + end + soc_litedramcore_timer_en_re <= vns_csrbank4_en0_re; + if (vns_csrbank4_update_value0_re) begin + soc_litedramcore_timer_update_value_storage <= vns_csrbank4_update_value0_r; + end + soc_litedramcore_timer_update_value_re <= vns_csrbank4_update_value0_re; + if (vns_csrbank4_ev_enable0_re) begin + soc_litedramcore_timer_eventmanager_storage <= vns_csrbank4_ev_enable0_r; + end + soc_litedramcore_timer_eventmanager_re <= vns_csrbank4_ev_enable0_re; + vns_interface5_bank_bus_dat_r <= 1'd0; + if (vns_csrbank5_sel) begin + case (vns_interface5_bank_bus_adr[2:0]) + 1'd0: begin + vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_rxtx_w; + end + 1'd1: begin + vns_interface5_bank_bus_dat_r <= vns_csrbank5_txfull_w; + end + 2'd2: begin + vns_interface5_bank_bus_dat_r <= vns_csrbank5_rxempty_w; + end + 2'd3: begin + vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_eventmanager_status_w; + end + 3'd4: begin + vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_eventmanager_pending_w; + end + 3'd5: begin + vns_interface5_bank_bus_dat_r <= vns_csrbank5_ev_enable0_w; + end + endcase + end + if (vns_csrbank5_ev_enable0_re) begin + soc_litedramcore_uart_eventmanager_storage[1:0] <= vns_csrbank5_ev_enable0_r; + end + soc_litedramcore_uart_eventmanager_re <= vns_csrbank5_ev_enable0_re; + vns_interface6_bank_bus_dat_r <= 1'd0; + if (vns_csrbank6_sel) begin + case (vns_interface6_bank_bus_adr[1:0]) + 1'd0: begin + vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word3_w; + end + 1'd1: begin + vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word2_w; + end + 2'd2: begin + vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word1_w; + end + 2'd3: begin + vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word0_w; + end + endcase + end + if (vns_csrbank6_tuning_word3_re) begin + soc_litedramcore_storage[31:24] <= vns_csrbank6_tuning_word3_r; + end + if (vns_csrbank6_tuning_word2_re) begin + soc_litedramcore_storage[23:16] <= vns_csrbank6_tuning_word2_r; + end + if (vns_csrbank6_tuning_word1_re) begin + soc_litedramcore_storage[15:8] <= vns_csrbank6_tuning_word1_r; + end + if (vns_csrbank6_tuning_word0_re) begin + soc_litedramcore_storage[7:0] <= vns_csrbank6_tuning_word0_r; + end + soc_litedramcore_re <= vns_csrbank6_tuning_word0_re; + if (sys_rst) begin + soc_litedramcore_soccontroller_reset_storage <= 1'd0; + soc_litedramcore_soccontroller_reset_re <= 1'd0; + soc_litedramcore_soccontroller_scratch_storage <= 32'd305419896; + soc_litedramcore_soccontroller_scratch_re <= 1'd0; + soc_litedramcore_soccontroller_bus_errors <= 32'd0; + soc_litedramcore_litedramcore_ram_bus_ack <= 1'd0; + soc_litedramcore_ram_bus_ram_bus_ack <= 1'd0; + serial_tx <= 1'd1; + soc_litedramcore_storage <= 32'd4947802; + soc_litedramcore_re <= 1'd0; + soc_litedramcore_sink_ready <= 1'd0; + soc_litedramcore_uart_clk_txen <= 1'd0; + soc_litedramcore_tx_busy <= 1'd0; + soc_litedramcore_source_valid <= 1'd0; + soc_litedramcore_uart_clk_rxen <= 1'd0; + soc_litedramcore_rx_r <= 1'd0; + soc_litedramcore_rx_busy <= 1'd0; + soc_litedramcore_uart_tx_pending <= 1'd0; + soc_litedramcore_uart_tx_old_trigger <= 1'd0; + soc_litedramcore_uart_rx_pending <= 1'd0; + soc_litedramcore_uart_rx_old_trigger <= 1'd0; + soc_litedramcore_uart_eventmanager_storage <= 2'd0; + soc_litedramcore_uart_eventmanager_re <= 1'd0; + soc_litedramcore_uart_tx_fifo_readable <= 1'd0; + soc_litedramcore_uart_tx_fifo_level0 <= 5'd0; + soc_litedramcore_uart_tx_fifo_produce <= 4'd0; + soc_litedramcore_uart_tx_fifo_consume <= 4'd0; + soc_litedramcore_uart_rx_fifo_readable <= 1'd0; + soc_litedramcore_uart_rx_fifo_level0 <= 5'd0; + soc_litedramcore_uart_rx_fifo_produce <= 4'd0; + soc_litedramcore_uart_rx_fifo_consume <= 4'd0; + soc_litedramcore_timer_load_storage <= 32'd0; + soc_litedramcore_timer_load_re <= 1'd0; + soc_litedramcore_timer_reload_storage <= 32'd0; + soc_litedramcore_timer_reload_re <= 1'd0; + soc_litedramcore_timer_en_storage <= 1'd0; + soc_litedramcore_timer_en_re <= 1'd0; + soc_litedramcore_timer_update_value_storage <= 1'd0; + soc_litedramcore_timer_update_value_re <= 1'd0; + soc_litedramcore_timer_value_status <= 32'd0; + soc_litedramcore_timer_zero_pending <= 1'd0; + soc_litedramcore_timer_zero_old_trigger <= 1'd0; + soc_litedramcore_timer_eventmanager_storage <= 1'd0; + soc_litedramcore_timer_eventmanager_re <= 1'd0; + soc_litedramcore_timer_value <= 32'd0; + soc_a7ddrphy_half_sys8x_taps_storage <= 5'd8; + soc_a7ddrphy_half_sys8x_taps_re <= 1'd0; + soc_a7ddrphy_wlevel_en_storage <= 1'd0; + soc_a7ddrphy_wlevel_en_re <= 1'd0; + soc_a7ddrphy_dly_sel_storage <= 2'd0; + soc_a7ddrphy_dly_sel_re <= 1'd0; + soc_a7ddrphy_dfi_p0_rddata_valid <= 1'd0; + soc_a7ddrphy_dfi_p1_rddata_valid <= 1'd0; + soc_a7ddrphy_dfi_p2_rddata_valid <= 1'd0; + soc_a7ddrphy_dfi_p3_rddata_valid <= 1'd0; + soc_a7ddrphy_dqs_oe_delayed <= 1'd0; + soc_a7ddrphy_dqspattern_o1 <= 8'd0; + soc_a7ddrphy_dq_oe_delayed <= 1'd0; + soc_a7ddrphy_bitslip0_value <= 3'd0; + soc_a7ddrphy_bitslip1_value <= 3'd0; + soc_a7ddrphy_bitslip2_value <= 3'd0; + soc_a7ddrphy_bitslip3_value <= 3'd0; + soc_a7ddrphy_bitslip4_value <= 3'd0; + soc_a7ddrphy_bitslip5_value <= 3'd0; + soc_a7ddrphy_bitslip6_value <= 3'd0; + soc_a7ddrphy_bitslip7_value <= 3'd0; + soc_a7ddrphy_bitslip8_value <= 3'd0; + soc_a7ddrphy_bitslip9_value <= 3'd0; + soc_a7ddrphy_bitslip10_value <= 3'd0; + soc_a7ddrphy_bitslip11_value <= 3'd0; + soc_a7ddrphy_bitslip12_value <= 3'd0; + soc_a7ddrphy_bitslip13_value <= 3'd0; + soc_a7ddrphy_bitslip14_value <= 3'd0; + soc_a7ddrphy_bitslip15_value <= 3'd0; + soc_a7ddrphy_rddata_en_last <= 8'd0; + soc_a7ddrphy_wrdata_en_last <= 4'd0; + soc_sdram_storage <= 4'd0; + soc_sdram_re <= 1'd0; + soc_sdram_phaseinjector0_command_storage <= 6'd0; + soc_sdram_phaseinjector0_command_re <= 1'd0; + soc_sdram_phaseinjector0_address_re <= 1'd0; + soc_sdram_phaseinjector0_baddress_re <= 1'd0; + soc_sdram_phaseinjector0_wrdata_re <= 1'd0; + soc_sdram_phaseinjector0_status <= 32'd0; + soc_sdram_phaseinjector1_command_storage <= 6'd0; + soc_sdram_phaseinjector1_command_re <= 1'd0; + soc_sdram_phaseinjector1_address_re <= 1'd0; + soc_sdram_phaseinjector1_baddress_re <= 1'd0; + soc_sdram_phaseinjector1_wrdata_re <= 1'd0; + soc_sdram_phaseinjector1_status <= 32'd0; + soc_sdram_phaseinjector2_command_storage <= 6'd0; + soc_sdram_phaseinjector2_command_re <= 1'd0; + soc_sdram_phaseinjector2_address_re <= 1'd0; + soc_sdram_phaseinjector2_baddress_re <= 1'd0; + soc_sdram_phaseinjector2_wrdata_re <= 1'd0; + soc_sdram_phaseinjector2_status <= 32'd0; + soc_sdram_phaseinjector3_command_storage <= 6'd0; + soc_sdram_phaseinjector3_command_re <= 1'd0; + soc_sdram_phaseinjector3_address_re <= 1'd0; + soc_sdram_phaseinjector3_baddress_re <= 1'd0; + soc_sdram_phaseinjector3_wrdata_re <= 1'd0; + soc_sdram_phaseinjector3_status <= 32'd0; + soc_sdram_dfi_p0_address <= 15'd0; + soc_sdram_dfi_p0_bank <= 3'd0; + soc_sdram_dfi_p0_cas_n <= 1'd1; + soc_sdram_dfi_p0_cs_n <= 1'd1; + soc_sdram_dfi_p0_ras_n <= 1'd1; + soc_sdram_dfi_p0_we_n <= 1'd1; + soc_sdram_dfi_p0_wrdata_en <= 1'd0; + soc_sdram_dfi_p0_rddata_en <= 1'd0; + soc_sdram_dfi_p1_address <= 15'd0; + soc_sdram_dfi_p1_bank <= 3'd0; + soc_sdram_dfi_p1_cas_n <= 1'd1; + soc_sdram_dfi_p1_cs_n <= 1'd1; + soc_sdram_dfi_p1_ras_n <= 1'd1; + soc_sdram_dfi_p1_we_n <= 1'd1; + soc_sdram_dfi_p1_wrdata_en <= 1'd0; + soc_sdram_dfi_p1_rddata_en <= 1'd0; + soc_sdram_dfi_p2_address <= 15'd0; + soc_sdram_dfi_p2_bank <= 3'd0; + soc_sdram_dfi_p2_cas_n <= 1'd1; + soc_sdram_dfi_p2_cs_n <= 1'd1; + soc_sdram_dfi_p2_ras_n <= 1'd1; + soc_sdram_dfi_p2_we_n <= 1'd1; + soc_sdram_dfi_p2_wrdata_en <= 1'd0; + soc_sdram_dfi_p2_rddata_en <= 1'd0; + soc_sdram_dfi_p3_address <= 15'd0; + soc_sdram_dfi_p3_bank <= 3'd0; + soc_sdram_dfi_p3_cas_n <= 1'd1; + soc_sdram_dfi_p3_cs_n <= 1'd1; + soc_sdram_dfi_p3_ras_n <= 1'd1; + soc_sdram_dfi_p3_we_n <= 1'd1; + soc_sdram_dfi_p3_wrdata_en <= 1'd0; + soc_sdram_dfi_p3_rddata_en <= 1'd0; + soc_sdram_timer_count1 <= 10'd781; + soc_sdram_postponer_req_o <= 1'd0; + soc_sdram_postponer_count <= 1'd0; + soc_sdram_sequencer_done1 <= 1'd0; + soc_sdram_sequencer_counter <= 6'd0; + soc_sdram_sequencer_count <= 1'd0; + soc_sdram_zqcs_timer_count1 <= 27'd99999999; + soc_sdram_zqcs_executer_done <= 1'd0; + soc_sdram_zqcs_executer_counter <= 5'd0; + soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; + soc_sdram_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; + soc_sdram_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; + soc_sdram_bankmachine0_cmd_buffer_source_valid <= 1'd0; + soc_sdram_bankmachine0_row <= 15'd0; + soc_sdram_bankmachine0_row_opened <= 1'd0; + soc_sdram_bankmachine0_twtpcon_ready <= 1'd1; + soc_sdram_bankmachine0_twtpcon_count <= 3'd0; + soc_sdram_bankmachine0_trccon_ready <= 1'd1; + soc_sdram_bankmachine0_trccon_count <= 3'd0; + soc_sdram_bankmachine0_trascon_ready <= 1'd1; + soc_sdram_bankmachine0_trascon_count <= 3'd0; + soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; + soc_sdram_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; + soc_sdram_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; + soc_sdram_bankmachine1_cmd_buffer_source_valid <= 1'd0; + soc_sdram_bankmachine1_row <= 15'd0; + soc_sdram_bankmachine1_row_opened <= 1'd0; + soc_sdram_bankmachine1_twtpcon_ready <= 1'd1; + soc_sdram_bankmachine1_twtpcon_count <= 3'd0; + soc_sdram_bankmachine1_trccon_ready <= 1'd1; + soc_sdram_bankmachine1_trccon_count <= 3'd0; + soc_sdram_bankmachine1_trascon_ready <= 1'd1; + soc_sdram_bankmachine1_trascon_count <= 3'd0; + soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; + soc_sdram_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; + soc_sdram_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; + soc_sdram_bankmachine2_cmd_buffer_source_valid <= 1'd0; + soc_sdram_bankmachine2_row <= 15'd0; + soc_sdram_bankmachine2_row_opened <= 1'd0; + soc_sdram_bankmachine2_twtpcon_ready <= 1'd1; + soc_sdram_bankmachine2_twtpcon_count <= 3'd0; + soc_sdram_bankmachine2_trccon_ready <= 1'd1; + soc_sdram_bankmachine2_trccon_count <= 3'd0; + soc_sdram_bankmachine2_trascon_ready <= 1'd1; + soc_sdram_bankmachine2_trascon_count <= 3'd0; + soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; + soc_sdram_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; + soc_sdram_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; + soc_sdram_bankmachine3_cmd_buffer_source_valid <= 1'd0; + soc_sdram_bankmachine3_row <= 15'd0; + soc_sdram_bankmachine3_row_opened <= 1'd0; + soc_sdram_bankmachine3_twtpcon_ready <= 1'd1; + soc_sdram_bankmachine3_twtpcon_count <= 3'd0; + soc_sdram_bankmachine3_trccon_ready <= 1'd1; + soc_sdram_bankmachine3_trccon_count <= 3'd0; + soc_sdram_bankmachine3_trascon_ready <= 1'd1; + soc_sdram_bankmachine3_trascon_count <= 3'd0; + soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; + soc_sdram_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; + soc_sdram_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; + soc_sdram_bankmachine4_cmd_buffer_source_valid <= 1'd0; + soc_sdram_bankmachine4_row <= 15'd0; + soc_sdram_bankmachine4_row_opened <= 1'd0; + soc_sdram_bankmachine4_twtpcon_ready <= 1'd1; + soc_sdram_bankmachine4_twtpcon_count <= 3'd0; + soc_sdram_bankmachine4_trccon_ready <= 1'd1; + soc_sdram_bankmachine4_trccon_count <= 3'd0; + soc_sdram_bankmachine4_trascon_ready <= 1'd1; + soc_sdram_bankmachine4_trascon_count <= 3'd0; + soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; + soc_sdram_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; + soc_sdram_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; + soc_sdram_bankmachine5_cmd_buffer_source_valid <= 1'd0; + soc_sdram_bankmachine5_row <= 15'd0; + soc_sdram_bankmachine5_row_opened <= 1'd0; + soc_sdram_bankmachine5_twtpcon_ready <= 1'd1; + soc_sdram_bankmachine5_twtpcon_count <= 3'd0; + soc_sdram_bankmachine5_trccon_ready <= 1'd1; + soc_sdram_bankmachine5_trccon_count <= 3'd0; + soc_sdram_bankmachine5_trascon_ready <= 1'd1; + soc_sdram_bankmachine5_trascon_count <= 3'd0; + soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; + soc_sdram_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; + soc_sdram_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; + soc_sdram_bankmachine6_cmd_buffer_source_valid <= 1'd0; + soc_sdram_bankmachine6_row <= 15'd0; + soc_sdram_bankmachine6_row_opened <= 1'd0; + soc_sdram_bankmachine6_twtpcon_ready <= 1'd1; + soc_sdram_bankmachine6_twtpcon_count <= 3'd0; + soc_sdram_bankmachine6_trccon_ready <= 1'd1; + soc_sdram_bankmachine6_trccon_count <= 3'd0; + soc_sdram_bankmachine6_trascon_ready <= 1'd1; + soc_sdram_bankmachine6_trascon_count <= 3'd0; + soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; + soc_sdram_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; + soc_sdram_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; + soc_sdram_bankmachine7_cmd_buffer_source_valid <= 1'd0; + soc_sdram_bankmachine7_row <= 15'd0; + soc_sdram_bankmachine7_row_opened <= 1'd0; + soc_sdram_bankmachine7_twtpcon_ready <= 1'd1; + soc_sdram_bankmachine7_twtpcon_count <= 3'd0; + soc_sdram_bankmachine7_trccon_ready <= 1'd1; + soc_sdram_bankmachine7_trccon_count <= 3'd0; + soc_sdram_bankmachine7_trascon_ready <= 1'd1; + soc_sdram_bankmachine7_trascon_count <= 3'd0; + soc_sdram_choose_cmd_grant <= 3'd0; + soc_sdram_choose_req_grant <= 3'd0; + soc_sdram_trrdcon_ready <= 1'd1; + soc_sdram_trrdcon_count <= 1'd0; + soc_sdram_tfawcon_ready <= 1'd1; + soc_sdram_tfawcon_window <= 5'd0; + soc_sdram_tccdcon_ready <= 1'd1; + soc_sdram_tccdcon_count <= 1'd0; + soc_sdram_twtrcon_ready <= 1'd1; + soc_sdram_twtrcon_count <= 3'd0; + soc_sdram_time0 <= 5'd0; + soc_sdram_time1 <= 4'd0; + soc_address_q <= 30'd0; + soc_counter <= 2'd0; + soc_need_refill_q <= 1'd1; + soc_cached_datas_flipflop0_q <= 32'd0; + soc_cached_datas_flipflop1_q <= 32'd0; + soc_cached_datas_flipflop2_q <= 32'd0; + soc_cached_datas_flipflop3_q <= 32'd0; + soc_cached_sels_flipflop0_q <= 4'd0; + soc_cached_sels_flipflop1_q <= 4'd0; + soc_cached_sels_flipflop2_q <= 4'd0; + soc_cached_sels_flipflop3_q <= 4'd0; + soc_count <= 1'd0; + soc_init_done_storage <= 1'd0; + soc_init_done_re <= 1'd0; + soc_init_error_storage <= 1'd0; + soc_init_error_re <= 1'd0; + vns_wb2csr_state <= 1'd0; + vns_refresher_state <= 2'd0; + vns_bankmachine0_state <= 4'd0; + vns_bankmachine1_state <= 4'd0; + vns_bankmachine2_state <= 4'd0; + vns_bankmachine3_state <= 4'd0; + vns_bankmachine4_state <= 4'd0; + vns_bankmachine5_state <= 4'd0; + vns_bankmachine6_state <= 4'd0; + vns_bankmachine7_state <= 4'd0; + vns_multiplexer_state <= 4'd0; + vns_roundrobin0_grant <= 1'd0; + vns_roundrobin1_grant <= 1'd0; + vns_roundrobin2_grant <= 1'd0; + vns_roundrobin3_grant <= 1'd0; + vns_roundrobin4_grant <= 1'd0; + vns_roundrobin5_grant <= 1'd0; + vns_roundrobin6_grant <= 1'd0; + vns_roundrobin7_grant <= 1'd0; + vns_new_master_wdata_ready0 <= 1'd0; + vns_new_master_wdata_ready1 <= 1'd0; + vns_new_master_wdata_ready2 <= 1'd0; + vns_new_master_wdata_ready3 <= 1'd0; + vns_new_master_wdata_ready4 <= 1'd0; + vns_new_master_wdata_ready5 <= 1'd0; + vns_new_master_rdata_valid0 <= 1'd0; + vns_new_master_rdata_valid1 <= 1'd0; + vns_new_master_rdata_valid2 <= 1'd0; + vns_new_master_rdata_valid3 <= 1'd0; + vns_new_master_rdata_valid4 <= 1'd0; + vns_new_master_rdata_valid5 <= 1'd0; + vns_new_master_rdata_valid6 <= 1'd0; + vns_new_master_rdata_valid7 <= 1'd0; + vns_new_master_rdata_valid8 <= 1'd0; + vns_new_master_rdata_valid9 <= 1'd0; + vns_new_master_rdata_valid10 <= 1'd0; + vns_new_master_rdata_valid11 <= 1'd0; + vns_new_master_rdata_valid12 <= 1'd0; + vns_new_master_rdata_valid13 <= 1'd0; + vns_new_master_rdata_valid14 <= 1'd0; + vns_new_master_rdata_valid15 <= 1'd0; + vns_new_master_rdata_valid16 <= 1'd0; + vns_new_master_rdata_valid17 <= 1'd0; + vns_converter_state <= 3'd0; + vns_litedramwishbone2native_state <= 2'd0; + vns_grant <= 1'd0; + vns_slave_sel_r <= 4'd0; + vns_count <= 20'd1000000; + end + vns_regs0 <= serial_rx; + vns_regs1 <= vns_regs0; +end + +reg [31:0] mem[0:6143]; +reg [31:0] memdat; +always @(posedge sys_clk) begin + memdat <= mem[soc_litedramcore_litedramcore_adr]; +end + +assign soc_litedramcore_litedramcore_dat_r = memdat; + +initial begin + $readmemh("litedram_core.init", mem); +end + +reg [31:0] mem_1[0:1023]; +reg [9:0] memadr; +always @(posedge sys_clk) begin + if (soc_litedramcore_ram_we[0]) + mem_1[soc_litedramcore_ram_adr][7:0] <= soc_litedramcore_ram_dat_w[7:0]; + if (soc_litedramcore_ram_we[1]) + mem_1[soc_litedramcore_ram_adr][15:8] <= soc_litedramcore_ram_dat_w[15:8]; + if (soc_litedramcore_ram_we[2]) + mem_1[soc_litedramcore_ram_adr][23:16] <= soc_litedramcore_ram_dat_w[23:16]; + if (soc_litedramcore_ram_we[3]) + mem_1[soc_litedramcore_ram_adr][31:24] <= soc_litedramcore_ram_dat_w[31:24]; + memadr <= soc_litedramcore_ram_adr; +end + +assign soc_litedramcore_ram_dat_r = mem_1[memadr]; + +initial begin + $readmemh("mem_1.init", mem_1); +end + +reg [9:0] storage[0:15]; +reg [9:0] memdat_1; +reg [9:0] memdat_2; +always @(posedge sys_clk) begin + if (soc_litedramcore_uart_tx_fifo_wrport_we) + storage[soc_litedramcore_uart_tx_fifo_wrport_adr] <= soc_litedramcore_uart_tx_fifo_wrport_dat_w; + memdat_1 <= storage[soc_litedramcore_uart_tx_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (soc_litedramcore_uart_tx_fifo_rdport_re) + memdat_2 <= storage[soc_litedramcore_uart_tx_fifo_rdport_adr]; +end + +assign soc_litedramcore_uart_tx_fifo_wrport_dat_r = memdat_1; +assign soc_litedramcore_uart_tx_fifo_rdport_dat_r = memdat_2; + +reg [9:0] storage_1[0:15]; +reg [9:0] memdat_3; +reg [9:0] memdat_4; +always @(posedge sys_clk) begin + if (soc_litedramcore_uart_rx_fifo_wrport_we) + storage_1[soc_litedramcore_uart_rx_fifo_wrport_adr] <= soc_litedramcore_uart_rx_fifo_wrport_dat_w; + memdat_3 <= storage_1[soc_litedramcore_uart_rx_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (soc_litedramcore_uart_rx_fifo_rdport_re) + memdat_4 <= storage_1[soc_litedramcore_uart_rx_fifo_rdport_adr]; +end + +assign soc_litedramcore_uart_rx_fifo_wrport_dat_r = memdat_3; +assign soc_litedramcore_uart_rx_fifo_rdport_dat_r = memdat_4; + +BUFG BUFG( + .I(soc_s7pll0_clkout0), + .O(soc_s7pll0_clkout_buf0) +); + +BUFG BUFG_1( + .I(soc_s7pll0_clkout1), + .O(soc_s7pll0_clkout_buf1) +); + +BUFG BUFG_2( + .I(soc_s7pll0_clkout2), + .O(soc_s7pll0_clkout_buf2) +); + +BUFG BUFG_3( + .I(soc_s7pll1_clkout), + .O(soc_s7pll1_clkout_buf) +); + +IDELAYCTRL IDELAYCTRL( + .REFCLK(iodelay_clk), + .RST(soc_ic_reset) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(1'd0), + .D2(1'd1), + .D3(1'd0), + .D4(1'd1), + .D5(1'd0), + .D6(1'd1), + .D7(1'd0), + .D8(1'd1), + .OCE(1'd1), + .RST(sys_rst), + .OQ(soc_a7ddrphy_sd_clk_se_nodelay) +); + +OBUFDS OBUFDS( + .I(soc_a7ddrphy_sd_clk_se_nodelay), + .O(ddram_clk_p), + .OB(ddram_clk_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_1 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[0]), + .D2(soc_a7ddrphy_dfi_p0_address[0]), + .D3(soc_a7ddrphy_dfi_p1_address[0]), + .D4(soc_a7ddrphy_dfi_p1_address[0]), + .D5(soc_a7ddrphy_dfi_p2_address[0]), + .D6(soc_a7ddrphy_dfi_p2_address[0]), + .D7(soc_a7ddrphy_dfi_p3_address[0]), + .D8(soc_a7ddrphy_dfi_p3_address[0]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_2 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[1]), + .D2(soc_a7ddrphy_dfi_p0_address[1]), + .D3(soc_a7ddrphy_dfi_p1_address[1]), + .D4(soc_a7ddrphy_dfi_p1_address[1]), + .D5(soc_a7ddrphy_dfi_p2_address[1]), + .D6(soc_a7ddrphy_dfi_p2_address[1]), + .D7(soc_a7ddrphy_dfi_p3_address[1]), + .D8(soc_a7ddrphy_dfi_p3_address[1]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_3 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[2]), + .D2(soc_a7ddrphy_dfi_p0_address[2]), + .D3(soc_a7ddrphy_dfi_p1_address[2]), + .D4(soc_a7ddrphy_dfi_p1_address[2]), + .D5(soc_a7ddrphy_dfi_p2_address[2]), + .D6(soc_a7ddrphy_dfi_p2_address[2]), + .D7(soc_a7ddrphy_dfi_p3_address[2]), + .D8(soc_a7ddrphy_dfi_p3_address[2]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[2]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_4 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[3]), + .D2(soc_a7ddrphy_dfi_p0_address[3]), + .D3(soc_a7ddrphy_dfi_p1_address[3]), + .D4(soc_a7ddrphy_dfi_p1_address[3]), + .D5(soc_a7ddrphy_dfi_p2_address[3]), + .D6(soc_a7ddrphy_dfi_p2_address[3]), + .D7(soc_a7ddrphy_dfi_p3_address[3]), + .D8(soc_a7ddrphy_dfi_p3_address[3]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[3]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_5 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[4]), + .D2(soc_a7ddrphy_dfi_p0_address[4]), + .D3(soc_a7ddrphy_dfi_p1_address[4]), + .D4(soc_a7ddrphy_dfi_p1_address[4]), + .D5(soc_a7ddrphy_dfi_p2_address[4]), + .D6(soc_a7ddrphy_dfi_p2_address[4]), + .D7(soc_a7ddrphy_dfi_p3_address[4]), + .D8(soc_a7ddrphy_dfi_p3_address[4]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[4]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_6 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[5]), + .D2(soc_a7ddrphy_dfi_p0_address[5]), + .D3(soc_a7ddrphy_dfi_p1_address[5]), + .D4(soc_a7ddrphy_dfi_p1_address[5]), + .D5(soc_a7ddrphy_dfi_p2_address[5]), + .D6(soc_a7ddrphy_dfi_p2_address[5]), + .D7(soc_a7ddrphy_dfi_p3_address[5]), + .D8(soc_a7ddrphy_dfi_p3_address[5]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[5]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_7 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[6]), + .D2(soc_a7ddrphy_dfi_p0_address[6]), + .D3(soc_a7ddrphy_dfi_p1_address[6]), + .D4(soc_a7ddrphy_dfi_p1_address[6]), + .D5(soc_a7ddrphy_dfi_p2_address[6]), + .D6(soc_a7ddrphy_dfi_p2_address[6]), + .D7(soc_a7ddrphy_dfi_p3_address[6]), + .D8(soc_a7ddrphy_dfi_p3_address[6]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[6]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_8 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[7]), + .D2(soc_a7ddrphy_dfi_p0_address[7]), + .D3(soc_a7ddrphy_dfi_p1_address[7]), + .D4(soc_a7ddrphy_dfi_p1_address[7]), + .D5(soc_a7ddrphy_dfi_p2_address[7]), + .D6(soc_a7ddrphy_dfi_p2_address[7]), + .D7(soc_a7ddrphy_dfi_p3_address[7]), + .D8(soc_a7ddrphy_dfi_p3_address[7]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[7]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_9 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[8]), + .D2(soc_a7ddrphy_dfi_p0_address[8]), + .D3(soc_a7ddrphy_dfi_p1_address[8]), + .D4(soc_a7ddrphy_dfi_p1_address[8]), + .D5(soc_a7ddrphy_dfi_p2_address[8]), + .D6(soc_a7ddrphy_dfi_p2_address[8]), + .D7(soc_a7ddrphy_dfi_p3_address[8]), + .D8(soc_a7ddrphy_dfi_p3_address[8]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[8]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_10 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[9]), + .D2(soc_a7ddrphy_dfi_p0_address[9]), + .D3(soc_a7ddrphy_dfi_p1_address[9]), + .D4(soc_a7ddrphy_dfi_p1_address[9]), + .D5(soc_a7ddrphy_dfi_p2_address[9]), + .D6(soc_a7ddrphy_dfi_p2_address[9]), + .D7(soc_a7ddrphy_dfi_p3_address[9]), + .D8(soc_a7ddrphy_dfi_p3_address[9]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[9]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_11 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[10]), + .D2(soc_a7ddrphy_dfi_p0_address[10]), + .D3(soc_a7ddrphy_dfi_p1_address[10]), + .D4(soc_a7ddrphy_dfi_p1_address[10]), + .D5(soc_a7ddrphy_dfi_p2_address[10]), + .D6(soc_a7ddrphy_dfi_p2_address[10]), + .D7(soc_a7ddrphy_dfi_p3_address[10]), + .D8(soc_a7ddrphy_dfi_p3_address[10]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[10]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_12 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[11]), + .D2(soc_a7ddrphy_dfi_p0_address[11]), + .D3(soc_a7ddrphy_dfi_p1_address[11]), + .D4(soc_a7ddrphy_dfi_p1_address[11]), + .D5(soc_a7ddrphy_dfi_p2_address[11]), + .D6(soc_a7ddrphy_dfi_p2_address[11]), + .D7(soc_a7ddrphy_dfi_p3_address[11]), + .D8(soc_a7ddrphy_dfi_p3_address[11]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[11]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_13 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[12]), + .D2(soc_a7ddrphy_dfi_p0_address[12]), + .D3(soc_a7ddrphy_dfi_p1_address[12]), + .D4(soc_a7ddrphy_dfi_p1_address[12]), + .D5(soc_a7ddrphy_dfi_p2_address[12]), + .D6(soc_a7ddrphy_dfi_p2_address[12]), + .D7(soc_a7ddrphy_dfi_p3_address[12]), + .D8(soc_a7ddrphy_dfi_p3_address[12]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[12]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_14 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[13]), + .D2(soc_a7ddrphy_dfi_p0_address[13]), + .D3(soc_a7ddrphy_dfi_p1_address[13]), + .D4(soc_a7ddrphy_dfi_p1_address[13]), + .D5(soc_a7ddrphy_dfi_p2_address[13]), + .D6(soc_a7ddrphy_dfi_p2_address[13]), + .D7(soc_a7ddrphy_dfi_p3_address[13]), + .D8(soc_a7ddrphy_dfi_p3_address[13]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[13]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_15 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_address[14]), + .D2(soc_a7ddrphy_dfi_p0_address[14]), + .D3(soc_a7ddrphy_dfi_p1_address[14]), + .D4(soc_a7ddrphy_dfi_p1_address[14]), + .D5(soc_a7ddrphy_dfi_p2_address[14]), + .D6(soc_a7ddrphy_dfi_p2_address[14]), + .D7(soc_a7ddrphy_dfi_p3_address[14]), + .D8(soc_a7ddrphy_dfi_p3_address[14]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[14]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_16 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_bank[0]), + .D2(soc_a7ddrphy_dfi_p0_bank[0]), + .D3(soc_a7ddrphy_dfi_p1_bank[0]), + .D4(soc_a7ddrphy_dfi_p1_bank[0]), + .D5(soc_a7ddrphy_dfi_p2_bank[0]), + .D6(soc_a7ddrphy_dfi_p2_bank[0]), + .D7(soc_a7ddrphy_dfi_p3_bank[0]), + .D8(soc_a7ddrphy_dfi_p3_bank[0]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_ba[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_17 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_bank[1]), + .D2(soc_a7ddrphy_dfi_p0_bank[1]), + .D3(soc_a7ddrphy_dfi_p1_bank[1]), + .D4(soc_a7ddrphy_dfi_p1_bank[1]), + .D5(soc_a7ddrphy_dfi_p2_bank[1]), + .D6(soc_a7ddrphy_dfi_p2_bank[1]), + .D7(soc_a7ddrphy_dfi_p3_bank[1]), + .D8(soc_a7ddrphy_dfi_p3_bank[1]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_ba[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_18 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_bank[2]), + .D2(soc_a7ddrphy_dfi_p0_bank[2]), + .D3(soc_a7ddrphy_dfi_p1_bank[2]), + .D4(soc_a7ddrphy_dfi_p1_bank[2]), + .D5(soc_a7ddrphy_dfi_p2_bank[2]), + .D6(soc_a7ddrphy_dfi_p2_bank[2]), + .D7(soc_a7ddrphy_dfi_p3_bank[2]), + .D8(soc_a7ddrphy_dfi_p3_bank[2]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_ba[2]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_19 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_ras_n), + .D2(soc_a7ddrphy_dfi_p0_ras_n), + .D3(soc_a7ddrphy_dfi_p1_ras_n), + .D4(soc_a7ddrphy_dfi_p1_ras_n), + .D5(soc_a7ddrphy_dfi_p2_ras_n), + .D6(soc_a7ddrphy_dfi_p2_ras_n), + .D7(soc_a7ddrphy_dfi_p3_ras_n), + .D8(soc_a7ddrphy_dfi_p3_ras_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_ras_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_20 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_cas_n), + .D2(soc_a7ddrphy_dfi_p0_cas_n), + .D3(soc_a7ddrphy_dfi_p1_cas_n), + .D4(soc_a7ddrphy_dfi_p1_cas_n), + .D5(soc_a7ddrphy_dfi_p2_cas_n), + .D6(soc_a7ddrphy_dfi_p2_cas_n), + .D7(soc_a7ddrphy_dfi_p3_cas_n), + .D8(soc_a7ddrphy_dfi_p3_cas_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_cas_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_21 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_we_n), + .D2(soc_a7ddrphy_dfi_p0_we_n), + .D3(soc_a7ddrphy_dfi_p1_we_n), + .D4(soc_a7ddrphy_dfi_p1_we_n), + .D5(soc_a7ddrphy_dfi_p2_we_n), + .D6(soc_a7ddrphy_dfi_p2_we_n), + .D7(soc_a7ddrphy_dfi_p3_we_n), + .D8(soc_a7ddrphy_dfi_p3_we_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_we_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_22 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_cke), + .D2(soc_a7ddrphy_dfi_p0_cke), + .D3(soc_a7ddrphy_dfi_p1_cke), + .D4(soc_a7ddrphy_dfi_p1_cke), + .D5(soc_a7ddrphy_dfi_p2_cke), + .D6(soc_a7ddrphy_dfi_p2_cke), + .D7(soc_a7ddrphy_dfi_p3_cke), + .D8(soc_a7ddrphy_dfi_p3_cke), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_cke) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_23 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_odt), + .D2(soc_a7ddrphy_dfi_p0_odt), + .D3(soc_a7ddrphy_dfi_p1_odt), + .D4(soc_a7ddrphy_dfi_p1_odt), + .D5(soc_a7ddrphy_dfi_p2_odt), + .D6(soc_a7ddrphy_dfi_p2_odt), + .D7(soc_a7ddrphy_dfi_p3_odt), + .D8(soc_a7ddrphy_dfi_p3_odt), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_odt) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_24 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_reset_n), + .D2(soc_a7ddrphy_dfi_p0_reset_n), + .D3(soc_a7ddrphy_dfi_p1_reset_n), + .D4(soc_a7ddrphy_dfi_p1_reset_n), + .D5(soc_a7ddrphy_dfi_p2_reset_n), + .D6(soc_a7ddrphy_dfi_p2_reset_n), + .D7(soc_a7ddrphy_dfi_p3_reset_n), + .D8(soc_a7ddrphy_dfi_p3_reset_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_reset_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_25 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_cs_n), + .D2(soc_a7ddrphy_dfi_p0_cs_n), + .D3(soc_a7ddrphy_dfi_p1_cs_n), + .D4(soc_a7ddrphy_dfi_p1_cs_n), + .D5(soc_a7ddrphy_dfi_p2_cs_n), + .D6(soc_a7ddrphy_dfi_p2_cs_n), + .D7(soc_a7ddrphy_dfi_p3_cs_n), + .D8(soc_a7ddrphy_dfi_p3_cs_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_cs_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_26 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[0]), + .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[2]), + .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[0]), + .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[2]), + .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[0]), + .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[2]), + .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[0]), + .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[2]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_dm[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_27 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[1]), + .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[3]), + .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[1]), + .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[3]), + .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[1]), + .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[3]), + .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[1]), + .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[3]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_dm[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_28 ( + .CLK(sys4x_dqs_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dqspattern_o1[0]), + .D2(soc_a7ddrphy_dqspattern_o1[1]), + .D3(soc_a7ddrphy_dqspattern_o1[2]), + .D4(soc_a7ddrphy_dqspattern_o1[3]), + .D5(soc_a7ddrphy_dqspattern_o1[4]), + .D6(soc_a7ddrphy_dqspattern_o1[5]), + .D7(soc_a7ddrphy_dqspattern_o1[6]), + .D8(soc_a7ddrphy_dqspattern_o1[7]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dqs_oe_delayed)), + .TCE(1'd1), + .OFB(soc_a7ddrphy0), + .OQ(soc_a7ddrphy_dqs_o_no_delay0), + .TQ(soc_a7ddrphy_dqs_t0) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("FIXED"), + .IDELAY_VALUE(4'd8), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2 ( + .IDATAIN(soc_a7ddrphy_dqs_i[0]), + .DATAOUT(soc_a7ddrphy_dqs_i_delayed[0]) +); + +IOBUFDS IOBUFDS( + .I(soc_a7ddrphy_dqs_o_no_delay0), + .T(soc_a7ddrphy_dqs_t0), + .IO(ddram_dqs_p[0]), + .IOB(ddram_dqs_n[0]), + .O(soc_a7ddrphy_dqs_i[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_29 ( + .CLK(sys4x_dqs_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dqspattern_o1[0]), + .D2(soc_a7ddrphy_dqspattern_o1[1]), + .D3(soc_a7ddrphy_dqspattern_o1[2]), + .D4(soc_a7ddrphy_dqspattern_o1[3]), + .D5(soc_a7ddrphy_dqspattern_o1[4]), + .D6(soc_a7ddrphy_dqspattern_o1[5]), + .D7(soc_a7ddrphy_dqspattern_o1[6]), + .D8(soc_a7ddrphy_dqspattern_o1[7]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dqs_oe_delayed)), + .TCE(1'd1), + .OFB(soc_a7ddrphy1), + .OQ(soc_a7ddrphy_dqs_o_no_delay1), + .TQ(soc_a7ddrphy_dqs_t1) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("FIXED"), + .IDELAY_VALUE(4'd8), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_1 ( + .IDATAIN(soc_a7ddrphy_dqs_i[1]), + .DATAOUT(soc_a7ddrphy_dqs_i_delayed[1]) +); + +IOBUFDS IOBUFDS_1( + .I(soc_a7ddrphy_dqs_o_no_delay1), + .T(soc_a7ddrphy_dqs_t1), + .IO(ddram_dqs_p[1]), + .IOB(ddram_dqs_n[1]), + .O(soc_a7ddrphy_dqs_i[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_30 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[0]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[16]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[0]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[16]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[0]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[16]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[0]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[16]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay0), + .TQ(soc_a7ddrphy_dq_t0) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed0), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data0[7]), + .Q2(soc_a7ddrphy_dq_i_data0[6]), + .Q3(soc_a7ddrphy_dq_i_data0[5]), + .Q4(soc_a7ddrphy_dq_i_data0[4]), + .Q5(soc_a7ddrphy_dq_i_data0[3]), + .Q6(soc_a7ddrphy_dq_i_data0[2]), + .Q7(soc_a7ddrphy_dq_i_data0[1]), + .Q8(soc_a7ddrphy_dq_i_data0[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_2 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay0), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed0) +); + +IOBUF IOBUF( + .I(soc_a7ddrphy_dq_o_nodelay0), + .T(soc_a7ddrphy_dq_t0), + .IO(ddram_dq[0]), + .O(soc_a7ddrphy_dq_i_nodelay0) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_31 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[1]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[17]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[1]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[17]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[1]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[17]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[1]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[17]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay1), + .TQ(soc_a7ddrphy_dq_t1) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_1 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed1), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data1[7]), + .Q2(soc_a7ddrphy_dq_i_data1[6]), + .Q3(soc_a7ddrphy_dq_i_data1[5]), + .Q4(soc_a7ddrphy_dq_i_data1[4]), + .Q5(soc_a7ddrphy_dq_i_data1[3]), + .Q6(soc_a7ddrphy_dq_i_data1[2]), + .Q7(soc_a7ddrphy_dq_i_data1[1]), + .Q8(soc_a7ddrphy_dq_i_data1[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_3 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay1), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed1) +); + +IOBUF IOBUF_1( + .I(soc_a7ddrphy_dq_o_nodelay1), + .T(soc_a7ddrphy_dq_t1), + .IO(ddram_dq[1]), + .O(soc_a7ddrphy_dq_i_nodelay1) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_32 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[2]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[18]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[2]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[18]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[2]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[18]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[2]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[18]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay2), + .TQ(soc_a7ddrphy_dq_t2) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_2 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed2), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data2[7]), + .Q2(soc_a7ddrphy_dq_i_data2[6]), + .Q3(soc_a7ddrphy_dq_i_data2[5]), + .Q4(soc_a7ddrphy_dq_i_data2[4]), + .Q5(soc_a7ddrphy_dq_i_data2[3]), + .Q6(soc_a7ddrphy_dq_i_data2[2]), + .Q7(soc_a7ddrphy_dq_i_data2[1]), + .Q8(soc_a7ddrphy_dq_i_data2[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_4 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay2), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed2) +); + +IOBUF IOBUF_2( + .I(soc_a7ddrphy_dq_o_nodelay2), + .T(soc_a7ddrphy_dq_t2), + .IO(ddram_dq[2]), + .O(soc_a7ddrphy_dq_i_nodelay2) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_33 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[3]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[19]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[3]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[19]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[3]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[19]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[3]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[19]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay3), + .TQ(soc_a7ddrphy_dq_t3) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_3 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed3), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data3[7]), + .Q2(soc_a7ddrphy_dq_i_data3[6]), + .Q3(soc_a7ddrphy_dq_i_data3[5]), + .Q4(soc_a7ddrphy_dq_i_data3[4]), + .Q5(soc_a7ddrphy_dq_i_data3[3]), + .Q6(soc_a7ddrphy_dq_i_data3[2]), + .Q7(soc_a7ddrphy_dq_i_data3[1]), + .Q8(soc_a7ddrphy_dq_i_data3[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_5 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay3), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed3) +); + +IOBUF IOBUF_3( + .I(soc_a7ddrphy_dq_o_nodelay3), + .T(soc_a7ddrphy_dq_t3), + .IO(ddram_dq[3]), + .O(soc_a7ddrphy_dq_i_nodelay3) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_34 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[4]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[20]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[4]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[20]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[4]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[20]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[4]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[20]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay4), + .TQ(soc_a7ddrphy_dq_t4) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_4 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed4), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data4[7]), + .Q2(soc_a7ddrphy_dq_i_data4[6]), + .Q3(soc_a7ddrphy_dq_i_data4[5]), + .Q4(soc_a7ddrphy_dq_i_data4[4]), + .Q5(soc_a7ddrphy_dq_i_data4[3]), + .Q6(soc_a7ddrphy_dq_i_data4[2]), + .Q7(soc_a7ddrphy_dq_i_data4[1]), + .Q8(soc_a7ddrphy_dq_i_data4[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_6 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay4), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed4) +); + +IOBUF IOBUF_4( + .I(soc_a7ddrphy_dq_o_nodelay4), + .T(soc_a7ddrphy_dq_t4), + .IO(ddram_dq[4]), + .O(soc_a7ddrphy_dq_i_nodelay4) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_35 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[5]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[21]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[5]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[21]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[5]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[21]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[5]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[21]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay5), + .TQ(soc_a7ddrphy_dq_t5) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_5 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed5), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data5[7]), + .Q2(soc_a7ddrphy_dq_i_data5[6]), + .Q3(soc_a7ddrphy_dq_i_data5[5]), + .Q4(soc_a7ddrphy_dq_i_data5[4]), + .Q5(soc_a7ddrphy_dq_i_data5[3]), + .Q6(soc_a7ddrphy_dq_i_data5[2]), + .Q7(soc_a7ddrphy_dq_i_data5[1]), + .Q8(soc_a7ddrphy_dq_i_data5[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_7 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay5), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed5) +); + +IOBUF IOBUF_5( + .I(soc_a7ddrphy_dq_o_nodelay5), + .T(soc_a7ddrphy_dq_t5), + .IO(ddram_dq[5]), + .O(soc_a7ddrphy_dq_i_nodelay5) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_36 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[6]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[22]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[6]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[22]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[6]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[22]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[6]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[22]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay6), + .TQ(soc_a7ddrphy_dq_t6) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_6 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed6), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data6[7]), + .Q2(soc_a7ddrphy_dq_i_data6[6]), + .Q3(soc_a7ddrphy_dq_i_data6[5]), + .Q4(soc_a7ddrphy_dq_i_data6[4]), + .Q5(soc_a7ddrphy_dq_i_data6[3]), + .Q6(soc_a7ddrphy_dq_i_data6[2]), + .Q7(soc_a7ddrphy_dq_i_data6[1]), + .Q8(soc_a7ddrphy_dq_i_data6[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_8 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay6), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed6) +); + +IOBUF IOBUF_6( + .I(soc_a7ddrphy_dq_o_nodelay6), + .T(soc_a7ddrphy_dq_t6), + .IO(ddram_dq[6]), + .O(soc_a7ddrphy_dq_i_nodelay6) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_37 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[7]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[23]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[7]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[23]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[7]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[23]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[7]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[23]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay7), + .TQ(soc_a7ddrphy_dq_t7) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_7 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed7), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data7[7]), + .Q2(soc_a7ddrphy_dq_i_data7[6]), + .Q3(soc_a7ddrphy_dq_i_data7[5]), + .Q4(soc_a7ddrphy_dq_i_data7[4]), + .Q5(soc_a7ddrphy_dq_i_data7[3]), + .Q6(soc_a7ddrphy_dq_i_data7[2]), + .Q7(soc_a7ddrphy_dq_i_data7[1]), + .Q8(soc_a7ddrphy_dq_i_data7[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_9 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay7), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed7) +); + +IOBUF IOBUF_7( + .I(soc_a7ddrphy_dq_o_nodelay7), + .T(soc_a7ddrphy_dq_t7), + .IO(ddram_dq[7]), + .O(soc_a7ddrphy_dq_i_nodelay7) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_38 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[8]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[24]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[8]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[24]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[8]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[24]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[8]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[24]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay8), + .TQ(soc_a7ddrphy_dq_t8) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_8 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed8), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data8[7]), + .Q2(soc_a7ddrphy_dq_i_data8[6]), + .Q3(soc_a7ddrphy_dq_i_data8[5]), + .Q4(soc_a7ddrphy_dq_i_data8[4]), + .Q5(soc_a7ddrphy_dq_i_data8[3]), + .Q6(soc_a7ddrphy_dq_i_data8[2]), + .Q7(soc_a7ddrphy_dq_i_data8[1]), + .Q8(soc_a7ddrphy_dq_i_data8[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_10 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay8), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed8) +); + +IOBUF IOBUF_8( + .I(soc_a7ddrphy_dq_o_nodelay8), + .T(soc_a7ddrphy_dq_t8), + .IO(ddram_dq[8]), + .O(soc_a7ddrphy_dq_i_nodelay8) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_39 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[9]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[25]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[9]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[25]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[9]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[25]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[9]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[25]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay9), + .TQ(soc_a7ddrphy_dq_t9) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_9 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed9), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data9[7]), + .Q2(soc_a7ddrphy_dq_i_data9[6]), + .Q3(soc_a7ddrphy_dq_i_data9[5]), + .Q4(soc_a7ddrphy_dq_i_data9[4]), + .Q5(soc_a7ddrphy_dq_i_data9[3]), + .Q6(soc_a7ddrphy_dq_i_data9[2]), + .Q7(soc_a7ddrphy_dq_i_data9[1]), + .Q8(soc_a7ddrphy_dq_i_data9[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_11 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay9), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed9) +); + +IOBUF IOBUF_9( + .I(soc_a7ddrphy_dq_o_nodelay9), + .T(soc_a7ddrphy_dq_t9), + .IO(ddram_dq[9]), + .O(soc_a7ddrphy_dq_i_nodelay9) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_40 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[10]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[26]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[10]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[26]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[10]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[26]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[10]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[26]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay10), + .TQ(soc_a7ddrphy_dq_t10) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_10 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed10), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data10[7]), + .Q2(soc_a7ddrphy_dq_i_data10[6]), + .Q3(soc_a7ddrphy_dq_i_data10[5]), + .Q4(soc_a7ddrphy_dq_i_data10[4]), + .Q5(soc_a7ddrphy_dq_i_data10[3]), + .Q6(soc_a7ddrphy_dq_i_data10[2]), + .Q7(soc_a7ddrphy_dq_i_data10[1]), + .Q8(soc_a7ddrphy_dq_i_data10[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_12 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay10), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed10) +); + +IOBUF IOBUF_10( + .I(soc_a7ddrphy_dq_o_nodelay10), + .T(soc_a7ddrphy_dq_t10), + .IO(ddram_dq[10]), + .O(soc_a7ddrphy_dq_i_nodelay10) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_41 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[11]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[27]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[11]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[27]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[11]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[27]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[11]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[27]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay11), + .TQ(soc_a7ddrphy_dq_t11) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_11 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed11), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data11[7]), + .Q2(soc_a7ddrphy_dq_i_data11[6]), + .Q3(soc_a7ddrphy_dq_i_data11[5]), + .Q4(soc_a7ddrphy_dq_i_data11[4]), + .Q5(soc_a7ddrphy_dq_i_data11[3]), + .Q6(soc_a7ddrphy_dq_i_data11[2]), + .Q7(soc_a7ddrphy_dq_i_data11[1]), + .Q8(soc_a7ddrphy_dq_i_data11[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_13 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay11), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed11) +); + +IOBUF IOBUF_11( + .I(soc_a7ddrphy_dq_o_nodelay11), + .T(soc_a7ddrphy_dq_t11), + .IO(ddram_dq[11]), + .O(soc_a7ddrphy_dq_i_nodelay11) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_42 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[12]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[28]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[12]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[28]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[12]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[28]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[12]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[28]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay12), + .TQ(soc_a7ddrphy_dq_t12) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_12 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed12), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data12[7]), + .Q2(soc_a7ddrphy_dq_i_data12[6]), + .Q3(soc_a7ddrphy_dq_i_data12[5]), + .Q4(soc_a7ddrphy_dq_i_data12[4]), + .Q5(soc_a7ddrphy_dq_i_data12[3]), + .Q6(soc_a7ddrphy_dq_i_data12[2]), + .Q7(soc_a7ddrphy_dq_i_data12[1]), + .Q8(soc_a7ddrphy_dq_i_data12[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_14 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay12), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed12) +); + +IOBUF IOBUF_12( + .I(soc_a7ddrphy_dq_o_nodelay12), + .T(soc_a7ddrphy_dq_t12), + .IO(ddram_dq[12]), + .O(soc_a7ddrphy_dq_i_nodelay12) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_43 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[13]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[29]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[13]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[29]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[13]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[29]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[13]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[29]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay13), + .TQ(soc_a7ddrphy_dq_t13) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_13 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed13), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data13[7]), + .Q2(soc_a7ddrphy_dq_i_data13[6]), + .Q3(soc_a7ddrphy_dq_i_data13[5]), + .Q4(soc_a7ddrphy_dq_i_data13[4]), + .Q5(soc_a7ddrphy_dq_i_data13[3]), + .Q6(soc_a7ddrphy_dq_i_data13[2]), + .Q7(soc_a7ddrphy_dq_i_data13[1]), + .Q8(soc_a7ddrphy_dq_i_data13[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_15 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay13), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed13) +); + +IOBUF IOBUF_13( + .I(soc_a7ddrphy_dq_o_nodelay13), + .T(soc_a7ddrphy_dq_t13), + .IO(ddram_dq[13]), + .O(soc_a7ddrphy_dq_i_nodelay13) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_44 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[14]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[30]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[14]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[30]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[14]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[30]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[14]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[30]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay14), + .TQ(soc_a7ddrphy_dq_t14) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_14 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed14), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data14[7]), + .Q2(soc_a7ddrphy_dq_i_data14[6]), + .Q3(soc_a7ddrphy_dq_i_data14[5]), + .Q4(soc_a7ddrphy_dq_i_data14[4]), + .Q5(soc_a7ddrphy_dq_i_data14[3]), + .Q6(soc_a7ddrphy_dq_i_data14[2]), + .Q7(soc_a7ddrphy_dq_i_data14[1]), + .Q8(soc_a7ddrphy_dq_i_data14[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_16 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay14), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed14) +); + +IOBUF IOBUF_14( + .I(soc_a7ddrphy_dq_o_nodelay14), + .T(soc_a7ddrphy_dq_t14), + .IO(ddram_dq[14]), + .O(soc_a7ddrphy_dq_i_nodelay14) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_45 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(soc_a7ddrphy_dfi_p0_wrdata[15]), + .D2(soc_a7ddrphy_dfi_p0_wrdata[31]), + .D3(soc_a7ddrphy_dfi_p1_wrdata[15]), + .D4(soc_a7ddrphy_dfi_p1_wrdata[31]), + .D5(soc_a7ddrphy_dfi_p2_wrdata[15]), + .D6(soc_a7ddrphy_dfi_p2_wrdata[31]), + .D7(soc_a7ddrphy_dfi_p3_wrdata[15]), + .D8(soc_a7ddrphy_dfi_p3_wrdata[31]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~soc_a7ddrphy_dq_oe_delayed)), + .TCE(1'd1), + .OQ(soc_a7ddrphy_dq_o_nodelay15), + .TQ(soc_a7ddrphy_dq_t15) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_15 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(soc_a7ddrphy_dq_i_delayed15), + .RST(sys_rst), + .Q1(soc_a7ddrphy_dq_i_data15[7]), + .Q2(soc_a7ddrphy_dq_i_data15[6]), + .Q3(soc_a7ddrphy_dq_i_data15[5]), + .Q4(soc_a7ddrphy_dq_i_data15[4]), + .Q5(soc_a7ddrphy_dq_i_data15[3]), + .Q6(soc_a7ddrphy_dq_i_data15[2]), + .Q7(soc_a7ddrphy_dq_i_data15[1]), + .Q8(soc_a7ddrphy_dq_i_data15[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_17 ( + .C(sys_clk), + .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(soc_a7ddrphy_dq_i_nodelay15), + .INC(1'd1), + .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(soc_a7ddrphy_dq_i_delayed15) +); + +IOBUF IOBUF_15( + .I(soc_a7ddrphy_dq_o_nodelay15), + .T(soc_a7ddrphy_dq_t15), + .IO(ddram_dq[15]), + .O(soc_a7ddrphy_dq_i_nodelay15) +); + +reg [24:0] storage_2[0:15]; +reg [24:0] memdat_5; +always @(posedge sys_clk) begin + if (soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we) + storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; + memdat_5 <= storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat_5; +assign soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr]; + +reg [24:0] storage_3[0:15]; +reg [24:0] memdat_6; +always @(posedge sys_clk) begin + if (soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we) + storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; + memdat_6 <= storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_6; +assign soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr]; + +reg [24:0] storage_4[0:15]; +reg [24:0] memdat_7; +always @(posedge sys_clk) begin + if (soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we) + storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; + memdat_7 <= storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_7; +assign soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr]; + +reg [24:0] storage_5[0:15]; +reg [24:0] memdat_8; +always @(posedge sys_clk) begin + if (soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we) + storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; + memdat_8 <= storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_8; +assign soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr]; + +reg [24:0] storage_6[0:15]; +reg [24:0] memdat_9; +always @(posedge sys_clk) begin + if (soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we) + storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; + memdat_9 <= storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_9; +assign soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr]; + +reg [24:0] storage_7[0:15]; +reg [24:0] memdat_10; +always @(posedge sys_clk) begin + if (soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we) + storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; + memdat_10 <= storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_10; +assign soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr]; + +reg [24:0] storage_8[0:15]; +reg [24:0] memdat_11; +always @(posedge sys_clk) begin + if (soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we) + storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; + memdat_11 <= storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_11; +assign soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr]; + +reg [24:0] storage_9[0:15]; +reg [24:0] memdat_12; +always @(posedge sys_clk) begin + if (soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we) + storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; + memdat_12 <= storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_12; +assign soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr]; + +VexRiscv VexRiscv( + .clk(sys_clk), + .dBusWishbone_ACK(soc_litedramcore_cpu_dbus_ack), + .dBusWishbone_DAT_MISO(soc_litedramcore_cpu_dbus_dat_r), + .dBusWishbone_ERR(soc_litedramcore_cpu_dbus_err), + .externalInterruptArray(soc_litedramcore_cpu_interrupt), + .externalResetVector(soc_litedramcore_vexriscv), + .iBusWishbone_ACK(soc_litedramcore_cpu_ibus_ack), + .iBusWishbone_DAT_MISO(soc_litedramcore_cpu_ibus_dat_r), + .iBusWishbone_ERR(soc_litedramcore_cpu_ibus_err), + .reset((sys_rst | soc_litedramcore_cpu_reset)), + .softwareInterrupt(1'd0), + .timerInterrupt(1'd0), + .dBusWishbone_ADR(soc_litedramcore_cpu_dbus_adr), + .dBusWishbone_BTE(soc_litedramcore_cpu_dbus_bte), + .dBusWishbone_CTI(soc_litedramcore_cpu_dbus_cti), + .dBusWishbone_CYC(soc_litedramcore_cpu_dbus_cyc), + .dBusWishbone_DAT_MOSI(soc_litedramcore_cpu_dbus_dat_w), + .dBusWishbone_SEL(soc_litedramcore_cpu_dbus_sel), + .dBusWishbone_STB(soc_litedramcore_cpu_dbus_stb), + .dBusWishbone_WE(soc_litedramcore_cpu_dbus_we), + .iBusWishbone_ADR(soc_litedramcore_cpu_ibus_adr), + .iBusWishbone_BTE(soc_litedramcore_cpu_ibus_bte), + .iBusWishbone_CTI(soc_litedramcore_cpu_ibus_cti), + .iBusWishbone_CYC(soc_litedramcore_cpu_ibus_cyc), + .iBusWishbone_DAT_MOSI(soc_litedramcore_cpu_ibus_dat_w), + .iBusWishbone_SEL(soc_litedramcore_cpu_ibus_sel), + .iBusWishbone_STB(soc_litedramcore_cpu_ibus_stb), + .iBusWishbone_WE(soc_litedramcore_cpu_ibus_we) +); + +PLLE2_ADV #( + .CLKFBOUT_MULT(5'd16), + .CLKIN1_PERIOD(10.0), + .CLKOUT0_DIVIDE(5'd16), + .CLKOUT0_PHASE(1'd0), + .CLKOUT1_DIVIDE(3'd4), + .CLKOUT1_PHASE(1'd0), + .CLKOUT2_DIVIDE(3'd4), + .CLKOUT2_PHASE(7'd90), + .DIVCLK_DIVIDE(1'd1), + .REF_JITTER1(0.01), + .STARTUP_WAIT("FALSE") +) PLLE2_ADV ( + .CLKFBIN(vns_pll_fb0), + .CLKIN1(soc_s7pll0_clkin), + .RST(soc_sys_pll_reset), + .CLKFBOUT(vns_pll_fb0), + .CLKOUT0(soc_s7pll0_clkout0), + .CLKOUT1(soc_s7pll0_clkout1), + .CLKOUT2(soc_s7pll0_clkout2), + .LOCKED(soc_sys_pll_locked) +); + +PLLE2_ADV #( + .CLKFBOUT_MULT(5'd16), + .CLKIN1_PERIOD(10.0), + .CLKOUT0_DIVIDE(4'd8), + .CLKOUT0_PHASE(1'd0), + .DIVCLK_DIVIDE(1'd1), + .REF_JITTER1(0.01), + .STARTUP_WAIT("FALSE") +) PLLE2_ADV_1 ( + .CLKFBIN(vns_pll_fb1), + .CLKIN1(soc_s7pll1_clkin), + .RST(soc_iodelay_pll_reset), + .CLKFBOUT(vns_pll_fb1), + .CLKOUT0(soc_s7pll1_clkout), + .LOCKED(soc_iodelay_pll_locked) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE ( + .C(sys_clk), + .CE(1'd1), + .D(1'd0), + .PRE(vns_xilinxasyncresetsynchronizerimpl0), + .Q(vns_xilinxasyncresetsynchronizerimpl0_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_1 ( + .C(sys_clk), + .CE(1'd1), + .D(vns_xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE(vns_xilinxasyncresetsynchronizerimpl0), + .Q(sys_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_2 ( + .C(sys4x_clk), + .CE(1'd1), + .D(1'd0), + .PRE(vns_xilinxasyncresetsynchronizerimpl1), + .Q(vns_xilinxasyncresetsynchronizerimpl1_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_3 ( + .C(sys4x_clk), + .CE(1'd1), + .D(vns_xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE(vns_xilinxasyncresetsynchronizerimpl1), + .Q(vns_xilinxasyncresetsynchronizerimpl1_expr) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_4 ( + .C(sys4x_dqs_clk), + .CE(1'd1), + .D(1'd0), + .PRE(vns_xilinxasyncresetsynchronizerimpl2), + .Q(vns_xilinxasyncresetsynchronizerimpl2_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_5 ( + .C(sys4x_dqs_clk), + .CE(1'd1), + .D(vns_xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE(vns_xilinxasyncresetsynchronizerimpl2), + .Q(vns_xilinxasyncresetsynchronizerimpl2_expr) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_6 ( + .C(iodelay_clk), + .CE(1'd1), + .D(1'd0), + .PRE(vns_xilinxasyncresetsynchronizerimpl3), + .Q(vns_xilinxasyncresetsynchronizerimpl3_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_7 ( + .C(iodelay_clk), + .CE(1'd1), + .D(vns_xilinxasyncresetsynchronizerimpl3_rst_meta), + .PRE(vns_xilinxasyncresetsynchronizerimpl3), + .Q(iodelay_rst) +); + +endmodule diff --git a/litedram/litedram.core b/litedram/litedram.core new file mode 100644 index 0000000..b2f7086 --- /dev/null +++ b/litedram/litedram.core @@ -0,0 +1,15 @@ +CAPI=2: + +name : :microwatt:litedram:0 + +generators: + litedram_gen: + interpreter: python3 + command: extras/fusesoc-add-files.py + description: Generate a litedram memory controller + usage: | + litedram_gen adds the pre-generated LiteX LiteDRAM memory controller + based on the board type. + + Parameters: + board: The board type (arty, nexys_video) diff --git a/microwatt.core b/microwatt.core index 0558470..23af8d7 100644 --- a/microwatt.core +++ b/microwatt.core @@ -87,6 +87,9 @@ filesets: - fpga/cmod_a7-35.xdc : {file_type : xdc} - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008} + litedram: + depend : [":microwatt:litedram"] + targets: nexys_a7: default_tool: vivado @@ -194,3 +197,9 @@ parameters: description : Prevent Vivado from flattening the main core components paramtype : generic default : false + + use_litedram: + datatype : bool + description : Use liteDRAM + paramtype : generic + default : false diff --git a/scripts/mw_debug/Makefile b/scripts/mw_debug/Makefile index 439b198..9920e71 100644 --- a/scripts/mw_debug/Makefile +++ b/scripts/mw_debug/Makefile @@ -5,3 +5,8 @@ all: mw_debug mw_debug: mw_debug.c $(CC) -o $@ $^ -lurjtag +clean: + rm -f mw_debug +distclean: + rm -f *~ + From 6853d22203501a35741ae40e320ac70896a4f0aa Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 7 May 2020 22:09:59 +1000 Subject: [PATCH 07/16] core: Add alternate reset address An external signal can control whether the core will start executing at the standard or the alternate reset address. This will be used when litedram is initialized by microwatt itself, to route the reset to the built-in init code secondary block RAM. Signed-off-by: Benjamin Herrenschmidt --- core.vhdl | 15 +++++++++++---- core_tb.vhdl | 3 ++- fetch1.vhdl | 10 ++++++++-- soc.vhdl | 7 +++++-- 4 files changed, 26 insertions(+), 9 deletions(-) diff --git a/core.vhdl b/core.vhdl index 0e60905..9895dc8 100644 --- a/core.vhdl +++ b/core.vhdl @@ -10,12 +10,17 @@ entity core is generic ( SIM : boolean := false; DISABLE_FLATTEN : boolean := false; - EX1_BYPASS : boolean := true + EX1_BYPASS : boolean := true; + ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0') ); port ( - clk : in std_logic; - rst : in std_logic; + clk : in std_ulogic; + rst : in std_ulogic; + -- Alternate reset (0xffff0000) for use by DRAM init fw + alt_reset : in std_ulogic; + + -- Wishbone interface wishbone_insn_in : in wishbone_slave_out; wishbone_insn_out : out wishbone_master_out; @@ -125,11 +130,13 @@ begin fetch1_0: entity work.fetch1 generic map ( - RESET_ADDRESS => (others => '0') + RESET_ADDRESS => (others => '0'), + ALT_RESET_ADDRESS => ALT_RESET_ADDRESS ) port map ( clk => clk, rst => core_rst, + alt_reset_in => alt_reset, stall_in => fetch1_stall_in, flush_in => flush, stop_in => dbg_core_stop, diff --git a/core_tb.vhdl b/core_tb.vhdl index 8597e06..8128993 100644 --- a/core_tb.vhdl +++ b/core_tb.vhdl @@ -27,7 +27,8 @@ begin rst => rst, system_clk => clk, uart0_rxd => '0', - uart0_txd => open + uart0_txd => open, + alt_reset => '0' ); clk_process: process diff --git a/fetch1.vhdl b/fetch1.vhdl index 9cd5445..301f317 100644 --- a/fetch1.vhdl +++ b/fetch1.vhdl @@ -7,7 +7,8 @@ use work.common.all; entity fetch1 is generic( - RESET_ADDRESS : std_logic_vector(63 downto 0) := (others => '0') + RESET_ADDRESS : std_logic_vector(63 downto 0) := (others => '0'); + ALT_RESET_ADDRESS : std_logic_vector(63 downto 0) := (others => '0') ); port( clk : in std_ulogic; @@ -17,6 +18,7 @@ entity fetch1 is stall_in : in std_ulogic; flush_in : in std_ulogic; stop_in : in std_ulogic; + alt_reset_in : in std_ulogic; -- redirect from execution unit e_in : in Execute1ToFetch1Type; @@ -60,7 +62,11 @@ begin v_int := r_int; if rst = '1' then - v.nia := RESET_ADDRESS; + if alt_reset_in = '1' then + v.nia := ALT_RESET_ADDRESS; + else + v.nia := RESET_ADDRESS; + end if; v_int.stop_state := RUNNING; elsif e_in.redirect = '1' then v.nia := e_in.redirect_nia; diff --git a/soc.vhdl b/soc.vhdl index 604c6d5..2318d0a 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -27,7 +27,8 @@ entity soc is -- UART0 signals: uart0_txd : out std_ulogic; - uart0_rxd : in std_ulogic + uart0_rxd : in std_ulogic; + alt_reset : in std_ulogic ); end entity soc; @@ -89,11 +90,13 @@ begin processor: entity work.core generic map( SIM => SIM, - DISABLE_FLATTEN => DISABLE_FLATTEN_CORE + DISABLE_FLATTEN => DISABLE_FLATTEN_CORE, + ALT_RESET_ADDRESS => (15 downto 0 => '0', others => '1') ) port map( clk => system_clk, rst => rst, + alt_reset => alt_reset, wishbone_insn_in => wishbone_icore_in, wishbone_insn_out => wishbone_icore_out, wishbone_data_in => wishbone_dcore_in, From 8bb3c8f8b6e71935cf9acceaa2139f6d68024975 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 10 Sep 2019 18:05:56 +0100 Subject: [PATCH 08/16] soc: Add DRAM address decoding Still not attached to any board Signed-off-by: Benjamin Herrenschmidt --- core_tb.vhdl | 12 +++++++ fpga/toplevel.vhdl | 9 +++++ soc.vhdl | 83 ++++++++++++++++++++++++++++++++++------------ 3 files changed, 83 insertions(+), 21 deletions(-) diff --git a/core_tb.vhdl b/core_tb.vhdl index 8128993..c473de3 100644 --- a/core_tb.vhdl +++ b/core_tb.vhdl @@ -14,6 +14,10 @@ architecture behave of core_tb is -- testbench signals constant clk_period : time := 10 ns; + + -- Dummy DRAM + signal wb_dram_in : wishbone_master_out; + signal wb_dram_out : wishbone_slave_out; begin soc0: entity work.soc @@ -28,6 +32,8 @@ begin system_clk => clk, uart0_rxd => '0', uart0_txd => open, + wb_dram_in => wb_dram_in, + wb_dram_out => wb_dram_out, alt_reset => '0' ); @@ -48,4 +54,10 @@ begin end process; jtag: entity work.sim_jtag; + + -- Dummy DRAM + wb_dram_out.ack <= wb_dram_in.cyc and wb_dram_in.stb; + wb_dram_out.dat <= x"FFFFFFFFFFFFFFFF"; + wb_dram_out.stall <= wb_dram_in.cyc and not wb_dram_out.ack; + end; diff --git a/fpga/toplevel.vhdl b/fpga/toplevel.vhdl index a3b8282..c0f1920 100644 --- a/fpga/toplevel.vhdl +++ b/fpga/toplevel.vhdl @@ -30,6 +30,10 @@ architecture behaviour of toplevel is signal system_clk : std_ulogic; signal system_clk_locked : std_ulogic; + -- Dummy DRAM + signal wb_dram_in : wishbone_master_out; + signal wb_dram_out : wishbone_slave_out; + begin reset_controller: entity work.soc_reset @@ -73,4 +77,9 @@ begin uart0_rxd => uart0_rxd ); + -- Dummy DRAM + wb_dram_out.ack <= wb_dram_in.cyc and wb_dram_in.stb; + wb_dram_out.dat <= x"FFFFFFFFFFFFFFFF"; + wb_dram_out.stall <= wb_dram_in.cyc and not wb_dram_out.ack; + end architecture behaviour; diff --git a/soc.vhdl b/soc.vhdl index 2318d0a..53fa2f1 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -10,24 +10,39 @@ use work.common.all; use work.wishbone_types.all; --- 0x00000000: Main memory (1 MB) --- 0xc0002000: UART0 (for host communication) +-- Memory map: +-- +-- 0x00000000: Block RAM +-- 0x40000000: DRAM (when present) +-- 0xc0002000: UART0 -- 0xc0004000: XICS ICP +-- 0xf0000000: Block RAM (aliased & repeated) +-- 0xffff0000: DRAM init code (if any) + entity soc is generic ( MEMORY_SIZE : positive; RAM_INIT_FILE : string; RESET_LOW : boolean; SIM : boolean; - DISABLE_FLATTEN_CORE : boolean := false + DISABLE_FLATTEN_CORE : boolean := false; + HAS_DRAM : boolean := false ); port( rst : in std_ulogic; system_clk : in std_ulogic; + -- DRAM controller signals + wb_dram_in : out wishbone_master_out; + wb_dram_out : in wishbone_slave_out; + wb_dram_csr : out std_ulogic; + wb_dram_init : out std_ulogic; + -- UART0 signals: uart0_txd : out std_ulogic; uart0_rxd : in std_ulogic; + + -- DRAM controller signals alt_reset : in std_ulogic ); end entity soc; @@ -35,9 +50,9 @@ end entity soc; architecture behaviour of soc is -- Wishbone master signals: - signal wishbone_dcore_in : wishbone_slave_out; + signal wishbone_dcore_in : wishbone_slave_out; signal wishbone_dcore_out : wishbone_master_out; - signal wishbone_icore_in : wishbone_slave_out; + signal wishbone_icore_in : wishbone_slave_out; signal wishbone_icore_out : wishbone_master_out; signal wishbone_debug_in : wishbone_slave_out; signal wishbone_debug_out : wishbone_master_out; @@ -49,8 +64,8 @@ architecture behaviour of soc is signal wb_masters_in : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1); -- Wishbone master (output of arbiter): - signal wb_master_in : wishbone_slave_out; - signal wb_master_out : wishbone_master_out; + signal wb_master_in : wishbone_slave_out; + signal wb_master_out : wishbone_master_out; -- UART0 signals: signal wb_uart0_in : wishbone_master_out; @@ -130,25 +145,35 @@ begin ); -- Wishbone slaves address decoder & mux - slave_intercon: process(wb_master_out, wb_bram_out, wb_uart0_out) + slave_intercon: process(wb_master_out, wb_bram_out, wb_uart0_out, wb_dram_out) -- Selected slave - type slave_type is (SLAVE_UART_0, - SLAVE_MEMORY, + type slave_type is (SLAVE_UART, + SLAVE_BRAM, + SLAVE_DRAM, + SLAVE_DRAM_INIT, + SLAVE_DRAM_CSR, SLAVE_ICP_0, SLAVE_NONE); variable slave : slave_type; begin -- Simple address decoder. slave := SLAVE_NONE; - if wb_master_out.adr(31 downto 24) = x"00" then - slave := SLAVE_MEMORY; - elsif wb_master_out.adr(31 downto 24) = x"c0" then - if wb_master_out.adr(23 downto 12) = x"002" then - slave := SLAVE_UART_0; - end if; - if wb_master_out.adr(23 downto 12) = x"004" then - slave := SLAVE_ICP_0; - end if; + -- Simple address decoder. Ignore top bits to save silicon for now + slave := SLAVE_NONE; + if std_match(wb_master_out.adr, x"0-------") then + slave := SLAVE_BRAM; + elsif std_match(wb_master_out.adr, x"FFFF----") then + slave := SLAVE_DRAM_INIT; + elsif std_match(wb_master_out.adr, x"F-------") then + slave := SLAVE_BRAM; + elsif std_match(wb_master_out.adr, x"4-------") and HAS_DRAM then + slave := SLAVE_DRAM; + elsif std_match(wb_master_out.adr, x"C0002---") then + slave := SLAVE_UART; + elsif std_match(wb_master_out.adr, x"C01-----") then + slave := SLAVE_DRAM_CSR; + elsif std_match(wb_master_out.adr, x"C0004---") then + slave := SLAVE_ICP_0; end if; -- Wishbone muxing. Defaults: @@ -162,11 +187,27 @@ begin wb_xics0_in.adr <= (others => '0'); wb_xics0_in.adr(7 downto 0) <= wb_master_out.adr(7 downto 0); wb_xics0_in.cyc <= '0'; + + wb_dram_in <= wb_master_out; + wb_dram_in.cyc <= '0'; + wb_dram_csr <= '0'; + wb_dram_init <= '0'; case slave is - when SLAVE_MEMORY => + when SLAVE_BRAM => wb_bram_in.cyc <= wb_master_out.cyc; wb_master_in <= wb_bram_out; - when SLAVE_UART_0 => + when SLAVE_DRAM => + wb_dram_in.cyc <= wb_master_out.cyc; + wb_master_in <= wb_dram_out; + when SLAVE_DRAM_INIT => + wb_dram_in.cyc <= wb_master_out.cyc; + wb_master_in <= wb_dram_out; + wb_dram_init <= '1'; + when SLAVE_DRAM_CSR => + wb_dram_in.cyc <= wb_master_out.cyc; + wb_master_in <= wb_dram_out; + wb_dram_csr <= '1'; + when SLAVE_UART => wb_uart0_in.cyc <= wb_master_out.cyc; wb_master_in <= wb_uart0_out; when SLAVE_ICP_0 => From 3ac815823c1f9312193a6144ca71bbe824d90fc1 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 10 Sep 2019 18:24:06 +0100 Subject: [PATCH 09/16] fpga: Hookup Arty to litedram The old toplevel.vhdl becomes top-generic.vhdl, which is to be used by platforms that do not have a litedram option. Arty has its own top-arty.vhdl which supports litedram and is now hooked up Signed-off-by: Benjamin Herrenschmidt --- fpga/arty_a7.xdc | 233 +++++++++++++++++++++- fpga/top-arty.vhdl | 244 +++++++++++++++++++++++ fpga/{toplevel.vhdl => top-generic.vhdl} | 0 microwatt.core | 40 +++- 4 files changed, 510 insertions(+), 7 deletions(-) create mode 100644 fpga/top-arty.vhdl rename fpga/{toplevel.vhdl => top-generic.vhdl} (100%) diff --git a/fpga/arty_a7.xdc b/fpga/arty_a7.xdc index a635211..9bd0226 100644 --- a/fpga/arty_a7.xdc +++ b/fpga/arty_a7.xdc @@ -1,10 +1,235 @@ -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { ext_clk }]; +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { ext_clk }]; create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { ext_clk }]; -set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ext_rst }]; +set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ext_rst }]; -set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart0_txd }]; -set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd }]; +set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart_main_tx }]; +set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart_main_rx }]; + +##Pmod Header JC: UART (bottom) + +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_cts_n }]; +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_tx }]; +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rx }]; +set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rts_n }]; + +# LEDs +set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; +set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; +set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; + +# DRAM (generated by LiteX) + ## ddram:0.a +set_property LOC R2 [get_ports ddram_a[0]] +set_property SLEW FAST [get_ports ddram_a[0]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[0]] + ## ddram:0.a +set_property LOC M6 [get_ports ddram_a[1]] +set_property SLEW FAST [get_ports ddram_a[1]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[1]] + ## ddram:0.a +set_property LOC N4 [get_ports ddram_a[2]] +set_property SLEW FAST [get_ports ddram_a[2]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[2]] + ## ddram:0.a +set_property LOC T1 [get_ports ddram_a[3]] +set_property SLEW FAST [get_ports ddram_a[3]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[3]] + ## ddram:0.a +set_property LOC N6 [get_ports ddram_a[4]] +set_property SLEW FAST [get_ports ddram_a[4]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[4]] + ## ddram:0.a +set_property LOC R7 [get_ports ddram_a[5]] +set_property SLEW FAST [get_ports ddram_a[5]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[5]] + ## ddram:0.a +set_property LOC V6 [get_ports ddram_a[6]] +set_property SLEW FAST [get_ports ddram_a[6]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[6]] + ## ddram:0.a +set_property LOC U7 [get_ports ddram_a[7]] +set_property SLEW FAST [get_ports ddram_a[7]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[7]] + ## ddram:0.a +set_property LOC R8 [get_ports ddram_a[8]] +set_property SLEW FAST [get_ports ddram_a[8]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[8]] + ## ddram:0.a +set_property LOC V7 [get_ports ddram_a[9]] +set_property SLEW FAST [get_ports ddram_a[9]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[9]] + ## ddram:0.a +set_property LOC R6 [get_ports ddram_a[10]] +set_property SLEW FAST [get_ports ddram_a[10]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[10]] + ## ddram:0.a +set_property LOC U6 [get_ports ddram_a[11]] +set_property SLEW FAST [get_ports ddram_a[11]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[11]] + ## ddram:0.a +set_property LOC T6 [get_ports ddram_a[12]] +set_property SLEW FAST [get_ports ddram_a[12]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[12]] + ## ddram:0.a +set_property LOC T8 [get_ports ddram_a[13]] +set_property SLEW FAST [get_ports ddram_a[13]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[13]] + ## ddram:0.ba +set_property LOC R1 [get_ports ddram_ba[0]] +set_property SLEW FAST [get_ports ddram_ba[0]] +set_property IOSTANDARD SSTL135 [get_ports ddram_ba[0]] + ## ddram:0.ba +set_property LOC P4 [get_ports ddram_ba[1]] +set_property SLEW FAST [get_ports ddram_ba[1]] +set_property IOSTANDARD SSTL135 [get_ports ddram_ba[1]] + ## ddram:0.ba +set_property LOC P2 [get_ports ddram_ba[2]] +set_property SLEW FAST [get_ports ddram_ba[2]] +set_property IOSTANDARD SSTL135 [get_ports ddram_ba[2]] + ## ddram:0.ras_n +set_property LOC P3 [get_ports ddram_ras_n] +set_property SLEW FAST [get_ports ddram_ras_n] +set_property IOSTANDARD SSTL135 [get_ports ddram_ras_n] + ## ddram:0.cas_n +set_property LOC M4 [get_ports ddram_cas_n] +set_property SLEW FAST [get_ports ddram_cas_n] +set_property IOSTANDARD SSTL135 [get_ports ddram_cas_n] + ## ddram:0.we_n +set_property LOC P5 [get_ports ddram_we_n] +set_property SLEW FAST [get_ports ddram_we_n] +set_property IOSTANDARD SSTL135 [get_ports ddram_we_n] + ## ddram:0.cs_n +set_property LOC U8 [get_ports ddram_cs_n] +set_property SLEW FAST [get_ports ddram_cs_n] +set_property IOSTANDARD SSTL135 [get_ports ddram_cs_n] + ## ddram:0.dm +set_property LOC L1 [get_ports ddram_dm[0]] +set_property SLEW FAST [get_ports ddram_dm[0]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dm[0]] + ## ddram:0.dm +set_property LOC U1 [get_ports ddram_dm[1]] +set_property SLEW FAST [get_ports ddram_dm[1]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dm[1]] + ## ddram:0.dq +set_property LOC K5 [get_ports ddram_dq[0]] +set_property SLEW FAST [get_ports ddram_dq[0]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[0]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[0]] + ## ddram:0.dq +set_property LOC L3 [get_ports ddram_dq[1]] +set_property SLEW FAST [get_ports ddram_dq[1]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[1]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[1]] + ## ddram:0.dq +set_property LOC K3 [get_ports ddram_dq[2]] +set_property SLEW FAST [get_ports ddram_dq[2]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[2]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[2]] + ## ddram:0.dq +set_property LOC L6 [get_ports ddram_dq[3]] +set_property SLEW FAST [get_ports ddram_dq[3]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[3]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[3]] + ## ddram:0.dq +set_property LOC M3 [get_ports ddram_dq[4]] +set_property SLEW FAST [get_ports ddram_dq[4]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[4]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[4]] + ## ddram:0.dq +set_property LOC M1 [get_ports ddram_dq[5]] +set_property SLEW FAST [get_ports ddram_dq[5]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[5]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[5]] + ## ddram:0.dq +set_property LOC L4 [get_ports ddram_dq[6]] +set_property SLEW FAST [get_ports ddram_dq[6]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[6]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[6]] + ## ddram:0.dq +set_property LOC M2 [get_ports ddram_dq[7]] +set_property SLEW FAST [get_ports ddram_dq[7]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[7]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[7]] + ## ddram:0.dq +set_property LOC V4 [get_ports ddram_dq[8]] +set_property SLEW FAST [get_ports ddram_dq[8]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[8]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[8]] + ## ddram:0.dq +set_property LOC T5 [get_ports ddram_dq[9]] +set_property SLEW FAST [get_ports ddram_dq[9]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[9]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[9]] + ## ddram:0.dq +set_property LOC U4 [get_ports ddram_dq[10]] +set_property SLEW FAST [get_ports ddram_dq[10]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[10]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[10]] + ## ddram:0.dq +set_property LOC V5 [get_ports ddram_dq[11]] +set_property SLEW FAST [get_ports ddram_dq[11]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[11]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[11]] + ## ddram:0.dq +set_property LOC V1 [get_ports ddram_dq[12]] +set_property SLEW FAST [get_ports ddram_dq[12]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[12]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[12]] + ## ddram:0.dq +set_property LOC T3 [get_ports ddram_dq[13]] +set_property SLEW FAST [get_ports ddram_dq[13]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[13]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[13]] + ## ddram:0.dq +set_property LOC U3 [get_ports ddram_dq[14]] +set_property SLEW FAST [get_ports ddram_dq[14]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[14]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[14]] + ## ddram:0.dq +set_property LOC R3 [get_ports ddram_dq[15]] +set_property SLEW FAST [get_ports ddram_dq[15]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[15]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[15]] + ## ddram:0.dqs_p +set_property LOC N2 [get_ports ddram_dqs_p[0]] +set_property SLEW FAST [get_ports ddram_dqs_p[0]] +set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[0]] + ## ddram:0.dqs_p +set_property LOC U2 [get_ports ddram_dqs_p[1]] +set_property SLEW FAST [get_ports ddram_dqs_p[1]] +set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[1]] + ## ddram:0.dqs_n +set_property LOC N1 [get_ports ddram_dqs_n[0]] +set_property SLEW FAST [get_ports ddram_dqs_n[0]] +set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[0]] + ## ddram:0.dqs_n +set_property LOC V2 [get_ports ddram_dqs_n[1]] +set_property SLEW FAST [get_ports ddram_dqs_n[1]] +set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[1]] + ## ddram:0.clk_p +set_property LOC U9 [get_ports ddram_clk_p] +set_property SLEW FAST [get_ports ddram_clk_p] +set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_p] + ## ddram:0.clk_n +set_property LOC V9 [get_ports ddram_clk_n] +set_property SLEW FAST [get_ports ddram_clk_n] +set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_n] + ## ddram:0.cke +set_property LOC N5 [get_ports ddram_cke] +set_property SLEW FAST [get_ports ddram_cke] +set_property IOSTANDARD SSTL135 [get_ports ddram_cke] + ## ddram:0.odt +set_property LOC R5 [get_ports ddram_odt] +set_property SLEW FAST [get_ports ddram_odt] +set_property IOSTANDARD SSTL135 [get_ports ddram_odt] + ## ddram:0.reset_n +set_property LOC K6 [get_ports ddram_reset_n] +set_property SLEW FAST [get_ports ddram_reset_n] +set_property IOSTANDARD SSTL135 [get_ports ddram_reset_n] + +#Internal VREF +set_property INTERNAL_VREF 0.675 [get_iobanks 34] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl new file mode 100644 index 0000000..a458c04 --- /dev/null +++ b/fpga/top-arty.vhdl @@ -0,0 +1,244 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.all; + +library work; +use work.wishbone_types.all; + +entity toplevel is + generic ( + MEMORY_SIZE : positive := 16384; + RAM_INIT_FILE : string := "firmware.hex"; + RESET_LOW : boolean := true; + CLK_FREQUENCY : positive := 100000000; + USE_LITEDRAM : boolean := false; + DISABLE_FLATTEN_CORE : boolean := false + ); + port( + ext_clk : in std_ulogic; + ext_rst : in std_ulogic; + + -- UART0 signals: + uart_main_tx : out std_ulogic; + uart_main_rx : in std_ulogic; + + -- DRAM UART signals (PMOD) + uart_pmod_tx : out std_ulogic; + uart_pmod_rx : in std_ulogic; + uart_pmod_cts_n : in std_ulogic; + uart_pmod_rts_n : out std_ulogic; + + -- LEDs + led0_b : out std_ulogic; + led0_g : out std_ulogic; + led0_r : out std_ulogic; + + -- DRAM wires + ddram_a : out std_ulogic_vector(13 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic + ); +end entity toplevel; + +architecture behaviour of toplevel is + + -- Reset signals: + signal soc_rst : std_ulogic; + signal pll_rst : std_ulogic; + + -- Internal clock signals: + signal system_clk : std_ulogic; + signal system_clk_locked : std_ulogic; + + -- DRAM wishbone connection + signal wb_dram_in : wishbone_master_out; + signal wb_dram_out : wishbone_slave_out; + signal wb_dram_csr : std_ulogic; + signal wb_dram_init : std_ulogic; + + -- Control/status + signal core_alt_reset : std_ulogic; + + -- Status LED + signal led0_b_pwm : std_ulogic; + signal led0_r_pwm : std_ulogic; + signal led0_g_pwm : std_ulogic; + + -- Dumb PWM for the LEDs, those RGB LEDs are too bright otherwise + signal pwm_counter : std_ulogic_vector(8 downto 0); +begin + + uart_pmod_rts_n <= '0'; + + -- Main SoC + soc0: entity work.soc + generic map( + MEMORY_SIZE => MEMORY_SIZE, + RAM_INIT_FILE => RAM_INIT_FILE, + RESET_LOW => RESET_LOW, + SIM => false, + HAS_DRAM => USE_LITEDRAM, + DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE + ) + port map ( + system_clk => system_clk, + rst => soc_rst, + uart0_txd => uart_main_tx, + uart0_rxd => uart_main_rx, + wb_dram_in => wb_dram_in, + wb_dram_out => wb_dram_out, + wb_dram_csr => wb_dram_csr, + wb_dram_init => wb_dram_init, + alt_reset => core_alt_reset + ); + + nodram: if not USE_LITEDRAM generate + signal ddram_clk_dummy : std_ulogic; + begin + reset_controller: entity work.soc_reset + generic map( + RESET_LOW => RESET_LOW + ) + port map( + ext_clk => ext_clk, + pll_clk => system_clk, + pll_locked_in => system_clk_locked, + ext_rst_in => ext_rst, + pll_rst_out => pll_rst, + rst_out => soc_rst + ); + + clkgen: entity work.clock_generator + generic map( + CLK_INPUT_HZ => 100000000, + CLK_OUTPUT_HZ => CLK_FREQUENCY + ) + port map( + ext_clk => ext_clk, + pll_rst_in => pll_rst, + pll_clk_out => system_clk, + pll_locked_out => system_clk_locked + ); + + led0_b_pwm <= '1'; + led0_r_pwm <= '1'; + led0_g_pwm <= '0'; + core_alt_reset <= '0'; + + -- Vivado barfs on those differential signals if left + -- unconnected. So instanciate a diff. buffer and feed + -- it a constant '0'. + dummy_dram_clk: OBUFDS + port map ( + O => ddram_clk_p, + OB => ddram_clk_n, + I => ddram_clk_dummy + ); + ddram_clk_dummy <= '0'; + + end generate; + + has_dram: if USE_LITEDRAM generate + signal dram_init_done : std_ulogic; + signal dram_init_error : std_ulogic; + signal soc_rst_0 : std_ulogic; + signal soc_rst_1 : std_ulogic; + begin + + -- Eventually dig out the frequency from the generator + -- but for now, assert it's 100Mhz + assert CLK_FREQUENCY = 100000000; + + reset_controller: entity work.soc_reset + generic map( + RESET_LOW => RESET_LOW + ) + port map( + ext_clk => ext_clk, + pll_clk => system_clk, + pll_locked_in => system_clk_locked, + ext_rst_in => ext_rst, + pll_rst_out => pll_rst, + rst_out => soc_rst_0 + ); + + dram: entity work.litedram_wrapper + generic map( + DRAM_ABITS => 24, + DRAM_ALINES => 14 + ) + port map( + clk_in => ext_clk, + rst => pll_rst, + system_clk => system_clk, + system_reset => soc_rst_1, + core_alt_reset => core_alt_reset, + pll_locked => system_clk_locked, + + wb_in => wb_dram_in, + wb_out => wb_dram_out, + wb_is_csr => wb_dram_csr, + wb_is_init => wb_dram_init, + + serial_tx => uart_pmod_tx, + serial_rx => uart_pmod_rx, + + init_done => dram_init_done, + init_error => dram_init_error, + + ddram_a => ddram_a, + ddram_ba => ddram_ba, + ddram_ras_n => ddram_ras_n, + ddram_cas_n => ddram_cas_n, + ddram_we_n => ddram_we_n, + ddram_cs_n => ddram_cs_n, + ddram_dm => ddram_dm, + ddram_dq => ddram_dq, + ddram_dqs_p => ddram_dqs_p, + ddram_dqs_n => ddram_dqs_n, + ddram_clk_p => ddram_clk_p, + ddram_clk_n => ddram_clk_n, + ddram_cke => ddram_cke, + ddram_odt => ddram_odt, + ddram_reset_n => ddram_reset_n + ); + + led0_b_pwm <= not dram_init_done; + led0_r_pwm <= dram_init_error; + led0_g_pwm <= dram_init_done and not dram_init_error; + soc_rst <= soc_rst_0 or soc_rst_1; + + end generate; + + leds_pwm : process(system_clk) + begin + if rising_edge(system_clk) then + pwm_counter <= std_ulogic_vector(signed(pwm_counter) + 1); + if pwm_counter(8 downto 4) = "00000" then + led0_b <= led0_b_pwm; + led0_r <= led0_r_pwm; + led0_g <= led0_g_pwm; + else + led0_b <= '0'; + led0_r <= '0'; + led0_g <= '0'; + end if; + end if; + end process; + +end architecture behaviour; diff --git a/fpga/toplevel.vhdl b/fpga/top-generic.vhdl similarity index 100% rename from fpga/toplevel.vhdl rename to fpga/top-generic.vhdl diff --git a/microwatt.core b/microwatt.core index 23af8d7..9e60792 100644 --- a/microwatt.core +++ b/microwatt.core @@ -55,7 +55,6 @@ filesets: - fpga/pp_fifo.vhd - fpga/pp_soc_uart.vhd - fpga/pp_utilities.vhd - - fpga/toplevel.vhdl - fpga/firmware.hex : {copyto : firmware.hex, file_type : user} file_type : vhdlSource-2008 @@ -71,21 +70,25 @@ filesets: files: - fpga/nexys_a7.xdc : {file_type : xdc} - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008} + - fpga/top-generic.vhdl : {file_type : vhdlSource-2008} nexys_video: files: - fpga/nexys-video.xdc : {file_type : xdc} - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008} + - fpga/top-generic.vhdl : {file_type : vhdlSource-2008} arty_a7: files: - fpga/arty_a7.xdc : {file_type : xdc} - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008} + - fpga/top-arty.vhdl : {file_type : vhdlSource-2008} cmod_a7-35: files: - fpga/cmod_a7-35.xdc : {file_type : xdc} - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008} + - fpga/top-generic.vhdl : {file_type : vhdlSource-2008} litedram: depend : [":microwatt:litedram"] @@ -117,7 +120,7 @@ targets: vivado: {part : xc7a200tsbg484-1} toplevel : toplevel - arty_a7-35: + arty_a7-35-nodram: default_tool: vivado filesets: [core, arty_a7, soc, fpga, debug_xilinx] parameters : @@ -130,7 +133,20 @@ targets: vivado: {part : xc7a35ticsg324-1L} toplevel : toplevel - arty_a7-100: + arty_a7-35: + default_tool: vivado + filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram] + parameters : + - memory_size + - ram_init_file + - use_litedram=true + - disable_flatten_core + generate: [dram_arty] + tools: + vivado: {part : xc7a35ticsg324-1L} + toplevel : toplevel + + arty_a7-100-nodram: default_tool: vivado filesets: [core, arty_a7, soc, fpga, debug_xilinx] parameters : @@ -143,6 +159,19 @@ targets: vivado: {part : xc7a100ticsg324-1L} toplevel : toplevel + arty_a7-100: + default_tool: vivado + filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram] + parameters: + - memory_size + - ram_init_file + - use_litedram=true + - disable_flatten_core + generate: [dram_arty] + tools: + vivado: {part : xc7a100ticsg324-1L} + toplevel : toplevel + cmod_a7-35: default_tool: vivado filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx] @@ -163,6 +192,11 @@ targets: vivado: {pnr : none} toplevel: core +generate: + dram_arty: + generator: litedram_gen + parameters: {board : arty} + parameters: memory_size: datatype : int From 2cef3005cd6eb1e6f4ca069ee5d797959b46c381 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 11 Sep 2019 10:59:13 +0100 Subject: [PATCH 10/16] fpga: Hookup nexys-video to litedram Signed-off-by: Benjamin Herrenschmidt --- fpga/nexys-video.xdc | 228 +++++++++++++++++++++++++++++++++++++- fpga/top-nexys-video.vhdl | 207 ++++++++++++++++++++++++++++++++++ microwatt.core | 21 +++- 3 files changed, 452 insertions(+), 4 deletions(-) create mode 100644 fpga/top-nexys-video.vhdl diff --git a/fpga/nexys-video.xdc b/fpga/nexys-video.xdc index 239376f..aa840c7 100644 --- a/fpga/nexys-video.xdc +++ b/fpga/nexys-video.xdc @@ -3,8 +3,232 @@ create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports ext_rst] -set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports uart0_txd] -set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports uart0_rxd] +set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports uart_main_tx] +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports uart_main_rx] + +##Pmod Header JA: UART (bottom) + +set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_cts_n }]; +set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_tx }]; +set_property -dict { PACKAGE_PIN AA20 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rx }]; +set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rts_n }]; + +# LEDs (no colors, just normal LEDs here) +set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { led0 }]; +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led1 }]; + +# DRAM (generated by LiteX) + ## ddram:0.a +set_property LOC M2 [get_ports ddram_a[0]] +set_property SLEW FAST [get_ports ddram_a[0]] +set_property IOSTANDARD SSTL15 [get_ports ddram_a[0]] + ## ddram:0.a +set_property LOC M5 [get_ports ddram_a[1]] +set_property SLEW FAST [get_ports ddram_a[1]] +set_property IOSTANDARD SSTL15 [get_ports ddram_a[1]] + ## ddram:0.a +set_property LOC M3 [get_ports ddram_a[2]] +set_property SLEW FAST [get_ports ddram_a[2]] +set_property IOSTANDARD SSTL15 [get_ports ddram_a[2]] + ## ddram:0.a +set_property LOC M1 [get_ports ddram_a[3]] +set_property SLEW FAST [get_ports ddram_a[3]] +set_property IOSTANDARD SSTL15 [get_ports ddram_a[3]] + ## ddram:0.a +set_property LOC L6 [get_ports ddram_a[4]] +set_property SLEW FAST [get_ports ddram_a[4]] +set_property IOSTANDARD SSTL15 [get_ports ddram_a[4]] + ## ddram:0.a +set_property LOC P1 [get_ports ddram_a[5]] +set_property SLEW FAST [get_ports ddram_a[5]] +set_property IOSTANDARD SSTL15 [get_ports ddram_a[5]] + ## ddram:0.a +set_property LOC N3 [get_ports ddram_a[6]] +set_property SLEW FAST [get_ports ddram_a[6]] +set_property IOSTANDARD SSTL15 [get_ports ddram_a[6]] + ## ddram:0.a +set_property LOC N2 [get_ports ddram_a[7]] +set_property SLEW FAST [get_ports ddram_a[7]] +set_property IOSTANDARD SSTL15 [get_ports ddram_a[7]] + ## ddram:0.a +set_property LOC M6 [get_ports ddram_a[8]] +set_property SLEW FAST [get_ports ddram_a[8]] +set_property IOSTANDARD SSTL15 [get_ports ddram_a[8]] + ## ddram:0.a +set_property LOC R1 [get_ports ddram_a[9]] +set_property SLEW FAST [get_ports ddram_a[9]] +set_property IOSTANDARD SSTL15 [get_ports ddram_a[9]] + ## ddram:0.a +set_property LOC L5 [get_ports ddram_a[10]] +set_property SLEW FAST [get_ports ddram_a[10]] +set_property IOSTANDARD SSTL15 [get_ports ddram_a[10]] + ## ddram:0.a +set_property LOC N5 [get_ports ddram_a[11]] +set_property SLEW FAST [get_ports ddram_a[11]] +set_property IOSTANDARD SSTL15 [get_ports ddram_a[11]] + ## ddram:0.a +set_property LOC N4 [get_ports ddram_a[12]] +set_property SLEW FAST [get_ports ddram_a[12]] +set_property IOSTANDARD SSTL15 [get_ports ddram_a[12]] + ## ddram:0.a +set_property LOC P2 [get_ports ddram_a[13]] +set_property SLEW FAST [get_ports ddram_a[13]] +set_property IOSTANDARD SSTL15 [get_ports ddram_a[13]] + ## ddram:0.a +set_property LOC P6 [get_ports ddram_a[14]] +set_property SLEW FAST [get_ports ddram_a[14]] +set_property IOSTANDARD SSTL15 [get_ports ddram_a[14]] + ## ddram:0.ba +set_property LOC L3 [get_ports ddram_ba[0]] +set_property SLEW FAST [get_ports ddram_ba[0]] +set_property IOSTANDARD SSTL15 [get_ports ddram_ba[0]] + ## ddram:0.ba +set_property LOC K6 [get_ports ddram_ba[1]] +set_property SLEW FAST [get_ports ddram_ba[1]] +set_property IOSTANDARD SSTL15 [get_ports ddram_ba[1]] + ## ddram:0.ba +set_property LOC L4 [get_ports ddram_ba[2]] +set_property SLEW FAST [get_ports ddram_ba[2]] +set_property IOSTANDARD SSTL15 [get_ports ddram_ba[2]] + ## ddram:0.ras_n +set_property LOC J4 [get_ports ddram_ras_n] +set_property SLEW FAST [get_ports ddram_ras_n] +set_property IOSTANDARD SSTL15 [get_ports ddram_ras_n] + ## ddram:0.cas_n +set_property LOC K3 [get_ports ddram_cas_n] +set_property SLEW FAST [get_ports ddram_cas_n] +set_property IOSTANDARD SSTL15 [get_ports ddram_cas_n] + ## ddram:0.we_n +set_property LOC L1 [get_ports ddram_we_n] +set_property SLEW FAST [get_ports ddram_we_n] +set_property IOSTANDARD SSTL15 [get_ports ddram_we_n] + ## ddram:0.dm +set_property LOC G3 [get_ports ddram_dm[0]] +set_property SLEW FAST [get_ports ddram_dm[0]] +set_property IOSTANDARD SSTL15 [get_ports ddram_dm[0]] + ## ddram:0.dm +set_property LOC F1 [get_ports ddram_dm[1]] +set_property SLEW FAST [get_ports ddram_dm[1]] +set_property IOSTANDARD SSTL15 [get_ports ddram_dm[1]] + ## ddram:0.dq +set_property LOC G2 [get_ports ddram_dq[0]] +set_property SLEW FAST [get_ports ddram_dq[0]] +set_property IOSTANDARD SSTL15 [get_ports ddram_dq[0]] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[0]] + ## ddram:0.dq +set_property LOC H4 [get_ports ddram_dq[1]] +set_property SLEW FAST [get_ports ddram_dq[1]] +set_property IOSTANDARD SSTL15 [get_ports ddram_dq[1]] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[1]] + ## ddram:0.dq +set_property LOC H5 [get_ports ddram_dq[2]] +set_property SLEW FAST [get_ports ddram_dq[2]] +set_property IOSTANDARD SSTL15 [get_ports ddram_dq[2]] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[2]] + ## ddram:0.dq +set_property LOC J1 [get_ports ddram_dq[3]] +set_property SLEW FAST [get_ports ddram_dq[3]] +set_property IOSTANDARD SSTL15 [get_ports ddram_dq[3]] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[3]] + ## ddram:0.dq +set_property LOC K1 [get_ports ddram_dq[4]] +set_property SLEW FAST [get_ports ddram_dq[4]] +set_property IOSTANDARD SSTL15 [get_ports ddram_dq[4]] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[4]] + ## ddram:0.dq +set_property LOC H3 [get_ports ddram_dq[5]] +set_property SLEW FAST [get_ports ddram_dq[5]] +set_property IOSTANDARD SSTL15 [get_ports ddram_dq[5]] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[5]] + ## ddram:0.dq +set_property LOC H2 [get_ports ddram_dq[6]] +set_property SLEW FAST [get_ports ddram_dq[6]] +set_property IOSTANDARD SSTL15 [get_ports ddram_dq[6]] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[6]] + ## ddram:0.dq +set_property LOC J5 [get_ports ddram_dq[7]] +set_property SLEW FAST [get_ports ddram_dq[7]] +set_property IOSTANDARD SSTL15 [get_ports ddram_dq[7]] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[7]] + ## ddram:0.dq +set_property LOC E3 [get_ports ddram_dq[8]] +set_property SLEW FAST [get_ports ddram_dq[8]] +set_property IOSTANDARD SSTL15 [get_ports ddram_dq[8]] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[8]] + ## ddram:0.dq +set_property LOC B2 [get_ports ddram_dq[9]] +set_property SLEW FAST [get_ports ddram_dq[9]] +set_property IOSTANDARD SSTL15 [get_ports ddram_dq[9]] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[9]] + ## ddram:0.dq +set_property LOC F3 [get_ports ddram_dq[10]] +set_property SLEW FAST [get_ports ddram_dq[10]] +set_property IOSTANDARD SSTL15 [get_ports ddram_dq[10]] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[10]] + ## ddram:0.dq +set_property LOC D2 [get_ports ddram_dq[11]] +set_property SLEW FAST [get_ports ddram_dq[11]] +set_property IOSTANDARD SSTL15 [get_ports ddram_dq[11]] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[11]] + ## ddram:0.dq +set_property LOC C2 [get_ports ddram_dq[12]] +set_property SLEW FAST [get_ports ddram_dq[12]] +set_property IOSTANDARD SSTL15 [get_ports ddram_dq[12]] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[12]] + ## ddram:0.dq +set_property LOC A1 [get_ports ddram_dq[13]] +set_property SLEW FAST [get_ports ddram_dq[13]] +set_property IOSTANDARD SSTL15 [get_ports ddram_dq[13]] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[13]] + ## ddram:0.dq +set_property LOC E2 [get_ports ddram_dq[14]] +set_property SLEW FAST [get_ports ddram_dq[14]] +set_property IOSTANDARD SSTL15 [get_ports ddram_dq[14]] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[14]] + ## ddram:0.dq +set_property LOC B1 [get_ports ddram_dq[15]] +set_property SLEW FAST [get_ports ddram_dq[15]] +set_property IOSTANDARD SSTL15 [get_ports ddram_dq[15]] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[15]] + ## ddram:0.dqs_p +set_property LOC K2 [get_ports ddram_dqs_p[0]] +set_property SLEW FAST [get_ports ddram_dqs_p[0]] +set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_p[0]] + ## ddram:0.dqs_p +set_property LOC E1 [get_ports ddram_dqs_p[1]] +set_property SLEW FAST [get_ports ddram_dqs_p[1]] +set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_p[1]] + ## ddram:0.dqs_n +set_property LOC J2 [get_ports ddram_dqs_n[0]] +set_property SLEW FAST [get_ports ddram_dqs_n[0]] +set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_n[0]] + ## ddram:0.dqs_n +set_property LOC D1 [get_ports ddram_dqs_n[1]] +set_property SLEW FAST [get_ports ddram_dqs_n[1]] +set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_n[1]] + ## ddram:0.clk_p +set_property LOC P5 [get_ports ddram_clk_p] +set_property SLEW FAST [get_ports ddram_clk_p] +set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_clk_p] + ## ddram:0.clk_n +set_property LOC P4 [get_ports ddram_clk_n] +set_property SLEW FAST [get_ports ddram_clk_n] +set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_clk_n] + ## ddram:0.cke +set_property LOC J6 [get_ports ddram_cke] +set_property SLEW FAST [get_ports ddram_cke] +set_property IOSTANDARD SSTL15 [get_ports ddram_cke] + ## ddram:0.odt +set_property LOC K4 [get_ports ddram_odt] +set_property SLEW FAST [get_ports ddram_odt] +set_property IOSTANDARD SSTL15 [get_ports ddram_odt] + ## ddram:0.reset_n +set_property LOC G1 [get_ports ddram_reset_n] +set_property SLEW FAST [get_ports ddram_reset_n] +set_property IOSTANDARD SSTL15 [get_ports ddram_reset_n] + +#Internal VREF +set_property INTERNAL_VREF 0.750 [get_iobanks 35] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl new file mode 100644 index 0000000..ea23dd5 --- /dev/null +++ b/fpga/top-nexys-video.vhdl @@ -0,0 +1,207 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.all; + +library work; +use work.wishbone_types.all; + +entity toplevel is + generic ( + MEMORY_SIZE : positive := 16384; + RAM_INIT_FILE : string := "firmware.hex"; + RESET_LOW : boolean := true; + CLK_FREQUENCY : positive := 100000000; + USE_LITEDRAM : boolean := false; + DISABLE_FLATTEN_CORE : boolean := false + ); + port( + ext_clk : in std_ulogic; + ext_rst : in std_ulogic; + + -- UART0 signals: + uart_main_tx : out std_ulogic; + uart_main_rx : in std_ulogic; + + -- LEDs + led0 : out std_logic; + led1 : out std_logic; + + -- DRAM wires + ddram_a : out std_logic_vector(14 downto 0); + ddram_ba : out std_logic_vector(2 downto 0); + ddram_ras_n : out std_logic; + ddram_cas_n : out std_logic; + ddram_we_n : out std_logic; + ddram_dm : out std_logic_vector(1 downto 0); + ddram_dq : inout std_logic_vector(15 downto 0); + ddram_dqs_p : inout std_logic_vector(1 downto 0); + ddram_dqs_n : inout std_logic_vector(1 downto 0); + ddram_clk_p : out std_logic; + ddram_clk_n : out std_logic; + ddram_cke : out std_logic; + ddram_odt : out std_logic; + ddram_reset_n : out std_logic + ); +end entity toplevel; + +architecture behaviour of toplevel is + + -- Reset signals: + signal soc_rst : std_ulogic; + signal pll_rst : std_ulogic; + + -- Internal clock signals: + signal system_clk : std_ulogic; + signal system_clk_locked : std_ulogic; + + -- DRAM wishbone connection + signal wb_dram_in : wishbone_master_out; + signal wb_dram_out : wishbone_slave_out; + signal wb_dram_csr : std_ulogic; + signal wb_dram_init : std_ulogic; + + -- Control/status + signal core_alt_reset : std_ulogic; + +begin + + -- Main SoC + soc0: entity work.soc + generic map( + MEMORY_SIZE => MEMORY_SIZE, + RAM_INIT_FILE => RAM_INIT_FILE, + RESET_LOW => RESET_LOW, + SIM => false, + HAS_DRAM => USE_LITEDRAM, + DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE + ) + port map ( + system_clk => system_clk, + rst => soc_rst, + uart0_txd => uart_main_tx, + uart0_rxd => uart_main_rx, + wb_dram_in => wb_dram_in, + wb_dram_out => wb_dram_out, + wb_dram_csr => wb_dram_csr, + wb_dram_init => wb_dram_init, + alt_reset => core_alt_reset + ); + + nodram: if not USE_LITEDRAM generate + signal ddram_clk_dummy : std_ulogic; + begin + reset_controller: entity work.soc_reset + generic map( + RESET_LOW => RESET_LOW + ) + port map( + ext_clk => ext_clk, + pll_clk => system_clk, + pll_locked_in => system_clk_locked, + ext_rst_in => ext_rst, + pll_rst_out => pll_rst, + rst_out => soc_rst + ); + + clkgen: entity work.clock_generator + generic map( + CLK_INPUT_HZ => 100000000, + CLK_OUTPUT_HZ => CLK_FREQUENCY + ) + port map( + ext_clk => ext_clk, + pll_rst_in => pll_rst, + pll_clk_out => system_clk, + pll_locked_out => system_clk_locked + ); + + led0 <= '1'; + led1 <= not soc_rst; + core_alt_reset <= '0'; + + -- Vivado barfs on those differential signals if left + -- unconnected. So instanciate a diff. buffer and feed + -- it a constant '0'. + dummy_dram_clk: OBUFDS + port map ( + O => ddram_clk_p, + OB => ddram_clk_n, + I => ddram_clk_dummy + ); + ddram_clk_dummy <= '0'; + + end generate; + + has_dram: if USE_LITEDRAM generate + signal dram_init_done : std_ulogic; + signal dram_init_error : std_ulogic; + signal soc_rst_0 : std_ulogic; + signal soc_rst_1 : std_ulogic; + begin + + -- Eventually dig out the frequency from the generator + -- but for now, assert it's 100Mhz + assert CLK_FREQUENCY = 100000000; + + reset_controller: entity work.soc_reset + generic map( + RESET_LOW => RESET_LOW + ) + port map( + ext_clk => ext_clk, + pll_clk => system_clk, + pll_locked_in => system_clk_locked, + ext_rst_in => ext_rst, + pll_rst_out => pll_rst, + rst_out => soc_rst_0 + ); + + dram: entity work.litedram_wrapper + generic map( + DRAM_ABITS => 25, + DRAM_ALINES => 15 + ) + port map( + clk_in => ext_clk, + rst => pll_rst, + system_clk => system_clk, + system_reset => soc_rst_1, + pll_locked => system_clk_locked, + + wb_in => wb_dram_in, + wb_out => wb_dram_out, + wb_is_csr => wb_dram_csr, + wb_is_init => wb_dram_init, + + serial_tx => open, + serial_rx => '0', + + init_done => dram_init_done, + init_error => dram_init_error, + + ddram_a => ddram_a, + ddram_ba => ddram_ba, + ddram_ras_n => ddram_ras_n, + ddram_cas_n => ddram_cas_n, + ddram_we_n => ddram_we_n, + ddram_cs_n => open, + ddram_dm => ddram_dm, + ddram_dq => ddram_dq, + ddram_dqs_p => ddram_dqs_p, + ddram_dqs_n => ddram_dqs_n, + ddram_clk_p => ddram_clk_p, + ddram_clk_n => ddram_clk_n, + ddram_cke => ddram_cke, + ddram_odt => ddram_odt, + ddram_reset_n => ddram_reset_n + ); + + led0 <= dram_init_done and not dram_init_error; + led1 <= dram_init_error; -- Make it blink ? + soc_rst <= soc_rst_0 or soc_rst_1; + + end generate; +end architecture behaviour; diff --git a/microwatt.core b/microwatt.core index 9e60792..f7002ae 100644 --- a/microwatt.core +++ b/microwatt.core @@ -76,7 +76,7 @@ filesets: files: - fpga/nexys-video.xdc : {file_type : xdc} - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008} - - fpga/top-generic.vhdl : {file_type : vhdlSource-2008} + - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008} arty_a7: files: @@ -107,7 +107,7 @@ targets: vivado: {part : xc7a100tcsg324-1} toplevel : toplevel - nexys_video: + nexys_video-nodram: default_tool: vivado filesets: [core, nexys_video, soc, fpga, debug_xilinx] parameters : @@ -120,6 +120,19 @@ targets: vivado: {part : xc7a200tsbg484-1} toplevel : toplevel + nexys_video: + default_tool: vivado + filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram] + parameters: + - memory_size + - ram_init_file + - use_litedram=true + - disable_flatten_core + generate: [dram_nexys_video] + tools: + vivado: {part : xc7a200tsbg484-1} + toplevel : toplevel + arty_a7-35-nodram: default_tool: vivado filesets: [core, arty_a7, soc, fpga, debug_xilinx] @@ -197,6 +210,10 @@ generate: generator: litedram_gen parameters: {board : arty} + dram_nexys_video: + generator: litedram_gen + parameters: {board : nexys-video} + parameters: memory_size: datatype : int From 025cf5efe8591c4f0802fd2f1472e57481069152 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 24 Sep 2019 22:24:31 +1000 Subject: [PATCH 11/16] syscon: Add syscon registers These provides some info about the SoC (though it's still somewhat incomplete and needs more work, see comments). There's also a control register for selecting DRAM vs. BRAM at 0 (and for soft-resetting the SoC but that isn't wired up yet). Signed-off-by: Benjamin Herrenschmidt --- Makefile | 3 +- core_tb.vhdl | 3 +- fpga/top-arty.vhdl | 2 + fpga/top-nexys-video.vhdl | 2 + litedram/gen-src/sdram_init/main.c | 3 +- microwatt.core | 1 + soc.vhdl | 49 +++++++++-- syscon.vhdl | 136 +++++++++++++++++++++++++++++ 8 files changed, 190 insertions(+), 9 deletions(-) create mode 100644 syscon.vhdl diff --git a/Makefile b/Makefile index 1978d01..b9ad461 100644 --- a/Makefile +++ b/Makefile @@ -71,7 +71,8 @@ rotator_tb.o: common.o glibc_random.o ppc_fx_insns.o insn_helpers.o rotator.o sim_console.o: sim_uart.o: wishbone_types.o sim_console.o xics.o: wishbone_types.o common.o -soc.o: common.o wishbone_types.o core.o wishbone_arbiter.o sim_uart.o wishbone_bram_wrapper.o dmi_dtm_xilinx.o wishbone_debug_master.o xics.o +soc.o: common.o wishbone_types.o core.o wishbone_arbiter.o sim_uart.o wishbone_bram_wrapper.o dmi_dtm_xilinx.o wishbone_debug_master.o xics.o syscon.o +syscon.o: wishbone_types.o wishbone_arbiter.o: wishbone_types.o wishbone_types.o: writeback.o: common.o crhelpers.o diff --git a/core_tb.vhdl b/core_tb.vhdl index c473de3..9c08919 100644 --- a/core_tb.vhdl +++ b/core_tb.vhdl @@ -25,7 +25,8 @@ begin SIM => true, MEMORY_SIZE => (384*1024), RAM_INIT_FILE => "main_ram.bin", - RESET_LOW => false + RESET_LOW => false, + CLK_FREQ => 100000000 ) port map( rst => rst, diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl index a458c04..fbea534 100644 --- a/fpga/top-arty.vhdl +++ b/fpga/top-arty.vhdl @@ -92,7 +92,9 @@ begin RAM_INIT_FILE => RAM_INIT_FILE, RESET_LOW => RESET_LOW, SIM => false, + CLK_FREQ => CLK_FREQUENCY, HAS_DRAM => USE_LITEDRAM, + DRAM_SIZE => 256 * 1024 * 1024, DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE ) port map ( diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl index ea23dd5..c0e3659 100644 --- a/fpga/top-nexys-video.vhdl +++ b/fpga/top-nexys-video.vhdl @@ -75,7 +75,9 @@ begin RAM_INIT_FILE => RAM_INIT_FILE, RESET_LOW => RESET_LOW, SIM => false, + CLK_FREQ => CLK_FREQUENCY, HAS_DRAM => USE_LITEDRAM, + DRAM_SIZE => 512 * 1024 * 1024, DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE ) port map ( diff --git a/litedram/gen-src/sdram_init/main.c b/litedram/gen-src/sdram_init/main.c index cc8b714..eae5c28 100644 --- a/litedram/gen-src/sdram_init/main.c +++ b/litedram/gen-src/sdram_init/main.c @@ -156,7 +156,8 @@ void main(void) printf(" INFO: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x08)); printf(" BRAMINFO: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x10)); printf(" DRAMINFO: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x18)); - printf(" CTRL: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x20)); + printf(" CLKINFO: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x20)); + printf(" CTRL: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x28)); sdrinit(); printf("Booting from BRAM...\n"); } diff --git a/microwatt.core b/microwatt.core index f7002ae..a1ae14b 100644 --- a/microwatt.core +++ b/microwatt.core @@ -46,6 +46,7 @@ filesets: - wishbone_bram_wrapper.vhdl - soc.vhdl - xics.vhdl + - syscon.vhdl file_type : vhdlSource-2008 fpga: diff --git a/soc.vhdl b/soc.vhdl index 53fa2f1..db52db3 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -12,8 +12,9 @@ use work.wishbone_types.all; -- Memory map: -- --- 0x00000000: Block RAM +-- 0x00000000: Block RAM (MEMORY_SIZE) or DRAM depending on syscon -- 0x40000000: DRAM (when present) +-- 0xc0000000: SYSCON -- 0xc0002000: UART0 -- 0xc0004000: XICS ICP -- 0xf0000000: Block RAM (aliased & repeated) @@ -24,9 +25,11 @@ entity soc is MEMORY_SIZE : positive; RAM_INIT_FILE : string; RESET_LOW : boolean; + CLK_FREQ : positive; SIM : boolean; DISABLE_FLATTEN_CORE : boolean := false; - HAS_DRAM : boolean := false + HAS_DRAM : boolean := false; + DRAM_SIZE : integer := 0 ); port( rst : in std_ulogic; @@ -67,6 +70,12 @@ architecture behaviour of soc is signal wb_master_in : wishbone_slave_out; signal wb_master_out : wishbone_master_out; + -- Syscon signals + signal dram_at_0 : std_ulogic; + signal core_reset : std_ulogic; + signal wb_syscon_in : wishbone_master_out; + signal wb_syscon_out : wishbone_slave_out; + -- UART0 signals: signal wb_uart0_in : wishbone_master_out; signal wb_uart0_out : wishbone_slave_out; @@ -110,7 +119,7 @@ begin ) port map( clk => system_clk, - rst => rst, + rst => rst or core_reset, alt_reset => alt_reset, wishbone_insn_in => wishbone_icore_in, wishbone_insn_out => wishbone_icore_out, @@ -145,9 +154,10 @@ begin ); -- Wishbone slaves address decoder & mux - slave_intercon: process(wb_master_out, wb_bram_out, wb_uart0_out, wb_dram_out) + slave_intercon: process(wb_master_out, wb_bram_out, wb_uart0_out, wb_dram_out, wb_syscon_out) -- Selected slave - type slave_type is (SLAVE_UART, + type slave_type is (SLAVE_SYSCON, + SLAVE_UART, SLAVE_BRAM, SLAVE_DRAM, SLAVE_DRAM_INIT, @@ -161,13 +171,16 @@ begin -- Simple address decoder. Ignore top bits to save silicon for now slave := SLAVE_NONE; if std_match(wb_master_out.adr, x"0-------") then - slave := SLAVE_BRAM; + slave := SLAVE_DRAM when HAS_DRAM and dram_at_0 = '1' else + SLAVE_BRAM; elsif std_match(wb_master_out.adr, x"FFFF----") then slave := SLAVE_DRAM_INIT; elsif std_match(wb_master_out.adr, x"F-------") then slave := SLAVE_BRAM; elsif std_match(wb_master_out.adr, x"4-------") and HAS_DRAM then slave := SLAVE_DRAM; + elsif std_match(wb_master_out.adr, x"C0000---") then + slave := SLAVE_SYSCON; elsif std_match(wb_master_out.adr, x"C0002---") then slave := SLAVE_UART; elsif std_match(wb_master_out.adr, x"C01-----") then @@ -192,6 +205,8 @@ begin wb_dram_in.cyc <= '0'; wb_dram_csr <= '0'; wb_dram_init <= '0'; + wb_syscon_in <= wb_master_out; + wb_syscon_in.cyc <= '0'; case slave is when SLAVE_BRAM => wb_bram_in.cyc <= wb_master_out.cyc; @@ -207,6 +222,9 @@ begin wb_dram_in.cyc <= wb_master_out.cyc; wb_master_in <= wb_dram_out; wb_dram_csr <= '1'; + when SLAVE_SYSCON => + wb_syscon_in.cyc <= wb_master_out.cyc; + wb_master_in <= wb_syscon_out; when SLAVE_UART => wb_uart0_in.cyc <= wb_master_out.cyc; wb_master_in <= wb_uart0_out; @@ -220,6 +238,25 @@ begin end case; end process slave_intercon; + -- Syscon slave + syscon0: entity work.syscon + generic map( + HAS_UART => true, + HAS_DRAM => HAS_DRAM, + BRAM_SIZE => MEMORY_SIZE, + DRAM_SIZE => DRAM_SIZE, + CLK_FREQ => CLK_FREQ + ) + port map( + clk => system_clk, + rst => rst, + wishbone_in => wb_syscon_in, + wishbone_out => wb_syscon_out, + dram_at_0 => dram_at_0, + core_reset => core_reset, + soc_reset => open -- XXX TODO + ); + -- Simulated memory and UART -- UART0 wishbone slave diff --git a/syscon.vhdl b/syscon.vhdl new file mode 100644 index 0000000..a5b569b --- /dev/null +++ b/syscon.vhdl @@ -0,0 +1,136 @@ +-- syscon module, a bunch of misc global system control MMIO registers +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.wishbone_types.all; + +entity syscon is + generic ( + SIG_VALUE : std_ulogic_vector(63 downto 0) := x"f00daa5500010001"; + CLK_FREQ : integer; + HAS_UART : boolean; + HAS_DRAM : boolean; + BRAM_SIZE : integer; + DRAM_SIZE : integer + ); + port ( + clk : in std_ulogic; + rst : in std_ulogic; + + -- Wishbone ports: + wishbone_in : in wishbone_master_out; + wishbone_out : out wishbone_slave_out; + + -- System control ports + dram_at_0 : out std_ulogic; + core_reset : out std_ulogic; + soc_reset : out std_ulogic + ); +end entity syscon; + + +architecture behaviour of syscon is + -- Register address bits + constant SYS_REG_BITS : positive := 3; + + -- Register addresses (matches wishbone addr downto 3, ie, 8 bytes per reg) + constant SYS_REG_SIG : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000"; + constant SYS_REG_INFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001"; + constant SYS_REG_BRAMINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "010"; + constant SYS_REG_DRAMINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "011"; + constant SYS_REG_CLKINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "100"; + constant SYS_REG_CTRL : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "101"; + + -- INFO register bits + constant SYS_REG_INFO_HAS_UART : integer := 0; + constant SYS_REG_INFO_HAS_DRAM : integer := 1; + + -- BRAMINFO contains the BRAM size in the bottom 52 bits + -- DRAMINFO contains the DRAM size if any in the bottom 52 bits + -- (both have reserved top bits for future use) + -- CLKINFO contains the CLK frequency is HZ in the bottom 40 bits + + -- CTRL register bits + constant SYS_REG_CTRL_BITS : positive := 3; + constant SYS_REG_CTRL_DRAM_AT_0 : integer := 0; + constant SYS_REG_CTRL_CORE_RESET : integer := 1; + constant SYS_REG_CTRL_SOC_RESET : integer := 2; + + -- Ctrl register + signal reg_ctrl : std_ulogic_vector(SYS_REG_CTRL_BITS-1 downto 0); + signal reg_ctrl_out : std_ulogic_vector(63 downto 0); + + -- Others + signal reg_info : std_ulogic_vector(63 downto 0); + signal reg_braminfo : std_ulogic_vector(63 downto 0); + signal reg_draminfo : std_ulogic_vector(63 downto 0); + signal reg_clkinfo : std_ulogic_vector(63 downto 0); + signal info_has_dram : std_ulogic; + signal info_has_uart : std_ulogic; + signal info_clk : std_ulogic_vector(39 downto 0); +begin + + -- Generated output signals + dram_at_0 <= reg_ctrl(SYS_REG_CTRL_DRAM_AT_0); + soc_reset <= reg_ctrl(SYS_REG_CTRL_SOC_RESET); + core_reset <= reg_ctrl(SYS_REG_CTRL_CORE_RESET); + + -- All register accesses are single cycle + wishbone_out.ack <= wishbone_in.cyc and wishbone_in.stb; + wishbone_out.stall <= '0'; + + -- Info register is hard wired + info_has_uart <= '1' when HAS_UART else '0'; + info_has_dram <= '1' when HAS_DRAM else '0'; + info_clk <= std_ulogic_vector(to_unsigned(CLK_FREQ, 40)); + reg_info <= (0 => info_has_uart, + 1 => info_has_dram, + others => '0'); + reg_braminfo <= x"000" & std_ulogic_vector(to_unsigned(BRAM_SIZE, 52)); + reg_draminfo <= x"000" & std_ulogic_vector(to_unsigned(DRAM_SIZE, 52)) when HAS_DRAM + else (others => '0'); + reg_clkinfo <= (39 downto 0 => info_clk, + others => '0'); + + -- Control register read composition + reg_ctrl_out <= (63 downto SYS_REG_CTRL_BITS => '0', + SYS_REG_CTRL_BITS-1 downto 0 => reg_ctrl); + + -- Register read mux + with wishbone_in.adr(SYS_REG_BITS+2 downto 3) select wishbone_out.dat <= + SIG_VALUE when SYS_REG_SIG, + reg_info when SYS_REG_INFO, + reg_braminfo when SYS_REG_BRAMINFO, + reg_draminfo when SYS_REG_DRAMINFO, + reg_clkinfo when SYS_REG_CLKINFO, + reg_ctrl_out when SYS_REG_CTRL, + (others => '0') when others; + + -- Register writes + regs_write: process(clk) + begin + if rising_edge(clk) then + if (rst) then + reg_ctrl <= (others => '0'); + else + if wishbone_in.cyc and wishbone_in.stb and wishbone_in.we then + if wishbone_in.adr(SYS_REG_BITS+2 downto 3) = SYS_REG_CTRL then + reg_ctrl(SYS_REG_CTRL_BITS-1 downto 0) <= + wishbone_in.dat(SYS_REG_CTRL_BITS-1 downto 0); + end if; + end if; + + -- Reset auto-clear + if reg_ctrl(SYS_REG_CTRL_SOC_RESET) = '1' then + reg_ctrl(SYS_REG_CTRL_SOC_RESET) <= '0'; + end if; + if reg_ctrl(SYS_REG_CTRL_CORE_RESET) = '1' then + reg_ctrl(SYS_REG_CTRL_CORE_RESET) <= '0'; + end if; + end if; + end if; + end process; + +end architecture behaviour; From 33de131384358767455f89a2b0e37a861aba8086 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 8 May 2020 10:27:33 +1000 Subject: [PATCH 12/16] Add microwatt_soc.h and io.h include file This contains C definitions for various Microwatt internal MMIOs and a set of accessors. Signed-off-by: Benjamin Herrenschmidt --- include/io.h | 53 +++++++++++++++++++++++++++++++++++++++++ include/microwatt_soc.h | 34 ++++++++++++++++++++++++++ 2 files changed, 87 insertions(+) create mode 100644 include/io.h create mode 100644 include/microwatt_soc.h diff --git a/include/io.h b/include/io.h new file mode 100644 index 0000000..bc73c9a --- /dev/null +++ b/include/io.h @@ -0,0 +1,53 @@ +#ifndef __IO_H +#define __IO_H + +static inline uint8_t readb(unsigned long addr) +{ + uint8_t val; + __asm__ volatile("sync; lbzcix %0,0,%1" : "=r" (val) : "r" (addr) : "memory"); + return val; +} + +static inline uint16_t readw(unsigned long addr) +{ + uint16_t val; + __asm__ volatile("sync; lhzcix %0,0,%1" : "=r" (val) : "r" (addr) : "memory"); + return val; +} + +static inline uint32_t readl(unsigned long addr) +{ + uint32_t val; + __asm__ volatile("sync; lwzcix %0,0,%1" : "=r" (val) : "r" (addr) : "memory"); + return val; +} + +static inline uint64_t readq(unsigned long addr) +{ + uint64_t val; + __asm__ volatile("sync; ldcix %0,0,%1" : "=r" (val) : "r" (addr) : "memory"); + return val; +} + +static inline void writeb(uint8_t val, unsigned long addr) +{ + __asm__ volatile("sync; stbcix %0,0,%1" : : "r" (val), "r" (addr) : "memory"); +} + +static inline void writew(uint16_t val, unsigned long addr) +{ + __asm__ volatile("sync; sthcix %0,0,%1" : : "r" (val), "r" (addr) : "memory"); +} + +static inline void writel(uint32_t val, unsigned long addr) +{ + __asm__ volatile("sync; stwcix %0,0,%1" : : "r" (val), "r" (addr) : "memory"); +} + +static inline void writeq(uint64_t val, unsigned long addr) +{ + __asm__ volatile("sync; stdcix %0,0,%1" : : "r" (val), "r" (addr) : "memory"); +} + +#endif /* __IO_H */ + diff --git a/include/microwatt_soc.h b/include/microwatt_soc.h new file mode 100644 index 0000000..35add6b --- /dev/null +++ b/include/microwatt_soc.h @@ -0,0 +1,34 @@ +#ifndef __MICROWATT_SOC_H +#define __MICROWATT_SOC_H + +/* + * Definitions for the syscon registers + */ +#define SYSCON_BASE 0xc0000000 + +#define SYS_REG_SIGNATURE 0x00 +#define SYS_REG_INFO 0x08 +#define SYS_REG_INFO_HAS_UART (1ull << 0) +#define SYS_REG_INFO_HAS_DRAM (1ull << 1) +#define SYS_REG_BRAMINFO 0x10 +#define SYS_REG_DRAMINFO 0x18 +#define SYS_REG_CLKINFO 0x20 +#define SYS_REG_CTRL 0x28 +#define SYS_REG_CTRL_DRAM_AT_0 (1ull << 0) +#define SYS_REG_CTRL_CORE_RESET (1ull << 1) +#define SYS_REG_CTRL_SOC_RESET (1ull << 2) + +/* Definition for the "Potato" UART */ +#define UART_BASE 0xc0002000 + +#define POTATO_CONSOLE_TX 0x00 +#define POTATO_CONSOLE_RX 0x08 +#define POTATO_CONSOLE_STATUS 0x10 +#define POTATO_CONSOLE_STATUS_RX_EMPTY 0x01 +#define POTATO_CONSOLE_STATUS_TX_EMPTY 0x02 +#define POTATO_CONSOLE_STATUS_RX_FULL 0x04 +#define POTATO_CONSOLE_STATUS_TX_FULL 0x08 +#define POTATO_CONSOLE_CLOCK_DIV 0x18 +#define POTATO_CONSOLE_IRQ_EN 0x20 + +#endif /* __MICROWATT_SOC_H */ From 12e8b0952ded227a77c612fd56060e124bc43b08 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 24 Sep 2019 16:19:29 +1000 Subject: [PATCH 13/16] litedram: Improve sdram init boot messages Signed-off-by: Benjamin Herrenschmidt --- litedram/gen-src/sdram_init/Makefile | 2 +- litedram/gen-src/sdram_init/main.c | 83 +++++++++++++--------------- 2 files changed, 39 insertions(+), 46 deletions(-) diff --git a/litedram/gen-src/sdram_init/Makefile b/litedram/gen-src/sdram_init/Makefile index ce57732..d330a85 100644 --- a/litedram/gen-src/sdram_init/Makefile +++ b/litedram/gen-src/sdram_init/Makefile @@ -22,7 +22,7 @@ OBJCOPY = $(CROSS_COMPILE)objcopy #### Flags CPPFLAGS = -nostdinc -CPPFLAGS += -I$(SRC_DIR)/libc/include -I$(LXSRC_DIR) -I$(LXINC_DIR) -I$(GENINC_DIR) -I$(SRC_DIR)/include +CPPFLAGS += -I$(SRC_DIR)/libc/include -I$(LXSRC_DIR) -I$(LXINC_DIR) -I$(GENINC_DIR) -I$(SRC_DIR)/include -I$(SRC_DIR)/../../include CPPFLAGS += -isystem $(shell $(CC) -print-file-name=include) CFLAGS = -Os -g -Wall -std=c99 -m64 -mabi=elfv2 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections -fno-delete-null-pointer-checks ASFLAGS = $(CPPFLAGS) $(CFLAGS) diff --git a/litedram/gen-src/sdram_init/main.c b/litedram/gen-src/sdram_init/main.c index eae5c28..57baccd 100644 --- a/litedram/gen-src/sdram_init/main.c +++ b/litedram/gen-src/sdram_init/main.c @@ -5,6 +5,10 @@ #include #include +#include + +#include "microwatt_soc.h" +#include "io.h" #include "sdram.h" /* @@ -15,42 +19,6 @@ static uint64_t potato_uart_base; #define PROC_FREQ 100000000 #define UART_FREQ 115200 -#define UART_BASE 0xc0002000 -#define SYSCON_BASE 0xc0000000 - -#define POTATO_CONSOLE_TX 0x00 -#define POTATO_CONSOLE_RX 0x08 -#define POTATO_CONSOLE_STATUS 0x10 -#define POTATO_CONSOLE_STATUS_RX_EMPTY 0x01 -#define POTATO_CONSOLE_STATUS_TX_EMPTY 0x02 -#define POTATO_CONSOLE_STATUS_RX_FULL 0x04 -#define POTATO_CONSOLE_STATUS_TX_FULL 0x08 -#define POTATO_CONSOLE_CLOCK_DIV 0x18 -#define POTATO_CONSOLE_IRQ_EN 0x20 - -static inline uint8_t readb(unsigned long addr) -{ - __asm__ volatile("sync" : : : "memory"); - return *((volatile uint8_t *)addr); -} - -static inline uint64_t readq(unsigned long addr) -{ - __asm__ volatile("sync" : : : "memory"); - return *((volatile uint64_t *)addr); -} - -static inline void writeb(uint8_t val, unsigned long addr) -{ - __asm__ volatile("sync" : : : "memory"); - *((volatile uint8_t *)addr) = val; -} - -static inline void writeq(uint64_t val, unsigned long addr) -{ - __asm__ volatile("sync" : : : "memory"); - *((volatile uint64_t *)addr) = val; -} static uint8_t potato_uart_reg_read(int offset) { @@ -145,19 +113,44 @@ void flush_l2_cache(void) { } void main(void) { + unsigned long long ftr, val; int i; - // Let things settle ... not sure why but UART not happy otherwise + /* + * Let things settle ... not sure why but the UART is + * not happy otherwise. The PLL might need to settle ? + */ potato_uart_init(); for (i = 0; i < 10000; i++) potato_uart_reg_read(POTATO_CONSOLE_STATUS); - printf("Welcome to Microwatt !\n"); - printf(" SIG: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x00)); - printf(" INFO: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x08)); - printf(" BRAMINFO: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x10)); - printf(" DRAMINFO: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x18)); - printf(" CLKINFO: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x20)); - printf(" CTRL: %016llx\n", (unsigned long long)readq(SYSCON_BASE + 0x28)); - sdrinit(); + printf("\n\nWelcome to Microwatt !\n\n"); + + /* TODO: Add core version information somewhere in syscon, possibly + * extracted from git + */ + printf(" Soc signature: %016llx\n", + (unsigned long long)readq(SYSCON_BASE + SYS_REG_SIGNATURE)); + printf(" Soc features: "); + ftr = readq(SYSCON_BASE + SYS_REG_INFO); + if (ftr & SYS_REG_INFO_HAS_UART) + printf("UART "); + if (ftr & SYS_REG_INFO_HAS_DRAM) + printf("DRAM "); + printf("\n"); + val = readq(SYSCON_BASE + SYS_REG_BRAMINFO); + printf(" BRAM: %lld KB\n", val / 1024); + if (ftr & SYS_REG_INFO_HAS_DRAM) { + val = readq(SYSCON_BASE + SYS_REG_DRAMINFO); + printf(" DRAM: %lld MB\n", val / (1024 * 1024)); + } + val = readq(SYSCON_BASE + SYS_REG_CLKINFO); + printf(" CLK: %lld MHz\n", val / 1000000); + + printf("\n"); + if (ftr & SYS_REG_INFO_HAS_DRAM) { + printf("LiteDRAM built from Migen %s and LiteX %s\n", + MIGEN_GIT_SHA1, LITEX_GIT_SHA1); + sdrinit(); + } printf("Booting from BRAM...\n"); } From c5f5f507385dd9d2dad62908c79d911d237a4eda Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 8 May 2020 10:42:01 +1000 Subject: [PATCH 14/16] hello_world: Use new headers and frequency from syscon This uses the new header files for register definitions and extracts the core frequency from syscon rather than hard coding it. Signed-off-by: Benjamin Herrenschmidt --- fpga/hello_world.hex | 120 +++++++++++++++++++++--------------- hello_world/Makefile | 2 +- hello_world/console.c | 31 +++------- hello_world/hello_world.bin | Bin 4536 -> 4688 bytes hello_world/hello_world.elf | Bin 77520 -> 79584 bytes hello_world/hello_world.hex | 89 +++++++++++++++----------- rust_lib_demo/Makefile | 2 +- tests/Makefile.test | 2 +- 8 files changed, 138 insertions(+), 108 deletions(-) diff --git a/fpga/hello_world.hex b/fpga/hello_world.hex index 6bbe412..6098247 100644 --- a/fpga/hello_world.hex +++ b/fpga/hello_world.hex @@ -1,23 +1,11 @@ +000000004800012c +0000000000000000 4800002408000048 01006b69a600607d a602487d05009f42 a64b5a7d14004a39 2402004ca64b7b7d -3c20000048000004 -782107c660210000 -60212f0064210000 -618c00003d800000 -658c0000798c07c6 -7d8903a6618c113c -480000004e800421 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 +00000000480000f4 0000000000000000 0000000000000000 0000000000000000 @@ -42,6 +30,18 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 +4800002408000048 +01006b69a600607d +a602487d05009f42 +a64b5a7d14004a39 +2402004ca64b7b7d +3c20000048000004 +782107c660210000 +60211f0064210000 +618c00003d800000 +658c0000798c07c6 +7d8903a6618c1014 +480000004e800421 0000000000000000 0000000000000000 0000000000000000 @@ -513,52 +513,74 @@ a64b5a7d14004a39 e8010010ebc1fff0 7c0803a6ebe1fff8 3c4000014e800020 +7c0802a63842a000 +3fe2fffffbe1fff8 +f80100103bff7240 +48000051f821ffd1 +7fe3fb7860000000 +60000000480001d5 +7fe3fb787c641b78 +600000004800017d +60000000480000ed +480001295463063e +4bffffec60000000 +0100000000000000 +3c40000100000180 3d20c0003842a000 6129200060000000 f922800079290020 -394000353d20c000 -7929002061292018 -4e800020f9490000 +612900203d20c000 +7c0004ac79290020 +3d40001c7d204eea +7d295392614a2000 +394a0018e9428000 +7c0004ac3929ffff +4e8000207d2057ea 0000000000000000 3c40000100000000 600000003842a000 -390a0010e9428000 -71290001e9280000 -e86a00084082fff8 +394000ffe9228000 +7c0004ac39290020 +4e8000207d404fea +0000000000000000 +3c40000100000000 +600000003842a000 +39400000e9228000 +7c0004ac39290020 +4e8000207d404fea +0000000000000000 +3c40000100000000 +600000003842a000 +39290010e9228000 +7d204eea7c0004ac +4082ffe871290001 +38630008e8628000 +7c601eea7c0004ac 4e8000205463063e 0000000000000000 3c40000100000000 600000003842a000 -390a0010e9428000 -71290008e9280000 -f86a00004082fff8 -000000004e800020 -0000000000000000 -3842a0003c400001 -fbc1fff07c0802a6 -7fc32214fbe1fff8 -f80100107c7f1b78 -7fbff040f821ffd1 -38210030409e000c -887f00004bffff10 -4bffff993bff0001 -000000004bffffe4 -0000028001000000 -7d4348ae39200000 -409e000c2f8a0000 -4e8000207d234b78 -4bffffe839290001 +39290010e9228000 +7d204eea7c0004ac +4082ffe871290008 +7c0004ace9228000 +4e8000207c604fea 0000000000000000 3c40000100000000 7c0802a63842a000 -3fe2fffffbe1fff8 -f80100103bff7190 -4bfffec1f821ffd1 -4bffffad7fe3fb78 -7fe3fb787c641b78 -4bfffee94bffff59 -4bffff195463063e -000000004bfffff4 -0000018001000000 +fbe1fff8fbc1fff0 +7c7f1b787fc32214 +f821ffd1f8010010 +409e000c7fbff040 +4bfffe0c38210030 +3bff0001887f0000 +4bffffe44bffff8d +0100000000000000 +3920000000000280 +2f8a00007d4348ae +7d234b78409e000c +392900014e800020 +000000004bffffe8 +0000000000000000 6f57206f6c6c6548 0000000a0d646c72 diff --git a/hello_world/Makefile b/hello_world/Makefile index a609199..9051e7d 100644 --- a/hello_world/Makefile +++ b/hello_world/Makefile @@ -9,7 +9,7 @@ CC = $(CROSS_COMPILE)gcc LD = $(CROSS_COMPILE)ld OBJCOPY = $(CROSS_COMPILE)objcopy -CFLAGS = -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections +CFLAGS = -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections -I../include ASFLAGS = $(CFLAGS) LDFLAGS = -T powerpc.lds diff --git a/hello_world/console.c b/hello_world/console.c index 4069244..6c1c311 100644 --- a/hello_world/console.c +++ b/hello_world/console.c @@ -2,6 +2,10 @@ #include #include "console.h" +#include "microwatt_soc.h" +#include "io.h" + +#define UART_FREQ 115200 /* * Core UART functions to implement for a port @@ -9,32 +13,14 @@ static uint64_t potato_uart_base; -#define PROC_FREQ 100000000 -#define UART_FREQ 115200 -#define UART_BASE 0xc0002000 - -#define POTATO_CONSOLE_TX 0x00 -#define POTATO_CONSOLE_RX 0x08 -#define POTATO_CONSOLE_STATUS 0x10 -#define POTATO_CONSOLE_STATUS_RX_EMPTY 0x01 -#define POTATO_CONSOLE_STATUS_TX_EMPTY 0x02 -#define POTATO_CONSOLE_STATUS_RX_FULL 0x04 -#define POTATO_CONSOLE_STATUS_TX_FULL 0x08 -#define POTATO_CONSOLE_CLOCK_DIV 0x18 -#define POTATO_CONSOLE_IRQ_EN 0x20 - static uint64_t potato_uart_reg_read(int offset) { - uint64_t val; - - __asm__ volatile("ldcix %0,%1,%2" : "=r" (val) : "b" (potato_uart_base), "r" (offset)); - - return val; + return readq(potato_uart_base + offset); } static void potato_uart_reg_write(int offset, uint64_t val) { - __asm__ volatile("stdcix %0,%1,%2" : : "r" (val), "b" (potato_uart_base), "r" (offset)); + writeq(val, potato_uart_base + offset); } static int potato_uart_rx_empty(void) @@ -86,9 +72,12 @@ static unsigned long potato_uart_divisor(unsigned long proc_freq, unsigned long void potato_uart_init(void) { + uint64_t proc_freq; + potato_uart_base = UART_BASE; + proc_freq = readq(SYSCON_BASE + SYS_REG_CLKINFO); - potato_uart_reg_write(POTATO_CONSOLE_CLOCK_DIV, potato_uart_divisor(PROC_FREQ, UART_FREQ)); + potato_uart_reg_write(POTATO_CONSOLE_CLOCK_DIV, potato_uart_divisor(proc_freq, UART_FREQ)); } void potato_uart_irq_en(void) diff --git a/hello_world/hello_world.bin b/hello_world/hello_world.bin index 73bc181a46073d0bccc3f5eb37f54f36447de921..ae4c4a8311b39e5cdef455ff1672da7b2cac9c4b 100755 GIT binary patch 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aXGu21}FsUh9LHPN*3 z?HfavvA6SPjl%Z#gzWA4vS{q>Jg#T|SjgVqmtHmYc73d8KM}IG=hgKM#-9t>+xy&s z_JE&V|LetnI%IFx>AbP8-v5k)FhBV^ERhbGc6&~~V(jg7n&#?TbC8~96M zkP<=mnz64xH>4$8|4WuxUx8(Cwf1jC>ZPl7Ut7oiPvj#lr&RUrQCC;RdY#2<#s9mW zK)U}X_CHw1{`&5~{`*1L>NU*sC+paMXHQ`N*Hz1)5bo=**0C?%7HICcN&o-T*r!5q zKKFsZ{`u;}HpaL8h;Tv5Vf&VSfyUz@zt+y?ZCtSBdeuo||HFDAm&5Bv?u?->YKx)$ zfmbsPRWIRKQV${0y65Eo@HnN6^PODo<)4keOBy+~@Ncd7zkeXGe@<)FF5&q918$d6 A2mk;8 diff --git a/hello_world/hello_world.hex b/hello_world/hello_world.hex index 633e218..6098247 100644 --- a/hello_world/hello_world.hex +++ b/hello_world/hello_world.hex @@ -515,53 +515,72 @@ e8010010ebc1fff0 3c4000014e800020 7c0802a63842a000 3fe2fffffbe1fff8 -f80100103bff71a8 +f80100103bff7240 48000051f821ffd1 7fe3fb7860000000 -6000000048000139 +60000000480001d5 7fe3fb787c641b78 -60000000480000e1 -6000000048000065 -480000955463063e +600000004800017d +60000000480000ed +480001295463063e 4bffffec60000000 0100000000000000 3c40000100000180 3d20c0003842a000 6129200060000000 -7929002039000018 -3940001af9228000 -4e8000207d4947ea +f922800079290020 +612900203d20c000 +7c0004ac79290020 +3d40001c7d204eea +7d295392614a2000 +394a0018e9428000 +7c0004ac3929ffff +4e8000207d2057ea 0000000000000000 3c40000100000000 600000003842a000 -39000010e9228000 -794707e17d4946ea -386000084082fff8 -5463063e7c691eea -000000004e800020 -0000000000000000 -3842a0003c400001 -e942800060000000 -7d2a46ea39000010 -4082fff87927efe3 -7c6a4fea39200000 -000000004e800020 -0000000000000000 -3842a0003c400001 -fbc1fff07c0802a6 -3884fffffbe1fff8 -7fe322143bc3ffff -f821ffd1f8010010 -419e00107fbef840 -4bffff9d8c7e0001 -382100304bfffff0 -000000004bfffe98 -0000028001000000 -7d4348ae39200000 -419e000c2f8a0000 -4bfffff039290001 -4e8000207d234b78 +394000ffe9228000 +7c0004ac39290020 +4e8000207d404fea +0000000000000000 +3c40000100000000 +600000003842a000 +39400000e9228000 +7c0004ac39290020 +4e8000207d404fea +0000000000000000 +3c40000100000000 +600000003842a000 +39290010e9228000 +7d204eea7c0004ac +4082ffe871290001 +38630008e8628000 +7c601eea7c0004ac +4e8000205463063e 0000000000000000 +3c40000100000000 +600000003842a000 +39290010e9228000 +7d204eea7c0004ac +4082ffe871290008 +7c0004ace9228000 +4e8000207c604fea +0000000000000000 +3c40000100000000 +7c0802a63842a000 +fbe1fff8fbc1fff0 +7c7f1b787fc32214 +f821ffd1f8010010 +409e000c7fbff040 +4bfffe0c38210030 +3bff0001887f0000 +4bffffe44bffff8d +0100000000000000 +3920000000000280 +2f8a00007d4348ae +7d234b78409e000c +392900014e800020 +000000004bffffe8 0000000000000000 6f57206f6c6c6548 0000000a0d646c72 diff --git a/rust_lib_demo/Makefile b/rust_lib_demo/Makefile index fdbb18b..607b533 100644 --- a/rust_lib_demo/Makefile +++ b/rust_lib_demo/Makefile @@ -9,7 +9,7 @@ CC = $(CROSS_COMPILE)gcc LD = $(CROSS_COMPILE)ld OBJCOPY = $(CROSS_COMPILE)objcopy -CFLAGS = -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections +CFLAGS = -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections -I../include ASFLAGS = $(CFLAGS) LDFLAGS = -T powerpc.lds diff --git a/tests/Makefile.test b/tests/Makefile.test index 250135d..9241e3f 100644 --- a/tests/Makefile.test +++ b/tests/Makefile.test @@ -9,7 +9,7 @@ CC = $(CROSS_COMPILE)gcc LD = $(CROSS_COMPILE)ld OBJCOPY = $(CROSS_COMPILE)objcopy -CFLAGS = -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections -I ../../hello_world +CFLAGS = -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections -I ../../hello_world -I ../../include ASFLAGS = $(CFLAGS) LDFLAGS = -T powerpc.lds From 7f1f6b852570ed003e425d5737d7570196ce6911 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Sat, 9 May 2020 01:09:26 +1000 Subject: [PATCH 15/16] litedram: Add support for Microwatt-initialized controller This adds support for initializing the memory controller from microwatt rather than using a built-in RiscV processor. This might require some fixes to LiteX and LiteDRAM (they haven't been merged as of this commit yet). This is enabled in the shipped generated files and can be changed via modifying the generator script to pass False to "mw_init" Signed-off-by: Benjamin Herrenschmidt --- litedram/gen-src/arty.yml | 1 + litedram/gen-src/generate.py | 19 +- litedram/gen-src/sdram_init/Makefile | 4 +- litedram/gen-src/sdram_init/include/system.h | 14 + .../gen-src/sdram_init/libc/include/limits.h | 32 + litedram/gen-src/sdram_init/main.c | 2 +- litedram/gen-src/wrapper-mw-init.vhdl | 58 +- litedram/generated/arty/init-cpu.txt | 1 - litedram/generated/arty/litedram-wrapper.vhdl | 117 +- litedram/generated/arty/litedram_core.init | 7328 ++---- litedram/generated/arty/litedram_core.v | 20528 +++++++--------- litedram/generated/nexys-video/init-cpu.txt | 1 - .../nexys-video/litedram-wrapper.vhdl | 117 +- .../generated/nexys-video/litedram_core.init | 7265 ++---- .../generated/nexys-video/litedram_core.v | 20010 +++++++-------- soc.vhdl | 1 + 16 files changed, 20545 insertions(+), 34953 deletions(-) create mode 100644 litedram/gen-src/sdram_init/libc/include/limits.h delete mode 100644 litedram/generated/arty/init-cpu.txt delete mode 100644 litedram/generated/nexys-video/init-cpu.txt diff --git a/litedram/gen-src/arty.yml b/litedram/gen-src/arty.yml index e82316a..a84f964 100644 --- a/litedram/gen-src/arty.yml +++ b/litedram/gen-src/arty.yml @@ -39,4 +39,5 @@ # CSR Port ----------------------------------------------------------------- "csr_expose": "False", # expose access to CSR (I/O) ports "csr_align" : 32, # CSR alignment + "csr_base" : 0xc0100000 # For cpu=None only } diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py index 37ee427..8c6b70a 100755 --- a/litedram/gen-src/generate.py +++ b/litedram/gen-src/generate.py @@ -35,7 +35,7 @@ def build_init_code(build_dir): # More path fudging sw_dir = os.path.join(build_dir, "software"); - sw_inc_dir = os.path.join(build_dir, "include") + sw_inc_dir = os.path.join(sw_dir, "include") gen_inc_dir = os.path.join(sw_inc_dir, "generated") src_dir = os.path.join(gen_src_dir, "sdram_init") lxbios_src_dir = os.path.join(soc_directory, "software", "bios") @@ -59,7 +59,7 @@ def build_init_code(build_dir): add_var("BUILD_DIR", sw_dir) add_var("SRC_DIR", src_dir) - add_var("GENINC_DIR", gen_inc_dir) + add_var("GENINC_DIR", sw_inc_dir) add_var("LXSRC_DIR", lxbios_src_dir) add_var("LXINC_DIR", lxbios_inc_dir) write_to_file(os.path.join(gen_inc_dir, "variables.mak"), "".join(env_vars)) @@ -72,7 +72,7 @@ def build_init_code(build_dir): return os.path.join(sw_dir, "obj", "sdram_init.hex") -def generate_one(t): +def generate_one(t, mw_init): print("Generating target:", t) @@ -101,6 +101,12 @@ def generate_one(t): if k == "sdram_phy": core_config[k] = getattr(litedram_phys, core_config[k]) + # Override values for mw_init + if mw_init: + core_config["cpu"] = None + core_config["csr_expose"] = True + core_config["csr_align"] = 64 + # Generate core if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]: platform = LatticePlatform("LFE5UM5G-45F-8BG381C", io=[], toolchain="trellis") @@ -120,8 +126,7 @@ def generate_one(t): # Generate init-cpu.txt if any and generate init code if none cpu = core_config["cpu"] - if cpu is None: - print("Microwatt based inits not supported yet !") + if mw_init: src_wrap_file = os.path.join(gen_src_dir, "wrapper-mw-init.vhdl") src_init_file = build_init_code(build_dir) else: @@ -141,8 +146,10 @@ def generate_one(t): def main(): targets = ['arty','nexys-video'] + + # XXX Set mw_init to False to use a local VexRiscV for memory inits for t in targets: - generate_one(t) + generate_one(t, mw_init = True) # XXX TODO: Remove build dir unless told not to via cmdline option diff --git a/litedram/gen-src/sdram_init/Makefile b/litedram/gen-src/sdram_init/Makefile index d330a85..28395a3 100644 --- a/litedram/gen-src/sdram_init/Makefile +++ b/litedram/gen-src/sdram_init/Makefile @@ -22,7 +22,7 @@ OBJCOPY = $(CROSS_COMPILE)objcopy #### Flags CPPFLAGS = -nostdinc -CPPFLAGS += -I$(SRC_DIR)/libc/include -I$(LXSRC_DIR) -I$(LXINC_DIR) -I$(GENINC_DIR) -I$(SRC_DIR)/include -I$(SRC_DIR)/../../include +CPPFLAGS += -I$(SRC_DIR)/libc/include -I$(LXSRC_DIR) -I$(LXINC_DIR) -I$(GENINC_DIR) -I$(SRC_DIR)/include -I$(SRC_DIR)/../../../include CPPFLAGS += -isystem $(shell $(CC) -print-file-name=include) CFLAGS = -Os -g -Wall -std=c99 -m64 -mabi=elfv2 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections -fno-delete-null-pointer-checks ASFLAGS = $(CPPFLAGS) $(CFLAGS) @@ -30,7 +30,7 @@ LDFLAGS = -static -nostdlib -Ttext-segment=0xffff0000 -T $(SRC_DIR)/$(PROGRAM).l #### Pretty print -ifeq ($(VERBOSE),1) +ifeq ($(V),1) define Q $(2) endef diff --git a/litedram/gen-src/sdram_init/include/system.h b/litedram/gen-src/sdram_init/include/system.h index b5df315..879f4ca 100644 --- a/litedram/gen-src/sdram_init/include/system.h +++ b/litedram/gen-src/sdram_init/include/system.h @@ -1,3 +1,17 @@ static inline void flush_cpu_dcache(void) { } static inline void flush_l2_cache(void) { } +#define CONFIG_CPU_NOP "nop" +#define CONFIG_CLOCK_FREQUENCY 100000000 + +static inline void timer0_en_write(int e) { } +static inline void timer0_reload_write(int r) { } +static inline void timer0_load_write(int l) { } +static inline void timer0_update_value_write(int v) { } +static inline uint64_t timer0_value_read(void) +{ + uint64_t val; + + __asm__ volatile ("mfdec %0" : "=r" (val)); + return val; +} diff --git a/litedram/gen-src/sdram_init/libc/include/limits.h b/litedram/gen-src/sdram_init/libc/include/limits.h new file mode 100644 index 0000000..4726835 --- /dev/null +++ b/litedram/gen-src/sdram_init/libc/include/limits.h @@ -0,0 +1,32 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +#ifndef _LIMITS_H +#define _LIMITS_H + +#define UCHAR_MAX 255 +#define SCHAR_MAX 127 +#define SCHAR_MIN (-128) + +#define USHRT_MAX 65535 +#define SHRT_MAX 32767 +#define SHRT_MIN (-32768) + +#define UINT_MAX (4294967295U) +#define INT_MAX 2147483647 +#define INT_MIN (-2147483648) + +#define ULONG_MAX ((unsigned long)-1L) +#define LONG_MAX (ULONG_MAX/2) +#define LONG_MIN ((-LONG_MAX)-1) + +#endif diff --git a/litedram/gen-src/sdram_init/main.c b/litedram/gen-src/sdram_init/main.c index 57baccd..e36b1da 100644 --- a/litedram/gen-src/sdram_init/main.c +++ b/litedram/gen-src/sdram_init/main.c @@ -121,7 +121,7 @@ void main(void) * not happy otherwise. The PLL might need to settle ? */ potato_uart_init(); - for (i = 0; i < 10000; i++) + for (i = 0; i < 100000; i++) potato_uart_reg_read(POTATO_CONSOLE_STATUS); printf("\n\nWelcome to Microwatt !\n\n"); diff --git a/litedram/gen-src/wrapper-mw-init.vhdl b/litedram/gen-src/wrapper-mw-init.vhdl index 70ff006..475e088 100644 --- a/litedram/gen-src/wrapper-mw-init.vhdl +++ b/litedram/gen-src/wrapper-mw-init.vhdl @@ -45,8 +45,8 @@ entity litedram_wrapper is ddram_cs_n : out std_ulogic; ddram_dm : out std_ulogic_vector(1 downto 0); ddram_dq : inout std_ulogic_vector(15 downto 0); - ddram_dqs_p : out std_ulogic_vector(1 downto 0); - ddram_dqs_n : out std_ulogic_vector(1 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(1 downto 0); ddram_clk_p : out std_ulogic; ddram_clk_n : out std_ulogic; ddram_cke : out std_ulogic; @@ -69,8 +69,8 @@ architecture behaviour of litedram_wrapper is ddram_cs_n : out std_ulogic; ddram_dm : out std_ulogic_vector(1 downto 0); ddram_dq : inout std_ulogic_vector(15 downto 0); - ddram_dqs_p : out std_ulogic_vector(1 downto 0); - ddram_dqs_n : out std_ulogic_vector(1 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(1 downto 0); ddram_clk_p : out std_ulogic; ddram_clk_n : out std_ulogic; ddram_cke : out std_ulogic; @@ -84,17 +84,17 @@ architecture behaviour of litedram_wrapper is csr_port0_we : in std_ulogic; csr_port0_dat_w : in std_ulogic_vector(7 downto 0); csr_port0_dat_r : out std_ulogic_vector(7 downto 0); - user_port0_cmd_valid : in std_ulogic; - user_port0_cmd_ready : out std_ulogic; - user_port0_cmd_we : in std_ulogic; - user_port0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0); - user_port0_wdata_valid : in std_ulogic; - user_port0_wdata_ready : out std_ulogic; - user_port0_wdata_we : in std_ulogic_vector(15 downto 0); - user_port0_wdata_data : in std_ulogic_vector(127 downto 0); - user_port0_rdata_valid : out std_ulogic; - user_port0_rdata_ready : in std_ulogic; - user_port0_rdata_data : out std_ulogic_vector(127 downto 0) + user_port_native_0_cmd_valid : in std_ulogic; + user_port_native_0_cmd_ready : out std_ulogic; + user_port_native_0_cmd_we : in std_ulogic; + user_port_native_0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0); + user_port_native_0_wdata_valid : in std_ulogic; + user_port_native_0_wdata_ready : out std_ulogic; + user_port_native_0_wdata_we : in std_ulogic_vector(15 downto 0); + user_port_native_0_wdata_data : in std_ulogic_vector(127 downto 0); + user_port_native_0_rdata_valid : out std_ulogic; + user_port_native_0_rdata_ready : in std_ulogic; + user_port_native_0_rdata_data : out std_ulogic_vector(127 downto 0) ); end component; @@ -130,7 +130,7 @@ architecture behaviour of litedram_wrapper is constant INIT_RAM_SIZE : integer := 16384; constant INIT_RAM_ABITS :integer := 14; - constant INIT_RAM_FILE : string := "sdram_init.hex"; + constant INIT_RAM_FILE : string := "litedram_core.init"; type ram_t is array(0 to (INIT_RAM_SIZE / 8) - 1) of std_logic_vector(63 downto 0); @@ -176,7 +176,7 @@ begin end if; wb_init_out.ack <= not wb_init_out.ack; end if; - end if; + end if; end process; wb_init_in.adr <= wb_in.adr; @@ -205,7 +205,7 @@ begin -- DRAM CSR interface signals. We only support access to the bottom byte csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; csr_write_valid <= wb_in.we and wb_in.sel(0); - csr_port0_adr <= wb_in.adr(15 downto 3) & '0' when wb_is_csr = '1' else (others => '0'); + csr_port0_adr <= wb_in.adr(13 downto 0) when wb_is_csr = '1' else (others => '0'); csr_port0_dat_w <= wb_in.dat(7 downto 0); csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; @@ -287,17 +287,17 @@ begin csr_port0_we => csr_port0_we, csr_port0_dat_w => csr_port0_dat_w, csr_port0_dat_r => csr_port0_dat_r, - user_port0_cmd_valid => user_port0_cmd_valid, - user_port0_cmd_ready => user_port0_cmd_ready, - user_port0_cmd_we => user_port0_cmd_we, - user_port0_cmd_addr => user_port0_cmd_addr, - user_port0_wdata_valid => user_port0_wdata_valid, - user_port0_wdata_ready => user_port0_wdata_ready, - user_port0_wdata_we => user_port0_wdata_we, - user_port0_wdata_data => user_port0_wdata_data, - user_port0_rdata_valid => user_port0_rdata_valid, - user_port0_rdata_ready => user_port0_rdata_ready, - user_port0_rdata_data => user_port0_rdata_data + user_port_native_0_cmd_valid => user_port0_cmd_valid, + user_port_native_0_cmd_ready => user_port0_cmd_ready, + user_port_native_0_cmd_we => user_port0_cmd_we, + user_port_native_0_cmd_addr => user_port0_cmd_addr, + user_port_native_0_wdata_valid => user_port0_wdata_valid, + user_port_native_0_wdata_ready => user_port0_wdata_ready, + user_port_native_0_wdata_we => user_port0_wdata_we, + user_port_native_0_wdata_data => user_port0_wdata_data, + user_port_native_0_rdata_valid => user_port0_rdata_valid, + user_port_native_0_rdata_ready => user_port0_rdata_ready, + user_port_native_0_rdata_data => user_port0_rdata_data ); end architecture behaviour; diff --git a/litedram/generated/arty/init-cpu.txt b/litedram/generated/arty/init-cpu.txt deleted file mode 100644 index b0b6e79..0000000 --- a/litedram/generated/arty/init-cpu.txt +++ /dev/null @@ -1 +0,0 @@ -vexriscv \ No newline at end of file diff --git a/litedram/generated/arty/litedram-wrapper.vhdl b/litedram/generated/arty/litedram-wrapper.vhdl index 0664866..475e088 100644 --- a/litedram/generated/arty/litedram-wrapper.vhdl +++ b/litedram/generated/arty/litedram-wrapper.vhdl @@ -60,8 +60,6 @@ architecture behaviour of litedram_wrapper is component litedram_core port ( clk : in std_ulogic; rst : in std_ulogic; - serial_tx : out std_ulogic; - serial_rx : in std_ulogic; pll_locked : out std_ulogic; ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); ddram_ba : out std_ulogic_vector(2 downto 0); @@ -82,6 +80,10 @@ architecture behaviour of litedram_wrapper is init_error : out std_ulogic; user_clk : out std_ulogic; user_rst : out std_ulogic; + csr_port0_adr : in std_ulogic_vector(13 downto 0); + csr_port0_we : in std_ulogic; + csr_port0_dat_w : in std_ulogic_vector(7 downto 0); + csr_port0_dat_r : out std_ulogic_vector(7 downto 0); user_port_native_0_cmd_valid : in std_ulogic; user_port_native_0_cmd_ready : out std_ulogic; user_port_native_0_cmd_we : in std_ulogic; @@ -112,17 +114,84 @@ architecture behaviour of litedram_wrapper is signal dram_user_reset : std_ulogic; - type state_t is (CMD, MWRITE, MREAD); + signal csr_port0_adr : std_ulogic_vector(13 downto 0); + signal csr_port0_we : std_ulogic; + signal csr_port0_dat_w : std_ulogic_vector(7 downto 0); + signal csr_port0_dat_r : std_ulogic_vector(7 downto 0); + signal csr_port_read_comb : std_ulogic_vector(63 downto 0); + signal csr_valid : std_ulogic; + signal csr_write_valid : std_ulogic; + + signal wb_init_in : wishbone_master_out; + signal wb_init_out : wishbone_slave_out; + + type state_t is (CMD, MWRITE, MREAD, CSR); signal state : state_t; + constant INIT_RAM_SIZE : integer := 16384; + constant INIT_RAM_ABITS :integer := 14; + constant INIT_RAM_FILE : string := "litedram_core.init"; + + type ram_t is array(0 to (INIT_RAM_SIZE / 8) - 1) of std_logic_vector(63 downto 0); + + impure function init_load_ram(name : string) return ram_t is + file ram_file : text open read_mode is name; + variable temp_word : std_logic_vector(63 downto 0); + variable temp_ram : ram_t := (others => (others => '0')); + variable ram_line : line; + begin + for i in 0 to (INIT_RAM_SIZE/8)-1 loop + exit when endfile(ram_file); + readline(ram_file, ram_line); + hread(ram_line, temp_word); + temp_ram(i) := temp_word; + end loop; + return temp_ram; + end function; + + signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE); + + attribute ram_style : string; + attribute ram_style of init_ram: signal is "block"; + begin - -- Address bit 3 selects the top or bottom half of the data + -- BRAM Memory slave + init_ram_0: process(system_clk) + variable adr : integer; + begin + if rising_edge(system_clk) then + wb_init_out.ack <= '0'; + if (wb_init_in.cyc and wb_init_in.stb) = '1' then + adr := to_integer((unsigned(wb_init_in.adr(INIT_RAM_ABITS-1 downto 3)))); + if wb_init_in.we = '0' then + wb_init_out.dat <= init_ram(adr); + else + for i in 0 to 7 loop + if wb_init_in.sel(i) = '1' then + init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= + wb_init_in.dat(((i + 1) * 8) - 1 downto i * 8); + end if; + end loop; + end if; + wb_init_out.ack <= not wb_init_out.ack; + end if; + end if; + end process; + + wb_init_in.adr <= wb_in.adr; + wb_init_in.dat <= wb_in.dat; + wb_init_in.sel <= wb_in.sel; + wb_init_in.we <= wb_in.we; + wb_init_in.stb <= wb_in.stb; + wb_init_in.cyc <= wb_in.cyc and wb_is_init; + + -- Address bit 3 selects the top or bottom half of the data -- bus (64-bit wishbone vs. 128-bit DRAM interface) -- ad3 <= wb_in.adr(3); - -- DRAM interface signals + -- DRAM data interface signals user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init) when state = CMD else '0'; user_port0_cmd_we <= wb_in.we when state = CMD else '0'; @@ -133,18 +202,32 @@ begin user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else "00000000" & wb_in.sel; - -- Wishbone out signals. CSR and init memory do nothing, just ack - wb_out.ack <= '1' when (wb_is_csr = '1' or wb_is_init = '1') else + -- DRAM CSR interface signals. We only support access to the bottom byte + csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; + csr_write_valid <= wb_in.we and wb_in.sel(0); + csr_port0_adr <= wb_in.adr(13 downto 0) when wb_is_csr = '1' else (others => '0'); + csr_port0_dat_w <= wb_in.dat(7 downto 0); + csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; + + -- Wishbone out signals + wb_out.ack <= '1' when state = CSR else + wb_init_out.ack when wb_is_init = '1' else user_port0_wdata_ready when state = MWRITE else user_port0_rdata_valid when state = MREAD else '0'; - wb_out.dat <= (others => '0') when (wb_is_csr = '1' or wb_is_init = '1') else + + csr_port_read_comb <= x"00000000000000" & csr_port0_dat_r; + wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else + wb_init_out.dat when wb_is_init = '1' else user_port0_rdata_data(127 downto 64) when ad3 = '1' else user_port0_rdata_data(63 downto 0); + -- We don't do pipelining yet. wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack; - -- Reset, lift it when init done, no alt core reset - system_reset <= dram_user_reset or not init_done; - core_alt_reset <= '0'; + -- Reset ignored, the reset controller use the pll lock signal, + -- and alternate core reset address set when DRAM is not initialized. + -- + system_reset <= '0'; + core_alt_reset <= not init_done; -- State machine sm: process(system_clk) @@ -156,7 +239,9 @@ begin else case state is when CMD => - if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then + if csr_valid = '1' then + state <= CSR; + elsif (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then state <= MWRITE when wb_in.we = '1' else MREAD; end if; when MWRITE => @@ -167,6 +252,8 @@ begin if user_port0_rdata_valid = '1' then state <= CMD; end if; + when CSR => + state <= CMD; end case; end if; end if; @@ -176,8 +263,6 @@ begin port map( clk => clk_in, rst => rst, - serial_tx => serial_tx, - serial_rx => serial_rx, pll_locked => pll_locked, ddram_a => ddram_a, ddram_ba => ddram_ba, @@ -198,6 +283,10 @@ begin init_error => init_error, user_clk => system_clk, user_rst => dram_user_reset, + csr_port0_adr => csr_port0_adr, + csr_port0_we => csr_port0_we, + csr_port0_dat_w => csr_port0_dat_w, + csr_port0_dat_r => csr_port0_dat_r, user_port_native_0_cmd_valid => user_port0_cmd_valid, user_port_native_0_cmd_ready => user_port0_cmd_ready, user_port_native_0_cmd_we => user_port0_cmd_we, diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init index 60f87de..1031ca2 100644 --- a/litedram/generated/arty/litedram_core.init +++ b/litedram/generated/arty/litedram_core.init @@ -1,5817 +1,1511 @@ -b00006f -13 -13 -13 -13 -13 -13 -13 -fe112e23 -fe512c23 -fe612a23 -fe712823 -fea12623 -feb12423 -fec12223 -fed12023 -fce12e23 -fcf12c23 -fd012a23 -fd112823 -fdc12623 -fdd12423 -fde12223 -fdf12023 -fc010113 -94000ef -3c12083 -3812283 -3412303 -3012383 -2c12503 -2812583 -2412603 -2012683 -1c12703 -1812783 -1412803 -1012883 -c12e03 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+00000000000000ff +000000000000ffff +0000000000ffffff +00000000ffffffff +000000ffffffffff +0000ffffffffffff +00ffffffffffffff +ffffffffffffffff +0000000000007830 diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v index 9a0843a..727e21a 100644 --- a/litedram/generated/arty/litedram_core.v +++ b/litedram/generated/arty/litedram_core.v @@ -1,9 +1,7 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (dc9cfe6) & LiteX (79ee135f) on 2020-05-08 01:29:17 +// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 10:54:03 //-------------------------------------------------------------------------------- module litedram_core( - output reg serial_tx, - input wire serial_rx, input wire clk, input wire rst, output wire pll_locked, @@ -24,6 +22,10 @@ module litedram_core( output wire ddram_reset_n, output wire init_done, output wire init_error, + input wire [13:0] csr_port0_adr, + input wire csr_port0_we, + input wire [7:0] csr_port0_dat_w, + output wire [7:0] csr_port0_dat_r, output wire user_clk, output wire user_rst, input wire user_port_native_0_cmd_valid, @@ -39,2520 +41,2000 @@ module litedram_core( output wire [127:0] user_port_native_0_rdata_data ); -reg soc_litedramcore_soccontroller_reset_storage = 1'd0; -reg soc_litedramcore_soccontroller_reset_re = 1'd0; -reg [31:0] soc_litedramcore_soccontroller_scratch_storage = 32'd305419896; -reg soc_litedramcore_soccontroller_scratch_re = 1'd0; -wire [31:0] soc_litedramcore_soccontroller_bus_errors_status; -wire soc_litedramcore_soccontroller_bus_errors_we; -wire soc_litedramcore_soccontroller_reset; -wire soc_litedramcore_soccontroller_bus_error; -reg [31:0] soc_litedramcore_soccontroller_bus_errors = 32'd0; -wire soc_litedramcore_cpu_reset; -reg [31:0] soc_litedramcore_cpu_interrupt = 32'd0; -wire [29:0] soc_litedramcore_cpu_ibus_adr; -wire [31:0] soc_litedramcore_cpu_ibus_dat_w; -wire [31:0] soc_litedramcore_cpu_ibus_dat_r; -wire [3:0] soc_litedramcore_cpu_ibus_sel; -wire soc_litedramcore_cpu_ibus_cyc; -wire soc_litedramcore_cpu_ibus_stb; -wire soc_litedramcore_cpu_ibus_ack; -wire soc_litedramcore_cpu_ibus_we; -wire [2:0] soc_litedramcore_cpu_ibus_cti; -wire [1:0] soc_litedramcore_cpu_ibus_bte; -wire soc_litedramcore_cpu_ibus_err; -wire [29:0] soc_litedramcore_cpu_dbus_adr; -wire [31:0] soc_litedramcore_cpu_dbus_dat_w; -wire [31:0] soc_litedramcore_cpu_dbus_dat_r; -wire [3:0] soc_litedramcore_cpu_dbus_sel; -wire soc_litedramcore_cpu_dbus_cyc; -wire soc_litedramcore_cpu_dbus_stb; -wire soc_litedramcore_cpu_dbus_ack; -wire soc_litedramcore_cpu_dbus_we; -wire [2:0] soc_litedramcore_cpu_dbus_cti; -wire [1:0] soc_litedramcore_cpu_dbus_bte; -wire soc_litedramcore_cpu_dbus_err; -reg [31:0] soc_litedramcore_vexriscv = 32'd0; -wire [29:0] soc_litedramcore_litedramcore_ram_bus_adr; -wire [31:0] soc_litedramcore_litedramcore_ram_bus_dat_w; -wire [31:0] soc_litedramcore_litedramcore_ram_bus_dat_r; -wire [3:0] soc_litedramcore_litedramcore_ram_bus_sel; -wire soc_litedramcore_litedramcore_ram_bus_cyc; -wire soc_litedramcore_litedramcore_ram_bus_stb; -reg soc_litedramcore_litedramcore_ram_bus_ack = 1'd0; -wire soc_litedramcore_litedramcore_ram_bus_we; -wire [2:0] soc_litedramcore_litedramcore_ram_bus_cti; -wire [1:0] soc_litedramcore_litedramcore_ram_bus_bte; -reg soc_litedramcore_litedramcore_ram_bus_err = 1'd0; -wire [12:0] soc_litedramcore_litedramcore_adr; -wire [31:0] soc_litedramcore_litedramcore_dat_r; -wire [29:0] soc_litedramcore_ram_bus_ram_bus_adr; -wire [31:0] soc_litedramcore_ram_bus_ram_bus_dat_w; -wire [31:0] soc_litedramcore_ram_bus_ram_bus_dat_r; -wire [3:0] soc_litedramcore_ram_bus_ram_bus_sel; -wire soc_litedramcore_ram_bus_ram_bus_cyc; -wire soc_litedramcore_ram_bus_ram_bus_stb; -reg soc_litedramcore_ram_bus_ram_bus_ack = 1'd0; -wire soc_litedramcore_ram_bus_ram_bus_we; -wire [2:0] soc_litedramcore_ram_bus_ram_bus_cti; -wire [1:0] soc_litedramcore_ram_bus_ram_bus_bte; -reg soc_litedramcore_ram_bus_ram_bus_err = 1'd0; -wire [9:0] soc_litedramcore_ram_adr; -wire [31:0] soc_litedramcore_ram_dat_r; -reg [3:0] soc_litedramcore_ram_we = 4'd0; -wire [31:0] soc_litedramcore_ram_dat_w; -reg [31:0] soc_litedramcore_storage = 32'd4947802; -reg soc_litedramcore_re = 1'd0; -wire soc_litedramcore_sink_valid; -reg soc_litedramcore_sink_ready = 1'd0; -wire soc_litedramcore_sink_first; -wire soc_litedramcore_sink_last; -wire [7:0] soc_litedramcore_sink_payload_data; -reg soc_litedramcore_uart_clk_txen = 1'd0; -reg [31:0] soc_litedramcore_phase_accumulator_tx = 32'd0; -reg [7:0] soc_litedramcore_tx_reg = 8'd0; -reg [3:0] soc_litedramcore_tx_bitcount = 4'd0; -reg soc_litedramcore_tx_busy = 1'd0; -reg soc_litedramcore_source_valid = 1'd0; -wire soc_litedramcore_source_ready; -reg soc_litedramcore_source_first = 1'd0; -reg soc_litedramcore_source_last = 1'd0; -reg [7:0] soc_litedramcore_source_payload_data = 8'd0; -reg soc_litedramcore_uart_clk_rxen = 1'd0; -reg [31:0] soc_litedramcore_phase_accumulator_rx = 32'd0; -wire soc_litedramcore_rx; -reg soc_litedramcore_rx_r = 1'd0; -reg [7:0] soc_litedramcore_rx_reg = 8'd0; -reg [3:0] soc_litedramcore_rx_bitcount = 4'd0; -reg soc_litedramcore_rx_busy = 1'd0; -wire soc_litedramcore_uart_rxtx_re; -wire [7:0] soc_litedramcore_uart_rxtx_r; -wire soc_litedramcore_uart_rxtx_we; -wire [7:0] soc_litedramcore_uart_rxtx_w; -wire soc_litedramcore_uart_txfull_status; -wire soc_litedramcore_uart_txfull_we; -wire soc_litedramcore_uart_rxempty_status; -wire soc_litedramcore_uart_rxempty_we; -wire soc_litedramcore_uart_irq; -wire soc_litedramcore_uart_tx_status; -reg soc_litedramcore_uart_tx_pending = 1'd0; -wire soc_litedramcore_uart_tx_trigger; -reg soc_litedramcore_uart_tx_clear = 1'd0; -reg soc_litedramcore_uart_tx_old_trigger = 1'd0; -wire soc_litedramcore_uart_rx_status; -reg soc_litedramcore_uart_rx_pending = 1'd0; -wire soc_litedramcore_uart_rx_trigger; -reg soc_litedramcore_uart_rx_clear = 1'd0; -reg soc_litedramcore_uart_rx_old_trigger = 1'd0; -wire soc_litedramcore_uart_eventmanager_status_re; -wire [1:0] soc_litedramcore_uart_eventmanager_status_r; -wire soc_litedramcore_uart_eventmanager_status_we; -reg [1:0] soc_litedramcore_uart_eventmanager_status_w = 2'd0; -wire soc_litedramcore_uart_eventmanager_pending_re; -wire [1:0] soc_litedramcore_uart_eventmanager_pending_r; -wire soc_litedramcore_uart_eventmanager_pending_we; -reg [1:0] soc_litedramcore_uart_eventmanager_pending_w = 2'd0; -reg [1:0] soc_litedramcore_uart_eventmanager_storage = 2'd0; -reg soc_litedramcore_uart_eventmanager_re = 1'd0; -wire soc_litedramcore_uart_uart_sink_valid; -wire soc_litedramcore_uart_uart_sink_ready; -wire soc_litedramcore_uart_uart_sink_first; -wire soc_litedramcore_uart_uart_sink_last; -wire [7:0] soc_litedramcore_uart_uart_sink_payload_data; -wire soc_litedramcore_uart_uart_source_valid; -wire soc_litedramcore_uart_uart_source_ready; -wire soc_litedramcore_uart_uart_source_first; -wire soc_litedramcore_uart_uart_source_last; -wire [7:0] soc_litedramcore_uart_uart_source_payload_data; -wire soc_litedramcore_uart_tx_fifo_sink_valid; -wire soc_litedramcore_uart_tx_fifo_sink_ready; -reg soc_litedramcore_uart_tx_fifo_sink_first = 1'd0; -reg soc_litedramcore_uart_tx_fifo_sink_last = 1'd0; -wire [7:0] soc_litedramcore_uart_tx_fifo_sink_payload_data; -wire soc_litedramcore_uart_tx_fifo_source_valid; -wire soc_litedramcore_uart_tx_fifo_source_ready; -wire soc_litedramcore_uart_tx_fifo_source_first; -wire soc_litedramcore_uart_tx_fifo_source_last; -wire [7:0] soc_litedramcore_uart_tx_fifo_source_payload_data; -wire soc_litedramcore_uart_tx_fifo_re; -reg soc_litedramcore_uart_tx_fifo_readable = 1'd0; -wire soc_litedramcore_uart_tx_fifo_syncfifo_we; -wire soc_litedramcore_uart_tx_fifo_syncfifo_writable; -wire soc_litedramcore_uart_tx_fifo_syncfifo_re; -wire soc_litedramcore_uart_tx_fifo_syncfifo_readable; -wire [9:0] soc_litedramcore_uart_tx_fifo_syncfifo_din; -wire [9:0] soc_litedramcore_uart_tx_fifo_syncfifo_dout; -reg [4:0] soc_litedramcore_uart_tx_fifo_level0 = 5'd0; -reg soc_litedramcore_uart_tx_fifo_replace = 1'd0; -reg [3:0] soc_litedramcore_uart_tx_fifo_produce = 4'd0; -reg [3:0] soc_litedramcore_uart_tx_fifo_consume = 4'd0; -reg [3:0] soc_litedramcore_uart_tx_fifo_wrport_adr = 4'd0; -wire [9:0] soc_litedramcore_uart_tx_fifo_wrport_dat_r; -wire soc_litedramcore_uart_tx_fifo_wrport_we; -wire [9:0] soc_litedramcore_uart_tx_fifo_wrport_dat_w; -wire soc_litedramcore_uart_tx_fifo_do_read; -wire [3:0] soc_litedramcore_uart_tx_fifo_rdport_adr; -wire [9:0] soc_litedramcore_uart_tx_fifo_rdport_dat_r; -wire soc_litedramcore_uart_tx_fifo_rdport_re; -wire [4:0] soc_litedramcore_uart_tx_fifo_level1; -wire [7:0] soc_litedramcore_uart_tx_fifo_fifo_in_payload_data; -wire soc_litedramcore_uart_tx_fifo_fifo_in_first; -wire soc_litedramcore_uart_tx_fifo_fifo_in_last; -wire [7:0] soc_litedramcore_uart_tx_fifo_fifo_out_payload_data; -wire soc_litedramcore_uart_tx_fifo_fifo_out_first; -wire soc_litedramcore_uart_tx_fifo_fifo_out_last; -wire soc_litedramcore_uart_rx_fifo_sink_valid; -wire soc_litedramcore_uart_rx_fifo_sink_ready; -wire soc_litedramcore_uart_rx_fifo_sink_first; -wire soc_litedramcore_uart_rx_fifo_sink_last; -wire [7:0] soc_litedramcore_uart_rx_fifo_sink_payload_data; -wire soc_litedramcore_uart_rx_fifo_source_valid; -wire soc_litedramcore_uart_rx_fifo_source_ready; -wire soc_litedramcore_uart_rx_fifo_source_first; -wire soc_litedramcore_uart_rx_fifo_source_last; -wire [7:0] soc_litedramcore_uart_rx_fifo_source_payload_data; -wire soc_litedramcore_uart_rx_fifo_re; -reg soc_litedramcore_uart_rx_fifo_readable = 1'd0; -wire soc_litedramcore_uart_rx_fifo_syncfifo_we; -wire soc_litedramcore_uart_rx_fifo_syncfifo_writable; -wire soc_litedramcore_uart_rx_fifo_syncfifo_re; -wire soc_litedramcore_uart_rx_fifo_syncfifo_readable; -wire [9:0] soc_litedramcore_uart_rx_fifo_syncfifo_din; -wire [9:0] soc_litedramcore_uart_rx_fifo_syncfifo_dout; -reg [4:0] soc_litedramcore_uart_rx_fifo_level0 = 5'd0; -reg soc_litedramcore_uart_rx_fifo_replace = 1'd0; -reg [3:0] soc_litedramcore_uart_rx_fifo_produce = 4'd0; -reg [3:0] soc_litedramcore_uart_rx_fifo_consume = 4'd0; -reg [3:0] soc_litedramcore_uart_rx_fifo_wrport_adr = 4'd0; -wire [9:0] soc_litedramcore_uart_rx_fifo_wrport_dat_r; -wire soc_litedramcore_uart_rx_fifo_wrport_we; -wire [9:0] soc_litedramcore_uart_rx_fifo_wrport_dat_w; -wire soc_litedramcore_uart_rx_fifo_do_read; -wire [3:0] soc_litedramcore_uart_rx_fifo_rdport_adr; -wire [9:0] soc_litedramcore_uart_rx_fifo_rdport_dat_r; -wire soc_litedramcore_uart_rx_fifo_rdport_re; -wire [4:0] soc_litedramcore_uart_rx_fifo_level1; -wire [7:0] soc_litedramcore_uart_rx_fifo_fifo_in_payload_data; -wire soc_litedramcore_uart_rx_fifo_fifo_in_first; -wire soc_litedramcore_uart_rx_fifo_fifo_in_last; -wire [7:0] soc_litedramcore_uart_rx_fifo_fifo_out_payload_data; -wire soc_litedramcore_uart_rx_fifo_fifo_out_first; -wire soc_litedramcore_uart_rx_fifo_fifo_out_last; -reg soc_litedramcore_uart_reset = 1'd0; -reg [31:0] soc_litedramcore_timer_load_storage = 32'd0; -reg soc_litedramcore_timer_load_re = 1'd0; -reg [31:0] soc_litedramcore_timer_reload_storage = 32'd0; -reg soc_litedramcore_timer_reload_re = 1'd0; -reg soc_litedramcore_timer_en_storage = 1'd0; -reg soc_litedramcore_timer_en_re = 1'd0; -reg soc_litedramcore_timer_update_value_storage = 1'd0; -reg soc_litedramcore_timer_update_value_re = 1'd0; -reg [31:0] soc_litedramcore_timer_value_status = 32'd0; -wire soc_litedramcore_timer_value_we; -wire soc_litedramcore_timer_irq; -wire soc_litedramcore_timer_zero_status; -reg soc_litedramcore_timer_zero_pending = 1'd0; -wire soc_litedramcore_timer_zero_trigger; -reg soc_litedramcore_timer_zero_clear = 1'd0; -reg soc_litedramcore_timer_zero_old_trigger = 1'd0; -wire soc_litedramcore_timer_eventmanager_status_re; -wire soc_litedramcore_timer_eventmanager_status_r; -wire soc_litedramcore_timer_eventmanager_status_we; -wire soc_litedramcore_timer_eventmanager_status_w; -wire soc_litedramcore_timer_eventmanager_pending_re; -wire soc_litedramcore_timer_eventmanager_pending_r; -wire soc_litedramcore_timer_eventmanager_pending_we; -wire soc_litedramcore_timer_eventmanager_pending_w; -reg soc_litedramcore_timer_eventmanager_storage = 1'd0; -reg soc_litedramcore_timer_eventmanager_re = 1'd0; -reg [31:0] soc_litedramcore_timer_value = 32'd0; -reg [13:0] soc_litedramcore_interface_adr = 14'd0; -reg soc_litedramcore_interface_we = 1'd0; -wire [7:0] soc_litedramcore_interface_dat_w; -wire [7:0] soc_litedramcore_interface_dat_r; -wire [29:0] soc_litedramcore_bus_wishbone_adr; -wire [31:0] soc_litedramcore_bus_wishbone_dat_w; -wire [31:0] soc_litedramcore_bus_wishbone_dat_r; -wire [3:0] soc_litedramcore_bus_wishbone_sel; -wire soc_litedramcore_bus_wishbone_cyc; -wire soc_litedramcore_bus_wishbone_stb; -reg soc_litedramcore_bus_wishbone_ack = 1'd0; -wire soc_litedramcore_bus_wishbone_we; -wire [2:0] soc_litedramcore_bus_wishbone_cti; -wire [1:0] soc_litedramcore_bus_wishbone_bte; -reg soc_litedramcore_bus_wishbone_err = 1'd0; wire sys_clk; wire sys_rst; wire sys4x_clk; wire sys4x_dqs_clk; wire iodelay_clk; wire iodelay_rst; -wire soc_sys_pll_reset; -wire soc_sys_pll_locked; -wire soc_s7pll0_clkin; -wire soc_s7pll0_clkout0; -wire soc_s7pll0_clkout_buf0; -wire soc_s7pll0_clkout1; -wire soc_s7pll0_clkout_buf1; -wire soc_s7pll0_clkout2; -wire soc_s7pll0_clkout_buf2; -wire soc_iodelay_pll_reset; -wire soc_iodelay_pll_locked; -wire soc_s7pll1_clkin; -wire soc_s7pll1_clkout; -wire soc_s7pll1_clkout_buf; -reg [3:0] soc_reset_counter = 4'd15; -reg soc_ic_reset = 1'd1; -reg [4:0] soc_a7ddrphy_half_sys8x_taps_storage = 5'd8; -reg soc_a7ddrphy_half_sys8x_taps_re = 1'd0; -reg soc_a7ddrphy_wlevel_en_storage = 1'd0; -reg soc_a7ddrphy_wlevel_en_re = 1'd0; -wire soc_a7ddrphy_wlevel_strobe_re; -wire soc_a7ddrphy_wlevel_strobe_r; -wire soc_a7ddrphy_wlevel_strobe_we; -reg soc_a7ddrphy_wlevel_strobe_w = 1'd0; -wire soc_a7ddrphy_cdly_rst_re; -wire soc_a7ddrphy_cdly_rst_r; -wire soc_a7ddrphy_cdly_rst_we; -reg soc_a7ddrphy_cdly_rst_w = 1'd0; -wire soc_a7ddrphy_cdly_inc_re; -wire soc_a7ddrphy_cdly_inc_r; -wire soc_a7ddrphy_cdly_inc_we; -reg soc_a7ddrphy_cdly_inc_w = 1'd0; -reg [1:0] soc_a7ddrphy_dly_sel_storage = 2'd0; -reg soc_a7ddrphy_dly_sel_re = 1'd0; -wire soc_a7ddrphy_rdly_dq_rst_re; -wire soc_a7ddrphy_rdly_dq_rst_r; -wire soc_a7ddrphy_rdly_dq_rst_we; -reg soc_a7ddrphy_rdly_dq_rst_w = 1'd0; -wire soc_a7ddrphy_rdly_dq_inc_re; -wire soc_a7ddrphy_rdly_dq_inc_r; -wire soc_a7ddrphy_rdly_dq_inc_we; -reg soc_a7ddrphy_rdly_dq_inc_w = 1'd0; -wire soc_a7ddrphy_rdly_dq_bitslip_rst_re; -wire soc_a7ddrphy_rdly_dq_bitslip_rst_r; -wire soc_a7ddrphy_rdly_dq_bitslip_rst_we; -reg soc_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -wire soc_a7ddrphy_rdly_dq_bitslip_re; -wire soc_a7ddrphy_rdly_dq_bitslip_r; -wire soc_a7ddrphy_rdly_dq_bitslip_we; -reg soc_a7ddrphy_rdly_dq_bitslip_w = 1'd0; -wire [13:0] soc_a7ddrphy_dfi_p0_address; -wire [2:0] soc_a7ddrphy_dfi_p0_bank; -wire soc_a7ddrphy_dfi_p0_cas_n; -wire soc_a7ddrphy_dfi_p0_cs_n; -wire soc_a7ddrphy_dfi_p0_ras_n; -wire soc_a7ddrphy_dfi_p0_we_n; -wire soc_a7ddrphy_dfi_p0_cke; -wire soc_a7ddrphy_dfi_p0_odt; -wire soc_a7ddrphy_dfi_p0_reset_n; -wire soc_a7ddrphy_dfi_p0_act_n; -wire [31:0] soc_a7ddrphy_dfi_p0_wrdata; -wire soc_a7ddrphy_dfi_p0_wrdata_en; -wire [3:0] soc_a7ddrphy_dfi_p0_wrdata_mask; -wire soc_a7ddrphy_dfi_p0_rddata_en; -reg [31:0] soc_a7ddrphy_dfi_p0_rddata = 32'd0; -reg soc_a7ddrphy_dfi_p0_rddata_valid = 1'd0; -wire [13:0] soc_a7ddrphy_dfi_p1_address; -wire [2:0] soc_a7ddrphy_dfi_p1_bank; -wire soc_a7ddrphy_dfi_p1_cas_n; -wire soc_a7ddrphy_dfi_p1_cs_n; -wire soc_a7ddrphy_dfi_p1_ras_n; -wire soc_a7ddrphy_dfi_p1_we_n; -wire soc_a7ddrphy_dfi_p1_cke; -wire soc_a7ddrphy_dfi_p1_odt; -wire soc_a7ddrphy_dfi_p1_reset_n; -wire soc_a7ddrphy_dfi_p1_act_n; -wire [31:0] soc_a7ddrphy_dfi_p1_wrdata; -wire soc_a7ddrphy_dfi_p1_wrdata_en; -wire [3:0] soc_a7ddrphy_dfi_p1_wrdata_mask; -wire soc_a7ddrphy_dfi_p1_rddata_en; -reg [31:0] soc_a7ddrphy_dfi_p1_rddata = 32'd0; -reg soc_a7ddrphy_dfi_p1_rddata_valid = 1'd0; -wire [13:0] soc_a7ddrphy_dfi_p2_address; -wire [2:0] soc_a7ddrphy_dfi_p2_bank; -wire soc_a7ddrphy_dfi_p2_cas_n; -wire soc_a7ddrphy_dfi_p2_cs_n; -wire soc_a7ddrphy_dfi_p2_ras_n; -wire soc_a7ddrphy_dfi_p2_we_n; -wire soc_a7ddrphy_dfi_p2_cke; -wire soc_a7ddrphy_dfi_p2_odt; -wire soc_a7ddrphy_dfi_p2_reset_n; -wire soc_a7ddrphy_dfi_p2_act_n; -wire [31:0] soc_a7ddrphy_dfi_p2_wrdata; -wire soc_a7ddrphy_dfi_p2_wrdata_en; -wire [3:0] soc_a7ddrphy_dfi_p2_wrdata_mask; -wire soc_a7ddrphy_dfi_p2_rddata_en; -reg [31:0] soc_a7ddrphy_dfi_p2_rddata = 32'd0; -reg soc_a7ddrphy_dfi_p2_rddata_valid = 1'd0; -wire [13:0] soc_a7ddrphy_dfi_p3_address; -wire [2:0] soc_a7ddrphy_dfi_p3_bank; -wire soc_a7ddrphy_dfi_p3_cas_n; -wire soc_a7ddrphy_dfi_p3_cs_n; -wire soc_a7ddrphy_dfi_p3_ras_n; -wire soc_a7ddrphy_dfi_p3_we_n; -wire soc_a7ddrphy_dfi_p3_cke; -wire soc_a7ddrphy_dfi_p3_odt; -wire soc_a7ddrphy_dfi_p3_reset_n; -wire soc_a7ddrphy_dfi_p3_act_n; -wire [31:0] soc_a7ddrphy_dfi_p3_wrdata; -wire soc_a7ddrphy_dfi_p3_wrdata_en; -wire [3:0] soc_a7ddrphy_dfi_p3_wrdata_mask; -wire soc_a7ddrphy_dfi_p3_rddata_en; -reg [31:0] soc_a7ddrphy_dfi_p3_rddata = 32'd0; -reg soc_a7ddrphy_dfi_p3_rddata_valid = 1'd0; -wire soc_a7ddrphy_sd_clk_se_nodelay; -reg soc_a7ddrphy_dqs_oe = 1'd0; -reg soc_a7ddrphy_dqs_oe_delayed = 1'd0; -wire soc_a7ddrphy_dqspattern0; -wire soc_a7ddrphy_dqspattern1; -reg [7:0] soc_a7ddrphy_dqspattern_o0 = 8'd0; -reg [7:0] soc_a7ddrphy_dqspattern_o1 = 8'd0; -wire [1:0] soc_a7ddrphy_dqs_i; -wire [1:0] soc_a7ddrphy_dqs_i_delayed; -wire soc_a7ddrphy_dqs_o_no_delay0; -wire soc_a7ddrphy_dqs_t0; -wire soc_a7ddrphy0; -wire soc_a7ddrphy_dqs_o_no_delay1; -wire soc_a7ddrphy_dqs_t1; -wire soc_a7ddrphy1; -wire soc_a7ddrphy_dq_oe; -reg soc_a7ddrphy_dq_oe_delayed = 1'd0; -wire soc_a7ddrphy_dq_o_nodelay0; -wire soc_a7ddrphy_dq_i_nodelay0; -wire soc_a7ddrphy_dq_i_delayed0; -wire soc_a7ddrphy_dq_t0; -wire [7:0] soc_a7ddrphy_dq_i_data0; -wire [7:0] soc_a7ddrphy_bitslip0_i; -reg [7:0] soc_a7ddrphy_bitslip0_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip0_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip0_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay1; -wire soc_a7ddrphy_dq_i_nodelay1; -wire soc_a7ddrphy_dq_i_delayed1; -wire soc_a7ddrphy_dq_t1; -wire [7:0] soc_a7ddrphy_dq_i_data1; -wire [7:0] soc_a7ddrphy_bitslip1_i; -reg [7:0] soc_a7ddrphy_bitslip1_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip1_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip1_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay2; -wire soc_a7ddrphy_dq_i_nodelay2; -wire soc_a7ddrphy_dq_i_delayed2; -wire soc_a7ddrphy_dq_t2; -wire [7:0] soc_a7ddrphy_dq_i_data2; -wire [7:0] soc_a7ddrphy_bitslip2_i; -reg [7:0] soc_a7ddrphy_bitslip2_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip2_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip2_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay3; -wire soc_a7ddrphy_dq_i_nodelay3; -wire soc_a7ddrphy_dq_i_delayed3; -wire soc_a7ddrphy_dq_t3; -wire [7:0] soc_a7ddrphy_dq_i_data3; -wire [7:0] soc_a7ddrphy_bitslip3_i; -reg [7:0] soc_a7ddrphy_bitslip3_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip3_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip3_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay4; -wire soc_a7ddrphy_dq_i_nodelay4; -wire soc_a7ddrphy_dq_i_delayed4; -wire soc_a7ddrphy_dq_t4; -wire [7:0] soc_a7ddrphy_dq_i_data4; -wire [7:0] soc_a7ddrphy_bitslip4_i; -reg [7:0] soc_a7ddrphy_bitslip4_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip4_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip4_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay5; -wire soc_a7ddrphy_dq_i_nodelay5; -wire soc_a7ddrphy_dq_i_delayed5; -wire soc_a7ddrphy_dq_t5; -wire [7:0] soc_a7ddrphy_dq_i_data5; -wire [7:0] soc_a7ddrphy_bitslip5_i; -reg [7:0] soc_a7ddrphy_bitslip5_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip5_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip5_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay6; -wire soc_a7ddrphy_dq_i_nodelay6; -wire soc_a7ddrphy_dq_i_delayed6; -wire soc_a7ddrphy_dq_t6; -wire [7:0] soc_a7ddrphy_dq_i_data6; -wire [7:0] soc_a7ddrphy_bitslip6_i; -reg [7:0] soc_a7ddrphy_bitslip6_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip6_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip6_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay7; -wire soc_a7ddrphy_dq_i_nodelay7; -wire soc_a7ddrphy_dq_i_delayed7; -wire soc_a7ddrphy_dq_t7; -wire [7:0] soc_a7ddrphy_dq_i_data7; -wire [7:0] soc_a7ddrphy_bitslip7_i; -reg [7:0] soc_a7ddrphy_bitslip7_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip7_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip7_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay8; -wire soc_a7ddrphy_dq_i_nodelay8; -wire soc_a7ddrphy_dq_i_delayed8; -wire soc_a7ddrphy_dq_t8; -wire [7:0] soc_a7ddrphy_dq_i_data8; -wire [7:0] soc_a7ddrphy_bitslip8_i; -reg [7:0] soc_a7ddrphy_bitslip8_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip8_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip8_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay9; -wire soc_a7ddrphy_dq_i_nodelay9; -wire soc_a7ddrphy_dq_i_delayed9; -wire soc_a7ddrphy_dq_t9; -wire [7:0] soc_a7ddrphy_dq_i_data9; -wire [7:0] soc_a7ddrphy_bitslip9_i; -reg [7:0] soc_a7ddrphy_bitslip9_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip9_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip9_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay10; -wire soc_a7ddrphy_dq_i_nodelay10; -wire soc_a7ddrphy_dq_i_delayed10; -wire soc_a7ddrphy_dq_t10; -wire [7:0] soc_a7ddrphy_dq_i_data10; -wire [7:0] soc_a7ddrphy_bitslip10_i; -reg [7:0] soc_a7ddrphy_bitslip10_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip10_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip10_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay11; -wire soc_a7ddrphy_dq_i_nodelay11; -wire soc_a7ddrphy_dq_i_delayed11; -wire soc_a7ddrphy_dq_t11; -wire [7:0] soc_a7ddrphy_dq_i_data11; -wire [7:0] soc_a7ddrphy_bitslip11_i; -reg [7:0] soc_a7ddrphy_bitslip11_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip11_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip11_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay12; -wire soc_a7ddrphy_dq_i_nodelay12; -wire soc_a7ddrphy_dq_i_delayed12; -wire soc_a7ddrphy_dq_t12; -wire [7:0] soc_a7ddrphy_dq_i_data12; -wire [7:0] soc_a7ddrphy_bitslip12_i; -reg [7:0] soc_a7ddrphy_bitslip12_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip12_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip12_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay13; -wire soc_a7ddrphy_dq_i_nodelay13; -wire soc_a7ddrphy_dq_i_delayed13; -wire soc_a7ddrphy_dq_t13; -wire [7:0] soc_a7ddrphy_dq_i_data13; -wire [7:0] soc_a7ddrphy_bitslip13_i; -reg [7:0] soc_a7ddrphy_bitslip13_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip13_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip13_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay14; -wire soc_a7ddrphy_dq_i_nodelay14; -wire soc_a7ddrphy_dq_i_delayed14; -wire soc_a7ddrphy_dq_t14; -wire [7:0] soc_a7ddrphy_dq_i_data14; -wire [7:0] soc_a7ddrphy_bitslip14_i; -reg [7:0] soc_a7ddrphy_bitslip14_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip14_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip14_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay15; -wire soc_a7ddrphy_dq_i_nodelay15; -wire soc_a7ddrphy_dq_i_delayed15; -wire soc_a7ddrphy_dq_t15; -wire [7:0] soc_a7ddrphy_dq_i_data15; -wire [7:0] soc_a7ddrphy_bitslip15_i; -reg [7:0] soc_a7ddrphy_bitslip15_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip15_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip15_r = 16'd0; -wire [7:0] soc_a7ddrphy_rddata_en; -reg [7:0] soc_a7ddrphy_rddata_en_last = 8'd0; -wire [3:0] soc_a7ddrphy_wrdata_en; -reg [3:0] soc_a7ddrphy_wrdata_en_last = 4'd0; -wire [13:0] soc_sdram_inti_p0_address; -wire [2:0] soc_sdram_inti_p0_bank; -reg soc_sdram_inti_p0_cas_n = 1'd1; -reg soc_sdram_inti_p0_cs_n = 1'd1; -reg soc_sdram_inti_p0_ras_n = 1'd1; -reg soc_sdram_inti_p0_we_n = 1'd1; -wire soc_sdram_inti_p0_cke; -wire soc_sdram_inti_p0_odt; -wire soc_sdram_inti_p0_reset_n; -reg soc_sdram_inti_p0_act_n = 1'd1; -wire [31:0] soc_sdram_inti_p0_wrdata; -wire soc_sdram_inti_p0_wrdata_en; -wire [3:0] soc_sdram_inti_p0_wrdata_mask; -wire soc_sdram_inti_p0_rddata_en; -reg [31:0] soc_sdram_inti_p0_rddata = 32'd0; -reg soc_sdram_inti_p0_rddata_valid = 1'd0; -wire [13:0] soc_sdram_inti_p1_address; -wire [2:0] soc_sdram_inti_p1_bank; -reg soc_sdram_inti_p1_cas_n = 1'd1; -reg soc_sdram_inti_p1_cs_n = 1'd1; -reg soc_sdram_inti_p1_ras_n = 1'd1; -reg soc_sdram_inti_p1_we_n = 1'd1; -wire soc_sdram_inti_p1_cke; -wire soc_sdram_inti_p1_odt; -wire soc_sdram_inti_p1_reset_n; -reg soc_sdram_inti_p1_act_n = 1'd1; -wire [31:0] soc_sdram_inti_p1_wrdata; -wire soc_sdram_inti_p1_wrdata_en; -wire [3:0] soc_sdram_inti_p1_wrdata_mask; -wire soc_sdram_inti_p1_rddata_en; -reg [31:0] soc_sdram_inti_p1_rddata = 32'd0; -reg soc_sdram_inti_p1_rddata_valid = 1'd0; -wire [13:0] soc_sdram_inti_p2_address; -wire [2:0] soc_sdram_inti_p2_bank; -reg soc_sdram_inti_p2_cas_n = 1'd1; -reg soc_sdram_inti_p2_cs_n = 1'd1; -reg soc_sdram_inti_p2_ras_n = 1'd1; -reg soc_sdram_inti_p2_we_n = 1'd1; -wire soc_sdram_inti_p2_cke; -wire soc_sdram_inti_p2_odt; -wire soc_sdram_inti_p2_reset_n; -reg soc_sdram_inti_p2_act_n = 1'd1; -wire [31:0] soc_sdram_inti_p2_wrdata; -wire soc_sdram_inti_p2_wrdata_en; -wire [3:0] soc_sdram_inti_p2_wrdata_mask; -wire soc_sdram_inti_p2_rddata_en; -reg [31:0] soc_sdram_inti_p2_rddata = 32'd0; -reg soc_sdram_inti_p2_rddata_valid = 1'd0; -wire [13:0] soc_sdram_inti_p3_address; -wire [2:0] soc_sdram_inti_p3_bank; -reg soc_sdram_inti_p3_cas_n = 1'd1; -reg soc_sdram_inti_p3_cs_n = 1'd1; -reg soc_sdram_inti_p3_ras_n = 1'd1; -reg soc_sdram_inti_p3_we_n = 1'd1; -wire soc_sdram_inti_p3_cke; -wire soc_sdram_inti_p3_odt; -wire soc_sdram_inti_p3_reset_n; -reg soc_sdram_inti_p3_act_n = 1'd1; -wire [31:0] soc_sdram_inti_p3_wrdata; -wire soc_sdram_inti_p3_wrdata_en; -wire [3:0] soc_sdram_inti_p3_wrdata_mask; -wire soc_sdram_inti_p3_rddata_en; -reg [31:0] soc_sdram_inti_p3_rddata = 32'd0; -reg soc_sdram_inti_p3_rddata_valid = 1'd0; -wire [13:0] soc_sdram_slave_p0_address; -wire [2:0] soc_sdram_slave_p0_bank; -wire soc_sdram_slave_p0_cas_n; -wire soc_sdram_slave_p0_cs_n; -wire soc_sdram_slave_p0_ras_n; -wire soc_sdram_slave_p0_we_n; -wire soc_sdram_slave_p0_cke; -wire soc_sdram_slave_p0_odt; -wire soc_sdram_slave_p0_reset_n; -wire soc_sdram_slave_p0_act_n; -wire [31:0] soc_sdram_slave_p0_wrdata; -wire soc_sdram_slave_p0_wrdata_en; -wire [3:0] soc_sdram_slave_p0_wrdata_mask; -wire soc_sdram_slave_p0_rddata_en; -reg [31:0] soc_sdram_slave_p0_rddata = 32'd0; -reg soc_sdram_slave_p0_rddata_valid = 1'd0; -wire [13:0] soc_sdram_slave_p1_address; -wire [2:0] soc_sdram_slave_p1_bank; -wire soc_sdram_slave_p1_cas_n; -wire soc_sdram_slave_p1_cs_n; -wire soc_sdram_slave_p1_ras_n; -wire soc_sdram_slave_p1_we_n; -wire soc_sdram_slave_p1_cke; -wire soc_sdram_slave_p1_odt; -wire soc_sdram_slave_p1_reset_n; -wire soc_sdram_slave_p1_act_n; -wire [31:0] soc_sdram_slave_p1_wrdata; -wire soc_sdram_slave_p1_wrdata_en; -wire [3:0] soc_sdram_slave_p1_wrdata_mask; -wire soc_sdram_slave_p1_rddata_en; -reg [31:0] soc_sdram_slave_p1_rddata = 32'd0; -reg soc_sdram_slave_p1_rddata_valid = 1'd0; -wire [13:0] soc_sdram_slave_p2_address; -wire [2:0] soc_sdram_slave_p2_bank; -wire soc_sdram_slave_p2_cas_n; -wire soc_sdram_slave_p2_cs_n; -wire soc_sdram_slave_p2_ras_n; -wire soc_sdram_slave_p2_we_n; -wire soc_sdram_slave_p2_cke; -wire soc_sdram_slave_p2_odt; -wire soc_sdram_slave_p2_reset_n; -wire soc_sdram_slave_p2_act_n; -wire [31:0] soc_sdram_slave_p2_wrdata; -wire soc_sdram_slave_p2_wrdata_en; -wire [3:0] soc_sdram_slave_p2_wrdata_mask; -wire soc_sdram_slave_p2_rddata_en; -reg [31:0] soc_sdram_slave_p2_rddata = 32'd0; -reg soc_sdram_slave_p2_rddata_valid = 1'd0; -wire [13:0] soc_sdram_slave_p3_address; -wire [2:0] soc_sdram_slave_p3_bank; -wire soc_sdram_slave_p3_cas_n; -wire soc_sdram_slave_p3_cs_n; -wire soc_sdram_slave_p3_ras_n; -wire soc_sdram_slave_p3_we_n; -wire soc_sdram_slave_p3_cke; -wire soc_sdram_slave_p3_odt; -wire soc_sdram_slave_p3_reset_n; -wire soc_sdram_slave_p3_act_n; -wire [31:0] soc_sdram_slave_p3_wrdata; -wire soc_sdram_slave_p3_wrdata_en; -wire [3:0] soc_sdram_slave_p3_wrdata_mask; -wire soc_sdram_slave_p3_rddata_en; -reg [31:0] soc_sdram_slave_p3_rddata = 32'd0; -reg soc_sdram_slave_p3_rddata_valid = 1'd0; -reg [13:0] soc_sdram_master_p0_address = 14'd0; -reg [2:0] soc_sdram_master_p0_bank = 3'd0; -reg soc_sdram_master_p0_cas_n = 1'd1; -reg soc_sdram_master_p0_cs_n = 1'd1; -reg soc_sdram_master_p0_ras_n = 1'd1; -reg soc_sdram_master_p0_we_n = 1'd1; -reg soc_sdram_master_p0_cke = 1'd0; -reg soc_sdram_master_p0_odt = 1'd0; -reg soc_sdram_master_p0_reset_n = 1'd0; -reg soc_sdram_master_p0_act_n = 1'd1; -reg [31:0] soc_sdram_master_p0_wrdata = 32'd0; -reg soc_sdram_master_p0_wrdata_en = 1'd0; -reg [3:0] soc_sdram_master_p0_wrdata_mask = 4'd0; -reg soc_sdram_master_p0_rddata_en = 1'd0; -wire [31:0] soc_sdram_master_p0_rddata; -wire soc_sdram_master_p0_rddata_valid; -reg [13:0] soc_sdram_master_p1_address = 14'd0; -reg [2:0] soc_sdram_master_p1_bank = 3'd0; -reg soc_sdram_master_p1_cas_n = 1'd1; -reg soc_sdram_master_p1_cs_n = 1'd1; -reg soc_sdram_master_p1_ras_n = 1'd1; -reg soc_sdram_master_p1_we_n = 1'd1; -reg soc_sdram_master_p1_cke = 1'd0; -reg soc_sdram_master_p1_odt = 1'd0; -reg soc_sdram_master_p1_reset_n = 1'd0; -reg soc_sdram_master_p1_act_n = 1'd1; -reg [31:0] soc_sdram_master_p1_wrdata = 32'd0; -reg soc_sdram_master_p1_wrdata_en = 1'd0; -reg [3:0] soc_sdram_master_p1_wrdata_mask = 4'd0; -reg soc_sdram_master_p1_rddata_en = 1'd0; -wire [31:0] soc_sdram_master_p1_rddata; -wire soc_sdram_master_p1_rddata_valid; -reg [13:0] soc_sdram_master_p2_address = 14'd0; -reg [2:0] soc_sdram_master_p2_bank = 3'd0; -reg soc_sdram_master_p2_cas_n = 1'd1; -reg soc_sdram_master_p2_cs_n = 1'd1; -reg soc_sdram_master_p2_ras_n = 1'd1; -reg soc_sdram_master_p2_we_n = 1'd1; -reg soc_sdram_master_p2_cke = 1'd0; -reg soc_sdram_master_p2_odt = 1'd0; -reg soc_sdram_master_p2_reset_n = 1'd0; -reg soc_sdram_master_p2_act_n = 1'd1; -reg [31:0] soc_sdram_master_p2_wrdata = 32'd0; -reg soc_sdram_master_p2_wrdata_en = 1'd0; -reg [3:0] soc_sdram_master_p2_wrdata_mask = 4'd0; -reg soc_sdram_master_p2_rddata_en = 1'd0; -wire [31:0] soc_sdram_master_p2_rddata; -wire soc_sdram_master_p2_rddata_valid; -reg [13:0] soc_sdram_master_p3_address = 14'd0; -reg [2:0] soc_sdram_master_p3_bank = 3'd0; -reg soc_sdram_master_p3_cas_n = 1'd1; -reg soc_sdram_master_p3_cs_n = 1'd1; -reg soc_sdram_master_p3_ras_n = 1'd1; -reg soc_sdram_master_p3_we_n = 1'd1; -reg soc_sdram_master_p3_cke = 1'd0; -reg soc_sdram_master_p3_odt = 1'd0; -reg soc_sdram_master_p3_reset_n = 1'd0; -reg soc_sdram_master_p3_act_n = 1'd1; -reg [31:0] soc_sdram_master_p3_wrdata = 32'd0; -reg soc_sdram_master_p3_wrdata_en = 1'd0; -reg [3:0] soc_sdram_master_p3_wrdata_mask = 4'd0; -reg soc_sdram_master_p3_rddata_en = 1'd0; -wire [31:0] soc_sdram_master_p3_rddata; -wire soc_sdram_master_p3_rddata_valid; -reg [3:0] soc_sdram_storage = 4'd0; -reg soc_sdram_re = 1'd0; -reg [5:0] soc_sdram_phaseinjector0_command_storage = 6'd0; -reg soc_sdram_phaseinjector0_command_re = 1'd0; -wire soc_sdram_phaseinjector0_command_issue_re; -wire soc_sdram_phaseinjector0_command_issue_r; -wire soc_sdram_phaseinjector0_command_issue_we; -reg soc_sdram_phaseinjector0_command_issue_w = 1'd0; -reg [13:0] soc_sdram_phaseinjector0_address_storage = 14'd0; -reg soc_sdram_phaseinjector0_address_re = 1'd0; -reg [2:0] soc_sdram_phaseinjector0_baddress_storage = 3'd0; -reg soc_sdram_phaseinjector0_baddress_re = 1'd0; -reg [31:0] soc_sdram_phaseinjector0_wrdata_storage = 32'd0; -reg soc_sdram_phaseinjector0_wrdata_re = 1'd0; -reg [31:0] soc_sdram_phaseinjector0_status = 32'd0; -wire soc_sdram_phaseinjector0_we; -reg [5:0] soc_sdram_phaseinjector1_command_storage = 6'd0; -reg soc_sdram_phaseinjector1_command_re = 1'd0; -wire soc_sdram_phaseinjector1_command_issue_re; -wire soc_sdram_phaseinjector1_command_issue_r; -wire soc_sdram_phaseinjector1_command_issue_we; -reg soc_sdram_phaseinjector1_command_issue_w = 1'd0; -reg [13:0] soc_sdram_phaseinjector1_address_storage = 14'd0; -reg soc_sdram_phaseinjector1_address_re = 1'd0; -reg [2:0] soc_sdram_phaseinjector1_baddress_storage = 3'd0; -reg soc_sdram_phaseinjector1_baddress_re = 1'd0; -reg [31:0] soc_sdram_phaseinjector1_wrdata_storage = 32'd0; -reg soc_sdram_phaseinjector1_wrdata_re = 1'd0; -reg [31:0] soc_sdram_phaseinjector1_status = 32'd0; -wire soc_sdram_phaseinjector1_we; -reg [5:0] soc_sdram_phaseinjector2_command_storage = 6'd0; -reg soc_sdram_phaseinjector2_command_re = 1'd0; -wire soc_sdram_phaseinjector2_command_issue_re; -wire soc_sdram_phaseinjector2_command_issue_r; -wire soc_sdram_phaseinjector2_command_issue_we; -reg soc_sdram_phaseinjector2_command_issue_w = 1'd0; -reg [13:0] soc_sdram_phaseinjector2_address_storage = 14'd0; -reg soc_sdram_phaseinjector2_address_re = 1'd0; -reg [2:0] soc_sdram_phaseinjector2_baddress_storage = 3'd0; -reg soc_sdram_phaseinjector2_baddress_re = 1'd0; -reg [31:0] soc_sdram_phaseinjector2_wrdata_storage = 32'd0; -reg soc_sdram_phaseinjector2_wrdata_re = 1'd0; -reg [31:0] soc_sdram_phaseinjector2_status = 32'd0; -wire soc_sdram_phaseinjector2_we; -reg [5:0] soc_sdram_phaseinjector3_command_storage = 6'd0; -reg soc_sdram_phaseinjector3_command_re = 1'd0; -wire soc_sdram_phaseinjector3_command_issue_re; -wire soc_sdram_phaseinjector3_command_issue_r; -wire soc_sdram_phaseinjector3_command_issue_we; -reg soc_sdram_phaseinjector3_command_issue_w = 1'd0; -reg [13:0] soc_sdram_phaseinjector3_address_storage = 14'd0; -reg soc_sdram_phaseinjector3_address_re = 1'd0; -reg [2:0] soc_sdram_phaseinjector3_baddress_storage = 3'd0; -reg soc_sdram_phaseinjector3_baddress_re = 1'd0; -reg [31:0] soc_sdram_phaseinjector3_wrdata_storage = 32'd0; -reg soc_sdram_phaseinjector3_wrdata_re = 1'd0; -reg [31:0] soc_sdram_phaseinjector3_status = 32'd0; -wire soc_sdram_phaseinjector3_we; -wire soc_sdram_interface_bank0_valid; -wire soc_sdram_interface_bank0_ready; -wire soc_sdram_interface_bank0_we; -wire [20:0] soc_sdram_interface_bank0_addr; -wire soc_sdram_interface_bank0_lock; -wire soc_sdram_interface_bank0_wdata_ready; -wire soc_sdram_interface_bank0_rdata_valid; -wire soc_sdram_interface_bank1_valid; -wire soc_sdram_interface_bank1_ready; -wire soc_sdram_interface_bank1_we; -wire [20:0] soc_sdram_interface_bank1_addr; -wire soc_sdram_interface_bank1_lock; -wire soc_sdram_interface_bank1_wdata_ready; -wire soc_sdram_interface_bank1_rdata_valid; -wire soc_sdram_interface_bank2_valid; -wire soc_sdram_interface_bank2_ready; -wire soc_sdram_interface_bank2_we; -wire [20:0] soc_sdram_interface_bank2_addr; -wire soc_sdram_interface_bank2_lock; -wire soc_sdram_interface_bank2_wdata_ready; -wire soc_sdram_interface_bank2_rdata_valid; -wire soc_sdram_interface_bank3_valid; -wire soc_sdram_interface_bank3_ready; -wire soc_sdram_interface_bank3_we; -wire [20:0] soc_sdram_interface_bank3_addr; -wire soc_sdram_interface_bank3_lock; -wire soc_sdram_interface_bank3_wdata_ready; -wire soc_sdram_interface_bank3_rdata_valid; -wire soc_sdram_interface_bank4_valid; -wire soc_sdram_interface_bank4_ready; -wire soc_sdram_interface_bank4_we; -wire [20:0] soc_sdram_interface_bank4_addr; -wire soc_sdram_interface_bank4_lock; -wire soc_sdram_interface_bank4_wdata_ready; -wire soc_sdram_interface_bank4_rdata_valid; -wire soc_sdram_interface_bank5_valid; -wire soc_sdram_interface_bank5_ready; -wire soc_sdram_interface_bank5_we; -wire [20:0] soc_sdram_interface_bank5_addr; -wire soc_sdram_interface_bank5_lock; -wire soc_sdram_interface_bank5_wdata_ready; -wire soc_sdram_interface_bank5_rdata_valid; -wire soc_sdram_interface_bank6_valid; -wire soc_sdram_interface_bank6_ready; -wire soc_sdram_interface_bank6_we; -wire [20:0] soc_sdram_interface_bank6_addr; -wire soc_sdram_interface_bank6_lock; -wire soc_sdram_interface_bank6_wdata_ready; -wire soc_sdram_interface_bank6_rdata_valid; -wire soc_sdram_interface_bank7_valid; -wire soc_sdram_interface_bank7_ready; -wire soc_sdram_interface_bank7_we; -wire [20:0] soc_sdram_interface_bank7_addr; -wire soc_sdram_interface_bank7_lock; -wire soc_sdram_interface_bank7_wdata_ready; -wire soc_sdram_interface_bank7_rdata_valid; -reg [127:0] soc_sdram_interface_wdata = 128'd0; -reg [15:0] soc_sdram_interface_wdata_we = 16'd0; -wire [127:0] soc_sdram_interface_rdata; -reg [13:0] soc_sdram_dfi_p0_address = 14'd0; -reg [2:0] soc_sdram_dfi_p0_bank = 3'd0; -reg soc_sdram_dfi_p0_cas_n = 1'd1; -reg soc_sdram_dfi_p0_cs_n = 1'd1; -reg soc_sdram_dfi_p0_ras_n = 1'd1; -reg soc_sdram_dfi_p0_we_n = 1'd1; -wire soc_sdram_dfi_p0_cke; -wire soc_sdram_dfi_p0_odt; -wire soc_sdram_dfi_p0_reset_n; -reg soc_sdram_dfi_p0_act_n = 1'd1; -wire [31:0] soc_sdram_dfi_p0_wrdata; -reg soc_sdram_dfi_p0_wrdata_en = 1'd0; -wire [3:0] soc_sdram_dfi_p0_wrdata_mask; -reg soc_sdram_dfi_p0_rddata_en = 1'd0; -wire [31:0] soc_sdram_dfi_p0_rddata; -wire soc_sdram_dfi_p0_rddata_valid; -reg [13:0] soc_sdram_dfi_p1_address = 14'd0; -reg [2:0] soc_sdram_dfi_p1_bank = 3'd0; -reg soc_sdram_dfi_p1_cas_n = 1'd1; -reg soc_sdram_dfi_p1_cs_n = 1'd1; -reg soc_sdram_dfi_p1_ras_n = 1'd1; -reg soc_sdram_dfi_p1_we_n = 1'd1; -wire soc_sdram_dfi_p1_cke; -wire soc_sdram_dfi_p1_odt; -wire soc_sdram_dfi_p1_reset_n; -reg soc_sdram_dfi_p1_act_n = 1'd1; -wire [31:0] soc_sdram_dfi_p1_wrdata; -reg soc_sdram_dfi_p1_wrdata_en = 1'd0; -wire [3:0] soc_sdram_dfi_p1_wrdata_mask; -reg soc_sdram_dfi_p1_rddata_en = 1'd0; -wire [31:0] soc_sdram_dfi_p1_rddata; -wire soc_sdram_dfi_p1_rddata_valid; -reg [13:0] soc_sdram_dfi_p2_address = 14'd0; -reg [2:0] soc_sdram_dfi_p2_bank = 3'd0; -reg soc_sdram_dfi_p2_cas_n = 1'd1; -reg soc_sdram_dfi_p2_cs_n = 1'd1; -reg soc_sdram_dfi_p2_ras_n = 1'd1; -reg soc_sdram_dfi_p2_we_n = 1'd1; -wire soc_sdram_dfi_p2_cke; -wire soc_sdram_dfi_p2_odt; -wire soc_sdram_dfi_p2_reset_n; -reg soc_sdram_dfi_p2_act_n = 1'd1; -wire [31:0] soc_sdram_dfi_p2_wrdata; -reg soc_sdram_dfi_p2_wrdata_en = 1'd0; -wire [3:0] soc_sdram_dfi_p2_wrdata_mask; -reg soc_sdram_dfi_p2_rddata_en = 1'd0; -wire [31:0] soc_sdram_dfi_p2_rddata; -wire soc_sdram_dfi_p2_rddata_valid; -reg [13:0] soc_sdram_dfi_p3_address = 14'd0; -reg [2:0] soc_sdram_dfi_p3_bank = 3'd0; -reg soc_sdram_dfi_p3_cas_n = 1'd1; -reg soc_sdram_dfi_p3_cs_n = 1'd1; -reg soc_sdram_dfi_p3_ras_n = 1'd1; -reg soc_sdram_dfi_p3_we_n = 1'd1; -wire soc_sdram_dfi_p3_cke; -wire soc_sdram_dfi_p3_odt; -wire soc_sdram_dfi_p3_reset_n; -reg soc_sdram_dfi_p3_act_n = 1'd1; -wire [31:0] soc_sdram_dfi_p3_wrdata; -reg soc_sdram_dfi_p3_wrdata_en = 1'd0; -wire [3:0] soc_sdram_dfi_p3_wrdata_mask; -reg soc_sdram_dfi_p3_rddata_en = 1'd0; -wire [31:0] soc_sdram_dfi_p3_rddata; -wire soc_sdram_dfi_p3_rddata_valid; -reg soc_sdram_cmd_valid = 1'd0; -reg soc_sdram_cmd_ready = 1'd0; -reg soc_sdram_cmd_last = 1'd0; -reg [13:0] soc_sdram_cmd_payload_a = 14'd0; -reg [2:0] soc_sdram_cmd_payload_ba = 3'd0; -reg soc_sdram_cmd_payload_cas = 1'd0; -reg soc_sdram_cmd_payload_ras = 1'd0; -reg soc_sdram_cmd_payload_we = 1'd0; -reg soc_sdram_cmd_payload_is_read = 1'd0; -reg soc_sdram_cmd_payload_is_write = 1'd0; -wire soc_sdram_wants_refresh; -wire soc_sdram_wants_zqcs; -wire soc_sdram_timer_wait; -wire soc_sdram_timer_done0; -wire [9:0] soc_sdram_timer_count0; -wire soc_sdram_timer_done1; -reg [9:0] soc_sdram_timer_count1 = 10'd781; -wire soc_sdram_postponer_req_i; -reg soc_sdram_postponer_req_o = 1'd0; -reg soc_sdram_postponer_count = 1'd0; -reg soc_sdram_sequencer_start0 = 1'd0; -wire soc_sdram_sequencer_done0; -wire soc_sdram_sequencer_start1; -reg soc_sdram_sequencer_done1 = 1'd0; -reg [5:0] soc_sdram_sequencer_counter = 6'd0; -reg soc_sdram_sequencer_count = 1'd0; -wire soc_sdram_zqcs_timer_wait; -wire soc_sdram_zqcs_timer_done0; -wire [26:0] soc_sdram_zqcs_timer_count0; -wire soc_sdram_zqcs_timer_done1; -reg [26:0] soc_sdram_zqcs_timer_count1 = 27'd99999999; -reg soc_sdram_zqcs_executer_start = 1'd0; -reg soc_sdram_zqcs_executer_done = 1'd0; -reg [4:0] soc_sdram_zqcs_executer_counter = 5'd0; -wire soc_sdram_bankmachine0_req_valid; -wire soc_sdram_bankmachine0_req_ready; -wire soc_sdram_bankmachine0_req_we; -wire [20:0] soc_sdram_bankmachine0_req_addr; -wire soc_sdram_bankmachine0_req_lock; -reg soc_sdram_bankmachine0_req_wdata_ready = 1'd0; -reg soc_sdram_bankmachine0_req_rdata_valid = 1'd0; -wire soc_sdram_bankmachine0_refresh_req; -reg soc_sdram_bankmachine0_refresh_gnt = 1'd0; -reg soc_sdram_bankmachine0_cmd_valid = 1'd0; -reg soc_sdram_bankmachine0_cmd_ready = 1'd0; -reg [13:0] soc_sdram_bankmachine0_cmd_payload_a = 14'd0; -wire [2:0] soc_sdram_bankmachine0_cmd_payload_ba; -reg soc_sdram_bankmachine0_cmd_payload_cas = 1'd0; -reg soc_sdram_bankmachine0_cmd_payload_ras = 1'd0; -reg soc_sdram_bankmachine0_cmd_payload_we = 1'd0; -reg soc_sdram_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg soc_sdram_bankmachine0_cmd_payload_is_read = 1'd0; -reg soc_sdram_bankmachine0_cmd_payload_is_write = 1'd0; -reg soc_sdram_bankmachine0_auto_precharge = 1'd0; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready; -reg soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -wire [23:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -wire [23:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -reg [4:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_level = 5'd0; -reg soc_sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read; -wire [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -wire soc_sdram_bankmachine0_cmd_buffer_sink_valid; -wire soc_sdram_bankmachine0_cmd_buffer_sink_ready; -wire soc_sdram_bankmachine0_cmd_buffer_sink_first; -wire soc_sdram_bankmachine0_cmd_buffer_sink_last; -wire soc_sdram_bankmachine0_cmd_buffer_sink_payload_we; -wire [20:0] soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr; -reg soc_sdram_bankmachine0_cmd_buffer_source_valid = 1'd0; -wire soc_sdram_bankmachine0_cmd_buffer_source_ready; -reg soc_sdram_bankmachine0_cmd_buffer_source_first = 1'd0; -reg soc_sdram_bankmachine0_cmd_buffer_source_last = 1'd0; -reg soc_sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_sdram_bankmachine0_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_sdram_bankmachine0_row = 14'd0; -reg soc_sdram_bankmachine0_row_opened = 1'd0; -wire soc_sdram_bankmachine0_row_hit; -reg soc_sdram_bankmachine0_row_open = 1'd0; -reg soc_sdram_bankmachine0_row_close = 1'd0; -reg soc_sdram_bankmachine0_row_col_n_addr_sel = 1'd0; -wire soc_sdram_bankmachine0_twtpcon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine0_twtpcon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine0_twtpcon_count = 3'd0; -wire soc_sdram_bankmachine0_trccon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine0_trccon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine0_trccon_count = 3'd0; -wire soc_sdram_bankmachine0_trascon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine0_trascon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine0_trascon_count = 3'd0; -wire soc_sdram_bankmachine1_req_valid; -wire soc_sdram_bankmachine1_req_ready; -wire soc_sdram_bankmachine1_req_we; -wire [20:0] soc_sdram_bankmachine1_req_addr; -wire soc_sdram_bankmachine1_req_lock; -reg soc_sdram_bankmachine1_req_wdata_ready = 1'd0; -reg soc_sdram_bankmachine1_req_rdata_valid = 1'd0; -wire soc_sdram_bankmachine1_refresh_req; -reg soc_sdram_bankmachine1_refresh_gnt = 1'd0; -reg soc_sdram_bankmachine1_cmd_valid = 1'd0; -reg soc_sdram_bankmachine1_cmd_ready = 1'd0; -reg [13:0] soc_sdram_bankmachine1_cmd_payload_a = 14'd0; -wire [2:0] soc_sdram_bankmachine1_cmd_payload_ba; -reg soc_sdram_bankmachine1_cmd_payload_cas = 1'd0; -reg soc_sdram_bankmachine1_cmd_payload_ras = 1'd0; -reg soc_sdram_bankmachine1_cmd_payload_we = 1'd0; -reg soc_sdram_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg soc_sdram_bankmachine1_cmd_payload_is_read = 1'd0; -reg soc_sdram_bankmachine1_cmd_payload_is_write = 1'd0; -reg soc_sdram_bankmachine1_auto_precharge = 1'd0; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready; -reg soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -wire [23:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -wire [23:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -reg [4:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_level = 5'd0; -reg soc_sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read; -wire [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -wire soc_sdram_bankmachine1_cmd_buffer_sink_valid; -wire soc_sdram_bankmachine1_cmd_buffer_sink_ready; -wire soc_sdram_bankmachine1_cmd_buffer_sink_first; -wire soc_sdram_bankmachine1_cmd_buffer_sink_last; -wire soc_sdram_bankmachine1_cmd_buffer_sink_payload_we; -wire [20:0] soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr; -reg soc_sdram_bankmachine1_cmd_buffer_source_valid = 1'd0; -wire soc_sdram_bankmachine1_cmd_buffer_source_ready; -reg soc_sdram_bankmachine1_cmd_buffer_source_first = 1'd0; -reg soc_sdram_bankmachine1_cmd_buffer_source_last = 1'd0; -reg soc_sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_sdram_bankmachine1_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_sdram_bankmachine1_row = 14'd0; -reg soc_sdram_bankmachine1_row_opened = 1'd0; -wire soc_sdram_bankmachine1_row_hit; -reg soc_sdram_bankmachine1_row_open = 1'd0; -reg soc_sdram_bankmachine1_row_close = 1'd0; -reg soc_sdram_bankmachine1_row_col_n_addr_sel = 1'd0; -wire soc_sdram_bankmachine1_twtpcon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine1_twtpcon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine1_twtpcon_count = 3'd0; -wire soc_sdram_bankmachine1_trccon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine1_trccon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine1_trccon_count = 3'd0; -wire soc_sdram_bankmachine1_trascon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine1_trascon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine1_trascon_count = 3'd0; -wire soc_sdram_bankmachine2_req_valid; -wire soc_sdram_bankmachine2_req_ready; -wire soc_sdram_bankmachine2_req_we; -wire [20:0] soc_sdram_bankmachine2_req_addr; -wire soc_sdram_bankmachine2_req_lock; -reg soc_sdram_bankmachine2_req_wdata_ready = 1'd0; -reg soc_sdram_bankmachine2_req_rdata_valid = 1'd0; -wire soc_sdram_bankmachine2_refresh_req; -reg soc_sdram_bankmachine2_refresh_gnt = 1'd0; -reg soc_sdram_bankmachine2_cmd_valid = 1'd0; -reg soc_sdram_bankmachine2_cmd_ready = 1'd0; -reg [13:0] soc_sdram_bankmachine2_cmd_payload_a = 14'd0; -wire [2:0] soc_sdram_bankmachine2_cmd_payload_ba; -reg soc_sdram_bankmachine2_cmd_payload_cas = 1'd0; -reg soc_sdram_bankmachine2_cmd_payload_ras = 1'd0; -reg soc_sdram_bankmachine2_cmd_payload_we = 1'd0; -reg soc_sdram_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg soc_sdram_bankmachine2_cmd_payload_is_read = 1'd0; -reg soc_sdram_bankmachine2_cmd_payload_is_write = 1'd0; -reg soc_sdram_bankmachine2_auto_precharge = 1'd0; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready; -reg soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -wire [23:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -wire [23:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -reg [4:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_level = 5'd0; -reg soc_sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read; -wire [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -wire soc_sdram_bankmachine2_cmd_buffer_sink_valid; -wire soc_sdram_bankmachine2_cmd_buffer_sink_ready; -wire soc_sdram_bankmachine2_cmd_buffer_sink_first; -wire soc_sdram_bankmachine2_cmd_buffer_sink_last; -wire soc_sdram_bankmachine2_cmd_buffer_sink_payload_we; -wire [20:0] soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr; -reg soc_sdram_bankmachine2_cmd_buffer_source_valid = 1'd0; -wire soc_sdram_bankmachine2_cmd_buffer_source_ready; -reg soc_sdram_bankmachine2_cmd_buffer_source_first = 1'd0; -reg soc_sdram_bankmachine2_cmd_buffer_source_last = 1'd0; -reg soc_sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_sdram_bankmachine2_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_sdram_bankmachine2_row = 14'd0; -reg soc_sdram_bankmachine2_row_opened = 1'd0; -wire soc_sdram_bankmachine2_row_hit; -reg soc_sdram_bankmachine2_row_open = 1'd0; -reg soc_sdram_bankmachine2_row_close = 1'd0; -reg soc_sdram_bankmachine2_row_col_n_addr_sel = 1'd0; -wire soc_sdram_bankmachine2_twtpcon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine2_twtpcon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine2_twtpcon_count = 3'd0; -wire soc_sdram_bankmachine2_trccon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine2_trccon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine2_trccon_count = 3'd0; -wire soc_sdram_bankmachine2_trascon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine2_trascon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine2_trascon_count = 3'd0; -wire soc_sdram_bankmachine3_req_valid; -wire soc_sdram_bankmachine3_req_ready; -wire soc_sdram_bankmachine3_req_we; -wire [20:0] soc_sdram_bankmachine3_req_addr; -wire soc_sdram_bankmachine3_req_lock; -reg soc_sdram_bankmachine3_req_wdata_ready = 1'd0; -reg soc_sdram_bankmachine3_req_rdata_valid = 1'd0; -wire soc_sdram_bankmachine3_refresh_req; -reg soc_sdram_bankmachine3_refresh_gnt = 1'd0; -reg soc_sdram_bankmachine3_cmd_valid = 1'd0; -reg soc_sdram_bankmachine3_cmd_ready = 1'd0; -reg [13:0] soc_sdram_bankmachine3_cmd_payload_a = 14'd0; -wire [2:0] soc_sdram_bankmachine3_cmd_payload_ba; -reg soc_sdram_bankmachine3_cmd_payload_cas = 1'd0; -reg soc_sdram_bankmachine3_cmd_payload_ras = 1'd0; -reg soc_sdram_bankmachine3_cmd_payload_we = 1'd0; -reg soc_sdram_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg soc_sdram_bankmachine3_cmd_payload_is_read = 1'd0; -reg soc_sdram_bankmachine3_cmd_payload_is_write = 1'd0; -reg soc_sdram_bankmachine3_auto_precharge = 1'd0; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready; -reg soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -wire [23:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -wire [23:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -reg [4:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_level = 5'd0; -reg soc_sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read; -wire [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -wire soc_sdram_bankmachine3_cmd_buffer_sink_valid; -wire soc_sdram_bankmachine3_cmd_buffer_sink_ready; -wire soc_sdram_bankmachine3_cmd_buffer_sink_first; -wire soc_sdram_bankmachine3_cmd_buffer_sink_last; -wire soc_sdram_bankmachine3_cmd_buffer_sink_payload_we; -wire [20:0] soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr; -reg soc_sdram_bankmachine3_cmd_buffer_source_valid = 1'd0; -wire soc_sdram_bankmachine3_cmd_buffer_source_ready; -reg soc_sdram_bankmachine3_cmd_buffer_source_first = 1'd0; -reg soc_sdram_bankmachine3_cmd_buffer_source_last = 1'd0; -reg soc_sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_sdram_bankmachine3_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_sdram_bankmachine3_row = 14'd0; -reg soc_sdram_bankmachine3_row_opened = 1'd0; -wire soc_sdram_bankmachine3_row_hit; -reg soc_sdram_bankmachine3_row_open = 1'd0; -reg soc_sdram_bankmachine3_row_close = 1'd0; -reg soc_sdram_bankmachine3_row_col_n_addr_sel = 1'd0; -wire soc_sdram_bankmachine3_twtpcon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine3_twtpcon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine3_twtpcon_count = 3'd0; -wire soc_sdram_bankmachine3_trccon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine3_trccon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine3_trccon_count = 3'd0; -wire soc_sdram_bankmachine3_trascon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine3_trascon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine3_trascon_count = 3'd0; -wire soc_sdram_bankmachine4_req_valid; -wire soc_sdram_bankmachine4_req_ready; -wire soc_sdram_bankmachine4_req_we; -wire [20:0] soc_sdram_bankmachine4_req_addr; -wire soc_sdram_bankmachine4_req_lock; -reg soc_sdram_bankmachine4_req_wdata_ready = 1'd0; -reg soc_sdram_bankmachine4_req_rdata_valid = 1'd0; -wire soc_sdram_bankmachine4_refresh_req; -reg soc_sdram_bankmachine4_refresh_gnt = 1'd0; -reg soc_sdram_bankmachine4_cmd_valid = 1'd0; -reg soc_sdram_bankmachine4_cmd_ready = 1'd0; -reg [13:0] soc_sdram_bankmachine4_cmd_payload_a = 14'd0; -wire [2:0] soc_sdram_bankmachine4_cmd_payload_ba; -reg soc_sdram_bankmachine4_cmd_payload_cas = 1'd0; -reg soc_sdram_bankmachine4_cmd_payload_ras = 1'd0; -reg soc_sdram_bankmachine4_cmd_payload_we = 1'd0; -reg soc_sdram_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg soc_sdram_bankmachine4_cmd_payload_is_read = 1'd0; -reg soc_sdram_bankmachine4_cmd_payload_is_write = 1'd0; -reg soc_sdram_bankmachine4_auto_precharge = 1'd0; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready; -reg soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -wire [23:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -wire [23:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -reg [4:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_level = 5'd0; -reg soc_sdram_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read; -wire [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -wire soc_sdram_bankmachine4_cmd_buffer_sink_valid; -wire soc_sdram_bankmachine4_cmd_buffer_sink_ready; -wire soc_sdram_bankmachine4_cmd_buffer_sink_first; -wire soc_sdram_bankmachine4_cmd_buffer_sink_last; -wire soc_sdram_bankmachine4_cmd_buffer_sink_payload_we; -wire [20:0] soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr; -reg soc_sdram_bankmachine4_cmd_buffer_source_valid = 1'd0; -wire soc_sdram_bankmachine4_cmd_buffer_source_ready; -reg soc_sdram_bankmachine4_cmd_buffer_source_first = 1'd0; -reg soc_sdram_bankmachine4_cmd_buffer_source_last = 1'd0; -reg soc_sdram_bankmachine4_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_sdram_bankmachine4_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_sdram_bankmachine4_row = 14'd0; -reg soc_sdram_bankmachine4_row_opened = 1'd0; -wire soc_sdram_bankmachine4_row_hit; -reg soc_sdram_bankmachine4_row_open = 1'd0; -reg soc_sdram_bankmachine4_row_close = 1'd0; -reg soc_sdram_bankmachine4_row_col_n_addr_sel = 1'd0; -wire soc_sdram_bankmachine4_twtpcon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine4_twtpcon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine4_twtpcon_count = 3'd0; -wire soc_sdram_bankmachine4_trccon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine4_trccon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine4_trccon_count = 3'd0; -wire soc_sdram_bankmachine4_trascon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine4_trascon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine4_trascon_count = 3'd0; -wire soc_sdram_bankmachine5_req_valid; -wire soc_sdram_bankmachine5_req_ready; -wire soc_sdram_bankmachine5_req_we; -wire [20:0] soc_sdram_bankmachine5_req_addr; -wire soc_sdram_bankmachine5_req_lock; -reg soc_sdram_bankmachine5_req_wdata_ready = 1'd0; -reg soc_sdram_bankmachine5_req_rdata_valid = 1'd0; -wire soc_sdram_bankmachine5_refresh_req; -reg soc_sdram_bankmachine5_refresh_gnt = 1'd0; -reg soc_sdram_bankmachine5_cmd_valid = 1'd0; -reg soc_sdram_bankmachine5_cmd_ready = 1'd0; -reg [13:0] soc_sdram_bankmachine5_cmd_payload_a = 14'd0; -wire [2:0] soc_sdram_bankmachine5_cmd_payload_ba; -reg soc_sdram_bankmachine5_cmd_payload_cas = 1'd0; -reg soc_sdram_bankmachine5_cmd_payload_ras = 1'd0; -reg soc_sdram_bankmachine5_cmd_payload_we = 1'd0; -reg soc_sdram_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg soc_sdram_bankmachine5_cmd_payload_is_read = 1'd0; -reg soc_sdram_bankmachine5_cmd_payload_is_write = 1'd0; -reg soc_sdram_bankmachine5_auto_precharge = 1'd0; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready; -reg soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -wire [23:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -wire [23:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -reg [4:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_level = 5'd0; -reg soc_sdram_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read; -wire [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -wire soc_sdram_bankmachine5_cmd_buffer_sink_valid; -wire soc_sdram_bankmachine5_cmd_buffer_sink_ready; -wire soc_sdram_bankmachine5_cmd_buffer_sink_first; -wire soc_sdram_bankmachine5_cmd_buffer_sink_last; -wire soc_sdram_bankmachine5_cmd_buffer_sink_payload_we; -wire [20:0] soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr; -reg soc_sdram_bankmachine5_cmd_buffer_source_valid = 1'd0; -wire soc_sdram_bankmachine5_cmd_buffer_source_ready; -reg soc_sdram_bankmachine5_cmd_buffer_source_first = 1'd0; -reg soc_sdram_bankmachine5_cmd_buffer_source_last = 1'd0; -reg soc_sdram_bankmachine5_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_sdram_bankmachine5_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_sdram_bankmachine5_row = 14'd0; -reg soc_sdram_bankmachine5_row_opened = 1'd0; -wire soc_sdram_bankmachine5_row_hit; -reg soc_sdram_bankmachine5_row_open = 1'd0; -reg soc_sdram_bankmachine5_row_close = 1'd0; -reg soc_sdram_bankmachine5_row_col_n_addr_sel = 1'd0; -wire soc_sdram_bankmachine5_twtpcon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine5_twtpcon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine5_twtpcon_count = 3'd0; -wire soc_sdram_bankmachine5_trccon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine5_trccon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine5_trccon_count = 3'd0; -wire soc_sdram_bankmachine5_trascon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine5_trascon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine5_trascon_count = 3'd0; -wire soc_sdram_bankmachine6_req_valid; -wire soc_sdram_bankmachine6_req_ready; -wire soc_sdram_bankmachine6_req_we; -wire [20:0] soc_sdram_bankmachine6_req_addr; -wire soc_sdram_bankmachine6_req_lock; -reg soc_sdram_bankmachine6_req_wdata_ready = 1'd0; -reg soc_sdram_bankmachine6_req_rdata_valid = 1'd0; -wire soc_sdram_bankmachine6_refresh_req; -reg soc_sdram_bankmachine6_refresh_gnt = 1'd0; -reg soc_sdram_bankmachine6_cmd_valid = 1'd0; -reg soc_sdram_bankmachine6_cmd_ready = 1'd0; -reg [13:0] soc_sdram_bankmachine6_cmd_payload_a = 14'd0; -wire [2:0] soc_sdram_bankmachine6_cmd_payload_ba; -reg soc_sdram_bankmachine6_cmd_payload_cas = 1'd0; -reg soc_sdram_bankmachine6_cmd_payload_ras = 1'd0; -reg soc_sdram_bankmachine6_cmd_payload_we = 1'd0; -reg soc_sdram_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg soc_sdram_bankmachine6_cmd_payload_is_read = 1'd0; -reg soc_sdram_bankmachine6_cmd_payload_is_write = 1'd0; -reg soc_sdram_bankmachine6_auto_precharge = 1'd0; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready; -reg soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -wire [23:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -wire [23:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -reg [4:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_level = 5'd0; -reg soc_sdram_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read; -wire [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -wire soc_sdram_bankmachine6_cmd_buffer_sink_valid; -wire soc_sdram_bankmachine6_cmd_buffer_sink_ready; -wire soc_sdram_bankmachine6_cmd_buffer_sink_first; -wire soc_sdram_bankmachine6_cmd_buffer_sink_last; -wire soc_sdram_bankmachine6_cmd_buffer_sink_payload_we; -wire [20:0] soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr; -reg soc_sdram_bankmachine6_cmd_buffer_source_valid = 1'd0; -wire soc_sdram_bankmachine6_cmd_buffer_source_ready; -reg soc_sdram_bankmachine6_cmd_buffer_source_first = 1'd0; -reg soc_sdram_bankmachine6_cmd_buffer_source_last = 1'd0; -reg soc_sdram_bankmachine6_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_sdram_bankmachine6_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_sdram_bankmachine6_row = 14'd0; -reg soc_sdram_bankmachine6_row_opened = 1'd0; -wire soc_sdram_bankmachine6_row_hit; -reg soc_sdram_bankmachine6_row_open = 1'd0; -reg soc_sdram_bankmachine6_row_close = 1'd0; -reg soc_sdram_bankmachine6_row_col_n_addr_sel = 1'd0; -wire soc_sdram_bankmachine6_twtpcon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine6_twtpcon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine6_twtpcon_count = 3'd0; -wire soc_sdram_bankmachine6_trccon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine6_trccon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine6_trccon_count = 3'd0; -wire soc_sdram_bankmachine6_trascon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine6_trascon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine6_trascon_count = 3'd0; -wire soc_sdram_bankmachine7_req_valid; -wire soc_sdram_bankmachine7_req_ready; -wire soc_sdram_bankmachine7_req_we; -wire [20:0] soc_sdram_bankmachine7_req_addr; -wire soc_sdram_bankmachine7_req_lock; -reg soc_sdram_bankmachine7_req_wdata_ready = 1'd0; -reg soc_sdram_bankmachine7_req_rdata_valid = 1'd0; -wire soc_sdram_bankmachine7_refresh_req; -reg soc_sdram_bankmachine7_refresh_gnt = 1'd0; -reg soc_sdram_bankmachine7_cmd_valid = 1'd0; -reg soc_sdram_bankmachine7_cmd_ready = 1'd0; -reg [13:0] soc_sdram_bankmachine7_cmd_payload_a = 14'd0; -wire [2:0] soc_sdram_bankmachine7_cmd_payload_ba; -reg soc_sdram_bankmachine7_cmd_payload_cas = 1'd0; -reg soc_sdram_bankmachine7_cmd_payload_ras = 1'd0; -reg soc_sdram_bankmachine7_cmd_payload_we = 1'd0; -reg soc_sdram_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg soc_sdram_bankmachine7_cmd_payload_is_read = 1'd0; -reg soc_sdram_bankmachine7_cmd_payload_is_write = 1'd0; -reg soc_sdram_bankmachine7_auto_precharge = 1'd0; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready; -reg soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -wire [23:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -wire [23:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -reg [4:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_level = 5'd0; -reg soc_sdram_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read; -wire [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -wire soc_sdram_bankmachine7_cmd_buffer_sink_valid; -wire soc_sdram_bankmachine7_cmd_buffer_sink_ready; -wire soc_sdram_bankmachine7_cmd_buffer_sink_first; -wire soc_sdram_bankmachine7_cmd_buffer_sink_last; -wire soc_sdram_bankmachine7_cmd_buffer_sink_payload_we; -wire [20:0] soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr; -reg soc_sdram_bankmachine7_cmd_buffer_source_valid = 1'd0; -wire soc_sdram_bankmachine7_cmd_buffer_source_ready; -reg soc_sdram_bankmachine7_cmd_buffer_source_first = 1'd0; -reg soc_sdram_bankmachine7_cmd_buffer_source_last = 1'd0; -reg soc_sdram_bankmachine7_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_sdram_bankmachine7_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_sdram_bankmachine7_row = 14'd0; -reg soc_sdram_bankmachine7_row_opened = 1'd0; -wire soc_sdram_bankmachine7_row_hit; -reg soc_sdram_bankmachine7_row_open = 1'd0; -reg soc_sdram_bankmachine7_row_close = 1'd0; -reg soc_sdram_bankmachine7_row_col_n_addr_sel = 1'd0; -wire soc_sdram_bankmachine7_twtpcon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine7_twtpcon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine7_twtpcon_count = 3'd0; -wire soc_sdram_bankmachine7_trccon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine7_trccon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine7_trccon_count = 3'd0; -wire soc_sdram_bankmachine7_trascon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine7_trascon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine7_trascon_count = 3'd0; -wire soc_sdram_ras_allowed; -wire soc_sdram_cas_allowed; -reg soc_sdram_choose_cmd_want_reads = 1'd0; -reg soc_sdram_choose_cmd_want_writes = 1'd0; -reg soc_sdram_choose_cmd_want_cmds = 1'd0; -reg soc_sdram_choose_cmd_want_activates = 1'd0; -wire soc_sdram_choose_cmd_cmd_valid; -reg soc_sdram_choose_cmd_cmd_ready = 1'd0; -wire [13:0] soc_sdram_choose_cmd_cmd_payload_a; -wire [2:0] soc_sdram_choose_cmd_cmd_payload_ba; -reg soc_sdram_choose_cmd_cmd_payload_cas = 1'd0; -reg soc_sdram_choose_cmd_cmd_payload_ras = 1'd0; -reg soc_sdram_choose_cmd_cmd_payload_we = 1'd0; -wire soc_sdram_choose_cmd_cmd_payload_is_cmd; -wire soc_sdram_choose_cmd_cmd_payload_is_read; -wire soc_sdram_choose_cmd_cmd_payload_is_write; -reg [7:0] soc_sdram_choose_cmd_valids = 8'd0; -wire [7:0] soc_sdram_choose_cmd_request; -reg [2:0] soc_sdram_choose_cmd_grant = 3'd0; -wire soc_sdram_choose_cmd_ce; -reg soc_sdram_choose_req_want_reads = 1'd0; -reg soc_sdram_choose_req_want_writes = 1'd0; -reg soc_sdram_choose_req_want_cmds = 1'd0; -reg soc_sdram_choose_req_want_activates = 1'd0; -wire soc_sdram_choose_req_cmd_valid; -reg soc_sdram_choose_req_cmd_ready = 1'd0; -wire [13:0] soc_sdram_choose_req_cmd_payload_a; -wire [2:0] soc_sdram_choose_req_cmd_payload_ba; -reg soc_sdram_choose_req_cmd_payload_cas = 1'd0; -reg soc_sdram_choose_req_cmd_payload_ras = 1'd0; -reg soc_sdram_choose_req_cmd_payload_we = 1'd0; -wire soc_sdram_choose_req_cmd_payload_is_cmd; -wire soc_sdram_choose_req_cmd_payload_is_read; -wire soc_sdram_choose_req_cmd_payload_is_write; -reg [7:0] soc_sdram_choose_req_valids = 8'd0; -wire [7:0] soc_sdram_choose_req_request; -reg [2:0] soc_sdram_choose_req_grant = 3'd0; -wire soc_sdram_choose_req_ce; -reg [13:0] soc_sdram_nop_a = 14'd0; -reg [2:0] soc_sdram_nop_ba = 3'd0; -reg [1:0] soc_sdram_steerer_sel0 = 2'd0; -reg [1:0] soc_sdram_steerer_sel1 = 2'd0; -reg [1:0] soc_sdram_steerer_sel2 = 2'd0; -reg [1:0] soc_sdram_steerer_sel3 = 2'd0; -reg soc_sdram_steerer0 = 1'd1; -reg soc_sdram_steerer1 = 1'd1; -reg soc_sdram_steerer2 = 1'd1; -reg soc_sdram_steerer3 = 1'd1; -reg soc_sdram_steerer4 = 1'd1; -reg soc_sdram_steerer5 = 1'd1; -reg soc_sdram_steerer6 = 1'd1; -reg soc_sdram_steerer7 = 1'd1; -wire soc_sdram_trrdcon_valid; -(* dont_touch = "true" *) reg soc_sdram_trrdcon_ready = 1'd1; -reg soc_sdram_trrdcon_count = 1'd0; -wire soc_sdram_tfawcon_valid; -(* dont_touch = "true" *) reg soc_sdram_tfawcon_ready = 1'd1; -wire [2:0] soc_sdram_tfawcon_count; -reg [4:0] soc_sdram_tfawcon_window = 5'd0; -wire soc_sdram_tccdcon_valid; -(* dont_touch = "true" *) reg soc_sdram_tccdcon_ready = 1'd1; -reg soc_sdram_tccdcon_count = 1'd0; -wire soc_sdram_twtrcon_valid; -(* dont_touch = "true" *) reg soc_sdram_twtrcon_ready = 1'd1; -reg [2:0] soc_sdram_twtrcon_count = 3'd0; -wire soc_sdram_read_available; -wire soc_sdram_write_available; -reg soc_sdram_en0 = 1'd0; -wire soc_sdram_max_time0; -reg [4:0] soc_sdram_time0 = 5'd0; -reg soc_sdram_en1 = 1'd0; -wire soc_sdram_max_time1; -reg [3:0] soc_sdram_time1 = 4'd0; -wire soc_sdram_go_to_refresh; -reg soc_port_cmd_valid = 1'd0; -wire soc_port_cmd_ready; -reg soc_port_cmd_payload_we = 1'd0; -reg [23:0] soc_port_cmd_payload_addr = 24'd0; -wire soc_port_wdata_valid; -wire soc_port_wdata_ready; -wire soc_port_wdata_first; -wire soc_port_wdata_last; -wire [127:0] soc_port_wdata_payload_data; -wire [15:0] soc_port_wdata_payload_we; -wire soc_port_rdata_valid; -wire soc_port_rdata_ready; -reg soc_port_rdata_first = 1'd0; -reg soc_port_rdata_last = 1'd0; -wire [127:0] soc_port_rdata_payload_data; -wire [29:0] soc_wb_sdram_adr; -wire [31:0] soc_wb_sdram_dat_w; -reg [31:0] soc_wb_sdram_dat_r = 32'd0; -wire [3:0] soc_wb_sdram_sel; -wire soc_wb_sdram_cyc; -wire soc_wb_sdram_stb; -reg soc_wb_sdram_ack = 1'd0; -wire soc_wb_sdram_we; -wire [2:0] soc_wb_sdram_cti; -wire [1:0] soc_wb_sdram_bte; -reg soc_wb_sdram_err = 1'd0; -wire [29:0] soc_litedram_wb_adr; -reg [127:0] soc_litedram_wb_dat_w = 128'd0; -wire [127:0] soc_litedram_wb_dat_r; -reg [15:0] soc_litedram_wb_sel = 16'd0; -reg soc_litedram_wb_cyc = 1'd0; -reg soc_litedram_wb_stb = 1'd0; -reg soc_litedram_wb_ack = 1'd0; -reg soc_litedram_wb_we = 1'd0; -wire [2:0] soc_litedram_wb_cti; -reg soc_write = 1'd0; -reg soc_evict = 1'd0; -reg soc_refill = 1'd0; -reg soc_read = 1'd0; -wire [29:0] soc_address_d; -reg [29:0] soc_address_q = 30'd0; -reg soc_address_ce = 1'd0; -reg soc_address_reset = 1'd0; -reg [1:0] soc_counter = 2'd0; -reg soc_counter_ce = 1'd0; -reg soc_counter_reset = 1'd0; -wire [1:0] soc_counter_offset; -wire soc_counter_done; -wire [127:0] soc_cached_data; -wire [15:0] soc_cached_sel; -wire soc_end_of_burst; -wire soc_need_refill_d; -reg soc_need_refill_q = 1'd1; -reg soc_need_refill_ce = 1'd0; -wire soc_need_refill_reset; -reg [31:0] soc_cached_datas_flipflop0_d = 32'd0; -reg [31:0] soc_cached_datas_flipflop0_q = 32'd0; -reg soc_cached_datas_ce0 = 1'd0; -reg soc_cached_datas_reset0 = 1'd0; -reg [31:0] soc_cached_datas_flipflop1_d = 32'd0; -reg [31:0] soc_cached_datas_flipflop1_q = 32'd0; -reg soc_cached_datas_ce1 = 1'd0; -reg soc_cached_datas_reset1 = 1'd0; -reg [31:0] soc_cached_datas_flipflop2_d = 32'd0; -reg [31:0] soc_cached_datas_flipflop2_q = 32'd0; -reg soc_cached_datas_ce2 = 1'd0; -reg soc_cached_datas_reset2 = 1'd0; -reg [31:0] soc_cached_datas_flipflop3_d = 32'd0; -reg [31:0] soc_cached_datas_flipflop3_q = 32'd0; -reg soc_cached_datas_ce3 = 1'd0; -reg soc_cached_datas_reset3 = 1'd0; -wire [3:0] soc_cached_sels_flipflop0_d; -reg [3:0] soc_cached_sels_flipflop0_q = 4'd0; -reg soc_cached_sels_ce0 = 1'd0; -wire soc_cached_sels_reset0; -wire [3:0] soc_cached_sels_flipflop1_d; -reg [3:0] soc_cached_sels_flipflop1_q = 4'd0; -reg soc_cached_sels_ce1 = 1'd0; -wire soc_cached_sels_reset1; -wire [3:0] soc_cached_sels_flipflop2_d; -reg [3:0] soc_cached_sels_flipflop2_q = 4'd0; -reg soc_cached_sels_ce2 = 1'd0; -wire soc_cached_sels_reset2; -wire [3:0] soc_cached_sels_flipflop3_d; -reg [3:0] soc_cached_sels_flipflop3_q = 4'd0; -reg soc_cached_sels_ce3 = 1'd0; -wire soc_cached_sels_reset3; -reg soc_write_sel0 = 1'd0; -reg soc_write_sel1 = 1'd0; -reg soc_write_sel2 = 1'd0; -reg soc_write_sel3 = 1'd0; -wire soc_wdata_converter_sink_valid; -wire soc_wdata_converter_sink_ready; -reg soc_wdata_converter_sink_first = 1'd0; -reg soc_wdata_converter_sink_last = 1'd0; -wire [127:0] soc_wdata_converter_sink_payload_data; -wire [15:0] soc_wdata_converter_sink_payload_we; -wire soc_wdata_converter_source_valid; -wire soc_wdata_converter_source_ready; -wire soc_wdata_converter_source_first; -wire soc_wdata_converter_source_last; -wire [127:0] soc_wdata_converter_source_payload_data; -wire [15:0] soc_wdata_converter_source_payload_we; -wire soc_wdata_converter_converter_sink_valid; -wire soc_wdata_converter_converter_sink_ready; -wire soc_wdata_converter_converter_sink_first; -wire soc_wdata_converter_converter_sink_last; -wire [143:0] soc_wdata_converter_converter_sink_payload_data; -wire soc_wdata_converter_converter_source_valid; -wire soc_wdata_converter_converter_source_ready; -wire soc_wdata_converter_converter_source_first; -wire soc_wdata_converter_converter_source_last; -wire [143:0] soc_wdata_converter_converter_source_payload_data; -wire soc_wdata_converter_converter_source_payload_valid_token_count; -wire soc_wdata_converter_source_source_valid; -wire soc_wdata_converter_source_source_ready; -wire soc_wdata_converter_source_source_first; -wire soc_wdata_converter_source_source_last; -wire [143:0] soc_wdata_converter_source_source_payload_data; -wire soc_rdata_converter_sink_valid; -wire soc_rdata_converter_sink_ready; -wire soc_rdata_converter_sink_first; -wire soc_rdata_converter_sink_last; -wire [127:0] soc_rdata_converter_sink_payload_data; -wire soc_rdata_converter_source_valid; -wire soc_rdata_converter_source_ready; -wire soc_rdata_converter_source_first; -wire soc_rdata_converter_source_last; -wire [127:0] soc_rdata_converter_source_payload_data; -wire soc_rdata_converter_converter_sink_valid; -wire soc_rdata_converter_converter_sink_ready; -wire soc_rdata_converter_converter_sink_first; -wire soc_rdata_converter_converter_sink_last; -wire [127:0] soc_rdata_converter_converter_sink_payload_data; -wire soc_rdata_converter_converter_source_valid; -wire soc_rdata_converter_converter_source_ready; -wire soc_rdata_converter_converter_source_first; -wire soc_rdata_converter_converter_source_last; -wire [127:0] soc_rdata_converter_converter_source_payload_data; -wire soc_rdata_converter_converter_source_payload_valid_token_count; -wire soc_rdata_converter_source_source_valid; -wire soc_rdata_converter_source_source_ready; -wire soc_rdata_converter_source_source_first; -wire soc_rdata_converter_source_source_last; -wire [127:0] soc_rdata_converter_source_source_payload_data; -reg soc_count = 1'd0; -reg soc_init_done_storage = 1'd0; -reg soc_init_done_re = 1'd0; -reg soc_init_error_storage = 1'd0; -reg soc_init_error_re = 1'd0; -wire soc_cmd_valid; -wire soc_cmd_ready; -wire soc_cmd_payload_we; -wire [23:0] soc_cmd_payload_addr; -wire soc_wdata_valid; -wire soc_wdata_ready; -wire [127:0] soc_wdata_payload_data; -wire [15:0] soc_wdata_payload_we; -wire soc_rdata_valid; -wire soc_rdata_ready; -wire [127:0] soc_rdata_payload_data; -reg vns_wb2csr_state = 1'd0; -reg vns_wb2csr_next_state = 1'd0; -wire vns_pll_fb0; -wire vns_pll_fb1; -reg [1:0] vns_refresher_state = 2'd0; -reg [1:0] vns_refresher_next_state = 2'd0; -reg [3:0] vns_bankmachine0_state = 4'd0; -reg [3:0] vns_bankmachine0_next_state = 4'd0; -reg [3:0] vns_bankmachine1_state = 4'd0; -reg [3:0] vns_bankmachine1_next_state = 4'd0; -reg [3:0] vns_bankmachine2_state = 4'd0; -reg [3:0] vns_bankmachine2_next_state = 4'd0; -reg [3:0] vns_bankmachine3_state = 4'd0; -reg [3:0] vns_bankmachine3_next_state = 4'd0; -reg [3:0] vns_bankmachine4_state = 4'd0; -reg [3:0] vns_bankmachine4_next_state = 4'd0; -reg [3:0] vns_bankmachine5_state = 4'd0; -reg [3:0] vns_bankmachine5_next_state = 4'd0; -reg [3:0] vns_bankmachine6_state = 4'd0; -reg [3:0] vns_bankmachine6_next_state = 4'd0; -reg [3:0] vns_bankmachine7_state = 4'd0; -reg [3:0] vns_bankmachine7_next_state = 4'd0; -reg [3:0] vns_multiplexer_state = 4'd0; -reg [3:0] vns_multiplexer_next_state = 4'd0; -wire [1:0] vns_roundrobin0_request; -reg vns_roundrobin0_grant = 1'd0; -wire vns_roundrobin0_ce; -wire [1:0] vns_roundrobin1_request; -reg vns_roundrobin1_grant = 1'd0; -wire vns_roundrobin1_ce; -wire [1:0] vns_roundrobin2_request; -reg vns_roundrobin2_grant = 1'd0; -wire vns_roundrobin2_ce; -wire [1:0] vns_roundrobin3_request; -reg vns_roundrobin3_grant = 1'd0; -wire vns_roundrobin3_ce; -wire [1:0] vns_roundrobin4_request; -reg vns_roundrobin4_grant = 1'd0; -wire vns_roundrobin4_ce; -wire [1:0] vns_roundrobin5_request; -reg vns_roundrobin5_grant = 1'd0; -wire vns_roundrobin5_ce; -wire [1:0] vns_roundrobin6_request; -reg vns_roundrobin6_grant = 1'd0; -wire vns_roundrobin6_ce; -wire [1:0] vns_roundrobin7_request; -reg vns_roundrobin7_grant = 1'd0; -wire vns_roundrobin7_ce; -reg vns_locked0 = 1'd0; -reg vns_locked1 = 1'd0; -reg vns_locked2 = 1'd0; -reg vns_locked3 = 1'd0; -reg vns_locked4 = 1'd0; -reg vns_locked5 = 1'd0; -reg vns_locked6 = 1'd0; -reg vns_locked7 = 1'd0; -reg vns_locked8 = 1'd0; -reg vns_locked9 = 1'd0; -reg vns_locked10 = 1'd0; -reg vns_locked11 = 1'd0; -reg vns_locked12 = 1'd0; -reg vns_locked13 = 1'd0; -reg vns_locked14 = 1'd0; -reg vns_locked15 = 1'd0; -reg vns_new_master_wdata_ready0 = 1'd0; -reg vns_new_master_wdata_ready1 = 1'd0; -reg vns_new_master_wdata_ready2 = 1'd0; -reg vns_new_master_wdata_ready3 = 1'd0; -reg vns_new_master_wdata_ready4 = 1'd0; -reg vns_new_master_wdata_ready5 = 1'd0; -reg vns_new_master_rdata_valid0 = 1'd0; -reg vns_new_master_rdata_valid1 = 1'd0; -reg vns_new_master_rdata_valid2 = 1'd0; -reg vns_new_master_rdata_valid3 = 1'd0; -reg vns_new_master_rdata_valid4 = 1'd0; -reg vns_new_master_rdata_valid5 = 1'd0; -reg vns_new_master_rdata_valid6 = 1'd0; -reg vns_new_master_rdata_valid7 = 1'd0; -reg vns_new_master_rdata_valid8 = 1'd0; -reg vns_new_master_rdata_valid9 = 1'd0; -reg vns_new_master_rdata_valid10 = 1'd0; -reg vns_new_master_rdata_valid11 = 1'd0; -reg vns_new_master_rdata_valid12 = 1'd0; -reg vns_new_master_rdata_valid13 = 1'd0; -reg vns_new_master_rdata_valid14 = 1'd0; -reg vns_new_master_rdata_valid15 = 1'd0; -reg vns_new_master_rdata_valid16 = 1'd0; -reg vns_new_master_rdata_valid17 = 1'd0; -reg [2:0] vns_converter_state = 3'd0; -reg [2:0] vns_converter_next_state = 3'd0; -reg [1:0] vns_litedramwishbone2native_state = 2'd0; -reg [1:0] vns_litedramwishbone2native_next_state = 2'd0; -reg soc_count_next_value = 1'd0; -reg soc_count_next_value_ce = 1'd0; -wire [29:0] vns_shared_adr; -wire [31:0] vns_shared_dat_w; -reg [31:0] vns_shared_dat_r = 32'd0; -wire [3:0] vns_shared_sel; -wire vns_shared_cyc; -wire vns_shared_stb; -reg vns_shared_ack = 1'd0; -wire vns_shared_we; -wire [2:0] vns_shared_cti; -wire [1:0] vns_shared_bte; -wire vns_shared_err; -wire [1:0] vns_request; -reg vns_grant = 1'd0; -reg [3:0] vns_slave_sel = 4'd0; -reg [3:0] vns_slave_sel_r = 4'd0; -reg vns_error = 1'd0; -wire vns_wait; -wire vns_done; -reg [19:0] vns_count = 20'd1000000; -wire [13:0] vns_interface0_bank_bus_adr; -wire vns_interface0_bank_bus_we; -wire [7:0] vns_interface0_bank_bus_dat_w; -reg [7:0] vns_interface0_bank_bus_dat_r = 8'd0; -wire vns_csrbank0_reset0_re; -wire vns_csrbank0_reset0_r; -wire vns_csrbank0_reset0_we; -wire vns_csrbank0_reset0_w; -wire vns_csrbank0_scratch3_re; -wire [7:0] vns_csrbank0_scratch3_r; -wire vns_csrbank0_scratch3_we; -wire [7:0] vns_csrbank0_scratch3_w; -wire vns_csrbank0_scratch2_re; -wire [7:0] vns_csrbank0_scratch2_r; -wire vns_csrbank0_scratch2_we; -wire [7:0] vns_csrbank0_scratch2_w; -wire vns_csrbank0_scratch1_re; -wire [7:0] vns_csrbank0_scratch1_r; -wire vns_csrbank0_scratch1_we; -wire [7:0] vns_csrbank0_scratch1_w; -wire vns_csrbank0_scratch0_re; -wire [7:0] vns_csrbank0_scratch0_r; -wire vns_csrbank0_scratch0_we; -wire [7:0] vns_csrbank0_scratch0_w; -wire vns_csrbank0_bus_errors3_re; -wire [7:0] vns_csrbank0_bus_errors3_r; -wire vns_csrbank0_bus_errors3_we; -wire [7:0] vns_csrbank0_bus_errors3_w; -wire vns_csrbank0_bus_errors2_re; -wire [7:0] vns_csrbank0_bus_errors2_r; -wire vns_csrbank0_bus_errors2_we; -wire [7:0] vns_csrbank0_bus_errors2_w; -wire vns_csrbank0_bus_errors1_re; -wire [7:0] vns_csrbank0_bus_errors1_r; -wire vns_csrbank0_bus_errors1_we; -wire [7:0] vns_csrbank0_bus_errors1_w; -wire vns_csrbank0_bus_errors0_re; -wire [7:0] vns_csrbank0_bus_errors0_r; -wire vns_csrbank0_bus_errors0_we; -wire [7:0] vns_csrbank0_bus_errors0_w; -wire vns_csrbank0_sel; -wire [13:0] vns_interface1_bank_bus_adr; -wire vns_interface1_bank_bus_we; -wire [7:0] vns_interface1_bank_bus_dat_w; -reg [7:0] vns_interface1_bank_bus_dat_r = 8'd0; -wire vns_csrbank1_init_done0_re; -wire vns_csrbank1_init_done0_r; -wire vns_csrbank1_init_done0_we; -wire vns_csrbank1_init_done0_w; -wire vns_csrbank1_init_error0_re; -wire vns_csrbank1_init_error0_r; -wire vns_csrbank1_init_error0_we; -wire vns_csrbank1_init_error0_w; -wire vns_csrbank1_sel; -wire [13:0] vns_interface2_bank_bus_adr; -wire vns_interface2_bank_bus_we; -wire [7:0] vns_interface2_bank_bus_dat_w; -reg [7:0] vns_interface2_bank_bus_dat_r = 8'd0; -wire vns_csrbank2_half_sys8x_taps0_re; -wire [4:0] vns_csrbank2_half_sys8x_taps0_r; -wire vns_csrbank2_half_sys8x_taps0_we; -wire [4:0] vns_csrbank2_half_sys8x_taps0_w; -wire vns_csrbank2_wlevel_en0_re; -wire vns_csrbank2_wlevel_en0_r; -wire vns_csrbank2_wlevel_en0_we; -wire vns_csrbank2_wlevel_en0_w; -wire vns_csrbank2_dly_sel0_re; -wire [1:0] vns_csrbank2_dly_sel0_r; -wire vns_csrbank2_dly_sel0_we; -wire [1:0] vns_csrbank2_dly_sel0_w; -wire vns_csrbank2_sel; -wire [13:0] vns_interface3_bank_bus_adr; -wire vns_interface3_bank_bus_we; -wire [7:0] vns_interface3_bank_bus_dat_w; -reg [7:0] vns_interface3_bank_bus_dat_r = 8'd0; -wire vns_csrbank3_dfii_control0_re; -wire [3:0] vns_csrbank3_dfii_control0_r; -wire vns_csrbank3_dfii_control0_we; -wire [3:0] vns_csrbank3_dfii_control0_w; -wire vns_csrbank3_dfii_pi0_command0_re; -wire [5:0] vns_csrbank3_dfii_pi0_command0_r; -wire vns_csrbank3_dfii_pi0_command0_we; -wire [5:0] vns_csrbank3_dfii_pi0_command0_w; -wire vns_csrbank3_dfii_pi0_address1_re; -wire [5:0] vns_csrbank3_dfii_pi0_address1_r; -wire vns_csrbank3_dfii_pi0_address1_we; -wire [5:0] vns_csrbank3_dfii_pi0_address1_w; -wire vns_csrbank3_dfii_pi0_address0_re; -wire [7:0] vns_csrbank3_dfii_pi0_address0_r; -wire vns_csrbank3_dfii_pi0_address0_we; -wire [7:0] vns_csrbank3_dfii_pi0_address0_w; -wire vns_csrbank3_dfii_pi0_baddress0_re; -wire [2:0] vns_csrbank3_dfii_pi0_baddress0_r; -wire vns_csrbank3_dfii_pi0_baddress0_we; -wire [2:0] vns_csrbank3_dfii_pi0_baddress0_w; -wire vns_csrbank3_dfii_pi0_wrdata3_re; -wire [7:0] vns_csrbank3_dfii_pi0_wrdata3_r; -wire vns_csrbank3_dfii_pi0_wrdata3_we; -wire [7:0] vns_csrbank3_dfii_pi0_wrdata3_w; -wire vns_csrbank3_dfii_pi0_wrdata2_re; -wire [7:0] vns_csrbank3_dfii_pi0_wrdata2_r; -wire vns_csrbank3_dfii_pi0_wrdata2_we; -wire [7:0] vns_csrbank3_dfii_pi0_wrdata2_w; -wire vns_csrbank3_dfii_pi0_wrdata1_re; -wire [7:0] vns_csrbank3_dfii_pi0_wrdata1_r; -wire vns_csrbank3_dfii_pi0_wrdata1_we; -wire [7:0] vns_csrbank3_dfii_pi0_wrdata1_w; -wire vns_csrbank3_dfii_pi0_wrdata0_re; -wire [7:0] vns_csrbank3_dfii_pi0_wrdata0_r; -wire vns_csrbank3_dfii_pi0_wrdata0_we; -wire [7:0] vns_csrbank3_dfii_pi0_wrdata0_w; -wire vns_csrbank3_dfii_pi0_rddata3_re; -wire [7:0] vns_csrbank3_dfii_pi0_rddata3_r; -wire vns_csrbank3_dfii_pi0_rddata3_we; -wire [7:0] vns_csrbank3_dfii_pi0_rddata3_w; -wire vns_csrbank3_dfii_pi0_rddata2_re; -wire [7:0] vns_csrbank3_dfii_pi0_rddata2_r; -wire vns_csrbank3_dfii_pi0_rddata2_we; -wire [7:0] vns_csrbank3_dfii_pi0_rddata2_w; -wire vns_csrbank3_dfii_pi0_rddata1_re; -wire [7:0] vns_csrbank3_dfii_pi0_rddata1_r; -wire vns_csrbank3_dfii_pi0_rddata1_we; -wire [7:0] vns_csrbank3_dfii_pi0_rddata1_w; -wire vns_csrbank3_dfii_pi0_rddata0_re; -wire [7:0] vns_csrbank3_dfii_pi0_rddata0_r; -wire vns_csrbank3_dfii_pi0_rddata0_we; -wire [7:0] vns_csrbank3_dfii_pi0_rddata0_w; -wire vns_csrbank3_dfii_pi1_command0_re; -wire [5:0] vns_csrbank3_dfii_pi1_command0_r; -wire vns_csrbank3_dfii_pi1_command0_we; -wire [5:0] vns_csrbank3_dfii_pi1_command0_w; -wire vns_csrbank3_dfii_pi1_address1_re; -wire [5:0] vns_csrbank3_dfii_pi1_address1_r; -wire vns_csrbank3_dfii_pi1_address1_we; -wire [5:0] vns_csrbank3_dfii_pi1_address1_w; -wire vns_csrbank3_dfii_pi1_address0_re; -wire [7:0] vns_csrbank3_dfii_pi1_address0_r; -wire vns_csrbank3_dfii_pi1_address0_we; -wire [7:0] vns_csrbank3_dfii_pi1_address0_w; -wire vns_csrbank3_dfii_pi1_baddress0_re; -wire [2:0] vns_csrbank3_dfii_pi1_baddress0_r; -wire vns_csrbank3_dfii_pi1_baddress0_we; -wire [2:0] vns_csrbank3_dfii_pi1_baddress0_w; -wire vns_csrbank3_dfii_pi1_wrdata3_re; -wire [7:0] vns_csrbank3_dfii_pi1_wrdata3_r; -wire vns_csrbank3_dfii_pi1_wrdata3_we; -wire [7:0] vns_csrbank3_dfii_pi1_wrdata3_w; -wire vns_csrbank3_dfii_pi1_wrdata2_re; -wire [7:0] vns_csrbank3_dfii_pi1_wrdata2_r; -wire vns_csrbank3_dfii_pi1_wrdata2_we; -wire [7:0] vns_csrbank3_dfii_pi1_wrdata2_w; -wire vns_csrbank3_dfii_pi1_wrdata1_re; -wire [7:0] vns_csrbank3_dfii_pi1_wrdata1_r; -wire vns_csrbank3_dfii_pi1_wrdata1_we; -wire [7:0] vns_csrbank3_dfii_pi1_wrdata1_w; -wire vns_csrbank3_dfii_pi1_wrdata0_re; -wire [7:0] vns_csrbank3_dfii_pi1_wrdata0_r; -wire vns_csrbank3_dfii_pi1_wrdata0_we; -wire [7:0] vns_csrbank3_dfii_pi1_wrdata0_w; -wire vns_csrbank3_dfii_pi1_rddata3_re; -wire [7:0] vns_csrbank3_dfii_pi1_rddata3_r; -wire vns_csrbank3_dfii_pi1_rddata3_we; -wire [7:0] vns_csrbank3_dfii_pi1_rddata3_w; -wire vns_csrbank3_dfii_pi1_rddata2_re; -wire [7:0] vns_csrbank3_dfii_pi1_rddata2_r; -wire vns_csrbank3_dfii_pi1_rddata2_we; -wire [7:0] vns_csrbank3_dfii_pi1_rddata2_w; -wire vns_csrbank3_dfii_pi1_rddata1_re; -wire [7:0] vns_csrbank3_dfii_pi1_rddata1_r; -wire vns_csrbank3_dfii_pi1_rddata1_we; -wire [7:0] vns_csrbank3_dfii_pi1_rddata1_w; -wire vns_csrbank3_dfii_pi1_rddata0_re; -wire [7:0] vns_csrbank3_dfii_pi1_rddata0_r; -wire vns_csrbank3_dfii_pi1_rddata0_we; -wire [7:0] vns_csrbank3_dfii_pi1_rddata0_w; -wire vns_csrbank3_dfii_pi2_command0_re; -wire [5:0] vns_csrbank3_dfii_pi2_command0_r; -wire vns_csrbank3_dfii_pi2_command0_we; -wire [5:0] vns_csrbank3_dfii_pi2_command0_w; -wire vns_csrbank3_dfii_pi2_address1_re; -wire [5:0] vns_csrbank3_dfii_pi2_address1_r; -wire vns_csrbank3_dfii_pi2_address1_we; -wire [5:0] vns_csrbank3_dfii_pi2_address1_w; -wire vns_csrbank3_dfii_pi2_address0_re; -wire [7:0] vns_csrbank3_dfii_pi2_address0_r; -wire vns_csrbank3_dfii_pi2_address0_we; -wire [7:0] vns_csrbank3_dfii_pi2_address0_w; -wire vns_csrbank3_dfii_pi2_baddress0_re; -wire [2:0] vns_csrbank3_dfii_pi2_baddress0_r; -wire vns_csrbank3_dfii_pi2_baddress0_we; -wire [2:0] vns_csrbank3_dfii_pi2_baddress0_w; -wire vns_csrbank3_dfii_pi2_wrdata3_re; -wire [7:0] vns_csrbank3_dfii_pi2_wrdata3_r; -wire vns_csrbank3_dfii_pi2_wrdata3_we; -wire [7:0] vns_csrbank3_dfii_pi2_wrdata3_w; -wire vns_csrbank3_dfii_pi2_wrdata2_re; -wire [7:0] vns_csrbank3_dfii_pi2_wrdata2_r; -wire vns_csrbank3_dfii_pi2_wrdata2_we; -wire [7:0] vns_csrbank3_dfii_pi2_wrdata2_w; -wire vns_csrbank3_dfii_pi2_wrdata1_re; -wire [7:0] vns_csrbank3_dfii_pi2_wrdata1_r; -wire vns_csrbank3_dfii_pi2_wrdata1_we; -wire [7:0] vns_csrbank3_dfii_pi2_wrdata1_w; -wire vns_csrbank3_dfii_pi2_wrdata0_re; -wire [7:0] vns_csrbank3_dfii_pi2_wrdata0_r; -wire vns_csrbank3_dfii_pi2_wrdata0_we; -wire [7:0] vns_csrbank3_dfii_pi2_wrdata0_w; -wire vns_csrbank3_dfii_pi2_rddata3_re; -wire [7:0] vns_csrbank3_dfii_pi2_rddata3_r; -wire vns_csrbank3_dfii_pi2_rddata3_we; -wire [7:0] vns_csrbank3_dfii_pi2_rddata3_w; -wire vns_csrbank3_dfii_pi2_rddata2_re; -wire [7:0] vns_csrbank3_dfii_pi2_rddata2_r; -wire vns_csrbank3_dfii_pi2_rddata2_we; -wire [7:0] vns_csrbank3_dfii_pi2_rddata2_w; -wire vns_csrbank3_dfii_pi2_rddata1_re; -wire [7:0] vns_csrbank3_dfii_pi2_rddata1_r; -wire vns_csrbank3_dfii_pi2_rddata1_we; -wire [7:0] vns_csrbank3_dfii_pi2_rddata1_w; -wire vns_csrbank3_dfii_pi2_rddata0_re; -wire [7:0] vns_csrbank3_dfii_pi2_rddata0_r; -wire vns_csrbank3_dfii_pi2_rddata0_we; -wire [7:0] vns_csrbank3_dfii_pi2_rddata0_w; -wire vns_csrbank3_dfii_pi3_command0_re; -wire [5:0] vns_csrbank3_dfii_pi3_command0_r; -wire vns_csrbank3_dfii_pi3_command0_we; -wire [5:0] vns_csrbank3_dfii_pi3_command0_w; -wire vns_csrbank3_dfii_pi3_address1_re; -wire [5:0] vns_csrbank3_dfii_pi3_address1_r; -wire vns_csrbank3_dfii_pi3_address1_we; -wire [5:0] vns_csrbank3_dfii_pi3_address1_w; -wire vns_csrbank3_dfii_pi3_address0_re; -wire [7:0] vns_csrbank3_dfii_pi3_address0_r; -wire vns_csrbank3_dfii_pi3_address0_we; -wire [7:0] vns_csrbank3_dfii_pi3_address0_w; -wire vns_csrbank3_dfii_pi3_baddress0_re; -wire [2:0] vns_csrbank3_dfii_pi3_baddress0_r; -wire vns_csrbank3_dfii_pi3_baddress0_we; -wire [2:0] vns_csrbank3_dfii_pi3_baddress0_w; -wire vns_csrbank3_dfii_pi3_wrdata3_re; -wire [7:0] vns_csrbank3_dfii_pi3_wrdata3_r; -wire vns_csrbank3_dfii_pi3_wrdata3_we; -wire [7:0] vns_csrbank3_dfii_pi3_wrdata3_w; -wire vns_csrbank3_dfii_pi3_wrdata2_re; -wire [7:0] vns_csrbank3_dfii_pi3_wrdata2_r; -wire vns_csrbank3_dfii_pi3_wrdata2_we; -wire [7:0] vns_csrbank3_dfii_pi3_wrdata2_w; -wire vns_csrbank3_dfii_pi3_wrdata1_re; -wire [7:0] vns_csrbank3_dfii_pi3_wrdata1_r; -wire vns_csrbank3_dfii_pi3_wrdata1_we; -wire [7:0] vns_csrbank3_dfii_pi3_wrdata1_w; -wire vns_csrbank3_dfii_pi3_wrdata0_re; -wire [7:0] vns_csrbank3_dfii_pi3_wrdata0_r; -wire vns_csrbank3_dfii_pi3_wrdata0_we; -wire [7:0] vns_csrbank3_dfii_pi3_wrdata0_w; -wire vns_csrbank3_dfii_pi3_rddata3_re; -wire [7:0] vns_csrbank3_dfii_pi3_rddata3_r; -wire vns_csrbank3_dfii_pi3_rddata3_we; -wire [7:0] vns_csrbank3_dfii_pi3_rddata3_w; -wire vns_csrbank3_dfii_pi3_rddata2_re; -wire [7:0] vns_csrbank3_dfii_pi3_rddata2_r; -wire vns_csrbank3_dfii_pi3_rddata2_we; -wire [7:0] vns_csrbank3_dfii_pi3_rddata2_w; -wire vns_csrbank3_dfii_pi3_rddata1_re; -wire [7:0] vns_csrbank3_dfii_pi3_rddata1_r; -wire vns_csrbank3_dfii_pi3_rddata1_we; -wire [7:0] vns_csrbank3_dfii_pi3_rddata1_w; -wire vns_csrbank3_dfii_pi3_rddata0_re; -wire [7:0] vns_csrbank3_dfii_pi3_rddata0_r; -wire vns_csrbank3_dfii_pi3_rddata0_we; -wire [7:0] vns_csrbank3_dfii_pi3_rddata0_w; -wire vns_csrbank3_sel; -wire [13:0] vns_interface4_bank_bus_adr; -wire vns_interface4_bank_bus_we; -wire [7:0] vns_interface4_bank_bus_dat_w; -reg [7:0] vns_interface4_bank_bus_dat_r = 8'd0; -wire vns_csrbank4_load3_re; -wire [7:0] vns_csrbank4_load3_r; -wire vns_csrbank4_load3_we; -wire [7:0] vns_csrbank4_load3_w; -wire vns_csrbank4_load2_re; -wire [7:0] vns_csrbank4_load2_r; -wire vns_csrbank4_load2_we; -wire [7:0] vns_csrbank4_load2_w; -wire vns_csrbank4_load1_re; -wire [7:0] vns_csrbank4_load1_r; -wire vns_csrbank4_load1_we; -wire [7:0] vns_csrbank4_load1_w; -wire vns_csrbank4_load0_re; -wire [7:0] vns_csrbank4_load0_r; -wire vns_csrbank4_load0_we; -wire [7:0] vns_csrbank4_load0_w; -wire vns_csrbank4_reload3_re; -wire [7:0] vns_csrbank4_reload3_r; -wire vns_csrbank4_reload3_we; -wire [7:0] vns_csrbank4_reload3_w; -wire vns_csrbank4_reload2_re; -wire [7:0] vns_csrbank4_reload2_r; -wire vns_csrbank4_reload2_we; -wire [7:0] vns_csrbank4_reload2_w; -wire vns_csrbank4_reload1_re; -wire [7:0] vns_csrbank4_reload1_r; -wire vns_csrbank4_reload1_we; -wire [7:0] vns_csrbank4_reload1_w; -wire vns_csrbank4_reload0_re; -wire [7:0] vns_csrbank4_reload0_r; -wire vns_csrbank4_reload0_we; -wire [7:0] vns_csrbank4_reload0_w; -wire vns_csrbank4_en0_re; -wire vns_csrbank4_en0_r; -wire vns_csrbank4_en0_we; -wire vns_csrbank4_en0_w; -wire vns_csrbank4_update_value0_re; -wire vns_csrbank4_update_value0_r; -wire vns_csrbank4_update_value0_we; -wire vns_csrbank4_update_value0_w; -wire vns_csrbank4_value3_re; -wire [7:0] vns_csrbank4_value3_r; -wire vns_csrbank4_value3_we; -wire [7:0] vns_csrbank4_value3_w; -wire vns_csrbank4_value2_re; -wire [7:0] vns_csrbank4_value2_r; -wire vns_csrbank4_value2_we; -wire [7:0] vns_csrbank4_value2_w; -wire vns_csrbank4_value1_re; -wire [7:0] vns_csrbank4_value1_r; -wire vns_csrbank4_value1_we; -wire [7:0] vns_csrbank4_value1_w; -wire vns_csrbank4_value0_re; -wire [7:0] vns_csrbank4_value0_r; -wire vns_csrbank4_value0_we; -wire [7:0] vns_csrbank4_value0_w; -wire vns_csrbank4_ev_enable0_re; -wire vns_csrbank4_ev_enable0_r; -wire vns_csrbank4_ev_enable0_we; -wire vns_csrbank4_ev_enable0_w; -wire vns_csrbank4_sel; -wire [13:0] vns_interface5_bank_bus_adr; -wire vns_interface5_bank_bus_we; -wire [7:0] vns_interface5_bank_bus_dat_w; -reg [7:0] vns_interface5_bank_bus_dat_r = 8'd0; -wire vns_csrbank5_txfull_re; -wire vns_csrbank5_txfull_r; -wire vns_csrbank5_txfull_we; -wire vns_csrbank5_txfull_w; -wire vns_csrbank5_rxempty_re; -wire vns_csrbank5_rxempty_r; -wire vns_csrbank5_rxempty_we; -wire vns_csrbank5_rxempty_w; -wire vns_csrbank5_ev_enable0_re; -wire [1:0] vns_csrbank5_ev_enable0_r; -wire vns_csrbank5_ev_enable0_we; -wire [1:0] vns_csrbank5_ev_enable0_w; -wire vns_csrbank5_sel; -wire [13:0] vns_interface6_bank_bus_adr; -wire vns_interface6_bank_bus_we; -wire [7:0] vns_interface6_bank_bus_dat_w; -reg [7:0] vns_interface6_bank_bus_dat_r = 8'd0; -wire vns_csrbank6_tuning_word3_re; -wire [7:0] vns_csrbank6_tuning_word3_r; -wire vns_csrbank6_tuning_word3_we; -wire [7:0] vns_csrbank6_tuning_word3_w; -wire vns_csrbank6_tuning_word2_re; -wire [7:0] vns_csrbank6_tuning_word2_r; -wire vns_csrbank6_tuning_word2_we; -wire [7:0] vns_csrbank6_tuning_word2_w; -wire vns_csrbank6_tuning_word1_re; -wire [7:0] vns_csrbank6_tuning_word1_r; -wire vns_csrbank6_tuning_word1_we; -wire [7:0] vns_csrbank6_tuning_word1_w; -wire vns_csrbank6_tuning_word0_re; -wire [7:0] vns_csrbank6_tuning_word0_r; -wire vns_csrbank6_tuning_word0_we; -wire [7:0] vns_csrbank6_tuning_word0_w; -wire vns_csrbank6_sel; -wire [13:0] vns_adr; -wire vns_we; -wire [7:0] vns_dat_w; -wire [7:0] vns_dat_r; -reg vns_rhs_array_muxed0 = 1'd0; -reg [13:0] vns_rhs_array_muxed1 = 14'd0; -reg [2:0] vns_rhs_array_muxed2 = 3'd0; -reg vns_rhs_array_muxed3 = 1'd0; -reg vns_rhs_array_muxed4 = 1'd0; -reg vns_rhs_array_muxed5 = 1'd0; -reg vns_t_array_muxed0 = 1'd0; -reg vns_t_array_muxed1 = 1'd0; -reg vns_t_array_muxed2 = 1'd0; -reg vns_rhs_array_muxed6 = 1'd0; -reg [13:0] vns_rhs_array_muxed7 = 14'd0; -reg [2:0] vns_rhs_array_muxed8 = 3'd0; -reg vns_rhs_array_muxed9 = 1'd0; -reg vns_rhs_array_muxed10 = 1'd0; -reg vns_rhs_array_muxed11 = 1'd0; -reg vns_t_array_muxed3 = 1'd0; -reg vns_t_array_muxed4 = 1'd0; -reg vns_t_array_muxed5 = 1'd0; -reg [20:0] vns_rhs_array_muxed12 = 21'd0; -reg vns_rhs_array_muxed13 = 1'd0; -reg vns_rhs_array_muxed14 = 1'd0; -reg [20:0] vns_rhs_array_muxed15 = 21'd0; -reg vns_rhs_array_muxed16 = 1'd0; -reg vns_rhs_array_muxed17 = 1'd0; -reg [20:0] vns_rhs_array_muxed18 = 21'd0; -reg vns_rhs_array_muxed19 = 1'd0; -reg vns_rhs_array_muxed20 = 1'd0; -reg [20:0] vns_rhs_array_muxed21 = 21'd0; -reg vns_rhs_array_muxed22 = 1'd0; -reg vns_rhs_array_muxed23 = 1'd0; -reg [20:0] vns_rhs_array_muxed24 = 21'd0; -reg vns_rhs_array_muxed25 = 1'd0; -reg vns_rhs_array_muxed26 = 1'd0; -reg [20:0] vns_rhs_array_muxed27 = 21'd0; -reg vns_rhs_array_muxed28 = 1'd0; -reg vns_rhs_array_muxed29 = 1'd0; -reg [20:0] vns_rhs_array_muxed30 = 21'd0; -reg vns_rhs_array_muxed31 = 1'd0; -reg vns_rhs_array_muxed32 = 1'd0; -reg [20:0] vns_rhs_array_muxed33 = 21'd0; -reg vns_rhs_array_muxed34 = 1'd0; -reg vns_rhs_array_muxed35 = 1'd0; -reg [29:0] vns_rhs_array_muxed36 = 30'd0; -reg [31:0] vns_rhs_array_muxed37 = 32'd0; -reg [3:0] vns_rhs_array_muxed38 = 4'd0; -reg vns_rhs_array_muxed39 = 1'd0; -reg vns_rhs_array_muxed40 = 1'd0; -reg vns_rhs_array_muxed41 = 1'd0; -reg [2:0] vns_rhs_array_muxed42 = 3'd0; -reg [1:0] vns_rhs_array_muxed43 = 2'd0; -reg [2:0] vns_array_muxed0 = 3'd0; -reg [13:0] vns_array_muxed1 = 14'd0; -reg vns_array_muxed2 = 1'd0; -reg vns_array_muxed3 = 1'd0; -reg vns_array_muxed4 = 1'd0; -reg vns_array_muxed5 = 1'd0; -reg vns_array_muxed6 = 1'd0; -reg [2:0] vns_array_muxed7 = 3'd0; -reg [13:0] vns_array_muxed8 = 14'd0; -reg vns_array_muxed9 = 1'd0; -reg vns_array_muxed10 = 1'd0; -reg vns_array_muxed11 = 1'd0; -reg vns_array_muxed12 = 1'd0; -reg vns_array_muxed13 = 1'd0; -reg [2:0] vns_array_muxed14 = 3'd0; -reg [13:0] vns_array_muxed15 = 14'd0; -reg vns_array_muxed16 = 1'd0; -reg vns_array_muxed17 = 1'd0; -reg vns_array_muxed18 = 1'd0; -reg vns_array_muxed19 = 1'd0; -reg vns_array_muxed20 = 1'd0; -reg [2:0] vns_array_muxed21 = 3'd0; -reg [13:0] vns_array_muxed22 = 14'd0; -reg vns_array_muxed23 = 1'd0; -reg vns_array_muxed24 = 1'd0; -reg vns_array_muxed25 = 1'd0; -reg vns_array_muxed26 = 1'd0; -reg vns_array_muxed27 = 1'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg vns_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg vns_regs1 = 1'd0; -wire vns_xilinxasyncresetsynchronizerimpl0; -wire vns_xilinxasyncresetsynchronizerimpl0_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl1; -wire vns_xilinxasyncresetsynchronizerimpl1_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl1_expr; -wire vns_xilinxasyncresetsynchronizerimpl2; -wire vns_xilinxasyncresetsynchronizerimpl2_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl2_expr; -wire vns_xilinxasyncresetsynchronizerimpl3; -wire vns_xilinxasyncresetsynchronizerimpl3_rst_meta; +wire sys_pll_reset; +wire sys_pll_locked; +wire s7pll0_clkin; +wire s7pll0_clkout0; +wire s7pll0_clkout_buf0; +wire s7pll0_clkout1; +wire s7pll0_clkout_buf1; +wire s7pll0_clkout2; +wire s7pll0_clkout_buf2; +wire iodelay_pll_reset; +wire iodelay_pll_locked; +wire s7pll1_clkin; +wire s7pll1_clkout; +wire s7pll1_clkout_buf; +reg [3:0] reset_counter = 4'd15; +reg ic_reset = 1'd1; +reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8; +reg a7ddrphy_half_sys8x_taps_re = 1'd0; +reg a7ddrphy_wlevel_en_storage = 1'd0; +reg a7ddrphy_wlevel_en_re = 1'd0; +wire a7ddrphy_wlevel_strobe_re; +wire a7ddrphy_wlevel_strobe_r; +wire a7ddrphy_wlevel_strobe_we; +reg a7ddrphy_wlevel_strobe_w = 1'd0; +wire a7ddrphy_cdly_rst_re; +wire a7ddrphy_cdly_rst_r; +wire a7ddrphy_cdly_rst_we; +reg a7ddrphy_cdly_rst_w = 1'd0; +wire a7ddrphy_cdly_inc_re; +wire a7ddrphy_cdly_inc_r; +wire a7ddrphy_cdly_inc_we; +reg a7ddrphy_cdly_inc_w = 1'd0; +reg [1:0] a7ddrphy_dly_sel_storage = 2'd0; +reg a7ddrphy_dly_sel_re = 1'd0; +wire a7ddrphy_rdly_dq_rst_re; +wire a7ddrphy_rdly_dq_rst_r; +wire a7ddrphy_rdly_dq_rst_we; +reg a7ddrphy_rdly_dq_rst_w = 1'd0; +wire a7ddrphy_rdly_dq_inc_re; +wire a7ddrphy_rdly_dq_inc_r; +wire a7ddrphy_rdly_dq_inc_we; +reg a7ddrphy_rdly_dq_inc_w = 1'd0; +wire a7ddrphy_rdly_dq_bitslip_rst_re; +wire a7ddrphy_rdly_dq_bitslip_rst_r; +wire a7ddrphy_rdly_dq_bitslip_rst_we; +reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +wire a7ddrphy_rdly_dq_bitslip_re; +wire a7ddrphy_rdly_dq_bitslip_r; +wire a7ddrphy_rdly_dq_bitslip_we; +reg a7ddrphy_rdly_dq_bitslip_w = 1'd0; +wire [13:0] a7ddrphy_dfi_p0_address; +wire [2:0] a7ddrphy_dfi_p0_bank; +wire a7ddrphy_dfi_p0_cas_n; +wire a7ddrphy_dfi_p0_cs_n; +wire a7ddrphy_dfi_p0_ras_n; +wire a7ddrphy_dfi_p0_we_n; +wire a7ddrphy_dfi_p0_cke; +wire a7ddrphy_dfi_p0_odt; +wire a7ddrphy_dfi_p0_reset_n; +wire a7ddrphy_dfi_p0_act_n; +wire [31:0] a7ddrphy_dfi_p0_wrdata; +wire a7ddrphy_dfi_p0_wrdata_en; +wire [3:0] a7ddrphy_dfi_p0_wrdata_mask; +wire a7ddrphy_dfi_p0_rddata_en; +reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0; +reg a7ddrphy_dfi_p0_rddata_valid = 1'd0; +wire [13:0] a7ddrphy_dfi_p1_address; +wire [2:0] a7ddrphy_dfi_p1_bank; +wire a7ddrphy_dfi_p1_cas_n; +wire a7ddrphy_dfi_p1_cs_n; +wire a7ddrphy_dfi_p1_ras_n; +wire a7ddrphy_dfi_p1_we_n; +wire a7ddrphy_dfi_p1_cke; +wire a7ddrphy_dfi_p1_odt; +wire a7ddrphy_dfi_p1_reset_n; +wire a7ddrphy_dfi_p1_act_n; +wire [31:0] a7ddrphy_dfi_p1_wrdata; +wire a7ddrphy_dfi_p1_wrdata_en; +wire [3:0] a7ddrphy_dfi_p1_wrdata_mask; +wire a7ddrphy_dfi_p1_rddata_en; +reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0; +reg a7ddrphy_dfi_p1_rddata_valid = 1'd0; +wire [13:0] a7ddrphy_dfi_p2_address; +wire [2:0] a7ddrphy_dfi_p2_bank; +wire a7ddrphy_dfi_p2_cas_n; +wire a7ddrphy_dfi_p2_cs_n; +wire a7ddrphy_dfi_p2_ras_n; +wire a7ddrphy_dfi_p2_we_n; +wire a7ddrphy_dfi_p2_cke; +wire a7ddrphy_dfi_p2_odt; +wire a7ddrphy_dfi_p2_reset_n; +wire a7ddrphy_dfi_p2_act_n; +wire [31:0] a7ddrphy_dfi_p2_wrdata; +wire a7ddrphy_dfi_p2_wrdata_en; +wire [3:0] a7ddrphy_dfi_p2_wrdata_mask; +wire a7ddrphy_dfi_p2_rddata_en; +reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0; +reg a7ddrphy_dfi_p2_rddata_valid = 1'd0; +wire [13:0] a7ddrphy_dfi_p3_address; +wire [2:0] a7ddrphy_dfi_p3_bank; +wire a7ddrphy_dfi_p3_cas_n; +wire a7ddrphy_dfi_p3_cs_n; +wire a7ddrphy_dfi_p3_ras_n; +wire a7ddrphy_dfi_p3_we_n; +wire a7ddrphy_dfi_p3_cke; +wire a7ddrphy_dfi_p3_odt; +wire a7ddrphy_dfi_p3_reset_n; +wire a7ddrphy_dfi_p3_act_n; +wire [31:0] a7ddrphy_dfi_p3_wrdata; +wire a7ddrphy_dfi_p3_wrdata_en; +wire [3:0] a7ddrphy_dfi_p3_wrdata_mask; +wire a7ddrphy_dfi_p3_rddata_en; +reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0; +reg a7ddrphy_dfi_p3_rddata_valid = 1'd0; +wire a7ddrphy_sd_clk_se_nodelay; +reg a7ddrphy_dqs_oe = 1'd0; +reg a7ddrphy_dqs_oe_delayed = 1'd0; +wire a7ddrphy_dqspattern0; +wire a7ddrphy_dqspattern1; +reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0; +wire [1:0] a7ddrphy_dqs_i; +wire [1:0] a7ddrphy_dqs_i_delayed; +wire a7ddrphy_dqs_o_no_delay0; +wire a7ddrphy_dqs_t0; +wire a7ddrphy0; +wire a7ddrphy_dqs_o_no_delay1; +wire a7ddrphy_dqs_t1; +wire a7ddrphy1; +wire a7ddrphy_dq_oe; +reg a7ddrphy_dq_oe_delayed = 1'd0; +wire a7ddrphy_dq_o_nodelay0; +wire a7ddrphy_dq_i_nodelay0; +wire a7ddrphy_dq_i_delayed0; +wire a7ddrphy_dq_t0; +wire [7:0] a7ddrphy_dq_i_data0; +wire [7:0] a7ddrphy_bitslip0_i; +reg [7:0] a7ddrphy_bitslip0_o = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value = 3'd0; +reg [15:0] a7ddrphy_bitslip0_r = 16'd0; +wire a7ddrphy_dq_o_nodelay1; +wire a7ddrphy_dq_i_nodelay1; +wire a7ddrphy_dq_i_delayed1; +wire a7ddrphy_dq_t1; +wire [7:0] a7ddrphy_dq_i_data1; +wire [7:0] a7ddrphy_bitslip1_i; +reg [7:0] a7ddrphy_bitslip1_o = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value = 3'd0; +reg [15:0] a7ddrphy_bitslip1_r = 16'd0; +wire a7ddrphy_dq_o_nodelay2; +wire a7ddrphy_dq_i_nodelay2; +wire a7ddrphy_dq_i_delayed2; +wire a7ddrphy_dq_t2; +wire [7:0] a7ddrphy_dq_i_data2; +wire [7:0] a7ddrphy_bitslip2_i; +reg [7:0] a7ddrphy_bitslip2_o = 8'd0; +reg [2:0] a7ddrphy_bitslip2_value = 3'd0; +reg [15:0] a7ddrphy_bitslip2_r = 16'd0; +wire a7ddrphy_dq_o_nodelay3; +wire a7ddrphy_dq_i_nodelay3; +wire a7ddrphy_dq_i_delayed3; +wire a7ddrphy_dq_t3; +wire [7:0] a7ddrphy_dq_i_data3; +wire [7:0] a7ddrphy_bitslip3_i; +reg [7:0] a7ddrphy_bitslip3_o = 8'd0; +reg [2:0] a7ddrphy_bitslip3_value = 3'd0; +reg [15:0] a7ddrphy_bitslip3_r = 16'd0; +wire a7ddrphy_dq_o_nodelay4; +wire a7ddrphy_dq_i_nodelay4; +wire a7ddrphy_dq_i_delayed4; +wire a7ddrphy_dq_t4; +wire [7:0] a7ddrphy_dq_i_data4; +wire [7:0] a7ddrphy_bitslip4_i; +reg [7:0] a7ddrphy_bitslip4_o = 8'd0; +reg [2:0] a7ddrphy_bitslip4_value = 3'd0; +reg [15:0] a7ddrphy_bitslip4_r = 16'd0; +wire a7ddrphy_dq_o_nodelay5; +wire a7ddrphy_dq_i_nodelay5; +wire a7ddrphy_dq_i_delayed5; +wire a7ddrphy_dq_t5; +wire [7:0] a7ddrphy_dq_i_data5; +wire [7:0] a7ddrphy_bitslip5_i; +reg [7:0] a7ddrphy_bitslip5_o = 8'd0; +reg [2:0] a7ddrphy_bitslip5_value = 3'd0; +reg [15:0] a7ddrphy_bitslip5_r = 16'd0; +wire a7ddrphy_dq_o_nodelay6; +wire a7ddrphy_dq_i_nodelay6; +wire a7ddrphy_dq_i_delayed6; +wire a7ddrphy_dq_t6; +wire [7:0] a7ddrphy_dq_i_data6; +wire [7:0] a7ddrphy_bitslip6_i; +reg [7:0] a7ddrphy_bitslip6_o = 8'd0; +reg [2:0] a7ddrphy_bitslip6_value = 3'd0; +reg [15:0] a7ddrphy_bitslip6_r = 16'd0; +wire a7ddrphy_dq_o_nodelay7; +wire a7ddrphy_dq_i_nodelay7; +wire a7ddrphy_dq_i_delayed7; +wire a7ddrphy_dq_t7; +wire [7:0] a7ddrphy_dq_i_data7; +wire [7:0] a7ddrphy_bitslip7_i; +reg [7:0] a7ddrphy_bitslip7_o = 8'd0; +reg [2:0] a7ddrphy_bitslip7_value = 3'd0; +reg [15:0] a7ddrphy_bitslip7_r = 16'd0; +wire a7ddrphy_dq_o_nodelay8; +wire a7ddrphy_dq_i_nodelay8; +wire a7ddrphy_dq_i_delayed8; +wire a7ddrphy_dq_t8; +wire [7:0] a7ddrphy_dq_i_data8; +wire [7:0] a7ddrphy_bitslip8_i; +reg [7:0] a7ddrphy_bitslip8_o = 8'd0; +reg [2:0] a7ddrphy_bitslip8_value = 3'd0; +reg [15:0] a7ddrphy_bitslip8_r = 16'd0; +wire a7ddrphy_dq_o_nodelay9; +wire a7ddrphy_dq_i_nodelay9; +wire a7ddrphy_dq_i_delayed9; +wire a7ddrphy_dq_t9; +wire [7:0] a7ddrphy_dq_i_data9; +wire [7:0] a7ddrphy_bitslip9_i; +reg [7:0] a7ddrphy_bitslip9_o = 8'd0; +reg [2:0] a7ddrphy_bitslip9_value = 3'd0; +reg [15:0] a7ddrphy_bitslip9_r = 16'd0; +wire a7ddrphy_dq_o_nodelay10; +wire a7ddrphy_dq_i_nodelay10; +wire a7ddrphy_dq_i_delayed10; +wire a7ddrphy_dq_t10; +wire [7:0] a7ddrphy_dq_i_data10; +wire [7:0] a7ddrphy_bitslip10_i; +reg [7:0] a7ddrphy_bitslip10_o = 8'd0; +reg [2:0] a7ddrphy_bitslip10_value = 3'd0; +reg [15:0] a7ddrphy_bitslip10_r = 16'd0; +wire a7ddrphy_dq_o_nodelay11; +wire a7ddrphy_dq_i_nodelay11; +wire a7ddrphy_dq_i_delayed11; +wire a7ddrphy_dq_t11; +wire [7:0] a7ddrphy_dq_i_data11; +wire [7:0] a7ddrphy_bitslip11_i; +reg [7:0] a7ddrphy_bitslip11_o = 8'd0; +reg [2:0] a7ddrphy_bitslip11_value = 3'd0; +reg [15:0] a7ddrphy_bitslip11_r = 16'd0; +wire a7ddrphy_dq_o_nodelay12; +wire a7ddrphy_dq_i_nodelay12; +wire a7ddrphy_dq_i_delayed12; +wire a7ddrphy_dq_t12; +wire [7:0] a7ddrphy_dq_i_data12; +wire [7:0] a7ddrphy_bitslip12_i; +reg [7:0] a7ddrphy_bitslip12_o = 8'd0; +reg [2:0] a7ddrphy_bitslip12_value = 3'd0; +reg [15:0] a7ddrphy_bitslip12_r = 16'd0; +wire a7ddrphy_dq_o_nodelay13; +wire a7ddrphy_dq_i_nodelay13; +wire a7ddrphy_dq_i_delayed13; +wire a7ddrphy_dq_t13; +wire [7:0] a7ddrphy_dq_i_data13; +wire [7:0] a7ddrphy_bitslip13_i; +reg [7:0] a7ddrphy_bitslip13_o = 8'd0; +reg [2:0] a7ddrphy_bitslip13_value = 3'd0; +reg [15:0] a7ddrphy_bitslip13_r = 16'd0; +wire a7ddrphy_dq_o_nodelay14; +wire a7ddrphy_dq_i_nodelay14; +wire a7ddrphy_dq_i_delayed14; +wire a7ddrphy_dq_t14; +wire [7:0] a7ddrphy_dq_i_data14; +wire [7:0] a7ddrphy_bitslip14_i; +reg [7:0] a7ddrphy_bitslip14_o = 8'd0; +reg [2:0] a7ddrphy_bitslip14_value = 3'd0; +reg [15:0] a7ddrphy_bitslip14_r = 16'd0; +wire a7ddrphy_dq_o_nodelay15; +wire a7ddrphy_dq_i_nodelay15; +wire a7ddrphy_dq_i_delayed15; +wire a7ddrphy_dq_t15; +wire [7:0] a7ddrphy_dq_i_data15; +wire [7:0] a7ddrphy_bitslip15_i; +reg [7:0] a7ddrphy_bitslip15_o = 8'd0; +reg [2:0] a7ddrphy_bitslip15_value = 3'd0; +reg [15:0] a7ddrphy_bitslip15_r = 16'd0; +wire [7:0] a7ddrphy_rddata_en; +reg [7:0] a7ddrphy_rddata_en_last = 8'd0; +wire [3:0] a7ddrphy_wrdata_en; +reg [3:0] a7ddrphy_wrdata_en_last = 4'd0; +wire [13:0] litedramcore_inti_p0_address; +wire [2:0] litedramcore_inti_p0_bank; +reg litedramcore_inti_p0_cas_n = 1'd1; +reg litedramcore_inti_p0_cs_n = 1'd1; +reg litedramcore_inti_p0_ras_n = 1'd1; +reg litedramcore_inti_p0_we_n = 1'd1; +wire litedramcore_inti_p0_cke; +wire litedramcore_inti_p0_odt; +wire litedramcore_inti_p0_reset_n; +reg litedramcore_inti_p0_act_n = 1'd1; +wire [31:0] litedramcore_inti_p0_wrdata; +wire litedramcore_inti_p0_wrdata_en; +wire [3:0] litedramcore_inti_p0_wrdata_mask; +wire litedramcore_inti_p0_rddata_en; +reg [31:0] litedramcore_inti_p0_rddata = 32'd0; +reg litedramcore_inti_p0_rddata_valid = 1'd0; +wire [13:0] litedramcore_inti_p1_address; +wire [2:0] litedramcore_inti_p1_bank; +reg litedramcore_inti_p1_cas_n = 1'd1; +reg litedramcore_inti_p1_cs_n = 1'd1; +reg litedramcore_inti_p1_ras_n = 1'd1; +reg litedramcore_inti_p1_we_n = 1'd1; +wire litedramcore_inti_p1_cke; +wire litedramcore_inti_p1_odt; +wire litedramcore_inti_p1_reset_n; +reg litedramcore_inti_p1_act_n = 1'd1; +wire [31:0] litedramcore_inti_p1_wrdata; +wire litedramcore_inti_p1_wrdata_en; +wire [3:0] litedramcore_inti_p1_wrdata_mask; +wire litedramcore_inti_p1_rddata_en; +reg [31:0] litedramcore_inti_p1_rddata = 32'd0; +reg litedramcore_inti_p1_rddata_valid = 1'd0; +wire [13:0] litedramcore_inti_p2_address; +wire [2:0] litedramcore_inti_p2_bank; +reg litedramcore_inti_p2_cas_n = 1'd1; +reg litedramcore_inti_p2_cs_n = 1'd1; +reg litedramcore_inti_p2_ras_n = 1'd1; +reg litedramcore_inti_p2_we_n = 1'd1; +wire litedramcore_inti_p2_cke; +wire litedramcore_inti_p2_odt; +wire litedramcore_inti_p2_reset_n; +reg litedramcore_inti_p2_act_n = 1'd1; +wire [31:0] litedramcore_inti_p2_wrdata; +wire litedramcore_inti_p2_wrdata_en; +wire [3:0] litedramcore_inti_p2_wrdata_mask; +wire litedramcore_inti_p2_rddata_en; +reg [31:0] litedramcore_inti_p2_rddata = 32'd0; +reg litedramcore_inti_p2_rddata_valid = 1'd0; +wire [13:0] litedramcore_inti_p3_address; +wire [2:0] litedramcore_inti_p3_bank; +reg litedramcore_inti_p3_cas_n = 1'd1; +reg litedramcore_inti_p3_cs_n = 1'd1; +reg litedramcore_inti_p3_ras_n = 1'd1; +reg litedramcore_inti_p3_we_n = 1'd1; +wire litedramcore_inti_p3_cke; +wire litedramcore_inti_p3_odt; +wire litedramcore_inti_p3_reset_n; +reg litedramcore_inti_p3_act_n = 1'd1; +wire [31:0] litedramcore_inti_p3_wrdata; +wire litedramcore_inti_p3_wrdata_en; +wire [3:0] litedramcore_inti_p3_wrdata_mask; +wire litedramcore_inti_p3_rddata_en; +reg [31:0] litedramcore_inti_p3_rddata = 32'd0; +reg litedramcore_inti_p3_rddata_valid = 1'd0; +wire [13:0] litedramcore_slave_p0_address; +wire [2:0] litedramcore_slave_p0_bank; +wire litedramcore_slave_p0_cas_n; +wire litedramcore_slave_p0_cs_n; +wire litedramcore_slave_p0_ras_n; +wire litedramcore_slave_p0_we_n; +wire litedramcore_slave_p0_cke; +wire litedramcore_slave_p0_odt; +wire litedramcore_slave_p0_reset_n; +wire litedramcore_slave_p0_act_n; +wire [31:0] litedramcore_slave_p0_wrdata; +wire litedramcore_slave_p0_wrdata_en; +wire [3:0] litedramcore_slave_p0_wrdata_mask; +wire litedramcore_slave_p0_rddata_en; +reg [31:0] litedramcore_slave_p0_rddata = 32'd0; +reg litedramcore_slave_p0_rddata_valid = 1'd0; +wire [13:0] litedramcore_slave_p1_address; +wire [2:0] litedramcore_slave_p1_bank; +wire litedramcore_slave_p1_cas_n; +wire litedramcore_slave_p1_cs_n; +wire litedramcore_slave_p1_ras_n; +wire litedramcore_slave_p1_we_n; +wire litedramcore_slave_p1_cke; +wire litedramcore_slave_p1_odt; +wire litedramcore_slave_p1_reset_n; +wire litedramcore_slave_p1_act_n; +wire [31:0] litedramcore_slave_p1_wrdata; +wire litedramcore_slave_p1_wrdata_en; +wire [3:0] litedramcore_slave_p1_wrdata_mask; +wire litedramcore_slave_p1_rddata_en; +reg [31:0] litedramcore_slave_p1_rddata = 32'd0; +reg litedramcore_slave_p1_rddata_valid = 1'd0; +wire [13:0] litedramcore_slave_p2_address; +wire [2:0] litedramcore_slave_p2_bank; +wire litedramcore_slave_p2_cas_n; +wire litedramcore_slave_p2_cs_n; +wire litedramcore_slave_p2_ras_n; +wire litedramcore_slave_p2_we_n; +wire litedramcore_slave_p2_cke; +wire litedramcore_slave_p2_odt; +wire litedramcore_slave_p2_reset_n; +wire litedramcore_slave_p2_act_n; +wire [31:0] litedramcore_slave_p2_wrdata; +wire litedramcore_slave_p2_wrdata_en; +wire [3:0] litedramcore_slave_p2_wrdata_mask; +wire litedramcore_slave_p2_rddata_en; +reg [31:0] litedramcore_slave_p2_rddata = 32'd0; +reg litedramcore_slave_p2_rddata_valid = 1'd0; +wire [13:0] litedramcore_slave_p3_address; +wire [2:0] litedramcore_slave_p3_bank; +wire litedramcore_slave_p3_cas_n; +wire litedramcore_slave_p3_cs_n; +wire litedramcore_slave_p3_ras_n; +wire litedramcore_slave_p3_we_n; +wire litedramcore_slave_p3_cke; +wire litedramcore_slave_p3_odt; +wire litedramcore_slave_p3_reset_n; +wire litedramcore_slave_p3_act_n; +wire [31:0] litedramcore_slave_p3_wrdata; +wire litedramcore_slave_p3_wrdata_en; +wire [3:0] litedramcore_slave_p3_wrdata_mask; +wire litedramcore_slave_p3_rddata_en; +reg [31:0] litedramcore_slave_p3_rddata = 32'd0; +reg litedramcore_slave_p3_rddata_valid = 1'd0; +reg [13:0] litedramcore_master_p0_address = 14'd0; +reg [2:0] litedramcore_master_p0_bank = 3'd0; +reg litedramcore_master_p0_cas_n = 1'd1; +reg litedramcore_master_p0_cs_n = 1'd1; +reg litedramcore_master_p0_ras_n = 1'd1; +reg litedramcore_master_p0_we_n = 1'd1; +reg litedramcore_master_p0_cke = 1'd0; +reg litedramcore_master_p0_odt = 1'd0; +reg litedramcore_master_p0_reset_n = 1'd0; +reg litedramcore_master_p0_act_n = 1'd1; +reg [31:0] litedramcore_master_p0_wrdata = 32'd0; +reg litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0; +reg litedramcore_master_p0_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p0_rddata; +wire litedramcore_master_p0_rddata_valid; +reg [13:0] litedramcore_master_p1_address = 14'd0; +reg [2:0] litedramcore_master_p1_bank = 3'd0; +reg litedramcore_master_p1_cas_n = 1'd1; +reg litedramcore_master_p1_cs_n = 1'd1; +reg litedramcore_master_p1_ras_n = 1'd1; +reg litedramcore_master_p1_we_n = 1'd1; +reg litedramcore_master_p1_cke = 1'd0; +reg litedramcore_master_p1_odt = 1'd0; +reg litedramcore_master_p1_reset_n = 1'd0; +reg litedramcore_master_p1_act_n = 1'd1; +reg [31:0] litedramcore_master_p1_wrdata = 32'd0; +reg litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0; +reg litedramcore_master_p1_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p1_rddata; +wire litedramcore_master_p1_rddata_valid; +reg [13:0] litedramcore_master_p2_address = 14'd0; +reg [2:0] litedramcore_master_p2_bank = 3'd0; +reg litedramcore_master_p2_cas_n = 1'd1; +reg litedramcore_master_p2_cs_n = 1'd1; +reg litedramcore_master_p2_ras_n = 1'd1; +reg litedramcore_master_p2_we_n = 1'd1; +reg litedramcore_master_p2_cke = 1'd0; +reg litedramcore_master_p2_odt = 1'd0; +reg litedramcore_master_p2_reset_n = 1'd0; +reg litedramcore_master_p2_act_n = 1'd1; +reg [31:0] litedramcore_master_p2_wrdata = 32'd0; +reg litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0; +reg litedramcore_master_p2_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p2_rddata; +wire litedramcore_master_p2_rddata_valid; +reg [13:0] litedramcore_master_p3_address = 14'd0; +reg [2:0] litedramcore_master_p3_bank = 3'd0; +reg litedramcore_master_p3_cas_n = 1'd1; +reg litedramcore_master_p3_cs_n = 1'd1; +reg litedramcore_master_p3_ras_n = 1'd1; +reg litedramcore_master_p3_we_n = 1'd1; +reg litedramcore_master_p3_cke = 1'd0; +reg litedramcore_master_p3_odt = 1'd0; +reg litedramcore_master_p3_reset_n = 1'd0; +reg litedramcore_master_p3_act_n = 1'd1; +reg [31:0] litedramcore_master_p3_wrdata = 32'd0; +reg litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0; +reg litedramcore_master_p3_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p3_rddata; +wire litedramcore_master_p3_rddata_valid; +reg [3:0] litedramcore_storage = 4'd0; +reg litedramcore_re = 1'd0; +reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; +reg litedramcore_phaseinjector0_command_re = 1'd0; +wire litedramcore_phaseinjector0_command_issue_re; +wire litedramcore_phaseinjector0_command_issue_r; +wire litedramcore_phaseinjector0_command_issue_we; +reg litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [13:0] litedramcore_phaseinjector0_address_storage = 14'd0; +reg litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector0_status = 32'd0; +wire litedramcore_phaseinjector0_we; +reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; +reg litedramcore_phaseinjector1_command_re = 1'd0; +wire litedramcore_phaseinjector1_command_issue_re; +wire litedramcore_phaseinjector1_command_issue_r; +wire litedramcore_phaseinjector1_command_issue_we; +reg litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [13:0] litedramcore_phaseinjector1_address_storage = 14'd0; +reg litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector1_status = 32'd0; +wire litedramcore_phaseinjector1_we; +reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0; +reg litedramcore_phaseinjector2_command_re = 1'd0; +wire litedramcore_phaseinjector2_command_issue_re; +wire litedramcore_phaseinjector2_command_issue_r; +wire litedramcore_phaseinjector2_command_issue_we; +reg litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [13:0] litedramcore_phaseinjector2_address_storage = 14'd0; +reg litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector2_status = 32'd0; +wire litedramcore_phaseinjector2_we; +reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0; +reg litedramcore_phaseinjector3_command_re = 1'd0; +wire litedramcore_phaseinjector3_command_issue_re; +wire litedramcore_phaseinjector3_command_issue_r; +wire litedramcore_phaseinjector3_command_issue_we; +reg litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [13:0] litedramcore_phaseinjector3_address_storage = 14'd0; +reg litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector3_status = 32'd0; +wire litedramcore_phaseinjector3_we; +wire litedramcore_interface_bank0_valid; +wire litedramcore_interface_bank0_ready; +wire litedramcore_interface_bank0_we; +wire [20:0] litedramcore_interface_bank0_addr; +wire litedramcore_interface_bank0_lock; +wire litedramcore_interface_bank0_wdata_ready; +wire litedramcore_interface_bank0_rdata_valid; +wire litedramcore_interface_bank1_valid; +wire litedramcore_interface_bank1_ready; +wire litedramcore_interface_bank1_we; +wire [20:0] litedramcore_interface_bank1_addr; +wire litedramcore_interface_bank1_lock; +wire litedramcore_interface_bank1_wdata_ready; +wire litedramcore_interface_bank1_rdata_valid; +wire litedramcore_interface_bank2_valid; +wire litedramcore_interface_bank2_ready; +wire litedramcore_interface_bank2_we; +wire [20:0] litedramcore_interface_bank2_addr; +wire litedramcore_interface_bank2_lock; +wire litedramcore_interface_bank2_wdata_ready; +wire litedramcore_interface_bank2_rdata_valid; +wire litedramcore_interface_bank3_valid; +wire litedramcore_interface_bank3_ready; +wire litedramcore_interface_bank3_we; +wire [20:0] litedramcore_interface_bank3_addr; +wire litedramcore_interface_bank3_lock; +wire litedramcore_interface_bank3_wdata_ready; +wire litedramcore_interface_bank3_rdata_valid; +wire litedramcore_interface_bank4_valid; +wire litedramcore_interface_bank4_ready; +wire litedramcore_interface_bank4_we; +wire [20:0] litedramcore_interface_bank4_addr; +wire litedramcore_interface_bank4_lock; +wire litedramcore_interface_bank4_wdata_ready; +wire litedramcore_interface_bank4_rdata_valid; +wire litedramcore_interface_bank5_valid; +wire litedramcore_interface_bank5_ready; +wire litedramcore_interface_bank5_we; +wire [20:0] litedramcore_interface_bank5_addr; +wire litedramcore_interface_bank5_lock; +wire litedramcore_interface_bank5_wdata_ready; +wire litedramcore_interface_bank5_rdata_valid; +wire litedramcore_interface_bank6_valid; +wire litedramcore_interface_bank6_ready; +wire litedramcore_interface_bank6_we; +wire [20:0] litedramcore_interface_bank6_addr; +wire litedramcore_interface_bank6_lock; +wire litedramcore_interface_bank6_wdata_ready; +wire litedramcore_interface_bank6_rdata_valid; +wire litedramcore_interface_bank7_valid; +wire litedramcore_interface_bank7_ready; +wire litedramcore_interface_bank7_we; +wire [20:0] litedramcore_interface_bank7_addr; +wire litedramcore_interface_bank7_lock; +wire litedramcore_interface_bank7_wdata_ready; +wire litedramcore_interface_bank7_rdata_valid; +reg [127:0] litedramcore_interface_wdata = 128'd0; +reg [15:0] litedramcore_interface_wdata_we = 16'd0; +wire [127:0] litedramcore_interface_rdata; +reg [13:0] litedramcore_dfi_p0_address = 14'd0; +reg [2:0] litedramcore_dfi_p0_bank = 3'd0; +reg litedramcore_dfi_p0_cas_n = 1'd1; +reg litedramcore_dfi_p0_cs_n = 1'd1; +reg litedramcore_dfi_p0_ras_n = 1'd1; +reg litedramcore_dfi_p0_we_n = 1'd1; +wire litedramcore_dfi_p0_cke; +wire litedramcore_dfi_p0_odt; +wire litedramcore_dfi_p0_reset_n; +reg litedramcore_dfi_p0_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p0_wrdata; +reg litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p0_wrdata_mask; +reg litedramcore_dfi_p0_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p0_rddata; +wire litedramcore_dfi_p0_rddata_valid; +reg [13:0] litedramcore_dfi_p1_address = 14'd0; +reg [2:0] litedramcore_dfi_p1_bank = 3'd0; +reg litedramcore_dfi_p1_cas_n = 1'd1; +reg litedramcore_dfi_p1_cs_n = 1'd1; +reg litedramcore_dfi_p1_ras_n = 1'd1; +reg litedramcore_dfi_p1_we_n = 1'd1; +wire litedramcore_dfi_p1_cke; +wire litedramcore_dfi_p1_odt; +wire litedramcore_dfi_p1_reset_n; +reg litedramcore_dfi_p1_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p1_wrdata; +reg litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p1_wrdata_mask; +reg litedramcore_dfi_p1_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p1_rddata; +wire litedramcore_dfi_p1_rddata_valid; +reg [13:0] litedramcore_dfi_p2_address = 14'd0; +reg [2:0] litedramcore_dfi_p2_bank = 3'd0; +reg litedramcore_dfi_p2_cas_n = 1'd1; +reg litedramcore_dfi_p2_cs_n = 1'd1; +reg litedramcore_dfi_p2_ras_n = 1'd1; +reg litedramcore_dfi_p2_we_n = 1'd1; +wire litedramcore_dfi_p2_cke; +wire litedramcore_dfi_p2_odt; +wire litedramcore_dfi_p2_reset_n; +reg litedramcore_dfi_p2_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p2_wrdata; +reg litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p2_wrdata_mask; +reg litedramcore_dfi_p2_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p2_rddata; +wire litedramcore_dfi_p2_rddata_valid; +reg [13:0] litedramcore_dfi_p3_address = 14'd0; +reg [2:0] litedramcore_dfi_p3_bank = 3'd0; +reg litedramcore_dfi_p3_cas_n = 1'd1; +reg litedramcore_dfi_p3_cs_n = 1'd1; +reg litedramcore_dfi_p3_ras_n = 1'd1; +reg litedramcore_dfi_p3_we_n = 1'd1; +wire litedramcore_dfi_p3_cke; +wire litedramcore_dfi_p3_odt; +wire litedramcore_dfi_p3_reset_n; +reg litedramcore_dfi_p3_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p3_wrdata; +reg litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p3_wrdata_mask; +reg litedramcore_dfi_p3_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p3_rddata; +wire litedramcore_dfi_p3_rddata_valid; +reg litedramcore_cmd_valid = 1'd0; +reg litedramcore_cmd_ready = 1'd0; +reg litedramcore_cmd_last = 1'd0; +reg [13:0] litedramcore_cmd_payload_a = 14'd0; +reg [2:0] litedramcore_cmd_payload_ba = 3'd0; +reg litedramcore_cmd_payload_cas = 1'd0; +reg litedramcore_cmd_payload_ras = 1'd0; +reg litedramcore_cmd_payload_we = 1'd0; +reg litedramcore_cmd_payload_is_read = 1'd0; +reg litedramcore_cmd_payload_is_write = 1'd0; +wire litedramcore_wants_refresh; +wire litedramcore_wants_zqcs; +wire litedramcore_timer_wait; +wire litedramcore_timer_done0; +wire [9:0] litedramcore_timer_count0; +wire litedramcore_timer_done1; +reg [9:0] litedramcore_timer_count1 = 10'd781; +wire litedramcore_postponer_req_i; +reg litedramcore_postponer_req_o = 1'd0; +reg litedramcore_postponer_count = 1'd0; +reg litedramcore_sequencer_start0 = 1'd0; +wire litedramcore_sequencer_done0; +wire litedramcore_sequencer_start1; +reg litedramcore_sequencer_done1 = 1'd0; +reg [5:0] litedramcore_sequencer_counter = 6'd0; +reg litedramcore_sequencer_count = 1'd0; +wire litedramcore_zqcs_timer_wait; +wire litedramcore_zqcs_timer_done0; +wire [26:0] litedramcore_zqcs_timer_count0; +wire litedramcore_zqcs_timer_done1; +reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999; +reg litedramcore_zqcs_executer_start = 1'd0; +reg litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] litedramcore_zqcs_executer_counter = 5'd0; +wire litedramcore_bankmachine0_req_valid; +wire litedramcore_bankmachine0_req_ready; +wire litedramcore_bankmachine0_req_we; +wire [20:0] litedramcore_bankmachine0_req_addr; +wire litedramcore_bankmachine0_req_lock; +reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine0_refresh_req; +reg litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg litedramcore_bankmachine0_cmd_valid = 1'd0; +reg litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine0_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; +reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine0_auto_precharge = 1'd0; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; +wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; +wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine0_cmd_buffer_sink_valid; +wire litedramcore_bankmachine0_cmd_buffer_sink_ready; +wire litedramcore_bankmachine0_cmd_buffer_sink_first; +wire litedramcore_bankmachine0_cmd_buffer_sink_last; +wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we; +wire [20:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine0_cmd_buffer_source_ready; +reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine0_row = 14'd0; +reg litedramcore_bankmachine0_row_opened = 1'd0; +wire litedramcore_bankmachine0_row_hit; +reg litedramcore_bankmachine0_row_open = 1'd0; +reg litedramcore_bankmachine0_row_close = 1'd0; +reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine0_twtpcon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; +wire litedramcore_bankmachine0_trccon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0; +wire litedramcore_bankmachine0_trascon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0; +wire litedramcore_bankmachine1_req_valid; +wire litedramcore_bankmachine1_req_ready; +wire litedramcore_bankmachine1_req_we; +wire [20:0] litedramcore_bankmachine1_req_addr; +wire litedramcore_bankmachine1_req_lock; +reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine1_refresh_req; +reg litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg litedramcore_bankmachine1_cmd_valid = 1'd0; +reg litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine1_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; +reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine1_auto_precharge = 1'd0; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; +wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; +wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine1_cmd_buffer_sink_valid; +wire litedramcore_bankmachine1_cmd_buffer_sink_ready; +wire litedramcore_bankmachine1_cmd_buffer_sink_first; +wire litedramcore_bankmachine1_cmd_buffer_sink_last; +wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we; +wire [20:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine1_cmd_buffer_source_ready; +reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine1_row = 14'd0; +reg litedramcore_bankmachine1_row_opened = 1'd0; +wire litedramcore_bankmachine1_row_hit; +reg litedramcore_bankmachine1_row_open = 1'd0; +reg litedramcore_bankmachine1_row_close = 1'd0; +reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine1_twtpcon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; +wire litedramcore_bankmachine1_trccon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0; +wire litedramcore_bankmachine1_trascon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0; +wire litedramcore_bankmachine2_req_valid; +wire litedramcore_bankmachine2_req_ready; +wire litedramcore_bankmachine2_req_we; +wire [20:0] litedramcore_bankmachine2_req_addr; +wire litedramcore_bankmachine2_req_lock; +reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine2_refresh_req; +reg litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg litedramcore_bankmachine2_cmd_valid = 1'd0; +reg litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine2_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; +reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine2_auto_precharge = 1'd0; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; +wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; +wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine2_cmd_buffer_sink_valid; +wire litedramcore_bankmachine2_cmd_buffer_sink_ready; +wire litedramcore_bankmachine2_cmd_buffer_sink_first; +wire litedramcore_bankmachine2_cmd_buffer_sink_last; +wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we; +wire [20:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine2_cmd_buffer_source_ready; +reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine2_row = 14'd0; +reg litedramcore_bankmachine2_row_opened = 1'd0; +wire litedramcore_bankmachine2_row_hit; +reg litedramcore_bankmachine2_row_open = 1'd0; +reg litedramcore_bankmachine2_row_close = 1'd0; +reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine2_twtpcon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; +wire litedramcore_bankmachine2_trccon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0; +wire litedramcore_bankmachine2_trascon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0; +wire litedramcore_bankmachine3_req_valid; +wire litedramcore_bankmachine3_req_ready; +wire litedramcore_bankmachine3_req_we; +wire [20:0] litedramcore_bankmachine3_req_addr; +wire litedramcore_bankmachine3_req_lock; +reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine3_refresh_req; +reg litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg litedramcore_bankmachine3_cmd_valid = 1'd0; +reg litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine3_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; +reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine3_auto_precharge = 1'd0; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; +wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; +wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine3_cmd_buffer_sink_valid; +wire litedramcore_bankmachine3_cmd_buffer_sink_ready; +wire litedramcore_bankmachine3_cmd_buffer_sink_first; +wire litedramcore_bankmachine3_cmd_buffer_sink_last; +wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we; +wire [20:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine3_cmd_buffer_source_ready; +reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine3_row = 14'd0; +reg litedramcore_bankmachine3_row_opened = 1'd0; +wire litedramcore_bankmachine3_row_hit; +reg litedramcore_bankmachine3_row_open = 1'd0; +reg litedramcore_bankmachine3_row_close = 1'd0; +reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine3_twtpcon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; +wire litedramcore_bankmachine3_trccon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0; +wire litedramcore_bankmachine3_trascon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0; +wire litedramcore_bankmachine4_req_valid; +wire litedramcore_bankmachine4_req_ready; +wire litedramcore_bankmachine4_req_we; +wire [20:0] litedramcore_bankmachine4_req_addr; +wire litedramcore_bankmachine4_req_lock; +reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine4_refresh_req; +reg litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg litedramcore_bankmachine4_cmd_valid = 1'd0; +reg litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine4_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; +reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine4_auto_precharge = 1'd0; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; +wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; +wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine4_cmd_buffer_sink_valid; +wire litedramcore_bankmachine4_cmd_buffer_sink_ready; +wire litedramcore_bankmachine4_cmd_buffer_sink_first; +wire litedramcore_bankmachine4_cmd_buffer_sink_last; +wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we; +wire [20:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine4_cmd_buffer_source_ready; +reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine4_row = 14'd0; +reg litedramcore_bankmachine4_row_opened = 1'd0; +wire litedramcore_bankmachine4_row_hit; +reg litedramcore_bankmachine4_row_open = 1'd0; +reg litedramcore_bankmachine4_row_close = 1'd0; +reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine4_twtpcon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; +wire litedramcore_bankmachine4_trccon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0; +wire litedramcore_bankmachine4_trascon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0; +wire litedramcore_bankmachine5_req_valid; +wire litedramcore_bankmachine5_req_ready; +wire litedramcore_bankmachine5_req_we; +wire [20:0] litedramcore_bankmachine5_req_addr; +wire litedramcore_bankmachine5_req_lock; +reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine5_refresh_req; +reg litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg litedramcore_bankmachine5_cmd_valid = 1'd0; +reg litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine5_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; +reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine5_auto_precharge = 1'd0; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; +wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; +wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine5_cmd_buffer_sink_valid; +wire litedramcore_bankmachine5_cmd_buffer_sink_ready; +wire litedramcore_bankmachine5_cmd_buffer_sink_first; +wire litedramcore_bankmachine5_cmd_buffer_sink_last; +wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we; +wire [20:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine5_cmd_buffer_source_ready; +reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine5_row = 14'd0; +reg litedramcore_bankmachine5_row_opened = 1'd0; +wire litedramcore_bankmachine5_row_hit; +reg litedramcore_bankmachine5_row_open = 1'd0; +reg litedramcore_bankmachine5_row_close = 1'd0; +reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine5_twtpcon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; +wire litedramcore_bankmachine5_trccon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0; +wire litedramcore_bankmachine5_trascon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0; +wire litedramcore_bankmachine6_req_valid; +wire litedramcore_bankmachine6_req_ready; +wire litedramcore_bankmachine6_req_we; +wire [20:0] litedramcore_bankmachine6_req_addr; +wire litedramcore_bankmachine6_req_lock; +reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine6_refresh_req; +reg litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg litedramcore_bankmachine6_cmd_valid = 1'd0; +reg litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine6_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; +reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine6_auto_precharge = 1'd0; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; +wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; +wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine6_cmd_buffer_sink_valid; +wire litedramcore_bankmachine6_cmd_buffer_sink_ready; +wire litedramcore_bankmachine6_cmd_buffer_sink_first; +wire litedramcore_bankmachine6_cmd_buffer_sink_last; +wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we; +wire [20:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine6_cmd_buffer_source_ready; +reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine6_row = 14'd0; +reg litedramcore_bankmachine6_row_opened = 1'd0; +wire litedramcore_bankmachine6_row_hit; +reg litedramcore_bankmachine6_row_open = 1'd0; +reg litedramcore_bankmachine6_row_close = 1'd0; +reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine6_twtpcon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; +wire litedramcore_bankmachine6_trccon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0; +wire litedramcore_bankmachine6_trascon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0; +wire litedramcore_bankmachine7_req_valid; +wire litedramcore_bankmachine7_req_ready; +wire litedramcore_bankmachine7_req_we; +wire [20:0] litedramcore_bankmachine7_req_addr; +wire litedramcore_bankmachine7_req_lock; +reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine7_refresh_req; +reg litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg litedramcore_bankmachine7_cmd_valid = 1'd0; +reg litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine7_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; +reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine7_auto_precharge = 1'd0; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; +wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; +wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine7_cmd_buffer_sink_valid; +wire litedramcore_bankmachine7_cmd_buffer_sink_ready; +wire litedramcore_bankmachine7_cmd_buffer_sink_first; +wire litedramcore_bankmachine7_cmd_buffer_sink_last; +wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we; +wire [20:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine7_cmd_buffer_source_ready; +reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine7_row = 14'd0; +reg litedramcore_bankmachine7_row_opened = 1'd0; +wire litedramcore_bankmachine7_row_hit; +reg litedramcore_bankmachine7_row_open = 1'd0; +reg litedramcore_bankmachine7_row_close = 1'd0; +reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine7_twtpcon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; +wire litedramcore_bankmachine7_trccon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0; +wire litedramcore_bankmachine7_trascon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0; +wire litedramcore_ras_allowed; +wire litedramcore_cas_allowed; +reg litedramcore_choose_cmd_want_reads = 1'd0; +reg litedramcore_choose_cmd_want_writes = 1'd0; +reg litedramcore_choose_cmd_want_cmds = 1'd0; +reg litedramcore_choose_cmd_want_activates = 1'd0; +wire litedramcore_choose_cmd_cmd_valid; +reg litedramcore_choose_cmd_cmd_ready = 1'd0; +wire [13:0] litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; +reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; +wire litedramcore_choose_cmd_cmd_payload_is_cmd; +wire litedramcore_choose_cmd_cmd_payload_is_read; +wire litedramcore_choose_cmd_cmd_payload_is_write; +reg [7:0] litedramcore_choose_cmd_valids = 8'd0; +wire [7:0] litedramcore_choose_cmd_request; +reg [2:0] litedramcore_choose_cmd_grant = 3'd0; +wire litedramcore_choose_cmd_ce; +reg litedramcore_choose_req_want_reads = 1'd0; +reg litedramcore_choose_req_want_writes = 1'd0; +reg litedramcore_choose_req_want_cmds = 1'd0; +reg litedramcore_choose_req_want_activates = 1'd0; +wire litedramcore_choose_req_cmd_valid; +reg litedramcore_choose_req_cmd_ready = 1'd0; +wire [13:0] litedramcore_choose_req_cmd_payload_a; +wire [2:0] litedramcore_choose_req_cmd_payload_ba; +reg litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg litedramcore_choose_req_cmd_payload_we = 1'd0; +wire litedramcore_choose_req_cmd_payload_is_cmd; +wire litedramcore_choose_req_cmd_payload_is_read; +wire litedramcore_choose_req_cmd_payload_is_write; +reg [7:0] litedramcore_choose_req_valids = 8'd0; +wire [7:0] litedramcore_choose_req_request; +reg [2:0] litedramcore_choose_req_grant = 3'd0; +wire litedramcore_choose_req_ce; +reg [13:0] litedramcore_nop_a = 14'd0; +reg [2:0] litedramcore_nop_ba = 3'd0; +reg [1:0] litedramcore_steerer_sel0 = 2'd0; +reg [1:0] litedramcore_steerer_sel1 = 2'd0; +reg [1:0] litedramcore_steerer_sel2 = 2'd0; +reg [1:0] litedramcore_steerer_sel3 = 2'd0; +reg litedramcore_steerer0 = 1'd1; +reg litedramcore_steerer1 = 1'd1; +reg litedramcore_steerer2 = 1'd1; +reg litedramcore_steerer3 = 1'd1; +reg litedramcore_steerer4 = 1'd1; +reg litedramcore_steerer5 = 1'd1; +reg litedramcore_steerer6 = 1'd1; +reg litedramcore_steerer7 = 1'd1; +wire litedramcore_trrdcon_valid; +(* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd1; +reg litedramcore_trrdcon_count = 1'd0; +wire litedramcore_tfawcon_valid; +(* dont_touch = "true" *) reg litedramcore_tfawcon_ready = 1'd1; +wire [2:0] litedramcore_tfawcon_count; +reg [4:0] litedramcore_tfawcon_window = 5'd0; +wire litedramcore_tccdcon_valid; +(* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd1; +reg litedramcore_tccdcon_count = 1'd0; +wire litedramcore_twtrcon_valid; +(* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd1; +reg [2:0] litedramcore_twtrcon_count = 3'd0; +wire litedramcore_read_available; +wire litedramcore_write_available; +reg litedramcore_en0 = 1'd0; +wire litedramcore_max_time0; +reg [4:0] litedramcore_time0 = 5'd0; +reg litedramcore_en1 = 1'd0; +wire litedramcore_max_time1; +reg [3:0] litedramcore_time1 = 4'd0; +wire litedramcore_go_to_refresh; +reg init_done_storage = 1'd0; +reg init_done_re = 1'd0; +reg init_error_storage = 1'd0; +reg init_error_re = 1'd0; +wire [13:0] csr_port_adr; +wire csr_port_we; +wire [7:0] csr_port_dat_w; +wire [7:0] csr_port_dat_r; +wire user_port_cmd_valid; +wire user_port_cmd_ready; +wire user_port_cmd_payload_we; +wire [23:0] user_port_cmd_payload_addr; +wire user_port_wdata_valid; +wire user_port_wdata_ready; +wire [127:0] user_port_wdata_payload_data; +wire [15:0] user_port_wdata_payload_we; +wire user_port_rdata_valid; +wire user_port_rdata_ready; +wire [127:0] user_port_rdata_payload_data; +wire pll_fb0; +wire pll_fb1; +reg [1:0] refresher_state = 2'd0; +reg [1:0] refresher_next_state = 2'd0; +reg [3:0] bankmachine0_state = 4'd0; +reg [3:0] bankmachine0_next_state = 4'd0; +reg [3:0] bankmachine1_state = 4'd0; +reg [3:0] bankmachine1_next_state = 4'd0; +reg [3:0] bankmachine2_state = 4'd0; +reg [3:0] bankmachine2_next_state = 4'd0; +reg [3:0] bankmachine3_state = 4'd0; +reg [3:0] bankmachine3_next_state = 4'd0; +reg [3:0] bankmachine4_state = 4'd0; +reg [3:0] bankmachine4_next_state = 4'd0; +reg [3:0] bankmachine5_state = 4'd0; +reg [3:0] bankmachine5_next_state = 4'd0; +reg [3:0] bankmachine6_state = 4'd0; +reg [3:0] bankmachine6_next_state = 4'd0; +reg [3:0] bankmachine7_state = 4'd0; +reg [3:0] bankmachine7_next_state = 4'd0; +reg [3:0] multiplexer_state = 4'd0; +reg [3:0] multiplexer_next_state = 4'd0; +wire roundrobin0_request; +wire roundrobin0_grant; +wire roundrobin0_ce; +wire roundrobin1_request; +wire roundrobin1_grant; +wire roundrobin1_ce; +wire roundrobin2_request; +wire roundrobin2_grant; +wire roundrobin2_ce; +wire roundrobin3_request; +wire roundrobin3_grant; +wire roundrobin3_ce; +wire roundrobin4_request; +wire roundrobin4_grant; +wire roundrobin4_ce; +wire roundrobin5_request; +wire roundrobin5_grant; +wire roundrobin5_ce; +wire roundrobin6_request; +wire roundrobin6_grant; +wire roundrobin6_ce; +wire roundrobin7_request; +wire roundrobin7_grant; +wire roundrobin7_ce; +reg locked0 = 1'd0; +reg locked1 = 1'd0; +reg locked2 = 1'd0; +reg locked3 = 1'd0; +reg locked4 = 1'd0; +reg locked5 = 1'd0; +reg locked6 = 1'd0; +reg locked7 = 1'd0; +reg new_master_wdata_ready0 = 1'd0; +reg new_master_wdata_ready1 = 1'd0; +reg new_master_wdata_ready2 = 1'd0; +reg new_master_rdata_valid0 = 1'd0; +reg new_master_rdata_valid1 = 1'd0; +reg new_master_rdata_valid2 = 1'd0; +reg new_master_rdata_valid3 = 1'd0; +reg new_master_rdata_valid4 = 1'd0; +reg new_master_rdata_valid5 = 1'd0; +reg new_master_rdata_valid6 = 1'd0; +reg new_master_rdata_valid7 = 1'd0; +reg new_master_rdata_valid8 = 1'd0; +wire [13:0] interface0_bank_bus_adr; +wire interface0_bank_bus_we; +wire [7:0] interface0_bank_bus_dat_w; +reg [7:0] interface0_bank_bus_dat_r = 8'd0; +wire csrbank0_init_done0_re; +wire csrbank0_init_done0_r; +wire csrbank0_init_done0_we; +wire csrbank0_init_done0_w; +wire csrbank0_init_error0_re; +wire csrbank0_init_error0_r; +wire csrbank0_init_error0_we; +wire csrbank0_init_error0_w; +reg csrbank0_sel = 1'd0; +wire [13:0] interface1_bank_bus_adr; +wire interface1_bank_bus_we; +wire [7:0] interface1_bank_bus_dat_w; +reg [7:0] interface1_bank_bus_dat_r = 8'd0; +wire csrbank1_half_sys8x_taps0_re; +wire [4:0] csrbank1_half_sys8x_taps0_r; +wire csrbank1_half_sys8x_taps0_we; +wire [4:0] csrbank1_half_sys8x_taps0_w; +wire csrbank1_wlevel_en0_re; +wire csrbank1_wlevel_en0_r; +wire csrbank1_wlevel_en0_we; +wire csrbank1_wlevel_en0_w; +wire csrbank1_dly_sel0_re; +wire [1:0] csrbank1_dly_sel0_r; +wire csrbank1_dly_sel0_we; +wire [1:0] csrbank1_dly_sel0_w; +reg csrbank1_sel = 1'd0; +wire [13:0] interface2_bank_bus_adr; +wire interface2_bank_bus_we; +wire [7:0] interface2_bank_bus_dat_w; +reg [7:0] interface2_bank_bus_dat_r = 8'd0; +wire csrbank2_dfii_control0_re; +wire [3:0] csrbank2_dfii_control0_r; +wire csrbank2_dfii_control0_we; +wire [3:0] csrbank2_dfii_control0_w; +wire csrbank2_dfii_pi0_command0_re; +wire [5:0] csrbank2_dfii_pi0_command0_r; +wire csrbank2_dfii_pi0_command0_we; +wire [5:0] csrbank2_dfii_pi0_command0_w; +wire csrbank2_dfii_pi0_address1_re; +wire [5:0] csrbank2_dfii_pi0_address1_r; +wire csrbank2_dfii_pi0_address1_we; +wire [5:0] csrbank2_dfii_pi0_address1_w; +wire csrbank2_dfii_pi0_address0_re; +wire [7:0] csrbank2_dfii_pi0_address0_r; +wire csrbank2_dfii_pi0_address0_we; +wire [7:0] csrbank2_dfii_pi0_address0_w; +wire csrbank2_dfii_pi0_baddress0_re; +wire [2:0] csrbank2_dfii_pi0_baddress0_r; +wire csrbank2_dfii_pi0_baddress0_we; +wire [2:0] csrbank2_dfii_pi0_baddress0_w; +wire csrbank2_dfii_pi0_wrdata3_re; +wire [7:0] csrbank2_dfii_pi0_wrdata3_r; +wire csrbank2_dfii_pi0_wrdata3_we; +wire [7:0] csrbank2_dfii_pi0_wrdata3_w; +wire csrbank2_dfii_pi0_wrdata2_re; +wire [7:0] csrbank2_dfii_pi0_wrdata2_r; +wire csrbank2_dfii_pi0_wrdata2_we; +wire [7:0] csrbank2_dfii_pi0_wrdata2_w; +wire csrbank2_dfii_pi0_wrdata1_re; +wire [7:0] csrbank2_dfii_pi0_wrdata1_r; +wire csrbank2_dfii_pi0_wrdata1_we; +wire [7:0] csrbank2_dfii_pi0_wrdata1_w; +wire csrbank2_dfii_pi0_wrdata0_re; +wire [7:0] csrbank2_dfii_pi0_wrdata0_r; +wire csrbank2_dfii_pi0_wrdata0_we; +wire [7:0] csrbank2_dfii_pi0_wrdata0_w; +wire csrbank2_dfii_pi0_rddata3_re; +wire [7:0] csrbank2_dfii_pi0_rddata3_r; +wire csrbank2_dfii_pi0_rddata3_we; +wire [7:0] csrbank2_dfii_pi0_rddata3_w; +wire csrbank2_dfii_pi0_rddata2_re; +wire [7:0] csrbank2_dfii_pi0_rddata2_r; +wire csrbank2_dfii_pi0_rddata2_we; +wire [7:0] csrbank2_dfii_pi0_rddata2_w; +wire csrbank2_dfii_pi0_rddata1_re; +wire [7:0] csrbank2_dfii_pi0_rddata1_r; +wire csrbank2_dfii_pi0_rddata1_we; +wire [7:0] csrbank2_dfii_pi0_rddata1_w; +wire csrbank2_dfii_pi0_rddata0_re; +wire [7:0] csrbank2_dfii_pi0_rddata0_r; +wire csrbank2_dfii_pi0_rddata0_we; +wire [7:0] csrbank2_dfii_pi0_rddata0_w; +wire csrbank2_dfii_pi1_command0_re; +wire [5:0] csrbank2_dfii_pi1_command0_r; +wire csrbank2_dfii_pi1_command0_we; +wire [5:0] csrbank2_dfii_pi1_command0_w; +wire csrbank2_dfii_pi1_address1_re; +wire [5:0] csrbank2_dfii_pi1_address1_r; +wire csrbank2_dfii_pi1_address1_we; +wire [5:0] csrbank2_dfii_pi1_address1_w; +wire csrbank2_dfii_pi1_address0_re; +wire [7:0] csrbank2_dfii_pi1_address0_r; +wire csrbank2_dfii_pi1_address0_we; +wire [7:0] csrbank2_dfii_pi1_address0_w; +wire csrbank2_dfii_pi1_baddress0_re; +wire [2:0] csrbank2_dfii_pi1_baddress0_r; +wire csrbank2_dfii_pi1_baddress0_we; +wire [2:0] csrbank2_dfii_pi1_baddress0_w; +wire csrbank2_dfii_pi1_wrdata3_re; +wire [7:0] csrbank2_dfii_pi1_wrdata3_r; +wire csrbank2_dfii_pi1_wrdata3_we; +wire [7:0] csrbank2_dfii_pi1_wrdata3_w; +wire csrbank2_dfii_pi1_wrdata2_re; +wire [7:0] csrbank2_dfii_pi1_wrdata2_r; +wire csrbank2_dfii_pi1_wrdata2_we; +wire [7:0] csrbank2_dfii_pi1_wrdata2_w; +wire csrbank2_dfii_pi1_wrdata1_re; +wire [7:0] csrbank2_dfii_pi1_wrdata1_r; +wire csrbank2_dfii_pi1_wrdata1_we; +wire [7:0] csrbank2_dfii_pi1_wrdata1_w; +wire csrbank2_dfii_pi1_wrdata0_re; +wire [7:0] csrbank2_dfii_pi1_wrdata0_r; +wire csrbank2_dfii_pi1_wrdata0_we; +wire [7:0] csrbank2_dfii_pi1_wrdata0_w; +wire csrbank2_dfii_pi1_rddata3_re; +wire [7:0] csrbank2_dfii_pi1_rddata3_r; +wire csrbank2_dfii_pi1_rddata3_we; +wire [7:0] csrbank2_dfii_pi1_rddata3_w; +wire csrbank2_dfii_pi1_rddata2_re; +wire [7:0] csrbank2_dfii_pi1_rddata2_r; +wire csrbank2_dfii_pi1_rddata2_we; +wire [7:0] csrbank2_dfii_pi1_rddata2_w; +wire csrbank2_dfii_pi1_rddata1_re; +wire [7:0] csrbank2_dfii_pi1_rddata1_r; +wire csrbank2_dfii_pi1_rddata1_we; +wire [7:0] csrbank2_dfii_pi1_rddata1_w; +wire csrbank2_dfii_pi1_rddata0_re; +wire [7:0] csrbank2_dfii_pi1_rddata0_r; +wire csrbank2_dfii_pi1_rddata0_we; +wire [7:0] csrbank2_dfii_pi1_rddata0_w; +wire csrbank2_dfii_pi2_command0_re; +wire [5:0] csrbank2_dfii_pi2_command0_r; +wire csrbank2_dfii_pi2_command0_we; +wire [5:0] csrbank2_dfii_pi2_command0_w; +wire csrbank2_dfii_pi2_address1_re; +wire [5:0] csrbank2_dfii_pi2_address1_r; +wire csrbank2_dfii_pi2_address1_we; +wire [5:0] csrbank2_dfii_pi2_address1_w; +wire csrbank2_dfii_pi2_address0_re; +wire [7:0] csrbank2_dfii_pi2_address0_r; +wire csrbank2_dfii_pi2_address0_we; +wire [7:0] csrbank2_dfii_pi2_address0_w; +wire csrbank2_dfii_pi2_baddress0_re; +wire [2:0] csrbank2_dfii_pi2_baddress0_r; +wire csrbank2_dfii_pi2_baddress0_we; +wire [2:0] csrbank2_dfii_pi2_baddress0_w; +wire csrbank2_dfii_pi2_wrdata3_re; +wire [7:0] csrbank2_dfii_pi2_wrdata3_r; +wire csrbank2_dfii_pi2_wrdata3_we; +wire [7:0] csrbank2_dfii_pi2_wrdata3_w; +wire csrbank2_dfii_pi2_wrdata2_re; +wire [7:0] csrbank2_dfii_pi2_wrdata2_r; +wire csrbank2_dfii_pi2_wrdata2_we; +wire [7:0] csrbank2_dfii_pi2_wrdata2_w; +wire csrbank2_dfii_pi2_wrdata1_re; +wire [7:0] csrbank2_dfii_pi2_wrdata1_r; +wire csrbank2_dfii_pi2_wrdata1_we; +wire [7:0] csrbank2_dfii_pi2_wrdata1_w; +wire csrbank2_dfii_pi2_wrdata0_re; +wire [7:0] csrbank2_dfii_pi2_wrdata0_r; +wire csrbank2_dfii_pi2_wrdata0_we; +wire [7:0] csrbank2_dfii_pi2_wrdata0_w; +wire csrbank2_dfii_pi2_rddata3_re; +wire [7:0] csrbank2_dfii_pi2_rddata3_r; +wire csrbank2_dfii_pi2_rddata3_we; +wire [7:0] csrbank2_dfii_pi2_rddata3_w; +wire csrbank2_dfii_pi2_rddata2_re; +wire [7:0] csrbank2_dfii_pi2_rddata2_r; +wire csrbank2_dfii_pi2_rddata2_we; +wire [7:0] csrbank2_dfii_pi2_rddata2_w; +wire csrbank2_dfii_pi2_rddata1_re; +wire [7:0] csrbank2_dfii_pi2_rddata1_r; +wire csrbank2_dfii_pi2_rddata1_we; +wire [7:0] csrbank2_dfii_pi2_rddata1_w; +wire csrbank2_dfii_pi2_rddata0_re; +wire [7:0] csrbank2_dfii_pi2_rddata0_r; +wire csrbank2_dfii_pi2_rddata0_we; +wire [7:0] csrbank2_dfii_pi2_rddata0_w; +wire csrbank2_dfii_pi3_command0_re; +wire [5:0] csrbank2_dfii_pi3_command0_r; +wire csrbank2_dfii_pi3_command0_we; +wire [5:0] csrbank2_dfii_pi3_command0_w; +wire csrbank2_dfii_pi3_address1_re; +wire [5:0] csrbank2_dfii_pi3_address1_r; +wire csrbank2_dfii_pi3_address1_we; +wire [5:0] csrbank2_dfii_pi3_address1_w; +wire csrbank2_dfii_pi3_address0_re; +wire [7:0] csrbank2_dfii_pi3_address0_r; +wire csrbank2_dfii_pi3_address0_we; +wire [7:0] csrbank2_dfii_pi3_address0_w; +wire csrbank2_dfii_pi3_baddress0_re; +wire [2:0] csrbank2_dfii_pi3_baddress0_r; +wire csrbank2_dfii_pi3_baddress0_we; +wire [2:0] csrbank2_dfii_pi3_baddress0_w; +wire csrbank2_dfii_pi3_wrdata3_re; +wire [7:0] csrbank2_dfii_pi3_wrdata3_r; +wire csrbank2_dfii_pi3_wrdata3_we; +wire [7:0] csrbank2_dfii_pi3_wrdata3_w; +wire csrbank2_dfii_pi3_wrdata2_re; +wire [7:0] csrbank2_dfii_pi3_wrdata2_r; +wire csrbank2_dfii_pi3_wrdata2_we; +wire [7:0] csrbank2_dfii_pi3_wrdata2_w; +wire csrbank2_dfii_pi3_wrdata1_re; +wire [7:0] csrbank2_dfii_pi3_wrdata1_r; +wire csrbank2_dfii_pi3_wrdata1_we; +wire [7:0] csrbank2_dfii_pi3_wrdata1_w; +wire csrbank2_dfii_pi3_wrdata0_re; +wire [7:0] csrbank2_dfii_pi3_wrdata0_r; +wire csrbank2_dfii_pi3_wrdata0_we; +wire [7:0] csrbank2_dfii_pi3_wrdata0_w; +wire csrbank2_dfii_pi3_rddata3_re; +wire [7:0] csrbank2_dfii_pi3_rddata3_r; +wire csrbank2_dfii_pi3_rddata3_we; +wire [7:0] csrbank2_dfii_pi3_rddata3_w; +wire csrbank2_dfii_pi3_rddata2_re; +wire [7:0] csrbank2_dfii_pi3_rddata2_r; +wire csrbank2_dfii_pi3_rddata2_we; +wire [7:0] csrbank2_dfii_pi3_rddata2_w; +wire csrbank2_dfii_pi3_rddata1_re; +wire [7:0] csrbank2_dfii_pi3_rddata1_r; +wire csrbank2_dfii_pi3_rddata1_we; +wire [7:0] csrbank2_dfii_pi3_rddata1_w; +wire csrbank2_dfii_pi3_rddata0_re; +wire [7:0] csrbank2_dfii_pi3_rddata0_r; +wire csrbank2_dfii_pi3_rddata0_we; +wire [7:0] csrbank2_dfii_pi3_rddata0_w; +reg csrbank2_sel = 1'd0; +wire [13:0] adr; +wire we; +wire [7:0] dat_w; +wire [7:0] dat_r; +reg rhs_array_muxed0 = 1'd0; +reg [13:0] rhs_array_muxed1 = 14'd0; +reg [2:0] rhs_array_muxed2 = 3'd0; +reg rhs_array_muxed3 = 1'd0; +reg rhs_array_muxed4 = 1'd0; +reg rhs_array_muxed5 = 1'd0; +reg t_array_muxed0 = 1'd0; +reg t_array_muxed1 = 1'd0; +reg t_array_muxed2 = 1'd0; +reg rhs_array_muxed6 = 1'd0; +reg [13:0] rhs_array_muxed7 = 14'd0; +reg [2:0] rhs_array_muxed8 = 3'd0; +reg rhs_array_muxed9 = 1'd0; +reg rhs_array_muxed10 = 1'd0; +reg rhs_array_muxed11 = 1'd0; +reg t_array_muxed3 = 1'd0; +reg t_array_muxed4 = 1'd0; +reg t_array_muxed5 = 1'd0; +reg [20:0] rhs_array_muxed12 = 21'd0; +reg rhs_array_muxed13 = 1'd0; +reg rhs_array_muxed14 = 1'd0; +reg [20:0] rhs_array_muxed15 = 21'd0; +reg rhs_array_muxed16 = 1'd0; +reg rhs_array_muxed17 = 1'd0; +reg [20:0] rhs_array_muxed18 = 21'd0; +reg rhs_array_muxed19 = 1'd0; +reg rhs_array_muxed20 = 1'd0; +reg [20:0] rhs_array_muxed21 = 21'd0; +reg rhs_array_muxed22 = 1'd0; +reg rhs_array_muxed23 = 1'd0; +reg [20:0] rhs_array_muxed24 = 21'd0; +reg rhs_array_muxed25 = 1'd0; +reg rhs_array_muxed26 = 1'd0; +reg [20:0] rhs_array_muxed27 = 21'd0; +reg rhs_array_muxed28 = 1'd0; +reg rhs_array_muxed29 = 1'd0; +reg [20:0] rhs_array_muxed30 = 21'd0; +reg rhs_array_muxed31 = 1'd0; +reg rhs_array_muxed32 = 1'd0; +reg [20:0] rhs_array_muxed33 = 21'd0; +reg rhs_array_muxed34 = 1'd0; +reg rhs_array_muxed35 = 1'd0; +reg [2:0] array_muxed0 = 3'd0; +reg [13:0] array_muxed1 = 14'd0; +reg array_muxed2 = 1'd0; +reg array_muxed3 = 1'd0; +reg array_muxed4 = 1'd0; +reg array_muxed5 = 1'd0; +reg array_muxed6 = 1'd0; +reg [2:0] array_muxed7 = 3'd0; +reg [13:0] array_muxed8 = 14'd0; +reg array_muxed9 = 1'd0; +reg array_muxed10 = 1'd0; +reg array_muxed11 = 1'd0; +reg array_muxed12 = 1'd0; +reg array_muxed13 = 1'd0; +reg [2:0] array_muxed14 = 3'd0; +reg [13:0] array_muxed15 = 14'd0; +reg array_muxed16 = 1'd0; +reg array_muxed17 = 1'd0; +reg array_muxed18 = 1'd0; +reg array_muxed19 = 1'd0; +reg array_muxed20 = 1'd0; +reg [2:0] array_muxed21 = 3'd0; +reg [13:0] array_muxed22 = 14'd0; +reg array_muxed23 = 1'd0; +reg array_muxed24 = 1'd0; +reg array_muxed25 = 1'd0; +reg array_muxed26 = 1'd0; +reg array_muxed27 = 1'd0; +wire xilinxasyncresetsynchronizerimpl0; +wire xilinxasyncresetsynchronizerimpl0_rst_meta; +wire xilinxasyncresetsynchronizerimpl1; +wire xilinxasyncresetsynchronizerimpl1_rst_meta; +wire xilinxasyncresetsynchronizerimpl1_expr; +wire xilinxasyncresetsynchronizerimpl2; +wire xilinxasyncresetsynchronizerimpl2_rst_meta; +wire xilinxasyncresetsynchronizerimpl2_expr; +wire xilinxasyncresetsynchronizerimpl3; +wire xilinxasyncresetsynchronizerimpl3_rst_meta; // synthesis translate_off reg dummy_s; initial dummy_s <= 1'd0; // synthesis translate_on -assign soc_litedramcore_cpu_reset = soc_litedramcore_soccontroller_reset; -assign init_done = soc_init_done_storage; -assign init_error = soc_init_error_storage; +assign init_done = init_done_storage; +assign init_error = init_error_storage; +assign csr_port_adr = csr_port0_adr; +assign csr_port_we = csr_port0_we; +assign csr_port_dat_w = csr_port0_dat_w; +assign csr_port0_dat_r = csr_port_dat_r; assign user_clk = sys_clk; assign user_rst = sys_rst; -assign soc_cmd_valid = user_port_native_0_cmd_valid; -assign user_port_native_0_cmd_ready = soc_cmd_ready; -assign soc_cmd_payload_we = user_port_native_0_cmd_we; -assign soc_cmd_payload_addr = user_port_native_0_cmd_addr; -assign soc_wdata_valid = user_port_native_0_wdata_valid; -assign user_port_native_0_wdata_ready = soc_wdata_ready; -assign soc_wdata_payload_we = user_port_native_0_wdata_we; -assign soc_wdata_payload_data = user_port_native_0_wdata_data; -assign user_port_native_0_rdata_valid = soc_rdata_valid; -assign soc_rdata_ready = user_port_native_0_rdata_ready; -assign user_port_native_0_rdata_data = soc_rdata_payload_data; -assign soc_litedramcore_soccontroller_bus_error = vns_error; +assign user_port_cmd_valid = user_port_native_0_cmd_valid; +assign user_port_native_0_cmd_ready = user_port_cmd_ready; +assign user_port_cmd_payload_we = user_port_native_0_cmd_we; +assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr; +assign user_port_wdata_valid = user_port_native_0_wdata_valid; +assign user_port_native_0_wdata_ready = user_port_wdata_ready; +assign user_port_wdata_payload_we = user_port_native_0_wdata_we; +assign user_port_wdata_payload_data = user_port_native_0_wdata_data; +assign user_port_native_0_rdata_valid = user_port_rdata_valid; +assign user_port_rdata_ready = user_port_native_0_rdata_ready; +assign user_port_native_0_rdata_data = user_port_rdata_payload_data; +assign sys_pll_reset = rst; +assign pll_locked = sys_pll_locked; +assign iodelay_pll_reset = rst; +assign s7pll0_clkin = clk; +assign sys_clk = s7pll0_clkout_buf0; +assign sys4x_clk = s7pll0_clkout_buf1; +assign sys4x_dqs_clk = s7pll0_clkout_buf2; +assign s7pll1_clkin = clk; +assign iodelay_clk = s7pll1_clkout_buf; +assign a7ddrphy_bitslip0_i = a7ddrphy_dq_i_data0; // synthesis translate_off reg dummy_d; // synthesis translate_on always @(*) begin - soc_litedramcore_cpu_interrupt <= 32'd0; - soc_litedramcore_cpu_interrupt[1] <= soc_litedramcore_timer_irq; - soc_litedramcore_cpu_interrupt[0] <= soc_litedramcore_uart_irq; + a7ddrphy_dfi_p0_rddata <= 32'd0; + a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip0_o[0]; + a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip0_o[1]; + a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip1_o[0]; + a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip1_o[1]; + a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip2_o[0]; + a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip2_o[1]; + a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip3_o[0]; + a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip3_o[1]; + a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip4_o[0]; + a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip4_o[1]; + a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip5_o[0]; + a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip5_o[1]; + a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip6_o[0]; + a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip6_o[1]; + a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip7_o[0]; + a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip7_o[1]; + a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip8_o[0]; + a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip8_o[1]; + a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip9_o[0]; + a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip9_o[1]; + a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip10_o[0]; + a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip10_o[1]; + a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip11_o[0]; + a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip11_o[1]; + a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip12_o[0]; + a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip12_o[1]; + a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip13_o[0]; + a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip13_o[1]; + a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip14_o[0]; + a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip14_o[1]; + a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip15_o[0]; + a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip15_o[1]; // synthesis translate_off dummy_d = dummy_s; // synthesis translate_on end -assign soc_litedramcore_soccontroller_reset = soc_litedramcore_soccontroller_reset_re; -assign soc_litedramcore_soccontroller_bus_errors_status = soc_litedramcore_soccontroller_bus_errors; -assign soc_litedramcore_litedramcore_adr = soc_litedramcore_litedramcore_ram_bus_adr[12:0]; -assign soc_litedramcore_litedramcore_ram_bus_dat_r = soc_litedramcore_litedramcore_dat_r; // synthesis translate_off reg dummy_d_1; // synthesis translate_on always @(*) begin - soc_litedramcore_ram_we <= 4'd0; - soc_litedramcore_ram_we[0] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[0]); - soc_litedramcore_ram_we[1] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[1]); - soc_litedramcore_ram_we[2] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[2]); - soc_litedramcore_ram_we[3] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[3]); + a7ddrphy_dfi_p1_rddata <= 32'd0; + a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip0_o[2]; + a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip0_o[3]; + a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip1_o[2]; + a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip1_o[3]; + a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip2_o[2]; + a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip2_o[3]; + a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip3_o[2]; + a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip3_o[3]; + a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip4_o[2]; + a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip4_o[3]; + a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip5_o[2]; + a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip5_o[3]; + a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip6_o[2]; + a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip6_o[3]; + a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip7_o[2]; + a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip7_o[3]; + a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip8_o[2]; + a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip8_o[3]; + a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip9_o[2]; + a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip9_o[3]; + a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip10_o[2]; + a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip10_o[3]; + a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip11_o[2]; + a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip11_o[3]; + a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip12_o[2]; + a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip12_o[3]; + a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip13_o[2]; + a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip13_o[3]; + a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip14_o[2]; + a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip14_o[3]; + a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip15_o[2]; + a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip15_o[3]; // synthesis translate_off dummy_d_1 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_ram_adr = soc_litedramcore_ram_bus_ram_bus_adr[9:0]; -assign soc_litedramcore_ram_bus_ram_bus_dat_r = soc_litedramcore_ram_dat_r; -assign soc_litedramcore_ram_dat_w = soc_litedramcore_ram_bus_ram_bus_dat_w; -assign soc_litedramcore_uart_uart_sink_valid = soc_litedramcore_source_valid; -assign soc_litedramcore_source_ready = soc_litedramcore_uart_uart_sink_ready; -assign soc_litedramcore_uart_uart_sink_first = soc_litedramcore_source_first; -assign soc_litedramcore_uart_uart_sink_last = soc_litedramcore_source_last; -assign soc_litedramcore_uart_uart_sink_payload_data = soc_litedramcore_source_payload_data; -assign soc_litedramcore_sink_valid = soc_litedramcore_uart_uart_source_valid; -assign soc_litedramcore_uart_uart_source_ready = soc_litedramcore_sink_ready; -assign soc_litedramcore_sink_first = soc_litedramcore_uart_uart_source_first; -assign soc_litedramcore_sink_last = soc_litedramcore_uart_uart_source_last; -assign soc_litedramcore_sink_payload_data = soc_litedramcore_uart_uart_source_payload_data; -assign soc_litedramcore_uart_tx_fifo_sink_valid = soc_litedramcore_uart_rxtx_re; -assign soc_litedramcore_uart_tx_fifo_sink_payload_data = soc_litedramcore_uart_rxtx_r; -assign soc_litedramcore_uart_txfull_status = (~soc_litedramcore_uart_tx_fifo_sink_ready); -assign soc_litedramcore_uart_uart_source_valid = soc_litedramcore_uart_tx_fifo_source_valid; -assign soc_litedramcore_uart_tx_fifo_source_ready = soc_litedramcore_uart_uart_source_ready; -assign soc_litedramcore_uart_uart_source_first = soc_litedramcore_uart_tx_fifo_source_first; -assign soc_litedramcore_uart_uart_source_last = soc_litedramcore_uart_tx_fifo_source_last; -assign soc_litedramcore_uart_uart_source_payload_data = soc_litedramcore_uart_tx_fifo_source_payload_data; -assign soc_litedramcore_uart_tx_trigger = (~soc_litedramcore_uart_tx_fifo_sink_ready); -assign soc_litedramcore_uart_rx_fifo_sink_valid = soc_litedramcore_uart_uart_sink_valid; -assign soc_litedramcore_uart_uart_sink_ready = soc_litedramcore_uart_rx_fifo_sink_ready; -assign soc_litedramcore_uart_rx_fifo_sink_first = soc_litedramcore_uart_uart_sink_first; -assign soc_litedramcore_uart_rx_fifo_sink_last = soc_litedramcore_uart_uart_sink_last; -assign soc_litedramcore_uart_rx_fifo_sink_payload_data = soc_litedramcore_uart_uart_sink_payload_data; -assign soc_litedramcore_uart_rxempty_status = (~soc_litedramcore_uart_rx_fifo_source_valid); -assign soc_litedramcore_uart_rxtx_w = soc_litedramcore_uart_rx_fifo_source_payload_data; -assign soc_litedramcore_uart_rx_fifo_source_ready = (soc_litedramcore_uart_rx_clear | (1'd0 & soc_litedramcore_uart_rxtx_we)); -assign soc_litedramcore_uart_rx_trigger = (~soc_litedramcore_uart_rx_fifo_source_valid); // synthesis translate_off reg dummy_d_2; // synthesis translate_on always @(*) begin - soc_litedramcore_uart_eventmanager_status_w <= 2'd0; - soc_litedramcore_uart_eventmanager_status_w[0] <= soc_litedramcore_uart_tx_status; - soc_litedramcore_uart_eventmanager_status_w[1] <= soc_litedramcore_uart_rx_status; + a7ddrphy_dfi_p2_rddata <= 32'd0; + a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip0_o[4]; + a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip0_o[5]; + a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip1_o[4]; + a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip1_o[5]; + a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip2_o[4]; + a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip2_o[5]; + a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip3_o[4]; + a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip3_o[5]; + a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip4_o[4]; + a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip4_o[5]; + a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip5_o[4]; + a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip5_o[5]; + a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip6_o[4]; + a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip6_o[5]; + a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip7_o[4]; + a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip7_o[5]; + a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip8_o[4]; + a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip8_o[5]; + a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip9_o[4]; + a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip9_o[5]; + a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip10_o[4]; + a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip10_o[5]; + a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip11_o[4]; + a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip11_o[5]; + a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip12_o[4]; + a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip12_o[5]; + a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip13_o[4]; + a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip13_o[5]; + a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip14_o[4]; + a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip14_o[5]; + a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip15_o[4]; + a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip15_o[5]; // synthesis translate_off dummy_d_2 = dummy_s; // synthesis translate_on @@ -2562,1302 +2044,1144 @@ end reg dummy_d_3; // synthesis translate_on always @(*) begin - soc_litedramcore_uart_tx_clear <= 1'd0; - if ((soc_litedramcore_uart_eventmanager_pending_re & soc_litedramcore_uart_eventmanager_pending_r[0])) begin - soc_litedramcore_uart_tx_clear <= 1'd1; - end + a7ddrphy_dfi_p3_rddata <= 32'd0; + a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip0_o[6]; + a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip0_o[7]; + a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip1_o[6]; + a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip1_o[7]; + a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip2_o[6]; + a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip2_o[7]; + a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip3_o[6]; + a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip3_o[7]; + a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip4_o[6]; + a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip4_o[7]; + a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip5_o[6]; + a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip5_o[7]; + a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip6_o[6]; + a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip6_o[7]; + a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip7_o[6]; + a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip7_o[7]; + a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip8_o[6]; + a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip8_o[7]; + a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip9_o[6]; + a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip9_o[7]; + a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip10_o[6]; + a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip10_o[7]; + a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip11_o[6]; + a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip11_o[7]; + a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip12_o[6]; + a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip12_o[7]; + a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip13_o[6]; + a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip13_o[7]; + a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip14_o[6]; + a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip14_o[7]; + a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip15_o[6]; + a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip15_o[7]; // synthesis translate_off dummy_d_3 = dummy_s; // synthesis translate_on end +assign a7ddrphy_bitslip1_i = a7ddrphy_dq_i_data1; +assign a7ddrphy_bitslip2_i = a7ddrphy_dq_i_data2; +assign a7ddrphy_bitslip3_i = a7ddrphy_dq_i_data3; +assign a7ddrphy_bitslip4_i = a7ddrphy_dq_i_data4; +assign a7ddrphy_bitslip5_i = a7ddrphy_dq_i_data5; +assign a7ddrphy_bitslip6_i = a7ddrphy_dq_i_data6; +assign a7ddrphy_bitslip7_i = a7ddrphy_dq_i_data7; +assign a7ddrphy_bitslip8_i = a7ddrphy_dq_i_data8; +assign a7ddrphy_bitslip9_i = a7ddrphy_dq_i_data9; +assign a7ddrphy_bitslip10_i = a7ddrphy_dq_i_data10; +assign a7ddrphy_bitslip11_i = a7ddrphy_dq_i_data11; +assign a7ddrphy_bitslip12_i = a7ddrphy_dq_i_data12; +assign a7ddrphy_bitslip13_i = a7ddrphy_dq_i_data13; +assign a7ddrphy_bitslip14_i = a7ddrphy_dq_i_data14; +assign a7ddrphy_bitslip15_i = a7ddrphy_dq_i_data15; +assign a7ddrphy_rddata_en = {a7ddrphy_rddata_en_last, a7ddrphy_dfi_p2_rddata_en}; +assign a7ddrphy_wrdata_en = {a7ddrphy_wrdata_en_last, a7ddrphy_dfi_p3_wrdata_en}; +assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en[2]; // synthesis translate_off reg dummy_d_4; // synthesis translate_on always @(*) begin - soc_litedramcore_uart_eventmanager_pending_w <= 2'd0; - soc_litedramcore_uart_eventmanager_pending_w[0] <= soc_litedramcore_uart_tx_pending; - soc_litedramcore_uart_eventmanager_pending_w[1] <= soc_litedramcore_uart_rx_pending; -// synthesis translate_off - dummy_d_4 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_5; -// synthesis translate_on -always @(*) begin - soc_litedramcore_uart_rx_clear <= 1'd0; - if ((soc_litedramcore_uart_eventmanager_pending_re & soc_litedramcore_uart_eventmanager_pending_r[1])) begin - soc_litedramcore_uart_rx_clear <= 1'd1; - end -// synthesis translate_off - dummy_d_5 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_uart_irq = ((soc_litedramcore_uart_eventmanager_pending_w[0] & soc_litedramcore_uart_eventmanager_storage[0]) | (soc_litedramcore_uart_eventmanager_pending_w[1] & soc_litedramcore_uart_eventmanager_storage[1])); -assign soc_litedramcore_uart_tx_status = soc_litedramcore_uart_tx_trigger; -assign soc_litedramcore_uart_rx_status = soc_litedramcore_uart_rx_trigger; -assign soc_litedramcore_uart_tx_fifo_syncfifo_din = {soc_litedramcore_uart_tx_fifo_fifo_in_last, soc_litedramcore_uart_tx_fifo_fifo_in_first, soc_litedramcore_uart_tx_fifo_fifo_in_payload_data}; -assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout; -assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout; -assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout; -assign soc_litedramcore_uart_tx_fifo_sink_ready = soc_litedramcore_uart_tx_fifo_syncfifo_writable; -assign soc_litedramcore_uart_tx_fifo_syncfifo_we = soc_litedramcore_uart_tx_fifo_sink_valid; -assign soc_litedramcore_uart_tx_fifo_fifo_in_first = soc_litedramcore_uart_tx_fifo_sink_first; -assign soc_litedramcore_uart_tx_fifo_fifo_in_last = soc_litedramcore_uart_tx_fifo_sink_last; -assign soc_litedramcore_uart_tx_fifo_fifo_in_payload_data = soc_litedramcore_uart_tx_fifo_sink_payload_data; -assign soc_litedramcore_uart_tx_fifo_source_valid = soc_litedramcore_uart_tx_fifo_readable; -assign soc_litedramcore_uart_tx_fifo_source_first = soc_litedramcore_uart_tx_fifo_fifo_out_first; -assign soc_litedramcore_uart_tx_fifo_source_last = soc_litedramcore_uart_tx_fifo_fifo_out_last; -assign soc_litedramcore_uart_tx_fifo_source_payload_data = soc_litedramcore_uart_tx_fifo_fifo_out_payload_data; -assign soc_litedramcore_uart_tx_fifo_re = soc_litedramcore_uart_tx_fifo_source_ready; -assign soc_litedramcore_uart_tx_fifo_syncfifo_re = (soc_litedramcore_uart_tx_fifo_syncfifo_readable & ((~soc_litedramcore_uart_tx_fifo_readable) | soc_litedramcore_uart_tx_fifo_re)); -assign soc_litedramcore_uart_tx_fifo_level1 = (soc_litedramcore_uart_tx_fifo_level0 + soc_litedramcore_uart_tx_fifo_readable); - -// synthesis translate_off -reg dummy_d_6; -// synthesis translate_on -always @(*) begin - soc_litedramcore_uart_tx_fifo_wrport_adr <= 4'd0; - if (soc_litedramcore_uart_tx_fifo_replace) begin - soc_litedramcore_uart_tx_fifo_wrport_adr <= (soc_litedramcore_uart_tx_fifo_produce - 1'd1); - end else begin - soc_litedramcore_uart_tx_fifo_wrport_adr <= soc_litedramcore_uart_tx_fifo_produce; - end -// synthesis translate_off - dummy_d_6 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_uart_tx_fifo_wrport_dat_w = soc_litedramcore_uart_tx_fifo_syncfifo_din; -assign soc_litedramcore_uart_tx_fifo_wrport_we = (soc_litedramcore_uart_tx_fifo_syncfifo_we & (soc_litedramcore_uart_tx_fifo_syncfifo_writable | soc_litedramcore_uart_tx_fifo_replace)); -assign soc_litedramcore_uart_tx_fifo_do_read = (soc_litedramcore_uart_tx_fifo_syncfifo_readable & soc_litedramcore_uart_tx_fifo_syncfifo_re); -assign soc_litedramcore_uart_tx_fifo_rdport_adr = soc_litedramcore_uart_tx_fifo_consume; -assign soc_litedramcore_uart_tx_fifo_syncfifo_dout = soc_litedramcore_uart_tx_fifo_rdport_dat_r; -assign soc_litedramcore_uart_tx_fifo_rdport_re = soc_litedramcore_uart_tx_fifo_do_read; -assign soc_litedramcore_uart_tx_fifo_syncfifo_writable = (soc_litedramcore_uart_tx_fifo_level0 != 5'd16); -assign soc_litedramcore_uart_tx_fifo_syncfifo_readable = (soc_litedramcore_uart_tx_fifo_level0 != 1'd0); -assign soc_litedramcore_uart_rx_fifo_syncfifo_din = {soc_litedramcore_uart_rx_fifo_fifo_in_last, soc_litedramcore_uart_rx_fifo_fifo_in_first, soc_litedramcore_uart_rx_fifo_fifo_in_payload_data}; -assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout; -assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout; -assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout; -assign soc_litedramcore_uart_rx_fifo_sink_ready = soc_litedramcore_uart_rx_fifo_syncfifo_writable; -assign soc_litedramcore_uart_rx_fifo_syncfifo_we = soc_litedramcore_uart_rx_fifo_sink_valid; -assign soc_litedramcore_uart_rx_fifo_fifo_in_first = soc_litedramcore_uart_rx_fifo_sink_first; -assign soc_litedramcore_uart_rx_fifo_fifo_in_last = soc_litedramcore_uart_rx_fifo_sink_last; -assign soc_litedramcore_uart_rx_fifo_fifo_in_payload_data = soc_litedramcore_uart_rx_fifo_sink_payload_data; -assign soc_litedramcore_uart_rx_fifo_source_valid = soc_litedramcore_uart_rx_fifo_readable; -assign soc_litedramcore_uart_rx_fifo_source_first = soc_litedramcore_uart_rx_fifo_fifo_out_first; -assign soc_litedramcore_uart_rx_fifo_source_last = soc_litedramcore_uart_rx_fifo_fifo_out_last; -assign soc_litedramcore_uart_rx_fifo_source_payload_data = soc_litedramcore_uart_rx_fifo_fifo_out_payload_data; -assign soc_litedramcore_uart_rx_fifo_re = soc_litedramcore_uart_rx_fifo_source_ready; -assign soc_litedramcore_uart_rx_fifo_syncfifo_re = (soc_litedramcore_uart_rx_fifo_syncfifo_readable & ((~soc_litedramcore_uart_rx_fifo_readable) | soc_litedramcore_uart_rx_fifo_re)); -assign soc_litedramcore_uart_rx_fifo_level1 = (soc_litedramcore_uart_rx_fifo_level0 + soc_litedramcore_uart_rx_fifo_readable); - -// synthesis translate_off -reg dummy_d_7; -// synthesis translate_on -always @(*) begin - soc_litedramcore_uart_rx_fifo_wrport_adr <= 4'd0; - if (soc_litedramcore_uart_rx_fifo_replace) begin - soc_litedramcore_uart_rx_fifo_wrport_adr <= (soc_litedramcore_uart_rx_fifo_produce - 1'd1); - end else begin - soc_litedramcore_uart_rx_fifo_wrport_adr <= soc_litedramcore_uart_rx_fifo_produce; - end -// synthesis translate_off - dummy_d_7 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_uart_rx_fifo_wrport_dat_w = soc_litedramcore_uart_rx_fifo_syncfifo_din; -assign soc_litedramcore_uart_rx_fifo_wrport_we = (soc_litedramcore_uart_rx_fifo_syncfifo_we & (soc_litedramcore_uart_rx_fifo_syncfifo_writable | soc_litedramcore_uart_rx_fifo_replace)); -assign soc_litedramcore_uart_rx_fifo_do_read = (soc_litedramcore_uart_rx_fifo_syncfifo_readable & soc_litedramcore_uart_rx_fifo_syncfifo_re); -assign soc_litedramcore_uart_rx_fifo_rdport_adr = soc_litedramcore_uart_rx_fifo_consume; -assign soc_litedramcore_uart_rx_fifo_syncfifo_dout = soc_litedramcore_uart_rx_fifo_rdport_dat_r; -assign soc_litedramcore_uart_rx_fifo_rdport_re = soc_litedramcore_uart_rx_fifo_do_read; -assign soc_litedramcore_uart_rx_fifo_syncfifo_writable = (soc_litedramcore_uart_rx_fifo_level0 != 5'd16); -assign soc_litedramcore_uart_rx_fifo_syncfifo_readable = (soc_litedramcore_uart_rx_fifo_level0 != 1'd0); -assign soc_litedramcore_timer_zero_trigger = (soc_litedramcore_timer_value != 1'd0); -assign soc_litedramcore_timer_eventmanager_status_w = soc_litedramcore_timer_zero_status; - -// synthesis translate_off -reg dummy_d_8; -// synthesis translate_on -always @(*) begin - soc_litedramcore_timer_zero_clear <= 1'd0; - if ((soc_litedramcore_timer_eventmanager_pending_re & soc_litedramcore_timer_eventmanager_pending_r)) begin - soc_litedramcore_timer_zero_clear <= 1'd1; - end -// synthesis translate_off - dummy_d_8 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_timer_eventmanager_pending_w = soc_litedramcore_timer_zero_pending; -assign soc_litedramcore_timer_irq = (soc_litedramcore_timer_eventmanager_pending_w & soc_litedramcore_timer_eventmanager_storage); -assign soc_litedramcore_timer_zero_status = soc_litedramcore_timer_zero_trigger; -assign soc_litedramcore_interface_dat_w = soc_litedramcore_bus_wishbone_dat_w; -assign soc_litedramcore_bus_wishbone_dat_r = soc_litedramcore_interface_dat_r; - -// synthesis translate_off -reg dummy_d_9; -// synthesis translate_on -always @(*) begin - vns_wb2csr_next_state <= 1'd0; - vns_wb2csr_next_state <= vns_wb2csr_state; - case (vns_wb2csr_state) - 1'd1: begin - vns_wb2csr_next_state <= 1'd0; - end - default: begin - if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin - vns_wb2csr_next_state <= 1'd1; - end - end - endcase -// synthesis translate_off - dummy_d_9 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_10; -// synthesis translate_on -always @(*) begin - soc_litedramcore_interface_we <= 1'd0; - case (vns_wb2csr_state) - 1'd1: begin - end - default: begin - if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin - soc_litedramcore_interface_we <= soc_litedramcore_bus_wishbone_we; - end - end - endcase -// synthesis translate_off - dummy_d_10 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_11; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bus_wishbone_ack <= 1'd0; - case (vns_wb2csr_state) - 1'd1: begin - soc_litedramcore_bus_wishbone_ack <= 1'd1; - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_11 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_12; -// synthesis translate_on -always @(*) begin - soc_litedramcore_interface_adr <= 14'd0; - case (vns_wb2csr_state) - 1'd1: begin - end - default: begin - if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin - soc_litedramcore_interface_adr <= soc_litedramcore_bus_wishbone_adr; - end - end - endcase -// synthesis translate_off - dummy_d_12 = dummy_s; -// synthesis translate_on -end -assign soc_sys_pll_reset = rst; -assign pll_locked = soc_sys_pll_locked; -assign soc_iodelay_pll_reset = rst; -assign soc_s7pll0_clkin = clk; -assign sys_clk = soc_s7pll0_clkout_buf0; -assign sys4x_clk = soc_s7pll0_clkout_buf1; -assign sys4x_dqs_clk = soc_s7pll0_clkout_buf2; -assign soc_s7pll1_clkin = clk; -assign iodelay_clk = soc_s7pll1_clkout_buf; -assign soc_a7ddrphy_bitslip0_i = soc_a7ddrphy_dq_i_data0; - -// synthesis translate_off -reg dummy_d_13; -// synthesis translate_on -always @(*) begin - soc_a7ddrphy_dfi_p0_rddata <= 32'd0; - soc_a7ddrphy_dfi_p0_rddata[0] <= soc_a7ddrphy_bitslip0_o[0]; - soc_a7ddrphy_dfi_p0_rddata[16] <= soc_a7ddrphy_bitslip0_o[1]; - soc_a7ddrphy_dfi_p0_rddata[1] <= soc_a7ddrphy_bitslip1_o[0]; - soc_a7ddrphy_dfi_p0_rddata[17] <= soc_a7ddrphy_bitslip1_o[1]; - soc_a7ddrphy_dfi_p0_rddata[2] <= soc_a7ddrphy_bitslip2_o[0]; - soc_a7ddrphy_dfi_p0_rddata[18] <= soc_a7ddrphy_bitslip2_o[1]; - soc_a7ddrphy_dfi_p0_rddata[3] <= soc_a7ddrphy_bitslip3_o[0]; - soc_a7ddrphy_dfi_p0_rddata[19] <= soc_a7ddrphy_bitslip3_o[1]; - soc_a7ddrphy_dfi_p0_rddata[4] <= soc_a7ddrphy_bitslip4_o[0]; - soc_a7ddrphy_dfi_p0_rddata[20] <= soc_a7ddrphy_bitslip4_o[1]; - soc_a7ddrphy_dfi_p0_rddata[5] <= soc_a7ddrphy_bitslip5_o[0]; - soc_a7ddrphy_dfi_p0_rddata[21] <= soc_a7ddrphy_bitslip5_o[1]; - soc_a7ddrphy_dfi_p0_rddata[6] <= soc_a7ddrphy_bitslip6_o[0]; - soc_a7ddrphy_dfi_p0_rddata[22] <= soc_a7ddrphy_bitslip6_o[1]; - soc_a7ddrphy_dfi_p0_rddata[7] <= soc_a7ddrphy_bitslip7_o[0]; - soc_a7ddrphy_dfi_p0_rddata[23] <= soc_a7ddrphy_bitslip7_o[1]; - soc_a7ddrphy_dfi_p0_rddata[8] <= soc_a7ddrphy_bitslip8_o[0]; - soc_a7ddrphy_dfi_p0_rddata[24] <= soc_a7ddrphy_bitslip8_o[1]; - soc_a7ddrphy_dfi_p0_rddata[9] <= soc_a7ddrphy_bitslip9_o[0]; - soc_a7ddrphy_dfi_p0_rddata[25] <= soc_a7ddrphy_bitslip9_o[1]; - soc_a7ddrphy_dfi_p0_rddata[10] <= soc_a7ddrphy_bitslip10_o[0]; - soc_a7ddrphy_dfi_p0_rddata[26] <= soc_a7ddrphy_bitslip10_o[1]; - soc_a7ddrphy_dfi_p0_rddata[11] <= soc_a7ddrphy_bitslip11_o[0]; - soc_a7ddrphy_dfi_p0_rddata[27] <= soc_a7ddrphy_bitslip11_o[1]; - soc_a7ddrphy_dfi_p0_rddata[12] <= soc_a7ddrphy_bitslip12_o[0]; - soc_a7ddrphy_dfi_p0_rddata[28] <= soc_a7ddrphy_bitslip12_o[1]; - soc_a7ddrphy_dfi_p0_rddata[13] <= soc_a7ddrphy_bitslip13_o[0]; - soc_a7ddrphy_dfi_p0_rddata[29] <= soc_a7ddrphy_bitslip13_o[1]; - soc_a7ddrphy_dfi_p0_rddata[14] <= soc_a7ddrphy_bitslip14_o[0]; - soc_a7ddrphy_dfi_p0_rddata[30] <= soc_a7ddrphy_bitslip14_o[1]; - soc_a7ddrphy_dfi_p0_rddata[15] <= soc_a7ddrphy_bitslip15_o[0]; - soc_a7ddrphy_dfi_p0_rddata[31] <= soc_a7ddrphy_bitslip15_o[1]; -// synthesis translate_off - dummy_d_13 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_14; -// synthesis translate_on -always @(*) begin - soc_a7ddrphy_dfi_p1_rddata <= 32'd0; - soc_a7ddrphy_dfi_p1_rddata[0] <= soc_a7ddrphy_bitslip0_o[2]; - soc_a7ddrphy_dfi_p1_rddata[16] <= soc_a7ddrphy_bitslip0_o[3]; - soc_a7ddrphy_dfi_p1_rddata[1] <= soc_a7ddrphy_bitslip1_o[2]; - soc_a7ddrphy_dfi_p1_rddata[17] <= soc_a7ddrphy_bitslip1_o[3]; - soc_a7ddrphy_dfi_p1_rddata[2] <= soc_a7ddrphy_bitslip2_o[2]; - soc_a7ddrphy_dfi_p1_rddata[18] <= soc_a7ddrphy_bitslip2_o[3]; - soc_a7ddrphy_dfi_p1_rddata[3] <= soc_a7ddrphy_bitslip3_o[2]; - soc_a7ddrphy_dfi_p1_rddata[19] <= soc_a7ddrphy_bitslip3_o[3]; - soc_a7ddrphy_dfi_p1_rddata[4] <= soc_a7ddrphy_bitslip4_o[2]; - soc_a7ddrphy_dfi_p1_rddata[20] <= soc_a7ddrphy_bitslip4_o[3]; - soc_a7ddrphy_dfi_p1_rddata[5] <= soc_a7ddrphy_bitslip5_o[2]; - soc_a7ddrphy_dfi_p1_rddata[21] <= soc_a7ddrphy_bitslip5_o[3]; - soc_a7ddrphy_dfi_p1_rddata[6] <= soc_a7ddrphy_bitslip6_o[2]; - soc_a7ddrphy_dfi_p1_rddata[22] <= soc_a7ddrphy_bitslip6_o[3]; - soc_a7ddrphy_dfi_p1_rddata[7] <= soc_a7ddrphy_bitslip7_o[2]; - soc_a7ddrphy_dfi_p1_rddata[23] <= soc_a7ddrphy_bitslip7_o[3]; - soc_a7ddrphy_dfi_p1_rddata[8] <= soc_a7ddrphy_bitslip8_o[2]; - soc_a7ddrphy_dfi_p1_rddata[24] <= soc_a7ddrphy_bitslip8_o[3]; - soc_a7ddrphy_dfi_p1_rddata[9] <= soc_a7ddrphy_bitslip9_o[2]; - soc_a7ddrphy_dfi_p1_rddata[25] <= soc_a7ddrphy_bitslip9_o[3]; - soc_a7ddrphy_dfi_p1_rddata[10] <= soc_a7ddrphy_bitslip10_o[2]; - soc_a7ddrphy_dfi_p1_rddata[26] <= soc_a7ddrphy_bitslip10_o[3]; - soc_a7ddrphy_dfi_p1_rddata[11] <= soc_a7ddrphy_bitslip11_o[2]; - soc_a7ddrphy_dfi_p1_rddata[27] <= soc_a7ddrphy_bitslip11_o[3]; - soc_a7ddrphy_dfi_p1_rddata[12] <= soc_a7ddrphy_bitslip12_o[2]; - soc_a7ddrphy_dfi_p1_rddata[28] <= soc_a7ddrphy_bitslip12_o[3]; - soc_a7ddrphy_dfi_p1_rddata[13] <= soc_a7ddrphy_bitslip13_o[2]; - soc_a7ddrphy_dfi_p1_rddata[29] <= soc_a7ddrphy_bitslip13_o[3]; - soc_a7ddrphy_dfi_p1_rddata[14] <= soc_a7ddrphy_bitslip14_o[2]; - soc_a7ddrphy_dfi_p1_rddata[30] <= soc_a7ddrphy_bitslip14_o[3]; - soc_a7ddrphy_dfi_p1_rddata[15] <= soc_a7ddrphy_bitslip15_o[2]; - soc_a7ddrphy_dfi_p1_rddata[31] <= soc_a7ddrphy_bitslip15_o[3]; -// synthesis translate_off - dummy_d_14 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_15; -// synthesis translate_on -always @(*) begin - soc_a7ddrphy_dfi_p2_rddata <= 32'd0; - soc_a7ddrphy_dfi_p2_rddata[0] <= soc_a7ddrphy_bitslip0_o[4]; - soc_a7ddrphy_dfi_p2_rddata[16] <= soc_a7ddrphy_bitslip0_o[5]; - soc_a7ddrphy_dfi_p2_rddata[1] <= soc_a7ddrphy_bitslip1_o[4]; - soc_a7ddrphy_dfi_p2_rddata[17] <= soc_a7ddrphy_bitslip1_o[5]; - soc_a7ddrphy_dfi_p2_rddata[2] <= soc_a7ddrphy_bitslip2_o[4]; - soc_a7ddrphy_dfi_p2_rddata[18] <= soc_a7ddrphy_bitslip2_o[5]; - soc_a7ddrphy_dfi_p2_rddata[3] <= soc_a7ddrphy_bitslip3_o[4]; - soc_a7ddrphy_dfi_p2_rddata[19] <= soc_a7ddrphy_bitslip3_o[5]; - soc_a7ddrphy_dfi_p2_rddata[4] <= soc_a7ddrphy_bitslip4_o[4]; - soc_a7ddrphy_dfi_p2_rddata[20] <= soc_a7ddrphy_bitslip4_o[5]; - soc_a7ddrphy_dfi_p2_rddata[5] <= soc_a7ddrphy_bitslip5_o[4]; - soc_a7ddrphy_dfi_p2_rddata[21] <= soc_a7ddrphy_bitslip5_o[5]; - soc_a7ddrphy_dfi_p2_rddata[6] <= soc_a7ddrphy_bitslip6_o[4]; - soc_a7ddrphy_dfi_p2_rddata[22] <= soc_a7ddrphy_bitslip6_o[5]; - soc_a7ddrphy_dfi_p2_rddata[7] <= soc_a7ddrphy_bitslip7_o[4]; - soc_a7ddrphy_dfi_p2_rddata[23] <= soc_a7ddrphy_bitslip7_o[5]; - soc_a7ddrphy_dfi_p2_rddata[8] <= soc_a7ddrphy_bitslip8_o[4]; - soc_a7ddrphy_dfi_p2_rddata[24] <= soc_a7ddrphy_bitslip8_o[5]; - soc_a7ddrphy_dfi_p2_rddata[9] <= soc_a7ddrphy_bitslip9_o[4]; - soc_a7ddrphy_dfi_p2_rddata[25] <= soc_a7ddrphy_bitslip9_o[5]; - soc_a7ddrphy_dfi_p2_rddata[10] <= soc_a7ddrphy_bitslip10_o[4]; - soc_a7ddrphy_dfi_p2_rddata[26] <= soc_a7ddrphy_bitslip10_o[5]; - soc_a7ddrphy_dfi_p2_rddata[11] <= soc_a7ddrphy_bitslip11_o[4]; - soc_a7ddrphy_dfi_p2_rddata[27] <= soc_a7ddrphy_bitslip11_o[5]; - soc_a7ddrphy_dfi_p2_rddata[12] <= soc_a7ddrphy_bitslip12_o[4]; - soc_a7ddrphy_dfi_p2_rddata[28] <= soc_a7ddrphy_bitslip12_o[5]; - soc_a7ddrphy_dfi_p2_rddata[13] <= soc_a7ddrphy_bitslip13_o[4]; - soc_a7ddrphy_dfi_p2_rddata[29] <= soc_a7ddrphy_bitslip13_o[5]; - soc_a7ddrphy_dfi_p2_rddata[14] <= soc_a7ddrphy_bitslip14_o[4]; - soc_a7ddrphy_dfi_p2_rddata[30] <= soc_a7ddrphy_bitslip14_o[5]; - soc_a7ddrphy_dfi_p2_rddata[15] <= soc_a7ddrphy_bitslip15_o[4]; - soc_a7ddrphy_dfi_p2_rddata[31] <= soc_a7ddrphy_bitslip15_o[5]; -// synthesis translate_off - dummy_d_15 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_16; -// synthesis translate_on -always @(*) begin - soc_a7ddrphy_dfi_p3_rddata <= 32'd0; - soc_a7ddrphy_dfi_p3_rddata[0] <= soc_a7ddrphy_bitslip0_o[6]; - soc_a7ddrphy_dfi_p3_rddata[16] <= soc_a7ddrphy_bitslip0_o[7]; - soc_a7ddrphy_dfi_p3_rddata[1] <= soc_a7ddrphy_bitslip1_o[6]; - soc_a7ddrphy_dfi_p3_rddata[17] <= soc_a7ddrphy_bitslip1_o[7]; - soc_a7ddrphy_dfi_p3_rddata[2] <= soc_a7ddrphy_bitslip2_o[6]; - soc_a7ddrphy_dfi_p3_rddata[18] <= soc_a7ddrphy_bitslip2_o[7]; - soc_a7ddrphy_dfi_p3_rddata[3] <= soc_a7ddrphy_bitslip3_o[6]; - soc_a7ddrphy_dfi_p3_rddata[19] <= soc_a7ddrphy_bitslip3_o[7]; - soc_a7ddrphy_dfi_p3_rddata[4] <= soc_a7ddrphy_bitslip4_o[6]; - soc_a7ddrphy_dfi_p3_rddata[20] <= soc_a7ddrphy_bitslip4_o[7]; - soc_a7ddrphy_dfi_p3_rddata[5] <= soc_a7ddrphy_bitslip5_o[6]; - soc_a7ddrphy_dfi_p3_rddata[21] <= soc_a7ddrphy_bitslip5_o[7]; - soc_a7ddrphy_dfi_p3_rddata[6] <= soc_a7ddrphy_bitslip6_o[6]; - soc_a7ddrphy_dfi_p3_rddata[22] <= soc_a7ddrphy_bitslip6_o[7]; - soc_a7ddrphy_dfi_p3_rddata[7] <= soc_a7ddrphy_bitslip7_o[6]; - soc_a7ddrphy_dfi_p3_rddata[23] <= soc_a7ddrphy_bitslip7_o[7]; - soc_a7ddrphy_dfi_p3_rddata[8] <= soc_a7ddrphy_bitslip8_o[6]; - soc_a7ddrphy_dfi_p3_rddata[24] <= soc_a7ddrphy_bitslip8_o[7]; - soc_a7ddrphy_dfi_p3_rddata[9] <= soc_a7ddrphy_bitslip9_o[6]; - soc_a7ddrphy_dfi_p3_rddata[25] <= soc_a7ddrphy_bitslip9_o[7]; - soc_a7ddrphy_dfi_p3_rddata[10] <= soc_a7ddrphy_bitslip10_o[6]; - soc_a7ddrphy_dfi_p3_rddata[26] <= soc_a7ddrphy_bitslip10_o[7]; - soc_a7ddrphy_dfi_p3_rddata[11] <= soc_a7ddrphy_bitslip11_o[6]; - soc_a7ddrphy_dfi_p3_rddata[27] <= soc_a7ddrphy_bitslip11_o[7]; - soc_a7ddrphy_dfi_p3_rddata[12] <= soc_a7ddrphy_bitslip12_o[6]; - soc_a7ddrphy_dfi_p3_rddata[28] <= soc_a7ddrphy_bitslip12_o[7]; - soc_a7ddrphy_dfi_p3_rddata[13] <= soc_a7ddrphy_bitslip13_o[6]; - soc_a7ddrphy_dfi_p3_rddata[29] <= soc_a7ddrphy_bitslip13_o[7]; - soc_a7ddrphy_dfi_p3_rddata[14] <= soc_a7ddrphy_bitslip14_o[6]; - soc_a7ddrphy_dfi_p3_rddata[30] <= soc_a7ddrphy_bitslip14_o[7]; - soc_a7ddrphy_dfi_p3_rddata[15] <= soc_a7ddrphy_bitslip15_o[6]; - soc_a7ddrphy_dfi_p3_rddata[31] <= soc_a7ddrphy_bitslip15_o[7]; -// synthesis translate_off - dummy_d_16 = dummy_s; -// synthesis translate_on -end -assign soc_a7ddrphy_bitslip1_i = soc_a7ddrphy_dq_i_data1; -assign soc_a7ddrphy_bitslip2_i = soc_a7ddrphy_dq_i_data2; -assign soc_a7ddrphy_bitslip3_i = soc_a7ddrphy_dq_i_data3; -assign soc_a7ddrphy_bitslip4_i = soc_a7ddrphy_dq_i_data4; -assign soc_a7ddrphy_bitslip5_i = soc_a7ddrphy_dq_i_data5; -assign soc_a7ddrphy_bitslip6_i = soc_a7ddrphy_dq_i_data6; -assign soc_a7ddrphy_bitslip7_i = soc_a7ddrphy_dq_i_data7; -assign soc_a7ddrphy_bitslip8_i = soc_a7ddrphy_dq_i_data8; -assign soc_a7ddrphy_bitslip9_i = soc_a7ddrphy_dq_i_data9; -assign soc_a7ddrphy_bitslip10_i = soc_a7ddrphy_dq_i_data10; -assign soc_a7ddrphy_bitslip11_i = soc_a7ddrphy_dq_i_data11; -assign soc_a7ddrphy_bitslip12_i = soc_a7ddrphy_dq_i_data12; -assign soc_a7ddrphy_bitslip13_i = soc_a7ddrphy_dq_i_data13; -assign soc_a7ddrphy_bitslip14_i = soc_a7ddrphy_dq_i_data14; -assign soc_a7ddrphy_bitslip15_i = soc_a7ddrphy_dq_i_data15; -assign soc_a7ddrphy_rddata_en = {soc_a7ddrphy_rddata_en_last, soc_a7ddrphy_dfi_p2_rddata_en}; -assign soc_a7ddrphy_wrdata_en = {soc_a7ddrphy_wrdata_en_last, soc_a7ddrphy_dfi_p3_wrdata_en}; -assign soc_a7ddrphy_dq_oe = soc_a7ddrphy_wrdata_en[2]; - -// synthesis translate_off -reg dummy_d_17; -// synthesis translate_on -always @(*) begin - soc_a7ddrphy_dqs_oe <= 1'd0; - if (soc_a7ddrphy_wlevel_en_storage) begin - soc_a7ddrphy_dqs_oe <= 1'd1; + a7ddrphy_dqs_oe <= 1'd0; + if (a7ddrphy_wlevel_en_storage) begin + a7ddrphy_dqs_oe <= 1'd1; end else begin - soc_a7ddrphy_dqs_oe <= soc_a7ddrphy_dq_oe; + a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; end // synthesis translate_off - dummy_d_17 = dummy_s; + dummy_d_4 = dummy_s; // synthesis translate_on end -assign soc_a7ddrphy_dqspattern0 = (soc_a7ddrphy_wrdata_en[1] & (~soc_a7ddrphy_wrdata_en[2])); -assign soc_a7ddrphy_dqspattern1 = (soc_a7ddrphy_wrdata_en[3] & (~soc_a7ddrphy_wrdata_en[2])); +assign a7ddrphy_dqspattern0 = (a7ddrphy_wrdata_en[1] & (~a7ddrphy_wrdata_en[2])); +assign a7ddrphy_dqspattern1 = (a7ddrphy_wrdata_en[3] & (~a7ddrphy_wrdata_en[2])); // synthesis translate_off -reg dummy_d_18; +reg dummy_d_5; // synthesis translate_on always @(*) begin - soc_a7ddrphy_dqspattern_o0 <= 8'd0; - soc_a7ddrphy_dqspattern_o0 <= 7'd85; - if (soc_a7ddrphy_dqspattern0) begin - soc_a7ddrphy_dqspattern_o0 <= 5'd21; + a7ddrphy_dqspattern_o0 <= 8'd0; + a7ddrphy_dqspattern_o0 <= 7'd85; + if (a7ddrphy_dqspattern0) begin + a7ddrphy_dqspattern_o0 <= 5'd21; end - if (soc_a7ddrphy_dqspattern1) begin - soc_a7ddrphy_dqspattern_o0 <= 7'd84; + if (a7ddrphy_dqspattern1) begin + a7ddrphy_dqspattern_o0 <= 7'd84; end - if (soc_a7ddrphy_wlevel_en_storage) begin - soc_a7ddrphy_dqspattern_o0 <= 1'd0; - if (soc_a7ddrphy_wlevel_strobe_re) begin - soc_a7ddrphy_dqspattern_o0 <= 1'd1; + if (a7ddrphy_wlevel_en_storage) begin + a7ddrphy_dqspattern_o0 <= 1'd0; + if (a7ddrphy_wlevel_strobe_re) begin + a7ddrphy_dqspattern_o0 <= 1'd1; end end // synthesis translate_off - dummy_d_18 = dummy_s; + dummy_d_5 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_19; +reg dummy_d_6; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip0_o <= 8'd0; - case (soc_a7ddrphy_bitslip0_value) + a7ddrphy_bitslip0_o <= 8'd0; + case (a7ddrphy_bitslip0_value) 1'd0: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[7:0]; + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[8:1]; + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[9:2]; + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[10:3]; + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[11:4]; + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[12:5]; + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[13:6]; + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[14:7]; + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[14:7]; end endcase // synthesis translate_off - dummy_d_19 = dummy_s; + dummy_d_6 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_20; +reg dummy_d_7; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip1_o <= 8'd0; - case (soc_a7ddrphy_bitslip1_value) + a7ddrphy_bitslip1_o <= 8'd0; + case (a7ddrphy_bitslip1_value) 1'd0: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[7:0]; + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[8:1]; + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[9:2]; + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[10:3]; + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[11:4]; + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[12:5]; + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[13:6]; + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[14:7]; + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[14:7]; end endcase // synthesis translate_off - dummy_d_20 = dummy_s; + dummy_d_7 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_21; +reg dummy_d_8; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip2_o <= 8'd0; - case (soc_a7ddrphy_bitslip2_value) + a7ddrphy_bitslip2_o <= 8'd0; + case (a7ddrphy_bitslip2_value) 1'd0: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[7:0]; + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[8:1]; + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[9:2]; + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[10:3]; + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[11:4]; + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[12:5]; + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[13:6]; + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[14:7]; + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[14:7]; end endcase // synthesis translate_off - dummy_d_21 = dummy_s; + dummy_d_8 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_22; +reg dummy_d_9; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip3_o <= 8'd0; - case (soc_a7ddrphy_bitslip3_value) + a7ddrphy_bitslip3_o <= 8'd0; + case (a7ddrphy_bitslip3_value) 1'd0: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[7:0]; + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[8:1]; + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[9:2]; + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[10:3]; + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[11:4]; + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[12:5]; + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[13:6]; + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[14:7]; + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[14:7]; end endcase // synthesis translate_off - dummy_d_22 = dummy_s; + dummy_d_9 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_23; +reg dummy_d_10; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip4_o <= 8'd0; - case (soc_a7ddrphy_bitslip4_value) + a7ddrphy_bitslip4_o <= 8'd0; + case (a7ddrphy_bitslip4_value) 1'd0: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[7:0]; + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[8:1]; + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[9:2]; + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[10:3]; + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[11:4]; + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[12:5]; + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[13:6]; + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[14:7]; + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[14:7]; end endcase // synthesis translate_off - dummy_d_23 = dummy_s; + dummy_d_10 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_24; +reg dummy_d_11; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip5_o <= 8'd0; - case (soc_a7ddrphy_bitslip5_value) + a7ddrphy_bitslip5_o <= 8'd0; + case (a7ddrphy_bitslip5_value) 1'd0: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[7:0]; + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[8:1]; + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[9:2]; + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[10:3]; + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[11:4]; + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[12:5]; + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[13:6]; + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[14:7]; + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[14:7]; end endcase // synthesis translate_off - dummy_d_24 = dummy_s; + dummy_d_11 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_25; +reg dummy_d_12; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip6_o <= 8'd0; - case (soc_a7ddrphy_bitslip6_value) + a7ddrphy_bitslip6_o <= 8'd0; + case (a7ddrphy_bitslip6_value) 1'd0: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[7:0]; + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[8:1]; + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[9:2]; + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[10:3]; + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[11:4]; + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[12:5]; + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[13:6]; + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[14:7]; + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[14:7]; end endcase // synthesis translate_off - dummy_d_25 = dummy_s; + dummy_d_12 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_26; +reg dummy_d_13; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip7_o <= 8'd0; - case (soc_a7ddrphy_bitslip7_value) + a7ddrphy_bitslip7_o <= 8'd0; + case (a7ddrphy_bitslip7_value) 1'd0: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[7:0]; + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[8:1]; + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[9:2]; + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[10:3]; + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[11:4]; + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[12:5]; + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[13:6]; + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[14:7]; + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[14:7]; end endcase // synthesis translate_off - dummy_d_26 = dummy_s; + dummy_d_13 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_27; +reg dummy_d_14; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip8_o <= 8'd0; - case (soc_a7ddrphy_bitslip8_value) + a7ddrphy_bitslip8_o <= 8'd0; + case (a7ddrphy_bitslip8_value) 1'd0: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[7:0]; + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[8:1]; + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[9:2]; + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[10:3]; + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[11:4]; + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[12:5]; + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[13:6]; + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[14:7]; + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[14:7]; end endcase // synthesis translate_off - dummy_d_27 = dummy_s; + dummy_d_14 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_28; +reg dummy_d_15; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip9_o <= 8'd0; - case (soc_a7ddrphy_bitslip9_value) + a7ddrphy_bitslip9_o <= 8'd0; + case (a7ddrphy_bitslip9_value) 1'd0: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[7:0]; + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[8:1]; + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[9:2]; + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[10:3]; + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[11:4]; + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[12:5]; + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[13:6]; + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[14:7]; + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[14:7]; end endcase // synthesis translate_off - dummy_d_28 = dummy_s; + dummy_d_15 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_29; +reg dummy_d_16; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip10_o <= 8'd0; - case (soc_a7ddrphy_bitslip10_value) + a7ddrphy_bitslip10_o <= 8'd0; + case (a7ddrphy_bitslip10_value) 1'd0: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[7:0]; + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[8:1]; + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[9:2]; + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[10:3]; + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[11:4]; + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[12:5]; + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[13:6]; + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[14:7]; + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[14:7]; end endcase // synthesis translate_off - dummy_d_29 = dummy_s; + dummy_d_16 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_30; +reg dummy_d_17; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip11_o <= 8'd0; - case (soc_a7ddrphy_bitslip11_value) + a7ddrphy_bitslip11_o <= 8'd0; + case (a7ddrphy_bitslip11_value) 1'd0: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[7:0]; + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[8:1]; + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[9:2]; + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[10:3]; + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[11:4]; + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[12:5]; + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[13:6]; + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[14:7]; + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[14:7]; end endcase // synthesis translate_off - dummy_d_30 = dummy_s; + dummy_d_17 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_31; +reg dummy_d_18; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip12_o <= 8'd0; - case (soc_a7ddrphy_bitslip12_value) + a7ddrphy_bitslip12_o <= 8'd0; + case (a7ddrphy_bitslip12_value) 1'd0: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[7:0]; + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[8:1]; + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[9:2]; + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[10:3]; + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[11:4]; + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[12:5]; + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[13:6]; + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[14:7]; + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[14:7]; end endcase // synthesis translate_off - dummy_d_31 = dummy_s; + dummy_d_18 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_32; +reg dummy_d_19; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip13_o <= 8'd0; - case (soc_a7ddrphy_bitslip13_value) + a7ddrphy_bitslip13_o <= 8'd0; + case (a7ddrphy_bitslip13_value) 1'd0: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[7:0]; + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[8:1]; + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[9:2]; + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[10:3]; + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[11:4]; + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[12:5]; + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[13:6]; + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[14:7]; + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[14:7]; end endcase // synthesis translate_off - dummy_d_32 = dummy_s; + dummy_d_19 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_33; +reg dummy_d_20; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip14_o <= 8'd0; - case (soc_a7ddrphy_bitslip14_value) + a7ddrphy_bitslip14_o <= 8'd0; + case (a7ddrphy_bitslip14_value) 1'd0: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[7:0]; + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[8:1]; + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[9:2]; + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[10:3]; + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[11:4]; + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[12:5]; + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[13:6]; + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[14:7]; + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[14:7]; end endcase // synthesis translate_off - dummy_d_33 = dummy_s; + dummy_d_20 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_34; +reg dummy_d_21; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip15_o <= 8'd0; - case (soc_a7ddrphy_bitslip15_value) + a7ddrphy_bitslip15_o <= 8'd0; + case (a7ddrphy_bitslip15_value) 1'd0: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[7:0]; + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[8:1]; + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[9:2]; + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[10:3]; + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[11:4]; + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[12:5]; + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[13:6]; + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[14:7]; + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[14:7]; end endcase // synthesis translate_off - dummy_d_34 = dummy_s; + dummy_d_21 = dummy_s; // synthesis translate_on end -assign soc_a7ddrphy_dfi_p0_address = soc_sdram_master_p0_address; -assign soc_a7ddrphy_dfi_p0_bank = soc_sdram_master_p0_bank; -assign soc_a7ddrphy_dfi_p0_cas_n = soc_sdram_master_p0_cas_n; -assign soc_a7ddrphy_dfi_p0_cs_n = soc_sdram_master_p0_cs_n; -assign soc_a7ddrphy_dfi_p0_ras_n = soc_sdram_master_p0_ras_n; -assign soc_a7ddrphy_dfi_p0_we_n = soc_sdram_master_p0_we_n; -assign soc_a7ddrphy_dfi_p0_cke = soc_sdram_master_p0_cke; -assign soc_a7ddrphy_dfi_p0_odt = soc_sdram_master_p0_odt; -assign soc_a7ddrphy_dfi_p0_reset_n = soc_sdram_master_p0_reset_n; -assign soc_a7ddrphy_dfi_p0_act_n = soc_sdram_master_p0_act_n; -assign soc_a7ddrphy_dfi_p0_wrdata = soc_sdram_master_p0_wrdata; -assign soc_a7ddrphy_dfi_p0_wrdata_en = soc_sdram_master_p0_wrdata_en; -assign soc_a7ddrphy_dfi_p0_wrdata_mask = soc_sdram_master_p0_wrdata_mask; -assign soc_a7ddrphy_dfi_p0_rddata_en = soc_sdram_master_p0_rddata_en; -assign soc_sdram_master_p0_rddata = soc_a7ddrphy_dfi_p0_rddata; -assign soc_sdram_master_p0_rddata_valid = soc_a7ddrphy_dfi_p0_rddata_valid; -assign soc_a7ddrphy_dfi_p1_address = soc_sdram_master_p1_address; -assign soc_a7ddrphy_dfi_p1_bank = soc_sdram_master_p1_bank; -assign soc_a7ddrphy_dfi_p1_cas_n = soc_sdram_master_p1_cas_n; -assign soc_a7ddrphy_dfi_p1_cs_n = soc_sdram_master_p1_cs_n; -assign soc_a7ddrphy_dfi_p1_ras_n = soc_sdram_master_p1_ras_n; -assign soc_a7ddrphy_dfi_p1_we_n = soc_sdram_master_p1_we_n; -assign soc_a7ddrphy_dfi_p1_cke = soc_sdram_master_p1_cke; -assign soc_a7ddrphy_dfi_p1_odt = soc_sdram_master_p1_odt; -assign soc_a7ddrphy_dfi_p1_reset_n = soc_sdram_master_p1_reset_n; -assign soc_a7ddrphy_dfi_p1_act_n = soc_sdram_master_p1_act_n; -assign soc_a7ddrphy_dfi_p1_wrdata = soc_sdram_master_p1_wrdata; -assign soc_a7ddrphy_dfi_p1_wrdata_en = soc_sdram_master_p1_wrdata_en; -assign soc_a7ddrphy_dfi_p1_wrdata_mask = soc_sdram_master_p1_wrdata_mask; -assign soc_a7ddrphy_dfi_p1_rddata_en = soc_sdram_master_p1_rddata_en; -assign soc_sdram_master_p1_rddata = soc_a7ddrphy_dfi_p1_rddata; -assign soc_sdram_master_p1_rddata_valid = soc_a7ddrphy_dfi_p1_rddata_valid; -assign soc_a7ddrphy_dfi_p2_address = soc_sdram_master_p2_address; -assign soc_a7ddrphy_dfi_p2_bank = soc_sdram_master_p2_bank; -assign soc_a7ddrphy_dfi_p2_cas_n = soc_sdram_master_p2_cas_n; -assign soc_a7ddrphy_dfi_p2_cs_n = soc_sdram_master_p2_cs_n; -assign soc_a7ddrphy_dfi_p2_ras_n = soc_sdram_master_p2_ras_n; -assign soc_a7ddrphy_dfi_p2_we_n = soc_sdram_master_p2_we_n; -assign soc_a7ddrphy_dfi_p2_cke = soc_sdram_master_p2_cke; -assign soc_a7ddrphy_dfi_p2_odt = soc_sdram_master_p2_odt; -assign soc_a7ddrphy_dfi_p2_reset_n = soc_sdram_master_p2_reset_n; -assign soc_a7ddrphy_dfi_p2_act_n = soc_sdram_master_p2_act_n; -assign soc_a7ddrphy_dfi_p2_wrdata = soc_sdram_master_p2_wrdata; -assign soc_a7ddrphy_dfi_p2_wrdata_en = soc_sdram_master_p2_wrdata_en; -assign soc_a7ddrphy_dfi_p2_wrdata_mask = soc_sdram_master_p2_wrdata_mask; -assign soc_a7ddrphy_dfi_p2_rddata_en = soc_sdram_master_p2_rddata_en; -assign soc_sdram_master_p2_rddata = soc_a7ddrphy_dfi_p2_rddata; -assign soc_sdram_master_p2_rddata_valid = soc_a7ddrphy_dfi_p2_rddata_valid; -assign soc_a7ddrphy_dfi_p3_address = soc_sdram_master_p3_address; -assign soc_a7ddrphy_dfi_p3_bank = soc_sdram_master_p3_bank; -assign soc_a7ddrphy_dfi_p3_cas_n = soc_sdram_master_p3_cas_n; -assign soc_a7ddrphy_dfi_p3_cs_n = soc_sdram_master_p3_cs_n; -assign soc_a7ddrphy_dfi_p3_ras_n = soc_sdram_master_p3_ras_n; -assign soc_a7ddrphy_dfi_p3_we_n = soc_sdram_master_p3_we_n; -assign soc_a7ddrphy_dfi_p3_cke = soc_sdram_master_p3_cke; -assign soc_a7ddrphy_dfi_p3_odt = soc_sdram_master_p3_odt; -assign soc_a7ddrphy_dfi_p3_reset_n = soc_sdram_master_p3_reset_n; -assign soc_a7ddrphy_dfi_p3_act_n = soc_sdram_master_p3_act_n; -assign soc_a7ddrphy_dfi_p3_wrdata = soc_sdram_master_p3_wrdata; -assign soc_a7ddrphy_dfi_p3_wrdata_en = soc_sdram_master_p3_wrdata_en; -assign soc_a7ddrphy_dfi_p3_wrdata_mask = soc_sdram_master_p3_wrdata_mask; -assign soc_a7ddrphy_dfi_p3_rddata_en = soc_sdram_master_p3_rddata_en; -assign soc_sdram_master_p3_rddata = soc_a7ddrphy_dfi_p3_rddata; -assign soc_sdram_master_p3_rddata_valid = soc_a7ddrphy_dfi_p3_rddata_valid; -assign soc_sdram_slave_p0_address = soc_sdram_dfi_p0_address; -assign soc_sdram_slave_p0_bank = soc_sdram_dfi_p0_bank; -assign soc_sdram_slave_p0_cas_n = soc_sdram_dfi_p0_cas_n; -assign soc_sdram_slave_p0_cs_n = soc_sdram_dfi_p0_cs_n; -assign soc_sdram_slave_p0_ras_n = soc_sdram_dfi_p0_ras_n; -assign soc_sdram_slave_p0_we_n = soc_sdram_dfi_p0_we_n; -assign soc_sdram_slave_p0_cke = soc_sdram_dfi_p0_cke; -assign soc_sdram_slave_p0_odt = soc_sdram_dfi_p0_odt; -assign soc_sdram_slave_p0_reset_n = soc_sdram_dfi_p0_reset_n; -assign soc_sdram_slave_p0_act_n = soc_sdram_dfi_p0_act_n; -assign soc_sdram_slave_p0_wrdata = soc_sdram_dfi_p0_wrdata; -assign soc_sdram_slave_p0_wrdata_en = soc_sdram_dfi_p0_wrdata_en; -assign soc_sdram_slave_p0_wrdata_mask = soc_sdram_dfi_p0_wrdata_mask; -assign soc_sdram_slave_p0_rddata_en = soc_sdram_dfi_p0_rddata_en; -assign soc_sdram_dfi_p0_rddata = soc_sdram_slave_p0_rddata; -assign soc_sdram_dfi_p0_rddata_valid = soc_sdram_slave_p0_rddata_valid; -assign soc_sdram_slave_p1_address = soc_sdram_dfi_p1_address; -assign soc_sdram_slave_p1_bank = soc_sdram_dfi_p1_bank; -assign soc_sdram_slave_p1_cas_n = soc_sdram_dfi_p1_cas_n; -assign soc_sdram_slave_p1_cs_n = soc_sdram_dfi_p1_cs_n; -assign soc_sdram_slave_p1_ras_n = soc_sdram_dfi_p1_ras_n; -assign soc_sdram_slave_p1_we_n = soc_sdram_dfi_p1_we_n; -assign soc_sdram_slave_p1_cke = soc_sdram_dfi_p1_cke; -assign soc_sdram_slave_p1_odt = soc_sdram_dfi_p1_odt; -assign soc_sdram_slave_p1_reset_n = soc_sdram_dfi_p1_reset_n; -assign soc_sdram_slave_p1_act_n = soc_sdram_dfi_p1_act_n; -assign soc_sdram_slave_p1_wrdata = soc_sdram_dfi_p1_wrdata; -assign soc_sdram_slave_p1_wrdata_en = soc_sdram_dfi_p1_wrdata_en; -assign soc_sdram_slave_p1_wrdata_mask = soc_sdram_dfi_p1_wrdata_mask; -assign soc_sdram_slave_p1_rddata_en = soc_sdram_dfi_p1_rddata_en; -assign soc_sdram_dfi_p1_rddata = soc_sdram_slave_p1_rddata; -assign soc_sdram_dfi_p1_rddata_valid = soc_sdram_slave_p1_rddata_valid; -assign soc_sdram_slave_p2_address = soc_sdram_dfi_p2_address; -assign soc_sdram_slave_p2_bank = soc_sdram_dfi_p2_bank; -assign soc_sdram_slave_p2_cas_n = soc_sdram_dfi_p2_cas_n; -assign soc_sdram_slave_p2_cs_n = soc_sdram_dfi_p2_cs_n; -assign soc_sdram_slave_p2_ras_n = soc_sdram_dfi_p2_ras_n; -assign soc_sdram_slave_p2_we_n = soc_sdram_dfi_p2_we_n; -assign soc_sdram_slave_p2_cke = soc_sdram_dfi_p2_cke; -assign soc_sdram_slave_p2_odt = soc_sdram_dfi_p2_odt; -assign soc_sdram_slave_p2_reset_n = soc_sdram_dfi_p2_reset_n; -assign soc_sdram_slave_p2_act_n = soc_sdram_dfi_p2_act_n; -assign soc_sdram_slave_p2_wrdata = soc_sdram_dfi_p2_wrdata; -assign soc_sdram_slave_p2_wrdata_en = soc_sdram_dfi_p2_wrdata_en; -assign soc_sdram_slave_p2_wrdata_mask = soc_sdram_dfi_p2_wrdata_mask; -assign soc_sdram_slave_p2_rddata_en = soc_sdram_dfi_p2_rddata_en; -assign soc_sdram_dfi_p2_rddata = soc_sdram_slave_p2_rddata; -assign soc_sdram_dfi_p2_rddata_valid = soc_sdram_slave_p2_rddata_valid; -assign soc_sdram_slave_p3_address = soc_sdram_dfi_p3_address; -assign soc_sdram_slave_p3_bank = soc_sdram_dfi_p3_bank; -assign soc_sdram_slave_p3_cas_n = soc_sdram_dfi_p3_cas_n; -assign soc_sdram_slave_p3_cs_n = soc_sdram_dfi_p3_cs_n; -assign soc_sdram_slave_p3_ras_n = soc_sdram_dfi_p3_ras_n; -assign soc_sdram_slave_p3_we_n = soc_sdram_dfi_p3_we_n; -assign soc_sdram_slave_p3_cke = soc_sdram_dfi_p3_cke; -assign soc_sdram_slave_p3_odt = soc_sdram_dfi_p3_odt; -assign soc_sdram_slave_p3_reset_n = soc_sdram_dfi_p3_reset_n; -assign soc_sdram_slave_p3_act_n = soc_sdram_dfi_p3_act_n; -assign soc_sdram_slave_p3_wrdata = soc_sdram_dfi_p3_wrdata; -assign soc_sdram_slave_p3_wrdata_en = soc_sdram_dfi_p3_wrdata_en; -assign soc_sdram_slave_p3_wrdata_mask = soc_sdram_dfi_p3_wrdata_mask; -assign soc_sdram_slave_p3_rddata_en = soc_sdram_dfi_p3_rddata_en; -assign soc_sdram_dfi_p3_rddata = soc_sdram_slave_p3_rddata; -assign soc_sdram_dfi_p3_rddata_valid = soc_sdram_slave_p3_rddata_valid; +assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address; +assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank; +assign a7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n; +assign a7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n; +assign a7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n; +assign a7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n; +assign a7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke; +assign a7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt; +assign a7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n; +assign a7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n; +assign a7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata; +assign a7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en; +assign a7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask; +assign a7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en; +assign litedramcore_master_p0_rddata = a7ddrphy_dfi_p0_rddata; +assign litedramcore_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid; +assign a7ddrphy_dfi_p1_address = litedramcore_master_p1_address; +assign a7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank; +assign a7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n; +assign a7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n; +assign a7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n; +assign a7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n; +assign a7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke; +assign a7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt; +assign a7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n; +assign a7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n; +assign a7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata; +assign a7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en; +assign a7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask; +assign a7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en; +assign litedramcore_master_p1_rddata = a7ddrphy_dfi_p1_rddata; +assign litedramcore_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid; +assign a7ddrphy_dfi_p2_address = litedramcore_master_p2_address; +assign a7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank; +assign a7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n; +assign a7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n; +assign a7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n; +assign a7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n; +assign a7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke; +assign a7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt; +assign a7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n; +assign a7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n; +assign a7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata; +assign a7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en; +assign a7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask; +assign a7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en; +assign litedramcore_master_p2_rddata = a7ddrphy_dfi_p2_rddata; +assign litedramcore_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid; +assign a7ddrphy_dfi_p3_address = litedramcore_master_p3_address; +assign a7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank; +assign a7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n; +assign a7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n; +assign a7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n; +assign a7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n; +assign a7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke; +assign a7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt; +assign a7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n; +assign a7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n; +assign a7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata; +assign a7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en; +assign a7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask; +assign a7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en; +assign litedramcore_master_p3_rddata = a7ddrphy_dfi_p3_rddata; +assign litedramcore_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid; +assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address; +assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank; +assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n; +assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n; +assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n; +assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n; +assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke; +assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt; +assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n; +assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n; +assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata; +assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en; +assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask; +assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en; +assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata; +assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid; +assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address; +assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank; +assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n; +assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n; +assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n; +assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n; +assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke; +assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt; +assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n; +assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n; +assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata; +assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en; +assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask; +assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en; +assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata; +assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid; +assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address; +assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank; +assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n; +assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n; +assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n; +assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n; +assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke; +assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt; +assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n; +assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n; +assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata; +assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en; +assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask; +assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en; +assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata; +assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid; +assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address; +assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank; +assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n; +assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n; +assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n; +assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n; +assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke; +assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt; +assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n; +assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n; +assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata; +assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en; +assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask; +assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en; +assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata; +assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; // synthesis translate_off -reg dummy_d_35; +reg dummy_d_22; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_bank <= 3'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_bank <= soc_sdram_slave_p0_bank; + litedramcore_master_p3_cke <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; end else begin - soc_sdram_master_p0_bank <= soc_sdram_inti_p0_bank; + litedramcore_master_p3_cke <= litedramcore_inti_p3_cke; end // synthesis translate_off - dummy_d_35 = dummy_s; + dummy_d_22 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_36; +reg dummy_d_23; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_cas_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_cas_n <= soc_sdram_slave_p0_cas_n; + litedramcore_master_p3_odt <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; end else begin - soc_sdram_master_p0_cas_n <= soc_sdram_inti_p0_cas_n; + litedramcore_master_p3_odt <= litedramcore_inti_p3_odt; end // synthesis translate_off - dummy_d_36 = dummy_s; + dummy_d_23 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_37; +reg dummy_d_24; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_cs_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_cs_n <= soc_sdram_slave_p0_cs_n; + litedramcore_master_p3_reset_n <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; end else begin - soc_sdram_master_p0_cs_n <= soc_sdram_inti_p0_cs_n; + litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n; end // synthesis translate_off - dummy_d_37 = dummy_s; + dummy_d_24 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_38; +reg dummy_d_25; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_ras_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_ras_n <= soc_sdram_slave_p0_ras_n; + litedramcore_master_p3_act_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; end else begin - soc_sdram_master_p0_ras_n <= soc_sdram_inti_p0_ras_n; + litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n; end // synthesis translate_off - dummy_d_38 = dummy_s; + dummy_d_25 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_39; +reg dummy_d_26; // synthesis translate_on always @(*) begin - soc_sdram_slave_p0_rddata <= 32'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_slave_p0_rddata <= soc_sdram_master_p0_rddata; + litedramcore_master_p3_wrdata <= 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; end else begin + litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata; end // synthesis translate_off - dummy_d_39 = dummy_s; + dummy_d_26 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_40; +reg dummy_d_27; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_we_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_we_n <= soc_sdram_slave_p0_we_n; + litedramcore_inti_p0_rddata <= 32'd0; + if (litedramcore_storage[0]) begin end else begin - soc_sdram_master_p0_we_n <= soc_sdram_inti_p0_we_n; + litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata; end // synthesis translate_off - dummy_d_40 = dummy_s; + dummy_d_27 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_41; +reg dummy_d_28; // synthesis translate_on always @(*) begin - soc_sdram_slave_p0_rddata_valid <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_slave_p0_rddata_valid <= soc_sdram_master_p0_rddata_valid; + litedramcore_master_p3_wrdata_en <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; end else begin + litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en; end // synthesis translate_off - dummy_d_41 = dummy_s; + dummy_d_28 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_42; +reg dummy_d_29; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_cke <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_cke <= soc_sdram_slave_p0_cke; + litedramcore_inti_p0_rddata_valid <= 1'd0; + if (litedramcore_storage[0]) begin end else begin - soc_sdram_master_p0_cke <= soc_sdram_inti_p0_cke; + litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end // synthesis translate_off - dummy_d_42 = dummy_s; + dummy_d_29 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_43; +reg dummy_d_30; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_odt <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_odt <= soc_sdram_slave_p0_odt; + litedramcore_master_p3_wrdata_mask <= 4'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; end else begin - soc_sdram_master_p0_odt <= soc_sdram_inti_p0_odt; + litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask; end // synthesis translate_off - dummy_d_43 = dummy_s; + dummy_d_30 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_44; +reg dummy_d_31; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_reset_n <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_reset_n <= soc_sdram_slave_p0_reset_n; + litedramcore_master_p3_rddata_en <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; end else begin - soc_sdram_master_p0_reset_n <= soc_sdram_inti_p0_reset_n; + litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en; end // synthesis translate_off - dummy_d_44 = dummy_s; + dummy_d_31 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_32; +// synthesis translate_on +always @(*) begin + litedramcore_master_p0_address <= 14'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_address <= litedramcore_slave_p0_address; + end else begin + litedramcore_master_p0_address <= litedramcore_inti_p0_address; + end +// synthesis translate_off + dummy_d_32 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_33; +// synthesis translate_on +always @(*) begin + litedramcore_master_p0_bank <= 3'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; + end else begin + litedramcore_master_p0_bank <= litedramcore_inti_p0_bank; + end +// synthesis translate_off + dummy_d_33 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_34; +// synthesis translate_on +always @(*) begin + litedramcore_master_p0_cas_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; + end else begin + litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n; + end +// synthesis translate_off + dummy_d_34 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_35; +// synthesis translate_on +always @(*) begin + litedramcore_master_p0_cs_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + end else begin + litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n; + end +// synthesis translate_off + dummy_d_35 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_36; +// synthesis translate_on +always @(*) begin + litedramcore_slave_p0_rddata <= 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; + end else begin + end +// synthesis translate_off + dummy_d_36 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_37; +// synthesis translate_on +always @(*) begin + litedramcore_master_p0_ras_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + end else begin + litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n; + end +// synthesis translate_off + dummy_d_37 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_38; +// synthesis translate_on +always @(*) begin + litedramcore_slave_p0_rddata_valid <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end else begin + end +// synthesis translate_off + dummy_d_38 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_39; +// synthesis translate_on +always @(*) begin + litedramcore_master_p0_we_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + end else begin + litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; + end +// synthesis translate_off + dummy_d_39 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_40; +// synthesis translate_on +always @(*) begin + litedramcore_master_p0_cke <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; + end else begin + litedramcore_master_p0_cke <= litedramcore_inti_p0_cke; + end +// synthesis translate_off + dummy_d_40 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_41; +// synthesis translate_on +always @(*) begin + litedramcore_master_p0_odt <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; + end else begin + litedramcore_master_p0_odt <= litedramcore_inti_p0_odt; + end +// synthesis translate_off + dummy_d_41 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_42; +// synthesis translate_on +always @(*) begin + litedramcore_master_p0_reset_n <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; + end else begin + litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n; + end +// synthesis translate_off + dummy_d_42 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_43; +// synthesis translate_on +always @(*) begin + litedramcore_master_p0_act_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; + end else begin + litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n; + end +// synthesis translate_off + dummy_d_43 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_44; +// synthesis translate_on +always @(*) begin + litedramcore_master_p0_wrdata <= 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; + end else begin + litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata; + end +// synthesis translate_off + dummy_d_44 = dummy_s; // synthesis translate_on end @@ -3865,11 +3189,10 @@ end reg dummy_d_45; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_act_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_act_n <= soc_sdram_slave_p0_act_n; + litedramcore_inti_p1_rddata <= 32'd0; + if (litedramcore_storage[0]) begin end else begin - soc_sdram_master_p0_act_n <= soc_sdram_inti_p0_act_n; + litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata; end // synthesis translate_off dummy_d_45 = dummy_s; @@ -3880,11 +3203,11 @@ end reg dummy_d_46; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_wrdata <= 32'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_wrdata <= soc_sdram_slave_p0_wrdata; + litedramcore_master_p0_wrdata_en <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; end else begin - soc_sdram_master_p0_wrdata <= soc_sdram_inti_p0_wrdata; + litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en; end // synthesis translate_off dummy_d_46 = dummy_s; @@ -3895,10 +3218,10 @@ end reg dummy_d_47; // synthesis translate_on always @(*) begin - soc_sdram_inti_p1_rddata <= 32'd0; - if (soc_sdram_storage[0]) begin + litedramcore_inti_p1_rddata_valid <= 1'd0; + if (litedramcore_storage[0]) begin end else begin - soc_sdram_inti_p1_rddata <= soc_sdram_master_p1_rddata; + litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end // synthesis translate_off dummy_d_47 = dummy_s; @@ -3909,11 +3232,11 @@ end reg dummy_d_48; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_wrdata_en <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_wrdata_en <= soc_sdram_slave_p0_wrdata_en; + litedramcore_master_p0_wrdata_mask <= 4'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; end else begin - soc_sdram_master_p0_wrdata_en <= soc_sdram_inti_p0_wrdata_en; + litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask; end // synthesis translate_off dummy_d_48 = dummy_s; @@ -3924,10 +3247,11 @@ end reg dummy_d_49; // synthesis translate_on always @(*) begin - soc_sdram_inti_p1_rddata_valid <= 1'd0; - if (soc_sdram_storage[0]) begin + litedramcore_master_p0_rddata_en <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; end else begin - soc_sdram_inti_p1_rddata_valid <= soc_sdram_master_p1_rddata_valid; + litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en; end // synthesis translate_off dummy_d_49 = dummy_s; @@ -3938,11 +3262,11 @@ end reg dummy_d_50; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_wrdata_mask <= 4'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_wrdata_mask <= soc_sdram_slave_p0_wrdata_mask; + litedramcore_master_p1_address <= 14'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_address <= litedramcore_slave_p1_address; end else begin - soc_sdram_master_p0_wrdata_mask <= soc_sdram_inti_p0_wrdata_mask; + litedramcore_master_p1_address <= litedramcore_inti_p1_address; end // synthesis translate_off dummy_d_50 = dummy_s; @@ -3953,11 +3277,11 @@ end reg dummy_d_51; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_rddata_en <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_rddata_en <= soc_sdram_slave_p0_rddata_en; + litedramcore_master_p1_bank <= 3'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; end else begin - soc_sdram_master_p0_rddata_en <= soc_sdram_inti_p0_rddata_en; + litedramcore_master_p1_bank <= litedramcore_inti_p1_bank; end // synthesis translate_off dummy_d_51 = dummy_s; @@ -3968,11 +3292,11 @@ end reg dummy_d_52; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_address <= 14'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_address <= soc_sdram_slave_p1_address; + litedramcore_master_p1_cas_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; end else begin - soc_sdram_master_p1_address <= soc_sdram_inti_p1_address; + litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n; end // synthesis translate_off dummy_d_52 = dummy_s; @@ -3983,11 +3307,11 @@ end reg dummy_d_53; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_bank <= 3'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_bank <= soc_sdram_slave_p1_bank; + litedramcore_master_p1_cs_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; end else begin - soc_sdram_master_p1_bank <= soc_sdram_inti_p1_bank; + litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n; end // synthesis translate_off dummy_d_53 = dummy_s; @@ -3998,11 +3322,11 @@ end reg dummy_d_54; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_cas_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_cas_n <= soc_sdram_slave_p1_cas_n; + litedramcore_master_p1_ras_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; end else begin - soc_sdram_master_p1_cas_n <= soc_sdram_inti_p1_cas_n; + litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n; end // synthesis translate_off dummy_d_54 = dummy_s; @@ -4013,11 +3337,10 @@ end reg dummy_d_55; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_cs_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_cs_n <= soc_sdram_slave_p1_cs_n; + litedramcore_slave_p1_rddata <= 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; end else begin - soc_sdram_master_p1_cs_n <= soc_sdram_inti_p1_cs_n; end // synthesis translate_off dummy_d_55 = dummy_s; @@ -4028,11 +3351,11 @@ end reg dummy_d_56; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_ras_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_ras_n <= soc_sdram_slave_p1_ras_n; + litedramcore_master_p1_we_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; end else begin - soc_sdram_master_p1_ras_n <= soc_sdram_inti_p1_ras_n; + litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n; end // synthesis translate_off dummy_d_56 = dummy_s; @@ -4043,9 +3366,9 @@ end reg dummy_d_57; // synthesis translate_on always @(*) begin - soc_sdram_slave_p1_rddata <= 32'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_slave_p1_rddata <= soc_sdram_master_p1_rddata; + litedramcore_slave_p1_rddata_valid <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end else begin end // synthesis translate_off @@ -4057,11 +3380,11 @@ end reg dummy_d_58; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_we_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_we_n <= soc_sdram_slave_p1_we_n; + litedramcore_master_p1_cke <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; end else begin - soc_sdram_master_p1_we_n <= soc_sdram_inti_p1_we_n; + litedramcore_master_p1_cke <= litedramcore_inti_p1_cke; end // synthesis translate_off dummy_d_58 = dummy_s; @@ -4072,10 +3395,11 @@ end reg dummy_d_59; // synthesis translate_on always @(*) begin - soc_sdram_slave_p1_rddata_valid <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_slave_p1_rddata_valid <= soc_sdram_master_p1_rddata_valid; + litedramcore_master_p1_odt <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; end else begin + litedramcore_master_p1_odt <= litedramcore_inti_p1_odt; end // synthesis translate_off dummy_d_59 = dummy_s; @@ -4086,11 +3410,11 @@ end reg dummy_d_60; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_cke <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_cke <= soc_sdram_slave_p1_cke; + litedramcore_master_p1_reset_n <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; end else begin - soc_sdram_master_p1_cke <= soc_sdram_inti_p1_cke; + litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; end // synthesis translate_off dummy_d_60 = dummy_s; @@ -4101,11 +3425,11 @@ end reg dummy_d_61; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_odt <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_odt <= soc_sdram_slave_p1_odt; + litedramcore_master_p1_act_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; end else begin - soc_sdram_master_p1_odt <= soc_sdram_inti_p1_odt; + litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n; end // synthesis translate_off dummy_d_61 = dummy_s; @@ -4116,11 +3440,11 @@ end reg dummy_d_62; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_reset_n <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_reset_n <= soc_sdram_slave_p1_reset_n; + litedramcore_master_p1_wrdata <= 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; end else begin - soc_sdram_master_p1_reset_n <= soc_sdram_inti_p1_reset_n; + litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata; end // synthesis translate_off dummy_d_62 = dummy_s; @@ -4131,11 +3455,10 @@ end reg dummy_d_63; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_act_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_act_n <= soc_sdram_slave_p1_act_n; + litedramcore_inti_p2_rddata <= 32'd0; + if (litedramcore_storage[0]) begin end else begin - soc_sdram_master_p1_act_n <= soc_sdram_inti_p1_act_n; + litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; end // synthesis translate_off dummy_d_63 = dummy_s; @@ -4146,11 +3469,11 @@ end reg dummy_d_64; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_wrdata <= 32'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_wrdata <= soc_sdram_slave_p1_wrdata; + litedramcore_master_p1_wrdata_en <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; end else begin - soc_sdram_master_p1_wrdata <= soc_sdram_inti_p1_wrdata; + litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; end // synthesis translate_off dummy_d_64 = dummy_s; @@ -4161,10 +3484,10 @@ end reg dummy_d_65; // synthesis translate_on always @(*) begin - soc_sdram_inti_p2_rddata <= 32'd0; - if (soc_sdram_storage[0]) begin + litedramcore_inti_p2_rddata_valid <= 1'd0; + if (litedramcore_storage[0]) begin end else begin - soc_sdram_inti_p2_rddata <= soc_sdram_master_p2_rddata; + litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end // synthesis translate_off dummy_d_65 = dummy_s; @@ -4175,11 +3498,11 @@ end reg dummy_d_66; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_wrdata_en <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_wrdata_en <= soc_sdram_slave_p1_wrdata_en; + litedramcore_master_p1_wrdata_mask <= 4'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; end else begin - soc_sdram_master_p1_wrdata_en <= soc_sdram_inti_p1_wrdata_en; + litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; end // synthesis translate_off dummy_d_66 = dummy_s; @@ -4190,10 +3513,11 @@ end reg dummy_d_67; // synthesis translate_on always @(*) begin - soc_sdram_inti_p2_rddata_valid <= 1'd0; - if (soc_sdram_storage[0]) begin + litedramcore_master_p1_rddata_en <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; end else begin - soc_sdram_inti_p2_rddata_valid <= soc_sdram_master_p2_rddata_valid; + litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; end // synthesis translate_off dummy_d_67 = dummy_s; @@ -4204,11 +3528,10 @@ end reg dummy_d_68; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_wrdata_mask <= 4'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_wrdata_mask <= soc_sdram_slave_p1_wrdata_mask; + litedramcore_slave_p3_rddata <= 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; end else begin - soc_sdram_master_p1_wrdata_mask <= soc_sdram_inti_p1_wrdata_mask; end // synthesis translate_off dummy_d_68 = dummy_s; @@ -4219,11 +3542,11 @@ end reg dummy_d_69; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_rddata_en <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_rddata_en <= soc_sdram_slave_p1_rddata_en; + litedramcore_master_p2_address <= 14'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_address <= litedramcore_slave_p2_address; end else begin - soc_sdram_master_p1_rddata_en <= soc_sdram_inti_p1_rddata_en; + litedramcore_master_p2_address <= litedramcore_inti_p2_address; end // synthesis translate_off dummy_d_69 = dummy_s; @@ -4234,11 +3557,11 @@ end reg dummy_d_70; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_address <= 14'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_address <= soc_sdram_slave_p2_address; + litedramcore_master_p2_bank <= 3'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; end else begin - soc_sdram_master_p2_address <= soc_sdram_inti_p2_address; + litedramcore_master_p2_bank <= litedramcore_inti_p2_bank; end // synthesis translate_off dummy_d_70 = dummy_s; @@ -4249,11 +3572,11 @@ end reg dummy_d_71; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_bank <= 3'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_bank <= soc_sdram_slave_p2_bank; + litedramcore_master_p2_cas_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; end else begin - soc_sdram_master_p2_bank <= soc_sdram_inti_p2_bank; + litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n; end // synthesis translate_off dummy_d_71 = dummy_s; @@ -4264,11 +3587,11 @@ end reg dummy_d_72; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_cas_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_cas_n <= soc_sdram_slave_p2_cas_n; + litedramcore_master_p2_cs_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; end else begin - soc_sdram_master_p2_cas_n <= soc_sdram_inti_p2_cas_n; + litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n; end // synthesis translate_off dummy_d_72 = dummy_s; @@ -4279,11 +3602,10 @@ end reg dummy_d_73; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_cs_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_cs_n <= soc_sdram_slave_p2_cs_n; + litedramcore_slave_p3_rddata_valid <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end else begin - soc_sdram_master_p2_cs_n <= soc_sdram_inti_p2_cs_n; end // synthesis translate_off dummy_d_73 = dummy_s; @@ -4294,11 +3616,11 @@ end reg dummy_d_74; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_ras_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_ras_n <= soc_sdram_slave_p2_ras_n; + litedramcore_master_p2_ras_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; end else begin - soc_sdram_master_p2_ras_n <= soc_sdram_inti_p2_ras_n; + litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n; end // synthesis translate_off dummy_d_74 = dummy_s; @@ -4309,9 +3631,9 @@ end reg dummy_d_75; // synthesis translate_on always @(*) begin - soc_sdram_slave_p2_rddata <= 32'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_slave_p2_rddata <= soc_sdram_master_p2_rddata; + litedramcore_slave_p2_rddata <= 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; end else begin end // synthesis translate_off @@ -4323,11 +3645,11 @@ end reg dummy_d_76; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_we_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_we_n <= soc_sdram_slave_p2_we_n; + litedramcore_master_p2_we_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; end else begin - soc_sdram_master_p2_we_n <= soc_sdram_inti_p2_we_n; + litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; end // synthesis translate_off dummy_d_76 = dummy_s; @@ -4338,9 +3660,9 @@ end reg dummy_d_77; // synthesis translate_on always @(*) begin - soc_sdram_slave_p2_rddata_valid <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_slave_p2_rddata_valid <= soc_sdram_master_p2_rddata_valid; + litedramcore_slave_p2_rddata_valid <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end else begin end // synthesis translate_off @@ -4352,11 +3674,11 @@ end reg dummy_d_78; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_cke <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_cke <= soc_sdram_slave_p2_cke; + litedramcore_master_p2_cke <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; end else begin - soc_sdram_master_p2_cke <= soc_sdram_inti_p2_cke; + litedramcore_master_p2_cke <= litedramcore_inti_p2_cke; end // synthesis translate_off dummy_d_78 = dummy_s; @@ -4367,11 +3689,11 @@ end reg dummy_d_79; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_odt <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_odt <= soc_sdram_slave_p2_odt; + litedramcore_master_p2_odt <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; end else begin - soc_sdram_master_p2_odt <= soc_sdram_inti_p2_odt; + litedramcore_master_p2_odt <= litedramcore_inti_p2_odt; end // synthesis translate_off dummy_d_79 = dummy_s; @@ -4382,11 +3704,11 @@ end reg dummy_d_80; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_reset_n <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_reset_n <= soc_sdram_slave_p2_reset_n; + litedramcore_master_p2_reset_n <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; end else begin - soc_sdram_master_p2_reset_n <= soc_sdram_inti_p2_reset_n; + litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n; end // synthesis translate_off dummy_d_80 = dummy_s; @@ -4397,11 +3719,11 @@ end reg dummy_d_81; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_act_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_act_n <= soc_sdram_slave_p2_act_n; + litedramcore_master_p2_act_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; end else begin - soc_sdram_master_p2_act_n <= soc_sdram_inti_p2_act_n; + litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n; end // synthesis translate_off dummy_d_81 = dummy_s; @@ -4412,11 +3734,11 @@ end reg dummy_d_82; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_wrdata <= 32'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_wrdata <= soc_sdram_slave_p2_wrdata; + litedramcore_master_p2_wrdata <= 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; end else begin - soc_sdram_master_p2_wrdata <= soc_sdram_inti_p2_wrdata; + litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata; end // synthesis translate_off dummy_d_82 = dummy_s; @@ -4427,10 +3749,10 @@ end reg dummy_d_83; // synthesis translate_on always @(*) begin - soc_sdram_inti_p3_rddata <= 32'd0; - if (soc_sdram_storage[0]) begin + litedramcore_inti_p3_rddata <= 32'd0; + if (litedramcore_storage[0]) begin end else begin - soc_sdram_inti_p3_rddata <= soc_sdram_master_p3_rddata; + litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata; end // synthesis translate_off dummy_d_83 = dummy_s; @@ -4441,11 +3763,11 @@ end reg dummy_d_84; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_wrdata_en <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_wrdata_en <= soc_sdram_slave_p2_wrdata_en; + litedramcore_master_p2_wrdata_en <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; end else begin - soc_sdram_master_p2_wrdata_en <= soc_sdram_inti_p2_wrdata_en; + litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en; end // synthesis translate_off dummy_d_84 = dummy_s; @@ -4456,10 +3778,10 @@ end reg dummy_d_85; // synthesis translate_on always @(*) begin - soc_sdram_inti_p3_rddata_valid <= 1'd0; - if (soc_sdram_storage[0]) begin + litedramcore_inti_p3_rddata_valid <= 1'd0; + if (litedramcore_storage[0]) begin end else begin - soc_sdram_inti_p3_rddata_valid <= soc_sdram_master_p3_rddata_valid; + litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end // synthesis translate_off dummy_d_85 = dummy_s; @@ -4470,11 +3792,11 @@ end reg dummy_d_86; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_wrdata_mask <= 4'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_wrdata_mask <= soc_sdram_slave_p2_wrdata_mask; + litedramcore_master_p2_wrdata_mask <= 4'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; end else begin - soc_sdram_master_p2_wrdata_mask <= soc_sdram_inti_p2_wrdata_mask; + litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask; end // synthesis translate_off dummy_d_86 = dummy_s; @@ -4485,11 +3807,11 @@ end reg dummy_d_87; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_rddata_en <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_rddata_en <= soc_sdram_slave_p2_rddata_en; + litedramcore_master_p2_rddata_en <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; end else begin - soc_sdram_master_p2_rddata_en <= soc_sdram_inti_p2_rddata_en; + litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en; end // synthesis translate_off dummy_d_87 = dummy_s; @@ -4500,11 +3822,11 @@ end reg dummy_d_88; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_address <= 14'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_address <= soc_sdram_slave_p3_address; + litedramcore_master_p3_address <= 14'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_address <= litedramcore_slave_p3_address; end else begin - soc_sdram_master_p3_address <= soc_sdram_inti_p3_address; + litedramcore_master_p3_address <= litedramcore_inti_p3_address; end // synthesis translate_off dummy_d_88 = dummy_s; @@ -4515,11 +3837,11 @@ end reg dummy_d_89; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_bank <= 3'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_bank <= soc_sdram_slave_p3_bank; + litedramcore_master_p3_bank <= 3'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; end else begin - soc_sdram_master_p3_bank <= soc_sdram_inti_p3_bank; + litedramcore_master_p3_bank <= litedramcore_inti_p3_bank; end // synthesis translate_off dummy_d_89 = dummy_s; @@ -4530,11 +3852,11 @@ end reg dummy_d_90; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_cas_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_cas_n <= soc_sdram_slave_p3_cas_n; + litedramcore_master_p3_cas_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; end else begin - soc_sdram_master_p3_cas_n <= soc_sdram_inti_p3_cas_n; + litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n; end // synthesis translate_off dummy_d_90 = dummy_s; @@ -4545,11 +3867,11 @@ end reg dummy_d_91; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_cs_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_cs_n <= soc_sdram_slave_p3_cs_n; + litedramcore_master_p3_cs_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; end else begin - soc_sdram_master_p3_cs_n <= soc_sdram_inti_p3_cs_n; + litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n; end // synthesis translate_off dummy_d_91 = dummy_s; @@ -4560,11 +3882,11 @@ end reg dummy_d_92; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_ras_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_ras_n <= soc_sdram_slave_p3_ras_n; + litedramcore_master_p3_ras_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; end else begin - soc_sdram_master_p3_ras_n <= soc_sdram_inti_p3_ras_n; + litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n; end // synthesis translate_off dummy_d_92 = dummy_s; @@ -4575,25 +3897,38 @@ end reg dummy_d_93; // synthesis translate_on always @(*) begin - soc_sdram_slave_p3_rddata <= 32'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_slave_p3_rddata <= soc_sdram_master_p3_rddata; + litedramcore_master_p3_we_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; end else begin + litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n; end // synthesis translate_off dummy_d_93 = dummy_s; // synthesis translate_on end +assign litedramcore_inti_p0_cke = litedramcore_storage[1]; +assign litedramcore_inti_p1_cke = litedramcore_storage[1]; +assign litedramcore_inti_p2_cke = litedramcore_storage[1]; +assign litedramcore_inti_p3_cke = litedramcore_storage[1]; +assign litedramcore_inti_p0_odt = litedramcore_storage[2]; +assign litedramcore_inti_p1_odt = litedramcore_storage[2]; +assign litedramcore_inti_p2_odt = litedramcore_storage[2]; +assign litedramcore_inti_p3_odt = litedramcore_storage[2]; +assign litedramcore_inti_p0_reset_n = litedramcore_storage[3]; +assign litedramcore_inti_p1_reset_n = litedramcore_storage[3]; +assign litedramcore_inti_p2_reset_n = litedramcore_storage[3]; +assign litedramcore_inti_p3_reset_n = litedramcore_storage[3]; // synthesis translate_off reg dummy_d_94; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_we_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_we_n <= soc_sdram_slave_p3_we_n; + litedramcore_inti_p0_cas_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]); end else begin - soc_sdram_master_p3_we_n <= soc_sdram_inti_p3_we_n; + litedramcore_inti_p0_cas_n <= 1'd1; end // synthesis translate_off dummy_d_94 = dummy_s; @@ -4604,10 +3939,11 @@ end reg dummy_d_95; // synthesis translate_on always @(*) begin - soc_sdram_slave_p3_rddata_valid <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_slave_p3_rddata_valid <= soc_sdram_master_p3_rddata_valid; + litedramcore_inti_p0_cs_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}}; end else begin + litedramcore_inti_p0_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_95 = dummy_s; @@ -4618,11 +3954,11 @@ end reg dummy_d_96; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_cke <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_cke <= soc_sdram_slave_p3_cke; + litedramcore_inti_p0_ras_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]); end else begin - soc_sdram_master_p3_cke <= soc_sdram_inti_p3_cke; + litedramcore_inti_p0_ras_n <= 1'd1; end // synthesis translate_off dummy_d_96 = dummy_s; @@ -4633,26 +3969,32 @@ end reg dummy_d_97; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_odt <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_odt <= soc_sdram_slave_p3_odt; + litedramcore_inti_p0_we_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]); end else begin - soc_sdram_master_p3_odt <= soc_sdram_inti_p3_odt; + litedramcore_inti_p0_we_n <= 1'd1; end // synthesis translate_off dummy_d_97 = dummy_s; // synthesis translate_on end +assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage; +assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage; +assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]); +assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]); +assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; +assign litedramcore_inti_p0_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_98; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_reset_n <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_reset_n <= soc_sdram_slave_p3_reset_n; + litedramcore_inti_p1_cas_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]); end else begin - soc_sdram_master_p3_reset_n <= soc_sdram_inti_p3_reset_n; + litedramcore_inti_p1_cas_n <= 1'd1; end // synthesis translate_off dummy_d_98 = dummy_s; @@ -4663,11 +4005,11 @@ end reg dummy_d_99; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_act_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_act_n <= soc_sdram_slave_p3_act_n; + litedramcore_inti_p1_cs_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}}; end else begin - soc_sdram_master_p3_act_n <= soc_sdram_inti_p3_act_n; + litedramcore_inti_p1_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_99 = dummy_s; @@ -4678,11 +4020,11 @@ end reg dummy_d_100; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_wrdata <= 32'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_wrdata <= soc_sdram_slave_p3_wrdata; + litedramcore_inti_p1_ras_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]); end else begin - soc_sdram_master_p3_wrdata <= soc_sdram_inti_p3_wrdata; + litedramcore_inti_p1_ras_n <= 1'd1; end // synthesis translate_off dummy_d_100 = dummy_s; @@ -4693,25 +4035,32 @@ end reg dummy_d_101; // synthesis translate_on always @(*) begin - soc_sdram_inti_p0_rddata <= 32'd0; - if (soc_sdram_storage[0]) begin + litedramcore_inti_p1_we_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]); end else begin - soc_sdram_inti_p0_rddata <= soc_sdram_master_p0_rddata; + litedramcore_inti_p1_we_n <= 1'd1; end // synthesis translate_off dummy_d_101 = dummy_s; // synthesis translate_on end +assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage; +assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage; +assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]); +assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]); +assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; +assign litedramcore_inti_p1_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_102; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_wrdata_en <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_wrdata_en <= soc_sdram_slave_p3_wrdata_en; + litedramcore_inti_p2_cas_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_inti_p2_cas_n <= (~litedramcore_phaseinjector2_command_storage[2]); end else begin - soc_sdram_master_p3_wrdata_en <= soc_sdram_inti_p3_wrdata_en; + litedramcore_inti_p2_cas_n <= 1'd1; end // synthesis translate_off dummy_d_102 = dummy_s; @@ -4722,10 +4071,11 @@ end reg dummy_d_103; // synthesis translate_on always @(*) begin - soc_sdram_inti_p0_rddata_valid <= 1'd0; - if (soc_sdram_storage[0]) begin + litedramcore_inti_p2_cs_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}}; end else begin - soc_sdram_inti_p0_rddata_valid <= soc_sdram_master_p0_rddata_valid; + litedramcore_inti_p2_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_103 = dummy_s; @@ -4736,11 +4086,11 @@ end reg dummy_d_104; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_wrdata_mask <= 4'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_wrdata_mask <= soc_sdram_slave_p3_wrdata_mask; + litedramcore_inti_p2_ras_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_inti_p2_ras_n <= (~litedramcore_phaseinjector2_command_storage[3]); end else begin - soc_sdram_master_p3_wrdata_mask <= soc_sdram_inti_p3_wrdata_mask; + litedramcore_inti_p2_ras_n <= 1'd1; end // synthesis translate_off dummy_d_104 = dummy_s; @@ -4751,53 +4101,47 @@ end reg dummy_d_105; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_rddata_en <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_rddata_en <= soc_sdram_slave_p3_rddata_en; + litedramcore_inti_p2_we_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_inti_p2_we_n <= (~litedramcore_phaseinjector2_command_storage[1]); end else begin - soc_sdram_master_p3_rddata_en <= soc_sdram_inti_p3_rddata_en; + litedramcore_inti_p2_we_n <= 1'd1; end // synthesis translate_off dummy_d_105 = dummy_s; // synthesis translate_on end +assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage; +assign litedramcore_inti_p2_bank = litedramcore_phaseinjector2_baddress_storage; +assign litedramcore_inti_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[4]); +assign litedramcore_inti_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[5]); +assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; +assign litedramcore_inti_p2_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_106; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_address <= 14'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_address <= soc_sdram_slave_p0_address; + litedramcore_inti_p3_cas_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_inti_p3_cas_n <= (~litedramcore_phaseinjector3_command_storage[2]); end else begin - soc_sdram_master_p0_address <= soc_sdram_inti_p0_address; + litedramcore_inti_p3_cas_n <= 1'd1; end // synthesis translate_off dummy_d_106 = dummy_s; // synthesis translate_on end -assign soc_sdram_inti_p0_cke = soc_sdram_storage[1]; -assign soc_sdram_inti_p1_cke = soc_sdram_storage[1]; -assign soc_sdram_inti_p2_cke = soc_sdram_storage[1]; -assign soc_sdram_inti_p3_cke = soc_sdram_storage[1]; -assign soc_sdram_inti_p0_odt = soc_sdram_storage[2]; -assign soc_sdram_inti_p1_odt = soc_sdram_storage[2]; -assign soc_sdram_inti_p2_odt = soc_sdram_storage[2]; -assign soc_sdram_inti_p3_odt = soc_sdram_storage[2]; -assign soc_sdram_inti_p0_reset_n = soc_sdram_storage[3]; -assign soc_sdram_inti_p1_reset_n = soc_sdram_storage[3]; -assign soc_sdram_inti_p2_reset_n = soc_sdram_storage[3]; -assign soc_sdram_inti_p3_reset_n = soc_sdram_storage[3]; // synthesis translate_off reg dummy_d_107; // synthesis translate_on always @(*) begin - soc_sdram_inti_p0_we_n <= 1'd1; - if (soc_sdram_phaseinjector0_command_issue_re) begin - soc_sdram_inti_p0_we_n <= (~soc_sdram_phaseinjector0_command_storage[1]); + litedramcore_inti_p3_cs_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}}; end else begin - soc_sdram_inti_p0_we_n <= 1'd1; + litedramcore_inti_p3_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_107 = dummy_s; @@ -4808,11 +4152,11 @@ end reg dummy_d_108; // synthesis translate_on always @(*) begin - soc_sdram_inti_p0_cas_n <= 1'd1; - if (soc_sdram_phaseinjector0_command_issue_re) begin - soc_sdram_inti_p0_cas_n <= (~soc_sdram_phaseinjector0_command_storage[2]); + litedramcore_inti_p3_ras_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_inti_p3_ras_n <= (~litedramcore_phaseinjector3_command_storage[3]); end else begin - soc_sdram_inti_p0_cas_n <= 1'd1; + litedramcore_inti_p3_ras_n <= 1'd1; end // synthesis translate_off dummy_d_108 = dummy_s; @@ -4823,48 +4167,158 @@ end reg dummy_d_109; // synthesis translate_on always @(*) begin - soc_sdram_inti_p0_cs_n <= 1'd1; - if (soc_sdram_phaseinjector0_command_issue_re) begin - soc_sdram_inti_p0_cs_n <= {1{(~soc_sdram_phaseinjector0_command_storage[0])}}; + litedramcore_inti_p3_we_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_inti_p3_we_n <= (~litedramcore_phaseinjector3_command_storage[1]); end else begin - soc_sdram_inti_p0_cs_n <= {1{1'd1}}; + litedramcore_inti_p3_we_n <= 1'd1; end // synthesis translate_off dummy_d_109 = dummy_s; // synthesis translate_on end +assign litedramcore_inti_p3_address = litedramcore_phaseinjector3_address_storage; +assign litedramcore_inti_p3_bank = litedramcore_phaseinjector3_baddress_storage; +assign litedramcore_inti_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[4]); +assign litedramcore_inti_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[5]); +assign litedramcore_inti_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage; +assign litedramcore_inti_p3_wrdata_mask = 1'd0; +assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid; +assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready; +assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we; +assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr; +assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock; +assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready; +assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid; +assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid; +assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready; +assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we; +assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr; +assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock; +assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready; +assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid; +assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid; +assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready; +assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we; +assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr; +assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock; +assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready; +assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid; +assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid; +assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready; +assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we; +assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr; +assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock; +assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready; +assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid; +assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid; +assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready; +assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we; +assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr; +assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock; +assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready; +assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid; +assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid; +assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready; +assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we; +assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr; +assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock; +assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready; +assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid; +assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid; +assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready; +assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we; +assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr; +assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock; +assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready; +assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid; +assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid; +assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready; +assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we; +assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr; +assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock; +assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready; +assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid; +assign litedramcore_timer_wait = (~litedramcore_timer_done0); +assign litedramcore_postponer_req_i = litedramcore_timer_done0; +assign litedramcore_wants_refresh = litedramcore_postponer_req_o; +assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0; +assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done); +assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0); +assign litedramcore_timer_done0 = litedramcore_timer_done1; +assign litedramcore_timer_count0 = litedramcore_timer_count1; +assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0)); +assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0)); +assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0); +assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; +assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; // synthesis translate_off reg dummy_d_110; // synthesis translate_on always @(*) begin - soc_sdram_inti_p0_ras_n <= 1'd1; - if (soc_sdram_phaseinjector0_command_issue_re) begin - soc_sdram_inti_p0_ras_n <= (~soc_sdram_phaseinjector0_command_storage[3]); - end else begin - soc_sdram_inti_p0_ras_n <= 1'd1; - end + refresher_next_state <= 2'd0; + refresher_next_state <= refresher_state; + case (refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + refresher_next_state <= 2'd2; + end + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + refresher_next_state <= 2'd3; + end else begin + refresher_next_state <= 1'd0; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + refresher_next_state <= 1'd0; + end + end + default: begin + if (1'd1) begin + if (litedramcore_wants_refresh) begin + refresher_next_state <= 1'd1; + end + end + end + endcase // synthesis translate_off dummy_d_110 = dummy_s; // synthesis translate_on end -assign soc_sdram_inti_p0_address = soc_sdram_phaseinjector0_address_storage; -assign soc_sdram_inti_p0_bank = soc_sdram_phaseinjector0_baddress_storage; -assign soc_sdram_inti_p0_wrdata_en = (soc_sdram_phaseinjector0_command_issue_re & soc_sdram_phaseinjector0_command_storage[4]); -assign soc_sdram_inti_p0_rddata_en = (soc_sdram_phaseinjector0_command_issue_re & soc_sdram_phaseinjector0_command_storage[5]); -assign soc_sdram_inti_p0_wrdata = soc_sdram_phaseinjector0_wrdata_storage; -assign soc_sdram_inti_p0_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_111; // synthesis translate_on always @(*) begin - soc_sdram_inti_p1_we_n <= 1'd1; - if (soc_sdram_phaseinjector1_command_issue_re) begin - soc_sdram_inti_p1_we_n <= (~soc_sdram_phaseinjector1_command_storage[1]); - end else begin - soc_sdram_inti_p1_we_n <= 1'd1; - end + litedramcore_cmd_valid <= 1'd0; + case (refresher_state) + 1'd1: begin + litedramcore_cmd_valid <= 1'd1; + end + 2'd2: begin + litedramcore_cmd_valid <= 1'd1; + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_valid <= 1'd0; + end + end + end + 2'd3: begin + litedramcore_cmd_valid <= 1'd1; + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_valid <= 1'd0; + end + end + default: begin + end + endcase // synthesis translate_off dummy_d_111 = dummy_s; // synthesis translate_on @@ -4874,12 +4328,23 @@ end reg dummy_d_112; // synthesis translate_on always @(*) begin - soc_sdram_inti_p1_cas_n <= 1'd1; - if (soc_sdram_phaseinjector1_command_issue_re) begin - soc_sdram_inti_p1_cas_n <= (~soc_sdram_phaseinjector1_command_storage[2]); - end else begin - soc_sdram_inti_p1_cas_n <= 1'd1; - end + litedramcore_zqcs_executer_start <= 1'd0; + case (refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + litedramcore_zqcs_executer_start <= 1'd1; + end else begin + end + end + end + 2'd3: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_112 = dummy_s; // synthesis translate_on @@ -4889,12 +4354,26 @@ end reg dummy_d_113; // synthesis translate_on always @(*) begin - soc_sdram_inti_p1_cs_n <= 1'd1; - if (soc_sdram_phaseinjector1_command_issue_re) begin - soc_sdram_inti_p1_cs_n <= {1{(~soc_sdram_phaseinjector1_command_storage[0])}}; - end else begin - soc_sdram_inti_p1_cs_n <= {1{1'd1}}; - end + litedramcore_cmd_last <= 1'd0; + case (refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_last <= 1'd1; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_last <= 1'd1; + end + end + default: begin + end + endcase // synthesis translate_off dummy_d_113 = dummy_s; // synthesis translate_on @@ -4904,542 +4383,431 @@ end reg dummy_d_114; // synthesis translate_on always @(*) begin - soc_sdram_inti_p1_ras_n <= 1'd1; - if (soc_sdram_phaseinjector1_command_issue_re) begin - soc_sdram_inti_p1_ras_n <= (~soc_sdram_phaseinjector1_command_storage[3]); - end else begin - soc_sdram_inti_p1_ras_n <= 1'd1; - end + litedramcore_sequencer_start0 <= 1'd0; + case (refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_sequencer_start0 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_114 = dummy_s; // synthesis translate_on end -assign soc_sdram_inti_p1_address = soc_sdram_phaseinjector1_address_storage; -assign soc_sdram_inti_p1_bank = soc_sdram_phaseinjector1_baddress_storage; -assign soc_sdram_inti_p1_wrdata_en = (soc_sdram_phaseinjector1_command_issue_re & soc_sdram_phaseinjector1_command_storage[4]); -assign soc_sdram_inti_p1_rddata_en = (soc_sdram_phaseinjector1_command_issue_re & soc_sdram_phaseinjector1_command_storage[5]); -assign soc_sdram_inti_p1_wrdata = soc_sdram_phaseinjector1_wrdata_storage; -assign soc_sdram_inti_p1_wrdata_mask = 1'd0; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid; +assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr; +assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready; +assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); +assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid); +assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]); +assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; // synthesis translate_off reg dummy_d_115; // synthesis translate_on always @(*) begin - soc_sdram_inti_p2_we_n <= 1'd1; - if (soc_sdram_phaseinjector2_command_issue_re) begin - soc_sdram_inti_p2_we_n <= (~soc_sdram_phaseinjector2_command_storage[1]); + litedramcore_bankmachine0_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine0_row_col_n_addr_sel) begin + litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]; end else begin - soc_sdram_inti_p2_we_n <= 1'd1; + litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off dummy_d_115 = dummy_s; // synthesis translate_on end +assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); +assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); +assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); // synthesis translate_off reg dummy_d_116; // synthesis translate_on always @(*) begin - soc_sdram_inti_p2_cas_n <= 1'd1; - if (soc_sdram_phaseinjector2_command_issue_re) begin - soc_sdram_inti_p2_cas_n <= (~soc_sdram_phaseinjector2_command_storage[2]); - end else begin - soc_sdram_inti_p2_cas_n <= 1'd1; + litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin + litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); + end end // synthesis translate_off dummy_d_116 = dummy_s; // synthesis translate_on end +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; // synthesis translate_off reg dummy_d_117; // synthesis translate_on always @(*) begin - soc_sdram_inti_p2_cs_n <= 1'd1; - if (soc_sdram_phaseinjector2_command_issue_re) begin - soc_sdram_inti_p2_cs_n <= {1{(~soc_sdram_phaseinjector2_command_storage[0])}}; + litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_sdram_inti_p2_cs_n <= {1{1'd1}}; + litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce; end // synthesis translate_off dummy_d_117 = dummy_s; // synthesis translate_on end +assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); +assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready); // synthesis translate_off reg dummy_d_118; // synthesis translate_on always @(*) begin - soc_sdram_inti_p2_ras_n <= 1'd1; - if (soc_sdram_phaseinjector2_command_issue_re) begin - soc_sdram_inti_p2_ras_n <= (~soc_sdram_phaseinjector2_command_storage[3]); - end else begin - soc_sdram_inti_p2_ras_n <= 1'd1; - end + bankmachine0_next_state <= 4'd0; + bankmachine0_next_state <= bankmachine0_state; + case (bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + if (litedramcore_bankmachine0_cmd_ready) begin + bankmachine0_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + bankmachine0_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + if (litedramcore_bankmachine0_cmd_ready) begin + bankmachine0_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine0_refresh_req)) begin + bankmachine0_next_state <= 1'd0; + end + end + 3'd5: begin + bankmachine0_next_state <= 3'd6; + end + 3'd6: begin + bankmachine0_next_state <= 2'd3; + end + 3'd7: begin + bankmachine0_next_state <= 4'd8; + end + 4'd8: begin + bankmachine0_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + bankmachine0_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin + bankmachine0_next_state <= 2'd2; + end + end else begin + bankmachine0_next_state <= 1'd1; + end + end else begin + bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase // synthesis translate_off dummy_d_118 = dummy_s; // synthesis translate_on end -assign soc_sdram_inti_p2_address = soc_sdram_phaseinjector2_address_storage; -assign soc_sdram_inti_p2_bank = soc_sdram_phaseinjector2_baddress_storage; -assign soc_sdram_inti_p2_wrdata_en = (soc_sdram_phaseinjector2_command_issue_re & soc_sdram_phaseinjector2_command_storage[4]); -assign soc_sdram_inti_p2_rddata_en = (soc_sdram_phaseinjector2_command_issue_re & soc_sdram_phaseinjector2_command_storage[5]); -assign soc_sdram_inti_p2_wrdata = soc_sdram_phaseinjector2_wrdata_storage; -assign soc_sdram_inti_p2_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_119; // synthesis translate_on always @(*) begin - soc_sdram_inti_p3_we_n <= 1'd1; - if (soc_sdram_phaseinjector3_command_issue_re) begin - soc_sdram_inti_p3_we_n <= (~soc_sdram_phaseinjector3_command_storage[1]); - end else begin - soc_sdram_inti_p3_we_n <= 1'd1; - end -// synthesis translate_off - dummy_d_119 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_120; -// synthesis translate_on -always @(*) begin - soc_sdram_inti_p3_cas_n <= 1'd1; - if (soc_sdram_phaseinjector3_command_issue_re) begin - soc_sdram_inti_p3_cas_n <= (~soc_sdram_phaseinjector3_command_storage[2]); - end else begin - soc_sdram_inti_p3_cas_n <= 1'd1; - end -// synthesis translate_off - dummy_d_120 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_121; -// synthesis translate_on -always @(*) begin - soc_sdram_inti_p3_cs_n <= 1'd1; - if (soc_sdram_phaseinjector3_command_issue_re) begin - soc_sdram_inti_p3_cs_n <= {1{(~soc_sdram_phaseinjector3_command_storage[0])}}; - end else begin - soc_sdram_inti_p3_cs_n <= {1{1'd1}}; - end -// synthesis translate_off - dummy_d_121 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_122; -// synthesis translate_on -always @(*) begin - soc_sdram_inti_p3_ras_n <= 1'd1; - if (soc_sdram_phaseinjector3_command_issue_re) begin - soc_sdram_inti_p3_ras_n <= (~soc_sdram_phaseinjector3_command_storage[3]); - end else begin - soc_sdram_inti_p3_ras_n <= 1'd1; - end -// synthesis translate_off - dummy_d_122 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_inti_p3_address = soc_sdram_phaseinjector3_address_storage; -assign soc_sdram_inti_p3_bank = soc_sdram_phaseinjector3_baddress_storage; -assign soc_sdram_inti_p3_wrdata_en = (soc_sdram_phaseinjector3_command_issue_re & soc_sdram_phaseinjector3_command_storage[4]); -assign soc_sdram_inti_p3_rddata_en = (soc_sdram_phaseinjector3_command_issue_re & soc_sdram_phaseinjector3_command_storage[5]); -assign soc_sdram_inti_p3_wrdata = soc_sdram_phaseinjector3_wrdata_storage; -assign soc_sdram_inti_p3_wrdata_mask = 1'd0; -assign soc_sdram_bankmachine0_req_valid = soc_sdram_interface_bank0_valid; -assign soc_sdram_interface_bank0_ready = soc_sdram_bankmachine0_req_ready; -assign soc_sdram_bankmachine0_req_we = soc_sdram_interface_bank0_we; -assign soc_sdram_bankmachine0_req_addr = soc_sdram_interface_bank0_addr; -assign soc_sdram_interface_bank0_lock = soc_sdram_bankmachine0_req_lock; -assign soc_sdram_interface_bank0_wdata_ready = soc_sdram_bankmachine0_req_wdata_ready; -assign soc_sdram_interface_bank0_rdata_valid = soc_sdram_bankmachine0_req_rdata_valid; -assign soc_sdram_bankmachine1_req_valid = soc_sdram_interface_bank1_valid; -assign soc_sdram_interface_bank1_ready = soc_sdram_bankmachine1_req_ready; -assign soc_sdram_bankmachine1_req_we = soc_sdram_interface_bank1_we; -assign soc_sdram_bankmachine1_req_addr = soc_sdram_interface_bank1_addr; -assign soc_sdram_interface_bank1_lock = soc_sdram_bankmachine1_req_lock; -assign soc_sdram_interface_bank1_wdata_ready = soc_sdram_bankmachine1_req_wdata_ready; -assign soc_sdram_interface_bank1_rdata_valid = soc_sdram_bankmachine1_req_rdata_valid; -assign soc_sdram_bankmachine2_req_valid = soc_sdram_interface_bank2_valid; -assign soc_sdram_interface_bank2_ready = soc_sdram_bankmachine2_req_ready; -assign soc_sdram_bankmachine2_req_we = soc_sdram_interface_bank2_we; -assign soc_sdram_bankmachine2_req_addr = soc_sdram_interface_bank2_addr; -assign soc_sdram_interface_bank2_lock = soc_sdram_bankmachine2_req_lock; -assign soc_sdram_interface_bank2_wdata_ready = soc_sdram_bankmachine2_req_wdata_ready; -assign soc_sdram_interface_bank2_rdata_valid = soc_sdram_bankmachine2_req_rdata_valid; -assign soc_sdram_bankmachine3_req_valid = soc_sdram_interface_bank3_valid; -assign soc_sdram_interface_bank3_ready = soc_sdram_bankmachine3_req_ready; -assign soc_sdram_bankmachine3_req_we = soc_sdram_interface_bank3_we; -assign soc_sdram_bankmachine3_req_addr = soc_sdram_interface_bank3_addr; -assign soc_sdram_interface_bank3_lock = soc_sdram_bankmachine3_req_lock; -assign soc_sdram_interface_bank3_wdata_ready = soc_sdram_bankmachine3_req_wdata_ready; -assign soc_sdram_interface_bank3_rdata_valid = soc_sdram_bankmachine3_req_rdata_valid; -assign soc_sdram_bankmachine4_req_valid = soc_sdram_interface_bank4_valid; -assign soc_sdram_interface_bank4_ready = soc_sdram_bankmachine4_req_ready; -assign soc_sdram_bankmachine4_req_we = soc_sdram_interface_bank4_we; -assign soc_sdram_bankmachine4_req_addr = soc_sdram_interface_bank4_addr; -assign soc_sdram_interface_bank4_lock = soc_sdram_bankmachine4_req_lock; -assign soc_sdram_interface_bank4_wdata_ready = soc_sdram_bankmachine4_req_wdata_ready; -assign soc_sdram_interface_bank4_rdata_valid = soc_sdram_bankmachine4_req_rdata_valid; -assign soc_sdram_bankmachine5_req_valid = soc_sdram_interface_bank5_valid; -assign soc_sdram_interface_bank5_ready = soc_sdram_bankmachine5_req_ready; -assign soc_sdram_bankmachine5_req_we = soc_sdram_interface_bank5_we; -assign soc_sdram_bankmachine5_req_addr = soc_sdram_interface_bank5_addr; -assign soc_sdram_interface_bank5_lock = soc_sdram_bankmachine5_req_lock; -assign soc_sdram_interface_bank5_wdata_ready = soc_sdram_bankmachine5_req_wdata_ready; -assign soc_sdram_interface_bank5_rdata_valid = soc_sdram_bankmachine5_req_rdata_valid; -assign soc_sdram_bankmachine6_req_valid = soc_sdram_interface_bank6_valid; -assign soc_sdram_interface_bank6_ready = soc_sdram_bankmachine6_req_ready; -assign soc_sdram_bankmachine6_req_we = soc_sdram_interface_bank6_we; -assign soc_sdram_bankmachine6_req_addr = soc_sdram_interface_bank6_addr; -assign soc_sdram_interface_bank6_lock = soc_sdram_bankmachine6_req_lock; -assign soc_sdram_interface_bank6_wdata_ready = soc_sdram_bankmachine6_req_wdata_ready; -assign soc_sdram_interface_bank6_rdata_valid = soc_sdram_bankmachine6_req_rdata_valid; -assign soc_sdram_bankmachine7_req_valid = soc_sdram_interface_bank7_valid; -assign soc_sdram_interface_bank7_ready = soc_sdram_bankmachine7_req_ready; -assign soc_sdram_bankmachine7_req_we = soc_sdram_interface_bank7_we; -assign soc_sdram_bankmachine7_req_addr = soc_sdram_interface_bank7_addr; -assign soc_sdram_interface_bank7_lock = soc_sdram_bankmachine7_req_lock; -assign soc_sdram_interface_bank7_wdata_ready = soc_sdram_bankmachine7_req_wdata_ready; -assign soc_sdram_interface_bank7_rdata_valid = soc_sdram_bankmachine7_req_rdata_valid; -assign soc_sdram_timer_wait = (~soc_sdram_timer_done0); -assign soc_sdram_postponer_req_i = soc_sdram_timer_done0; -assign soc_sdram_wants_refresh = soc_sdram_postponer_req_o; -assign soc_sdram_wants_zqcs = soc_sdram_zqcs_timer_done0; -assign soc_sdram_zqcs_timer_wait = (~soc_sdram_zqcs_executer_done); -assign soc_sdram_timer_done1 = (soc_sdram_timer_count1 == 1'd0); -assign soc_sdram_timer_done0 = soc_sdram_timer_done1; -assign soc_sdram_timer_count0 = soc_sdram_timer_count1; -assign soc_sdram_sequencer_start1 = (soc_sdram_sequencer_start0 | (soc_sdram_sequencer_count != 1'd0)); -assign soc_sdram_sequencer_done0 = (soc_sdram_sequencer_done1 & (soc_sdram_sequencer_count == 1'd0)); -assign soc_sdram_zqcs_timer_done1 = (soc_sdram_zqcs_timer_count1 == 1'd0); -assign soc_sdram_zqcs_timer_done0 = soc_sdram_zqcs_timer_done1; -assign soc_sdram_zqcs_timer_count0 = soc_sdram_zqcs_timer_count1; - -// synthesis translate_off -reg dummy_d_123; -// synthesis translate_on -always @(*) begin - vns_refresher_next_state <= 2'd0; - vns_refresher_next_state <= vns_refresher_state; - case (vns_refresher_state) + litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (bankmachine0_state) 1'd1: begin - if (soc_sdram_cmd_ready) begin - vns_refresher_next_state <= 2'd2; - end end 2'd2: begin - if (soc_sdram_sequencer_done0) begin - if (soc_sdram_wants_zqcs) begin - vns_refresher_next_state <= 2'd3; - end else begin - vns_refresher_next_state <= 1'd0; - end - end end 2'd3: begin - if (soc_sdram_zqcs_executer_done) begin - vns_refresher_next_state <= 1'd0; - end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin end default: begin - if (1'd1) begin - if (soc_sdram_wants_refresh) begin - vns_refresher_next_state <= 1'd1; + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end end end end endcase // synthesis translate_off - dummy_d_123 = dummy_s; + dummy_d_119 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_124; +reg dummy_d_120; // synthesis translate_on always @(*) begin - soc_sdram_sequencer_start0 <= 1'd0; - case (vns_refresher_state) + litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (bankmachine0_state) 1'd1: begin - if (soc_sdram_cmd_ready) begin - soc_sdram_sequencer_start0 <= 1'd1; - end end 2'd2: begin end 2'd3: begin end + 3'd4: begin + if (litedramcore_bankmachine0_twtpcon_ready) begin + litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end default: begin end endcase // synthesis translate_off - dummy_d_124 = dummy_s; + dummy_d_120 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_125; +reg dummy_d_121; // synthesis translate_on always @(*) begin - soc_sdram_cmd_valid <= 1'd0; - case (vns_refresher_state) + litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (bankmachine0_state) 1'd1: begin - soc_sdram_cmd_valid <= 1'd1; + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end end 2'd2: begin - soc_sdram_cmd_valid <= 1'd1; - if (soc_sdram_sequencer_done0) begin - if (soc_sdram_wants_zqcs) begin - end else begin - soc_sdram_cmd_valid <= 1'd0; - end - end end 2'd3: begin - soc_sdram_cmd_valid <= 1'd1; - if (soc_sdram_zqcs_executer_done) begin - soc_sdram_cmd_valid <= 1'd0; + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; end end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_125 = dummy_s; + dummy_d_121 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_126; +reg dummy_d_122; // synthesis translate_on always @(*) begin - soc_sdram_zqcs_executer_start <= 1'd0; - case (vns_refresher_state) + litedramcore_bankmachine0_row_open <= 1'd0; + case (bankmachine0_state) 1'd1: begin end 2'd2: begin - if (soc_sdram_sequencer_done0) begin - if (soc_sdram_wants_zqcs) begin - soc_sdram_zqcs_executer_start <= 1'd1; - end else begin - end - end end 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin end default: begin end endcase // synthesis translate_off - dummy_d_126 = dummy_s; + dummy_d_122 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_127; +reg dummy_d_123; // synthesis translate_on always @(*) begin - soc_sdram_cmd_last <= 1'd0; - case (vns_refresher_state) + litedramcore_bankmachine0_row_close <= 1'd0; + case (bankmachine0_state) 1'd1: begin + litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin - if (soc_sdram_sequencer_done0) begin - if (soc_sdram_wants_zqcs) begin - end else begin - soc_sdram_cmd_last <= 1'd1; - end - end + litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin - if (soc_sdram_zqcs_executer_done) begin - soc_sdram_cmd_last <= 1'd1; - end + end + 3'd4: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin end default: begin end endcase // synthesis translate_off - dummy_d_127 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine0_req_valid; -assign soc_sdram_bankmachine0_req_ready = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine0_req_we; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine0_req_addr; -assign soc_sdram_bankmachine0_cmd_buffer_sink_valid = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine0_cmd_buffer_sink_ready; -assign soc_sdram_bankmachine0_cmd_buffer_sink_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first; -assign soc_sdram_bankmachine0_cmd_buffer_sink_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last; -assign soc_sdram_bankmachine0_cmd_buffer_sink_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we; -assign soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -assign soc_sdram_bankmachine0_cmd_buffer_source_ready = (soc_sdram_bankmachine0_req_wdata_ready | soc_sdram_bankmachine0_req_rdata_valid); -assign soc_sdram_bankmachine0_req_lock = (soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine0_cmd_buffer_source_valid); -assign soc_sdram_bankmachine0_row_hit = (soc_sdram_bankmachine0_row == soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]); -assign soc_sdram_bankmachine0_cmd_payload_ba = 1'd0; - -// synthesis translate_off -reg dummy_d_128; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine0_cmd_payload_a <= 14'd0; - if (soc_sdram_bankmachine0_row_col_n_addr_sel) begin - soc_sdram_bankmachine0_cmd_payload_a <= soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_sdram_bankmachine0_cmd_payload_a <= ((soc_sdram_bankmachine0_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_128 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine0_twtpcon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_cmd_payload_is_write); -assign soc_sdram_bankmachine0_trccon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_row_open); -assign soc_sdram_bankmachine0_trascon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_row_open); - -// synthesis translate_off -reg dummy_d_129; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine0_auto_precharge <= 1'd0; - if ((soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine0_cmd_buffer_source_valid)) begin - if ((soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin - soc_sdram_bankmachine0_auto_precharge <= (soc_sdram_bankmachine0_row_close == 1'd0); - end - end -// synthesis translate_off - dummy_d_129 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_first; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_last; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_130; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_sdram_bankmachine0_cmd_buffer_lookahead_replace) begin - soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine0_cmd_buffer_lookahead_produce; - end -// synthesis translate_off - dummy_d_130 = dummy_s; + dummy_d_123 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_sdram_bankmachine0_cmd_buffer_lookahead_replace)); -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine0_cmd_buffer_lookahead_consume; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_sdram_bankmachine0_cmd_buffer_lookahead_level != 5'd16); -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0); -assign soc_sdram_bankmachine0_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine0_cmd_buffer_source_valid) | soc_sdram_bankmachine0_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_131; +reg dummy_d_124; // synthesis translate_on always @(*) begin - vns_bankmachine0_next_state <= 4'd0; - vns_bankmachine0_next_state <= vns_bankmachine0_state; - case (vns_bankmachine0_state) + litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (bankmachine0_state) 1'd1: begin - if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin - if (soc_sdram_bankmachine0_cmd_ready) begin - vns_bankmachine0_next_state <= 3'd5; - end - end end 2'd2: begin - if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin - vns_bankmachine0_next_state <= 3'd5; - end end 2'd3: begin - if (soc_sdram_bankmachine0_trccon_ready) begin - if (soc_sdram_bankmachine0_cmd_ready) begin - vns_bankmachine0_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~soc_sdram_bankmachine0_refresh_req)) begin - vns_bankmachine0_next_state <= 1'd0; - end end 3'd5: begin - vns_bankmachine0_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine0_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine0_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine0_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine0_refresh_req) begin - vns_bankmachine0_next_state <= 3'd4; + if (litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine0_row_opened) begin - if (soc_sdram_bankmachine0_row_hit) begin - if ((soc_sdram_bankmachine0_cmd_ready & soc_sdram_bankmachine0_auto_precharge)) begin - vns_bankmachine0_next_state <= 2'd2; - end + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; end else begin - vns_bankmachine0_next_state <= 1'd1; end end else begin - vns_bankmachine0_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_131 = dummy_s; + dummy_d_124 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_132; +reg dummy_d_125; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_cmd_payload_we <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (bankmachine0_state) 1'd1: begin - if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin - soc_sdram_bankmachine0_cmd_payload_we <= 1'd1; + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -5452,42 +4820,27 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine0_refresh_req) begin - end else begin - if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine0_row_opened) begin - if (soc_sdram_bankmachine0_row_hit) begin - if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine0_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_132 = dummy_s; + dummy_d_125 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_133; +reg dummy_d_126; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (bankmachine0_state) 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine0_trccon_ready) begin - soc_sdram_bankmachine0_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -5500,33 +4853,44 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_133 = dummy_s; + dummy_d_126 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_134; +reg dummy_d_127; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (bankmachine0_state) 1'd1: begin - if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin - soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine0_trccon_ready) begin - soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin - soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5540,23 +4904,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_134 = dummy_s; + dummy_d_127 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_135; +reg dummy_d_128; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (bankmachine0_state) 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5567,34 +4938,19 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine0_refresh_req) begin - end else begin - if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine0_row_opened) begin - if (soc_sdram_bankmachine0_row_hit) begin - if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - soc_sdram_bankmachine0_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_135 = dummy_s; + dummy_d_128 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_136; +reg dummy_d_129; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5612,14 +4968,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine0_refresh_req) begin + if (litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine0_row_opened) begin - if (soc_sdram_bankmachine0_row_hit) begin - if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine0_cmd_payload_is_write <= 1'd1; + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin end else begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; end end else begin end @@ -5630,16 +4986,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_136 = dummy_s; + dummy_d_129 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_137; +reg dummy_d_130; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_req_wdata_ready <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5657,13 +5013,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine0_refresh_req) begin + if (litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine0_row_opened) begin - if (soc_sdram_bankmachine0_row_hit) begin - if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine0_req_wdata_ready <= soc_sdram_bankmachine0_cmd_ready; + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -5675,16 +5031,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_137 = dummy_s; + dummy_d_130 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_138; +reg dummy_d_131; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_req_rdata_valid <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5702,14 +5058,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine0_refresh_req) begin + if (litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine0_row_opened) begin - if (soc_sdram_bankmachine0_row_hit) begin - if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; end else begin - soc_sdram_bankmachine0_req_rdata_valid <= soc_sdram_bankmachine0_cmd_ready; end end else begin end @@ -5720,60 +5076,176 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_138 = dummy_s; + dummy_d_131 = dummy_s; // synthesis translate_on end +assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid; +assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr; +assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready; +assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); +assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid); +assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]); +assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; // synthesis translate_off -reg dummy_d_139; +reg dummy_d_132; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_refresh_gnt <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin + litedramcore_bankmachine1_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine1_row_col_n_addr_sel) begin + litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_132 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); +assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); +assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); + +// synthesis translate_off +reg dummy_d_133; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin + litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_133 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_134; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_134 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); +assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_135; +// synthesis translate_on +always @(*) begin + bankmachine1_next_state <= 4'd0; + bankmachine1_next_state <= bankmachine1_state; + case (bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + if (litedramcore_bankmachine1_cmd_ready) begin + bankmachine1_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + bankmachine1_next_state <= 3'd5; + end end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + if (litedramcore_bankmachine1_cmd_ready) begin + bankmachine1_next_state <= 3'd7; + end + end end 3'd4: begin - if (soc_sdram_bankmachine0_twtpcon_ready) begin - soc_sdram_bankmachine0_refresh_gnt <= 1'd1; + if ((~litedramcore_bankmachine1_refresh_req)) begin + bankmachine1_next_state <= 1'd0; end end 3'd5: begin + bankmachine1_next_state <= 3'd6; end 3'd6: begin + bankmachine1_next_state <= 2'd3; end 3'd7: begin + bankmachine1_next_state <= 4'd8; end 4'd8: begin + bankmachine1_next_state <= 1'd0; end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + bankmachine1_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin + bankmachine1_next_state <= 2'd2; + end + end else begin + bankmachine1_next_state <= 1'd1; + end + end else begin + bankmachine1_next_state <= 2'd3; + end + end + end end endcase // synthesis translate_off - dummy_d_139 = dummy_s; + dummy_d_135 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_140; +reg dummy_d_136; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_cmd_valid <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (bankmachine1_state) 1'd1: begin - if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin - soc_sdram_bankmachine0_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine0_trccon_ready) begin - soc_sdram_bankmachine0_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -5786,12 +5258,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine0_refresh_req) begin + if (litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine0_row_opened) begin - if (soc_sdram_bankmachine0_row_hit) begin - soc_sdram_bankmachine0_cmd_valid <= 1'd1; + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; + end end else begin end end else begin @@ -5801,23 +5276,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_140 = dummy_s; + dummy_d_136 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_141; +reg dummy_d_137; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_row_open <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine0_trccon_ready) begin - soc_sdram_bankmachine0_row_open <= 1'd1; + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -5834,26 +5309,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_141 = dummy_s; + dummy_d_137 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_142; +reg dummy_d_138; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_row_close <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (bankmachine1_state) 1'd1: begin - soc_sdram_bankmachine0_row_close <= 1'd1; end 2'd2: begin - soc_sdram_bankmachine0_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_sdram_bankmachine0_row_close <= 1'd1; + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -5867,21 +5342,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_142 = dummy_s; + dummy_d_138 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_143; +reg dummy_d_139; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_cmd_payload_cas <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -5894,12 +5375,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine0_refresh_req) begin + if (litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine0_row_opened) begin - if (soc_sdram_bankmachine0_row_hit) begin - soc_sdram_bankmachine0_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; end else begin end end else begin @@ -5909,26 +5390,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_143 = dummy_s; + dummy_d_139 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_144; +reg dummy_d_140; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_cmd_payload_ras <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine1_row_open <= 1'd0; + case (bankmachine1_state) 1'd1: begin - if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin - soc_sdram_bankmachine0_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine0_trccon_ready) begin - soc_sdram_bankmachine0_cmd_payload_ras <= 1'd1; + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_open <= 1'd1; end end 3'd4: begin @@ -5945,174 +5423,130 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_144 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine1_req_valid; -assign soc_sdram_bankmachine1_req_ready = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine1_req_we; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine1_req_addr; -assign soc_sdram_bankmachine1_cmd_buffer_sink_valid = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine1_cmd_buffer_sink_ready; -assign soc_sdram_bankmachine1_cmd_buffer_sink_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first; -assign soc_sdram_bankmachine1_cmd_buffer_sink_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last; -assign soc_sdram_bankmachine1_cmd_buffer_sink_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we; -assign soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -assign soc_sdram_bankmachine1_cmd_buffer_source_ready = (soc_sdram_bankmachine1_req_wdata_ready | soc_sdram_bankmachine1_req_rdata_valid); -assign soc_sdram_bankmachine1_req_lock = (soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine1_cmd_buffer_source_valid); -assign soc_sdram_bankmachine1_row_hit = (soc_sdram_bankmachine1_row == soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]); -assign soc_sdram_bankmachine1_cmd_payload_ba = 1'd1; - -// synthesis translate_off -reg dummy_d_145; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine1_cmd_payload_a <= 14'd0; - if (soc_sdram_bankmachine1_row_col_n_addr_sel) begin - soc_sdram_bankmachine1_cmd_payload_a <= soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_sdram_bankmachine1_cmd_payload_a <= ((soc_sdram_bankmachine1_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_145 = dummy_s; + dummy_d_140 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine1_twtpcon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_cmd_payload_is_write); -assign soc_sdram_bankmachine1_trccon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_row_open); -assign soc_sdram_bankmachine1_trascon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_row_open); // synthesis translate_off -reg dummy_d_146; +reg dummy_d_141; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_auto_precharge <= 1'd0; - if ((soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine1_cmd_buffer_source_valid)) begin - if ((soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin - soc_sdram_bankmachine1_auto_precharge <= (soc_sdram_bankmachine1_row_close == 1'd0); + litedramcore_bankmachine1_row_close <= 1'd0; + case (bankmachine1_state) + 1'd1: begin + litedramcore_bankmachine1_row_close <= 1'd1; end - end + 2'd2: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off - dummy_d_146 = dummy_s; + dummy_d_141 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_first; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_last; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_147; +reg dummy_d_142; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_sdram_bankmachine1_cmd_buffer_lookahead_replace) begin - soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine1_cmd_buffer_lookahead_produce; - end + litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase // synthesis translate_off - dummy_d_147 = dummy_s; + dummy_d_142 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_sdram_bankmachine1_cmd_buffer_lookahead_replace)); -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine1_cmd_buffer_lookahead_consume; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_sdram_bankmachine1_cmd_buffer_lookahead_level != 5'd16); -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0); -assign soc_sdram_bankmachine1_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine1_cmd_buffer_source_valid) | soc_sdram_bankmachine1_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_148; +reg dummy_d_143; // synthesis translate_on always @(*) begin - vns_bankmachine1_next_state <= 4'd0; - vns_bankmachine1_next_state <= vns_bankmachine1_state; - case (vns_bankmachine1_state) + litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (bankmachine1_state) 1'd1: begin - if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin - if (soc_sdram_bankmachine1_cmd_ready) begin - vns_bankmachine1_next_state <= 3'd5; - end + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; end end 2'd2: begin - if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin - vns_bankmachine1_next_state <= 3'd5; - end end 2'd3: begin - if (soc_sdram_bankmachine1_trccon_ready) begin - if (soc_sdram_bankmachine1_cmd_ready) begin - vns_bankmachine1_next_state <= 3'd7; - end + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; end end 3'd4: begin - if ((~soc_sdram_bankmachine1_refresh_req)) begin - vns_bankmachine1_next_state <= 1'd0; - end end 3'd5: begin - vns_bankmachine1_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine1_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine1_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine1_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine1_refresh_req) begin - vns_bankmachine1_next_state <= 3'd4; - end else begin - if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine1_row_opened) begin - if (soc_sdram_bankmachine1_row_hit) begin - if ((soc_sdram_bankmachine1_cmd_ready & soc_sdram_bankmachine1_auto_precharge)) begin - vns_bankmachine1_next_state <= 2'd2; - end - end else begin - vns_bankmachine1_next_state <= 1'd1; - end - end else begin - vns_bankmachine1_next_state <= 2'd3; - end - end - end end endcase // synthesis translate_off - dummy_d_148 = dummy_s; + dummy_d_143 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_149; +reg dummy_d_144; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_cmd_payload_we <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (bankmachine1_state) 1'd1: begin - if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin - soc_sdram_bankmachine1_cmd_payload_we <= 1'd1; + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -6130,13 +5564,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine1_refresh_req) begin + if (litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine1_row_opened) begin - if (soc_sdram_bankmachine1_row_hit) begin - if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine1_cmd_payload_we <= 1'd1; + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -6148,26 +5582,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_149 = dummy_s; + dummy_d_144 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_150; +reg dummy_d_145; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine1_trccon_ready) begin - soc_sdram_bankmachine1_row_col_n_addr_sel <= 1'd1; + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6181,30 +5619,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_150 = dummy_s; + dummy_d_145 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_151; +reg dummy_d_146; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (bankmachine1_state) 1'd1: begin - if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin - soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine1_trccon_ready) begin - soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6215,19 +5646,34 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_151 = dummy_s; + dummy_d_146 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_152; +reg dummy_d_147; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -6245,14 +5691,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine1_refresh_req) begin + if (litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine1_row_opened) begin - if (soc_sdram_bankmachine1_row_hit) begin - if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; end else begin - soc_sdram_bankmachine1_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6263,16 +5709,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_152 = dummy_s; + dummy_d_147 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_153; +reg dummy_d_148; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -6290,13 +5736,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine1_refresh_req) begin + if (litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine1_row_opened) begin - if (soc_sdram_bankmachine1_row_hit) begin - if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine1_cmd_payload_is_write <= 1'd1; + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; end else begin end end else begin @@ -6308,61 +5754,171 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_153 = dummy_s; + dummy_d_148 = dummy_s; // synthesis translate_on end +assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid; +assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr; +assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready; +assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); +assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid); +assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]); +assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; // synthesis translate_off -reg dummy_d_154; +reg dummy_d_149; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine2_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine2_row_col_n_addr_sel) begin + litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_149 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); +assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); +assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); + +// synthesis translate_off +reg dummy_d_150; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin + litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_150 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_151; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_151 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); +assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_152; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_req_wdata_ready <= 1'd0; - case (vns_bankmachine1_state) + bankmachine2_next_state <= 4'd0; + bankmachine2_next_state <= bankmachine2_state; + case (bankmachine2_state) 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + if (litedramcore_bankmachine2_cmd_ready) begin + bankmachine2_next_state <= 3'd5; + end + end end 2'd2: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + bankmachine2_next_state <= 3'd5; + end end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + if (litedramcore_bankmachine2_cmd_ready) begin + bankmachine2_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~litedramcore_bankmachine2_refresh_req)) begin + bankmachine2_next_state <= 1'd0; + end end 3'd5: begin + bankmachine2_next_state <= 3'd6; end 3'd6: begin + bankmachine2_next_state <= 2'd3; end 3'd7: begin + bankmachine2_next_state <= 4'd8; end 4'd8: begin + bankmachine2_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine1_refresh_req) begin + if (litedramcore_bankmachine2_refresh_req) begin + bankmachine2_next_state <= 3'd4; end else begin - if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine1_row_opened) begin - if (soc_sdram_bankmachine1_row_hit) begin - if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine1_req_wdata_ready <= soc_sdram_bankmachine1_cmd_ready; - end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin + bankmachine2_next_state <= 2'd2; end end else begin + bankmachine2_next_state <= 1'd1; end end else begin + bankmachine2_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_154 = dummy_s; + dummy_d_152 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_155; +reg dummy_d_153; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_req_rdata_valid <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6380,14 +5936,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine1_refresh_req) begin + if (litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine1_row_opened) begin - if (soc_sdram_bankmachine1_row_hit) begin - if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin end else begin - soc_sdram_bankmachine1_req_rdata_valid <= soc_sdram_bankmachine1_cmd_ready; + litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; end end else begin end @@ -6398,16 +5954,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_155 = dummy_s; + dummy_d_153 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_156; +reg dummy_d_154; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_refresh_gnt <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6415,8 +5971,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (soc_sdram_bankmachine1_twtpcon_ready) begin - soc_sdram_bankmachine1_refresh_gnt <= 1'd1; + if (litedramcore_bankmachine2_twtpcon_ready) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -6431,26 +5987,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_156 = dummy_s; + dummy_d_154 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_157; +reg dummy_d_155; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_cmd_valid <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (bankmachine2_state) 1'd1: begin - if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin - soc_sdram_bankmachine1_cmd_valid <= 1'd1; + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine1_trccon_ready) begin - soc_sdram_bankmachine1_cmd_valid <= 1'd1; + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; end end 3'd4: begin @@ -6464,12 +6020,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine1_refresh_req) begin + if (litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine1_row_opened) begin - if (soc_sdram_bankmachine1_row_hit) begin - soc_sdram_bankmachine1_cmd_valid <= 1'd1; + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; end else begin end end else begin @@ -6479,23 +6035,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_157 = dummy_s; + dummy_d_155 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_158; +reg dummy_d_156; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_row_open <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine1_trccon_ready) begin - soc_sdram_bankmachine1_row_open <= 1'd1; + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -6512,26 +6068,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_158 = dummy_s; + dummy_d_156 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_159; +reg dummy_d_157; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_row_close <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine2_row_open <= 1'd0; + case (bankmachine2_state) 1'd1: begin - soc_sdram_bankmachine1_row_close <= 1'd1; end 2'd2: begin - soc_sdram_bankmachine1_row_close <= 1'd1; end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_open <= 1'd1; + end end 3'd4: begin - soc_sdram_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -6545,23 +6101,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_159 = dummy_s; + dummy_d_157 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_160; +reg dummy_d_158; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_cmd_payload_cas <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine2_row_close <= 1'd0; + case (bankmachine2_state) 1'd1: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6572,42 +6131,24 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine1_refresh_req) begin - end else begin - if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine1_row_opened) begin - if (soc_sdram_bankmachine1_row_hit) begin - soc_sdram_bankmachine1_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_160 = dummy_s; + dummy_d_158 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_161; +reg dummy_d_159; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_cmd_payload_ras <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (bankmachine2_state) 1'd1: begin - if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin - soc_sdram_bankmachine1_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine1_trccon_ready) begin - soc_sdram_bankmachine1_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -6620,177 +6161,70 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_161 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine2_req_valid; -assign soc_sdram_bankmachine2_req_ready = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine2_req_we; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine2_req_addr; -assign soc_sdram_bankmachine2_cmd_buffer_sink_valid = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine2_cmd_buffer_sink_ready; -assign soc_sdram_bankmachine2_cmd_buffer_sink_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first; -assign soc_sdram_bankmachine2_cmd_buffer_sink_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last; -assign soc_sdram_bankmachine2_cmd_buffer_sink_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we; -assign soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -assign soc_sdram_bankmachine2_cmd_buffer_source_ready = (soc_sdram_bankmachine2_req_wdata_ready | soc_sdram_bankmachine2_req_rdata_valid); -assign soc_sdram_bankmachine2_req_lock = (soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine2_cmd_buffer_source_valid); -assign soc_sdram_bankmachine2_row_hit = (soc_sdram_bankmachine2_row == soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]); -assign soc_sdram_bankmachine2_cmd_payload_ba = 2'd2; - -// synthesis translate_off -reg dummy_d_162; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine2_cmd_payload_a <= 14'd0; - if (soc_sdram_bankmachine2_row_col_n_addr_sel) begin - soc_sdram_bankmachine2_cmd_payload_a <= soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_sdram_bankmachine2_cmd_payload_a <= ((soc_sdram_bankmachine2_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_162 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine2_twtpcon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_cmd_payload_is_write); -assign soc_sdram_bankmachine2_trccon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_row_open); -assign soc_sdram_bankmachine2_trascon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_row_open); - -// synthesis translate_off -reg dummy_d_163; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine2_auto_precharge <= 1'd0; - if ((soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine2_cmd_buffer_source_valid)) begin - if ((soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin - soc_sdram_bankmachine2_auto_precharge <= (soc_sdram_bankmachine2_row_close == 1'd0); - end - end -// synthesis translate_off - dummy_d_163 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_first; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_last; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_164; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_sdram_bankmachine2_cmd_buffer_lookahead_replace) begin - soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine2_cmd_buffer_lookahead_produce; - end -// synthesis translate_off - dummy_d_164 = dummy_s; + dummy_d_159 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_sdram_bankmachine2_cmd_buffer_lookahead_replace)); -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine2_cmd_buffer_lookahead_consume; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_sdram_bankmachine2_cmd_buffer_lookahead_level != 5'd16); -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0); -assign soc_sdram_bankmachine2_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine2_cmd_buffer_source_valid) | soc_sdram_bankmachine2_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_165; +reg dummy_d_160; // synthesis translate_on always @(*) begin - vns_bankmachine2_next_state <= 4'd0; - vns_bankmachine2_next_state <= vns_bankmachine2_state; - case (vns_bankmachine2_state) + litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (bankmachine2_state) 1'd1: begin - if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin - if (soc_sdram_bankmachine2_cmd_ready) begin - vns_bankmachine2_next_state <= 3'd5; - end + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 2'd2: begin - if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin - vns_bankmachine2_next_state <= 3'd5; - end end 2'd3: begin - if (soc_sdram_bankmachine2_trccon_ready) begin - if (soc_sdram_bankmachine2_cmd_ready) begin - vns_bankmachine2_next_state <= 3'd7; - end + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 3'd4: begin - if ((~soc_sdram_bankmachine2_refresh_req)) begin - vns_bankmachine2_next_state <= 1'd0; - end end 3'd5: begin - vns_bankmachine2_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine2_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine2_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine2_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine2_refresh_req) begin - vns_bankmachine2_next_state <= 3'd4; - end else begin - if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine2_row_opened) begin - if (soc_sdram_bankmachine2_row_hit) begin - if ((soc_sdram_bankmachine2_cmd_ready & soc_sdram_bankmachine2_auto_precharge)) begin - vns_bankmachine2_next_state <= 2'd2; - end - end else begin - vns_bankmachine2_next_state <= 1'd1; - end - end else begin - vns_bankmachine2_next_state <= 2'd3; - end - end - end end endcase // synthesis translate_off - dummy_d_165 = dummy_s; + dummy_d_160 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_166; +reg dummy_d_161; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_cmd_payload_we <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (bankmachine2_state) 1'd1: begin - if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin - soc_sdram_bankmachine2_cmd_payload_we <= 1'd1; + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -6808,13 +6242,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine2_refresh_req) begin + if (litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine2_row_opened) begin - if (soc_sdram_bankmachine2_row_hit) begin - if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine2_cmd_payload_we <= 1'd1; + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -6826,26 +6260,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_166 = dummy_s; + dummy_d_161 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_167; +reg dummy_d_162; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (bankmachine2_state) 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine2_trccon_ready) begin - soc_sdram_bankmachine2_row_col_n_addr_sel <= 1'd1; + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6859,30 +6297,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_167 = dummy_s; + dummy_d_162 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_168; +reg dummy_d_163; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (bankmachine2_state) 1'd1: begin - if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin - soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine2_trccon_ready) begin - soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6893,19 +6324,34 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_168 = dummy_s; + dummy_d_163 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_169; +reg dummy_d_164; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6923,14 +6369,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine2_refresh_req) begin + if (litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine2_row_opened) begin - if (soc_sdram_bankmachine2_row_hit) begin - if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; end else begin - soc_sdram_bankmachine2_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6941,16 +6387,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_169 = dummy_s; + dummy_d_164 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_170; +reg dummy_d_165; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6968,13 +6414,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine2_refresh_req) begin + if (litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine2_row_opened) begin - if (soc_sdram_bankmachine2_row_hit) begin - if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine2_cmd_payload_is_write <= 1'd1; + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; end else begin end end else begin @@ -6986,61 +6432,171 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_170 = dummy_s; + dummy_d_165 = dummy_s; // synthesis translate_on end +assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid; +assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr; +assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready; +assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); +assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid); +assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]); +assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; // synthesis translate_off -reg dummy_d_171; +reg dummy_d_166; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine3_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine3_row_col_n_addr_sel) begin + litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_166 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); +assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); +assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); + +// synthesis translate_off +reg dummy_d_167; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin + litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_167 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_168; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_168 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); +assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_169; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_req_wdata_ready <= 1'd0; - case (vns_bankmachine2_state) + bankmachine3_next_state <= 4'd0; + bankmachine3_next_state <= bankmachine3_state; + case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + if (litedramcore_bankmachine3_cmd_ready) begin + bankmachine3_next_state <= 3'd5; + end + end end 2'd2: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + bankmachine3_next_state <= 3'd5; + end end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + if (litedramcore_bankmachine3_cmd_ready) begin + bankmachine3_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~litedramcore_bankmachine3_refresh_req)) begin + bankmachine3_next_state <= 1'd0; + end end 3'd5: begin + bankmachine3_next_state <= 3'd6; end 3'd6: begin + bankmachine3_next_state <= 2'd3; end 3'd7: begin + bankmachine3_next_state <= 4'd8; end 4'd8: begin + bankmachine3_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine2_refresh_req) begin + if (litedramcore_bankmachine3_refresh_req) begin + bankmachine3_next_state <= 3'd4; end else begin - if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine2_row_opened) begin - if (soc_sdram_bankmachine2_row_hit) begin - if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine2_req_wdata_ready <= soc_sdram_bankmachine2_cmd_ready; - end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin + bankmachine3_next_state <= 2'd2; end end else begin + bankmachine3_next_state <= 1'd1; end end else begin + bankmachine3_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_171 = dummy_s; + dummy_d_169 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_172; +reg dummy_d_170; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_req_rdata_valid <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -7058,14 +6614,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine2_refresh_req) begin + if (litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine2_row_opened) begin - if (soc_sdram_bankmachine2_row_hit) begin - if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin end else begin - soc_sdram_bankmachine2_req_rdata_valid <= soc_sdram_bankmachine2_cmd_ready; + litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -7076,16 +6632,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_172 = dummy_s; + dummy_d_170 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_173; +reg dummy_d_171; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_refresh_gnt <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -7093,8 +6649,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (soc_sdram_bankmachine2_twtpcon_ready) begin - soc_sdram_bankmachine2_refresh_gnt <= 1'd1; + if (litedramcore_bankmachine3_twtpcon_ready) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -7109,26 +6665,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_173 = dummy_s; + dummy_d_171 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_174; +reg dummy_d_172; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_cmd_valid <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (bankmachine3_state) 1'd1: begin - if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin - soc_sdram_bankmachine2_cmd_valid <= 1'd1; + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine2_trccon_ready) begin - soc_sdram_bankmachine2_cmd_valid <= 1'd1; + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; end end 3'd4: begin @@ -7142,12 +6698,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine2_refresh_req) begin + if (litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine2_row_opened) begin - if (soc_sdram_bankmachine2_row_hit) begin - soc_sdram_bankmachine2_cmd_valid <= 1'd1; + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; end else begin end end else begin @@ -7157,23 +6713,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_174 = dummy_s; + dummy_d_172 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_175; +reg dummy_d_173; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_row_open <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine3_row_open <= 1'd0; + case (bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine2_trccon_ready) begin - soc_sdram_bankmachine2_row_open <= 1'd1; + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_open <= 1'd1; end end 3'd4: begin @@ -7190,26 +6746,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_175 = dummy_s; + dummy_d_173 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_176; +reg dummy_d_174; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_row_close <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine3_row_close <= 1'd0; + case (bankmachine3_state) 1'd1: begin - soc_sdram_bankmachine2_row_close <= 1'd1; + litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin - soc_sdram_bankmachine2_row_close <= 1'd1; + litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_sdram_bankmachine2_row_close <= 1'd1; + litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -7223,16 +6779,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_176 = dummy_s; + dummy_d_174 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_177; +reg dummy_d_175; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_cmd_payload_cas <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -7250,12 +6806,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine2_refresh_req) begin + if (litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine2_row_opened) begin - if (soc_sdram_bankmachine2_row_hit) begin - soc_sdram_bankmachine2_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7265,26 +6821,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_177 = dummy_s; + dummy_d_175 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_178; +reg dummy_d_176; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_cmd_payload_ras <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (bankmachine3_state) 1'd1: begin - if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin - soc_sdram_bankmachine2_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine2_trccon_ready) begin - soc_sdram_bankmachine2_cmd_payload_ras <= 1'd1; + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -7301,174 +6854,55 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_178 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine3_req_valid; -assign soc_sdram_bankmachine3_req_ready = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine3_req_we; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine3_req_addr; -assign soc_sdram_bankmachine3_cmd_buffer_sink_valid = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine3_cmd_buffer_sink_ready; -assign soc_sdram_bankmachine3_cmd_buffer_sink_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first; -assign soc_sdram_bankmachine3_cmd_buffer_sink_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last; -assign soc_sdram_bankmachine3_cmd_buffer_sink_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we; -assign soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -assign soc_sdram_bankmachine3_cmd_buffer_source_ready = (soc_sdram_bankmachine3_req_wdata_ready | soc_sdram_bankmachine3_req_rdata_valid); -assign soc_sdram_bankmachine3_req_lock = (soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine3_cmd_buffer_source_valid); -assign soc_sdram_bankmachine3_row_hit = (soc_sdram_bankmachine3_row == soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]); -assign soc_sdram_bankmachine3_cmd_payload_ba = 2'd3; - -// synthesis translate_off -reg dummy_d_179; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine3_cmd_payload_a <= 14'd0; - if (soc_sdram_bankmachine3_row_col_n_addr_sel) begin - soc_sdram_bankmachine3_cmd_payload_a <= soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_sdram_bankmachine3_cmd_payload_a <= ((soc_sdram_bankmachine3_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_179 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine3_twtpcon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_cmd_payload_is_write); -assign soc_sdram_bankmachine3_trccon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_row_open); -assign soc_sdram_bankmachine3_trascon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_row_open); - -// synthesis translate_off -reg dummy_d_180; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine3_auto_precharge <= 1'd0; - if ((soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine3_cmd_buffer_source_valid)) begin - if ((soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin - soc_sdram_bankmachine3_auto_precharge <= (soc_sdram_bankmachine3_row_close == 1'd0); - end - end -// synthesis translate_off - dummy_d_180 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_first; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_last; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_181; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_sdram_bankmachine3_cmd_buffer_lookahead_replace) begin - soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine3_cmd_buffer_lookahead_produce; - end -// synthesis translate_off - dummy_d_181 = dummy_s; + dummy_d_176 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_sdram_bankmachine3_cmd_buffer_lookahead_replace)); -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine3_cmd_buffer_lookahead_consume; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_sdram_bankmachine3_cmd_buffer_lookahead_level != 5'd16); -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0); -assign soc_sdram_bankmachine3_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine3_cmd_buffer_source_valid) | soc_sdram_bankmachine3_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_182; +reg dummy_d_177; // synthesis translate_on always @(*) begin - vns_bankmachine3_next_state <= 4'd0; - vns_bankmachine3_next_state <= vns_bankmachine3_state; - case (vns_bankmachine3_state) + litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (bankmachine3_state) 1'd1: begin - if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin - if (soc_sdram_bankmachine3_cmd_ready) begin - vns_bankmachine3_next_state <= 3'd5; - end + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; end end 2'd2: begin - if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin - vns_bankmachine3_next_state <= 3'd5; - end end 2'd3: begin - if (soc_sdram_bankmachine3_trccon_ready) begin - if (soc_sdram_bankmachine3_cmd_ready) begin - vns_bankmachine3_next_state <= 3'd7; - end + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; end end 3'd4: begin - if ((~soc_sdram_bankmachine3_refresh_req)) begin - vns_bankmachine3_next_state <= 1'd0; - end end 3'd5: begin - vns_bankmachine3_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine3_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine3_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine3_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine3_refresh_req) begin - vns_bankmachine3_next_state <= 3'd4; - end else begin - if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine3_row_opened) begin - if (soc_sdram_bankmachine3_row_hit) begin - if ((soc_sdram_bankmachine3_cmd_ready & soc_sdram_bankmachine3_auto_precharge)) begin - vns_bankmachine3_next_state <= 2'd2; - end - end else begin - vns_bankmachine3_next_state <= 1'd1; - end - end else begin - vns_bankmachine3_next_state <= 2'd3; - end - end - end end endcase // synthesis translate_off - dummy_d_182 = dummy_s; + dummy_d_177 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_183; +reg dummy_d_178; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_cmd_payload_we <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (bankmachine3_state) 1'd1: begin - if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin - soc_sdram_bankmachine3_cmd_payload_we <= 1'd1; + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -7486,13 +6920,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine3_refresh_req) begin + if (litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine3_row_opened) begin - if (soc_sdram_bankmachine3_row_hit) begin - if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine3_cmd_payload_we <= 1'd1; + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -7504,26 +6938,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_183 = dummy_s; + dummy_d_178 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_184; +reg dummy_d_179; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine3_trccon_ready) begin - soc_sdram_bankmachine3_row_col_n_addr_sel <= 1'd1; + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7537,30 +6975,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_184 = dummy_s; + dummy_d_179 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_185; +reg dummy_d_180; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (bankmachine3_state) 1'd1: begin - if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin - soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine3_trccon_ready) begin - soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7571,19 +7002,34 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_185 = dummy_s; + dummy_d_180 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_186; +reg dummy_d_181; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -7601,14 +7047,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine3_refresh_req) begin + if (litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine3_row_opened) begin - if (soc_sdram_bankmachine3_row_hit) begin - if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; end else begin - soc_sdram_bankmachine3_cmd_payload_is_read <= 1'd1; end end else begin end @@ -7619,16 +7065,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_186 = dummy_s; + dummy_d_181 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_187; +reg dummy_d_182; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -7646,13 +7092,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine3_refresh_req) begin + if (litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine3_row_opened) begin - if (soc_sdram_bankmachine3_row_hit) begin - if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine3_cmd_payload_is_write <= 1'd1; + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; end else begin end end else begin @@ -7664,61 +7110,171 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_187 = dummy_s; + dummy_d_182 = dummy_s; // synthesis translate_on end +assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid; +assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr; +assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready; +assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); +assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid); +assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]); +assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; // synthesis translate_off -reg dummy_d_188; +reg dummy_d_183; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine4_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine4_row_col_n_addr_sel) begin + litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_183 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); +assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); +assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); + +// synthesis translate_off +reg dummy_d_184; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin + litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_184 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_185; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_185 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); +assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_186; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_req_wdata_ready <= 1'd0; - case (vns_bankmachine3_state) + bankmachine4_next_state <= 4'd0; + bankmachine4_next_state <= bankmachine4_state; + case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + if (litedramcore_bankmachine4_cmd_ready) begin + bankmachine4_next_state <= 3'd5; + end + end end 2'd2: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + bankmachine4_next_state <= 3'd5; + end end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + if (litedramcore_bankmachine4_cmd_ready) begin + bankmachine4_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~litedramcore_bankmachine4_refresh_req)) begin + bankmachine4_next_state <= 1'd0; + end end 3'd5: begin + bankmachine4_next_state <= 3'd6; end 3'd6: begin + bankmachine4_next_state <= 2'd3; end 3'd7: begin + bankmachine4_next_state <= 4'd8; end 4'd8: begin + bankmachine4_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine3_refresh_req) begin + if (litedramcore_bankmachine4_refresh_req) begin + bankmachine4_next_state <= 3'd4; end else begin - if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine3_row_opened) begin - if (soc_sdram_bankmachine3_row_hit) begin - if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine3_req_wdata_ready <= soc_sdram_bankmachine3_cmd_ready; - end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin + bankmachine4_next_state <= 2'd2; end end else begin + bankmachine4_next_state <= 1'd1; end end else begin + bankmachine4_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_188 = dummy_s; + dummy_d_186 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_189; +reg dummy_d_187; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_req_rdata_valid <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7736,14 +7292,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine3_refresh_req) begin + if (litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine3_row_opened) begin - if (soc_sdram_bankmachine3_row_hit) begin - if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin end else begin - soc_sdram_bankmachine3_req_rdata_valid <= soc_sdram_bankmachine3_cmd_ready; + litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; end end else begin end @@ -7754,16 +7310,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_189 = dummy_s; + dummy_d_187 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_190; +reg dummy_d_188; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_refresh_gnt <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7771,8 +7327,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (soc_sdram_bankmachine3_twtpcon_ready) begin - soc_sdram_bankmachine3_refresh_gnt <= 1'd1; + if (litedramcore_bankmachine4_twtpcon_ready) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -7787,26 +7343,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_190 = dummy_s; + dummy_d_188 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_191; +reg dummy_d_189; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_cmd_valid <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (bankmachine4_state) 1'd1: begin - if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin - soc_sdram_bankmachine3_cmd_valid <= 1'd1; + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine3_trccon_ready) begin - soc_sdram_bankmachine3_cmd_valid <= 1'd1; + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 3'd4: begin @@ -7820,12 +7376,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine3_refresh_req) begin + if (litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine3_row_opened) begin - if (soc_sdram_bankmachine3_row_hit) begin - soc_sdram_bankmachine3_cmd_valid <= 1'd1; + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; end else begin end end else begin @@ -7835,23 +7391,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_191 = dummy_s; + dummy_d_189 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_192; +reg dummy_d_190; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_row_open <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine4_row_open <= 1'd0; + case (bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine3_trccon_ready) begin - soc_sdram_bankmachine3_row_open <= 1'd1; + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_open <= 1'd1; end end 3'd4: begin @@ -7868,26 +7424,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_192 = dummy_s; + dummy_d_190 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_193; +reg dummy_d_191; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_row_close <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine4_row_close <= 1'd0; + case (bankmachine4_state) 1'd1: begin - soc_sdram_bankmachine3_row_close <= 1'd1; + litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin - soc_sdram_bankmachine3_row_close <= 1'd1; + litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_sdram_bankmachine3_row_close <= 1'd1; + litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -7901,16 +7457,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_193 = dummy_s; + dummy_d_191 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_194; +reg dummy_d_192; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_cmd_payload_cas <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -7928,12 +7484,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine3_refresh_req) begin + if (litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine3_row_opened) begin - if (soc_sdram_bankmachine3_row_hit) begin - soc_sdram_bankmachine3_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7943,26 +7499,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_194 = dummy_s; + dummy_d_192 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_195; +reg dummy_d_193; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_cmd_payload_ras <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (bankmachine4_state) 1'd1: begin - if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin - soc_sdram_bankmachine3_cmd_payload_ras <= 1'd1; + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine3_trccon_ready) begin - soc_sdram_bankmachine3_cmd_payload_ras <= 1'd1; + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -7979,181 +7535,78 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_195 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine4_req_valid; -assign soc_sdram_bankmachine4_req_ready = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine4_req_we; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine4_req_addr; -assign soc_sdram_bankmachine4_cmd_buffer_sink_valid = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine4_cmd_buffer_sink_ready; -assign soc_sdram_bankmachine4_cmd_buffer_sink_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first; -assign soc_sdram_bankmachine4_cmd_buffer_sink_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last; -assign soc_sdram_bankmachine4_cmd_buffer_sink_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we; -assign soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -assign soc_sdram_bankmachine4_cmd_buffer_source_ready = (soc_sdram_bankmachine4_req_wdata_ready | soc_sdram_bankmachine4_req_rdata_valid); -assign soc_sdram_bankmachine4_req_lock = (soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine4_cmd_buffer_source_valid); -assign soc_sdram_bankmachine4_row_hit = (soc_sdram_bankmachine4_row == soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]); -assign soc_sdram_bankmachine4_cmd_payload_ba = 3'd4; - -// synthesis translate_off -reg dummy_d_196; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine4_cmd_payload_a <= 14'd0; - if (soc_sdram_bankmachine4_row_col_n_addr_sel) begin - soc_sdram_bankmachine4_cmd_payload_a <= soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_sdram_bankmachine4_cmd_payload_a <= ((soc_sdram_bankmachine4_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_196 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine4_twtpcon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_cmd_payload_is_write); -assign soc_sdram_bankmachine4_trccon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_row_open); -assign soc_sdram_bankmachine4_trascon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_row_open); - -// synthesis translate_off -reg dummy_d_197; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine4_auto_precharge <= 1'd0; - if ((soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine4_cmd_buffer_source_valid)) begin - if ((soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin - soc_sdram_bankmachine4_auto_precharge <= (soc_sdram_bankmachine4_row_close == 1'd0); - end - end -// synthesis translate_off - dummy_d_197 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_first; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_last; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_198; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_sdram_bankmachine4_cmd_buffer_lookahead_replace) begin - soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine4_cmd_buffer_lookahead_produce; - end -// synthesis translate_off - dummy_d_198 = dummy_s; + dummy_d_193 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_sdram_bankmachine4_cmd_buffer_lookahead_replace)); -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine4_cmd_buffer_lookahead_consume; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_sdram_bankmachine4_cmd_buffer_lookahead_level != 5'd16); -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_sdram_bankmachine4_cmd_buffer_lookahead_level != 1'd0); -assign soc_sdram_bankmachine4_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine4_cmd_buffer_source_valid) | soc_sdram_bankmachine4_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_199; +reg dummy_d_194; // synthesis translate_on always @(*) begin - vns_bankmachine4_next_state <= 4'd0; - vns_bankmachine4_next_state <= vns_bankmachine4_state; - case (vns_bankmachine4_state) + litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (bankmachine4_state) 1'd1: begin - if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin - if (soc_sdram_bankmachine4_cmd_ready) begin - vns_bankmachine4_next_state <= 3'd5; - end + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end end 2'd2: begin - if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin - vns_bankmachine4_next_state <= 3'd5; - end end 2'd3: begin - if (soc_sdram_bankmachine4_trccon_ready) begin - if (soc_sdram_bankmachine4_cmd_ready) begin - vns_bankmachine4_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~soc_sdram_bankmachine4_refresh_req)) begin - vns_bankmachine4_next_state <= 1'd0; - end end 3'd5: begin - vns_bankmachine4_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine4_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine4_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine4_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine4_refresh_req) begin - vns_bankmachine4_next_state <= 3'd4; + if (litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine4_row_opened) begin - if (soc_sdram_bankmachine4_row_hit) begin - if ((soc_sdram_bankmachine4_cmd_ready & soc_sdram_bankmachine4_auto_precharge)) begin - vns_bankmachine4_next_state <= 2'd2; + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin end end else begin - vns_bankmachine4_next_state <= 1'd1; end end else begin - vns_bankmachine4_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_199 = dummy_s; + dummy_d_194 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_200; +reg dummy_d_195; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_cmd_payload_we <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (bankmachine4_state) 1'd1: begin - if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin - soc_sdram_bankmachine4_cmd_payload_we <= 1'd1; + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8164,42 +7617,24 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine4_refresh_req) begin - end else begin - if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine4_row_opened) begin - if (soc_sdram_bankmachine4_row_hit) begin - if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine4_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_200 = dummy_s; + dummy_d_195 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_201; +reg dummy_d_196; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine4_trccon_ready) begin - soc_sdram_bankmachine4_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -8212,33 +7647,44 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_201 = dummy_s; + dummy_d_196 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_202; +reg dummy_d_197; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (bankmachine4_state) 1'd1: begin - if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin - soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine4_trccon_ready) begin - soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin - soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8252,16 +7698,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_202 = dummy_s; + dummy_d_197 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_203; +reg dummy_d_198; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -8279,14 +7725,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine4_refresh_req) begin + if (litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine4_row_opened) begin - if (soc_sdram_bankmachine4_row_hit) begin - if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; end else begin - soc_sdram_bankmachine4_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8297,16 +7743,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_203 = dummy_s; + dummy_d_198 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_204; +reg dummy_d_199; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -8324,13 +7770,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine4_refresh_req) begin + if (litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine4_row_opened) begin - if (soc_sdram_bankmachine4_row_hit) begin - if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine4_cmd_payload_is_write <= 1'd1; + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; end else begin end end else begin @@ -8342,61 +7788,171 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_204 = dummy_s; + dummy_d_199 = dummy_s; // synthesis translate_on end +assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid; +assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr; +assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready; +assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); +assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid); +assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]); +assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; // synthesis translate_off -reg dummy_d_205; +reg dummy_d_200; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine5_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine5_row_col_n_addr_sel) begin + litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_200 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); +assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); +assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); + +// synthesis translate_off +reg dummy_d_201; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin + litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_201 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_202; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_202 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); +assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_203; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_req_wdata_ready <= 1'd0; - case (vns_bankmachine4_state) + bankmachine5_next_state <= 4'd0; + bankmachine5_next_state <= bankmachine5_state; + case (bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + if (litedramcore_bankmachine5_cmd_ready) begin + bankmachine5_next_state <= 3'd5; + end + end end 2'd2: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + bankmachine5_next_state <= 3'd5; + end end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + if (litedramcore_bankmachine5_cmd_ready) begin + bankmachine5_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~litedramcore_bankmachine5_refresh_req)) begin + bankmachine5_next_state <= 1'd0; + end end 3'd5: begin + bankmachine5_next_state <= 3'd6; end 3'd6: begin + bankmachine5_next_state <= 2'd3; end 3'd7: begin + bankmachine5_next_state <= 4'd8; end 4'd8: begin + bankmachine5_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine4_refresh_req) begin + if (litedramcore_bankmachine5_refresh_req) begin + bankmachine5_next_state <= 3'd4; end else begin - if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine4_row_opened) begin - if (soc_sdram_bankmachine4_row_hit) begin - if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine4_req_wdata_ready <= soc_sdram_bankmachine4_cmd_ready; - end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin + bankmachine5_next_state <= 2'd2; end end else begin + bankmachine5_next_state <= 1'd1; end end else begin + bankmachine5_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_205 = dummy_s; + dummy_d_203 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_206; +reg dummy_d_204; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_req_rdata_valid <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8414,14 +7970,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine4_refresh_req) begin + if (litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine4_row_opened) begin - if (soc_sdram_bankmachine4_row_hit) begin - if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin end else begin - soc_sdram_bankmachine4_req_rdata_valid <= soc_sdram_bankmachine4_cmd_ready; + litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; end end else begin end @@ -8432,16 +7988,49 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_206 = dummy_s; + dummy_d_204 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_207; +reg dummy_d_205; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_205 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_206; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_refresh_gnt <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8449,8 +8038,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (soc_sdram_bankmachine4_twtpcon_ready) begin - soc_sdram_bankmachine4_refresh_gnt <= 1'd1; + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -8465,26 +8054,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_207 = dummy_s; + dummy_d_206 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_208; +reg dummy_d_207; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_cmd_valid <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (bankmachine5_state) 1'd1: begin - if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin - soc_sdram_bankmachine4_cmd_valid <= 1'd1; + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine4_trccon_ready) begin - soc_sdram_bankmachine4_cmd_valid <= 1'd1; + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 3'd4: begin @@ -8498,12 +8087,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine4_refresh_req) begin + if (litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine4_row_opened) begin - if (soc_sdram_bankmachine4_row_hit) begin - soc_sdram_bankmachine4_cmd_valid <= 1'd1; + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; end else begin end end else begin @@ -8513,23 +8102,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_208 = dummy_s; + dummy_d_207 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_209; +reg dummy_d_208; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_row_open <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine5_row_open <= 1'd0; + case (bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine4_trccon_ready) begin - soc_sdram_bankmachine4_row_open <= 1'd1; + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_open <= 1'd1; end end 3'd4: begin @@ -8546,26 +8135,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_209 = dummy_s; + dummy_d_208 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_210; +reg dummy_d_209; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_row_close <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine5_row_close <= 1'd0; + case (bankmachine5_state) 1'd1: begin - soc_sdram_bankmachine4_row_close <= 1'd1; + litedramcore_bankmachine5_row_close <= 1'd1; end 2'd2: begin - soc_sdram_bankmachine4_row_close <= 1'd1; + litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_sdram_bankmachine4_row_close <= 1'd1; + litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -8579,16 +8168,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_210 = dummy_s; + dummy_d_209 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_211; +reg dummy_d_210; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_cmd_payload_cas <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8606,12 +8195,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine4_refresh_req) begin + if (litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine4_row_opened) begin - if (soc_sdram_bankmachine4_row_hit) begin - soc_sdram_bankmachine4_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -8621,26 +8210,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_211 = dummy_s; + dummy_d_210 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_212; +reg dummy_d_211; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_cmd_payload_ras <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (bankmachine5_state) 1'd1: begin - if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin - soc_sdram_bankmachine4_cmd_payload_ras <= 1'd1; + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine4_trccon_ready) begin - soc_sdram_bankmachine4_cmd_payload_ras <= 1'd1; + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -8657,176 +8246,103 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_212 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine5_req_valid; -assign soc_sdram_bankmachine5_req_ready = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine5_req_we; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine5_req_addr; -assign soc_sdram_bankmachine5_cmd_buffer_sink_valid = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine5_cmd_buffer_sink_ready; -assign soc_sdram_bankmachine5_cmd_buffer_sink_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first; -assign soc_sdram_bankmachine5_cmd_buffer_sink_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last; -assign soc_sdram_bankmachine5_cmd_buffer_sink_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we; -assign soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -assign soc_sdram_bankmachine5_cmd_buffer_source_ready = (soc_sdram_bankmachine5_req_wdata_ready | soc_sdram_bankmachine5_req_rdata_valid); -assign soc_sdram_bankmachine5_req_lock = (soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine5_cmd_buffer_source_valid); -assign soc_sdram_bankmachine5_row_hit = (soc_sdram_bankmachine5_row == soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]); -assign soc_sdram_bankmachine5_cmd_payload_ba = 3'd5; - -// synthesis translate_off -reg dummy_d_213; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine5_cmd_payload_a <= 14'd0; - if (soc_sdram_bankmachine5_row_col_n_addr_sel) begin - soc_sdram_bankmachine5_cmd_payload_a <= soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_sdram_bankmachine5_cmd_payload_a <= ((soc_sdram_bankmachine5_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_213 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine5_twtpcon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_cmd_payload_is_write); -assign soc_sdram_bankmachine5_trccon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_row_open); -assign soc_sdram_bankmachine5_trascon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_row_open); - -// synthesis translate_off -reg dummy_d_214; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine5_auto_precharge <= 1'd0; - if ((soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine5_cmd_buffer_source_valid)) begin - if ((soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin - soc_sdram_bankmachine5_auto_precharge <= (soc_sdram_bankmachine5_row_close == 1'd0); - end - end -// synthesis translate_off - dummy_d_214 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_first; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_last; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_215; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_sdram_bankmachine5_cmd_buffer_lookahead_replace) begin - soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine5_cmd_buffer_lookahead_produce; - end -// synthesis translate_off - dummy_d_215 = dummy_s; + dummy_d_211 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_sdram_bankmachine5_cmd_buffer_lookahead_replace)); -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine5_cmd_buffer_lookahead_consume; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_sdram_bankmachine5_cmd_buffer_lookahead_level != 5'd16); -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_sdram_bankmachine5_cmd_buffer_lookahead_level != 1'd0); -assign soc_sdram_bankmachine5_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine5_cmd_buffer_source_valid) | soc_sdram_bankmachine5_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_216; +reg dummy_d_212; // synthesis translate_on always @(*) begin - vns_bankmachine5_next_state <= 4'd0; - vns_bankmachine5_next_state <= vns_bankmachine5_state; - case (vns_bankmachine5_state) + litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (bankmachine5_state) 1'd1: begin - if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin - if (soc_sdram_bankmachine5_cmd_ready) begin - vns_bankmachine5_next_state <= 3'd5; - end + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end end 2'd2: begin - if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin - vns_bankmachine5_next_state <= 3'd5; - end end 2'd3: begin - if (soc_sdram_bankmachine5_trccon_ready) begin - if (soc_sdram_bankmachine5_cmd_ready) begin - vns_bankmachine5_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~soc_sdram_bankmachine5_refresh_req)) begin - vns_bankmachine5_next_state <= 1'd0; - end end 3'd5: begin - vns_bankmachine5_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine5_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine5_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine5_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine5_refresh_req) begin - vns_bankmachine5_next_state <= 3'd4; + if (litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine5_row_opened) begin - if (soc_sdram_bankmachine5_row_hit) begin - if ((soc_sdram_bankmachine5_cmd_ready & soc_sdram_bankmachine5_auto_precharge)) begin - vns_bankmachine5_next_state <= 2'd2; + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end else begin end end else begin - vns_bankmachine5_next_state <= 1'd1; end end else begin - vns_bankmachine5_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_216 = dummy_s; + dummy_d_212 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_217; +reg dummy_d_213; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_cmd_payload_we <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (bankmachine5_state) 1'd1: begin - if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin - soc_sdram_bankmachine5_cmd_payload_we <= 1'd1; + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end + 3'd4: begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_213 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_214; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (bankmachine5_state) + 1'd1: begin + end 2'd2: begin end 2'd3: begin @@ -8842,14 +8358,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine5_refresh_req) begin + if (litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine5_row_opened) begin - if (soc_sdram_bankmachine5_row_hit) begin - if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine5_cmd_payload_we <= 1'd1; + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin end else begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8860,24 +8376,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_217 = dummy_s; + dummy_d_214 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_218; +reg dummy_d_215; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine5_trccon_ready) begin - soc_sdram_bankmachine5_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -8890,33 +8403,41 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_218 = dummy_s; + dummy_d_215 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_219; +reg dummy_d_216; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (bankmachine5_state) 1'd1: begin - if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin - soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine5_trccon_ready) begin - soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8927,48 +8448,173 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase +// synthesis translate_off + dummy_d_216 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid; +assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr; +assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready; +assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); +assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid); +assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]); +assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; + +// synthesis translate_off +reg dummy_d_217; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine6_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine6_row_col_n_addr_sel) begin + litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_217 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); +assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); +assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); + +// synthesis translate_off +reg dummy_d_218; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin + litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_218 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_219; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce; + end // synthesis translate_off dummy_d_219 = dummy_s; // synthesis translate_on end +assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); +assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready); // synthesis translate_off reg dummy_d_220; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine5_state) + bankmachine6_next_state <= 4'd0; + bankmachine6_next_state <= bankmachine6_state; + case (bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + if (litedramcore_bankmachine6_cmd_ready) begin + bankmachine6_next_state <= 3'd5; + end + end end 2'd2: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + bankmachine6_next_state <= 3'd5; + end end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + if (litedramcore_bankmachine6_cmd_ready) begin + bankmachine6_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~litedramcore_bankmachine6_refresh_req)) begin + bankmachine6_next_state <= 1'd0; + end end 3'd5: begin + bankmachine6_next_state <= 3'd6; end 3'd6: begin + bankmachine6_next_state <= 2'd3; end 3'd7: begin + bankmachine6_next_state <= 4'd8; end 4'd8: begin + bankmachine6_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine5_refresh_req) begin + if (litedramcore_bankmachine6_refresh_req) begin + bankmachine6_next_state <= 3'd4; end else begin - if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine5_row_opened) begin - if (soc_sdram_bankmachine5_row_hit) begin - if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - soc_sdram_bankmachine5_cmd_payload_is_read <= 1'd1; + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin + bankmachine6_next_state <= 2'd2; end end else begin + bankmachine6_next_state <= 1'd1; end end else begin + bankmachine6_next_state <= 2'd3; end end end @@ -8983,8 +8629,8 @@ end reg dummy_d_221; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -9002,14 +8648,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine5_refresh_req) begin + if (litedramcore_bankmachine6_refresh_req) begin end else begin - if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine5_row_opened) begin - if (soc_sdram_bankmachine5_row_hit) begin - if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine5_cmd_payload_is_write <= 1'd1; + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin end else begin + litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; end end else begin end @@ -9028,8 +8674,8 @@ end reg dummy_d_222; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_req_wdata_ready <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -9037,6 +8683,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (litedramcore_bankmachine6_twtpcon_ready) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9047,21 +8696,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine5_refresh_req) begin - end else begin - if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine5_row_opened) begin - if (soc_sdram_bankmachine5_row_hit) begin - if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine5_req_wdata_ready <= soc_sdram_bankmachine5_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -9073,13 +8707,19 @@ end reg dummy_d_223; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_req_rdata_valid <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -9092,15 +8732,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine5_refresh_req) begin + if (litedramcore_bankmachine6_refresh_req) begin end else begin - if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine5_row_opened) begin - if (soc_sdram_bankmachine5_row_hit) begin - if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - soc_sdram_bankmachine5_req_rdata_valid <= soc_sdram_bankmachine5_cmd_ready; - end + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; end else begin end end else begin @@ -9118,18 +8755,18 @@ end reg dummy_d_224; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_refresh_gnt <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin - if (soc_sdram_bankmachine5_twtpcon_ready) begin - soc_sdram_bankmachine5_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9151,18 +8788,15 @@ end reg dummy_d_225; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_cmd_valid <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine6_row_open <= 1'd0; + case (bankmachine6_state) 1'd1: begin - if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin - soc_sdram_bankmachine5_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine5_trccon_ready) begin - soc_sdram_bankmachine5_cmd_valid <= 1'd1; + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_open <= 1'd1; end end 3'd4: begin @@ -9176,18 +8810,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine5_refresh_req) begin - end else begin - if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine5_row_opened) begin - if (soc_sdram_bankmachine5_row_hit) begin - soc_sdram_bankmachine5_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -9199,18 +8821,18 @@ end reg dummy_d_226; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_row_open <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine6_row_close <= 1'd0; + case (bankmachine6_state) 1'd1: begin + litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin - if (soc_sdram_bankmachine5_trccon_ready) begin - soc_sdram_bankmachine5_row_open <= 1'd1; - end end 3'd4: begin + litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -9232,18 +8854,15 @@ end reg dummy_d_227; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_row_close <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (bankmachine6_state) 1'd1: begin - soc_sdram_bankmachine5_row_close <= 1'd1; end 2'd2: begin - soc_sdram_bankmachine5_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_sdram_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -9254,6 +8873,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -9265,13 +8896,19 @@ end reg dummy_d_228; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_cmd_payload_cas <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -9284,18 +8921,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine5_refresh_req) begin - end else begin - if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine5_row_opened) begin - if (soc_sdram_bankmachine5_row_hit) begin - soc_sdram_bankmachine5_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -9307,19 +8932,16 @@ end reg dummy_d_229; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_cmd_payload_ras <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (bankmachine6_state) 1'd1: begin - if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin - soc_sdram_bankmachine5_cmd_payload_ras <= 1'd1; + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine5_trccon_ready) begin - soc_sdram_bankmachine5_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -9332,178 +8954,72 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off dummy_d_229 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine6_req_valid; -assign soc_sdram_bankmachine6_req_ready = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine6_req_we; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine6_req_addr; -assign soc_sdram_bankmachine6_cmd_buffer_sink_valid = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine6_cmd_buffer_sink_ready; -assign soc_sdram_bankmachine6_cmd_buffer_sink_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first; -assign soc_sdram_bankmachine6_cmd_buffer_sink_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last; -assign soc_sdram_bankmachine6_cmd_buffer_sink_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we; -assign soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -assign soc_sdram_bankmachine6_cmd_buffer_source_ready = (soc_sdram_bankmachine6_req_wdata_ready | soc_sdram_bankmachine6_req_rdata_valid); -assign soc_sdram_bankmachine6_req_lock = (soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine6_cmd_buffer_source_valid); -assign soc_sdram_bankmachine6_row_hit = (soc_sdram_bankmachine6_row == soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]); -assign soc_sdram_bankmachine6_cmd_payload_ba = 3'd6; // synthesis translate_off reg dummy_d_230; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_cmd_payload_a <= 14'd0; - if (soc_sdram_bankmachine6_row_col_n_addr_sel) begin - soc_sdram_bankmachine6_cmd_payload_a <= soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_sdram_bankmachine6_cmd_payload_a <= ((soc_sdram_bankmachine6_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_230 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine6_twtpcon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_cmd_payload_is_write); -assign soc_sdram_bankmachine6_trccon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_row_open); -assign soc_sdram_bankmachine6_trascon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_row_open); - -// synthesis translate_off -reg dummy_d_231; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine6_auto_precharge <= 1'd0; - if ((soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine6_cmd_buffer_source_valid)) begin - if ((soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin - soc_sdram_bankmachine6_auto_precharge <= (soc_sdram_bankmachine6_row_close == 1'd0); - end - end -// synthesis translate_off - dummy_d_231 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_first; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_last; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_232; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_sdram_bankmachine6_cmd_buffer_lookahead_replace) begin - soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine6_cmd_buffer_lookahead_produce; - end -// synthesis translate_off - dummy_d_232 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_sdram_bankmachine6_cmd_buffer_lookahead_replace)); -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine6_cmd_buffer_lookahead_consume; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_sdram_bankmachine6_cmd_buffer_lookahead_level != 5'd16); -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_sdram_bankmachine6_cmd_buffer_lookahead_level != 1'd0); -assign soc_sdram_bankmachine6_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine6_cmd_buffer_source_valid) | soc_sdram_bankmachine6_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_233; -// synthesis translate_on -always @(*) begin - vns_bankmachine6_next_state <= 4'd0; - vns_bankmachine6_next_state <= vns_bankmachine6_state; - case (vns_bankmachine6_state) + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (bankmachine6_state) 1'd1: begin - if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin - if (soc_sdram_bankmachine6_cmd_ready) begin - vns_bankmachine6_next_state <= 3'd5; - end + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin - if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin - vns_bankmachine6_next_state <= 3'd5; - end end 2'd3: begin - if (soc_sdram_bankmachine6_trccon_ready) begin - if (soc_sdram_bankmachine6_cmd_ready) begin - vns_bankmachine6_next_state <= 3'd7; - end + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - if ((~soc_sdram_bankmachine6_refresh_req)) begin - vns_bankmachine6_next_state <= 1'd0; - end + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin - vns_bankmachine6_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine6_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine6_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine6_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine6_refresh_req) begin - vns_bankmachine6_next_state <= 3'd4; - end else begin - if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine6_row_opened) begin - if (soc_sdram_bankmachine6_row_hit) begin - if ((soc_sdram_bankmachine6_cmd_ready & soc_sdram_bankmachine6_auto_precharge)) begin - vns_bankmachine6_next_state <= 2'd2; - end - end else begin - vns_bankmachine6_next_state <= 1'd1; - end - end else begin - vns_bankmachine6_next_state <= 2'd3; - end - end - end end endcase // synthesis translate_off - dummy_d_233 = dummy_s; + dummy_d_230 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_234; +reg dummy_d_231; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_cmd_payload_we <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (bankmachine6_state) 1'd1: begin - if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin - soc_sdram_bankmachine6_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -9520,14 +9036,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine6_refresh_req) begin + if (litedramcore_bankmachine6_refresh_req) begin end else begin - if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine6_row_opened) begin - if (soc_sdram_bankmachine6_row_hit) begin - if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine6_cmd_payload_we <= 1'd1; + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin end else begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9538,24 +9054,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_234 = dummy_s; + dummy_d_231 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_235; +reg dummy_d_232; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine6_trccon_ready) begin - soc_sdram_bankmachine6_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -9568,81 +9081,14 @@ always @(*) begin 4'd8: begin end default: begin - end - endcase -// synthesis translate_off - dummy_d_235 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_236; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine6_state) - 1'd1: begin - if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin - soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_sdram_bankmachine6_trccon_ready) begin - soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_236 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_237; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine6_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_sdram_bankmachine6_refresh_req) begin + if (litedramcore_bankmachine6_refresh_req) begin end else begin - if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine6_row_opened) begin - if (soc_sdram_bankmachine6_row_hit) begin - if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; end else begin - soc_sdram_bankmachine6_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9653,16 +9099,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_237 = dummy_s; + dummy_d_232 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_238; +reg dummy_d_233; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -9680,13 +9126,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine6_refresh_req) begin + if (litedramcore_bankmachine6_refresh_req) begin end else begin - if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine6_row_opened) begin - if (soc_sdram_bankmachine6_row_hit) begin - if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine6_cmd_payload_is_write <= 1'd1; + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; end else begin end end else begin @@ -9698,61 +9144,171 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_238 = dummy_s; + dummy_d_233 = dummy_s; // synthesis translate_on end +assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid; +assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr; +assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready; +assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); +assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid); +assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]); +assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; // synthesis translate_off -reg dummy_d_239; +reg dummy_d_234; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine7_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine7_row_col_n_addr_sel) begin + litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +// synthesis translate_off + dummy_d_234 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); +assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); +assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); + +// synthesis translate_off +reg dummy_d_235; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin + litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); + end + end +// synthesis translate_off + dummy_d_235 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; + +// synthesis translate_off +reg dummy_d_236; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_236 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); +assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_237; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_req_wdata_ready <= 1'd0; - case (vns_bankmachine6_state) + bankmachine7_next_state <= 4'd0; + bankmachine7_next_state <= bankmachine7_state; + case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + if (litedramcore_bankmachine7_cmd_ready) begin + bankmachine7_next_state <= 3'd5; + end + end end 2'd2: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + bankmachine7_next_state <= 3'd5; + end end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + if (litedramcore_bankmachine7_cmd_ready) begin + bankmachine7_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~litedramcore_bankmachine7_refresh_req)) begin + bankmachine7_next_state <= 1'd0; + end end 3'd5: begin + bankmachine7_next_state <= 3'd6; end 3'd6: begin + bankmachine7_next_state <= 2'd3; end 3'd7: begin + bankmachine7_next_state <= 4'd8; end 4'd8: begin + bankmachine7_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine6_refresh_req) begin + if (litedramcore_bankmachine7_refresh_req) begin + bankmachine7_next_state <= 3'd4; end else begin - if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine6_row_opened) begin - if (soc_sdram_bankmachine6_row_hit) begin - if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine6_req_wdata_ready <= soc_sdram_bankmachine6_cmd_ready; - end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin + bankmachine7_next_state <= 2'd2; end end else begin + bankmachine7_next_state <= 1'd1; end end else begin + bankmachine7_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_239 = dummy_s; + dummy_d_237 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_240; +reg dummy_d_238; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_req_rdata_valid <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9770,14 +9326,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine6_refresh_req) begin + if (litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine6_row_opened) begin - if (soc_sdram_bankmachine6_row_hit) begin - if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin end else begin - soc_sdram_bankmachine6_req_rdata_valid <= soc_sdram_bankmachine6_cmd_ready; + litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -9788,16 +9344,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_240 = dummy_s; + dummy_d_238 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_241; +reg dummy_d_239; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_refresh_gnt <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9805,8 +9361,8 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (soc_sdram_bankmachine6_twtpcon_ready) begin - soc_sdram_bankmachine6_refresh_gnt <= 1'd1; + if (litedramcore_bankmachine7_twtpcon_ready) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -9821,26 +9377,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_241 = dummy_s; + dummy_d_239 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_242; +reg dummy_d_240; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_cmd_valid <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (bankmachine7_state) 1'd1: begin - if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin - soc_sdram_bankmachine6_cmd_valid <= 1'd1; + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine6_trccon_ready) begin - soc_sdram_bankmachine6_cmd_valid <= 1'd1; + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; end end 3'd4: begin @@ -9854,12 +9410,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine6_refresh_req) begin + if (litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine6_row_opened) begin - if (soc_sdram_bankmachine6_row_hit) begin - soc_sdram_bankmachine6_cmd_valid <= 1'd1; + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; end else begin end end else begin @@ -9869,23 +9425,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_242 = dummy_s; + dummy_d_240 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_243; +reg dummy_d_241; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_row_open <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine7_row_open <= 1'd0; + case (bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine6_trccon_ready) begin - soc_sdram_bankmachine6_row_open <= 1'd1; + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_open <= 1'd1; end end 3'd4: begin @@ -9902,26 +9458,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_243 = dummy_s; + dummy_d_241 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_244; +reg dummy_d_242; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_row_close <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine7_row_close <= 1'd0; + case (bankmachine7_state) 1'd1: begin - soc_sdram_bankmachine6_row_close <= 1'd1; + litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin - soc_sdram_bankmachine6_row_close <= 1'd1; + litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_sdram_bankmachine6_row_close <= 1'd1; + litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9935,16 +9491,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_244 = dummy_s; + dummy_d_242 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_245; +reg dummy_d_243; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_cmd_payload_cas <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -9962,12 +9518,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine6_refresh_req) begin + if (litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine6_row_opened) begin - if (soc_sdram_bankmachine6_row_hit) begin - soc_sdram_bankmachine6_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -9977,210 +9533,55 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_245 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_246; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine6_cmd_payload_ras <= 1'd0; - case (vns_bankmachine6_state) - 1'd1: begin - if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin - soc_sdram_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_sdram_bankmachine6_trccon_ready) begin - soc_sdram_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_246 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine7_req_valid; -assign soc_sdram_bankmachine7_req_ready = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine7_req_we; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine7_req_addr; -assign soc_sdram_bankmachine7_cmd_buffer_sink_valid = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine7_cmd_buffer_sink_ready; -assign soc_sdram_bankmachine7_cmd_buffer_sink_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first; -assign soc_sdram_bankmachine7_cmd_buffer_sink_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last; -assign soc_sdram_bankmachine7_cmd_buffer_sink_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we; -assign soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -assign soc_sdram_bankmachine7_cmd_buffer_source_ready = (soc_sdram_bankmachine7_req_wdata_ready | soc_sdram_bankmachine7_req_rdata_valid); -assign soc_sdram_bankmachine7_req_lock = (soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine7_cmd_buffer_source_valid); -assign soc_sdram_bankmachine7_row_hit = (soc_sdram_bankmachine7_row == soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]); -assign soc_sdram_bankmachine7_cmd_payload_ba = 3'd7; - -// synthesis translate_off -reg dummy_d_247; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine7_cmd_payload_a <= 14'd0; - if (soc_sdram_bankmachine7_row_col_n_addr_sel) begin - soc_sdram_bankmachine7_cmd_payload_a <= soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_sdram_bankmachine7_cmd_payload_a <= ((soc_sdram_bankmachine7_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_247 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine7_twtpcon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_cmd_payload_is_write); -assign soc_sdram_bankmachine7_trccon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_row_open); -assign soc_sdram_bankmachine7_trascon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_row_open); - -// synthesis translate_off -reg dummy_d_248; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine7_auto_precharge <= 1'd0; - if ((soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine7_cmd_buffer_source_valid)) begin - if ((soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin - soc_sdram_bankmachine7_auto_precharge <= (soc_sdram_bankmachine7_row_close == 1'd0); - end - end -// synthesis translate_off - dummy_d_248 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_first; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_last; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_249; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_sdram_bankmachine7_cmd_buffer_lookahead_replace) begin - soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine7_cmd_buffer_lookahead_produce; - end -// synthesis translate_off - dummy_d_249 = dummy_s; + dummy_d_243 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_sdram_bankmachine7_cmd_buffer_lookahead_replace)); -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine7_cmd_buffer_lookahead_consume; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_sdram_bankmachine7_cmd_buffer_lookahead_level != 5'd16); -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_sdram_bankmachine7_cmd_buffer_lookahead_level != 1'd0); -assign soc_sdram_bankmachine7_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine7_cmd_buffer_source_valid) | soc_sdram_bankmachine7_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_250; +reg dummy_d_244; // synthesis translate_on always @(*) begin - vns_bankmachine7_next_state <= 4'd0; - vns_bankmachine7_next_state <= vns_bankmachine7_state; - case (vns_bankmachine7_state) + litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (bankmachine7_state) 1'd1: begin - if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin - if (soc_sdram_bankmachine7_cmd_ready) begin - vns_bankmachine7_next_state <= 3'd5; - end + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 2'd2: begin - if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin - vns_bankmachine7_next_state <= 3'd5; - end end 2'd3: begin - if (soc_sdram_bankmachine7_trccon_ready) begin - if (soc_sdram_bankmachine7_cmd_ready) begin - vns_bankmachine7_next_state <= 3'd7; - end + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 3'd4: begin - if ((~soc_sdram_bankmachine7_refresh_req)) begin - vns_bankmachine7_next_state <= 1'd0; - end end 3'd5: begin - vns_bankmachine7_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine7_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine7_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine7_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine7_refresh_req) begin - vns_bankmachine7_next_state <= 3'd4; - end else begin - if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine7_row_opened) begin - if (soc_sdram_bankmachine7_row_hit) begin - if ((soc_sdram_bankmachine7_cmd_ready & soc_sdram_bankmachine7_auto_precharge)) begin - vns_bankmachine7_next_state <= 2'd2; - end - end else begin - vns_bankmachine7_next_state <= 1'd1; - end - end else begin - vns_bankmachine7_next_state <= 2'd3; - end - end - end end endcase // synthesis translate_off - dummy_d_250 = dummy_s; + dummy_d_244 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_251; +reg dummy_d_245; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_cmd_payload_we <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (bankmachine7_state) 1'd1: begin - if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin - soc_sdram_bankmachine7_cmd_payload_we <= 1'd1; + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -10198,13 +9599,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine7_refresh_req) begin + if (litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine7_row_opened) begin - if (soc_sdram_bankmachine7_row_hit) begin - if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine7_cmd_payload_we <= 1'd1; + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -10216,26 +9617,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_251 = dummy_s; + dummy_d_245 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_252; +reg dummy_d_246; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine7_trccon_ready) begin - soc_sdram_bankmachine7_row_col_n_addr_sel <= 1'd1; + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -10249,30 +9654,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_252 = dummy_s; + dummy_d_246 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_253; +reg dummy_d_247; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (bankmachine7_state) 1'd1: begin - if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin - soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine7_trccon_ready) begin - soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin - soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -10286,16 +9687,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_253 = dummy_s; + dummy_d_247 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_254; +reg dummy_d_248; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -10313,14 +9714,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine7_refresh_req) begin + if (litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine7_row_opened) begin - if (soc_sdram_bankmachine7_row_hit) begin - if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin end else begin - soc_sdram_bankmachine7_cmd_payload_is_read <= 1'd1; + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -10331,16 +9732,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_254 = dummy_s; + dummy_d_248 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_255; +reg dummy_d_249; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -10358,13 +9759,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine7_refresh_req) begin + if (litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine7_row_opened) begin - if (soc_sdram_bankmachine7_row_hit) begin - if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine7_cmd_payload_is_write <= 1'd1; + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -10376,16 +9777,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_255 = dummy_s; + dummy_d_249 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_256; +reg dummy_d_250; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_req_wdata_ready <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -10403,13 +9804,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine7_refresh_req) begin + if (litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine7_row_opened) begin - if (soc_sdram_bankmachine7_row_hit) begin - if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine7_req_wdata_ready <= soc_sdram_bankmachine7_cmd_ready; + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; end else begin end end else begin @@ -10421,50 +9822,145 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_256 = dummy_s; + dummy_d_250 = dummy_s; // synthesis translate_on end +assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); +assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); +assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready); +assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read)); +assign litedramcore_cas_allowed = litedramcore_tccdcon_ready; +assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); +assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read)); +assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write)); +assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0); +assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0); +assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid; +assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt); +assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata}; +assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; +assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; +assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; +assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; +assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); +assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); +assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); +assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); // synthesis translate_off -reg dummy_d_257; +reg dummy_d_251; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_req_rdata_valid <= 1'd0; - case (vns_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_sdram_bankmachine7_refresh_req) begin - end else begin - if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine7_row_opened) begin - if (soc_sdram_bankmachine7_row_hit) begin - if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - soc_sdram_bankmachine7_req_rdata_valid <= soc_sdram_bankmachine7_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase + litedramcore_choose_cmd_valids <= 8'd0; + litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); +// synthesis translate_off + dummy_d_251 = dummy_s; +// synthesis translate_on +end +assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; +assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; +assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1; +assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2; +assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; +assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; +assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; + +// synthesis translate_off +reg dummy_d_252; +// synthesis translate_on +always @(*) begin + litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; + end +// synthesis translate_off + dummy_d_252 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_253; +// synthesis translate_on +always @(*) begin + litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; + end +// synthesis translate_off + dummy_d_253 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_254; +// synthesis translate_on +always @(*) begin + litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; + end +// synthesis translate_off + dummy_d_254 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_255; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_255 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_256; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_256 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_257; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready <= 1'd1; + end // synthesis translate_off dummy_d_257 = dummy_s; // synthesis translate_on @@ -10474,52 +9970,236 @@ end reg dummy_d_258; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_refresh_gnt <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_258 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_259; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_259 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_260; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_260 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_261; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_261 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_262; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready <= 1'd1; + end +// synthesis translate_off + dummy_d_262 = dummy_s; +// synthesis translate_on +end +assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); + +// synthesis translate_off +reg dummy_d_263; +// synthesis translate_on +always @(*) begin + litedramcore_choose_req_valids <= 8'd0; + litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); +// synthesis translate_off + dummy_d_263 = dummy_s; +// synthesis translate_on +end +assign litedramcore_choose_req_request = litedramcore_choose_req_valids; +assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6; +assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7; +assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8; +assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; +assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; +assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; + +// synthesis translate_off +reg dummy_d_264; +// synthesis translate_on +always @(*) begin + litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; + end +// synthesis translate_off + dummy_d_264 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_265; +// synthesis translate_on +always @(*) begin + litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; + end +// synthesis translate_off + dummy_d_265 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_266; +// synthesis translate_on +always @(*) begin + litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; + end +// synthesis translate_off + dummy_d_266 = dummy_s; +// synthesis translate_on +end +assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); +assign litedramcore_dfi_p0_reset_n = 1'd1; +assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}}; +assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}}; +assign litedramcore_dfi_p1_reset_n = 1'd1; +assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}}; +assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}}; +assign litedramcore_dfi_p2_reset_n = 1'd1; +assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}}; +assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}}; +assign litedramcore_dfi_p3_reset_n = 1'd1; +assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}}; +assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}}; +assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]); + +// synthesis translate_off +reg dummy_d_267; +// synthesis translate_on +always @(*) begin + multiplexer_next_state <= 4'd0; + multiplexer_next_state <= multiplexer_state; + case (multiplexer_state) 1'd1: begin + if (litedramcore_read_available) begin + if (((~litedramcore_write_available) | litedramcore_max_time1)) begin + multiplexer_next_state <= 2'd3; + end + end + if (litedramcore_go_to_refresh) begin + multiplexer_next_state <= 2'd2; + end end 2'd2: begin + if (litedramcore_cmd_last) begin + multiplexer_next_state <= 1'd0; + end end 2'd3: begin + if (litedramcore_twtrcon_ready) begin + multiplexer_next_state <= 1'd0; + end end 3'd4: begin - if (soc_sdram_bankmachine7_twtpcon_ready) begin - soc_sdram_bankmachine7_refresh_gnt <= 1'd1; - end + multiplexer_next_state <= 3'd5; end 3'd5: begin + multiplexer_next_state <= 3'd6; end 3'd6: begin + multiplexer_next_state <= 3'd7; end 3'd7: begin + multiplexer_next_state <= 4'd8; end 4'd8: begin + multiplexer_next_state <= 4'd9; + end + 4'd9: begin + multiplexer_next_state <= 4'd10; + end + 4'd10: begin + multiplexer_next_state <= 1'd1; end default: begin + if (litedramcore_write_available) begin + if (((~litedramcore_read_available) | litedramcore_max_time0)) begin + multiplexer_next_state <= 3'd4; + end + end + if (litedramcore_go_to_refresh) begin + multiplexer_next_state <= 2'd2; + end end endcase // synthesis translate_off - dummy_d_258 = dummy_s; + dummy_d_267 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_259; +reg dummy_d_268; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_cmd_valid <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_en0 <= 1'd0; + case (multiplexer_state) 1'd1: begin - if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin - soc_sdram_bankmachine7_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine7_trccon_ready) begin - soc_sdram_bankmachine7_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -10531,40 +10211,31 @@ always @(*) begin end 4'd8: begin end + 4'd9: begin + end + 4'd10: begin + end default: begin - if (soc_sdram_bankmachine7_refresh_req) begin - end else begin - if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine7_row_opened) begin - if (soc_sdram_bankmachine7_row_hit) begin - soc_sdram_bankmachine7_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end + litedramcore_en0 <= 1'd1; end endcase // synthesis translate_off - dummy_d_259 = dummy_s; + dummy_d_268 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_260; +reg dummy_d_269; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_row_open <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_cmd_ready <= 1'd0; + case (multiplexer_state) 1'd1: begin end 2'd2: begin + litedramcore_cmd_ready <= 1'd1; end 2'd3: begin - if (soc_sdram_bankmachine7_trccon_ready) begin - soc_sdram_bankmachine7_row_open <= 1'd1; - end end 3'd4: begin end @@ -10576,30 +10247,35 @@ always @(*) begin end 4'd8: begin end + 4'd9: begin + end + 4'd10: begin + end default: begin end endcase // synthesis translate_off - dummy_d_260 = dummy_s; + dummy_d_269 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_261; +reg dummy_d_270; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_row_close <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (multiplexer_state) 1'd1: begin - soc_sdram_bankmachine7_row_close <= 1'd1; + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end end 2'd2: begin - soc_sdram_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_sdram_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -10609,20 +10285,28 @@ always @(*) begin end 4'd8: begin end + 4'd9: begin + end + 4'd10: begin + end default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end end endcase // synthesis translate_off - dummy_d_261 = dummy_s; + dummy_d_270 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_262; +reg dummy_d_271; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_cmd_payload_cas <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_choose_req_want_reads <= 1'd0; + case (multiplexer_state) 1'd1: begin end 2'd2: begin @@ -10639,43 +10323,31 @@ always @(*) begin end 4'd8: begin end + 4'd9: begin + end + 4'd10: begin + end default: begin - if (soc_sdram_bankmachine7_refresh_req) begin - end else begin - if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine7_row_opened) begin - if (soc_sdram_bankmachine7_row_hit) begin - soc_sdram_bankmachine7_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end + litedramcore_choose_req_want_reads <= 1'd1; end endcase // synthesis translate_off - dummy_d_262 = dummy_s; + dummy_d_271 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_263; +reg dummy_d_272; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_cmd_payload_ras <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_choose_req_want_writes <= 1'd0; + case (multiplexer_state) 1'd1: begin - if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin - soc_sdram_bankmachine7_cmd_payload_ras <= 1'd1; - end + litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine7_trccon_ready) begin - soc_sdram_bankmachine7_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -10687,423 +10359,31 @@ always @(*) begin end 4'd8: begin end + 4'd9: begin + end + 4'd10: begin + end default: begin end endcase // synthesis translate_off - dummy_d_263 = dummy_s; + dummy_d_272 = dummy_s; // synthesis translate_on end -assign soc_sdram_trrdcon_valid = ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & ((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))); -assign soc_sdram_tfawcon_valid = ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & ((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))); -assign soc_sdram_ras_allowed = (soc_sdram_trrdcon_ready & soc_sdram_tfawcon_ready); -assign soc_sdram_tccdcon_valid = ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_cmd_payload_is_write | soc_sdram_choose_req_cmd_payload_is_read)); -assign soc_sdram_cas_allowed = soc_sdram_tccdcon_ready; -assign soc_sdram_twtrcon_valid = ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write); -assign soc_sdram_read_available = ((((((((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_payload_is_read) | (soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_payload_is_read)) | (soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_payload_is_read)) | (soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_payload_is_read)) | (soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_payload_is_read)) | (soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_payload_is_read)) | (soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_payload_is_read)) | (soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_payload_is_read)); -assign soc_sdram_write_available = ((((((((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_payload_is_write) | (soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_payload_is_write)) | (soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_payload_is_write)) | (soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_payload_is_write)) | (soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_payload_is_write)) | (soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_payload_is_write)) | (soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_payload_is_write)) | (soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_payload_is_write)); -assign soc_sdram_max_time0 = (soc_sdram_time0 == 1'd0); -assign soc_sdram_max_time1 = (soc_sdram_time1 == 1'd0); -assign soc_sdram_bankmachine0_refresh_req = soc_sdram_cmd_valid; -assign soc_sdram_bankmachine1_refresh_req = soc_sdram_cmd_valid; -assign soc_sdram_bankmachine2_refresh_req = soc_sdram_cmd_valid; -assign soc_sdram_bankmachine3_refresh_req = soc_sdram_cmd_valid; -assign soc_sdram_bankmachine4_refresh_req = soc_sdram_cmd_valid; -assign soc_sdram_bankmachine5_refresh_req = soc_sdram_cmd_valid; -assign soc_sdram_bankmachine6_refresh_req = soc_sdram_cmd_valid; -assign soc_sdram_bankmachine7_refresh_req = soc_sdram_cmd_valid; -assign soc_sdram_go_to_refresh = (((((((soc_sdram_bankmachine0_refresh_gnt & soc_sdram_bankmachine1_refresh_gnt) & soc_sdram_bankmachine2_refresh_gnt) & soc_sdram_bankmachine3_refresh_gnt) & soc_sdram_bankmachine4_refresh_gnt) & soc_sdram_bankmachine5_refresh_gnt) & soc_sdram_bankmachine6_refresh_gnt) & soc_sdram_bankmachine7_refresh_gnt); -assign soc_sdram_interface_rdata = {soc_sdram_dfi_p3_rddata, soc_sdram_dfi_p2_rddata, soc_sdram_dfi_p1_rddata, soc_sdram_dfi_p0_rddata}; -assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata; -assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata; -assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata; -assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata; -assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we); -assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we); -assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we); -assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we); // synthesis translate_off -reg dummy_d_264; +reg dummy_d_273; // synthesis translate_on always @(*) begin - soc_sdram_choose_cmd_valids <= 8'd0; - soc_sdram_choose_cmd_valids[0] <= (soc_sdram_bankmachine0_cmd_valid & (((soc_sdram_bankmachine0_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine0_cmd_payload_ras & (~soc_sdram_bankmachine0_cmd_payload_cas)) & (~soc_sdram_bankmachine0_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine0_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine0_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); - soc_sdram_choose_cmd_valids[1] <= (soc_sdram_bankmachine1_cmd_valid & (((soc_sdram_bankmachine1_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine1_cmd_payload_ras & (~soc_sdram_bankmachine1_cmd_payload_cas)) & (~soc_sdram_bankmachine1_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine1_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine1_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); - soc_sdram_choose_cmd_valids[2] <= (soc_sdram_bankmachine2_cmd_valid & (((soc_sdram_bankmachine2_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine2_cmd_payload_ras & (~soc_sdram_bankmachine2_cmd_payload_cas)) & (~soc_sdram_bankmachine2_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine2_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine2_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); - soc_sdram_choose_cmd_valids[3] <= (soc_sdram_bankmachine3_cmd_valid & (((soc_sdram_bankmachine3_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine3_cmd_payload_ras & (~soc_sdram_bankmachine3_cmd_payload_cas)) & (~soc_sdram_bankmachine3_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine3_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine3_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); - soc_sdram_choose_cmd_valids[4] <= (soc_sdram_bankmachine4_cmd_valid & (((soc_sdram_bankmachine4_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine4_cmd_payload_ras & (~soc_sdram_bankmachine4_cmd_payload_cas)) & (~soc_sdram_bankmachine4_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine4_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine4_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); - soc_sdram_choose_cmd_valids[5] <= (soc_sdram_bankmachine5_cmd_valid & (((soc_sdram_bankmachine5_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine5_cmd_payload_ras & (~soc_sdram_bankmachine5_cmd_payload_cas)) & (~soc_sdram_bankmachine5_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine5_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine5_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); - soc_sdram_choose_cmd_valids[6] <= (soc_sdram_bankmachine6_cmd_valid & (((soc_sdram_bankmachine6_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine6_cmd_payload_ras & (~soc_sdram_bankmachine6_cmd_payload_cas)) & (~soc_sdram_bankmachine6_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine6_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine6_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); - soc_sdram_choose_cmd_valids[7] <= (soc_sdram_bankmachine7_cmd_valid & (((soc_sdram_bankmachine7_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine7_cmd_payload_ras & (~soc_sdram_bankmachine7_cmd_payload_cas)) & (~soc_sdram_bankmachine7_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine7_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine7_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); -// synthesis translate_off - dummy_d_264 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_choose_cmd_request = soc_sdram_choose_cmd_valids; -assign soc_sdram_choose_cmd_cmd_valid = vns_rhs_array_muxed0; -assign soc_sdram_choose_cmd_cmd_payload_a = vns_rhs_array_muxed1; -assign soc_sdram_choose_cmd_cmd_payload_ba = vns_rhs_array_muxed2; -assign soc_sdram_choose_cmd_cmd_payload_is_read = vns_rhs_array_muxed3; -assign soc_sdram_choose_cmd_cmd_payload_is_write = vns_rhs_array_muxed4; -assign soc_sdram_choose_cmd_cmd_payload_is_cmd = vns_rhs_array_muxed5; - -// synthesis translate_off -reg dummy_d_265; -// synthesis translate_on -always @(*) begin - soc_sdram_choose_cmd_cmd_payload_cas <= 1'd0; - if (soc_sdram_choose_cmd_cmd_valid) begin - soc_sdram_choose_cmd_cmd_payload_cas <= vns_t_array_muxed0; - end -// synthesis translate_off - dummy_d_265 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_266; -// synthesis translate_on -always @(*) begin - soc_sdram_choose_cmd_cmd_payload_ras <= 1'd0; - if (soc_sdram_choose_cmd_cmd_valid) begin - soc_sdram_choose_cmd_cmd_payload_ras <= vns_t_array_muxed1; - end -// synthesis translate_off - dummy_d_266 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_267; -// synthesis translate_on -always @(*) begin - soc_sdram_choose_cmd_cmd_payload_we <= 1'd0; - if (soc_sdram_choose_cmd_cmd_valid) begin - soc_sdram_choose_cmd_cmd_payload_we <= vns_t_array_muxed2; - end -// synthesis translate_off - dummy_d_267 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_268; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine0_cmd_ready <= 1'd0; - if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 1'd0))) begin - soc_sdram_bankmachine0_cmd_ready <= 1'd1; - end - if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 1'd0))) begin - soc_sdram_bankmachine0_cmd_ready <= 1'd1; - end -// synthesis translate_off - dummy_d_268 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_269; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine1_cmd_ready <= 1'd0; - if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 1'd1))) begin - soc_sdram_bankmachine1_cmd_ready <= 1'd1; - end - if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 1'd1))) begin - soc_sdram_bankmachine1_cmd_ready <= 1'd1; - end -// synthesis translate_off - dummy_d_269 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_270; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine2_cmd_ready <= 1'd0; - if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 2'd2))) begin - soc_sdram_bankmachine2_cmd_ready <= 1'd1; - end - if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 2'd2))) begin - soc_sdram_bankmachine2_cmd_ready <= 1'd1; - end -// synthesis translate_off - dummy_d_270 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_271; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine3_cmd_ready <= 1'd0; - if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 2'd3))) begin - soc_sdram_bankmachine3_cmd_ready <= 1'd1; - end - if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 2'd3))) begin - soc_sdram_bankmachine3_cmd_ready <= 1'd1; - end -// synthesis translate_off - dummy_d_271 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_272; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine4_cmd_ready <= 1'd0; - if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd4))) begin - soc_sdram_bankmachine4_cmd_ready <= 1'd1; - end - if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd4))) begin - soc_sdram_bankmachine4_cmd_ready <= 1'd1; - end -// synthesis translate_off - dummy_d_272 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_273; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine5_cmd_ready <= 1'd0; - if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd5))) begin - soc_sdram_bankmachine5_cmd_ready <= 1'd1; - end - if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd5))) begin - soc_sdram_bankmachine5_cmd_ready <= 1'd1; - end -// synthesis translate_off - dummy_d_273 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_274; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine6_cmd_ready <= 1'd0; - if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd6))) begin - soc_sdram_bankmachine6_cmd_ready <= 1'd1; - end - if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd6))) begin - soc_sdram_bankmachine6_cmd_ready <= 1'd1; - end -// synthesis translate_off - dummy_d_274 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_275; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine7_cmd_ready <= 1'd0; - if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd7))) begin - soc_sdram_bankmachine7_cmd_ready <= 1'd1; - end - if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd7))) begin - soc_sdram_bankmachine7_cmd_ready <= 1'd1; - end -// synthesis translate_off - dummy_d_275 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_choose_cmd_ce = (soc_sdram_choose_cmd_cmd_ready | (~soc_sdram_choose_cmd_cmd_valid)); - -// synthesis translate_off -reg dummy_d_276; -// synthesis translate_on -always @(*) begin - soc_sdram_choose_req_valids <= 8'd0; - soc_sdram_choose_req_valids[0] <= (soc_sdram_bankmachine0_cmd_valid & (((soc_sdram_bankmachine0_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine0_cmd_payload_ras & (~soc_sdram_bankmachine0_cmd_payload_cas)) & (~soc_sdram_bankmachine0_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine0_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine0_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); - soc_sdram_choose_req_valids[1] <= (soc_sdram_bankmachine1_cmd_valid & (((soc_sdram_bankmachine1_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine1_cmd_payload_ras & (~soc_sdram_bankmachine1_cmd_payload_cas)) & (~soc_sdram_bankmachine1_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine1_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine1_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); - soc_sdram_choose_req_valids[2] <= (soc_sdram_bankmachine2_cmd_valid & (((soc_sdram_bankmachine2_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine2_cmd_payload_ras & (~soc_sdram_bankmachine2_cmd_payload_cas)) & (~soc_sdram_bankmachine2_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine2_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine2_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); - soc_sdram_choose_req_valids[3] <= (soc_sdram_bankmachine3_cmd_valid & (((soc_sdram_bankmachine3_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine3_cmd_payload_ras & (~soc_sdram_bankmachine3_cmd_payload_cas)) & (~soc_sdram_bankmachine3_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine3_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine3_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); - soc_sdram_choose_req_valids[4] <= (soc_sdram_bankmachine4_cmd_valid & (((soc_sdram_bankmachine4_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine4_cmd_payload_ras & (~soc_sdram_bankmachine4_cmd_payload_cas)) & (~soc_sdram_bankmachine4_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine4_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine4_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); - soc_sdram_choose_req_valids[5] <= (soc_sdram_bankmachine5_cmd_valid & (((soc_sdram_bankmachine5_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine5_cmd_payload_ras & (~soc_sdram_bankmachine5_cmd_payload_cas)) & (~soc_sdram_bankmachine5_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine5_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine5_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); - soc_sdram_choose_req_valids[6] <= (soc_sdram_bankmachine6_cmd_valid & (((soc_sdram_bankmachine6_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine6_cmd_payload_ras & (~soc_sdram_bankmachine6_cmd_payload_cas)) & (~soc_sdram_bankmachine6_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine6_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine6_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); - soc_sdram_choose_req_valids[7] <= (soc_sdram_bankmachine7_cmd_valid & (((soc_sdram_bankmachine7_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine7_cmd_payload_ras & (~soc_sdram_bankmachine7_cmd_payload_cas)) & (~soc_sdram_bankmachine7_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine7_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine7_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); -// synthesis translate_off - dummy_d_276 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_choose_req_request = soc_sdram_choose_req_valids; -assign soc_sdram_choose_req_cmd_valid = vns_rhs_array_muxed6; -assign soc_sdram_choose_req_cmd_payload_a = vns_rhs_array_muxed7; -assign soc_sdram_choose_req_cmd_payload_ba = vns_rhs_array_muxed8; -assign soc_sdram_choose_req_cmd_payload_is_read = vns_rhs_array_muxed9; -assign soc_sdram_choose_req_cmd_payload_is_write = vns_rhs_array_muxed10; -assign soc_sdram_choose_req_cmd_payload_is_cmd = vns_rhs_array_muxed11; - -// synthesis translate_off -reg dummy_d_277; -// synthesis translate_on -always @(*) begin - soc_sdram_choose_req_cmd_payload_cas <= 1'd0; - if (soc_sdram_choose_req_cmd_valid) begin - soc_sdram_choose_req_cmd_payload_cas <= vns_t_array_muxed3; - end -// synthesis translate_off - dummy_d_277 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_278; -// synthesis translate_on -always @(*) begin - soc_sdram_choose_req_cmd_payload_ras <= 1'd0; - if (soc_sdram_choose_req_cmd_valid) begin - soc_sdram_choose_req_cmd_payload_ras <= vns_t_array_muxed4; - end -// synthesis translate_off - dummy_d_278 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_279; -// synthesis translate_on -always @(*) begin - soc_sdram_choose_req_cmd_payload_we <= 1'd0; - if (soc_sdram_choose_req_cmd_valid) begin - soc_sdram_choose_req_cmd_payload_we <= vns_t_array_muxed5; - end -// synthesis translate_off - dummy_d_279 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_choose_req_ce = (soc_sdram_choose_req_cmd_ready | (~soc_sdram_choose_req_cmd_valid)); -assign soc_sdram_dfi_p0_reset_n = 1'd1; -assign soc_sdram_dfi_p0_cke = {1{soc_sdram_steerer0}}; -assign soc_sdram_dfi_p0_odt = {1{soc_sdram_steerer1}}; -assign soc_sdram_dfi_p1_reset_n = 1'd1; -assign soc_sdram_dfi_p1_cke = {1{soc_sdram_steerer2}}; -assign soc_sdram_dfi_p1_odt = {1{soc_sdram_steerer3}}; -assign soc_sdram_dfi_p2_reset_n = 1'd1; -assign soc_sdram_dfi_p2_cke = {1{soc_sdram_steerer4}}; -assign soc_sdram_dfi_p2_odt = {1{soc_sdram_steerer5}}; -assign soc_sdram_dfi_p3_reset_n = 1'd1; -assign soc_sdram_dfi_p3_cke = {1{soc_sdram_steerer6}}; -assign soc_sdram_dfi_p3_odt = {1{soc_sdram_steerer7}}; -assign soc_sdram_tfawcon_count = ((((soc_sdram_tfawcon_window[0] + soc_sdram_tfawcon_window[1]) + soc_sdram_tfawcon_window[2]) + soc_sdram_tfawcon_window[3]) + soc_sdram_tfawcon_window[4]); - -// synthesis translate_off -reg dummy_d_280; -// synthesis translate_on -always @(*) begin - vns_multiplexer_next_state <= 4'd0; - vns_multiplexer_next_state <= vns_multiplexer_state; - case (vns_multiplexer_state) + litedramcore_choose_req_cmd_ready <= 1'd0; + case (multiplexer_state) 1'd1: begin - if (soc_sdram_read_available) begin - if (((~soc_sdram_write_available) | soc_sdram_max_time1)) begin - vns_multiplexer_next_state <= 2'd3; - end - end - if (soc_sdram_go_to_refresh) begin - vns_multiplexer_next_state <= 2'd2; - end - end - 2'd2: begin - if (soc_sdram_cmd_last) begin - vns_multiplexer_next_state <= 1'd0; - end - end - 2'd3: begin - if (soc_sdram_twtrcon_ready) begin - vns_multiplexer_next_state <= 1'd0; - end - end - 3'd4: begin - vns_multiplexer_next_state <= 3'd5; - end - 3'd5: begin - vns_multiplexer_next_state <= 3'd6; - end - 3'd6: begin - vns_multiplexer_next_state <= 3'd7; - end - 3'd7: begin - vns_multiplexer_next_state <= 4'd8; - end - 4'd8: begin - vns_multiplexer_next_state <= 4'd9; - end - 4'd9: begin - vns_multiplexer_next_state <= 4'd10; - end - 4'd10: begin - vns_multiplexer_next_state <= 1'd1; - end - default: begin - if (soc_sdram_write_available) begin - if (((~soc_sdram_read_available) | soc_sdram_max_time0)) begin - vns_multiplexer_next_state <= 3'd4; - end - end - if (soc_sdram_go_to_refresh) begin - vns_multiplexer_next_state <= 2'd2; + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; end end - endcase -// synthesis translate_off - dummy_d_280 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_281; -// synthesis translate_on -always @(*) begin - soc_sdram_steerer_sel0 <= 2'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_sdram_steerer_sel0 <= 1'd0; - end - 2'd2: begin - soc_sdram_steerer_sel0 <= 2'd3; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_sdram_steerer_sel0 <= 1'd0; - end - endcase -// synthesis translate_off - dummy_d_281 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_282; -// synthesis translate_on -always @(*) begin - soc_sdram_steerer_sel1 <= 2'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_sdram_steerer_sel1 <= 1'd0; - end 2'd2: begin end 2'd3: begin @@ -11121,4875 +10401,3215 @@ always @(*) begin 4'd9: begin end 4'd10: begin - end - default: begin - soc_sdram_steerer_sel1 <= 1'd1; - end - endcase -// synthesis translate_off - dummy_d_282 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_283; -// synthesis translate_on -always @(*) begin - soc_sdram_steerer_sel2 <= 2'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_sdram_steerer_sel2 <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_sdram_steerer_sel2 <= 2'd2; - end - endcase -// synthesis translate_off - dummy_d_283 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_284; -// synthesis translate_on -always @(*) begin - soc_sdram_choose_cmd_want_activates <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - soc_sdram_choose_cmd_want_activates <= soc_sdram_ras_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - soc_sdram_choose_cmd_want_activates <= soc_sdram_ras_allowed; - end - end - endcase -// synthesis translate_off - dummy_d_284 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_285; -// synthesis translate_on -always @(*) begin - soc_sdram_steerer_sel3 <= 2'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_sdram_steerer_sel3 <= 2'd2; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_sdram_steerer_sel3 <= 1'd0; - end - endcase -// synthesis translate_off - dummy_d_285 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_286; -// synthesis translate_on -always @(*) begin - soc_sdram_en0 <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_sdram_en0 <= 1'd1; - end - endcase -// synthesis translate_off - dummy_d_286 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_287; -// synthesis translate_on -always @(*) begin - soc_sdram_cmd_ready <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - soc_sdram_cmd_ready <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_287 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_288; -// synthesis translate_on -always @(*) begin - soc_sdram_choose_cmd_cmd_ready <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - soc_sdram_choose_cmd_cmd_ready <= ((~((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))) | soc_sdram_ras_allowed); - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - soc_sdram_choose_cmd_cmd_ready <= ((~((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))) | soc_sdram_ras_allowed); - end - end - endcase -// synthesis translate_off - dummy_d_288 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_289; -// synthesis translate_on -always @(*) begin - soc_sdram_choose_req_want_reads <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_sdram_choose_req_want_reads <= 1'd1; - end - endcase -// synthesis translate_off - dummy_d_289 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_290; -// synthesis translate_on -always @(*) begin - soc_sdram_choose_req_want_writes <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_sdram_choose_req_want_writes <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_290 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_291; -// synthesis translate_on -always @(*) begin - soc_sdram_en1 <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_sdram_en1 <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_291 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_292; -// synthesis translate_on -always @(*) begin - soc_sdram_choose_req_cmd_ready <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - if (1'd0) begin - soc_sdram_choose_req_cmd_ready <= (soc_sdram_cas_allowed & ((~((soc_sdram_choose_req_cmd_payload_ras & (~soc_sdram_choose_req_cmd_payload_cas)) & (~soc_sdram_choose_req_cmd_payload_we))) | soc_sdram_ras_allowed)); - end else begin - soc_sdram_choose_req_cmd_ready <= soc_sdram_cas_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - soc_sdram_choose_req_cmd_ready <= (soc_sdram_cas_allowed & ((~((soc_sdram_choose_req_cmd_payload_ras & (~soc_sdram_choose_req_cmd_payload_cas)) & (~soc_sdram_choose_req_cmd_payload_we))) | soc_sdram_ras_allowed)); - end else begin - soc_sdram_choose_req_cmd_ready <= soc_sdram_cas_allowed; - end - end - endcase -// synthesis translate_off - dummy_d_292 = dummy_s; -// synthesis translate_on -end -assign vns_roundrobin0_request = {(((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; -assign vns_roundrobin0_ce = ((~soc_sdram_interface_bank0_valid) & (~soc_sdram_interface_bank0_lock)); -assign soc_sdram_interface_bank0_addr = vns_rhs_array_muxed12; -assign soc_sdram_interface_bank0_we = vns_rhs_array_muxed13; -assign soc_sdram_interface_bank0_valid = vns_rhs_array_muxed14; -assign vns_roundrobin1_request = {(((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; -assign vns_roundrobin1_ce = ((~soc_sdram_interface_bank1_valid) & (~soc_sdram_interface_bank1_lock)); -assign soc_sdram_interface_bank1_addr = vns_rhs_array_muxed15; -assign soc_sdram_interface_bank1_we = vns_rhs_array_muxed16; -assign soc_sdram_interface_bank1_valid = vns_rhs_array_muxed17; -assign vns_roundrobin2_request = {(((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; -assign vns_roundrobin2_ce = ((~soc_sdram_interface_bank2_valid) & (~soc_sdram_interface_bank2_lock)); -assign soc_sdram_interface_bank2_addr = vns_rhs_array_muxed18; -assign soc_sdram_interface_bank2_we = vns_rhs_array_muxed19; -assign soc_sdram_interface_bank2_valid = vns_rhs_array_muxed20; -assign vns_roundrobin3_request = {(((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; -assign vns_roundrobin3_ce = ((~soc_sdram_interface_bank3_valid) & (~soc_sdram_interface_bank3_lock)); -assign soc_sdram_interface_bank3_addr = vns_rhs_array_muxed21; -assign soc_sdram_interface_bank3_we = vns_rhs_array_muxed22; -assign soc_sdram_interface_bank3_valid = vns_rhs_array_muxed23; -assign vns_roundrobin4_request = {(((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; -assign vns_roundrobin4_ce = ((~soc_sdram_interface_bank4_valid) & (~soc_sdram_interface_bank4_lock)); -assign soc_sdram_interface_bank4_addr = vns_rhs_array_muxed24; -assign soc_sdram_interface_bank4_we = vns_rhs_array_muxed25; -assign soc_sdram_interface_bank4_valid = vns_rhs_array_muxed26; -assign vns_roundrobin5_request = {(((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; -assign vns_roundrobin5_ce = ((~soc_sdram_interface_bank5_valid) & (~soc_sdram_interface_bank5_lock)); -assign soc_sdram_interface_bank5_addr = vns_rhs_array_muxed27; -assign soc_sdram_interface_bank5_we = vns_rhs_array_muxed28; -assign soc_sdram_interface_bank5_valid = vns_rhs_array_muxed29; -assign vns_roundrobin6_request = {(((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; -assign vns_roundrobin6_ce = ((~soc_sdram_interface_bank6_valid) & (~soc_sdram_interface_bank6_lock)); -assign soc_sdram_interface_bank6_addr = vns_rhs_array_muxed30; -assign soc_sdram_interface_bank6_we = vns_rhs_array_muxed31; -assign soc_sdram_interface_bank6_valid = vns_rhs_array_muxed32; -assign vns_roundrobin7_request = {(((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_port_cmd_valid)}; -assign vns_roundrobin7_ce = ((~soc_sdram_interface_bank7_valid) & (~soc_sdram_interface_bank7_lock)); -assign soc_sdram_interface_bank7_addr = vns_rhs_array_muxed33; -assign soc_sdram_interface_bank7_we = vns_rhs_array_muxed34; -assign soc_sdram_interface_bank7_valid = vns_rhs_array_muxed35; -assign soc_port_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0)))))) & soc_sdram_interface_bank7_ready)); -assign soc_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1)))))) & soc_sdram_interface_bank7_ready)); -assign soc_port_wdata_ready = vns_new_master_wdata_ready2; -assign soc_wdata_ready = vns_new_master_wdata_ready5; -assign soc_port_rdata_valid = vns_new_master_rdata_valid8; -assign soc_rdata_valid = vns_new_master_rdata_valid17; - -// synthesis translate_off -reg dummy_d_293; -// synthesis translate_on -always @(*) begin - soc_sdram_interface_wdata <= 128'd0; - case ({vns_new_master_wdata_ready5, vns_new_master_wdata_ready2}) - 1'd1: begin - soc_sdram_interface_wdata <= soc_port_wdata_payload_data; - end - 2'd2: begin - soc_sdram_interface_wdata <= soc_wdata_payload_data; - end - default: begin - soc_sdram_interface_wdata <= 1'd0; - end - endcase -// synthesis translate_off - dummy_d_293 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_294; -// synthesis translate_on -always @(*) begin - soc_sdram_interface_wdata_we <= 16'd0; - case ({vns_new_master_wdata_ready5, vns_new_master_wdata_ready2}) - 1'd1: begin - soc_sdram_interface_wdata_we <= soc_port_wdata_payload_we; - end - 2'd2: begin - soc_sdram_interface_wdata_we <= soc_wdata_payload_we; - end - default: begin - soc_sdram_interface_wdata_we <= 1'd0; - end - endcase -// synthesis translate_off - dummy_d_294 = dummy_s; -// synthesis translate_on -end -assign soc_port_rdata_payload_data = soc_sdram_interface_rdata; -assign soc_rdata_payload_data = soc_sdram_interface_rdata; -assign soc_address_d = soc_wb_sdram_adr; -assign soc_counter_offset = soc_address_q; -assign soc_counter_done = ((soc_counter + soc_counter_offset) == 2'd3); -assign soc_end_of_burst = ((~soc_wb_sdram_cyc) | (((soc_wb_sdram_stb & soc_wb_sdram_cyc) & soc_wb_sdram_ack) & ((soc_wb_sdram_cti == 3'd7) | soc_counter_done))); -assign soc_need_refill_reset = soc_end_of_burst; -assign soc_need_refill_d = 1'd0; -assign soc_litedram_wb_cti = 3'd7; -assign soc_litedram_wb_adr = soc_address_q[29:2]; -assign soc_cached_sels_reset0 = soc_counter_reset; - -// synthesis translate_off -reg dummy_d_295; -// synthesis translate_on -always @(*) begin - soc_cached_datas_flipflop0_d <= 32'd0; - if (soc_write) begin - soc_cached_datas_flipflop0_d <= soc_wb_sdram_dat_w; - end else begin - soc_cached_datas_flipflop0_d <= soc_litedram_wb_dat_r[31:0]; - end -// synthesis translate_off - dummy_d_295 = dummy_s; -// synthesis translate_on -end -assign soc_cached_sels_flipflop0_d = soc_wb_sdram_sel; - -// synthesis translate_off -reg dummy_d_296; -// synthesis translate_on -always @(*) begin - soc_cached_datas_ce0 <= 1'd0; - if (((soc_write & soc_write_sel0) | soc_refill)) begin - soc_cached_datas_ce0 <= 1'd1; - end -// synthesis translate_off - dummy_d_296 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_297; -// synthesis translate_on -always @(*) begin - soc_cached_sels_ce0 <= 1'd0; - if (((soc_write & soc_write_sel0) | soc_refill)) begin - soc_cached_sels_ce0 <= 1'd1; - end -// synthesis translate_off - dummy_d_297 = dummy_s; -// synthesis translate_on -end -assign soc_cached_sels_reset1 = soc_counter_reset; - -// synthesis translate_off -reg dummy_d_298; -// synthesis translate_on -always @(*) begin - soc_cached_datas_flipflop1_d <= 32'd0; - if (soc_write) begin - soc_cached_datas_flipflop1_d <= soc_wb_sdram_dat_w; - end else begin - soc_cached_datas_flipflop1_d <= soc_litedram_wb_dat_r[63:32]; - end -// synthesis translate_off - dummy_d_298 = dummy_s; -// synthesis translate_on -end -assign soc_cached_sels_flipflop1_d = soc_wb_sdram_sel; - -// synthesis translate_off -reg dummy_d_299; -// synthesis translate_on -always @(*) begin - soc_cached_datas_ce1 <= 1'd0; - if (((soc_write & soc_write_sel1) | soc_refill)) begin - soc_cached_datas_ce1 <= 1'd1; - end -// synthesis translate_off - dummy_d_299 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_300; -// synthesis translate_on -always @(*) begin - soc_cached_sels_ce1 <= 1'd0; - if (((soc_write & soc_write_sel1) | soc_refill)) begin - soc_cached_sels_ce1 <= 1'd1; - end -// synthesis translate_off - dummy_d_300 = dummy_s; -// synthesis translate_on -end -assign soc_cached_sels_reset2 = soc_counter_reset; - -// synthesis translate_off -reg dummy_d_301; -// synthesis translate_on -always @(*) begin - soc_cached_datas_flipflop2_d <= 32'd0; - if (soc_write) begin - soc_cached_datas_flipflop2_d <= soc_wb_sdram_dat_w; - end else begin - soc_cached_datas_flipflop2_d <= soc_litedram_wb_dat_r[95:64]; - end -// synthesis translate_off - dummy_d_301 = dummy_s; -// synthesis translate_on -end -assign soc_cached_sels_flipflop2_d = soc_wb_sdram_sel; - -// synthesis translate_off -reg dummy_d_302; -// synthesis translate_on -always @(*) begin - soc_cached_datas_ce2 <= 1'd0; - if (((soc_write & soc_write_sel2) | soc_refill)) begin - soc_cached_datas_ce2 <= 1'd1; - end -// synthesis translate_off - dummy_d_302 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_303; -// synthesis translate_on -always @(*) begin - soc_cached_sels_ce2 <= 1'd0; - if (((soc_write & soc_write_sel2) | soc_refill)) begin - soc_cached_sels_ce2 <= 1'd1; - end -// synthesis translate_off - dummy_d_303 = dummy_s; -// synthesis translate_on -end -assign soc_cached_sels_reset3 = soc_counter_reset; - -// synthesis translate_off -reg dummy_d_304; -// synthesis translate_on -always @(*) begin - soc_cached_datas_flipflop3_d <= 32'd0; - if (soc_write) begin - soc_cached_datas_flipflop3_d <= soc_wb_sdram_dat_w; - end else begin - soc_cached_datas_flipflop3_d <= soc_litedram_wb_dat_r[127:96]; - end -// synthesis translate_off - dummy_d_304 = dummy_s; -// synthesis translate_on -end -assign soc_cached_sels_flipflop3_d = soc_wb_sdram_sel; - -// synthesis translate_off -reg dummy_d_305; -// synthesis translate_on -always @(*) begin - soc_cached_datas_ce3 <= 1'd0; - if (((soc_write & soc_write_sel3) | soc_refill)) begin - soc_cached_datas_ce3 <= 1'd1; - end -// synthesis translate_off - dummy_d_305 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_306; -// synthesis translate_on -always @(*) begin - soc_cached_sels_ce3 <= 1'd0; - if (((soc_write & soc_write_sel3) | soc_refill)) begin - soc_cached_sels_ce3 <= 1'd1; - end -// synthesis translate_off - dummy_d_306 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_307; -// synthesis translate_on -always @(*) begin - soc_write_sel2 <= 1'd0; - case ((soc_counter + soc_counter_offset)) - 1'd0: begin - end - 1'd1: begin - end - 2'd2: begin - soc_write_sel2 <= 1'd1; - end - 2'd3: begin - end - endcase -// synthesis translate_off - dummy_d_307 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_308; -// synthesis translate_on -always @(*) begin - soc_write_sel3 <= 1'd0; - case ((soc_counter + soc_counter_offset)) - 1'd0: begin - end - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - soc_write_sel3 <= 1'd1; - end - endcase -// synthesis translate_off - dummy_d_308 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_309; -// synthesis translate_on -always @(*) begin - soc_write_sel0 <= 1'd0; - case ((soc_counter + soc_counter_offset)) - 1'd0: begin - soc_write_sel0 <= 1'd1; - end - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - endcase -// synthesis translate_off - dummy_d_309 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_310; -// synthesis translate_on -always @(*) begin - soc_write_sel1 <= 1'd0; - case ((soc_counter + soc_counter_offset)) - 1'd0: begin - end - 1'd1: begin - soc_write_sel1 <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - endcase -// synthesis translate_off - dummy_d_310 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_311; -// synthesis translate_on -always @(*) begin - soc_wb_sdram_dat_r <= 32'd0; - case (soc_address_q[1:0]) - 1'd0: begin - soc_wb_sdram_dat_r <= soc_cached_datas_flipflop0_q; - end - 1'd1: begin - soc_wb_sdram_dat_r <= soc_cached_datas_flipflop1_q; - end - 2'd2: begin - soc_wb_sdram_dat_r <= soc_cached_datas_flipflop2_q; - end - 2'd3: begin - soc_wb_sdram_dat_r <= soc_cached_datas_flipflop3_q; - end - endcase -// synthesis translate_off - dummy_d_311 = dummy_s; -// synthesis translate_on -end -assign soc_cached_data = {soc_cached_datas_flipflop3_q, soc_cached_datas_flipflop2_q, soc_cached_datas_flipflop1_q, soc_cached_datas_flipflop0_q}; -assign soc_cached_sel = {soc_cached_sels_flipflop3_q, soc_cached_sels_flipflop2_q, soc_cached_sels_flipflop1_q, soc_cached_sels_flipflop0_q}; - -// synthesis translate_off -reg dummy_d_312; -// synthesis translate_on -always @(*) begin - vns_converter_next_state <= 3'd0; - vns_converter_next_state <= vns_converter_state; - case (vns_converter_state) - 1'd1: begin - if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin - if (soc_counter_done) begin - vns_converter_next_state <= 2'd2; - end - end else begin - if ((~soc_wb_sdram_cyc)) begin - vns_converter_next_state <= 2'd2; - end - end - end - 2'd2: begin - if (soc_litedram_wb_ack) begin - vns_converter_next_state <= 1'd0; - end - end - 2'd3: begin - if (soc_litedram_wb_ack) begin - vns_converter_next_state <= 3'd4; - end - end - 3'd4: begin - vns_converter_next_state <= 1'd0; - end - default: begin - if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin - if (soc_wb_sdram_we) begin - vns_converter_next_state <= 1'd1; - end else begin - if (soc_need_refill_q) begin - vns_converter_next_state <= 2'd3; - end else begin - vns_converter_next_state <= 3'd4; - end - end - end - end - endcase -// synthesis translate_off - dummy_d_312 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_313; -// synthesis translate_on -always @(*) begin - soc_address_ce <= 1'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - default: begin - if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin - soc_address_ce <= 1'd1; - end - end - endcase -// synthesis translate_off - dummy_d_313 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_314; -// synthesis translate_on -always @(*) begin - soc_litedram_wb_dat_w <= 128'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - soc_litedram_wb_dat_w <= soc_cached_data; - end - 2'd3: begin - end - 3'd4: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_314 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_315; -// synthesis translate_on -always @(*) begin - soc_litedram_wb_sel <= 16'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - soc_litedram_wb_sel <= soc_cached_sel; - end - 2'd3: begin - end - 3'd4: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_315 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_316; -// synthesis translate_on -always @(*) begin - soc_counter_ce <= 1'd0; - case (vns_converter_state) - 1'd1: begin - if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin - soc_counter_ce <= 1'd1; - end else begin - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_316 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_317; -// synthesis translate_on -always @(*) begin - soc_litedram_wb_cyc <= 1'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - soc_litedram_wb_cyc <= 1'd1; - end - 2'd3: begin - soc_litedram_wb_cyc <= 1'd1; - end - 3'd4: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_317 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_318; -// synthesis translate_on -always @(*) begin - soc_counter_reset <= 1'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - default: begin - soc_counter_reset <= 1'd1; - end - endcase -// synthesis translate_off - dummy_d_318 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_319; -// synthesis translate_on -always @(*) begin - soc_litedram_wb_stb <= 1'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - soc_litedram_wb_stb <= 1'd1; - end - 2'd3: begin - soc_litedram_wb_stb <= 1'd1; - end - 3'd4: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_319 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_320; -// synthesis translate_on -always @(*) begin - soc_need_refill_ce <= 1'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedram_wb_ack) begin - soc_need_refill_ce <= 1'd1; - end - end - 3'd4: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_320 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_321; -// synthesis translate_on -always @(*) begin - soc_litedram_wb_we <= 1'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - soc_litedram_wb_we <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_321 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_322; -// synthesis translate_on -always @(*) begin - soc_write <= 1'd0; - case (vns_converter_state) - 1'd1: begin - if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin - soc_write <= 1'd1; - end else begin - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_322 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_323; -// synthesis translate_on -always @(*) begin - soc_wb_sdram_ack <= 1'd0; - case (vns_converter_state) - 1'd1: begin - if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin - soc_wb_sdram_ack <= 1'd1; - end else begin - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin - soc_wb_sdram_ack <= 1'd1; - end - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_323 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_324; -// synthesis translate_on -always @(*) begin - soc_evict <= 1'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - soc_evict <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_324 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_325; -// synthesis translate_on -always @(*) begin - soc_refill <= 1'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - soc_refill <= 1'd1; - end - 3'd4: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_325 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_326; -// synthesis translate_on -always @(*) begin - soc_read <= 1'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - soc_read <= 1'd1; - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_326 = dummy_s; -// synthesis translate_on -end -assign soc_wdata_converter_sink_valid = ((soc_litedram_wb_cyc & soc_litedram_wb_stb) & soc_litedram_wb_we); -assign soc_wdata_converter_sink_payload_data = soc_litedram_wb_dat_w; -assign soc_wdata_converter_sink_payload_we = soc_litedram_wb_sel; -assign soc_port_wdata_valid = soc_wdata_converter_source_valid; -assign soc_wdata_converter_source_ready = soc_port_wdata_ready; -assign soc_port_wdata_first = soc_wdata_converter_source_first; -assign soc_port_wdata_last = soc_wdata_converter_source_last; -assign soc_port_wdata_payload_data = soc_wdata_converter_source_payload_data; -assign soc_port_wdata_payload_we = soc_wdata_converter_source_payload_we; -assign soc_rdata_converter_sink_valid = soc_port_rdata_valid; -assign soc_port_rdata_ready = soc_rdata_converter_sink_ready; -assign soc_rdata_converter_sink_first = soc_port_rdata_first; -assign soc_rdata_converter_sink_last = soc_port_rdata_last; -assign soc_rdata_converter_sink_payload_data = soc_port_rdata_payload_data; -assign soc_rdata_converter_source_ready = 1'd1; -assign soc_litedram_wb_dat_r = soc_rdata_converter_source_payload_data; -assign soc_wdata_converter_converter_sink_valid = soc_wdata_converter_sink_valid; -assign soc_wdata_converter_converter_sink_first = soc_wdata_converter_sink_first; -assign soc_wdata_converter_converter_sink_last = soc_wdata_converter_sink_last; -assign soc_wdata_converter_sink_ready = soc_wdata_converter_converter_sink_ready; -assign soc_wdata_converter_converter_sink_payload_data = {soc_wdata_converter_sink_payload_we, soc_wdata_converter_sink_payload_data}; -assign soc_wdata_converter_source_valid = soc_wdata_converter_source_source_valid; -assign soc_wdata_converter_source_first = soc_wdata_converter_source_source_first; -assign soc_wdata_converter_source_last = soc_wdata_converter_source_source_last; -assign soc_wdata_converter_source_source_ready = soc_wdata_converter_source_ready; -assign {soc_wdata_converter_source_payload_we, soc_wdata_converter_source_payload_data} = soc_wdata_converter_source_source_payload_data; -assign {soc_wdata_converter_source_payload_we, soc_wdata_converter_source_payload_data} = soc_wdata_converter_source_source_payload_data; -assign soc_wdata_converter_source_source_valid = soc_wdata_converter_converter_source_valid; -assign soc_wdata_converter_converter_source_ready = soc_wdata_converter_source_source_ready; -assign soc_wdata_converter_source_source_first = soc_wdata_converter_converter_source_first; -assign soc_wdata_converter_source_source_last = soc_wdata_converter_converter_source_last; -assign soc_wdata_converter_source_source_payload_data = soc_wdata_converter_converter_source_payload_data; -assign soc_wdata_converter_converter_source_valid = soc_wdata_converter_converter_sink_valid; -assign soc_wdata_converter_converter_sink_ready = soc_wdata_converter_converter_source_ready; -assign soc_wdata_converter_converter_source_first = soc_wdata_converter_converter_sink_first; -assign soc_wdata_converter_converter_source_last = soc_wdata_converter_converter_sink_last; -assign soc_wdata_converter_converter_source_payload_data = soc_wdata_converter_converter_sink_payload_data; -assign soc_wdata_converter_converter_source_payload_valid_token_count = 1'd1; -assign soc_rdata_converter_converter_sink_valid = soc_rdata_converter_sink_valid; -assign soc_rdata_converter_converter_sink_first = soc_rdata_converter_sink_first; -assign soc_rdata_converter_converter_sink_last = soc_rdata_converter_sink_last; -assign soc_rdata_converter_sink_ready = soc_rdata_converter_converter_sink_ready; -assign soc_rdata_converter_converter_sink_payload_data = {soc_rdata_converter_sink_payload_data}; -assign soc_rdata_converter_source_valid = soc_rdata_converter_source_source_valid; -assign soc_rdata_converter_source_first = soc_rdata_converter_source_source_first; -assign soc_rdata_converter_source_last = soc_rdata_converter_source_source_last; -assign soc_rdata_converter_source_source_ready = soc_rdata_converter_source_ready; -assign {soc_rdata_converter_source_payload_data} = soc_rdata_converter_source_source_payload_data; -assign soc_rdata_converter_source_source_valid = soc_rdata_converter_converter_source_valid; -assign soc_rdata_converter_converter_source_ready = soc_rdata_converter_source_source_ready; -assign soc_rdata_converter_source_source_first = soc_rdata_converter_converter_source_first; -assign soc_rdata_converter_source_source_last = soc_rdata_converter_converter_source_last; -assign soc_rdata_converter_source_source_payload_data = soc_rdata_converter_converter_source_payload_data; -assign soc_rdata_converter_converter_source_valid = soc_rdata_converter_converter_sink_valid; -assign soc_rdata_converter_converter_sink_ready = soc_rdata_converter_converter_source_ready; -assign soc_rdata_converter_converter_source_first = soc_rdata_converter_converter_sink_first; -assign soc_rdata_converter_converter_source_last = soc_rdata_converter_converter_sink_last; -assign soc_rdata_converter_converter_source_payload_data = soc_rdata_converter_converter_sink_payload_data; -assign soc_rdata_converter_converter_source_payload_valid_token_count = 1'd1; - -// synthesis translate_off -reg dummy_d_327; -// synthesis translate_on -always @(*) begin - vns_litedramwishbone2native_next_state <= 2'd0; - vns_litedramwishbone2native_next_state <= vns_litedramwishbone2native_state; - case (vns_litedramwishbone2native_state) - 1'd1: begin - if (soc_wdata_converter_sink_ready) begin - vns_litedramwishbone2native_next_state <= 1'd0; - end - end - 2'd2: begin - if (soc_rdata_converter_source_valid) begin - vns_litedramwishbone2native_next_state <= 1'd0; - end - end - default: begin - if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin - if ((soc_count == 1'd0)) begin - if (soc_litedram_wb_we) begin - vns_litedramwishbone2native_next_state <= 1'd1; - end else begin - vns_litedramwishbone2native_next_state <= 2'd2; - end - end - end - end - endcase -// synthesis translate_off - dummy_d_327 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_328; -// synthesis translate_on -always @(*) begin - soc_count_next_value <= 1'd0; - case (vns_litedramwishbone2native_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin - soc_count_next_value <= (soc_count + 1'd1); - if ((soc_count == 1'd0)) begin - soc_count_next_value <= 1'd0; - end - end - end - endcase -// synthesis translate_off - dummy_d_328 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_329; -// synthesis translate_on -always @(*) begin - soc_count_next_value_ce <= 1'd0; - case (vns_litedramwishbone2native_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin - soc_count_next_value_ce <= 1'd1; - if ((soc_count == 1'd0)) begin - soc_count_next_value_ce <= 1'd1; - end - end - end - endcase -// synthesis translate_off - dummy_d_329 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_330; -// synthesis translate_on -always @(*) begin - soc_port_cmd_valid <= 1'd0; - case (vns_litedramwishbone2native_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - soc_port_cmd_valid <= (soc_litedram_wb_cyc & soc_litedram_wb_stb); - end - endcase -// synthesis translate_off - dummy_d_330 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_331; -// synthesis translate_on -always @(*) begin - soc_litedram_wb_ack <= 1'd0; - case (vns_litedramwishbone2native_state) - 1'd1: begin - if (soc_wdata_converter_sink_ready) begin - soc_litedram_wb_ack <= 1'd1; - end - end - 2'd2: begin - if (soc_rdata_converter_source_valid) begin - soc_litedram_wb_ack <= 1'd1; - end - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_331 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_332; -// synthesis translate_on -always @(*) begin - soc_port_cmd_payload_we <= 1'd0; - case (vns_litedramwishbone2native_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - soc_port_cmd_payload_we <= soc_litedram_wb_we; - end - endcase -// synthesis translate_off - dummy_d_332 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_333; -// synthesis translate_on -always @(*) begin - soc_port_cmd_payload_addr <= 24'd0; - case (vns_litedramwishbone2native_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - soc_port_cmd_payload_addr <= (((soc_litedram_wb_adr * 1'd1) + soc_count) - 27'd67108864); - end - endcase -// synthesis translate_off - dummy_d_333 = dummy_s; -// synthesis translate_on -end -assign vns_shared_adr = vns_rhs_array_muxed36; -assign vns_shared_dat_w = vns_rhs_array_muxed37; -assign vns_shared_sel = vns_rhs_array_muxed38; -assign vns_shared_cyc = vns_rhs_array_muxed39; -assign vns_shared_stb = vns_rhs_array_muxed40; -assign vns_shared_we = vns_rhs_array_muxed41; -assign vns_shared_cti = vns_rhs_array_muxed42; -assign vns_shared_bte = vns_rhs_array_muxed43; -assign soc_litedramcore_cpu_ibus_dat_r = vns_shared_dat_r; -assign soc_litedramcore_cpu_dbus_dat_r = vns_shared_dat_r; -assign soc_litedramcore_cpu_ibus_ack = (vns_shared_ack & (vns_grant == 1'd0)); -assign soc_litedramcore_cpu_dbus_ack = (vns_shared_ack & (vns_grant == 1'd1)); -assign soc_litedramcore_cpu_ibus_err = (vns_shared_err & (vns_grant == 1'd0)); -assign soc_litedramcore_cpu_dbus_err = (vns_shared_err & (vns_grant == 1'd1)); -assign vns_request = {soc_litedramcore_cpu_dbus_cyc, soc_litedramcore_cpu_ibus_cyc}; - -// synthesis translate_off -reg dummy_d_334; -// synthesis translate_on -always @(*) begin - vns_slave_sel <= 4'd0; - vns_slave_sel[0] <= (vns_shared_adr[29:13] == 1'd0); - vns_slave_sel[1] <= (vns_shared_adr[29:10] == 13'd4096); - vns_slave_sel[2] <= (vns_shared_adr[29:14] == 16'd33280); - vns_slave_sel[3] <= (vns_shared_adr[29:22] == 7'd64); -// synthesis translate_off - dummy_d_334 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_litedramcore_ram_bus_adr = vns_shared_adr; -assign soc_litedramcore_litedramcore_ram_bus_dat_w = vns_shared_dat_w; -assign soc_litedramcore_litedramcore_ram_bus_sel = vns_shared_sel; -assign soc_litedramcore_litedramcore_ram_bus_stb = vns_shared_stb; -assign soc_litedramcore_litedramcore_ram_bus_we = vns_shared_we; -assign soc_litedramcore_litedramcore_ram_bus_cti = vns_shared_cti; -assign soc_litedramcore_litedramcore_ram_bus_bte = vns_shared_bte; -assign soc_litedramcore_ram_bus_ram_bus_adr = vns_shared_adr; -assign soc_litedramcore_ram_bus_ram_bus_dat_w = vns_shared_dat_w; -assign soc_litedramcore_ram_bus_ram_bus_sel = vns_shared_sel; -assign soc_litedramcore_ram_bus_ram_bus_stb = vns_shared_stb; -assign soc_litedramcore_ram_bus_ram_bus_we = vns_shared_we; -assign soc_litedramcore_ram_bus_ram_bus_cti = vns_shared_cti; -assign soc_litedramcore_ram_bus_ram_bus_bte = vns_shared_bte; -assign soc_litedramcore_bus_wishbone_adr = vns_shared_adr; -assign soc_litedramcore_bus_wishbone_dat_w = vns_shared_dat_w; -assign soc_litedramcore_bus_wishbone_sel = vns_shared_sel; -assign soc_litedramcore_bus_wishbone_stb = vns_shared_stb; -assign soc_litedramcore_bus_wishbone_we = vns_shared_we; -assign soc_litedramcore_bus_wishbone_cti = vns_shared_cti; -assign soc_litedramcore_bus_wishbone_bte = vns_shared_bte; -assign soc_wb_sdram_adr = vns_shared_adr; -assign soc_wb_sdram_dat_w = vns_shared_dat_w; -assign soc_wb_sdram_sel = vns_shared_sel; -assign soc_wb_sdram_stb = vns_shared_stb; -assign soc_wb_sdram_we = vns_shared_we; -assign soc_wb_sdram_cti = vns_shared_cti; -assign soc_wb_sdram_bte = vns_shared_bte; -assign soc_litedramcore_litedramcore_ram_bus_cyc = (vns_shared_cyc & vns_slave_sel[0]); -assign soc_litedramcore_ram_bus_ram_bus_cyc = (vns_shared_cyc & vns_slave_sel[1]); -assign soc_litedramcore_bus_wishbone_cyc = (vns_shared_cyc & vns_slave_sel[2]); -assign soc_wb_sdram_cyc = (vns_shared_cyc & vns_slave_sel[3]); - -// synthesis translate_off -reg dummy_d_335; -// synthesis translate_on -always @(*) begin - vns_shared_ack <= 1'd0; - vns_shared_ack <= (((soc_litedramcore_litedramcore_ram_bus_ack | soc_litedramcore_ram_bus_ram_bus_ack) | soc_litedramcore_bus_wishbone_ack) | soc_wb_sdram_ack); - if (vns_done) begin - vns_shared_ack <= 1'd1; - end -// synthesis translate_off - dummy_d_335 = dummy_s; -// synthesis translate_on -end -assign vns_shared_err = (((soc_litedramcore_litedramcore_ram_bus_err | soc_litedramcore_ram_bus_ram_bus_err) | soc_litedramcore_bus_wishbone_err) | soc_wb_sdram_err); - -// synthesis translate_off -reg dummy_d_336; -// synthesis translate_on -always @(*) begin - vns_shared_dat_r <= 32'd0; - vns_shared_dat_r <= (((({32{vns_slave_sel_r[0]}} & soc_litedramcore_litedramcore_ram_bus_dat_r) | ({32{vns_slave_sel_r[1]}} & soc_litedramcore_ram_bus_ram_bus_dat_r)) | ({32{vns_slave_sel_r[2]}} & soc_litedramcore_bus_wishbone_dat_r)) | ({32{vns_slave_sel_r[3]}} & soc_wb_sdram_dat_r)); - if (vns_done) begin - vns_shared_dat_r <= 32'd4294967295; - end -// synthesis translate_off - dummy_d_336 = dummy_s; -// synthesis translate_on -end -assign vns_wait = ((vns_shared_stb & vns_shared_cyc) & (~vns_shared_ack)); - -// synthesis translate_off -reg dummy_d_337; -// synthesis translate_on -always @(*) begin - vns_error <= 1'd0; - if (vns_done) begin - vns_error <= 1'd1; - end + end + default: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end + end + endcase // synthesis translate_off - dummy_d_337 = dummy_s; + dummy_d_273 = dummy_s; // synthesis translate_on end -assign vns_done = (vns_count == 1'd0); -assign vns_csrbank0_sel = (vns_interface0_bank_bus_adr[13:9] == 1'd0); -assign vns_csrbank0_reset0_r = vns_interface0_bank_bus_dat_w[0]; -assign vns_csrbank0_reset0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 1'd0)); -assign vns_csrbank0_reset0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 1'd0)); -assign vns_csrbank0_scratch3_r = vns_interface0_bank_bus_dat_w[7:0]; -assign vns_csrbank0_scratch3_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 1'd1)); -assign vns_csrbank0_scratch3_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 1'd1)); -assign vns_csrbank0_scratch2_r = vns_interface0_bank_bus_dat_w[7:0]; -assign vns_csrbank0_scratch2_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 2'd2)); -assign vns_csrbank0_scratch2_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 2'd2)); -assign vns_csrbank0_scratch1_r = vns_interface0_bank_bus_dat_w[7:0]; -assign vns_csrbank0_scratch1_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 2'd3)); -assign vns_csrbank0_scratch1_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 2'd3)); -assign vns_csrbank0_scratch0_r = vns_interface0_bank_bus_dat_w[7:0]; -assign vns_csrbank0_scratch0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd4)); -assign vns_csrbank0_scratch0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd4)); -assign vns_csrbank0_bus_errors3_r = vns_interface0_bank_bus_dat_w[7:0]; -assign vns_csrbank0_bus_errors3_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd5)); -assign vns_csrbank0_bus_errors3_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd5)); -assign vns_csrbank0_bus_errors2_r = vns_interface0_bank_bus_dat_w[7:0]; -assign vns_csrbank0_bus_errors2_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd6)); -assign vns_csrbank0_bus_errors2_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd6)); -assign vns_csrbank0_bus_errors1_r = vns_interface0_bank_bus_dat_w[7:0]; -assign vns_csrbank0_bus_errors1_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd7)); -assign vns_csrbank0_bus_errors1_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd7)); -assign vns_csrbank0_bus_errors0_r = vns_interface0_bank_bus_dat_w[7:0]; -assign vns_csrbank0_bus_errors0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 4'd8)); -assign vns_csrbank0_bus_errors0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 4'd8)); -assign vns_csrbank0_reset0_w = soc_litedramcore_soccontroller_reset_storage; -assign vns_csrbank0_scratch3_w = soc_litedramcore_soccontroller_scratch_storage[31:24]; -assign vns_csrbank0_scratch2_w = soc_litedramcore_soccontroller_scratch_storage[23:16]; -assign vns_csrbank0_scratch1_w = soc_litedramcore_soccontroller_scratch_storage[15:8]; -assign vns_csrbank0_scratch0_w = soc_litedramcore_soccontroller_scratch_storage[7:0]; -assign vns_csrbank0_bus_errors3_w = soc_litedramcore_soccontroller_bus_errors_status[31:24]; -assign vns_csrbank0_bus_errors2_w = soc_litedramcore_soccontroller_bus_errors_status[23:16]; -assign vns_csrbank0_bus_errors1_w = soc_litedramcore_soccontroller_bus_errors_status[15:8]; -assign vns_csrbank0_bus_errors0_w = soc_litedramcore_soccontroller_bus_errors_status[7:0]; -assign soc_litedramcore_soccontroller_bus_errors_we = vns_csrbank0_bus_errors0_we; -assign vns_csrbank1_sel = (vns_interface1_bank_bus_adr[13:9] == 3'd7); -assign vns_csrbank1_init_done0_r = vns_interface1_bank_bus_dat_w[0]; -assign vns_csrbank1_init_done0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[0] == 1'd0)); -assign vns_csrbank1_init_done0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[0] == 1'd0)); -assign vns_csrbank1_init_error0_r = vns_interface1_bank_bus_dat_w[0]; -assign vns_csrbank1_init_error0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[0] == 1'd1)); -assign vns_csrbank1_init_error0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[0] == 1'd1)); -assign vns_csrbank1_init_done0_w = soc_init_done_storage; -assign vns_csrbank1_init_error0_w = soc_init_error_storage; -assign vns_csrbank2_sel = (vns_interface2_bank_bus_adr[13:9] == 3'd5); -assign vns_csrbank2_half_sys8x_taps0_r = vns_interface2_bank_bus_dat_w[4:0]; -assign vns_csrbank2_half_sys8x_taps0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 1'd0)); -assign vns_csrbank2_half_sys8x_taps0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 1'd0)); -assign vns_csrbank2_wlevel_en0_r = vns_interface2_bank_bus_dat_w[0]; -assign vns_csrbank2_wlevel_en0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 1'd1)); -assign vns_csrbank2_wlevel_en0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 1'd1)); -assign soc_a7ddrphy_wlevel_strobe_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_a7ddrphy_wlevel_strobe_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 2'd2)); -assign soc_a7ddrphy_wlevel_strobe_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 2'd2)); -assign soc_a7ddrphy_cdly_rst_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_a7ddrphy_cdly_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 2'd3)); -assign soc_a7ddrphy_cdly_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 2'd3)); -assign soc_a7ddrphy_cdly_inc_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_a7ddrphy_cdly_inc_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd4)); -assign soc_a7ddrphy_cdly_inc_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd4)); -assign vns_csrbank2_dly_sel0_r = vns_interface2_bank_bus_dat_w[1:0]; -assign vns_csrbank2_dly_sel0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd5)); -assign vns_csrbank2_dly_sel0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd5)); -assign soc_a7ddrphy_rdly_dq_rst_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_a7ddrphy_rdly_dq_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd6)); -assign soc_a7ddrphy_rdly_dq_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd6)); -assign soc_a7ddrphy_rdly_dq_inc_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_a7ddrphy_rdly_dq_inc_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd7)); -assign soc_a7ddrphy_rdly_dq_inc_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd7)); -assign soc_a7ddrphy_rdly_dq_bitslip_rst_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_a7ddrphy_rdly_dq_bitslip_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 4'd8)); -assign soc_a7ddrphy_rdly_dq_bitslip_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 4'd8)); -assign soc_a7ddrphy_rdly_dq_bitslip_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_a7ddrphy_rdly_dq_bitslip_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 4'd9)); -assign soc_a7ddrphy_rdly_dq_bitslip_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 4'd9)); -assign vns_csrbank2_half_sys8x_taps0_w = soc_a7ddrphy_half_sys8x_taps_storage[4:0]; -assign vns_csrbank2_wlevel_en0_w = soc_a7ddrphy_wlevel_en_storage; -assign vns_csrbank2_dly_sel0_w = soc_a7ddrphy_dly_sel_storage[1:0]; -assign vns_csrbank3_sel = (vns_interface3_bank_bus_adr[13:9] == 3'd6); -assign vns_csrbank3_dfii_control0_r = vns_interface3_bank_bus_dat_w[3:0]; -assign vns_csrbank3_dfii_control0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 1'd0)); -assign vns_csrbank3_dfii_control0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 1'd0)); -assign vns_csrbank3_dfii_pi0_command0_r = vns_interface3_bank_bus_dat_w[5:0]; -assign vns_csrbank3_dfii_pi0_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 1'd1)); -assign vns_csrbank3_dfii_pi0_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 1'd1)); -assign soc_sdram_phaseinjector0_command_issue_r = vns_interface3_bank_bus_dat_w[0]; -assign soc_sdram_phaseinjector0_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 2'd2)); -assign soc_sdram_phaseinjector0_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 2'd2)); -assign vns_csrbank3_dfii_pi0_address1_r = vns_interface3_bank_bus_dat_w[5:0]; -assign vns_csrbank3_dfii_pi0_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 2'd3)); -assign vns_csrbank3_dfii_pi0_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 2'd3)); -assign vns_csrbank3_dfii_pi0_address0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi0_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd4)); -assign vns_csrbank3_dfii_pi0_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd4)); -assign vns_csrbank3_dfii_pi0_baddress0_r = vns_interface3_bank_bus_dat_w[2:0]; -assign vns_csrbank3_dfii_pi0_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd5)); -assign vns_csrbank3_dfii_pi0_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd5)); -assign vns_csrbank3_dfii_pi0_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi0_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd6)); -assign vns_csrbank3_dfii_pi0_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd6)); -assign vns_csrbank3_dfii_pi0_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi0_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd7)); -assign vns_csrbank3_dfii_pi0_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd7)); -assign vns_csrbank3_dfii_pi0_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi0_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd8)); -assign vns_csrbank3_dfii_pi0_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd8)); -assign vns_csrbank3_dfii_pi0_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi0_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd9)); -assign vns_csrbank3_dfii_pi0_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd9)); -assign vns_csrbank3_dfii_pi0_rddata3_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi0_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd10)); -assign vns_csrbank3_dfii_pi0_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd10)); -assign vns_csrbank3_dfii_pi0_rddata2_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi0_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd11)); -assign vns_csrbank3_dfii_pi0_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd11)); -assign vns_csrbank3_dfii_pi0_rddata1_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi0_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd12)); -assign vns_csrbank3_dfii_pi0_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd12)); -assign vns_csrbank3_dfii_pi0_rddata0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi0_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd13)); -assign vns_csrbank3_dfii_pi0_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd13)); -assign vns_csrbank3_dfii_pi1_command0_r = vns_interface3_bank_bus_dat_w[5:0]; -assign vns_csrbank3_dfii_pi1_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd14)); -assign vns_csrbank3_dfii_pi1_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd14)); -assign soc_sdram_phaseinjector1_command_issue_r = vns_interface3_bank_bus_dat_w[0]; -assign soc_sdram_phaseinjector1_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd15)); -assign soc_sdram_phaseinjector1_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd15)); -assign vns_csrbank3_dfii_pi1_address1_r = vns_interface3_bank_bus_dat_w[5:0]; -assign vns_csrbank3_dfii_pi1_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd16)); -assign vns_csrbank3_dfii_pi1_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd16)); -assign vns_csrbank3_dfii_pi1_address0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi1_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd17)); -assign vns_csrbank3_dfii_pi1_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd17)); -assign vns_csrbank3_dfii_pi1_baddress0_r = vns_interface3_bank_bus_dat_w[2:0]; -assign vns_csrbank3_dfii_pi1_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd18)); -assign vns_csrbank3_dfii_pi1_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd18)); -assign vns_csrbank3_dfii_pi1_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi1_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd19)); -assign vns_csrbank3_dfii_pi1_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd19)); -assign vns_csrbank3_dfii_pi1_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi1_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd20)); -assign vns_csrbank3_dfii_pi1_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd20)); -assign vns_csrbank3_dfii_pi1_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi1_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd21)); -assign vns_csrbank3_dfii_pi1_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd21)); -assign vns_csrbank3_dfii_pi1_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi1_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd22)); -assign vns_csrbank3_dfii_pi1_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd22)); -assign vns_csrbank3_dfii_pi1_rddata3_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi1_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd23)); -assign vns_csrbank3_dfii_pi1_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd23)); -assign vns_csrbank3_dfii_pi1_rddata2_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi1_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd24)); -assign vns_csrbank3_dfii_pi1_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd24)); -assign vns_csrbank3_dfii_pi1_rddata1_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi1_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd25)); -assign vns_csrbank3_dfii_pi1_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd25)); -assign vns_csrbank3_dfii_pi1_rddata0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi1_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd26)); -assign vns_csrbank3_dfii_pi1_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd26)); -assign vns_csrbank3_dfii_pi2_command0_r = vns_interface3_bank_bus_dat_w[5:0]; -assign vns_csrbank3_dfii_pi2_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd27)); -assign vns_csrbank3_dfii_pi2_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd27)); -assign soc_sdram_phaseinjector2_command_issue_r = vns_interface3_bank_bus_dat_w[0]; -assign soc_sdram_phaseinjector2_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd28)); -assign soc_sdram_phaseinjector2_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd28)); -assign vns_csrbank3_dfii_pi2_address1_r = vns_interface3_bank_bus_dat_w[5:0]; -assign vns_csrbank3_dfii_pi2_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd29)); -assign vns_csrbank3_dfii_pi2_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd29)); -assign vns_csrbank3_dfii_pi2_address0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi2_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd30)); -assign vns_csrbank3_dfii_pi2_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd30)); -assign vns_csrbank3_dfii_pi2_baddress0_r = vns_interface3_bank_bus_dat_w[2:0]; -assign vns_csrbank3_dfii_pi2_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd31)); -assign vns_csrbank3_dfii_pi2_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd31)); -assign vns_csrbank3_dfii_pi2_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi2_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd32)); -assign vns_csrbank3_dfii_pi2_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd32)); -assign vns_csrbank3_dfii_pi2_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi2_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd33)); -assign vns_csrbank3_dfii_pi2_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd33)); -assign vns_csrbank3_dfii_pi2_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi2_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd34)); -assign vns_csrbank3_dfii_pi2_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd34)); -assign vns_csrbank3_dfii_pi2_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi2_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd35)); -assign vns_csrbank3_dfii_pi2_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd35)); -assign vns_csrbank3_dfii_pi2_rddata3_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi2_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd36)); -assign vns_csrbank3_dfii_pi2_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd36)); -assign vns_csrbank3_dfii_pi2_rddata2_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi2_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd37)); -assign vns_csrbank3_dfii_pi2_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd37)); -assign vns_csrbank3_dfii_pi2_rddata1_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi2_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd38)); -assign vns_csrbank3_dfii_pi2_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd38)); -assign vns_csrbank3_dfii_pi2_rddata0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi2_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd39)); -assign vns_csrbank3_dfii_pi2_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd39)); -assign vns_csrbank3_dfii_pi3_command0_r = vns_interface3_bank_bus_dat_w[5:0]; -assign vns_csrbank3_dfii_pi3_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd40)); -assign vns_csrbank3_dfii_pi3_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd40)); -assign soc_sdram_phaseinjector3_command_issue_r = vns_interface3_bank_bus_dat_w[0]; -assign soc_sdram_phaseinjector3_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd41)); -assign soc_sdram_phaseinjector3_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd41)); -assign vns_csrbank3_dfii_pi3_address1_r = vns_interface3_bank_bus_dat_w[5:0]; -assign vns_csrbank3_dfii_pi3_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd42)); -assign vns_csrbank3_dfii_pi3_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd42)); -assign vns_csrbank3_dfii_pi3_address0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi3_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd43)); -assign vns_csrbank3_dfii_pi3_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd43)); -assign vns_csrbank3_dfii_pi3_baddress0_r = vns_interface3_bank_bus_dat_w[2:0]; -assign vns_csrbank3_dfii_pi3_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd44)); -assign vns_csrbank3_dfii_pi3_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd44)); -assign vns_csrbank3_dfii_pi3_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi3_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd45)); -assign vns_csrbank3_dfii_pi3_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd45)); -assign vns_csrbank3_dfii_pi3_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi3_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd46)); -assign vns_csrbank3_dfii_pi3_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd46)); -assign vns_csrbank3_dfii_pi3_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi3_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd47)); -assign vns_csrbank3_dfii_pi3_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd47)); -assign vns_csrbank3_dfii_pi3_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi3_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd48)); -assign vns_csrbank3_dfii_pi3_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd48)); -assign vns_csrbank3_dfii_pi3_rddata3_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi3_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd49)); -assign vns_csrbank3_dfii_pi3_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd49)); -assign vns_csrbank3_dfii_pi3_rddata2_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi3_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd50)); -assign vns_csrbank3_dfii_pi3_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd50)); -assign vns_csrbank3_dfii_pi3_rddata1_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi3_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd51)); -assign vns_csrbank3_dfii_pi3_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd51)); -assign vns_csrbank3_dfii_pi3_rddata0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi3_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd52)); -assign vns_csrbank3_dfii_pi3_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd52)); -assign vns_csrbank3_dfii_control0_w = soc_sdram_storage[3:0]; -assign vns_csrbank3_dfii_pi0_command0_w = soc_sdram_phaseinjector0_command_storage[5:0]; -assign vns_csrbank3_dfii_pi0_address1_w = soc_sdram_phaseinjector0_address_storage[13:8]; -assign vns_csrbank3_dfii_pi0_address0_w = soc_sdram_phaseinjector0_address_storage[7:0]; -assign vns_csrbank3_dfii_pi0_baddress0_w = soc_sdram_phaseinjector0_baddress_storage[2:0]; -assign vns_csrbank3_dfii_pi0_wrdata3_w = soc_sdram_phaseinjector0_wrdata_storage[31:24]; -assign vns_csrbank3_dfii_pi0_wrdata2_w = soc_sdram_phaseinjector0_wrdata_storage[23:16]; -assign vns_csrbank3_dfii_pi0_wrdata1_w = soc_sdram_phaseinjector0_wrdata_storage[15:8]; -assign vns_csrbank3_dfii_pi0_wrdata0_w = soc_sdram_phaseinjector0_wrdata_storage[7:0]; -assign vns_csrbank3_dfii_pi0_rddata3_w = soc_sdram_phaseinjector0_status[31:24]; -assign vns_csrbank3_dfii_pi0_rddata2_w = soc_sdram_phaseinjector0_status[23:16]; -assign vns_csrbank3_dfii_pi0_rddata1_w = soc_sdram_phaseinjector0_status[15:8]; -assign vns_csrbank3_dfii_pi0_rddata0_w = soc_sdram_phaseinjector0_status[7:0]; -assign soc_sdram_phaseinjector0_we = vns_csrbank3_dfii_pi0_rddata0_we; -assign vns_csrbank3_dfii_pi1_command0_w = soc_sdram_phaseinjector1_command_storage[5:0]; -assign vns_csrbank3_dfii_pi1_address1_w = soc_sdram_phaseinjector1_address_storage[13:8]; -assign vns_csrbank3_dfii_pi1_address0_w = soc_sdram_phaseinjector1_address_storage[7:0]; -assign vns_csrbank3_dfii_pi1_baddress0_w = soc_sdram_phaseinjector1_baddress_storage[2:0]; -assign vns_csrbank3_dfii_pi1_wrdata3_w = soc_sdram_phaseinjector1_wrdata_storage[31:24]; -assign vns_csrbank3_dfii_pi1_wrdata2_w = soc_sdram_phaseinjector1_wrdata_storage[23:16]; -assign vns_csrbank3_dfii_pi1_wrdata1_w = soc_sdram_phaseinjector1_wrdata_storage[15:8]; -assign vns_csrbank3_dfii_pi1_wrdata0_w = soc_sdram_phaseinjector1_wrdata_storage[7:0]; -assign vns_csrbank3_dfii_pi1_rddata3_w = soc_sdram_phaseinjector1_status[31:24]; -assign vns_csrbank3_dfii_pi1_rddata2_w = soc_sdram_phaseinjector1_status[23:16]; -assign vns_csrbank3_dfii_pi1_rddata1_w = soc_sdram_phaseinjector1_status[15:8]; -assign vns_csrbank3_dfii_pi1_rddata0_w = soc_sdram_phaseinjector1_status[7:0]; -assign soc_sdram_phaseinjector1_we = vns_csrbank3_dfii_pi1_rddata0_we; -assign vns_csrbank3_dfii_pi2_command0_w = soc_sdram_phaseinjector2_command_storage[5:0]; -assign vns_csrbank3_dfii_pi2_address1_w = soc_sdram_phaseinjector2_address_storage[13:8]; -assign vns_csrbank3_dfii_pi2_address0_w = soc_sdram_phaseinjector2_address_storage[7:0]; -assign vns_csrbank3_dfii_pi2_baddress0_w = soc_sdram_phaseinjector2_baddress_storage[2:0]; -assign vns_csrbank3_dfii_pi2_wrdata3_w = soc_sdram_phaseinjector2_wrdata_storage[31:24]; -assign vns_csrbank3_dfii_pi2_wrdata2_w = soc_sdram_phaseinjector2_wrdata_storage[23:16]; -assign vns_csrbank3_dfii_pi2_wrdata1_w = soc_sdram_phaseinjector2_wrdata_storage[15:8]; -assign vns_csrbank3_dfii_pi2_wrdata0_w = soc_sdram_phaseinjector2_wrdata_storage[7:0]; -assign vns_csrbank3_dfii_pi2_rddata3_w = soc_sdram_phaseinjector2_status[31:24]; -assign vns_csrbank3_dfii_pi2_rddata2_w = soc_sdram_phaseinjector2_status[23:16]; -assign vns_csrbank3_dfii_pi2_rddata1_w = soc_sdram_phaseinjector2_status[15:8]; -assign vns_csrbank3_dfii_pi2_rddata0_w = soc_sdram_phaseinjector2_status[7:0]; -assign soc_sdram_phaseinjector2_we = vns_csrbank3_dfii_pi2_rddata0_we; -assign vns_csrbank3_dfii_pi3_command0_w = soc_sdram_phaseinjector3_command_storage[5:0]; -assign vns_csrbank3_dfii_pi3_address1_w = soc_sdram_phaseinjector3_address_storage[13:8]; -assign vns_csrbank3_dfii_pi3_address0_w = soc_sdram_phaseinjector3_address_storage[7:0]; -assign vns_csrbank3_dfii_pi3_baddress0_w = soc_sdram_phaseinjector3_baddress_storage[2:0]; -assign vns_csrbank3_dfii_pi3_wrdata3_w = soc_sdram_phaseinjector3_wrdata_storage[31:24]; -assign vns_csrbank3_dfii_pi3_wrdata2_w = soc_sdram_phaseinjector3_wrdata_storage[23:16]; -assign vns_csrbank3_dfii_pi3_wrdata1_w = soc_sdram_phaseinjector3_wrdata_storage[15:8]; -assign vns_csrbank3_dfii_pi3_wrdata0_w = soc_sdram_phaseinjector3_wrdata_storage[7:0]; -assign vns_csrbank3_dfii_pi3_rddata3_w = soc_sdram_phaseinjector3_status[31:24]; -assign vns_csrbank3_dfii_pi3_rddata2_w = soc_sdram_phaseinjector3_status[23:16]; -assign vns_csrbank3_dfii_pi3_rddata1_w = soc_sdram_phaseinjector3_status[15:8]; -assign vns_csrbank3_dfii_pi3_rddata0_w = soc_sdram_phaseinjector3_status[7:0]; -assign soc_sdram_phaseinjector3_we = vns_csrbank3_dfii_pi3_rddata0_we; -assign vns_csrbank4_sel = (vns_interface4_bank_bus_adr[13:9] == 3'd4); -assign vns_csrbank4_load3_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_load3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 1'd0)); -assign vns_csrbank4_load3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 1'd0)); -assign vns_csrbank4_load2_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_load2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 1'd1)); -assign vns_csrbank4_load2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 1'd1)); -assign vns_csrbank4_load1_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_load1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 2'd2)); -assign vns_csrbank4_load1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 2'd2)); -assign vns_csrbank4_load0_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_load0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 2'd3)); -assign vns_csrbank4_load0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 2'd3)); -assign vns_csrbank4_reload3_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_reload3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd4)); -assign vns_csrbank4_reload3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd4)); -assign vns_csrbank4_reload2_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_reload2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd5)); -assign vns_csrbank4_reload2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd5)); -assign vns_csrbank4_reload1_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_reload1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd6)); -assign vns_csrbank4_reload1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd6)); -assign vns_csrbank4_reload0_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_reload0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd7)); -assign vns_csrbank4_reload0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd7)); -assign vns_csrbank4_en0_r = vns_interface4_bank_bus_dat_w[0]; -assign vns_csrbank4_en0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd8)); -assign vns_csrbank4_en0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd8)); -assign vns_csrbank4_update_value0_r = vns_interface4_bank_bus_dat_w[0]; -assign vns_csrbank4_update_value0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd9)); -assign vns_csrbank4_update_value0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd9)); -assign vns_csrbank4_value3_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_value3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd10)); -assign vns_csrbank4_value3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd10)); -assign vns_csrbank4_value2_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_value2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd11)); -assign vns_csrbank4_value2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd11)); -assign vns_csrbank4_value1_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_value1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd12)); -assign vns_csrbank4_value1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd12)); -assign vns_csrbank4_value0_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_value0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd13)); -assign vns_csrbank4_value0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd13)); -assign soc_litedramcore_timer_eventmanager_status_r = vns_interface4_bank_bus_dat_w[0]; -assign soc_litedramcore_timer_eventmanager_status_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd14)); -assign soc_litedramcore_timer_eventmanager_status_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd14)); -assign soc_litedramcore_timer_eventmanager_pending_r = vns_interface4_bank_bus_dat_w[0]; -assign soc_litedramcore_timer_eventmanager_pending_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd15)); -assign soc_litedramcore_timer_eventmanager_pending_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd15)); -assign vns_csrbank4_ev_enable0_r = vns_interface4_bank_bus_dat_w[0]; -assign vns_csrbank4_ev_enable0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 5'd16)); -assign vns_csrbank4_ev_enable0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 5'd16)); -assign vns_csrbank4_load3_w = soc_litedramcore_timer_load_storage[31:24]; -assign vns_csrbank4_load2_w = soc_litedramcore_timer_load_storage[23:16]; -assign vns_csrbank4_load1_w = soc_litedramcore_timer_load_storage[15:8]; -assign vns_csrbank4_load0_w = soc_litedramcore_timer_load_storage[7:0]; -assign vns_csrbank4_reload3_w = soc_litedramcore_timer_reload_storage[31:24]; -assign vns_csrbank4_reload2_w = soc_litedramcore_timer_reload_storage[23:16]; -assign vns_csrbank4_reload1_w = soc_litedramcore_timer_reload_storage[15:8]; -assign vns_csrbank4_reload0_w = soc_litedramcore_timer_reload_storage[7:0]; -assign vns_csrbank4_en0_w = soc_litedramcore_timer_en_storage; -assign vns_csrbank4_update_value0_w = soc_litedramcore_timer_update_value_storage; -assign vns_csrbank4_value3_w = soc_litedramcore_timer_value_status[31:24]; -assign vns_csrbank4_value2_w = soc_litedramcore_timer_value_status[23:16]; -assign vns_csrbank4_value1_w = soc_litedramcore_timer_value_status[15:8]; -assign vns_csrbank4_value0_w = soc_litedramcore_timer_value_status[7:0]; -assign soc_litedramcore_timer_value_we = vns_csrbank4_value0_we; -assign vns_csrbank4_ev_enable0_w = soc_litedramcore_timer_eventmanager_storage; -assign vns_csrbank5_sel = (vns_interface5_bank_bus_adr[13:9] == 2'd3); -assign soc_litedramcore_uart_rxtx_r = vns_interface5_bank_bus_dat_w[7:0]; -assign soc_litedramcore_uart_rxtx_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 1'd0)); -assign soc_litedramcore_uart_rxtx_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 1'd0)); -assign vns_csrbank5_txfull_r = vns_interface5_bank_bus_dat_w[0]; -assign vns_csrbank5_txfull_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 1'd1)); -assign vns_csrbank5_txfull_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 1'd1)); -assign vns_csrbank5_rxempty_r = vns_interface5_bank_bus_dat_w[0]; -assign vns_csrbank5_rxempty_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 2'd2)); -assign vns_csrbank5_rxempty_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 2'd2)); -assign soc_litedramcore_uart_eventmanager_status_r = vns_interface5_bank_bus_dat_w[1:0]; -assign soc_litedramcore_uart_eventmanager_status_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 2'd3)); -assign soc_litedramcore_uart_eventmanager_status_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 2'd3)); -assign soc_litedramcore_uart_eventmanager_pending_r = vns_interface5_bank_bus_dat_w[1:0]; -assign soc_litedramcore_uart_eventmanager_pending_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 3'd4)); -assign soc_litedramcore_uart_eventmanager_pending_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 3'd4)); -assign vns_csrbank5_ev_enable0_r = vns_interface5_bank_bus_dat_w[1:0]; -assign vns_csrbank5_ev_enable0_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 3'd5)); -assign vns_csrbank5_ev_enable0_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 3'd5)); -assign vns_csrbank5_txfull_w = soc_litedramcore_uart_txfull_status; -assign soc_litedramcore_uart_txfull_we = vns_csrbank5_txfull_we; -assign vns_csrbank5_rxempty_w = soc_litedramcore_uart_rxempty_status; -assign soc_litedramcore_uart_rxempty_we = vns_csrbank5_rxempty_we; -assign vns_csrbank5_ev_enable0_w = soc_litedramcore_uart_eventmanager_storage[1:0]; -assign vns_csrbank6_sel = (vns_interface6_bank_bus_adr[13:9] == 2'd2); -assign vns_csrbank6_tuning_word3_r = vns_interface6_bank_bus_dat_w[7:0]; -assign vns_csrbank6_tuning_word3_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 1'd0)); -assign vns_csrbank6_tuning_word3_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 1'd0)); -assign vns_csrbank6_tuning_word2_r = vns_interface6_bank_bus_dat_w[7:0]; -assign vns_csrbank6_tuning_word2_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 1'd1)); -assign vns_csrbank6_tuning_word2_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 1'd1)); -assign vns_csrbank6_tuning_word1_r = vns_interface6_bank_bus_dat_w[7:0]; -assign vns_csrbank6_tuning_word1_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 2'd2)); -assign vns_csrbank6_tuning_word1_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 2'd2)); -assign vns_csrbank6_tuning_word0_r = vns_interface6_bank_bus_dat_w[7:0]; -assign vns_csrbank6_tuning_word0_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 2'd3)); -assign vns_csrbank6_tuning_word0_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 2'd3)); -assign vns_csrbank6_tuning_word3_w = soc_litedramcore_storage[31:24]; -assign vns_csrbank6_tuning_word2_w = soc_litedramcore_storage[23:16]; -assign vns_csrbank6_tuning_word1_w = soc_litedramcore_storage[15:8]; -assign vns_csrbank6_tuning_word0_w = soc_litedramcore_storage[7:0]; -assign vns_adr = soc_litedramcore_interface_adr; -assign vns_we = soc_litedramcore_interface_we; -assign vns_dat_w = soc_litedramcore_interface_dat_w; -assign soc_litedramcore_interface_dat_r = vns_dat_r; -assign vns_interface0_bank_bus_adr = vns_adr; -assign vns_interface1_bank_bus_adr = vns_adr; -assign vns_interface2_bank_bus_adr = vns_adr; -assign vns_interface3_bank_bus_adr = vns_adr; -assign vns_interface4_bank_bus_adr = vns_adr; -assign vns_interface5_bank_bus_adr = vns_adr; -assign vns_interface6_bank_bus_adr = vns_adr; -assign vns_interface0_bank_bus_we = vns_we; -assign vns_interface1_bank_bus_we = vns_we; -assign vns_interface2_bank_bus_we = vns_we; -assign vns_interface3_bank_bus_we = vns_we; -assign vns_interface4_bank_bus_we = vns_we; -assign vns_interface5_bank_bus_we = vns_we; -assign vns_interface6_bank_bus_we = vns_we; -assign vns_interface0_bank_bus_dat_w = vns_dat_w; -assign vns_interface1_bank_bus_dat_w = vns_dat_w; -assign vns_interface2_bank_bus_dat_w = vns_dat_w; -assign vns_interface3_bank_bus_dat_w = vns_dat_w; -assign vns_interface4_bank_bus_dat_w = vns_dat_w; -assign vns_interface5_bank_bus_dat_w = vns_dat_w; -assign vns_interface6_bank_bus_dat_w = vns_dat_w; -assign vns_dat_r = ((((((vns_interface0_bank_bus_dat_r | vns_interface1_bank_bus_dat_r) | vns_interface2_bank_bus_dat_r) | vns_interface3_bank_bus_dat_r) | vns_interface4_bank_bus_dat_r) | vns_interface5_bank_bus_dat_r) | vns_interface6_bank_bus_dat_r); // synthesis translate_off -reg dummy_d_338; +reg dummy_d_274; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed0 <= 1'd0; - case (soc_sdram_choose_cmd_grant) - 1'd0: begin - vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[0]; - end + litedramcore_en1 <= 1'd0; + case (multiplexer_state) 1'd1: begin - vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[1]; + litedramcore_en1 <= 1'd1; end 2'd2: begin - vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[2]; end 2'd3: begin - vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[3]; end 3'd4: begin - vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[4]; end 3'd5: begin - vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[5]; end 3'd6: begin - vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[6]; + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin end default: begin - vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[7]; end endcase // synthesis translate_off - dummy_d_338 = dummy_s; + dummy_d_274 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_339; +reg dummy_d_275; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed1 <= 14'd0; - case (soc_sdram_choose_cmd_grant) - 1'd0: begin - vns_rhs_array_muxed1 <= soc_sdram_bankmachine0_cmd_payload_a; - end + litedramcore_steerer_sel3 <= 2'd0; + case (multiplexer_state) 1'd1: begin - vns_rhs_array_muxed1 <= soc_sdram_bankmachine1_cmd_payload_a; + litedramcore_steerer_sel3 <= 2'd2; end 2'd2: begin - vns_rhs_array_muxed1 <= soc_sdram_bankmachine2_cmd_payload_a; end 2'd3: begin - vns_rhs_array_muxed1 <= soc_sdram_bankmachine3_cmd_payload_a; end 3'd4: begin - vns_rhs_array_muxed1 <= soc_sdram_bankmachine4_cmd_payload_a; end 3'd5: begin - vns_rhs_array_muxed1 <= soc_sdram_bankmachine5_cmd_payload_a; end 3'd6: begin - vns_rhs_array_muxed1 <= soc_sdram_bankmachine6_cmd_payload_a; + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin end default: begin - vns_rhs_array_muxed1 <= soc_sdram_bankmachine7_cmd_payload_a; + litedramcore_steerer_sel3 <= 1'd0; end endcase // synthesis translate_off - dummy_d_339 = dummy_s; + dummy_d_275 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_340; +reg dummy_d_276; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed2 <= 3'd0; - case (soc_sdram_choose_cmd_grant) - 1'd0: begin - vns_rhs_array_muxed2 <= soc_sdram_bankmachine0_cmd_payload_ba; - end + litedramcore_steerer_sel0 <= 2'd0; + case (multiplexer_state) 1'd1: begin - vns_rhs_array_muxed2 <= soc_sdram_bankmachine1_cmd_payload_ba; + litedramcore_steerer_sel0 <= 1'd0; end 2'd2: begin - vns_rhs_array_muxed2 <= soc_sdram_bankmachine2_cmd_payload_ba; + litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin - vns_rhs_array_muxed2 <= soc_sdram_bankmachine3_cmd_payload_ba; end 3'd4: begin - vns_rhs_array_muxed2 <= soc_sdram_bankmachine4_cmd_payload_ba; end 3'd5: begin - vns_rhs_array_muxed2 <= soc_sdram_bankmachine5_cmd_payload_ba; end 3'd6: begin - vns_rhs_array_muxed2 <= soc_sdram_bankmachine6_cmd_payload_ba; + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin end default: begin - vns_rhs_array_muxed2 <= soc_sdram_bankmachine7_cmd_payload_ba; + litedramcore_steerer_sel0 <= 1'd0; end endcase // synthesis translate_off - dummy_d_340 = dummy_s; + dummy_d_276 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_341; +reg dummy_d_277; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed3 <= 1'd0; - case (soc_sdram_choose_cmd_grant) - 1'd0: begin - vns_rhs_array_muxed3 <= soc_sdram_bankmachine0_cmd_payload_is_read; - end + litedramcore_steerer_sel1 <= 2'd0; + case (multiplexer_state) 1'd1: begin - vns_rhs_array_muxed3 <= soc_sdram_bankmachine1_cmd_payload_is_read; + litedramcore_steerer_sel1 <= 1'd0; end 2'd2: begin - vns_rhs_array_muxed3 <= soc_sdram_bankmachine2_cmd_payload_is_read; end 2'd3: begin - vns_rhs_array_muxed3 <= soc_sdram_bankmachine3_cmd_payload_is_read; end 3'd4: begin - vns_rhs_array_muxed3 <= soc_sdram_bankmachine4_cmd_payload_is_read; end 3'd5: begin - vns_rhs_array_muxed3 <= soc_sdram_bankmachine5_cmd_payload_is_read; end 3'd6: begin - vns_rhs_array_muxed3 <= soc_sdram_bankmachine6_cmd_payload_is_read; + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin end default: begin - vns_rhs_array_muxed3 <= soc_sdram_bankmachine7_cmd_payload_is_read; + litedramcore_steerer_sel1 <= 1'd1; end endcase // synthesis translate_off - dummy_d_341 = dummy_s; + dummy_d_277 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_342; +reg dummy_d_278; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed4 <= 1'd0; - case (soc_sdram_choose_cmd_grant) - 1'd0: begin - vns_rhs_array_muxed4 <= soc_sdram_bankmachine0_cmd_payload_is_write; - end + litedramcore_steerer_sel2 <= 2'd0; + case (multiplexer_state) 1'd1: begin - vns_rhs_array_muxed4 <= soc_sdram_bankmachine1_cmd_payload_is_write; + litedramcore_steerer_sel2 <= 1'd1; end 2'd2: begin - vns_rhs_array_muxed4 <= soc_sdram_bankmachine2_cmd_payload_is_write; end 2'd3: begin - vns_rhs_array_muxed4 <= soc_sdram_bankmachine3_cmd_payload_is_write; end 3'd4: begin - vns_rhs_array_muxed4 <= soc_sdram_bankmachine4_cmd_payload_is_write; end 3'd5: begin - vns_rhs_array_muxed4 <= soc_sdram_bankmachine5_cmd_payload_is_write; end 3'd6: begin - vns_rhs_array_muxed4 <= soc_sdram_bankmachine6_cmd_payload_is_write; + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin end default: begin - vns_rhs_array_muxed4 <= soc_sdram_bankmachine7_cmd_payload_is_write; + litedramcore_steerer_sel2 <= 2'd2; end endcase // synthesis translate_off - dummy_d_342 = dummy_s; + dummy_d_278 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_343; +reg dummy_d_279; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed5 <= 1'd0; - case (soc_sdram_choose_cmd_grant) - 1'd0: begin - vns_rhs_array_muxed5 <= soc_sdram_bankmachine0_cmd_payload_is_cmd; - end + litedramcore_choose_cmd_want_activates <= 1'd0; + case (multiplexer_state) 1'd1: begin - vns_rhs_array_muxed5 <= soc_sdram_bankmachine1_cmd_payload_is_cmd; + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end end 2'd2: begin - vns_rhs_array_muxed5 <= soc_sdram_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - vns_rhs_array_muxed5 <= soc_sdram_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - vns_rhs_array_muxed5 <= soc_sdram_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - vns_rhs_array_muxed5 <= soc_sdram_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - vns_rhs_array_muxed5 <= soc_sdram_bankmachine6_cmd_payload_is_cmd; + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin end default: begin - vns_rhs_array_muxed5 <= soc_sdram_bankmachine7_cmd_payload_is_cmd; + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end end endcase // synthesis translate_off - dummy_d_343 = dummy_s; + dummy_d_279 = dummy_s; // synthesis translate_on end +assign roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); +assign litedramcore_interface_bank0_addr = rhs_array_muxed12; +assign litedramcore_interface_bank0_we = rhs_array_muxed13; +assign litedramcore_interface_bank0_valid = rhs_array_muxed14; +assign roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock)); +assign litedramcore_interface_bank1_addr = rhs_array_muxed15; +assign litedramcore_interface_bank1_we = rhs_array_muxed16; +assign litedramcore_interface_bank1_valid = rhs_array_muxed17; +assign roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock)); +assign litedramcore_interface_bank2_addr = rhs_array_muxed18; +assign litedramcore_interface_bank2_we = rhs_array_muxed19; +assign litedramcore_interface_bank2_valid = rhs_array_muxed20; +assign roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock)); +assign litedramcore_interface_bank3_addr = rhs_array_muxed21; +assign litedramcore_interface_bank3_we = rhs_array_muxed22; +assign litedramcore_interface_bank3_valid = rhs_array_muxed23; +assign roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock)); +assign litedramcore_interface_bank4_addr = rhs_array_muxed24; +assign litedramcore_interface_bank4_we = rhs_array_muxed25; +assign litedramcore_interface_bank4_valid = rhs_array_muxed26; +assign roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock)); +assign litedramcore_interface_bank5_addr = rhs_array_muxed27; +assign litedramcore_interface_bank5_we = rhs_array_muxed28; +assign litedramcore_interface_bank5_valid = rhs_array_muxed29; +assign roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock)); +assign litedramcore_interface_bank6_addr = rhs_array_muxed30; +assign litedramcore_interface_bank6_we = rhs_array_muxed31; +assign litedramcore_interface_bank6_valid = rhs_array_muxed32; +assign roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock)); +assign litedramcore_interface_bank7_addr = rhs_array_muxed33; +assign litedramcore_interface_bank7_we = rhs_array_muxed34; +assign litedramcore_interface_bank7_valid = rhs_array_muxed35; +assign user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready)); +assign user_port_wdata_ready = new_master_wdata_ready2; +assign user_port_rdata_valid = new_master_rdata_valid8; // synthesis translate_off -reg dummy_d_344; +reg dummy_d_280; // synthesis translate_on always @(*) begin - vns_t_array_muxed0 <= 1'd0; - case (soc_sdram_choose_cmd_grant) - 1'd0: begin - vns_t_array_muxed0 <= soc_sdram_bankmachine0_cmd_payload_cas; - end + litedramcore_interface_wdata_we <= 16'd0; + case ({new_master_wdata_ready2}) 1'd1: begin - vns_t_array_muxed0 <= soc_sdram_bankmachine1_cmd_payload_cas; - end - 2'd2: begin - vns_t_array_muxed0 <= soc_sdram_bankmachine2_cmd_payload_cas; - end - 2'd3: begin - vns_t_array_muxed0 <= soc_sdram_bankmachine3_cmd_payload_cas; - end - 3'd4: begin - vns_t_array_muxed0 <= soc_sdram_bankmachine4_cmd_payload_cas; + litedramcore_interface_wdata_we <= user_port_wdata_payload_we; end - 3'd5: begin - vns_t_array_muxed0 <= soc_sdram_bankmachine5_cmd_payload_cas; + default: begin + litedramcore_interface_wdata_we <= 1'd0; end - 3'd6: begin - vns_t_array_muxed0 <= soc_sdram_bankmachine6_cmd_payload_cas; + endcase +// synthesis translate_off + dummy_d_280 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_281; +// synthesis translate_on +always @(*) begin + litedramcore_interface_wdata <= 128'd0; + case ({new_master_wdata_ready2}) + 1'd1: begin + litedramcore_interface_wdata <= user_port_wdata_payload_data; end default: begin - vns_t_array_muxed0 <= soc_sdram_bankmachine7_cmd_payload_cas; + litedramcore_interface_wdata <= 1'd0; end endcase // synthesis translate_off - dummy_d_344 = dummy_s; + dummy_d_281 = dummy_s; // synthesis translate_on end +assign user_port_rdata_payload_data = litedramcore_interface_rdata; +assign roundrobin0_grant = 1'd0; +assign roundrobin1_grant = 1'd0; +assign roundrobin2_grant = 1'd0; +assign roundrobin3_grant = 1'd0; +assign roundrobin4_grant = 1'd0; +assign roundrobin5_grant = 1'd0; +assign roundrobin6_grant = 1'd0; +assign roundrobin7_grant = 1'd0; // synthesis translate_off -reg dummy_d_345; +reg dummy_d_282; +// synthesis translate_on +always @(*) begin + csrbank0_sel <= 1'd0; + csrbank0_sel <= (interface0_bank_bus_adr[13:11] == 2'd2); + if (interface0_bank_bus_adr[0]) begin + csrbank0_sel <= 1'd0; + end +// synthesis translate_off + dummy_d_282 = dummy_s; +// synthesis translate_on +end +assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; +assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd0)); +assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd0)); +assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; +assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd1)); +assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd1)); +assign csrbank0_init_done0_w = init_done_storage; +assign csrbank0_init_error0_w = init_error_storage; + +// synthesis translate_off +reg dummy_d_283; +// synthesis translate_on +always @(*) begin + csrbank1_sel <= 1'd0; + csrbank1_sel <= (interface1_bank_bus_adr[13:11] == 1'd0); + if (interface1_bank_bus_adr[0]) begin + csrbank1_sel <= 1'd0; + end +// synthesis translate_off + dummy_d_283 = dummy_s; +// synthesis translate_on +end +assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; +assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd0)); +assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd0)); +assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; +assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd1)); +assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd1)); +assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; +assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd2)); +assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd2)); +assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0]; +assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd3)); +assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd3)); +assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0]; +assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd4)); +assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd4)); +assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; +assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd5)); +assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd5)); +assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; +assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd6)); +assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; +assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd7)); +assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; +assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; +assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd9)); +assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0]; +assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; +assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; + +// synthesis translate_off +reg dummy_d_284; +// synthesis translate_on +always @(*) begin + csrbank2_sel <= 1'd0; + csrbank2_sel <= (interface2_bank_bus_adr[13:11] == 1'd1); + if (interface2_bank_bus_adr[0]) begin + csrbank2_sel <= 1'd0; + end +// synthesis translate_off + dummy_d_284 = dummy_s; +// synthesis translate_on +end +assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; +assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd0)); +assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd0)); +assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; +assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd1)); +assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd1)); +assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; +assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd2)); +assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd2)); +assign csrbank2_dfii_pi0_address1_r = interface2_bank_bus_dat_w[5:0]; +assign csrbank2_dfii_pi0_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd3)); +assign csrbank2_dfii_pi0_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd3)); +assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd4)); +assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd4)); +assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd5)); +assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd5)); +assign csrbank2_dfii_pi0_wrdata3_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi0_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd6)); +assign csrbank2_dfii_pi0_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd6)); +assign csrbank2_dfii_pi0_wrdata2_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi0_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd7)); +assign csrbank2_dfii_pi0_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd7)); +assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi0_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd8)); +assign csrbank2_dfii_pi0_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd8)); +assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd9)); +assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd9)); +assign csrbank2_dfii_pi0_rddata3_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi0_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd10)); +assign csrbank2_dfii_pi0_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd10)); +assign csrbank2_dfii_pi0_rddata2_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi0_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd11)); +assign csrbank2_dfii_pi0_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd11)); +assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi0_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd12)); +assign csrbank2_dfii_pi0_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd12)); +assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi0_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd13)); +assign csrbank2_dfii_pi0_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd13)); +assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; +assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd14)); +assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd14)); +assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; +assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd15)); +assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd15)); +assign csrbank2_dfii_pi1_address1_r = interface2_bank_bus_dat_w[5:0]; +assign csrbank2_dfii_pi1_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd16)); +assign csrbank2_dfii_pi1_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd16)); +assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd17)); +assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd17)); +assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd18)); +assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd18)); +assign csrbank2_dfii_pi1_wrdata3_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi1_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd19)); +assign csrbank2_dfii_pi1_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd19)); +assign csrbank2_dfii_pi1_wrdata2_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi1_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd20)); +assign csrbank2_dfii_pi1_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd20)); +assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi1_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd21)); +assign csrbank2_dfii_pi1_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd21)); +assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd22)); +assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd22)); +assign csrbank2_dfii_pi1_rddata3_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi1_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd23)); +assign csrbank2_dfii_pi1_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd23)); +assign csrbank2_dfii_pi1_rddata2_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi1_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd24)); +assign csrbank2_dfii_pi1_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd24)); +assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi1_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd25)); +assign csrbank2_dfii_pi1_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd25)); +assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi1_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd26)); +assign csrbank2_dfii_pi1_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd26)); +assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; +assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd27)); +assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd27)); +assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; +assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd28)); +assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd28)); +assign csrbank2_dfii_pi2_address1_r = interface2_bank_bus_dat_w[5:0]; +assign csrbank2_dfii_pi2_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd29)); +assign csrbank2_dfii_pi2_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd29)); +assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd30)); +assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd30)); +assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd31)); +assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd31)); +assign csrbank2_dfii_pi2_wrdata3_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi2_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd32)); +assign csrbank2_dfii_pi2_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd32)); +assign csrbank2_dfii_pi2_wrdata2_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi2_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd33)); +assign csrbank2_dfii_pi2_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd33)); +assign csrbank2_dfii_pi2_wrdata1_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi2_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd34)); +assign csrbank2_dfii_pi2_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd34)); +assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd35)); +assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd35)); +assign csrbank2_dfii_pi2_rddata3_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi2_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd36)); +assign csrbank2_dfii_pi2_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd36)); +assign csrbank2_dfii_pi2_rddata2_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi2_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd37)); +assign csrbank2_dfii_pi2_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd37)); +assign csrbank2_dfii_pi2_rddata1_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi2_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd38)); +assign csrbank2_dfii_pi2_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd38)); +assign csrbank2_dfii_pi2_rddata0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi2_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd39)); +assign csrbank2_dfii_pi2_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd39)); +assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; +assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd40)); +assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd40)); +assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; +assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd41)); +assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd41)); +assign csrbank2_dfii_pi3_address1_r = interface2_bank_bus_dat_w[5:0]; +assign csrbank2_dfii_pi3_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd42)); +assign csrbank2_dfii_pi3_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd42)); +assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd43)); +assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd43)); +assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd44)); +assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd44)); +assign csrbank2_dfii_pi3_wrdata3_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi3_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd45)); +assign csrbank2_dfii_pi3_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd45)); +assign csrbank2_dfii_pi3_wrdata2_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi3_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd46)); +assign csrbank2_dfii_pi3_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd46)); +assign csrbank2_dfii_pi3_wrdata1_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi3_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd47)); +assign csrbank2_dfii_pi3_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd47)); +assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd48)); +assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd48)); +assign csrbank2_dfii_pi3_rddata3_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi3_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd49)); +assign csrbank2_dfii_pi3_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd49)); +assign csrbank2_dfii_pi3_rddata2_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi3_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd50)); +assign csrbank2_dfii_pi3_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd50)); +assign csrbank2_dfii_pi3_rddata1_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi3_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd51)); +assign csrbank2_dfii_pi3_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd51)); +assign csrbank2_dfii_pi3_rddata0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi3_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd52)); +assign csrbank2_dfii_pi3_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd52)); +assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; +assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; +assign csrbank2_dfii_pi0_address1_w = litedramcore_phaseinjector0_address_storage[13:8]; +assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[7:0]; +assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; +assign csrbank2_dfii_pi0_wrdata3_w = litedramcore_phaseinjector0_wrdata_storage[31:24]; +assign csrbank2_dfii_pi0_wrdata2_w = litedramcore_phaseinjector0_wrdata_storage[23:16]; +assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[15:8]; +assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[7:0]; +assign csrbank2_dfii_pi0_rddata3_w = litedramcore_phaseinjector0_status[31:24]; +assign csrbank2_dfii_pi0_rddata2_w = litedramcore_phaseinjector0_status[23:16]; +assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_status[15:8]; +assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_status[7:0]; +assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata0_we; +assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0]; +assign csrbank2_dfii_pi1_address1_w = litedramcore_phaseinjector1_address_storage[13:8]; +assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[7:0]; +assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; +assign csrbank2_dfii_pi1_wrdata3_w = litedramcore_phaseinjector1_wrdata_storage[31:24]; +assign csrbank2_dfii_pi1_wrdata2_w = litedramcore_phaseinjector1_wrdata_storage[23:16]; +assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[15:8]; +assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[7:0]; +assign csrbank2_dfii_pi1_rddata3_w = litedramcore_phaseinjector1_status[31:24]; +assign csrbank2_dfii_pi1_rddata2_w = litedramcore_phaseinjector1_status[23:16]; +assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_status[15:8]; +assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_status[7:0]; +assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata0_we; +assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0]; +assign csrbank2_dfii_pi2_address1_w = litedramcore_phaseinjector2_address_storage[13:8]; +assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[7:0]; +assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0]; +assign csrbank2_dfii_pi2_wrdata3_w = litedramcore_phaseinjector2_wrdata_storage[31:24]; +assign csrbank2_dfii_pi2_wrdata2_w = litedramcore_phaseinjector2_wrdata_storage[23:16]; +assign csrbank2_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[15:8]; +assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[7:0]; +assign csrbank2_dfii_pi2_rddata3_w = litedramcore_phaseinjector2_status[31:24]; +assign csrbank2_dfii_pi2_rddata2_w = litedramcore_phaseinjector2_status[23:16]; +assign csrbank2_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_status[15:8]; +assign csrbank2_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_status[7:0]; +assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata0_we; +assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0]; +assign csrbank2_dfii_pi3_address1_w = litedramcore_phaseinjector3_address_storage[13:8]; +assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[7:0]; +assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0]; +assign csrbank2_dfii_pi3_wrdata3_w = litedramcore_phaseinjector3_wrdata_storage[31:24]; +assign csrbank2_dfii_pi3_wrdata2_w = litedramcore_phaseinjector3_wrdata_storage[23:16]; +assign csrbank2_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[15:8]; +assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[7:0]; +assign csrbank2_dfii_pi3_rddata3_w = litedramcore_phaseinjector3_status[31:24]; +assign csrbank2_dfii_pi3_rddata2_w = litedramcore_phaseinjector3_status[23:16]; +assign csrbank2_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_status[15:8]; +assign csrbank2_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_status[7:0]; +assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata0_we; +assign adr = csr_port_adr; +assign we = csr_port_we; +assign dat_w = csr_port_dat_w; +assign csr_port_dat_r = dat_r; +assign interface0_bank_bus_adr = adr; +assign interface1_bank_bus_adr = adr; +assign interface2_bank_bus_adr = adr; +assign interface0_bank_bus_we = we; +assign interface1_bank_bus_we = we; +assign interface2_bank_bus_we = we; +assign interface0_bank_bus_dat_w = dat_w; +assign interface1_bank_bus_dat_w = dat_w; +assign interface2_bank_bus_dat_w = dat_w; +assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); + +// synthesis translate_off +reg dummy_d_285; // synthesis translate_on always @(*) begin - vns_t_array_muxed1 <= 1'd0; - case (soc_sdram_choose_cmd_grant) + rhs_array_muxed0 <= 1'd0; + case (litedramcore_choose_cmd_grant) 1'd0: begin - vns_t_array_muxed1 <= soc_sdram_bankmachine0_cmd_payload_ras; + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; end 1'd1: begin - vns_t_array_muxed1 <= soc_sdram_bankmachine1_cmd_payload_ras; + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; end 2'd2: begin - vns_t_array_muxed1 <= soc_sdram_bankmachine2_cmd_payload_ras; + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; end 2'd3: begin - vns_t_array_muxed1 <= soc_sdram_bankmachine3_cmd_payload_ras; + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; end 3'd4: begin - vns_t_array_muxed1 <= soc_sdram_bankmachine4_cmd_payload_ras; + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; end 3'd5: begin - vns_t_array_muxed1 <= soc_sdram_bankmachine5_cmd_payload_ras; + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; end 3'd6: begin - vns_t_array_muxed1 <= soc_sdram_bankmachine6_cmd_payload_ras; + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; end default: begin - vns_t_array_muxed1 <= soc_sdram_bankmachine7_cmd_payload_ras; + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; end endcase // synthesis translate_off - dummy_d_345 = dummy_s; + dummy_d_285 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_346; +reg dummy_d_286; // synthesis translate_on always @(*) begin - vns_t_array_muxed2 <= 1'd0; - case (soc_sdram_choose_cmd_grant) + rhs_array_muxed1 <= 14'd0; + case (litedramcore_choose_cmd_grant) 1'd0: begin - vns_t_array_muxed2 <= soc_sdram_bankmachine0_cmd_payload_we; + rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - vns_t_array_muxed2 <= soc_sdram_bankmachine1_cmd_payload_we; + rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - vns_t_array_muxed2 <= soc_sdram_bankmachine2_cmd_payload_we; + rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - vns_t_array_muxed2 <= soc_sdram_bankmachine3_cmd_payload_we; + rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - vns_t_array_muxed2 <= soc_sdram_bankmachine4_cmd_payload_we; + rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - vns_t_array_muxed2 <= soc_sdram_bankmachine5_cmd_payload_we; + rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - vns_t_array_muxed2 <= soc_sdram_bankmachine6_cmd_payload_we; + rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; end default: begin - vns_t_array_muxed2 <= soc_sdram_bankmachine7_cmd_payload_we; + rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_346 = dummy_s; + dummy_d_286 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_347; +reg dummy_d_287; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed6 <= 1'd0; - case (soc_sdram_choose_req_grant) + rhs_array_muxed2 <= 3'd0; + case (litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[0]; + rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[1]; + rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[2]; + rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[3]; + rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[4]; + rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[5]; + rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[6]; + rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; end default: begin - vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[7]; + rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; end endcase // synthesis translate_off - dummy_d_347 = dummy_s; + dummy_d_287 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_348; +reg dummy_d_288; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed7 <= 14'd0; - case (soc_sdram_choose_req_grant) + rhs_array_muxed3 <= 1'd0; + case (litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed7 <= soc_sdram_bankmachine0_cmd_payload_a; + rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - vns_rhs_array_muxed7 <= soc_sdram_bankmachine1_cmd_payload_a; + rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - vns_rhs_array_muxed7 <= soc_sdram_bankmachine2_cmd_payload_a; + rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - vns_rhs_array_muxed7 <= soc_sdram_bankmachine3_cmd_payload_a; + rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - vns_rhs_array_muxed7 <= soc_sdram_bankmachine4_cmd_payload_a; + rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - vns_rhs_array_muxed7 <= soc_sdram_bankmachine5_cmd_payload_a; + rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - vns_rhs_array_muxed7 <= soc_sdram_bankmachine6_cmd_payload_a; + rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - vns_rhs_array_muxed7 <= soc_sdram_bankmachine7_cmd_payload_a; + rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; end endcase // synthesis translate_off - dummy_d_348 = dummy_s; + dummy_d_288 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_349; +reg dummy_d_289; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed8 <= 3'd0; - case (soc_sdram_choose_req_grant) + rhs_array_muxed4 <= 1'd0; + case (litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed8 <= soc_sdram_bankmachine0_cmd_payload_ba; + rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - vns_rhs_array_muxed8 <= soc_sdram_bankmachine1_cmd_payload_ba; + rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - vns_rhs_array_muxed8 <= soc_sdram_bankmachine2_cmd_payload_ba; + rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - vns_rhs_array_muxed8 <= soc_sdram_bankmachine3_cmd_payload_ba; + rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - vns_rhs_array_muxed8 <= soc_sdram_bankmachine4_cmd_payload_ba; + rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - vns_rhs_array_muxed8 <= soc_sdram_bankmachine5_cmd_payload_ba; + rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - vns_rhs_array_muxed8 <= soc_sdram_bankmachine6_cmd_payload_ba; + rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - vns_rhs_array_muxed8 <= soc_sdram_bankmachine7_cmd_payload_ba; + rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; end endcase // synthesis translate_off - dummy_d_349 = dummy_s; + dummy_d_289 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_350; +reg dummy_d_290; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed9 <= 1'd0; - case (soc_sdram_choose_req_grant) + rhs_array_muxed5 <= 1'd0; + case (litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed9 <= soc_sdram_bankmachine0_cmd_payload_is_read; + rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - vns_rhs_array_muxed9 <= soc_sdram_bankmachine1_cmd_payload_is_read; + rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - vns_rhs_array_muxed9 <= soc_sdram_bankmachine2_cmd_payload_is_read; + rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - vns_rhs_array_muxed9 <= soc_sdram_bankmachine3_cmd_payload_is_read; + rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - vns_rhs_array_muxed9 <= soc_sdram_bankmachine4_cmd_payload_is_read; + rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - vns_rhs_array_muxed9 <= soc_sdram_bankmachine5_cmd_payload_is_read; + rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - vns_rhs_array_muxed9 <= soc_sdram_bankmachine6_cmd_payload_is_read; + rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - vns_rhs_array_muxed9 <= soc_sdram_bankmachine7_cmd_payload_is_read; + rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase // synthesis translate_off - dummy_d_350 = dummy_s; + dummy_d_290 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_351; +reg dummy_d_291; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed10 <= 1'd0; - case (soc_sdram_choose_req_grant) + t_array_muxed0 <= 1'd0; + case (litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed10 <= soc_sdram_bankmachine0_cmd_payload_is_write; + t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - vns_rhs_array_muxed10 <= soc_sdram_bankmachine1_cmd_payload_is_write; + t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - vns_rhs_array_muxed10 <= soc_sdram_bankmachine2_cmd_payload_is_write; + t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - vns_rhs_array_muxed10 <= soc_sdram_bankmachine3_cmd_payload_is_write; + t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - vns_rhs_array_muxed10 <= soc_sdram_bankmachine4_cmd_payload_is_write; + t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - vns_rhs_array_muxed10 <= soc_sdram_bankmachine5_cmd_payload_is_write; + t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - vns_rhs_array_muxed10 <= soc_sdram_bankmachine6_cmd_payload_is_write; + t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; end default: begin - vns_rhs_array_muxed10 <= soc_sdram_bankmachine7_cmd_payload_is_write; + t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; end endcase // synthesis translate_off - dummy_d_351 = dummy_s; + dummy_d_291 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_352; +reg dummy_d_292; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed11 <= 1'd0; - case (soc_sdram_choose_req_grant) + t_array_muxed1 <= 1'd0; + case (litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed11 <= soc_sdram_bankmachine0_cmd_payload_is_cmd; + t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - vns_rhs_array_muxed11 <= soc_sdram_bankmachine1_cmd_payload_is_cmd; + t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - vns_rhs_array_muxed11 <= soc_sdram_bankmachine2_cmd_payload_is_cmd; + t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - vns_rhs_array_muxed11 <= soc_sdram_bankmachine3_cmd_payload_is_cmd; + t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - vns_rhs_array_muxed11 <= soc_sdram_bankmachine4_cmd_payload_is_cmd; + t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - vns_rhs_array_muxed11 <= soc_sdram_bankmachine5_cmd_payload_is_cmd; + t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - vns_rhs_array_muxed11 <= soc_sdram_bankmachine6_cmd_payload_is_cmd; + t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; end default: begin - vns_rhs_array_muxed11 <= soc_sdram_bankmachine7_cmd_payload_is_cmd; + t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; end endcase // synthesis translate_off - dummy_d_352 = dummy_s; + dummy_d_292 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_353; +reg dummy_d_293; // synthesis translate_on always @(*) begin - vns_t_array_muxed3 <= 1'd0; - case (soc_sdram_choose_req_grant) + t_array_muxed2 <= 1'd0; + case (litedramcore_choose_cmd_grant) 1'd0: begin - vns_t_array_muxed3 <= soc_sdram_bankmachine0_cmd_payload_cas; + t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - vns_t_array_muxed3 <= soc_sdram_bankmachine1_cmd_payload_cas; + t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - vns_t_array_muxed3 <= soc_sdram_bankmachine2_cmd_payload_cas; + t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - vns_t_array_muxed3 <= soc_sdram_bankmachine3_cmd_payload_cas; + t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - vns_t_array_muxed3 <= soc_sdram_bankmachine4_cmd_payload_cas; + t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - vns_t_array_muxed3 <= soc_sdram_bankmachine5_cmd_payload_cas; + t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - vns_t_array_muxed3 <= soc_sdram_bankmachine6_cmd_payload_cas; + t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; end default: begin - vns_t_array_muxed3 <= soc_sdram_bankmachine7_cmd_payload_cas; + t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_353 = dummy_s; + dummy_d_293 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_354; +reg dummy_d_294; // synthesis translate_on always @(*) begin - vns_t_array_muxed4 <= 1'd0; - case (soc_sdram_choose_req_grant) + rhs_array_muxed6 <= 1'd0; + case (litedramcore_choose_req_grant) 1'd0: begin - vns_t_array_muxed4 <= soc_sdram_bankmachine0_cmd_payload_ras; + rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; end 1'd1: begin - vns_t_array_muxed4 <= soc_sdram_bankmachine1_cmd_payload_ras; + rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; end 2'd2: begin - vns_t_array_muxed4 <= soc_sdram_bankmachine2_cmd_payload_ras; + rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; end 2'd3: begin - vns_t_array_muxed4 <= soc_sdram_bankmachine3_cmd_payload_ras; + rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; end 3'd4: begin - vns_t_array_muxed4 <= soc_sdram_bankmachine4_cmd_payload_ras; + rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; end 3'd5: begin - vns_t_array_muxed4 <= soc_sdram_bankmachine5_cmd_payload_ras; + rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; end 3'd6: begin - vns_t_array_muxed4 <= soc_sdram_bankmachine6_cmd_payload_ras; + rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; end default: begin - vns_t_array_muxed4 <= soc_sdram_bankmachine7_cmd_payload_ras; + rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; end endcase // synthesis translate_off - dummy_d_354 = dummy_s; + dummy_d_294 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_355; +reg dummy_d_295; // synthesis translate_on always @(*) begin - vns_t_array_muxed5 <= 1'd0; - case (soc_sdram_choose_req_grant) + rhs_array_muxed7 <= 14'd0; + case (litedramcore_choose_req_grant) 1'd0: begin - vns_t_array_muxed5 <= soc_sdram_bankmachine0_cmd_payload_we; + rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - vns_t_array_muxed5 <= soc_sdram_bankmachine1_cmd_payload_we; + rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - vns_t_array_muxed5 <= soc_sdram_bankmachine2_cmd_payload_we; + rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - vns_t_array_muxed5 <= soc_sdram_bankmachine3_cmd_payload_we; + rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - vns_t_array_muxed5 <= soc_sdram_bankmachine4_cmd_payload_we; + rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - vns_t_array_muxed5 <= soc_sdram_bankmachine5_cmd_payload_we; + rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - vns_t_array_muxed5 <= soc_sdram_bankmachine6_cmd_payload_we; + rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; end default: begin - vns_t_array_muxed5 <= soc_sdram_bankmachine7_cmd_payload_we; + rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_355 = dummy_s; + dummy_d_295 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_356; +reg dummy_d_296; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed12 <= 21'd0; - case (vns_roundrobin0_grant) + rhs_array_muxed8 <= 3'd0; + case (litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed12 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]}; + rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; end - default: begin - vns_rhs_array_muxed12 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]}; + 1'd1: begin + rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; end - endcase -// synthesis translate_off - dummy_d_356 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_357; -// synthesis translate_on -always @(*) begin - vns_rhs_array_muxed13 <= 1'd0; - case (vns_roundrobin0_grant) - 1'd0: begin - vns_rhs_array_muxed13 <= soc_port_cmd_payload_we; + 2'd2: begin + rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; end default: begin - vns_rhs_array_muxed13 <= soc_cmd_payload_we; + rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; end endcase // synthesis translate_off - dummy_d_357 = dummy_s; + dummy_d_296 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_358; +reg dummy_d_297; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed14 <= 1'd0; - case (vns_roundrobin0_grant) + rhs_array_muxed9 <= 1'd0; + case (litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed14 <= (((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); + rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - vns_rhs_array_muxed14 <= (((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; end endcase // synthesis translate_off - dummy_d_358 = dummy_s; + dummy_d_297 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_359; +reg dummy_d_298; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed15 <= 21'd0; - case (vns_roundrobin1_grant) + rhs_array_muxed10 <= 1'd0; + case (litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed15 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]}; + rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - vns_rhs_array_muxed15 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]}; + rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; end endcase // synthesis translate_off - dummy_d_359 = dummy_s; + dummy_d_298 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_360; +reg dummy_d_299; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed16 <= 1'd0; - case (vns_roundrobin1_grant) + rhs_array_muxed11 <= 1'd0; + case (litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed16 <= soc_port_cmd_payload_we; + rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - vns_rhs_array_muxed16 <= soc_cmd_payload_we; + rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase // synthesis translate_off - dummy_d_360 = dummy_s; + dummy_d_299 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_361; +reg dummy_d_300; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed17 <= 1'd0; - case (vns_roundrobin1_grant) + t_array_muxed3 <= 1'd0; + case (litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed17 <= (((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); + t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; end default: begin - vns_rhs_array_muxed17 <= (((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; end endcase // synthesis translate_off - dummy_d_361 = dummy_s; + dummy_d_300 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_362; +reg dummy_d_301; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed18 <= 21'd0; - case (vns_roundrobin2_grant) + t_array_muxed4 <= 1'd0; + case (litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed18 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]}; + t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; end default: begin - vns_rhs_array_muxed18 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]}; + t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; end endcase // synthesis translate_off - dummy_d_362 = dummy_s; + dummy_d_301 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_363; +reg dummy_d_302; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed19 <= 1'd0; - case (vns_roundrobin2_grant) + t_array_muxed5 <= 1'd0; + case (litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed19 <= soc_port_cmd_payload_we; + t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; end default: begin - vns_rhs_array_muxed19 <= soc_cmd_payload_we; + t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_363 = dummy_s; + dummy_d_302 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_364; +reg dummy_d_303; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed20 <= 1'd0; - case (vns_roundrobin2_grant) - 1'd0: begin - vns_rhs_array_muxed20 <= (((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); - end + rhs_array_muxed12 <= 21'd0; + case (roundrobin0_grant) default: begin - vns_rhs_array_muxed20 <= (((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + rhs_array_muxed12 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_364 = dummy_s; + dummy_d_303 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_365; +reg dummy_d_304; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed21 <= 21'd0; - case (vns_roundrobin3_grant) - 1'd0: begin - vns_rhs_array_muxed21 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]}; - end + rhs_array_muxed13 <= 1'd0; + case (roundrobin0_grant) default: begin - vns_rhs_array_muxed21 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]}; + rhs_array_muxed13 <= user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_365 = dummy_s; + dummy_d_304 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_366; +reg dummy_d_305; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed22 <= 1'd0; - case (vns_roundrobin3_grant) - 1'd0: begin - vns_rhs_array_muxed22 <= soc_port_cmd_payload_we; - end + rhs_array_muxed14 <= 1'd0; + case (roundrobin0_grant) default: begin - vns_rhs_array_muxed22 <= soc_cmd_payload_we; + rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_366 = dummy_s; + dummy_d_305 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_367; +reg dummy_d_306; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed23 <= 1'd0; - case (vns_roundrobin3_grant) - 1'd0: begin - vns_rhs_array_muxed23 <= (((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); - end + rhs_array_muxed15 <= 21'd0; + case (roundrobin1_grant) default: begin - vns_rhs_array_muxed23 <= (((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + rhs_array_muxed15 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_367 = dummy_s; + dummy_d_306 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_368; +reg dummy_d_307; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed24 <= 21'd0; - case (vns_roundrobin4_grant) - 1'd0: begin - vns_rhs_array_muxed24 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]}; - end + rhs_array_muxed16 <= 1'd0; + case (roundrobin1_grant) default: begin - vns_rhs_array_muxed24 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]}; + rhs_array_muxed16 <= user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_368 = dummy_s; + dummy_d_307 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_369; +reg dummy_d_308; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed25 <= 1'd0; - case (vns_roundrobin4_grant) - 1'd0: begin - vns_rhs_array_muxed25 <= soc_port_cmd_payload_we; - end + rhs_array_muxed17 <= 1'd0; + case (roundrobin1_grant) default: begin - vns_rhs_array_muxed25 <= soc_cmd_payload_we; + rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_369 = dummy_s; + dummy_d_308 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_370; +reg dummy_d_309; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed26 <= 1'd0; - case (vns_roundrobin4_grant) - 1'd0: begin - vns_rhs_array_muxed26 <= (((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); - end + rhs_array_muxed18 <= 21'd0; + case (roundrobin2_grant) default: begin - vns_rhs_array_muxed26 <= (((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + rhs_array_muxed18 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_370 = dummy_s; + dummy_d_309 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_371; +reg dummy_d_310; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed27 <= 21'd0; - case (vns_roundrobin5_grant) - 1'd0: begin - vns_rhs_array_muxed27 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]}; - end + rhs_array_muxed19 <= 1'd0; + case (roundrobin2_grant) default: begin - vns_rhs_array_muxed27 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]}; + rhs_array_muxed19 <= user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_371 = dummy_s; + dummy_d_310 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_372; +reg dummy_d_311; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed28 <= 1'd0; - case (vns_roundrobin5_grant) - 1'd0: begin - vns_rhs_array_muxed28 <= soc_port_cmd_payload_we; - end + rhs_array_muxed20 <= 1'd0; + case (roundrobin2_grant) default: begin - vns_rhs_array_muxed28 <= soc_cmd_payload_we; + rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_372 = dummy_s; + dummy_d_311 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_373; +reg dummy_d_312; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed29 <= 1'd0; - case (vns_roundrobin5_grant) - 1'd0: begin - vns_rhs_array_muxed29 <= (((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); - end + rhs_array_muxed21 <= 21'd0; + case (roundrobin3_grant) default: begin - vns_rhs_array_muxed29 <= (((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + rhs_array_muxed21 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_373 = dummy_s; + dummy_d_312 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_374; +reg dummy_d_313; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed30 <= 21'd0; - case (vns_roundrobin6_grant) - 1'd0: begin - vns_rhs_array_muxed30 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]}; - end + rhs_array_muxed22 <= 1'd0; + case (roundrobin3_grant) default: begin - vns_rhs_array_muxed30 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]}; + rhs_array_muxed22 <= user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_374 = dummy_s; + dummy_d_313 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_375; +reg dummy_d_314; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed31 <= 1'd0; - case (vns_roundrobin6_grant) - 1'd0: begin - vns_rhs_array_muxed31 <= soc_port_cmd_payload_we; - end + rhs_array_muxed23 <= 1'd0; + case (roundrobin3_grant) default: begin - vns_rhs_array_muxed31 <= soc_cmd_payload_we; + rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_375 = dummy_s; + dummy_d_314 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_376; +reg dummy_d_315; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed32 <= 1'd0; - case (vns_roundrobin6_grant) - 1'd0: begin - vns_rhs_array_muxed32 <= (((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); - end + rhs_array_muxed24 <= 21'd0; + case (roundrobin4_grant) default: begin - vns_rhs_array_muxed32 <= (((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + rhs_array_muxed24 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_376 = dummy_s; + dummy_d_315 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_377; +reg dummy_d_316; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed33 <= 21'd0; - case (vns_roundrobin7_grant) - 1'd0: begin - vns_rhs_array_muxed33 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]}; - end + rhs_array_muxed25 <= 1'd0; + case (roundrobin4_grant) default: begin - vns_rhs_array_muxed33 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]}; + rhs_array_muxed25 <= user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_377 = dummy_s; + dummy_d_316 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_378; +reg dummy_d_317; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed34 <= 1'd0; - case (vns_roundrobin7_grant) - 1'd0: begin - vns_rhs_array_muxed34 <= soc_port_cmd_payload_we; - end + rhs_array_muxed26 <= 1'd0; + case (roundrobin4_grant) default: begin - vns_rhs_array_muxed34 <= soc_cmd_payload_we; + rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_378 = dummy_s; + dummy_d_317 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_379; +reg dummy_d_318; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed35 <= 1'd0; - case (vns_roundrobin7_grant) - 1'd0: begin - vns_rhs_array_muxed35 <= (((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_port_cmd_valid); - end + rhs_array_muxed27 <= 21'd0; + case (roundrobin5_grant) default: begin - vns_rhs_array_muxed35 <= (((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))))) & soc_cmd_valid); + rhs_array_muxed27 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_379 = dummy_s; + dummy_d_318 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_380; +reg dummy_d_319; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed36 <= 30'd0; - case (vns_grant) - 1'd0: begin - vns_rhs_array_muxed36 <= soc_litedramcore_cpu_ibus_adr; - end + rhs_array_muxed28 <= 1'd0; + case (roundrobin5_grant) default: begin - vns_rhs_array_muxed36 <= soc_litedramcore_cpu_dbus_adr; + rhs_array_muxed28 <= user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_380 = dummy_s; + dummy_d_319 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_381; +reg dummy_d_320; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed37 <= 32'd0; - case (vns_grant) - 1'd0: begin - vns_rhs_array_muxed37 <= soc_litedramcore_cpu_ibus_dat_w; - end + rhs_array_muxed29 <= 1'd0; + case (roundrobin5_grant) default: begin - vns_rhs_array_muxed37 <= soc_litedramcore_cpu_dbus_dat_w; + rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_381 = dummy_s; + dummy_d_320 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_382; +reg dummy_d_321; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed38 <= 4'd0; - case (vns_grant) - 1'd0: begin - vns_rhs_array_muxed38 <= soc_litedramcore_cpu_ibus_sel; - end + rhs_array_muxed30 <= 21'd0; + case (roundrobin6_grant) default: begin - vns_rhs_array_muxed38 <= soc_litedramcore_cpu_dbus_sel; + rhs_array_muxed30 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_382 = dummy_s; + dummy_d_321 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_383; +reg dummy_d_322; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed39 <= 1'd0; - case (vns_grant) - 1'd0: begin - vns_rhs_array_muxed39 <= soc_litedramcore_cpu_ibus_cyc; - end + rhs_array_muxed31 <= 1'd0; + case (roundrobin6_grant) default: begin - vns_rhs_array_muxed39 <= soc_litedramcore_cpu_dbus_cyc; + rhs_array_muxed31 <= user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_383 = dummy_s; + dummy_d_322 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_384; +reg dummy_d_323; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed40 <= 1'd0; - case (vns_grant) - 1'd0: begin - vns_rhs_array_muxed40 <= soc_litedramcore_cpu_ibus_stb; - end + rhs_array_muxed32 <= 1'd0; + case (roundrobin6_grant) default: begin - vns_rhs_array_muxed40 <= soc_litedramcore_cpu_dbus_stb; + rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_384 = dummy_s; + dummy_d_323 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_385; +reg dummy_d_324; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed41 <= 1'd0; - case (vns_grant) - 1'd0: begin - vns_rhs_array_muxed41 <= soc_litedramcore_cpu_ibus_we; - end + rhs_array_muxed33 <= 21'd0; + case (roundrobin7_grant) default: begin - vns_rhs_array_muxed41 <= soc_litedramcore_cpu_dbus_we; + rhs_array_muxed33 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_385 = dummy_s; + dummy_d_324 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_386; +reg dummy_d_325; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed42 <= 3'd0; - case (vns_grant) - 1'd0: begin - vns_rhs_array_muxed42 <= soc_litedramcore_cpu_ibus_cti; - end + rhs_array_muxed34 <= 1'd0; + case (roundrobin7_grant) default: begin - vns_rhs_array_muxed42 <= soc_litedramcore_cpu_dbus_cti; + rhs_array_muxed34 <= user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_386 = dummy_s; + dummy_d_325 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_387; +reg dummy_d_326; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed43 <= 2'd0; - case (vns_grant) - 1'd0: begin - vns_rhs_array_muxed43 <= soc_litedramcore_cpu_ibus_bte; - end + rhs_array_muxed35 <= 1'd0; + case (roundrobin7_grant) default: begin - vns_rhs_array_muxed43 <= soc_litedramcore_cpu_dbus_bte; + rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_387 = dummy_s; + dummy_d_326 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_388; +reg dummy_d_327; // synthesis translate_on always @(*) begin - vns_array_muxed0 <= 3'd0; - case (soc_sdram_steerer_sel0) + array_muxed0 <= 3'd0; + case (litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed0 <= soc_sdram_nop_ba[2:0]; + array_muxed0 <= litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed0 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0]; + array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed0 <= soc_sdram_choose_req_cmd_payload_ba[2:0]; + array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed0 <= soc_sdram_cmd_payload_ba[2:0]; + array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_388 = dummy_s; + dummy_d_327 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_389; +reg dummy_d_328; // synthesis translate_on always @(*) begin - vns_array_muxed1 <= 14'd0; - case (soc_sdram_steerer_sel0) + array_muxed1 <= 14'd0; + case (litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed1 <= soc_sdram_nop_a; + array_muxed1 <= litedramcore_nop_a; end 1'd1: begin - vns_array_muxed1 <= soc_sdram_choose_cmd_cmd_payload_a; + array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed1 <= soc_sdram_choose_req_cmd_payload_a; + array_muxed1 <= litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed1 <= soc_sdram_cmd_payload_a; + array_muxed1 <= litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_389 = dummy_s; + dummy_d_328 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_390; +reg dummy_d_329; // synthesis translate_on always @(*) begin - vns_array_muxed2 <= 1'd0; - case (soc_sdram_steerer_sel0) + array_muxed2 <= 1'd0; + case (litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed2 <= 1'd0; + array_muxed2 <= 1'd0; end 1'd1: begin - vns_array_muxed2 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas); + array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed2 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas); + array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed2 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas); + array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_390 = dummy_s; + dummy_d_329 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_391; +reg dummy_d_330; // synthesis translate_on always @(*) begin - vns_array_muxed3 <= 1'd0; - case (soc_sdram_steerer_sel0) + array_muxed3 <= 1'd0; + case (litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed3 <= 1'd0; + array_muxed3 <= 1'd0; end 1'd1: begin - vns_array_muxed3 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras); + array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed3 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras); + array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed3 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras); + array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_391 = dummy_s; + dummy_d_330 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_392; +reg dummy_d_331; // synthesis translate_on always @(*) begin - vns_array_muxed4 <= 1'd0; - case (soc_sdram_steerer_sel0) + array_muxed4 <= 1'd0; + case (litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed4 <= 1'd0; + array_muxed4 <= 1'd0; end 1'd1: begin - vns_array_muxed4 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we); + array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed4 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we); + array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed4 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we); + array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_392 = dummy_s; + dummy_d_331 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_393; +reg dummy_d_332; // synthesis translate_on always @(*) begin - vns_array_muxed5 <= 1'd0; - case (soc_sdram_steerer_sel0) + array_muxed5 <= 1'd0; + case (litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed5 <= 1'd0; + array_muxed5 <= 1'd0; end 1'd1: begin - vns_array_muxed5 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read); + array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed5 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read); + array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed5 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read); + array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_393 = dummy_s; + dummy_d_332 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_394; +reg dummy_d_333; // synthesis translate_on always @(*) begin - vns_array_muxed6 <= 1'd0; - case (soc_sdram_steerer_sel0) + array_muxed6 <= 1'd0; + case (litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed6 <= 1'd0; + array_muxed6 <= 1'd0; end 1'd1: begin - vns_array_muxed6 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write); + array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed6 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write); + array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed6 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write); + array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_394 = dummy_s; + dummy_d_333 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_395; +reg dummy_d_334; // synthesis translate_on always @(*) begin - vns_array_muxed7 <= 3'd0; - case (soc_sdram_steerer_sel1) + array_muxed7 <= 3'd0; + case (litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed7 <= soc_sdram_nop_ba[2:0]; + array_muxed7 <= litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed7 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0]; + array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed7 <= soc_sdram_choose_req_cmd_payload_ba[2:0]; + array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed7 <= soc_sdram_cmd_payload_ba[2:0]; + array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_395 = dummy_s; + dummy_d_334 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_396; +reg dummy_d_335; // synthesis translate_on always @(*) begin - vns_array_muxed8 <= 14'd0; - case (soc_sdram_steerer_sel1) + array_muxed8 <= 14'd0; + case (litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed8 <= soc_sdram_nop_a; + array_muxed8 <= litedramcore_nop_a; end 1'd1: begin - vns_array_muxed8 <= soc_sdram_choose_cmd_cmd_payload_a; + array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed8 <= soc_sdram_choose_req_cmd_payload_a; + array_muxed8 <= litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed8 <= soc_sdram_cmd_payload_a; + array_muxed8 <= litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_396 = dummy_s; + dummy_d_335 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_397; +reg dummy_d_336; // synthesis translate_on always @(*) begin - vns_array_muxed9 <= 1'd0; - case (soc_sdram_steerer_sel1) + array_muxed9 <= 1'd0; + case (litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed9 <= 1'd0; + array_muxed9 <= 1'd0; end 1'd1: begin - vns_array_muxed9 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas); + array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed9 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas); + array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed9 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas); + array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_397 = dummy_s; + dummy_d_336 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_398; +reg dummy_d_337; // synthesis translate_on always @(*) begin - vns_array_muxed10 <= 1'd0; - case (soc_sdram_steerer_sel1) + array_muxed10 <= 1'd0; + case (litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed10 <= 1'd0; + array_muxed10 <= 1'd0; end 1'd1: begin - vns_array_muxed10 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras); + array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed10 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras); + array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed10 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras); + array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_398 = dummy_s; + dummy_d_337 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_399; +reg dummy_d_338; // synthesis translate_on always @(*) begin - vns_array_muxed11 <= 1'd0; - case (soc_sdram_steerer_sel1) + array_muxed11 <= 1'd0; + case (litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed11 <= 1'd0; + array_muxed11 <= 1'd0; end 1'd1: begin - vns_array_muxed11 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we); + array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed11 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we); + array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed11 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we); + array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_399 = dummy_s; + dummy_d_338 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_400; +reg dummy_d_339; // synthesis translate_on always @(*) begin - vns_array_muxed12 <= 1'd0; - case (soc_sdram_steerer_sel1) + array_muxed12 <= 1'd0; + case (litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed12 <= 1'd0; + array_muxed12 <= 1'd0; end 1'd1: begin - vns_array_muxed12 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read); + array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed12 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read); + array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed12 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read); + array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_400 = dummy_s; + dummy_d_339 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_401; +reg dummy_d_340; // synthesis translate_on always @(*) begin - vns_array_muxed13 <= 1'd0; - case (soc_sdram_steerer_sel1) + array_muxed13 <= 1'd0; + case (litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed13 <= 1'd0; + array_muxed13 <= 1'd0; end 1'd1: begin - vns_array_muxed13 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write); + array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed13 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write); + array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed13 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write); + array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_401 = dummy_s; + dummy_d_340 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_402; +reg dummy_d_341; // synthesis translate_on always @(*) begin - vns_array_muxed14 <= 3'd0; - case (soc_sdram_steerer_sel2) + array_muxed14 <= 3'd0; + case (litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed14 <= soc_sdram_nop_ba[2:0]; + array_muxed14 <= litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed14 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0]; + array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed14 <= soc_sdram_choose_req_cmd_payload_ba[2:0]; + array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed14 <= soc_sdram_cmd_payload_ba[2:0]; + array_muxed14 <= litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_402 = dummy_s; + dummy_d_341 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_403; +reg dummy_d_342; // synthesis translate_on always @(*) begin - vns_array_muxed15 <= 14'd0; - case (soc_sdram_steerer_sel2) + array_muxed15 <= 14'd0; + case (litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed15 <= soc_sdram_nop_a; + array_muxed15 <= litedramcore_nop_a; end 1'd1: begin - vns_array_muxed15 <= soc_sdram_choose_cmd_cmd_payload_a; + array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed15 <= soc_sdram_choose_req_cmd_payload_a; + array_muxed15 <= litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed15 <= soc_sdram_cmd_payload_a; + array_muxed15 <= litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_403 = dummy_s; + dummy_d_342 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_404; +reg dummy_d_343; // synthesis translate_on always @(*) begin - vns_array_muxed16 <= 1'd0; - case (soc_sdram_steerer_sel2) + array_muxed16 <= 1'd0; + case (litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed16 <= 1'd0; + array_muxed16 <= 1'd0; end 1'd1: begin - vns_array_muxed16 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas); + array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed16 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas); + array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed16 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas); + array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_404 = dummy_s; + dummy_d_343 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_405; +reg dummy_d_344; // synthesis translate_on always @(*) begin - vns_array_muxed17 <= 1'd0; - case (soc_sdram_steerer_sel2) + array_muxed17 <= 1'd0; + case (litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed17 <= 1'd0; + array_muxed17 <= 1'd0; end 1'd1: begin - vns_array_muxed17 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras); + array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed17 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras); + array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed17 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras); + array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_405 = dummy_s; + dummy_d_344 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_406; +reg dummy_d_345; // synthesis translate_on always @(*) begin - vns_array_muxed18 <= 1'd0; - case (soc_sdram_steerer_sel2) + array_muxed18 <= 1'd0; + case (litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed18 <= 1'd0; + array_muxed18 <= 1'd0; end 1'd1: begin - vns_array_muxed18 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we); + array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed18 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we); + array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed18 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we); + array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_406 = dummy_s; + dummy_d_345 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_407; +reg dummy_d_346; // synthesis translate_on always @(*) begin - vns_array_muxed19 <= 1'd0; - case (soc_sdram_steerer_sel2) + array_muxed19 <= 1'd0; + case (litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed19 <= 1'd0; + array_muxed19 <= 1'd0; end 1'd1: begin - vns_array_muxed19 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read); + array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed19 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read); + array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed19 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read); + array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_407 = dummy_s; + dummy_d_346 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_408; +reg dummy_d_347; // synthesis translate_on always @(*) begin - vns_array_muxed20 <= 1'd0; - case (soc_sdram_steerer_sel2) + array_muxed20 <= 1'd0; + case (litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed20 <= 1'd0; + array_muxed20 <= 1'd0; end 1'd1: begin - vns_array_muxed20 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write); + array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed20 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write); + array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed20 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write); + array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_408 = dummy_s; + dummy_d_347 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_409; +reg dummy_d_348; // synthesis translate_on always @(*) begin - vns_array_muxed21 <= 3'd0; - case (soc_sdram_steerer_sel3) + array_muxed21 <= 3'd0; + case (litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed21 <= soc_sdram_nop_ba[2:0]; + array_muxed21 <= litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed21 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0]; + array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed21 <= soc_sdram_choose_req_cmd_payload_ba[2:0]; + array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed21 <= soc_sdram_cmd_payload_ba[2:0]; + array_muxed21 <= litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_409 = dummy_s; + dummy_d_348 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_410; +reg dummy_d_349; // synthesis translate_on always @(*) begin - vns_array_muxed22 <= 14'd0; - case (soc_sdram_steerer_sel3) + array_muxed22 <= 14'd0; + case (litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed22 <= soc_sdram_nop_a; + array_muxed22 <= litedramcore_nop_a; end 1'd1: begin - vns_array_muxed22 <= soc_sdram_choose_cmd_cmd_payload_a; + array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed22 <= soc_sdram_choose_req_cmd_payload_a; + array_muxed22 <= litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed22 <= soc_sdram_cmd_payload_a; + array_muxed22 <= litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_410 = dummy_s; + dummy_d_349 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_411; +reg dummy_d_350; // synthesis translate_on always @(*) begin - vns_array_muxed23 <= 1'd0; - case (soc_sdram_steerer_sel3) + array_muxed23 <= 1'd0; + case (litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed23 <= 1'd0; + array_muxed23 <= 1'd0; end 1'd1: begin - vns_array_muxed23 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas); + array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed23 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas); + array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed23 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas); + array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_411 = dummy_s; + dummy_d_350 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_412; +reg dummy_d_351; // synthesis translate_on always @(*) begin - vns_array_muxed24 <= 1'd0; - case (soc_sdram_steerer_sel3) + array_muxed24 <= 1'd0; + case (litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed24 <= 1'd0; + array_muxed24 <= 1'd0; end 1'd1: begin - vns_array_muxed24 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras); + array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed24 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras); + array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed24 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras); + array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_412 = dummy_s; + dummy_d_351 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_413; +reg dummy_d_352; // synthesis translate_on always @(*) begin - vns_array_muxed25 <= 1'd0; - case (soc_sdram_steerer_sel3) + array_muxed25 <= 1'd0; + case (litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed25 <= 1'd0; + array_muxed25 <= 1'd0; end 1'd1: begin - vns_array_muxed25 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we); + array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed25 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we); + array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed25 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we); + array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_413 = dummy_s; + dummy_d_352 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_414; +reg dummy_d_353; // synthesis translate_on always @(*) begin - vns_array_muxed26 <= 1'd0; - case (soc_sdram_steerer_sel3) + array_muxed26 <= 1'd0; + case (litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed26 <= 1'd0; + array_muxed26 <= 1'd0; end 1'd1: begin - vns_array_muxed26 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read); + array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed26 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read); + array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed26 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read); + array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_414 = dummy_s; + dummy_d_353 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_415; +reg dummy_d_354; // synthesis translate_on always @(*) begin - vns_array_muxed27 <= 1'd0; - case (soc_sdram_steerer_sel3) + array_muxed27 <= 1'd0; + case (litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed27 <= 1'd0; + array_muxed27 <= 1'd0; end 1'd1: begin - vns_array_muxed27 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write); + array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed27 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write); + array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed27 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write); + array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_415 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_rx = vns_regs1; -assign vns_xilinxasyncresetsynchronizerimpl0 = ((~soc_sys_pll_locked) | soc_sys_pll_reset); -assign vns_xilinxasyncresetsynchronizerimpl1 = ((~soc_sys_pll_locked) | soc_sys_pll_reset); -assign vns_xilinxasyncresetsynchronizerimpl2 = ((~soc_sys_pll_locked) | soc_sys_pll_reset); -assign vns_xilinxasyncresetsynchronizerimpl3 = ((~soc_iodelay_pll_locked) | soc_iodelay_pll_reset); - -always @(posedge iodelay_clk) begin - if ((soc_reset_counter != 1'd0)) begin - soc_reset_counter <= (soc_reset_counter - 1'd1); - end else begin - soc_ic_reset <= 1'd0; - end - if (iodelay_rst) begin - soc_reset_counter <= 4'd15; - soc_ic_reset <= 1'd1; - end -end - -always @(posedge sys_clk) begin - if ((soc_litedramcore_soccontroller_bus_errors != 32'd4294967295)) begin - if (soc_litedramcore_soccontroller_bus_error) begin - soc_litedramcore_soccontroller_bus_errors <= (soc_litedramcore_soccontroller_bus_errors + 1'd1); - end - end - soc_litedramcore_litedramcore_ram_bus_ack <= 1'd0; - if (((soc_litedramcore_litedramcore_ram_bus_cyc & soc_litedramcore_litedramcore_ram_bus_stb) & (~soc_litedramcore_litedramcore_ram_bus_ack))) begin - soc_litedramcore_litedramcore_ram_bus_ack <= 1'd1; - end - soc_litedramcore_ram_bus_ram_bus_ack <= 1'd0; - if (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & (~soc_litedramcore_ram_bus_ram_bus_ack))) begin - soc_litedramcore_ram_bus_ram_bus_ack <= 1'd1; - end - soc_litedramcore_sink_ready <= 1'd0; - if (((soc_litedramcore_sink_valid & (~soc_litedramcore_tx_busy)) & (~soc_litedramcore_sink_ready))) begin - soc_litedramcore_tx_reg <= soc_litedramcore_sink_payload_data; - soc_litedramcore_tx_bitcount <= 1'd0; - soc_litedramcore_tx_busy <= 1'd1; - serial_tx <= 1'd0; - end else begin - if ((soc_litedramcore_uart_clk_txen & soc_litedramcore_tx_busy)) begin - soc_litedramcore_tx_bitcount <= (soc_litedramcore_tx_bitcount + 1'd1); - if ((soc_litedramcore_tx_bitcount == 4'd8)) begin - serial_tx <= 1'd1; - end else begin - if ((soc_litedramcore_tx_bitcount == 4'd9)) begin - serial_tx <= 1'd1; - soc_litedramcore_tx_busy <= 1'd0; - soc_litedramcore_sink_ready <= 1'd1; - end else begin - serial_tx <= soc_litedramcore_tx_reg[0]; - soc_litedramcore_tx_reg <= {1'd0, soc_litedramcore_tx_reg[7:1]}; - end - end - end - end - if (soc_litedramcore_tx_busy) begin - {soc_litedramcore_uart_clk_txen, soc_litedramcore_phase_accumulator_tx} <= (soc_litedramcore_phase_accumulator_tx + soc_litedramcore_storage); - end else begin - {soc_litedramcore_uart_clk_txen, soc_litedramcore_phase_accumulator_tx} <= 1'd0; - end - soc_litedramcore_source_valid <= 1'd0; - soc_litedramcore_rx_r <= soc_litedramcore_rx; - if ((~soc_litedramcore_rx_busy)) begin - if (((~soc_litedramcore_rx) & soc_litedramcore_rx_r)) begin - soc_litedramcore_rx_busy <= 1'd1; - soc_litedramcore_rx_bitcount <= 1'd0; - end - end else begin - if (soc_litedramcore_uart_clk_rxen) begin - soc_litedramcore_rx_bitcount <= (soc_litedramcore_rx_bitcount + 1'd1); - if ((soc_litedramcore_rx_bitcount == 1'd0)) begin - if (soc_litedramcore_rx) begin - soc_litedramcore_rx_busy <= 1'd0; - end - end else begin - if ((soc_litedramcore_rx_bitcount == 4'd9)) begin - soc_litedramcore_rx_busy <= 1'd0; - if (soc_litedramcore_rx) begin - soc_litedramcore_source_payload_data <= soc_litedramcore_rx_reg; - soc_litedramcore_source_valid <= 1'd1; - end - end else begin - soc_litedramcore_rx_reg <= {soc_litedramcore_rx, soc_litedramcore_rx_reg[7:1]}; - end - end - end - end - if (soc_litedramcore_rx_busy) begin - {soc_litedramcore_uart_clk_rxen, soc_litedramcore_phase_accumulator_rx} <= (soc_litedramcore_phase_accumulator_rx + soc_litedramcore_storage); - end else begin - {soc_litedramcore_uart_clk_rxen, soc_litedramcore_phase_accumulator_rx} <= 32'd2147483648; - end - if (soc_litedramcore_uart_tx_clear) begin - soc_litedramcore_uart_tx_pending <= 1'd0; - end - soc_litedramcore_uart_tx_old_trigger <= soc_litedramcore_uart_tx_trigger; - if (((~soc_litedramcore_uart_tx_trigger) & soc_litedramcore_uart_tx_old_trigger)) begin - soc_litedramcore_uart_tx_pending <= 1'd1; - end - if (soc_litedramcore_uart_rx_clear) begin - soc_litedramcore_uart_rx_pending <= 1'd0; - end - soc_litedramcore_uart_rx_old_trigger <= soc_litedramcore_uart_rx_trigger; - if (((~soc_litedramcore_uart_rx_trigger) & soc_litedramcore_uart_rx_old_trigger)) begin - soc_litedramcore_uart_rx_pending <= 1'd1; - end - if (soc_litedramcore_uart_tx_fifo_syncfifo_re) begin - soc_litedramcore_uart_tx_fifo_readable <= 1'd1; - end else begin - if (soc_litedramcore_uart_tx_fifo_re) begin - soc_litedramcore_uart_tx_fifo_readable <= 1'd0; - end - end - if (((soc_litedramcore_uart_tx_fifo_syncfifo_we & soc_litedramcore_uart_tx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_tx_fifo_replace))) begin - soc_litedramcore_uart_tx_fifo_produce <= (soc_litedramcore_uart_tx_fifo_produce + 1'd1); - end - if (soc_litedramcore_uart_tx_fifo_do_read) begin - soc_litedramcore_uart_tx_fifo_consume <= (soc_litedramcore_uart_tx_fifo_consume + 1'd1); - end - if (((soc_litedramcore_uart_tx_fifo_syncfifo_we & soc_litedramcore_uart_tx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_tx_fifo_replace))) begin - if ((~soc_litedramcore_uart_tx_fifo_do_read)) begin - soc_litedramcore_uart_tx_fifo_level0 <= (soc_litedramcore_uart_tx_fifo_level0 + 1'd1); - end - end else begin - if (soc_litedramcore_uart_tx_fifo_do_read) begin - soc_litedramcore_uart_tx_fifo_level0 <= (soc_litedramcore_uart_tx_fifo_level0 - 1'd1); - end - end - if (soc_litedramcore_uart_rx_fifo_syncfifo_re) begin - soc_litedramcore_uart_rx_fifo_readable <= 1'd1; - end else begin - if (soc_litedramcore_uart_rx_fifo_re) begin - soc_litedramcore_uart_rx_fifo_readable <= 1'd0; - end - end - if (((soc_litedramcore_uart_rx_fifo_syncfifo_we & soc_litedramcore_uart_rx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_rx_fifo_replace))) begin - soc_litedramcore_uart_rx_fifo_produce <= (soc_litedramcore_uart_rx_fifo_produce + 1'd1); - end - if (soc_litedramcore_uart_rx_fifo_do_read) begin - soc_litedramcore_uart_rx_fifo_consume <= (soc_litedramcore_uart_rx_fifo_consume + 1'd1); - end - if (((soc_litedramcore_uart_rx_fifo_syncfifo_we & soc_litedramcore_uart_rx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_rx_fifo_replace))) begin - if ((~soc_litedramcore_uart_rx_fifo_do_read)) begin - soc_litedramcore_uart_rx_fifo_level0 <= (soc_litedramcore_uart_rx_fifo_level0 + 1'd1); - end - end else begin - if (soc_litedramcore_uart_rx_fifo_do_read) begin - soc_litedramcore_uart_rx_fifo_level0 <= (soc_litedramcore_uart_rx_fifo_level0 - 1'd1); - end - end - if (soc_litedramcore_uart_reset) begin - soc_litedramcore_uart_tx_pending <= 1'd0; - soc_litedramcore_uart_tx_old_trigger <= 1'd0; - soc_litedramcore_uart_rx_pending <= 1'd0; - soc_litedramcore_uart_rx_old_trigger <= 1'd0; - soc_litedramcore_uart_tx_fifo_readable <= 1'd0; - soc_litedramcore_uart_tx_fifo_level0 <= 5'd0; - soc_litedramcore_uart_tx_fifo_produce <= 4'd0; - soc_litedramcore_uart_tx_fifo_consume <= 4'd0; - soc_litedramcore_uart_rx_fifo_readable <= 1'd0; - soc_litedramcore_uart_rx_fifo_level0 <= 5'd0; - soc_litedramcore_uart_rx_fifo_produce <= 4'd0; - soc_litedramcore_uart_rx_fifo_consume <= 4'd0; - end - if (soc_litedramcore_timer_en_storage) begin - if ((soc_litedramcore_timer_value == 1'd0)) begin - soc_litedramcore_timer_value <= soc_litedramcore_timer_reload_storage; - end else begin - soc_litedramcore_timer_value <= (soc_litedramcore_timer_value - 1'd1); - end + dummy_d_354 = dummy_s; +// synthesis translate_on +end +assign xilinxasyncresetsynchronizerimpl0 = ((~sys_pll_locked) | sys_pll_reset); +assign xilinxasyncresetsynchronizerimpl1 = ((~sys_pll_locked) | sys_pll_reset); +assign xilinxasyncresetsynchronizerimpl2 = ((~sys_pll_locked) | sys_pll_reset); +assign xilinxasyncresetsynchronizerimpl3 = ((~iodelay_pll_locked) | iodelay_pll_reset); + +always @(posedge iodelay_clk) begin + if ((reset_counter != 1'd0)) begin + reset_counter <= (reset_counter - 1'd1); end else begin - soc_litedramcore_timer_value <= soc_litedramcore_timer_load_storage; - end - if (soc_litedramcore_timer_update_value_re) begin - soc_litedramcore_timer_value_status <= soc_litedramcore_timer_value; + ic_reset <= 1'd0; end - if (soc_litedramcore_timer_zero_clear) begin - soc_litedramcore_timer_zero_pending <= 1'd0; - end - soc_litedramcore_timer_zero_old_trigger <= soc_litedramcore_timer_zero_trigger; - if (((~soc_litedramcore_timer_zero_trigger) & soc_litedramcore_timer_zero_old_trigger)) begin - soc_litedramcore_timer_zero_pending <= 1'd1; + if (iodelay_rst) begin + reset_counter <= 4'd15; + ic_reset <= 1'd1; end - vns_wb2csr_state <= vns_wb2csr_next_state; - soc_a7ddrphy_dqs_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dqs_oe) | soc_a7ddrphy_dqspattern1); - soc_a7ddrphy_dq_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dq_oe) | soc_a7ddrphy_dqspattern1); - soc_a7ddrphy_rddata_en_last <= soc_a7ddrphy_rddata_en; - soc_a7ddrphy_dfi_p0_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); - soc_a7ddrphy_dfi_p1_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); - soc_a7ddrphy_dfi_p2_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); - soc_a7ddrphy_dfi_p3_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); - soc_a7ddrphy_wrdata_en_last <= soc_a7ddrphy_wrdata_en; - soc_a7ddrphy_dqspattern_o1 <= soc_a7ddrphy_dqspattern_o0; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip0_value <= (soc_a7ddrphy_bitslip0_value + 1'd1); +end + +always @(posedge sys_clk) begin + a7ddrphy_dqs_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dqs_oe) | a7ddrphy_dqspattern1); + a7ddrphy_dq_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dq_oe) | a7ddrphy_dqspattern1); + a7ddrphy_rddata_en_last <= a7ddrphy_rddata_en; + a7ddrphy_dfi_p0_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage); + a7ddrphy_dfi_p1_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage); + a7ddrphy_dfi_p2_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage); + a7ddrphy_dfi_p3_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage); + a7ddrphy_wrdata_en_last <= a7ddrphy_wrdata_en; + a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value <= (a7ddrphy_bitslip0_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip0_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip0_value <= 1'd0; end - soc_a7ddrphy_bitslip0_r <= {soc_a7ddrphy_bitslip0_i, soc_a7ddrphy_bitslip0_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip1_value <= (soc_a7ddrphy_bitslip1_value + 1'd1); + a7ddrphy_bitslip0_r <= {a7ddrphy_bitslip0_i, a7ddrphy_bitslip0_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value <= (a7ddrphy_bitslip1_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip1_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip1_value <= 1'd0; end - soc_a7ddrphy_bitslip1_r <= {soc_a7ddrphy_bitslip1_i, soc_a7ddrphy_bitslip1_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip2_value <= (soc_a7ddrphy_bitslip2_value + 1'd1); + a7ddrphy_bitslip1_r <= {a7ddrphy_bitslip1_i, a7ddrphy_bitslip1_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip2_value <= (a7ddrphy_bitslip2_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip2_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip2_value <= 1'd0; end - soc_a7ddrphy_bitslip2_r <= {soc_a7ddrphy_bitslip2_i, soc_a7ddrphy_bitslip2_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip3_value <= (soc_a7ddrphy_bitslip3_value + 1'd1); + a7ddrphy_bitslip2_r <= {a7ddrphy_bitslip2_i, a7ddrphy_bitslip2_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip3_value <= (a7ddrphy_bitslip3_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip3_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip3_value <= 1'd0; end - soc_a7ddrphy_bitslip3_r <= {soc_a7ddrphy_bitslip3_i, soc_a7ddrphy_bitslip3_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip4_value <= (soc_a7ddrphy_bitslip4_value + 1'd1); + a7ddrphy_bitslip3_r <= {a7ddrphy_bitslip3_i, a7ddrphy_bitslip3_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip4_value <= (a7ddrphy_bitslip4_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip4_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip4_value <= 1'd0; end - soc_a7ddrphy_bitslip4_r <= {soc_a7ddrphy_bitslip4_i, soc_a7ddrphy_bitslip4_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip5_value <= (soc_a7ddrphy_bitslip5_value + 1'd1); + a7ddrphy_bitslip4_r <= {a7ddrphy_bitslip4_i, a7ddrphy_bitslip4_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip5_value <= (a7ddrphy_bitslip5_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip5_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip5_value <= 1'd0; end - soc_a7ddrphy_bitslip5_r <= {soc_a7ddrphy_bitslip5_i, soc_a7ddrphy_bitslip5_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip6_value <= (soc_a7ddrphy_bitslip6_value + 1'd1); + a7ddrphy_bitslip5_r <= {a7ddrphy_bitslip5_i, a7ddrphy_bitslip5_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip6_value <= (a7ddrphy_bitslip6_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip6_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip6_value <= 1'd0; end - soc_a7ddrphy_bitslip6_r <= {soc_a7ddrphy_bitslip6_i, soc_a7ddrphy_bitslip6_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip7_value <= (soc_a7ddrphy_bitslip7_value + 1'd1); + a7ddrphy_bitslip6_r <= {a7ddrphy_bitslip6_i, a7ddrphy_bitslip6_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip7_value <= (a7ddrphy_bitslip7_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip7_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip7_value <= 1'd0; end - soc_a7ddrphy_bitslip7_r <= {soc_a7ddrphy_bitslip7_i, soc_a7ddrphy_bitslip7_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip8_value <= (soc_a7ddrphy_bitslip8_value + 1'd1); + a7ddrphy_bitslip7_r <= {a7ddrphy_bitslip7_i, a7ddrphy_bitslip7_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip8_value <= (a7ddrphy_bitslip8_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip8_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip8_value <= 1'd0; end - soc_a7ddrphy_bitslip8_r <= {soc_a7ddrphy_bitslip8_i, soc_a7ddrphy_bitslip8_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip9_value <= (soc_a7ddrphy_bitslip9_value + 1'd1); + a7ddrphy_bitslip8_r <= {a7ddrphy_bitslip8_i, a7ddrphy_bitslip8_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip9_value <= (a7ddrphy_bitslip9_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip9_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip9_value <= 1'd0; end - soc_a7ddrphy_bitslip9_r <= {soc_a7ddrphy_bitslip9_i, soc_a7ddrphy_bitslip9_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip10_value <= (soc_a7ddrphy_bitslip10_value + 1'd1); + a7ddrphy_bitslip9_r <= {a7ddrphy_bitslip9_i, a7ddrphy_bitslip9_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip10_value <= (a7ddrphy_bitslip10_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip10_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip10_value <= 1'd0; end - soc_a7ddrphy_bitslip10_r <= {soc_a7ddrphy_bitslip10_i, soc_a7ddrphy_bitslip10_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip11_value <= (soc_a7ddrphy_bitslip11_value + 1'd1); + a7ddrphy_bitslip10_r <= {a7ddrphy_bitslip10_i, a7ddrphy_bitslip10_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip11_value <= (a7ddrphy_bitslip11_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip11_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip11_value <= 1'd0; end - soc_a7ddrphy_bitslip11_r <= {soc_a7ddrphy_bitslip11_i, soc_a7ddrphy_bitslip11_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip12_value <= (soc_a7ddrphy_bitslip12_value + 1'd1); + a7ddrphy_bitslip11_r <= {a7ddrphy_bitslip11_i, a7ddrphy_bitslip11_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip12_value <= (a7ddrphy_bitslip12_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip12_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip12_value <= 1'd0; end - soc_a7ddrphy_bitslip12_r <= {soc_a7ddrphy_bitslip12_i, soc_a7ddrphy_bitslip12_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip13_value <= (soc_a7ddrphy_bitslip13_value + 1'd1); + a7ddrphy_bitslip12_r <= {a7ddrphy_bitslip12_i, a7ddrphy_bitslip12_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip13_value <= (a7ddrphy_bitslip13_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip13_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip13_value <= 1'd0; end - soc_a7ddrphy_bitslip13_r <= {soc_a7ddrphy_bitslip13_i, soc_a7ddrphy_bitslip13_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip14_value <= (soc_a7ddrphy_bitslip14_value + 1'd1); + a7ddrphy_bitslip13_r <= {a7ddrphy_bitslip13_i, a7ddrphy_bitslip13_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip14_value <= (a7ddrphy_bitslip14_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip14_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip14_value <= 1'd0; end - soc_a7ddrphy_bitslip14_r <= {soc_a7ddrphy_bitslip14_i, soc_a7ddrphy_bitslip14_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip15_value <= (soc_a7ddrphy_bitslip15_value + 1'd1); + a7ddrphy_bitslip14_r <= {a7ddrphy_bitslip14_i, a7ddrphy_bitslip14_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip15_value <= (a7ddrphy_bitslip15_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip15_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip15_value <= 1'd0; end - soc_a7ddrphy_bitslip15_r <= {soc_a7ddrphy_bitslip15_i, soc_a7ddrphy_bitslip15_r[15:8]}; - if (soc_sdram_inti_p0_rddata_valid) begin - soc_sdram_phaseinjector0_status <= soc_sdram_inti_p0_rddata; + a7ddrphy_bitslip15_r <= {a7ddrphy_bitslip15_i, a7ddrphy_bitslip15_r[15:8]}; + if (litedramcore_inti_p0_rddata_valid) begin + litedramcore_phaseinjector0_status <= litedramcore_inti_p0_rddata; end - if (soc_sdram_inti_p1_rddata_valid) begin - soc_sdram_phaseinjector1_status <= soc_sdram_inti_p1_rddata; + if (litedramcore_inti_p1_rddata_valid) begin + litedramcore_phaseinjector1_status <= litedramcore_inti_p1_rddata; end - if (soc_sdram_inti_p2_rddata_valid) begin - soc_sdram_phaseinjector2_status <= soc_sdram_inti_p2_rddata; + if (litedramcore_inti_p2_rddata_valid) begin + litedramcore_phaseinjector2_status <= litedramcore_inti_p2_rddata; end - if (soc_sdram_inti_p3_rddata_valid) begin - soc_sdram_phaseinjector3_status <= soc_sdram_inti_p3_rddata; + if (litedramcore_inti_p3_rddata_valid) begin + litedramcore_phaseinjector3_status <= litedramcore_inti_p3_rddata; end - if ((soc_sdram_timer_wait & (~soc_sdram_timer_done0))) begin - soc_sdram_timer_count1 <= (soc_sdram_timer_count1 - 1'd1); + if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin + litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); end else begin - soc_sdram_timer_count1 <= 10'd781; + litedramcore_timer_count1 <= 10'd781; end - soc_sdram_postponer_req_o <= 1'd0; - if (soc_sdram_postponer_req_i) begin - soc_sdram_postponer_count <= (soc_sdram_postponer_count - 1'd1); - if ((soc_sdram_postponer_count == 1'd0)) begin - soc_sdram_postponer_count <= 1'd0; - soc_sdram_postponer_req_o <= 1'd1; + litedramcore_postponer_req_o <= 1'd0; + if (litedramcore_postponer_req_i) begin + litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); + if ((litedramcore_postponer_count == 1'd0)) begin + litedramcore_postponer_count <= 1'd0; + litedramcore_postponer_req_o <= 1'd1; end end - if (soc_sdram_sequencer_start0) begin - soc_sdram_sequencer_count <= 1'd0; + if (litedramcore_sequencer_start0) begin + litedramcore_sequencer_count <= 1'd0; end else begin - if (soc_sdram_sequencer_done1) begin - if ((soc_sdram_sequencer_count != 1'd0)) begin - soc_sdram_sequencer_count <= (soc_sdram_sequencer_count - 1'd1); - end - end - end - soc_sdram_cmd_payload_a <= 1'd0; - soc_sdram_cmd_payload_ba <= 1'd0; - soc_sdram_cmd_payload_cas <= 1'd0; - soc_sdram_cmd_payload_ras <= 1'd0; - soc_sdram_cmd_payload_we <= 1'd0; - soc_sdram_sequencer_done1 <= 1'd0; - if ((soc_sdram_sequencer_start1 & (soc_sdram_sequencer_counter == 1'd0))) begin - soc_sdram_cmd_payload_a <= 11'd1024; - soc_sdram_cmd_payload_ba <= 1'd0; - soc_sdram_cmd_payload_cas <= 1'd0; - soc_sdram_cmd_payload_ras <= 1'd1; - soc_sdram_cmd_payload_we <= 1'd1; - end - if ((soc_sdram_sequencer_counter == 2'd3)) begin - soc_sdram_cmd_payload_a <= 1'd0; - soc_sdram_cmd_payload_ba <= 1'd0; - soc_sdram_cmd_payload_cas <= 1'd1; - soc_sdram_cmd_payload_ras <= 1'd1; - soc_sdram_cmd_payload_we <= 1'd0; - end - if ((soc_sdram_sequencer_counter == 6'd35)) begin - soc_sdram_cmd_payload_a <= 1'd0; - soc_sdram_cmd_payload_ba <= 1'd0; - soc_sdram_cmd_payload_cas <= 1'd0; - soc_sdram_cmd_payload_ras <= 1'd0; - soc_sdram_cmd_payload_we <= 1'd0; - soc_sdram_sequencer_done1 <= 1'd1; - end - if ((soc_sdram_sequencer_counter == 6'd35)) begin - soc_sdram_sequencer_counter <= 1'd0; + if (litedramcore_sequencer_done1) begin + if ((litedramcore_sequencer_count != 1'd0)) begin + litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); + end + end + end + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_sequencer_counter == 2'd3)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd1; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd0; + end + if ((litedramcore_sequencer_counter == 6'd35)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd1; + end + if ((litedramcore_sequencer_counter == 6'd35)) begin + litedramcore_sequencer_counter <= 1'd0; end else begin - if ((soc_sdram_sequencer_counter != 1'd0)) begin - soc_sdram_sequencer_counter <= (soc_sdram_sequencer_counter + 1'd1); + if ((litedramcore_sequencer_counter != 1'd0)) begin + litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); end else begin - if (soc_sdram_sequencer_start1) begin - soc_sdram_sequencer_counter <= 1'd1; + if (litedramcore_sequencer_start1) begin + litedramcore_sequencer_counter <= 1'd1; end end end - if ((soc_sdram_zqcs_timer_wait & (~soc_sdram_zqcs_timer_done0))) begin - soc_sdram_zqcs_timer_count1 <= (soc_sdram_zqcs_timer_count1 - 1'd1); + if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin + litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); end else begin - soc_sdram_zqcs_timer_count1 <= 27'd99999999; - end - soc_sdram_zqcs_executer_done <= 1'd0; - if ((soc_sdram_zqcs_executer_start & (soc_sdram_zqcs_executer_counter == 1'd0))) begin - soc_sdram_cmd_payload_a <= 11'd1024; - soc_sdram_cmd_payload_ba <= 1'd0; - soc_sdram_cmd_payload_cas <= 1'd0; - soc_sdram_cmd_payload_ras <= 1'd1; - soc_sdram_cmd_payload_we <= 1'd1; - end - if ((soc_sdram_zqcs_executer_counter == 2'd3)) begin - soc_sdram_cmd_payload_a <= 1'd0; - soc_sdram_cmd_payload_ba <= 1'd0; - soc_sdram_cmd_payload_cas <= 1'd0; - soc_sdram_cmd_payload_ras <= 1'd0; - soc_sdram_cmd_payload_we <= 1'd1; - end - if ((soc_sdram_zqcs_executer_counter == 5'd19)) begin - soc_sdram_cmd_payload_a <= 1'd0; - soc_sdram_cmd_payload_ba <= 1'd0; - soc_sdram_cmd_payload_cas <= 1'd0; - soc_sdram_cmd_payload_ras <= 1'd0; - soc_sdram_cmd_payload_we <= 1'd0; - soc_sdram_zqcs_executer_done <= 1'd1; - end - if ((soc_sdram_zqcs_executer_counter == 5'd19)) begin - soc_sdram_zqcs_executer_counter <= 1'd0; + litedramcore_zqcs_timer_count1 <= 27'd99999999; + end + litedramcore_zqcs_executer_done <= 1'd0; + if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 2'd3)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 5'd19)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_zqcs_executer_done <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 5'd19)) begin + litedramcore_zqcs_executer_counter <= 1'd0; end else begin - if ((soc_sdram_zqcs_executer_counter != 1'd0)) begin - soc_sdram_zqcs_executer_counter <= (soc_sdram_zqcs_executer_counter + 1'd1); + if ((litedramcore_zqcs_executer_counter != 1'd0)) begin + litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); end else begin - if (soc_sdram_zqcs_executer_start) begin - soc_sdram_zqcs_executer_counter <= 1'd1; + if (litedramcore_zqcs_executer_start) begin + litedramcore_zqcs_executer_counter <= 1'd1; end end end - vns_refresher_state <= vns_refresher_next_state; - if (soc_sdram_bankmachine0_row_close) begin - soc_sdram_bankmachine0_row_opened <= 1'd0; + refresher_state <= refresher_next_state; + if (litedramcore_bankmachine0_row_close) begin + litedramcore_bankmachine0_row_opened <= 1'd0; end else begin - if (soc_sdram_bankmachine0_row_open) begin - soc_sdram_bankmachine0_row_opened <= 1'd1; - soc_sdram_bankmachine0_row <= soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]; + if (litedramcore_bankmachine0_row_open) begin + litedramcore_bankmachine0_row_opened <= 1'd1; + litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]; end end - if (((soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin - soc_sdram_bankmachine0_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); + if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine0_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); + if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin - if ((~soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin - soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1); + if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1); + if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_sdram_bankmachine0_cmd_buffer_source_valid) | soc_sdram_bankmachine0_cmd_buffer_source_ready)) begin - soc_sdram_bankmachine0_cmd_buffer_source_valid <= soc_sdram_bankmachine0_cmd_buffer_sink_valid; - soc_sdram_bankmachine0_cmd_buffer_source_first <= soc_sdram_bankmachine0_cmd_buffer_sink_first; - soc_sdram_bankmachine0_cmd_buffer_source_last <= soc_sdram_bankmachine0_cmd_buffer_sink_last; - soc_sdram_bankmachine0_cmd_buffer_source_payload_we <= soc_sdram_bankmachine0_cmd_buffer_sink_payload_we; - soc_sdram_bankmachine0_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr; + if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin + litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid; + litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first; + litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last; + litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we; + litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; end - if (soc_sdram_bankmachine0_twtpcon_valid) begin - soc_sdram_bankmachine0_twtpcon_count <= 3'd5; + if (litedramcore_bankmachine0_twtpcon_valid) begin + litedramcore_bankmachine0_twtpcon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine0_twtpcon_ready <= 1'd1; + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end else begin - soc_sdram_bankmachine0_twtpcon_ready <= 1'd0; + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine0_twtpcon_ready)) begin - soc_sdram_bankmachine0_twtpcon_count <= (soc_sdram_bankmachine0_twtpcon_count - 1'd1); - if ((soc_sdram_bankmachine0_twtpcon_count == 1'd1)) begin - soc_sdram_bankmachine0_twtpcon_ready <= 1'd1; + if ((~litedramcore_bankmachine0_twtpcon_ready)) begin + litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine0_trccon_valid) begin - soc_sdram_bankmachine0_trccon_count <= 3'd5; + if (litedramcore_bankmachine0_trccon_valid) begin + litedramcore_bankmachine0_trccon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine0_trccon_ready <= 1'd1; + litedramcore_bankmachine0_trccon_ready <= 1'd1; end else begin - soc_sdram_bankmachine0_trccon_ready <= 1'd0; + litedramcore_bankmachine0_trccon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine0_trccon_ready)) begin - soc_sdram_bankmachine0_trccon_count <= (soc_sdram_bankmachine0_trccon_count - 1'd1); - if ((soc_sdram_bankmachine0_trccon_count == 1'd1)) begin - soc_sdram_bankmachine0_trccon_ready <= 1'd1; + if ((~litedramcore_bankmachine0_trccon_ready)) begin + litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); + if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine0_trascon_valid) begin - soc_sdram_bankmachine0_trascon_count <= 3'd4; + if (litedramcore_bankmachine0_trascon_valid) begin + litedramcore_bankmachine0_trascon_count <= 3'd4; if (1'd0) begin - soc_sdram_bankmachine0_trascon_ready <= 1'd1; + litedramcore_bankmachine0_trascon_ready <= 1'd1; end else begin - soc_sdram_bankmachine0_trascon_ready <= 1'd0; + litedramcore_bankmachine0_trascon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine0_trascon_ready)) begin - soc_sdram_bankmachine0_trascon_count <= (soc_sdram_bankmachine0_trascon_count - 1'd1); - if ((soc_sdram_bankmachine0_trascon_count == 1'd1)) begin - soc_sdram_bankmachine0_trascon_ready <= 1'd1; + if ((~litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); + if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; end end end - vns_bankmachine0_state <= vns_bankmachine0_next_state; - if (soc_sdram_bankmachine1_row_close) begin - soc_sdram_bankmachine1_row_opened <= 1'd0; + bankmachine0_state <= bankmachine0_next_state; + if (litedramcore_bankmachine1_row_close) begin + litedramcore_bankmachine1_row_opened <= 1'd0; end else begin - if (soc_sdram_bankmachine1_row_open) begin - soc_sdram_bankmachine1_row_opened <= 1'd1; - soc_sdram_bankmachine1_row <= soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]; + if (litedramcore_bankmachine1_row_open) begin + litedramcore_bankmachine1_row_opened <= 1'd1; + litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]; end end - if (((soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin - soc_sdram_bankmachine1_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); + if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine1_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); + if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin - if ((~soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin - soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1); + if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1); + if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_sdram_bankmachine1_cmd_buffer_source_valid) | soc_sdram_bankmachine1_cmd_buffer_source_ready)) begin - soc_sdram_bankmachine1_cmd_buffer_source_valid <= soc_sdram_bankmachine1_cmd_buffer_sink_valid; - soc_sdram_bankmachine1_cmd_buffer_source_first <= soc_sdram_bankmachine1_cmd_buffer_sink_first; - soc_sdram_bankmachine1_cmd_buffer_source_last <= soc_sdram_bankmachine1_cmd_buffer_sink_last; - soc_sdram_bankmachine1_cmd_buffer_source_payload_we <= soc_sdram_bankmachine1_cmd_buffer_sink_payload_we; - soc_sdram_bankmachine1_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr; + if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin + litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid; + litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first; + litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last; + litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we; + litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; end - if (soc_sdram_bankmachine1_twtpcon_valid) begin - soc_sdram_bankmachine1_twtpcon_count <= 3'd5; + if (litedramcore_bankmachine1_twtpcon_valid) begin + litedramcore_bankmachine1_twtpcon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine1_twtpcon_ready <= 1'd1; + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end else begin - soc_sdram_bankmachine1_twtpcon_ready <= 1'd0; + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine1_twtpcon_ready)) begin - soc_sdram_bankmachine1_twtpcon_count <= (soc_sdram_bankmachine1_twtpcon_count - 1'd1); - if ((soc_sdram_bankmachine1_twtpcon_count == 1'd1)) begin - soc_sdram_bankmachine1_twtpcon_ready <= 1'd1; + if ((~litedramcore_bankmachine1_twtpcon_ready)) begin + litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine1_trccon_valid) begin - soc_sdram_bankmachine1_trccon_count <= 3'd5; + if (litedramcore_bankmachine1_trccon_valid) begin + litedramcore_bankmachine1_trccon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine1_trccon_ready <= 1'd1; + litedramcore_bankmachine1_trccon_ready <= 1'd1; end else begin - soc_sdram_bankmachine1_trccon_ready <= 1'd0; + litedramcore_bankmachine1_trccon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine1_trccon_ready)) begin - soc_sdram_bankmachine1_trccon_count <= (soc_sdram_bankmachine1_trccon_count - 1'd1); - if ((soc_sdram_bankmachine1_trccon_count == 1'd1)) begin - soc_sdram_bankmachine1_trccon_ready <= 1'd1; + if ((~litedramcore_bankmachine1_trccon_ready)) begin + litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); + if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine1_trascon_valid) begin - soc_sdram_bankmachine1_trascon_count <= 3'd4; + if (litedramcore_bankmachine1_trascon_valid) begin + litedramcore_bankmachine1_trascon_count <= 3'd4; if (1'd0) begin - soc_sdram_bankmachine1_trascon_ready <= 1'd1; + litedramcore_bankmachine1_trascon_ready <= 1'd1; end else begin - soc_sdram_bankmachine1_trascon_ready <= 1'd0; + litedramcore_bankmachine1_trascon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine1_trascon_ready)) begin - soc_sdram_bankmachine1_trascon_count <= (soc_sdram_bankmachine1_trascon_count - 1'd1); - if ((soc_sdram_bankmachine1_trascon_count == 1'd1)) begin - soc_sdram_bankmachine1_trascon_ready <= 1'd1; + if ((~litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); + if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; end end end - vns_bankmachine1_state <= vns_bankmachine1_next_state; - if (soc_sdram_bankmachine2_row_close) begin - soc_sdram_bankmachine2_row_opened <= 1'd0; + bankmachine1_state <= bankmachine1_next_state; + if (litedramcore_bankmachine2_row_close) begin + litedramcore_bankmachine2_row_opened <= 1'd0; end else begin - if (soc_sdram_bankmachine2_row_open) begin - soc_sdram_bankmachine2_row_opened <= 1'd1; - soc_sdram_bankmachine2_row <= soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]; + if (litedramcore_bankmachine2_row_open) begin + litedramcore_bankmachine2_row_opened <= 1'd1; + litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]; end end - if (((soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin - soc_sdram_bankmachine2_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); + if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine2_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); + if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin - if ((~soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin - soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1); + if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1); + if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_sdram_bankmachine2_cmd_buffer_source_valid) | soc_sdram_bankmachine2_cmd_buffer_source_ready)) begin - soc_sdram_bankmachine2_cmd_buffer_source_valid <= soc_sdram_bankmachine2_cmd_buffer_sink_valid; - soc_sdram_bankmachine2_cmd_buffer_source_first <= soc_sdram_bankmachine2_cmd_buffer_sink_first; - soc_sdram_bankmachine2_cmd_buffer_source_last <= soc_sdram_bankmachine2_cmd_buffer_sink_last; - soc_sdram_bankmachine2_cmd_buffer_source_payload_we <= soc_sdram_bankmachine2_cmd_buffer_sink_payload_we; - soc_sdram_bankmachine2_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr; + if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin + litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid; + litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first; + litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last; + litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we; + litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; end - if (soc_sdram_bankmachine2_twtpcon_valid) begin - soc_sdram_bankmachine2_twtpcon_count <= 3'd5; + if (litedramcore_bankmachine2_twtpcon_valid) begin + litedramcore_bankmachine2_twtpcon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine2_twtpcon_ready <= 1'd1; + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end else begin - soc_sdram_bankmachine2_twtpcon_ready <= 1'd0; + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine2_twtpcon_ready)) begin - soc_sdram_bankmachine2_twtpcon_count <= (soc_sdram_bankmachine2_twtpcon_count - 1'd1); - if ((soc_sdram_bankmachine2_twtpcon_count == 1'd1)) begin - soc_sdram_bankmachine2_twtpcon_ready <= 1'd1; + if ((~litedramcore_bankmachine2_twtpcon_ready)) begin + litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine2_trccon_valid) begin - soc_sdram_bankmachine2_trccon_count <= 3'd5; + if (litedramcore_bankmachine2_trccon_valid) begin + litedramcore_bankmachine2_trccon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine2_trccon_ready <= 1'd1; + litedramcore_bankmachine2_trccon_ready <= 1'd1; end else begin - soc_sdram_bankmachine2_trccon_ready <= 1'd0; + litedramcore_bankmachine2_trccon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine2_trccon_ready)) begin - soc_sdram_bankmachine2_trccon_count <= (soc_sdram_bankmachine2_trccon_count - 1'd1); - if ((soc_sdram_bankmachine2_trccon_count == 1'd1)) begin - soc_sdram_bankmachine2_trccon_ready <= 1'd1; + if ((~litedramcore_bankmachine2_trccon_ready)) begin + litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); + if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine2_trascon_valid) begin - soc_sdram_bankmachine2_trascon_count <= 3'd4; + if (litedramcore_bankmachine2_trascon_valid) begin + litedramcore_bankmachine2_trascon_count <= 3'd4; if (1'd0) begin - soc_sdram_bankmachine2_trascon_ready <= 1'd1; + litedramcore_bankmachine2_trascon_ready <= 1'd1; end else begin - soc_sdram_bankmachine2_trascon_ready <= 1'd0; + litedramcore_bankmachine2_trascon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine2_trascon_ready)) begin - soc_sdram_bankmachine2_trascon_count <= (soc_sdram_bankmachine2_trascon_count - 1'd1); - if ((soc_sdram_bankmachine2_trascon_count == 1'd1)) begin - soc_sdram_bankmachine2_trascon_ready <= 1'd1; + if ((~litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); + if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; end end end - vns_bankmachine2_state <= vns_bankmachine2_next_state; - if (soc_sdram_bankmachine3_row_close) begin - soc_sdram_bankmachine3_row_opened <= 1'd0; + bankmachine2_state <= bankmachine2_next_state; + if (litedramcore_bankmachine3_row_close) begin + litedramcore_bankmachine3_row_opened <= 1'd0; end else begin - if (soc_sdram_bankmachine3_row_open) begin - soc_sdram_bankmachine3_row_opened <= 1'd1; - soc_sdram_bankmachine3_row <= soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]; + if (litedramcore_bankmachine3_row_open) begin + litedramcore_bankmachine3_row_opened <= 1'd1; + litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]; end end - if (((soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin - soc_sdram_bankmachine3_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); + if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine3_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); + if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin - if ((~soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin - soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1); + if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1); + if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_sdram_bankmachine3_cmd_buffer_source_valid) | soc_sdram_bankmachine3_cmd_buffer_source_ready)) begin - soc_sdram_bankmachine3_cmd_buffer_source_valid <= soc_sdram_bankmachine3_cmd_buffer_sink_valid; - soc_sdram_bankmachine3_cmd_buffer_source_first <= soc_sdram_bankmachine3_cmd_buffer_sink_first; - soc_sdram_bankmachine3_cmd_buffer_source_last <= soc_sdram_bankmachine3_cmd_buffer_sink_last; - soc_sdram_bankmachine3_cmd_buffer_source_payload_we <= soc_sdram_bankmachine3_cmd_buffer_sink_payload_we; - soc_sdram_bankmachine3_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr; + if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin + litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid; + litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first; + litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last; + litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we; + litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; end - if (soc_sdram_bankmachine3_twtpcon_valid) begin - soc_sdram_bankmachine3_twtpcon_count <= 3'd5; + if (litedramcore_bankmachine3_twtpcon_valid) begin + litedramcore_bankmachine3_twtpcon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine3_twtpcon_ready <= 1'd1; + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end else begin - soc_sdram_bankmachine3_twtpcon_ready <= 1'd0; + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine3_twtpcon_ready)) begin - soc_sdram_bankmachine3_twtpcon_count <= (soc_sdram_bankmachine3_twtpcon_count - 1'd1); - if ((soc_sdram_bankmachine3_twtpcon_count == 1'd1)) begin - soc_sdram_bankmachine3_twtpcon_ready <= 1'd1; + if ((~litedramcore_bankmachine3_twtpcon_ready)) begin + litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine3_trccon_valid) begin - soc_sdram_bankmachine3_trccon_count <= 3'd5; + if (litedramcore_bankmachine3_trccon_valid) begin + litedramcore_bankmachine3_trccon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine3_trccon_ready <= 1'd1; + litedramcore_bankmachine3_trccon_ready <= 1'd1; end else begin - soc_sdram_bankmachine3_trccon_ready <= 1'd0; + litedramcore_bankmachine3_trccon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine3_trccon_ready)) begin - soc_sdram_bankmachine3_trccon_count <= (soc_sdram_bankmachine3_trccon_count - 1'd1); - if ((soc_sdram_bankmachine3_trccon_count == 1'd1)) begin - soc_sdram_bankmachine3_trccon_ready <= 1'd1; + if ((~litedramcore_bankmachine3_trccon_ready)) begin + litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); + if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine3_trascon_valid) begin - soc_sdram_bankmachine3_trascon_count <= 3'd4; + if (litedramcore_bankmachine3_trascon_valid) begin + litedramcore_bankmachine3_trascon_count <= 3'd4; if (1'd0) begin - soc_sdram_bankmachine3_trascon_ready <= 1'd1; + litedramcore_bankmachine3_trascon_ready <= 1'd1; end else begin - soc_sdram_bankmachine3_trascon_ready <= 1'd0; + litedramcore_bankmachine3_trascon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine3_trascon_ready)) begin - soc_sdram_bankmachine3_trascon_count <= (soc_sdram_bankmachine3_trascon_count - 1'd1); - if ((soc_sdram_bankmachine3_trascon_count == 1'd1)) begin - soc_sdram_bankmachine3_trascon_ready <= 1'd1; + if ((~litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); + if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; end end end - vns_bankmachine3_state <= vns_bankmachine3_next_state; - if (soc_sdram_bankmachine4_row_close) begin - soc_sdram_bankmachine4_row_opened <= 1'd0; + bankmachine3_state <= bankmachine3_next_state; + if (litedramcore_bankmachine4_row_close) begin + litedramcore_bankmachine4_row_opened <= 1'd0; end else begin - if (soc_sdram_bankmachine4_row_open) begin - soc_sdram_bankmachine4_row_opened <= 1'd1; - soc_sdram_bankmachine4_row <= soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]; + if (litedramcore_bankmachine4_row_open) begin + litedramcore_bankmachine4_row_opened <= 1'd1; + litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]; end end - if (((soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin - soc_sdram_bankmachine4_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); + if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine4_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); + if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin - if ((~soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read)) begin - soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_level + 1'd1); + if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_level - 1'd1); + if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_sdram_bankmachine4_cmd_buffer_source_valid) | soc_sdram_bankmachine4_cmd_buffer_source_ready)) begin - soc_sdram_bankmachine4_cmd_buffer_source_valid <= soc_sdram_bankmachine4_cmd_buffer_sink_valid; - soc_sdram_bankmachine4_cmd_buffer_source_first <= soc_sdram_bankmachine4_cmd_buffer_sink_first; - soc_sdram_bankmachine4_cmd_buffer_source_last <= soc_sdram_bankmachine4_cmd_buffer_sink_last; - soc_sdram_bankmachine4_cmd_buffer_source_payload_we <= soc_sdram_bankmachine4_cmd_buffer_sink_payload_we; - soc_sdram_bankmachine4_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr; + if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin + litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid; + litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first; + litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last; + litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we; + litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; end - if (soc_sdram_bankmachine4_twtpcon_valid) begin - soc_sdram_bankmachine4_twtpcon_count <= 3'd5; + if (litedramcore_bankmachine4_twtpcon_valid) begin + litedramcore_bankmachine4_twtpcon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine4_twtpcon_ready <= 1'd1; + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end else begin - soc_sdram_bankmachine4_twtpcon_ready <= 1'd0; + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine4_twtpcon_ready)) begin - soc_sdram_bankmachine4_twtpcon_count <= (soc_sdram_bankmachine4_twtpcon_count - 1'd1); - if ((soc_sdram_bankmachine4_twtpcon_count == 1'd1)) begin - soc_sdram_bankmachine4_twtpcon_ready <= 1'd1; + if ((~litedramcore_bankmachine4_twtpcon_ready)) begin + litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine4_trccon_valid) begin - soc_sdram_bankmachine4_trccon_count <= 3'd5; + if (litedramcore_bankmachine4_trccon_valid) begin + litedramcore_bankmachine4_trccon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine4_trccon_ready <= 1'd1; + litedramcore_bankmachine4_trccon_ready <= 1'd1; end else begin - soc_sdram_bankmachine4_trccon_ready <= 1'd0; + litedramcore_bankmachine4_trccon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine4_trccon_ready)) begin - soc_sdram_bankmachine4_trccon_count <= (soc_sdram_bankmachine4_trccon_count - 1'd1); - if ((soc_sdram_bankmachine4_trccon_count == 1'd1)) begin - soc_sdram_bankmachine4_trccon_ready <= 1'd1; + if ((~litedramcore_bankmachine4_trccon_ready)) begin + litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); + if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine4_trascon_valid) begin - soc_sdram_bankmachine4_trascon_count <= 3'd4; + if (litedramcore_bankmachine4_trascon_valid) begin + litedramcore_bankmachine4_trascon_count <= 3'd4; if (1'd0) begin - soc_sdram_bankmachine4_trascon_ready <= 1'd1; + litedramcore_bankmachine4_trascon_ready <= 1'd1; end else begin - soc_sdram_bankmachine4_trascon_ready <= 1'd0; + litedramcore_bankmachine4_trascon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine4_trascon_ready)) begin - soc_sdram_bankmachine4_trascon_count <= (soc_sdram_bankmachine4_trascon_count - 1'd1); - if ((soc_sdram_bankmachine4_trascon_count == 1'd1)) begin - soc_sdram_bankmachine4_trascon_ready <= 1'd1; + if ((~litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); + if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; end end end - vns_bankmachine4_state <= vns_bankmachine4_next_state; - if (soc_sdram_bankmachine5_row_close) begin - soc_sdram_bankmachine5_row_opened <= 1'd0; + bankmachine4_state <= bankmachine4_next_state; + if (litedramcore_bankmachine5_row_close) begin + litedramcore_bankmachine5_row_opened <= 1'd0; end else begin - if (soc_sdram_bankmachine5_row_open) begin - soc_sdram_bankmachine5_row_opened <= 1'd1; - soc_sdram_bankmachine5_row <= soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]; + if (litedramcore_bankmachine5_row_open) begin + litedramcore_bankmachine5_row_opened <= 1'd1; + litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]; end end - if (((soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin - soc_sdram_bankmachine5_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); + if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine5_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); + if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin - if ((~soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read)) begin - soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_level + 1'd1); + if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_level - 1'd1); + if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_sdram_bankmachine5_cmd_buffer_source_valid) | soc_sdram_bankmachine5_cmd_buffer_source_ready)) begin - soc_sdram_bankmachine5_cmd_buffer_source_valid <= soc_sdram_bankmachine5_cmd_buffer_sink_valid; - soc_sdram_bankmachine5_cmd_buffer_source_first <= soc_sdram_bankmachine5_cmd_buffer_sink_first; - soc_sdram_bankmachine5_cmd_buffer_source_last <= soc_sdram_bankmachine5_cmd_buffer_sink_last; - soc_sdram_bankmachine5_cmd_buffer_source_payload_we <= soc_sdram_bankmachine5_cmd_buffer_sink_payload_we; - soc_sdram_bankmachine5_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr; + if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin + litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid; + litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first; + litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last; + litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we; + litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; end - if (soc_sdram_bankmachine5_twtpcon_valid) begin - soc_sdram_bankmachine5_twtpcon_count <= 3'd5; + if (litedramcore_bankmachine5_twtpcon_valid) begin + litedramcore_bankmachine5_twtpcon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine5_twtpcon_ready <= 1'd1; + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end else begin - soc_sdram_bankmachine5_twtpcon_ready <= 1'd0; + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine5_twtpcon_ready)) begin - soc_sdram_bankmachine5_twtpcon_count <= (soc_sdram_bankmachine5_twtpcon_count - 1'd1); - if ((soc_sdram_bankmachine5_twtpcon_count == 1'd1)) begin - soc_sdram_bankmachine5_twtpcon_ready <= 1'd1; + if ((~litedramcore_bankmachine5_twtpcon_ready)) begin + litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine5_trccon_valid) begin - soc_sdram_bankmachine5_trccon_count <= 3'd5; + if (litedramcore_bankmachine5_trccon_valid) begin + litedramcore_bankmachine5_trccon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine5_trccon_ready <= 1'd1; + litedramcore_bankmachine5_trccon_ready <= 1'd1; end else begin - soc_sdram_bankmachine5_trccon_ready <= 1'd0; + litedramcore_bankmachine5_trccon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine5_trccon_ready)) begin - soc_sdram_bankmachine5_trccon_count <= (soc_sdram_bankmachine5_trccon_count - 1'd1); - if ((soc_sdram_bankmachine5_trccon_count == 1'd1)) begin - soc_sdram_bankmachine5_trccon_ready <= 1'd1; + if ((~litedramcore_bankmachine5_trccon_ready)) begin + litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); + if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine5_trascon_valid) begin - soc_sdram_bankmachine5_trascon_count <= 3'd4; + if (litedramcore_bankmachine5_trascon_valid) begin + litedramcore_bankmachine5_trascon_count <= 3'd4; if (1'd0) begin - soc_sdram_bankmachine5_trascon_ready <= 1'd1; + litedramcore_bankmachine5_trascon_ready <= 1'd1; end else begin - soc_sdram_bankmachine5_trascon_ready <= 1'd0; + litedramcore_bankmachine5_trascon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine5_trascon_ready)) begin - soc_sdram_bankmachine5_trascon_count <= (soc_sdram_bankmachine5_trascon_count - 1'd1); - if ((soc_sdram_bankmachine5_trascon_count == 1'd1)) begin - soc_sdram_bankmachine5_trascon_ready <= 1'd1; + if ((~litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); + if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; end end end - vns_bankmachine5_state <= vns_bankmachine5_next_state; - if (soc_sdram_bankmachine6_row_close) begin - soc_sdram_bankmachine6_row_opened <= 1'd0; + bankmachine5_state <= bankmachine5_next_state; + if (litedramcore_bankmachine6_row_close) begin + litedramcore_bankmachine6_row_opened <= 1'd0; end else begin - if (soc_sdram_bankmachine6_row_open) begin - soc_sdram_bankmachine6_row_opened <= 1'd1; - soc_sdram_bankmachine6_row <= soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]; + if (litedramcore_bankmachine6_row_open) begin + litedramcore_bankmachine6_row_opened <= 1'd1; + litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]; end end - if (((soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin - soc_sdram_bankmachine6_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); + if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine6_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); + if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin - if ((~soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read)) begin - soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_level + 1'd1); + if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_level - 1'd1); + if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_sdram_bankmachine6_cmd_buffer_source_valid) | soc_sdram_bankmachine6_cmd_buffer_source_ready)) begin - soc_sdram_bankmachine6_cmd_buffer_source_valid <= soc_sdram_bankmachine6_cmd_buffer_sink_valid; - soc_sdram_bankmachine6_cmd_buffer_source_first <= soc_sdram_bankmachine6_cmd_buffer_sink_first; - soc_sdram_bankmachine6_cmd_buffer_source_last <= soc_sdram_bankmachine6_cmd_buffer_sink_last; - soc_sdram_bankmachine6_cmd_buffer_source_payload_we <= soc_sdram_bankmachine6_cmd_buffer_sink_payload_we; - soc_sdram_bankmachine6_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr; + if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin + litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid; + litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first; + litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last; + litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we; + litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; end - if (soc_sdram_bankmachine6_twtpcon_valid) begin - soc_sdram_bankmachine6_twtpcon_count <= 3'd5; + if (litedramcore_bankmachine6_twtpcon_valid) begin + litedramcore_bankmachine6_twtpcon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine6_twtpcon_ready <= 1'd1; + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end else begin - soc_sdram_bankmachine6_twtpcon_ready <= 1'd0; + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine6_twtpcon_ready)) begin - soc_sdram_bankmachine6_twtpcon_count <= (soc_sdram_bankmachine6_twtpcon_count - 1'd1); - if ((soc_sdram_bankmachine6_twtpcon_count == 1'd1)) begin - soc_sdram_bankmachine6_twtpcon_ready <= 1'd1; + if ((~litedramcore_bankmachine6_twtpcon_ready)) begin + litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine6_trccon_valid) begin - soc_sdram_bankmachine6_trccon_count <= 3'd5; + if (litedramcore_bankmachine6_trccon_valid) begin + litedramcore_bankmachine6_trccon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine6_trccon_ready <= 1'd1; + litedramcore_bankmachine6_trccon_ready <= 1'd1; end else begin - soc_sdram_bankmachine6_trccon_ready <= 1'd0; + litedramcore_bankmachine6_trccon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine6_trccon_ready)) begin - soc_sdram_bankmachine6_trccon_count <= (soc_sdram_bankmachine6_trccon_count - 1'd1); - if ((soc_sdram_bankmachine6_trccon_count == 1'd1)) begin - soc_sdram_bankmachine6_trccon_ready <= 1'd1; + if ((~litedramcore_bankmachine6_trccon_ready)) begin + litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); + if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine6_trascon_valid) begin - soc_sdram_bankmachine6_trascon_count <= 3'd4; + if (litedramcore_bankmachine6_trascon_valid) begin + litedramcore_bankmachine6_trascon_count <= 3'd4; if (1'd0) begin - soc_sdram_bankmachine6_trascon_ready <= 1'd1; + litedramcore_bankmachine6_trascon_ready <= 1'd1; end else begin - soc_sdram_bankmachine6_trascon_ready <= 1'd0; + litedramcore_bankmachine6_trascon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine6_trascon_ready)) begin - soc_sdram_bankmachine6_trascon_count <= (soc_sdram_bankmachine6_trascon_count - 1'd1); - if ((soc_sdram_bankmachine6_trascon_count == 1'd1)) begin - soc_sdram_bankmachine6_trascon_ready <= 1'd1; + if ((~litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); + if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; end end end - vns_bankmachine6_state <= vns_bankmachine6_next_state; - if (soc_sdram_bankmachine7_row_close) begin - soc_sdram_bankmachine7_row_opened <= 1'd0; + bankmachine6_state <= bankmachine6_next_state; + if (litedramcore_bankmachine7_row_close) begin + litedramcore_bankmachine7_row_opened <= 1'd0; end else begin - if (soc_sdram_bankmachine7_row_open) begin - soc_sdram_bankmachine7_row_opened <= 1'd1; - soc_sdram_bankmachine7_row <= soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]; + if (litedramcore_bankmachine7_row_open) begin + litedramcore_bankmachine7_row_opened <= 1'd1; + litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]; end end - if (((soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin - soc_sdram_bankmachine7_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); + if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine7_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); + if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin - if ((~soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read)) begin - soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_level + 1'd1); + if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_level - 1'd1); + if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_sdram_bankmachine7_cmd_buffer_source_valid) | soc_sdram_bankmachine7_cmd_buffer_source_ready)) begin - soc_sdram_bankmachine7_cmd_buffer_source_valid <= soc_sdram_bankmachine7_cmd_buffer_sink_valid; - soc_sdram_bankmachine7_cmd_buffer_source_first <= soc_sdram_bankmachine7_cmd_buffer_sink_first; - soc_sdram_bankmachine7_cmd_buffer_source_last <= soc_sdram_bankmachine7_cmd_buffer_sink_last; - soc_sdram_bankmachine7_cmd_buffer_source_payload_we <= soc_sdram_bankmachine7_cmd_buffer_sink_payload_we; - soc_sdram_bankmachine7_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr; + if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin + litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid; + litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first; + litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last; + litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we; + litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; end - if (soc_sdram_bankmachine7_twtpcon_valid) begin - soc_sdram_bankmachine7_twtpcon_count <= 3'd5; + if (litedramcore_bankmachine7_twtpcon_valid) begin + litedramcore_bankmachine7_twtpcon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine7_twtpcon_ready <= 1'd1; + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end else begin - soc_sdram_bankmachine7_twtpcon_ready <= 1'd0; + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine7_twtpcon_ready)) begin - soc_sdram_bankmachine7_twtpcon_count <= (soc_sdram_bankmachine7_twtpcon_count - 1'd1); - if ((soc_sdram_bankmachine7_twtpcon_count == 1'd1)) begin - soc_sdram_bankmachine7_twtpcon_ready <= 1'd1; + if ((~litedramcore_bankmachine7_twtpcon_ready)) begin + litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine7_trccon_valid) begin - soc_sdram_bankmachine7_trccon_count <= 3'd5; + if (litedramcore_bankmachine7_trccon_valid) begin + litedramcore_bankmachine7_trccon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine7_trccon_ready <= 1'd1; + litedramcore_bankmachine7_trccon_ready <= 1'd1; end else begin - soc_sdram_bankmachine7_trccon_ready <= 1'd0; + litedramcore_bankmachine7_trccon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine7_trccon_ready)) begin - soc_sdram_bankmachine7_trccon_count <= (soc_sdram_bankmachine7_trccon_count - 1'd1); - if ((soc_sdram_bankmachine7_trccon_count == 1'd1)) begin - soc_sdram_bankmachine7_trccon_ready <= 1'd1; + if ((~litedramcore_bankmachine7_trccon_ready)) begin + litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); + if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine7_trascon_valid) begin - soc_sdram_bankmachine7_trascon_count <= 3'd4; + if (litedramcore_bankmachine7_trascon_valid) begin + litedramcore_bankmachine7_trascon_count <= 3'd4; if (1'd0) begin - soc_sdram_bankmachine7_trascon_ready <= 1'd1; + litedramcore_bankmachine7_trascon_ready <= 1'd1; end else begin - soc_sdram_bankmachine7_trascon_ready <= 1'd0; + litedramcore_bankmachine7_trascon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine7_trascon_ready)) begin - soc_sdram_bankmachine7_trascon_count <= (soc_sdram_bankmachine7_trascon_count - 1'd1); - if ((soc_sdram_bankmachine7_trascon_count == 1'd1)) begin - soc_sdram_bankmachine7_trascon_ready <= 1'd1; + if ((~litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); + if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; end end end - vns_bankmachine7_state <= vns_bankmachine7_next_state; - if ((~soc_sdram_en0)) begin - soc_sdram_time0 <= 5'd31; + bankmachine7_state <= bankmachine7_next_state; + if ((~litedramcore_en0)) begin + litedramcore_time0 <= 5'd31; end else begin - if ((~soc_sdram_max_time0)) begin - soc_sdram_time0 <= (soc_sdram_time0 - 1'd1); + if ((~litedramcore_max_time0)) begin + litedramcore_time0 <= (litedramcore_time0 - 1'd1); end end - if ((~soc_sdram_en1)) begin - soc_sdram_time1 <= 4'd15; + if ((~litedramcore_en1)) begin + litedramcore_time1 <= 4'd15; end else begin - if ((~soc_sdram_max_time1)) begin - soc_sdram_time1 <= (soc_sdram_time1 - 1'd1); + if ((~litedramcore_max_time1)) begin + litedramcore_time1 <= (litedramcore_time1 - 1'd1); end end - if (soc_sdram_choose_cmd_ce) begin - case (soc_sdram_choose_cmd_grant) + if (litedramcore_choose_cmd_ce) begin + case (litedramcore_choose_cmd_grant) 1'd0: begin - if (soc_sdram_choose_cmd_request[1]) begin - soc_sdram_choose_cmd_grant <= 1'd1; + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_sdram_choose_cmd_request[2]) begin - soc_sdram_choose_cmd_grant <= 2'd2; + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_sdram_choose_cmd_request[3]) begin - soc_sdram_choose_cmd_grant <= 2'd3; + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_sdram_choose_cmd_request[4]) begin - soc_sdram_choose_cmd_grant <= 3'd4; + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_sdram_choose_cmd_request[5]) begin - soc_sdram_choose_cmd_grant <= 3'd5; + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_sdram_choose_cmd_request[6]) begin - soc_sdram_choose_cmd_grant <= 3'd6; + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_sdram_choose_cmd_request[7]) begin - soc_sdram_choose_cmd_grant <= 3'd7; + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; end end end @@ -15999,26 +13619,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (soc_sdram_choose_cmd_request[2]) begin - soc_sdram_choose_cmd_grant <= 2'd2; + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_sdram_choose_cmd_request[3]) begin - soc_sdram_choose_cmd_grant <= 2'd3; + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_sdram_choose_cmd_request[4]) begin - soc_sdram_choose_cmd_grant <= 3'd4; + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_sdram_choose_cmd_request[5]) begin - soc_sdram_choose_cmd_grant <= 3'd5; + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_sdram_choose_cmd_request[6]) begin - soc_sdram_choose_cmd_grant <= 3'd6; + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_sdram_choose_cmd_request[7]) begin - soc_sdram_choose_cmd_grant <= 3'd7; + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_sdram_choose_cmd_request[0]) begin - soc_sdram_choose_cmd_grant <= 1'd0; + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; end end end @@ -16028,26 +13648,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (soc_sdram_choose_cmd_request[3]) begin - soc_sdram_choose_cmd_grant <= 2'd3; + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_sdram_choose_cmd_request[4]) begin - soc_sdram_choose_cmd_grant <= 3'd4; + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_sdram_choose_cmd_request[5]) begin - soc_sdram_choose_cmd_grant <= 3'd5; + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_sdram_choose_cmd_request[6]) begin - soc_sdram_choose_cmd_grant <= 3'd6; + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_sdram_choose_cmd_request[7]) begin - soc_sdram_choose_cmd_grant <= 3'd7; + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_sdram_choose_cmd_request[0]) begin - soc_sdram_choose_cmd_grant <= 1'd0; + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_sdram_choose_cmd_request[1]) begin - soc_sdram_choose_cmd_grant <= 1'd1; + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; end end end @@ -16057,26 +13677,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (soc_sdram_choose_cmd_request[4]) begin - soc_sdram_choose_cmd_grant <= 3'd4; + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_sdram_choose_cmd_request[5]) begin - soc_sdram_choose_cmd_grant <= 3'd5; + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_sdram_choose_cmd_request[6]) begin - soc_sdram_choose_cmd_grant <= 3'd6; + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_sdram_choose_cmd_request[7]) begin - soc_sdram_choose_cmd_grant <= 3'd7; + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_sdram_choose_cmd_request[0]) begin - soc_sdram_choose_cmd_grant <= 1'd0; + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_sdram_choose_cmd_request[1]) begin - soc_sdram_choose_cmd_grant <= 1'd1; + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_sdram_choose_cmd_request[2]) begin - soc_sdram_choose_cmd_grant <= 2'd2; + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; end end end @@ -16086,26 +13706,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (soc_sdram_choose_cmd_request[5]) begin - soc_sdram_choose_cmd_grant <= 3'd5; + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_sdram_choose_cmd_request[6]) begin - soc_sdram_choose_cmd_grant <= 3'd6; + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_sdram_choose_cmd_request[7]) begin - soc_sdram_choose_cmd_grant <= 3'd7; + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_sdram_choose_cmd_request[0]) begin - soc_sdram_choose_cmd_grant <= 1'd0; + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_sdram_choose_cmd_request[1]) begin - soc_sdram_choose_cmd_grant <= 1'd1; + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_sdram_choose_cmd_request[2]) begin - soc_sdram_choose_cmd_grant <= 2'd2; + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_sdram_choose_cmd_request[3]) begin - soc_sdram_choose_cmd_grant <= 2'd3; + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; end end end @@ -16115,26 +13735,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (soc_sdram_choose_cmd_request[6]) begin - soc_sdram_choose_cmd_grant <= 3'd6; + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_sdram_choose_cmd_request[7]) begin - soc_sdram_choose_cmd_grant <= 3'd7; + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_sdram_choose_cmd_request[0]) begin - soc_sdram_choose_cmd_grant <= 1'd0; + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_sdram_choose_cmd_request[1]) begin - soc_sdram_choose_cmd_grant <= 1'd1; + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_sdram_choose_cmd_request[2]) begin - soc_sdram_choose_cmd_grant <= 2'd2; + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_sdram_choose_cmd_request[3]) begin - soc_sdram_choose_cmd_grant <= 2'd3; + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_sdram_choose_cmd_request[4]) begin - soc_sdram_choose_cmd_grant <= 3'd4; + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; end end end @@ -16144,26 +13764,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (soc_sdram_choose_cmd_request[7]) begin - soc_sdram_choose_cmd_grant <= 3'd7; + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_sdram_choose_cmd_request[0]) begin - soc_sdram_choose_cmd_grant <= 1'd0; + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_sdram_choose_cmd_request[1]) begin - soc_sdram_choose_cmd_grant <= 1'd1; + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_sdram_choose_cmd_request[2]) begin - soc_sdram_choose_cmd_grant <= 2'd2; + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_sdram_choose_cmd_request[3]) begin - soc_sdram_choose_cmd_grant <= 2'd3; + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_sdram_choose_cmd_request[4]) begin - soc_sdram_choose_cmd_grant <= 3'd4; + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_sdram_choose_cmd_request[5]) begin - soc_sdram_choose_cmd_grant <= 3'd5; + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; end end end @@ -16173,26 +13793,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (soc_sdram_choose_cmd_request[0]) begin - soc_sdram_choose_cmd_grant <= 1'd0; + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_sdram_choose_cmd_request[1]) begin - soc_sdram_choose_cmd_grant <= 1'd1; + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_sdram_choose_cmd_request[2]) begin - soc_sdram_choose_cmd_grant <= 2'd2; + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_sdram_choose_cmd_request[3]) begin - soc_sdram_choose_cmd_grant <= 2'd3; + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_sdram_choose_cmd_request[4]) begin - soc_sdram_choose_cmd_grant <= 3'd4; + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_sdram_choose_cmd_request[5]) begin - soc_sdram_choose_cmd_grant <= 3'd5; + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_sdram_choose_cmd_request[6]) begin - soc_sdram_choose_cmd_grant <= 3'd6; + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; end end end @@ -16203,29 +13823,29 @@ always @(posedge sys_clk) begin end endcase end - if (soc_sdram_choose_req_ce) begin - case (soc_sdram_choose_req_grant) + if (litedramcore_choose_req_ce) begin + case (litedramcore_choose_req_grant) 1'd0: begin - if (soc_sdram_choose_req_request[1]) begin - soc_sdram_choose_req_grant <= 1'd1; + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_sdram_choose_req_request[2]) begin - soc_sdram_choose_req_grant <= 2'd2; + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_sdram_choose_req_request[3]) begin - soc_sdram_choose_req_grant <= 2'd3; + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_sdram_choose_req_request[4]) begin - soc_sdram_choose_req_grant <= 3'd4; + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_sdram_choose_req_request[5]) begin - soc_sdram_choose_req_grant <= 3'd5; + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_sdram_choose_req_request[6]) begin - soc_sdram_choose_req_grant <= 3'd6; + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_sdram_choose_req_request[7]) begin - soc_sdram_choose_req_grant <= 3'd7; + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; end end end @@ -16235,26 +13855,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (soc_sdram_choose_req_request[2]) begin - soc_sdram_choose_req_grant <= 2'd2; + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_sdram_choose_req_request[3]) begin - soc_sdram_choose_req_grant <= 2'd3; + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_sdram_choose_req_request[4]) begin - soc_sdram_choose_req_grant <= 3'd4; + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_sdram_choose_req_request[5]) begin - soc_sdram_choose_req_grant <= 3'd5; + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_sdram_choose_req_request[6]) begin - soc_sdram_choose_req_grant <= 3'd6; + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_sdram_choose_req_request[7]) begin - soc_sdram_choose_req_grant <= 3'd7; + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_sdram_choose_req_request[0]) begin - soc_sdram_choose_req_grant <= 1'd0; + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; end end end @@ -16264,26 +13884,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (soc_sdram_choose_req_request[3]) begin - soc_sdram_choose_req_grant <= 2'd3; + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_sdram_choose_req_request[4]) begin - soc_sdram_choose_req_grant <= 3'd4; + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_sdram_choose_req_request[5]) begin - soc_sdram_choose_req_grant <= 3'd5; + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_sdram_choose_req_request[6]) begin - soc_sdram_choose_req_grant <= 3'd6; + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_sdram_choose_req_request[7]) begin - soc_sdram_choose_req_grant <= 3'd7; + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_sdram_choose_req_request[0]) begin - soc_sdram_choose_req_grant <= 1'd0; + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_sdram_choose_req_request[1]) begin - soc_sdram_choose_req_grant <= 1'd1; + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; end end end @@ -16293,26 +13913,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (soc_sdram_choose_req_request[4]) begin - soc_sdram_choose_req_grant <= 3'd4; + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_sdram_choose_req_request[5]) begin - soc_sdram_choose_req_grant <= 3'd5; + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_sdram_choose_req_request[6]) begin - soc_sdram_choose_req_grant <= 3'd6; + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_sdram_choose_req_request[7]) begin - soc_sdram_choose_req_grant <= 3'd7; + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_sdram_choose_req_request[0]) begin - soc_sdram_choose_req_grant <= 1'd0; + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_sdram_choose_req_request[1]) begin - soc_sdram_choose_req_grant <= 1'd1; + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_sdram_choose_req_request[2]) begin - soc_sdram_choose_req_grant <= 2'd2; + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; end end end @@ -16322,26 +13942,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (soc_sdram_choose_req_request[5]) begin - soc_sdram_choose_req_grant <= 3'd5; + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_sdram_choose_req_request[6]) begin - soc_sdram_choose_req_grant <= 3'd6; + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_sdram_choose_req_request[7]) begin - soc_sdram_choose_req_grant <= 3'd7; + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_sdram_choose_req_request[0]) begin - soc_sdram_choose_req_grant <= 1'd0; + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_sdram_choose_req_request[1]) begin - soc_sdram_choose_req_grant <= 1'd1; + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_sdram_choose_req_request[2]) begin - soc_sdram_choose_req_grant <= 2'd2; + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_sdram_choose_req_request[3]) begin - soc_sdram_choose_req_grant <= 2'd3; + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; end end end @@ -16351,26 +13971,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (soc_sdram_choose_req_request[6]) begin - soc_sdram_choose_req_grant <= 3'd6; + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_sdram_choose_req_request[7]) begin - soc_sdram_choose_req_grant <= 3'd7; + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_sdram_choose_req_request[0]) begin - soc_sdram_choose_req_grant <= 1'd0; + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_sdram_choose_req_request[1]) begin - soc_sdram_choose_req_grant <= 1'd1; + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_sdram_choose_req_request[2]) begin - soc_sdram_choose_req_grant <= 2'd2; + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_sdram_choose_req_request[3]) begin - soc_sdram_choose_req_grant <= 2'd3; + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_sdram_choose_req_request[4]) begin - soc_sdram_choose_req_grant <= 3'd4; + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; end end end @@ -16380,26 +14000,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (soc_sdram_choose_req_request[7]) begin - soc_sdram_choose_req_grant <= 3'd7; + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_sdram_choose_req_request[0]) begin - soc_sdram_choose_req_grant <= 1'd0; + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_sdram_choose_req_request[1]) begin - soc_sdram_choose_req_grant <= 1'd1; + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_sdram_choose_req_request[2]) begin - soc_sdram_choose_req_grant <= 2'd2; + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_sdram_choose_req_request[3]) begin - soc_sdram_choose_req_grant <= 2'd3; + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_sdram_choose_req_request[4]) begin - soc_sdram_choose_req_grant <= 3'd4; + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_sdram_choose_req_request[5]) begin - soc_sdram_choose_req_grant <= 3'd5; + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; end end end @@ -16409,26 +14029,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (soc_sdram_choose_req_request[0]) begin - soc_sdram_choose_req_grant <= 1'd0; + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_sdram_choose_req_request[1]) begin - soc_sdram_choose_req_grant <= 1'd1; + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_sdram_choose_req_request[2]) begin - soc_sdram_choose_req_grant <= 2'd2; + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_sdram_choose_req_request[3]) begin - soc_sdram_choose_req_grant <= 2'd3; + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_sdram_choose_req_request[4]) begin - soc_sdram_choose_req_grant <= 3'd4; + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_sdram_choose_req_request[5]) begin - soc_sdram_choose_req_grant <= 3'd5; + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_sdram_choose_req_request[6]) begin - soc_sdram_choose_req_grant <= 3'd6; + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; end end end @@ -16439,1280 +14059,709 @@ always @(posedge sys_clk) begin end endcase end - soc_sdram_dfi_p0_cs_n <= 1'd0; - soc_sdram_dfi_p0_bank <= vns_array_muxed0; - soc_sdram_dfi_p0_address <= vns_array_muxed1; - soc_sdram_dfi_p0_cas_n <= (~vns_array_muxed2); - soc_sdram_dfi_p0_ras_n <= (~vns_array_muxed3); - soc_sdram_dfi_p0_we_n <= (~vns_array_muxed4); - soc_sdram_dfi_p0_rddata_en <= vns_array_muxed5; - soc_sdram_dfi_p0_wrdata_en <= vns_array_muxed6; - soc_sdram_dfi_p1_cs_n <= 1'd0; - soc_sdram_dfi_p1_bank <= vns_array_muxed7; - soc_sdram_dfi_p1_address <= vns_array_muxed8; - soc_sdram_dfi_p1_cas_n <= (~vns_array_muxed9); - soc_sdram_dfi_p1_ras_n <= (~vns_array_muxed10); - soc_sdram_dfi_p1_we_n <= (~vns_array_muxed11); - soc_sdram_dfi_p1_rddata_en <= vns_array_muxed12; - soc_sdram_dfi_p1_wrdata_en <= vns_array_muxed13; - soc_sdram_dfi_p2_cs_n <= 1'd0; - soc_sdram_dfi_p2_bank <= vns_array_muxed14; - soc_sdram_dfi_p2_address <= vns_array_muxed15; - soc_sdram_dfi_p2_cas_n <= (~vns_array_muxed16); - soc_sdram_dfi_p2_ras_n <= (~vns_array_muxed17); - soc_sdram_dfi_p2_we_n <= (~vns_array_muxed18); - soc_sdram_dfi_p2_rddata_en <= vns_array_muxed19; - soc_sdram_dfi_p2_wrdata_en <= vns_array_muxed20; - soc_sdram_dfi_p3_cs_n <= 1'd0; - soc_sdram_dfi_p3_bank <= vns_array_muxed21; - soc_sdram_dfi_p3_address <= vns_array_muxed22; - soc_sdram_dfi_p3_cas_n <= (~vns_array_muxed23); - soc_sdram_dfi_p3_ras_n <= (~vns_array_muxed24); - soc_sdram_dfi_p3_we_n <= (~vns_array_muxed25); - soc_sdram_dfi_p3_rddata_en <= vns_array_muxed26; - soc_sdram_dfi_p3_wrdata_en <= vns_array_muxed27; - if (soc_sdram_trrdcon_valid) begin - soc_sdram_trrdcon_count <= 1'd1; + litedramcore_dfi_p0_cs_n <= 1'd0; + litedramcore_dfi_p0_bank <= array_muxed0; + litedramcore_dfi_p0_address <= array_muxed1; + litedramcore_dfi_p0_cas_n <= (~array_muxed2); + litedramcore_dfi_p0_ras_n <= (~array_muxed3); + litedramcore_dfi_p0_we_n <= (~array_muxed4); + litedramcore_dfi_p0_rddata_en <= array_muxed5; + litedramcore_dfi_p0_wrdata_en <= array_muxed6; + litedramcore_dfi_p1_cs_n <= 1'd0; + litedramcore_dfi_p1_bank <= array_muxed7; + litedramcore_dfi_p1_address <= array_muxed8; + litedramcore_dfi_p1_cas_n <= (~array_muxed9); + litedramcore_dfi_p1_ras_n <= (~array_muxed10); + litedramcore_dfi_p1_we_n <= (~array_muxed11); + litedramcore_dfi_p1_rddata_en <= array_muxed12; + litedramcore_dfi_p1_wrdata_en <= array_muxed13; + litedramcore_dfi_p2_cs_n <= 1'd0; + litedramcore_dfi_p2_bank <= array_muxed14; + litedramcore_dfi_p2_address <= array_muxed15; + litedramcore_dfi_p2_cas_n <= (~array_muxed16); + litedramcore_dfi_p2_ras_n <= (~array_muxed17); + litedramcore_dfi_p2_we_n <= (~array_muxed18); + litedramcore_dfi_p2_rddata_en <= array_muxed19; + litedramcore_dfi_p2_wrdata_en <= array_muxed20; + litedramcore_dfi_p3_cs_n <= 1'd0; + litedramcore_dfi_p3_bank <= array_muxed21; + litedramcore_dfi_p3_address <= array_muxed22; + litedramcore_dfi_p3_cas_n <= (~array_muxed23); + litedramcore_dfi_p3_ras_n <= (~array_muxed24); + litedramcore_dfi_p3_we_n <= (~array_muxed25); + litedramcore_dfi_p3_rddata_en <= array_muxed26; + litedramcore_dfi_p3_wrdata_en <= array_muxed27; + if (litedramcore_trrdcon_valid) begin + litedramcore_trrdcon_count <= 1'd1; if (1'd0) begin - soc_sdram_trrdcon_ready <= 1'd1; + litedramcore_trrdcon_ready <= 1'd1; end else begin - soc_sdram_trrdcon_ready <= 1'd0; + litedramcore_trrdcon_ready <= 1'd0; end end else begin - if ((~soc_sdram_trrdcon_ready)) begin - soc_sdram_trrdcon_count <= (soc_sdram_trrdcon_count - 1'd1); - if ((soc_sdram_trrdcon_count == 1'd1)) begin - soc_sdram_trrdcon_ready <= 1'd1; + if ((~litedramcore_trrdcon_ready)) begin + litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); + if ((litedramcore_trrdcon_count == 1'd1)) begin + litedramcore_trrdcon_ready <= 1'd1; end end end - soc_sdram_tfawcon_window <= {soc_sdram_tfawcon_window, soc_sdram_tfawcon_valid}; - if ((soc_sdram_tfawcon_count < 3'd4)) begin - if ((soc_sdram_tfawcon_count == 2'd3)) begin - soc_sdram_tfawcon_ready <= (~soc_sdram_tfawcon_valid); + litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; + if ((litedramcore_tfawcon_count < 3'd4)) begin + if ((litedramcore_tfawcon_count == 2'd3)) begin + litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); end else begin - soc_sdram_tfawcon_ready <= 1'd1; + litedramcore_tfawcon_ready <= 1'd1; end end - if (soc_sdram_tccdcon_valid) begin - soc_sdram_tccdcon_count <= 1'd0; + if (litedramcore_tccdcon_valid) begin + litedramcore_tccdcon_count <= 1'd0; if (1'd1) begin - soc_sdram_tccdcon_ready <= 1'd1; + litedramcore_tccdcon_ready <= 1'd1; end else begin - soc_sdram_tccdcon_ready <= 1'd0; + litedramcore_tccdcon_ready <= 1'd0; end end else begin - if ((~soc_sdram_tccdcon_ready)) begin - soc_sdram_tccdcon_count <= (soc_sdram_tccdcon_count - 1'd1); - if ((soc_sdram_tccdcon_count == 1'd1)) begin - soc_sdram_tccdcon_ready <= 1'd1; + if ((~litedramcore_tccdcon_ready)) begin + litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); + if ((litedramcore_tccdcon_count == 1'd1)) begin + litedramcore_tccdcon_ready <= 1'd1; end end end - if (soc_sdram_twtrcon_valid) begin - soc_sdram_twtrcon_count <= 3'd4; + if (litedramcore_twtrcon_valid) begin + litedramcore_twtrcon_count <= 3'd4; if (1'd0) begin - soc_sdram_twtrcon_ready <= 1'd1; + litedramcore_twtrcon_ready <= 1'd1; end else begin - soc_sdram_twtrcon_ready <= 1'd0; - end - end else begin - if ((~soc_sdram_twtrcon_ready)) begin - soc_sdram_twtrcon_count <= (soc_sdram_twtrcon_count - 1'd1); - if ((soc_sdram_twtrcon_count == 1'd1)) begin - soc_sdram_twtrcon_ready <= 1'd1; - end - end - end - vns_multiplexer_state <= vns_multiplexer_next_state; - vns_new_master_wdata_ready0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_sdram_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd0) & soc_sdram_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd0) & soc_sdram_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd0) & soc_sdram_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd0) & soc_sdram_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd0) & soc_sdram_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd0) & soc_sdram_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd0) & soc_sdram_interface_bank7_wdata_ready)); - vns_new_master_wdata_ready1 <= vns_new_master_wdata_ready0; - vns_new_master_wdata_ready2 <= vns_new_master_wdata_ready1; - vns_new_master_wdata_ready3 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd1) & soc_sdram_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd1) & soc_sdram_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd1) & soc_sdram_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd1) & soc_sdram_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd1) & soc_sdram_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd1) & soc_sdram_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd1) & soc_sdram_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd1) & soc_sdram_interface_bank7_wdata_ready)); - vns_new_master_wdata_ready4 <= vns_new_master_wdata_ready3; - vns_new_master_wdata_ready5 <= vns_new_master_wdata_ready4; - vns_new_master_rdata_valid0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_sdram_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd0) & soc_sdram_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd0) & soc_sdram_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd0) & soc_sdram_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd0) & soc_sdram_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd0) & soc_sdram_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd0) & soc_sdram_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd0) & soc_sdram_interface_bank7_rdata_valid)); - vns_new_master_rdata_valid1 <= vns_new_master_rdata_valid0; - vns_new_master_rdata_valid2 <= vns_new_master_rdata_valid1; - vns_new_master_rdata_valid3 <= vns_new_master_rdata_valid2; - vns_new_master_rdata_valid4 <= vns_new_master_rdata_valid3; - vns_new_master_rdata_valid5 <= vns_new_master_rdata_valid4; - vns_new_master_rdata_valid6 <= vns_new_master_rdata_valid5; - vns_new_master_rdata_valid7 <= vns_new_master_rdata_valid6; - vns_new_master_rdata_valid8 <= vns_new_master_rdata_valid7; - vns_new_master_rdata_valid9 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd1) & soc_sdram_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd1) & soc_sdram_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd1) & soc_sdram_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd1) & soc_sdram_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd1) & soc_sdram_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd1) & soc_sdram_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd1) & soc_sdram_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd1) & soc_sdram_interface_bank7_rdata_valid)); - vns_new_master_rdata_valid10 <= vns_new_master_rdata_valid9; - vns_new_master_rdata_valid11 <= vns_new_master_rdata_valid10; - vns_new_master_rdata_valid12 <= vns_new_master_rdata_valid11; - vns_new_master_rdata_valid13 <= vns_new_master_rdata_valid12; - vns_new_master_rdata_valid14 <= vns_new_master_rdata_valid13; - vns_new_master_rdata_valid15 <= vns_new_master_rdata_valid14; - vns_new_master_rdata_valid16 <= vns_new_master_rdata_valid15; - vns_new_master_rdata_valid17 <= vns_new_master_rdata_valid16; - if (vns_roundrobin0_ce) begin - case (vns_roundrobin0_grant) - 1'd0: begin - if (vns_roundrobin0_request[1]) begin - vns_roundrobin0_grant <= 1'd1; - end - end - 1'd1: begin - if (vns_roundrobin0_request[0]) begin - vns_roundrobin0_grant <= 1'd0; - end - end - endcase - end - if (vns_roundrobin1_ce) begin - case (vns_roundrobin1_grant) - 1'd0: begin - if (vns_roundrobin1_request[1]) begin - vns_roundrobin1_grant <= 1'd1; - end - end - 1'd1: begin - if (vns_roundrobin1_request[0]) begin - vns_roundrobin1_grant <= 1'd0; - end - end - endcase - end - if (vns_roundrobin2_ce) begin - case (vns_roundrobin2_grant) - 1'd0: begin - if (vns_roundrobin2_request[1]) begin - vns_roundrobin2_grant <= 1'd1; - end - end - 1'd1: begin - if (vns_roundrobin2_request[0]) begin - vns_roundrobin2_grant <= 1'd0; - end - end - endcase - end - if (vns_roundrobin3_ce) begin - case (vns_roundrobin3_grant) - 1'd0: begin - if (vns_roundrobin3_request[1]) begin - vns_roundrobin3_grant <= 1'd1; - end - end - 1'd1: begin - if (vns_roundrobin3_request[0]) begin - vns_roundrobin3_grant <= 1'd0; - end - end - endcase - end - if (vns_roundrobin4_ce) begin - case (vns_roundrobin4_grant) - 1'd0: begin - if (vns_roundrobin4_request[1]) begin - vns_roundrobin4_grant <= 1'd1; - end - end - 1'd1: begin - if (vns_roundrobin4_request[0]) begin - vns_roundrobin4_grant <= 1'd0; - end - end - endcase - end - if (vns_roundrobin5_ce) begin - case (vns_roundrobin5_grant) - 1'd0: begin - if (vns_roundrobin5_request[1]) begin - vns_roundrobin5_grant <= 1'd1; - end - end - 1'd1: begin - if (vns_roundrobin5_request[0]) begin - vns_roundrobin5_grant <= 1'd0; - end - end - endcase - end - if (vns_roundrobin6_ce) begin - case (vns_roundrobin6_grant) - 1'd0: begin - if (vns_roundrobin6_request[1]) begin - vns_roundrobin6_grant <= 1'd1; - end - end - 1'd1: begin - if (vns_roundrobin6_request[0]) begin - vns_roundrobin6_grant <= 1'd0; - end - end - endcase - end - if (vns_roundrobin7_ce) begin - case (vns_roundrobin7_grant) - 1'd0: begin - if (vns_roundrobin7_request[1]) begin - vns_roundrobin7_grant <= 1'd1; - end - end - 1'd1: begin - if (vns_roundrobin7_request[0]) begin - vns_roundrobin7_grant <= 1'd0; - end - end - endcase - end - if (soc_counter_reset) begin - soc_counter <= 1'd0; - end else begin - if (soc_counter_ce) begin - soc_counter <= (soc_counter + 1'd1); - end - end - if (soc_address_ce) begin - soc_address_q <= soc_address_d; - end - if (soc_address_reset) begin - soc_address_q <= 30'd0; - end - if (soc_need_refill_ce) begin - soc_need_refill_q <= soc_need_refill_d; - end - if (soc_need_refill_reset) begin - soc_need_refill_q <= 1'd1; - end - vns_converter_state <= vns_converter_next_state; - if (soc_cached_datas_ce0) begin - soc_cached_datas_flipflop0_q <= soc_cached_datas_flipflop0_d; - end - if (soc_cached_datas_reset0) begin - soc_cached_datas_flipflop0_q <= 32'd0; - end - if (soc_cached_datas_ce1) begin - soc_cached_datas_flipflop1_q <= soc_cached_datas_flipflop1_d; - end - if (soc_cached_datas_reset1) begin - soc_cached_datas_flipflop1_q <= 32'd0; - end - if (soc_cached_datas_ce2) begin - soc_cached_datas_flipflop2_q <= soc_cached_datas_flipflop2_d; - end - if (soc_cached_datas_reset2) begin - soc_cached_datas_flipflop2_q <= 32'd0; - end - if (soc_cached_datas_ce3) begin - soc_cached_datas_flipflop3_q <= soc_cached_datas_flipflop3_d; - end - if (soc_cached_datas_reset3) begin - soc_cached_datas_flipflop3_q <= 32'd0; - end - if (soc_cached_sels_ce0) begin - soc_cached_sels_flipflop0_q <= soc_cached_sels_flipflop0_d; - end - if (soc_cached_sels_reset0) begin - soc_cached_sels_flipflop0_q <= 4'd0; - end - if (soc_cached_sels_ce1) begin - soc_cached_sels_flipflop1_q <= soc_cached_sels_flipflop1_d; - end - if (soc_cached_sels_reset1) begin - soc_cached_sels_flipflop1_q <= 4'd0; - end - if (soc_cached_sels_ce2) begin - soc_cached_sels_flipflop2_q <= soc_cached_sels_flipflop2_d; - end - if (soc_cached_sels_reset2) begin - soc_cached_sels_flipflop2_q <= 4'd0; - end - if (soc_cached_sels_ce3) begin - soc_cached_sels_flipflop3_q <= soc_cached_sels_flipflop3_d; - end - if (soc_cached_sels_reset3) begin - soc_cached_sels_flipflop3_q <= 4'd0; - end - vns_litedramwishbone2native_state <= vns_litedramwishbone2native_next_state; - if (soc_count_next_value_ce) begin - soc_count <= soc_count_next_value; - end - case (vns_grant) - 1'd0: begin - if ((~vns_request[0])) begin - if (vns_request[1]) begin - vns_grant <= 1'd1; - end - end - end - 1'd1: begin - if ((~vns_request[1])) begin - if (vns_request[0]) begin - vns_grant <= 1'd0; - end - end - end - endcase - vns_slave_sel_r <= vns_slave_sel; - if (vns_wait) begin - if ((~vns_done)) begin - vns_count <= (vns_count - 1'd1); + litedramcore_twtrcon_ready <= 1'd0; end end else begin - vns_count <= 20'd1000000; - end - vns_interface0_bank_bus_dat_r <= 1'd0; - if (vns_csrbank0_sel) begin - case (vns_interface0_bank_bus_adr[3:0]) - 1'd0: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_reset0_w; - end - 1'd1: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch3_w; - end - 2'd2: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch2_w; - end - 2'd3: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch1_w; - end - 3'd4: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch0_w; - end - 3'd5: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors3_w; - end - 3'd6: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors2_w; - end - 3'd7: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors1_w; - end - 4'd8: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors0_w; - end - endcase - end - if (vns_csrbank0_reset0_re) begin - soc_litedramcore_soccontroller_reset_storage <= vns_csrbank0_reset0_r; - end - soc_litedramcore_soccontroller_reset_re <= vns_csrbank0_reset0_re; - if (vns_csrbank0_scratch3_re) begin - soc_litedramcore_soccontroller_scratch_storage[31:24] <= vns_csrbank0_scratch3_r; - end - if (vns_csrbank0_scratch2_re) begin - soc_litedramcore_soccontroller_scratch_storage[23:16] <= vns_csrbank0_scratch2_r; - end - if (vns_csrbank0_scratch1_re) begin - soc_litedramcore_soccontroller_scratch_storage[15:8] <= vns_csrbank0_scratch1_r; - end - if (vns_csrbank0_scratch0_re) begin - soc_litedramcore_soccontroller_scratch_storage[7:0] <= vns_csrbank0_scratch0_r; - end - soc_litedramcore_soccontroller_scratch_re <= vns_csrbank0_scratch0_re; - vns_interface1_bank_bus_dat_r <= 1'd0; - if (vns_csrbank1_sel) begin - case (vns_interface1_bank_bus_adr[0]) + if ((~litedramcore_twtrcon_ready)) begin + litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); + if ((litedramcore_twtrcon_count == 1'd1)) begin + litedramcore_twtrcon_ready <= 1'd1; + end + end + end + multiplexer_state <= multiplexer_next_state; + new_master_wdata_ready0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); + new_master_wdata_ready1 <= new_master_wdata_ready0; + new_master_wdata_ready2 <= new_master_wdata_ready1; + new_master_rdata_valid0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); + new_master_rdata_valid1 <= new_master_rdata_valid0; + new_master_rdata_valid2 <= new_master_rdata_valid1; + new_master_rdata_valid3 <= new_master_rdata_valid2; + new_master_rdata_valid4 <= new_master_rdata_valid3; + new_master_rdata_valid5 <= new_master_rdata_valid4; + new_master_rdata_valid6 <= new_master_rdata_valid5; + new_master_rdata_valid7 <= new_master_rdata_valid6; + new_master_rdata_valid8 <= new_master_rdata_valid7; + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[3]) 1'd0: begin - vns_interface1_bank_bus_dat_r <= vns_csrbank1_init_done0_w; + interface0_bank_bus_dat_r <= csrbank0_init_done0_w; end 1'd1: begin - vns_interface1_bank_bus_dat_r <= vns_csrbank1_init_error0_w; + interface0_bank_bus_dat_r <= csrbank0_init_error0_w; end endcase end - if (vns_csrbank1_init_done0_re) begin - soc_init_done_storage <= vns_csrbank1_init_done0_r; + if (csrbank0_init_done0_re) begin + init_done_storage <= csrbank0_init_done0_r; end - soc_init_done_re <= vns_csrbank1_init_done0_re; - if (vns_csrbank1_init_error0_re) begin - soc_init_error_storage <= vns_csrbank1_init_error0_r; + init_done_re <= csrbank0_init_done0_re; + if (csrbank0_init_error0_re) begin + init_error_storage <= csrbank0_init_error0_r; end - soc_init_error_re <= vns_csrbank1_init_error0_re; - vns_interface2_bank_bus_dat_r <= 1'd0; - if (vns_csrbank2_sel) begin - case (vns_interface2_bank_bus_adr[3:0]) + init_error_re <= csrbank0_init_error0_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[6:3]) 1'd0: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_half_sys8x_taps0_w; + interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; end 1'd1: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_wlevel_en0_w; + interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w; end 2'd2: begin - vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_wlevel_strobe_w; + interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w; end 2'd3: begin - vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_cdly_rst_w; + interface1_bank_bus_dat_r <= a7ddrphy_cdly_rst_w; end 3'd4: begin - vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_cdly_inc_w; + interface1_bank_bus_dat_r <= a7ddrphy_cdly_inc_w; end 3'd5: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dly_sel0_w; + interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; end 3'd6: begin - vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_rst_w; + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w; end 3'd7: begin - vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_inc_w; + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w; end 4'd8: begin - vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_rst_w; + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w; end 4'd9: begin - vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_w; + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w; end endcase end - if (vns_csrbank2_half_sys8x_taps0_re) begin - soc_a7ddrphy_half_sys8x_taps_storage[4:0] <= vns_csrbank2_half_sys8x_taps0_r; + if (csrbank1_half_sys8x_taps0_re) begin + a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r; end - soc_a7ddrphy_half_sys8x_taps_re <= vns_csrbank2_half_sys8x_taps0_re; - if (vns_csrbank2_wlevel_en0_re) begin - soc_a7ddrphy_wlevel_en_storage <= vns_csrbank2_wlevel_en0_r; + a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re; + if (csrbank1_wlevel_en0_re) begin + a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r; end - soc_a7ddrphy_wlevel_en_re <= vns_csrbank2_wlevel_en0_re; - if (vns_csrbank2_dly_sel0_re) begin - soc_a7ddrphy_dly_sel_storage[1:0] <= vns_csrbank2_dly_sel0_r; + a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re; + if (csrbank1_dly_sel0_re) begin + a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r; end - soc_a7ddrphy_dly_sel_re <= vns_csrbank2_dly_sel0_re; - vns_interface3_bank_bus_dat_r <= 1'd0; - if (vns_csrbank3_sel) begin - case (vns_interface3_bank_bus_adr[5:0]) + a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; + interface2_bank_bus_dat_r <= 1'd0; + if (csrbank2_sel) begin + case (interface2_bank_bus_adr[8:3]) 1'd0: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_control0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; end 1'd1: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_command0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; end 2'd2: begin - vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector0_command_issue_w; + interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_address1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address1_w; end 3'd4: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_address0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; end 3'd5: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_baddress0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; end 3'd6: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata3_w; end 3'd7: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata2_w; end 4'd8: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w; end 4'd9: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; end 4'd10: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata3_w; end 4'd11: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata2_w; end 4'd12: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w; end 4'd13: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w; end 4'd14: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_command0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; end 4'd15: begin - vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector1_command_issue_w; + interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; end 5'd16: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_address1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address1_w; end 5'd17: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_address0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; end 5'd18: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_baddress0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; end 5'd19: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata3_w; end 5'd20: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata2_w; end 5'd21: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w; end 5'd22: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; end 5'd23: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata3_w; end 5'd24: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata2_w; end 5'd25: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w; end 5'd26: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w; end 5'd27: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_command0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; end 5'd28: begin - vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector2_command_issue_w; + interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; end 5'd29: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_address1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address1_w; end 5'd30: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_address0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; end 5'd31: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_baddress0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; end 6'd32: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata3_w; end 6'd33: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata2_w; end 6'd34: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata1_w; end 6'd35: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; end 6'd36: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata3_w; end 6'd37: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata2_w; end 6'd38: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata1_w; end 6'd39: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata0_w; end 6'd40: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_command0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; end 6'd41: begin - vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector3_command_issue_w; + interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; end 6'd42: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_address1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address1_w; end 6'd43: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_address0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; end 6'd44: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_baddress0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; end 6'd45: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata3_w; end 6'd46: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata2_w; end 6'd47: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata1_w; end 6'd48: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; end 6'd49: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata3_w; end 6'd50: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata2_w; end 6'd51: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata1_w; end 6'd52: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata0_w; end endcase end - if (vns_csrbank3_dfii_control0_re) begin - soc_sdram_storage[3:0] <= vns_csrbank3_dfii_control0_r; - end - soc_sdram_re <= vns_csrbank3_dfii_control0_re; - if (vns_csrbank3_dfii_pi0_command0_re) begin - soc_sdram_phaseinjector0_command_storage[5:0] <= vns_csrbank3_dfii_pi0_command0_r; - end - soc_sdram_phaseinjector0_command_re <= vns_csrbank3_dfii_pi0_command0_re; - if (vns_csrbank3_dfii_pi0_address1_re) begin - soc_sdram_phaseinjector0_address_storage[13:8] <= vns_csrbank3_dfii_pi0_address1_r; - end - if (vns_csrbank3_dfii_pi0_address0_re) begin - soc_sdram_phaseinjector0_address_storage[7:0] <= vns_csrbank3_dfii_pi0_address0_r; - end - soc_sdram_phaseinjector0_address_re <= vns_csrbank3_dfii_pi0_address0_re; - if (vns_csrbank3_dfii_pi0_baddress0_re) begin - soc_sdram_phaseinjector0_baddress_storage[2:0] <= vns_csrbank3_dfii_pi0_baddress0_r; - end - soc_sdram_phaseinjector0_baddress_re <= vns_csrbank3_dfii_pi0_baddress0_re; - if (vns_csrbank3_dfii_pi0_wrdata3_re) begin - soc_sdram_phaseinjector0_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi0_wrdata3_r; - end - if (vns_csrbank3_dfii_pi0_wrdata2_re) begin - soc_sdram_phaseinjector0_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi0_wrdata2_r; - end - if (vns_csrbank3_dfii_pi0_wrdata1_re) begin - soc_sdram_phaseinjector0_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi0_wrdata1_r; - end - if (vns_csrbank3_dfii_pi0_wrdata0_re) begin - soc_sdram_phaseinjector0_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi0_wrdata0_r; + if (csrbank2_dfii_control0_re) begin + litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; end - soc_sdram_phaseinjector0_wrdata_re <= vns_csrbank3_dfii_pi0_wrdata0_re; - if (vns_csrbank3_dfii_pi1_command0_re) begin - soc_sdram_phaseinjector1_command_storage[5:0] <= vns_csrbank3_dfii_pi1_command0_r; + litedramcore_re <= csrbank2_dfii_control0_re; + if (csrbank2_dfii_pi0_command0_re) begin + litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; end - soc_sdram_phaseinjector1_command_re <= vns_csrbank3_dfii_pi1_command0_re; - if (vns_csrbank3_dfii_pi1_address1_re) begin - soc_sdram_phaseinjector1_address_storage[13:8] <= vns_csrbank3_dfii_pi1_address1_r; + litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; + if (csrbank2_dfii_pi0_address1_re) begin + litedramcore_phaseinjector0_address_storage[13:8] <= csrbank2_dfii_pi0_address1_r; end - if (vns_csrbank3_dfii_pi1_address0_re) begin - soc_sdram_phaseinjector1_address_storage[7:0] <= vns_csrbank3_dfii_pi1_address0_r; + if (csrbank2_dfii_pi0_address0_re) begin + litedramcore_phaseinjector0_address_storage[7:0] <= csrbank2_dfii_pi0_address0_r; end - soc_sdram_phaseinjector1_address_re <= vns_csrbank3_dfii_pi1_address0_re; - if (vns_csrbank3_dfii_pi1_baddress0_re) begin - soc_sdram_phaseinjector1_baddress_storage[2:0] <= vns_csrbank3_dfii_pi1_baddress0_r; + litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; + if (csrbank2_dfii_pi0_baddress0_re) begin + litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; end - soc_sdram_phaseinjector1_baddress_re <= vns_csrbank3_dfii_pi1_baddress0_re; - if (vns_csrbank3_dfii_pi1_wrdata3_re) begin - soc_sdram_phaseinjector1_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi1_wrdata3_r; + litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; + if (csrbank2_dfii_pi0_wrdata3_re) begin + litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank2_dfii_pi0_wrdata3_r; end - if (vns_csrbank3_dfii_pi1_wrdata2_re) begin - soc_sdram_phaseinjector1_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi1_wrdata2_r; + if (csrbank2_dfii_pi0_wrdata2_re) begin + litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank2_dfii_pi0_wrdata2_r; end - if (vns_csrbank3_dfii_pi1_wrdata1_re) begin - soc_sdram_phaseinjector1_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi1_wrdata1_r; + if (csrbank2_dfii_pi0_wrdata1_re) begin + litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank2_dfii_pi0_wrdata1_r; end - if (vns_csrbank3_dfii_pi1_wrdata0_re) begin - soc_sdram_phaseinjector1_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi1_wrdata0_r; + if (csrbank2_dfii_pi0_wrdata0_re) begin + litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank2_dfii_pi0_wrdata0_r; end - soc_sdram_phaseinjector1_wrdata_re <= vns_csrbank3_dfii_pi1_wrdata0_re; - if (vns_csrbank3_dfii_pi2_command0_re) begin - soc_sdram_phaseinjector2_command_storage[5:0] <= vns_csrbank3_dfii_pi2_command0_r; + litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; + if (csrbank2_dfii_pi1_command0_re) begin + litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; end - soc_sdram_phaseinjector2_command_re <= vns_csrbank3_dfii_pi2_command0_re; - if (vns_csrbank3_dfii_pi2_address1_re) begin - soc_sdram_phaseinjector2_address_storage[13:8] <= vns_csrbank3_dfii_pi2_address1_r; + litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; + if (csrbank2_dfii_pi1_address1_re) begin + litedramcore_phaseinjector1_address_storage[13:8] <= csrbank2_dfii_pi1_address1_r; end - if (vns_csrbank3_dfii_pi2_address0_re) begin - soc_sdram_phaseinjector2_address_storage[7:0] <= vns_csrbank3_dfii_pi2_address0_r; + if (csrbank2_dfii_pi1_address0_re) begin + litedramcore_phaseinjector1_address_storage[7:0] <= csrbank2_dfii_pi1_address0_r; end - soc_sdram_phaseinjector2_address_re <= vns_csrbank3_dfii_pi2_address0_re; - if (vns_csrbank3_dfii_pi2_baddress0_re) begin - soc_sdram_phaseinjector2_baddress_storage[2:0] <= vns_csrbank3_dfii_pi2_baddress0_r; + litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; + if (csrbank2_dfii_pi1_baddress0_re) begin + litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; end - soc_sdram_phaseinjector2_baddress_re <= vns_csrbank3_dfii_pi2_baddress0_re; - if (vns_csrbank3_dfii_pi2_wrdata3_re) begin - soc_sdram_phaseinjector2_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi2_wrdata3_r; + litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; + if (csrbank2_dfii_pi1_wrdata3_re) begin + litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank2_dfii_pi1_wrdata3_r; end - if (vns_csrbank3_dfii_pi2_wrdata2_re) begin - soc_sdram_phaseinjector2_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi2_wrdata2_r; - end - if (vns_csrbank3_dfii_pi2_wrdata1_re) begin - soc_sdram_phaseinjector2_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi2_wrdata1_r; - end - if (vns_csrbank3_dfii_pi2_wrdata0_re) begin - soc_sdram_phaseinjector2_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi2_wrdata0_r; - end - soc_sdram_phaseinjector2_wrdata_re <= vns_csrbank3_dfii_pi2_wrdata0_re; - if (vns_csrbank3_dfii_pi3_command0_re) begin - soc_sdram_phaseinjector3_command_storage[5:0] <= vns_csrbank3_dfii_pi3_command0_r; - end - soc_sdram_phaseinjector3_command_re <= vns_csrbank3_dfii_pi3_command0_re; - if (vns_csrbank3_dfii_pi3_address1_re) begin - soc_sdram_phaseinjector3_address_storage[13:8] <= vns_csrbank3_dfii_pi3_address1_r; - end - if (vns_csrbank3_dfii_pi3_address0_re) begin - soc_sdram_phaseinjector3_address_storage[7:0] <= vns_csrbank3_dfii_pi3_address0_r; - end - soc_sdram_phaseinjector3_address_re <= vns_csrbank3_dfii_pi3_address0_re; - if (vns_csrbank3_dfii_pi3_baddress0_re) begin - soc_sdram_phaseinjector3_baddress_storage[2:0] <= vns_csrbank3_dfii_pi3_baddress0_r; - end - soc_sdram_phaseinjector3_baddress_re <= vns_csrbank3_dfii_pi3_baddress0_re; - if (vns_csrbank3_dfii_pi3_wrdata3_re) begin - soc_sdram_phaseinjector3_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi3_wrdata3_r; - end - if (vns_csrbank3_dfii_pi3_wrdata2_re) begin - soc_sdram_phaseinjector3_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi3_wrdata2_r; - end - if (vns_csrbank3_dfii_pi3_wrdata1_re) begin - soc_sdram_phaseinjector3_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi3_wrdata1_r; - end - if (vns_csrbank3_dfii_pi3_wrdata0_re) begin - soc_sdram_phaseinjector3_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi3_wrdata0_r; - end - soc_sdram_phaseinjector3_wrdata_re <= vns_csrbank3_dfii_pi3_wrdata0_re; - vns_interface4_bank_bus_dat_r <= 1'd0; - if (vns_csrbank4_sel) begin - case (vns_interface4_bank_bus_adr[4:0]) - 1'd0: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_load3_w; - end - 1'd1: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_load2_w; - end - 2'd2: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_load1_w; - end - 2'd3: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_load0_w; - end - 3'd4: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload3_w; - end - 3'd5: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload2_w; - end - 3'd6: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload1_w; - end - 3'd7: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload0_w; - end - 4'd8: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_en0_w; - end - 4'd9: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_update_value0_w; - end - 4'd10: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_value3_w; - end - 4'd11: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_value2_w; - end - 4'd12: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_value1_w; - end - 4'd13: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_value0_w; - end - 4'd14: begin - vns_interface4_bank_bus_dat_r <= soc_litedramcore_timer_eventmanager_status_w; - end - 4'd15: begin - vns_interface4_bank_bus_dat_r <= soc_litedramcore_timer_eventmanager_pending_w; - end - 5'd16: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_ev_enable0_w; - end - endcase + if (csrbank2_dfii_pi1_wrdata2_re) begin + litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank2_dfii_pi1_wrdata2_r; end - if (vns_csrbank4_load3_re) begin - soc_litedramcore_timer_load_storage[31:24] <= vns_csrbank4_load3_r; + if (csrbank2_dfii_pi1_wrdata1_re) begin + litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank2_dfii_pi1_wrdata1_r; end - if (vns_csrbank4_load2_re) begin - soc_litedramcore_timer_load_storage[23:16] <= vns_csrbank4_load2_r; + if (csrbank2_dfii_pi1_wrdata0_re) begin + litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank2_dfii_pi1_wrdata0_r; end - if (vns_csrbank4_load1_re) begin - soc_litedramcore_timer_load_storage[15:8] <= vns_csrbank4_load1_r; + litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; + if (csrbank2_dfii_pi2_command0_re) begin + litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; end - if (vns_csrbank4_load0_re) begin - soc_litedramcore_timer_load_storage[7:0] <= vns_csrbank4_load0_r; + litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; + if (csrbank2_dfii_pi2_address1_re) begin + litedramcore_phaseinjector2_address_storage[13:8] <= csrbank2_dfii_pi2_address1_r; end - soc_litedramcore_timer_load_re <= vns_csrbank4_load0_re; - if (vns_csrbank4_reload3_re) begin - soc_litedramcore_timer_reload_storage[31:24] <= vns_csrbank4_reload3_r; + if (csrbank2_dfii_pi2_address0_re) begin + litedramcore_phaseinjector2_address_storage[7:0] <= csrbank2_dfii_pi2_address0_r; end - if (vns_csrbank4_reload2_re) begin - soc_litedramcore_timer_reload_storage[23:16] <= vns_csrbank4_reload2_r; + litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; + if (csrbank2_dfii_pi2_baddress0_re) begin + litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; end - if (vns_csrbank4_reload1_re) begin - soc_litedramcore_timer_reload_storage[15:8] <= vns_csrbank4_reload1_r; + litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; + if (csrbank2_dfii_pi2_wrdata3_re) begin + litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank2_dfii_pi2_wrdata3_r; end - if (vns_csrbank4_reload0_re) begin - soc_litedramcore_timer_reload_storage[7:0] <= vns_csrbank4_reload0_r; + if (csrbank2_dfii_pi2_wrdata2_re) begin + litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank2_dfii_pi2_wrdata2_r; end - soc_litedramcore_timer_reload_re <= vns_csrbank4_reload0_re; - if (vns_csrbank4_en0_re) begin - soc_litedramcore_timer_en_storage <= vns_csrbank4_en0_r; + if (csrbank2_dfii_pi2_wrdata1_re) begin + litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank2_dfii_pi2_wrdata1_r; end - soc_litedramcore_timer_en_re <= vns_csrbank4_en0_re; - if (vns_csrbank4_update_value0_re) begin - soc_litedramcore_timer_update_value_storage <= vns_csrbank4_update_value0_r; + if (csrbank2_dfii_pi2_wrdata0_re) begin + litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank2_dfii_pi2_wrdata0_r; end - soc_litedramcore_timer_update_value_re <= vns_csrbank4_update_value0_re; - if (vns_csrbank4_ev_enable0_re) begin - soc_litedramcore_timer_eventmanager_storage <= vns_csrbank4_ev_enable0_r; + litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; + if (csrbank2_dfii_pi3_command0_re) begin + litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; end - soc_litedramcore_timer_eventmanager_re <= vns_csrbank4_ev_enable0_re; - vns_interface5_bank_bus_dat_r <= 1'd0; - if (vns_csrbank5_sel) begin - case (vns_interface5_bank_bus_adr[2:0]) - 1'd0: begin - vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_rxtx_w; - end - 1'd1: begin - vns_interface5_bank_bus_dat_r <= vns_csrbank5_txfull_w; - end - 2'd2: begin - vns_interface5_bank_bus_dat_r <= vns_csrbank5_rxempty_w; - end - 2'd3: begin - vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_eventmanager_status_w; - end - 3'd4: begin - vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_eventmanager_pending_w; - end - 3'd5: begin - vns_interface5_bank_bus_dat_r <= vns_csrbank5_ev_enable0_w; - end - endcase + litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; + if (csrbank2_dfii_pi3_address1_re) begin + litedramcore_phaseinjector3_address_storage[13:8] <= csrbank2_dfii_pi3_address1_r; end - if (vns_csrbank5_ev_enable0_re) begin - soc_litedramcore_uart_eventmanager_storage[1:0] <= vns_csrbank5_ev_enable0_r; + if (csrbank2_dfii_pi3_address0_re) begin + litedramcore_phaseinjector3_address_storage[7:0] <= csrbank2_dfii_pi3_address0_r; end - soc_litedramcore_uart_eventmanager_re <= vns_csrbank5_ev_enable0_re; - vns_interface6_bank_bus_dat_r <= 1'd0; - if (vns_csrbank6_sel) begin - case (vns_interface6_bank_bus_adr[1:0]) - 1'd0: begin - vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word3_w; - end - 1'd1: begin - vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word2_w; - end - 2'd2: begin - vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word1_w; - end - 2'd3: begin - vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word0_w; - end - endcase + litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; + if (csrbank2_dfii_pi3_baddress0_re) begin + litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; end - if (vns_csrbank6_tuning_word3_re) begin - soc_litedramcore_storage[31:24] <= vns_csrbank6_tuning_word3_r; + litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; + if (csrbank2_dfii_pi3_wrdata3_re) begin + litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank2_dfii_pi3_wrdata3_r; end - if (vns_csrbank6_tuning_word2_re) begin - soc_litedramcore_storage[23:16] <= vns_csrbank6_tuning_word2_r; + if (csrbank2_dfii_pi3_wrdata2_re) begin + litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank2_dfii_pi3_wrdata2_r; end - if (vns_csrbank6_tuning_word1_re) begin - soc_litedramcore_storage[15:8] <= vns_csrbank6_tuning_word1_r; + if (csrbank2_dfii_pi3_wrdata1_re) begin + litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank2_dfii_pi3_wrdata1_r; end - if (vns_csrbank6_tuning_word0_re) begin - soc_litedramcore_storage[7:0] <= vns_csrbank6_tuning_word0_r; + if (csrbank2_dfii_pi3_wrdata0_re) begin + litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank2_dfii_pi3_wrdata0_r; end - soc_litedramcore_re <= vns_csrbank6_tuning_word0_re; + litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; if (sys_rst) begin - soc_litedramcore_soccontroller_reset_storage <= 1'd0; - soc_litedramcore_soccontroller_reset_re <= 1'd0; - soc_litedramcore_soccontroller_scratch_storage <= 32'd305419896; - soc_litedramcore_soccontroller_scratch_re <= 1'd0; - soc_litedramcore_soccontroller_bus_errors <= 32'd0; - soc_litedramcore_litedramcore_ram_bus_ack <= 1'd0; - soc_litedramcore_ram_bus_ram_bus_ack <= 1'd0; - serial_tx <= 1'd1; - soc_litedramcore_storage <= 32'd4947802; - soc_litedramcore_re <= 1'd0; - soc_litedramcore_sink_ready <= 1'd0; - soc_litedramcore_uart_clk_txen <= 1'd0; - soc_litedramcore_tx_busy <= 1'd0; - soc_litedramcore_source_valid <= 1'd0; - soc_litedramcore_uart_clk_rxen <= 1'd0; - soc_litedramcore_rx_r <= 1'd0; - soc_litedramcore_rx_busy <= 1'd0; - soc_litedramcore_uart_tx_pending <= 1'd0; - soc_litedramcore_uart_tx_old_trigger <= 1'd0; - soc_litedramcore_uart_rx_pending <= 1'd0; - soc_litedramcore_uart_rx_old_trigger <= 1'd0; - soc_litedramcore_uart_eventmanager_storage <= 2'd0; - soc_litedramcore_uart_eventmanager_re <= 1'd0; - soc_litedramcore_uart_tx_fifo_readable <= 1'd0; - soc_litedramcore_uart_tx_fifo_level0 <= 5'd0; - soc_litedramcore_uart_tx_fifo_produce <= 4'd0; - soc_litedramcore_uart_tx_fifo_consume <= 4'd0; - soc_litedramcore_uart_rx_fifo_readable <= 1'd0; - soc_litedramcore_uart_rx_fifo_level0 <= 5'd0; - soc_litedramcore_uart_rx_fifo_produce <= 4'd0; - soc_litedramcore_uart_rx_fifo_consume <= 4'd0; - soc_litedramcore_timer_load_storage <= 32'd0; - soc_litedramcore_timer_load_re <= 1'd0; - soc_litedramcore_timer_reload_storage <= 32'd0; - soc_litedramcore_timer_reload_re <= 1'd0; - soc_litedramcore_timer_en_storage <= 1'd0; - soc_litedramcore_timer_en_re <= 1'd0; - soc_litedramcore_timer_update_value_storage <= 1'd0; - soc_litedramcore_timer_update_value_re <= 1'd0; - soc_litedramcore_timer_value_status <= 32'd0; - soc_litedramcore_timer_zero_pending <= 1'd0; - soc_litedramcore_timer_zero_old_trigger <= 1'd0; - soc_litedramcore_timer_eventmanager_storage <= 1'd0; - soc_litedramcore_timer_eventmanager_re <= 1'd0; - soc_litedramcore_timer_value <= 32'd0; - soc_a7ddrphy_half_sys8x_taps_storage <= 5'd8; - soc_a7ddrphy_half_sys8x_taps_re <= 1'd0; - soc_a7ddrphy_wlevel_en_storage <= 1'd0; - soc_a7ddrphy_wlevel_en_re <= 1'd0; - soc_a7ddrphy_dly_sel_storage <= 2'd0; - soc_a7ddrphy_dly_sel_re <= 1'd0; - soc_a7ddrphy_dfi_p0_rddata_valid <= 1'd0; - soc_a7ddrphy_dfi_p1_rddata_valid <= 1'd0; - soc_a7ddrphy_dfi_p2_rddata_valid <= 1'd0; - soc_a7ddrphy_dfi_p3_rddata_valid <= 1'd0; - soc_a7ddrphy_dqs_oe_delayed <= 1'd0; - soc_a7ddrphy_dqspattern_o1 <= 8'd0; - soc_a7ddrphy_dq_oe_delayed <= 1'd0; - soc_a7ddrphy_bitslip0_value <= 3'd0; - soc_a7ddrphy_bitslip1_value <= 3'd0; - soc_a7ddrphy_bitslip2_value <= 3'd0; - soc_a7ddrphy_bitslip3_value <= 3'd0; - soc_a7ddrphy_bitslip4_value <= 3'd0; - soc_a7ddrphy_bitslip5_value <= 3'd0; - soc_a7ddrphy_bitslip6_value <= 3'd0; - soc_a7ddrphy_bitslip7_value <= 3'd0; - soc_a7ddrphy_bitslip8_value <= 3'd0; - soc_a7ddrphy_bitslip9_value <= 3'd0; - soc_a7ddrphy_bitslip10_value <= 3'd0; - soc_a7ddrphy_bitslip11_value <= 3'd0; - soc_a7ddrphy_bitslip12_value <= 3'd0; - soc_a7ddrphy_bitslip13_value <= 3'd0; - soc_a7ddrphy_bitslip14_value <= 3'd0; - soc_a7ddrphy_bitslip15_value <= 3'd0; - soc_a7ddrphy_rddata_en_last <= 8'd0; - soc_a7ddrphy_wrdata_en_last <= 4'd0; - soc_sdram_storage <= 4'd0; - soc_sdram_re <= 1'd0; - soc_sdram_phaseinjector0_command_storage <= 6'd0; - soc_sdram_phaseinjector0_command_re <= 1'd0; - soc_sdram_phaseinjector0_address_re <= 1'd0; - soc_sdram_phaseinjector0_baddress_re <= 1'd0; - soc_sdram_phaseinjector0_wrdata_re <= 1'd0; - soc_sdram_phaseinjector0_status <= 32'd0; - soc_sdram_phaseinjector1_command_storage <= 6'd0; - soc_sdram_phaseinjector1_command_re <= 1'd0; - soc_sdram_phaseinjector1_address_re <= 1'd0; - soc_sdram_phaseinjector1_baddress_re <= 1'd0; - soc_sdram_phaseinjector1_wrdata_re <= 1'd0; - soc_sdram_phaseinjector1_status <= 32'd0; - soc_sdram_phaseinjector2_command_storage <= 6'd0; - soc_sdram_phaseinjector2_command_re <= 1'd0; - soc_sdram_phaseinjector2_address_re <= 1'd0; - soc_sdram_phaseinjector2_baddress_re <= 1'd0; - soc_sdram_phaseinjector2_wrdata_re <= 1'd0; - soc_sdram_phaseinjector2_status <= 32'd0; - soc_sdram_phaseinjector3_command_storage <= 6'd0; - soc_sdram_phaseinjector3_command_re <= 1'd0; - soc_sdram_phaseinjector3_address_re <= 1'd0; - soc_sdram_phaseinjector3_baddress_re <= 1'd0; - soc_sdram_phaseinjector3_wrdata_re <= 1'd0; - soc_sdram_phaseinjector3_status <= 32'd0; - soc_sdram_dfi_p0_address <= 14'd0; - soc_sdram_dfi_p0_bank <= 3'd0; - soc_sdram_dfi_p0_cas_n <= 1'd1; - soc_sdram_dfi_p0_cs_n <= 1'd1; - soc_sdram_dfi_p0_ras_n <= 1'd1; - soc_sdram_dfi_p0_we_n <= 1'd1; - soc_sdram_dfi_p0_wrdata_en <= 1'd0; - soc_sdram_dfi_p0_rddata_en <= 1'd0; - soc_sdram_dfi_p1_address <= 14'd0; - soc_sdram_dfi_p1_bank <= 3'd0; - soc_sdram_dfi_p1_cas_n <= 1'd1; - soc_sdram_dfi_p1_cs_n <= 1'd1; - soc_sdram_dfi_p1_ras_n <= 1'd1; - soc_sdram_dfi_p1_we_n <= 1'd1; - soc_sdram_dfi_p1_wrdata_en <= 1'd0; - soc_sdram_dfi_p1_rddata_en <= 1'd0; - soc_sdram_dfi_p2_address <= 14'd0; - soc_sdram_dfi_p2_bank <= 3'd0; - soc_sdram_dfi_p2_cas_n <= 1'd1; - soc_sdram_dfi_p2_cs_n <= 1'd1; - soc_sdram_dfi_p2_ras_n <= 1'd1; - soc_sdram_dfi_p2_we_n <= 1'd1; - soc_sdram_dfi_p2_wrdata_en <= 1'd0; - soc_sdram_dfi_p2_rddata_en <= 1'd0; - soc_sdram_dfi_p3_address <= 14'd0; - soc_sdram_dfi_p3_bank <= 3'd0; - soc_sdram_dfi_p3_cas_n <= 1'd1; - soc_sdram_dfi_p3_cs_n <= 1'd1; - soc_sdram_dfi_p3_ras_n <= 1'd1; - soc_sdram_dfi_p3_we_n <= 1'd1; - soc_sdram_dfi_p3_wrdata_en <= 1'd0; - soc_sdram_dfi_p3_rddata_en <= 1'd0; - soc_sdram_timer_count1 <= 10'd781; - soc_sdram_postponer_req_o <= 1'd0; - soc_sdram_postponer_count <= 1'd0; - soc_sdram_sequencer_done1 <= 1'd0; - soc_sdram_sequencer_counter <= 6'd0; - soc_sdram_sequencer_count <= 1'd0; - soc_sdram_zqcs_timer_count1 <= 27'd99999999; - soc_sdram_zqcs_executer_done <= 1'd0; - soc_sdram_zqcs_executer_counter <= 5'd0; - soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; - soc_sdram_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; - soc_sdram_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; - soc_sdram_bankmachine0_cmd_buffer_source_valid <= 1'd0; - soc_sdram_bankmachine0_row <= 14'd0; - soc_sdram_bankmachine0_row_opened <= 1'd0; - soc_sdram_bankmachine0_twtpcon_ready <= 1'd1; - soc_sdram_bankmachine0_twtpcon_count <= 3'd0; - soc_sdram_bankmachine0_trccon_ready <= 1'd1; - soc_sdram_bankmachine0_trccon_count <= 3'd0; - soc_sdram_bankmachine0_trascon_ready <= 1'd1; - soc_sdram_bankmachine0_trascon_count <= 3'd0; - soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; - soc_sdram_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; - soc_sdram_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; - soc_sdram_bankmachine1_cmd_buffer_source_valid <= 1'd0; - soc_sdram_bankmachine1_row <= 14'd0; - soc_sdram_bankmachine1_row_opened <= 1'd0; - soc_sdram_bankmachine1_twtpcon_ready <= 1'd1; - soc_sdram_bankmachine1_twtpcon_count <= 3'd0; - soc_sdram_bankmachine1_trccon_ready <= 1'd1; - soc_sdram_bankmachine1_trccon_count <= 3'd0; - soc_sdram_bankmachine1_trascon_ready <= 1'd1; - soc_sdram_bankmachine1_trascon_count <= 3'd0; - soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; - soc_sdram_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; - soc_sdram_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; - soc_sdram_bankmachine2_cmd_buffer_source_valid <= 1'd0; - soc_sdram_bankmachine2_row <= 14'd0; - soc_sdram_bankmachine2_row_opened <= 1'd0; - soc_sdram_bankmachine2_twtpcon_ready <= 1'd1; - soc_sdram_bankmachine2_twtpcon_count <= 3'd0; - soc_sdram_bankmachine2_trccon_ready <= 1'd1; - soc_sdram_bankmachine2_trccon_count <= 3'd0; - soc_sdram_bankmachine2_trascon_ready <= 1'd1; - soc_sdram_bankmachine2_trascon_count <= 3'd0; - soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; - soc_sdram_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; - soc_sdram_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; - soc_sdram_bankmachine3_cmd_buffer_source_valid <= 1'd0; - soc_sdram_bankmachine3_row <= 14'd0; - soc_sdram_bankmachine3_row_opened <= 1'd0; - soc_sdram_bankmachine3_twtpcon_ready <= 1'd1; - soc_sdram_bankmachine3_twtpcon_count <= 3'd0; - soc_sdram_bankmachine3_trccon_ready <= 1'd1; - soc_sdram_bankmachine3_trccon_count <= 3'd0; - soc_sdram_bankmachine3_trascon_ready <= 1'd1; - soc_sdram_bankmachine3_trascon_count <= 3'd0; - soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; - soc_sdram_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; - soc_sdram_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; - soc_sdram_bankmachine4_cmd_buffer_source_valid <= 1'd0; - soc_sdram_bankmachine4_row <= 14'd0; - soc_sdram_bankmachine4_row_opened <= 1'd0; - soc_sdram_bankmachine4_twtpcon_ready <= 1'd1; - soc_sdram_bankmachine4_twtpcon_count <= 3'd0; - soc_sdram_bankmachine4_trccon_ready <= 1'd1; - soc_sdram_bankmachine4_trccon_count <= 3'd0; - soc_sdram_bankmachine4_trascon_ready <= 1'd1; - soc_sdram_bankmachine4_trascon_count <= 3'd0; - soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; - soc_sdram_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; - soc_sdram_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; - soc_sdram_bankmachine5_cmd_buffer_source_valid <= 1'd0; - soc_sdram_bankmachine5_row <= 14'd0; - soc_sdram_bankmachine5_row_opened <= 1'd0; - soc_sdram_bankmachine5_twtpcon_ready <= 1'd1; - soc_sdram_bankmachine5_twtpcon_count <= 3'd0; - soc_sdram_bankmachine5_trccon_ready <= 1'd1; - soc_sdram_bankmachine5_trccon_count <= 3'd0; - soc_sdram_bankmachine5_trascon_ready <= 1'd1; - soc_sdram_bankmachine5_trascon_count <= 3'd0; - soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; - soc_sdram_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; - soc_sdram_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; - soc_sdram_bankmachine6_cmd_buffer_source_valid <= 1'd0; - soc_sdram_bankmachine6_row <= 14'd0; - soc_sdram_bankmachine6_row_opened <= 1'd0; - soc_sdram_bankmachine6_twtpcon_ready <= 1'd1; - soc_sdram_bankmachine6_twtpcon_count <= 3'd0; - soc_sdram_bankmachine6_trccon_ready <= 1'd1; - soc_sdram_bankmachine6_trccon_count <= 3'd0; - soc_sdram_bankmachine6_trascon_ready <= 1'd1; - soc_sdram_bankmachine6_trascon_count <= 3'd0; - soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; - soc_sdram_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; - soc_sdram_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; - soc_sdram_bankmachine7_cmd_buffer_source_valid <= 1'd0; - soc_sdram_bankmachine7_row <= 14'd0; - soc_sdram_bankmachine7_row_opened <= 1'd0; - soc_sdram_bankmachine7_twtpcon_ready <= 1'd1; - soc_sdram_bankmachine7_twtpcon_count <= 3'd0; - soc_sdram_bankmachine7_trccon_ready <= 1'd1; - soc_sdram_bankmachine7_trccon_count <= 3'd0; - soc_sdram_bankmachine7_trascon_ready <= 1'd1; - soc_sdram_bankmachine7_trascon_count <= 3'd0; - soc_sdram_choose_cmd_grant <= 3'd0; - soc_sdram_choose_req_grant <= 3'd0; - soc_sdram_trrdcon_ready <= 1'd1; - soc_sdram_trrdcon_count <= 1'd0; - soc_sdram_tfawcon_ready <= 1'd1; - soc_sdram_tfawcon_window <= 5'd0; - soc_sdram_tccdcon_ready <= 1'd1; - soc_sdram_tccdcon_count <= 1'd0; - soc_sdram_twtrcon_ready <= 1'd1; - soc_sdram_twtrcon_count <= 3'd0; - soc_sdram_time0 <= 5'd0; - soc_sdram_time1 <= 4'd0; - soc_address_q <= 30'd0; - soc_counter <= 2'd0; - soc_need_refill_q <= 1'd1; - soc_cached_datas_flipflop0_q <= 32'd0; - soc_cached_datas_flipflop1_q <= 32'd0; - soc_cached_datas_flipflop2_q <= 32'd0; - soc_cached_datas_flipflop3_q <= 32'd0; - soc_cached_sels_flipflop0_q <= 4'd0; - soc_cached_sels_flipflop1_q <= 4'd0; - soc_cached_sels_flipflop2_q <= 4'd0; - soc_cached_sels_flipflop3_q <= 4'd0; - soc_count <= 1'd0; - soc_init_done_storage <= 1'd0; - soc_init_done_re <= 1'd0; - soc_init_error_storage <= 1'd0; - soc_init_error_re <= 1'd0; - vns_wb2csr_state <= 1'd0; - vns_refresher_state <= 2'd0; - vns_bankmachine0_state <= 4'd0; - vns_bankmachine1_state <= 4'd0; - vns_bankmachine2_state <= 4'd0; - vns_bankmachine3_state <= 4'd0; - vns_bankmachine4_state <= 4'd0; - vns_bankmachine5_state <= 4'd0; - vns_bankmachine6_state <= 4'd0; - vns_bankmachine7_state <= 4'd0; - vns_multiplexer_state <= 4'd0; - vns_roundrobin0_grant <= 1'd0; - vns_roundrobin1_grant <= 1'd0; - vns_roundrobin2_grant <= 1'd0; - vns_roundrobin3_grant <= 1'd0; - vns_roundrobin4_grant <= 1'd0; - vns_roundrobin5_grant <= 1'd0; - vns_roundrobin6_grant <= 1'd0; - vns_roundrobin7_grant <= 1'd0; - vns_new_master_wdata_ready0 <= 1'd0; - vns_new_master_wdata_ready1 <= 1'd0; - vns_new_master_wdata_ready2 <= 1'd0; - vns_new_master_wdata_ready3 <= 1'd0; - vns_new_master_wdata_ready4 <= 1'd0; - vns_new_master_wdata_ready5 <= 1'd0; - vns_new_master_rdata_valid0 <= 1'd0; - vns_new_master_rdata_valid1 <= 1'd0; - vns_new_master_rdata_valid2 <= 1'd0; - vns_new_master_rdata_valid3 <= 1'd0; - vns_new_master_rdata_valid4 <= 1'd0; - vns_new_master_rdata_valid5 <= 1'd0; - vns_new_master_rdata_valid6 <= 1'd0; - vns_new_master_rdata_valid7 <= 1'd0; - vns_new_master_rdata_valid8 <= 1'd0; - vns_new_master_rdata_valid9 <= 1'd0; - vns_new_master_rdata_valid10 <= 1'd0; - vns_new_master_rdata_valid11 <= 1'd0; - vns_new_master_rdata_valid12 <= 1'd0; - vns_new_master_rdata_valid13 <= 1'd0; - vns_new_master_rdata_valid14 <= 1'd0; - vns_new_master_rdata_valid15 <= 1'd0; - vns_new_master_rdata_valid16 <= 1'd0; - vns_new_master_rdata_valid17 <= 1'd0; - vns_converter_state <= 3'd0; - vns_litedramwishbone2native_state <= 2'd0; - vns_grant <= 1'd0; - vns_slave_sel_r <= 4'd0; - vns_count <= 20'd1000000; - end - vns_regs0 <= serial_rx; - vns_regs1 <= vns_regs0; -end - -reg [31:0] mem[0:6143]; -reg [31:0] memdat; -always @(posedge sys_clk) begin - memdat <= mem[soc_litedramcore_litedramcore_adr]; -end - -assign soc_litedramcore_litedramcore_dat_r = memdat; - -initial begin - $readmemh("litedram_core.init", mem); -end - -reg [31:0] mem_1[0:1023]; -reg [9:0] memadr; -always @(posedge sys_clk) begin - if (soc_litedramcore_ram_we[0]) - mem_1[soc_litedramcore_ram_adr][7:0] <= soc_litedramcore_ram_dat_w[7:0]; - if (soc_litedramcore_ram_we[1]) - mem_1[soc_litedramcore_ram_adr][15:8] <= soc_litedramcore_ram_dat_w[15:8]; - if (soc_litedramcore_ram_we[2]) - mem_1[soc_litedramcore_ram_adr][23:16] <= soc_litedramcore_ram_dat_w[23:16]; - if (soc_litedramcore_ram_we[3]) - mem_1[soc_litedramcore_ram_adr][31:24] <= soc_litedramcore_ram_dat_w[31:24]; - memadr <= soc_litedramcore_ram_adr; -end - -assign soc_litedramcore_ram_dat_r = mem_1[memadr]; - -initial begin - $readmemh("mem_1.init", mem_1); -end - -reg [9:0] storage[0:15]; -reg [9:0] memdat_1; -reg [9:0] memdat_2; -always @(posedge sys_clk) begin - if (soc_litedramcore_uart_tx_fifo_wrport_we) - storage[soc_litedramcore_uart_tx_fifo_wrport_adr] <= soc_litedramcore_uart_tx_fifo_wrport_dat_w; - memdat_1 <= storage[soc_litedramcore_uart_tx_fifo_wrport_adr]; -end - -always @(posedge sys_clk) begin - if (soc_litedramcore_uart_tx_fifo_rdport_re) - memdat_2 <= storage[soc_litedramcore_uart_tx_fifo_rdport_adr]; -end - -assign soc_litedramcore_uart_tx_fifo_wrport_dat_r = memdat_1; -assign soc_litedramcore_uart_tx_fifo_rdport_dat_r = memdat_2; - -reg [9:0] storage_1[0:15]; -reg [9:0] memdat_3; -reg [9:0] memdat_4; -always @(posedge sys_clk) begin - if (soc_litedramcore_uart_rx_fifo_wrport_we) - storage_1[soc_litedramcore_uart_rx_fifo_wrport_adr] <= soc_litedramcore_uart_rx_fifo_wrport_dat_w; - memdat_3 <= storage_1[soc_litedramcore_uart_rx_fifo_wrport_adr]; -end - -always @(posedge sys_clk) begin - if (soc_litedramcore_uart_rx_fifo_rdport_re) - memdat_4 <= storage_1[soc_litedramcore_uart_rx_fifo_rdport_adr]; + a7ddrphy_half_sys8x_taps_storage <= 5'd8; + a7ddrphy_half_sys8x_taps_re <= 1'd0; + a7ddrphy_wlevel_en_storage <= 1'd0; + a7ddrphy_wlevel_en_re <= 1'd0; + a7ddrphy_dly_sel_storage <= 2'd0; + a7ddrphy_dly_sel_re <= 1'd0; + a7ddrphy_dfi_p0_rddata_valid <= 1'd0; + a7ddrphy_dfi_p1_rddata_valid <= 1'd0; + a7ddrphy_dfi_p2_rddata_valid <= 1'd0; + a7ddrphy_dfi_p3_rddata_valid <= 1'd0; + a7ddrphy_dqs_oe_delayed <= 1'd0; + a7ddrphy_dqspattern_o1 <= 8'd0; + a7ddrphy_dq_oe_delayed <= 1'd0; + a7ddrphy_bitslip0_value <= 3'd0; + a7ddrphy_bitslip1_value <= 3'd0; + a7ddrphy_bitslip2_value <= 3'd0; + a7ddrphy_bitslip3_value <= 3'd0; + a7ddrphy_bitslip4_value <= 3'd0; + a7ddrphy_bitslip5_value <= 3'd0; + a7ddrphy_bitslip6_value <= 3'd0; + a7ddrphy_bitslip7_value <= 3'd0; + a7ddrphy_bitslip8_value <= 3'd0; + a7ddrphy_bitslip9_value <= 3'd0; + a7ddrphy_bitslip10_value <= 3'd0; + a7ddrphy_bitslip11_value <= 3'd0; + a7ddrphy_bitslip12_value <= 3'd0; + a7ddrphy_bitslip13_value <= 3'd0; + a7ddrphy_bitslip14_value <= 3'd0; + a7ddrphy_bitslip15_value <= 3'd0; + a7ddrphy_rddata_en_last <= 8'd0; + a7ddrphy_wrdata_en_last <= 4'd0; + litedramcore_storage <= 4'd0; + litedramcore_re <= 1'd0; + litedramcore_phaseinjector0_command_storage <= 6'd0; + litedramcore_phaseinjector0_command_re <= 1'd0; + litedramcore_phaseinjector0_address_re <= 1'd0; + litedramcore_phaseinjector0_baddress_re <= 1'd0; + litedramcore_phaseinjector0_wrdata_re <= 1'd0; + litedramcore_phaseinjector0_status <= 32'd0; + litedramcore_phaseinjector1_command_storage <= 6'd0; + litedramcore_phaseinjector1_command_re <= 1'd0; + litedramcore_phaseinjector1_address_re <= 1'd0; + litedramcore_phaseinjector1_baddress_re <= 1'd0; + litedramcore_phaseinjector1_wrdata_re <= 1'd0; + litedramcore_phaseinjector1_status <= 32'd0; + litedramcore_phaseinjector2_command_storage <= 6'd0; + litedramcore_phaseinjector2_command_re <= 1'd0; + litedramcore_phaseinjector2_address_re <= 1'd0; + litedramcore_phaseinjector2_baddress_re <= 1'd0; + litedramcore_phaseinjector2_wrdata_re <= 1'd0; + litedramcore_phaseinjector2_status <= 32'd0; + litedramcore_phaseinjector3_command_storage <= 6'd0; + litedramcore_phaseinjector3_command_re <= 1'd0; + litedramcore_phaseinjector3_address_re <= 1'd0; + litedramcore_phaseinjector3_baddress_re <= 1'd0; + litedramcore_phaseinjector3_wrdata_re <= 1'd0; + litedramcore_phaseinjector3_status <= 32'd0; + litedramcore_dfi_p0_address <= 14'd0; + litedramcore_dfi_p0_bank <= 3'd0; + litedramcore_dfi_p0_cas_n <= 1'd1; + litedramcore_dfi_p0_cs_n <= 1'd1; + litedramcore_dfi_p0_ras_n <= 1'd1; + litedramcore_dfi_p0_we_n <= 1'd1; + litedramcore_dfi_p0_wrdata_en <= 1'd0; + litedramcore_dfi_p0_rddata_en <= 1'd0; + litedramcore_dfi_p1_address <= 14'd0; + litedramcore_dfi_p1_bank <= 3'd0; + litedramcore_dfi_p1_cas_n <= 1'd1; + litedramcore_dfi_p1_cs_n <= 1'd1; + litedramcore_dfi_p1_ras_n <= 1'd1; + litedramcore_dfi_p1_we_n <= 1'd1; + litedramcore_dfi_p1_wrdata_en <= 1'd0; + litedramcore_dfi_p1_rddata_en <= 1'd0; + litedramcore_dfi_p2_address <= 14'd0; + litedramcore_dfi_p2_bank <= 3'd0; + litedramcore_dfi_p2_cas_n <= 1'd1; + litedramcore_dfi_p2_cs_n <= 1'd1; + litedramcore_dfi_p2_ras_n <= 1'd1; + litedramcore_dfi_p2_we_n <= 1'd1; + litedramcore_dfi_p2_wrdata_en <= 1'd0; + litedramcore_dfi_p2_rddata_en <= 1'd0; + litedramcore_dfi_p3_address <= 14'd0; + litedramcore_dfi_p3_bank <= 3'd0; + litedramcore_dfi_p3_cas_n <= 1'd1; + litedramcore_dfi_p3_cs_n <= 1'd1; + litedramcore_dfi_p3_ras_n <= 1'd1; + litedramcore_dfi_p3_we_n <= 1'd1; + litedramcore_dfi_p3_wrdata_en <= 1'd0; + litedramcore_dfi_p3_rddata_en <= 1'd0; + litedramcore_timer_count1 <= 10'd781; + litedramcore_postponer_req_o <= 1'd0; + litedramcore_postponer_count <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + litedramcore_sequencer_counter <= 6'd0; + litedramcore_sequencer_count <= 1'd0; + litedramcore_zqcs_timer_count1 <= 27'd99999999; + litedramcore_zqcs_executer_done <= 1'd0; + litedramcore_zqcs_executer_counter <= 5'd0; + litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine0_row <= 14'd0; + litedramcore_bankmachine0_row_opened <= 1'd0; + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + litedramcore_bankmachine0_twtpcon_count <= 3'd0; + litedramcore_bankmachine0_trccon_ready <= 1'd1; + litedramcore_bankmachine0_trccon_count <= 3'd0; + litedramcore_bankmachine0_trascon_ready <= 1'd1; + litedramcore_bankmachine0_trascon_count <= 3'd0; + litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine1_row <= 14'd0; + litedramcore_bankmachine1_row_opened <= 1'd0; + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + litedramcore_bankmachine1_twtpcon_count <= 3'd0; + litedramcore_bankmachine1_trccon_ready <= 1'd1; + litedramcore_bankmachine1_trccon_count <= 3'd0; + litedramcore_bankmachine1_trascon_ready <= 1'd1; + litedramcore_bankmachine1_trascon_count <= 3'd0; + litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine2_row <= 14'd0; + litedramcore_bankmachine2_row_opened <= 1'd0; + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + litedramcore_bankmachine2_twtpcon_count <= 3'd0; + litedramcore_bankmachine2_trccon_ready <= 1'd1; + litedramcore_bankmachine2_trccon_count <= 3'd0; + litedramcore_bankmachine2_trascon_ready <= 1'd1; + litedramcore_bankmachine2_trascon_count <= 3'd0; + litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine3_row <= 14'd0; + litedramcore_bankmachine3_row_opened <= 1'd0; + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + litedramcore_bankmachine3_twtpcon_count <= 3'd0; + litedramcore_bankmachine3_trccon_ready <= 1'd1; + litedramcore_bankmachine3_trccon_count <= 3'd0; + litedramcore_bankmachine3_trascon_ready <= 1'd1; + litedramcore_bankmachine3_trascon_count <= 3'd0; + litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine4_row <= 14'd0; + litedramcore_bankmachine4_row_opened <= 1'd0; + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + litedramcore_bankmachine4_twtpcon_count <= 3'd0; + litedramcore_bankmachine4_trccon_ready <= 1'd1; + litedramcore_bankmachine4_trccon_count <= 3'd0; + litedramcore_bankmachine4_trascon_ready <= 1'd1; + litedramcore_bankmachine4_trascon_count <= 3'd0; + litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine5_row <= 14'd0; + litedramcore_bankmachine5_row_opened <= 1'd0; + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + litedramcore_bankmachine5_twtpcon_count <= 3'd0; + litedramcore_bankmachine5_trccon_ready <= 1'd1; + litedramcore_bankmachine5_trccon_count <= 3'd0; + litedramcore_bankmachine5_trascon_ready <= 1'd1; + litedramcore_bankmachine5_trascon_count <= 3'd0; + litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine6_row <= 14'd0; + litedramcore_bankmachine6_row_opened <= 1'd0; + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + litedramcore_bankmachine6_twtpcon_count <= 3'd0; + litedramcore_bankmachine6_trccon_ready <= 1'd1; + litedramcore_bankmachine6_trccon_count <= 3'd0; + litedramcore_bankmachine6_trascon_ready <= 1'd1; + litedramcore_bankmachine6_trascon_count <= 3'd0; + litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine7_row <= 14'd0; + litedramcore_bankmachine7_row_opened <= 1'd0; + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + litedramcore_bankmachine7_twtpcon_count <= 3'd0; + litedramcore_bankmachine7_trccon_ready <= 1'd1; + litedramcore_bankmachine7_trccon_count <= 3'd0; + litedramcore_bankmachine7_trascon_ready <= 1'd1; + litedramcore_bankmachine7_trascon_count <= 3'd0; + litedramcore_choose_cmd_grant <= 3'd0; + litedramcore_choose_req_grant <= 3'd0; + litedramcore_trrdcon_ready <= 1'd1; + litedramcore_trrdcon_count <= 1'd0; + litedramcore_tfawcon_ready <= 1'd1; + litedramcore_tfawcon_window <= 5'd0; + litedramcore_tccdcon_ready <= 1'd1; + litedramcore_tccdcon_count <= 1'd0; + litedramcore_twtrcon_ready <= 1'd1; + litedramcore_twtrcon_count <= 3'd0; + litedramcore_time0 <= 5'd0; + litedramcore_time1 <= 4'd0; + init_done_storage <= 1'd0; + init_done_re <= 1'd0; + init_error_storage <= 1'd0; + init_error_re <= 1'd0; + refresher_state <= 2'd0; + bankmachine0_state <= 4'd0; + bankmachine1_state <= 4'd0; + bankmachine2_state <= 4'd0; + bankmachine3_state <= 4'd0; + bankmachine4_state <= 4'd0; + bankmachine5_state <= 4'd0; + bankmachine6_state <= 4'd0; + bankmachine7_state <= 4'd0; + multiplexer_state <= 4'd0; + new_master_wdata_ready0 <= 1'd0; + new_master_wdata_ready1 <= 1'd0; + new_master_wdata_ready2 <= 1'd0; + new_master_rdata_valid0 <= 1'd0; + new_master_rdata_valid1 <= 1'd0; + new_master_rdata_valid2 <= 1'd0; + new_master_rdata_valid3 <= 1'd0; + new_master_rdata_valid4 <= 1'd0; + new_master_rdata_valid5 <= 1'd0; + new_master_rdata_valid6 <= 1'd0; + new_master_rdata_valid7 <= 1'd0; + new_master_rdata_valid8 <= 1'd0; + end end -assign soc_litedramcore_uart_rx_fifo_wrport_dat_r = memdat_3; -assign soc_litedramcore_uart_rx_fifo_rdport_dat_r = memdat_4; - BUFG BUFG( - .I(soc_s7pll0_clkout0), - .O(soc_s7pll0_clkout_buf0) + .I(s7pll0_clkout0), + .O(s7pll0_clkout_buf0) ); BUFG BUFG_1( - .I(soc_s7pll0_clkout1), - .O(soc_s7pll0_clkout_buf1) + .I(s7pll0_clkout1), + .O(s7pll0_clkout_buf1) ); BUFG BUFG_2( - .I(soc_s7pll0_clkout2), - .O(soc_s7pll0_clkout_buf2) + .I(s7pll0_clkout2), + .O(s7pll0_clkout_buf2) ); BUFG BUFG_3( - .I(soc_s7pll1_clkout), - .O(soc_s7pll1_clkout_buf) + .I(s7pll1_clkout), + .O(s7pll1_clkout_buf) ); IDELAYCTRL IDELAYCTRL( .REFCLK(iodelay_clk), - .RST(soc_ic_reset) + .RST(ic_reset) ); OSERDESE2 #( @@ -17734,11 +14783,11 @@ OSERDESE2 #( .D8(1'd1), .OCE(1'd1), .RST(sys_rst), - .OQ(soc_a7ddrphy_sd_clk_se_nodelay) + .OQ(a7ddrphy_sd_clk_se_nodelay) ); OBUFDS OBUFDS( - .I(soc_a7ddrphy_sd_clk_se_nodelay), + .I(a7ddrphy_sd_clk_se_nodelay), .O(ddram_clk_p), .OB(ddram_clk_n) ); @@ -17752,14 +14801,14 @@ OSERDESE2 #( ) OSERDESE2_1 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[0]), - .D2(soc_a7ddrphy_dfi_p0_address[0]), - .D3(soc_a7ddrphy_dfi_p1_address[0]), - .D4(soc_a7ddrphy_dfi_p1_address[0]), - .D5(soc_a7ddrphy_dfi_p2_address[0]), - .D6(soc_a7ddrphy_dfi_p2_address[0]), - .D7(soc_a7ddrphy_dfi_p3_address[0]), - .D8(soc_a7ddrphy_dfi_p3_address[0]), + .D1(a7ddrphy_dfi_p0_address[0]), + .D2(a7ddrphy_dfi_p0_address[0]), + .D3(a7ddrphy_dfi_p1_address[0]), + .D4(a7ddrphy_dfi_p1_address[0]), + .D5(a7ddrphy_dfi_p2_address[0]), + .D6(a7ddrphy_dfi_p2_address[0]), + .D7(a7ddrphy_dfi_p3_address[0]), + .D8(a7ddrphy_dfi_p3_address[0]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[0]) @@ -17774,14 +14823,14 @@ OSERDESE2 #( ) OSERDESE2_2 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[1]), - .D2(soc_a7ddrphy_dfi_p0_address[1]), - .D3(soc_a7ddrphy_dfi_p1_address[1]), - .D4(soc_a7ddrphy_dfi_p1_address[1]), - .D5(soc_a7ddrphy_dfi_p2_address[1]), - .D6(soc_a7ddrphy_dfi_p2_address[1]), - .D7(soc_a7ddrphy_dfi_p3_address[1]), - .D8(soc_a7ddrphy_dfi_p3_address[1]), + .D1(a7ddrphy_dfi_p0_address[1]), + .D2(a7ddrphy_dfi_p0_address[1]), + .D3(a7ddrphy_dfi_p1_address[1]), + .D4(a7ddrphy_dfi_p1_address[1]), + .D5(a7ddrphy_dfi_p2_address[1]), + .D6(a7ddrphy_dfi_p2_address[1]), + .D7(a7ddrphy_dfi_p3_address[1]), + .D8(a7ddrphy_dfi_p3_address[1]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[1]) @@ -17796,14 +14845,14 @@ OSERDESE2 #( ) OSERDESE2_3 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[2]), - .D2(soc_a7ddrphy_dfi_p0_address[2]), - .D3(soc_a7ddrphy_dfi_p1_address[2]), - .D4(soc_a7ddrphy_dfi_p1_address[2]), - .D5(soc_a7ddrphy_dfi_p2_address[2]), - .D6(soc_a7ddrphy_dfi_p2_address[2]), - .D7(soc_a7ddrphy_dfi_p3_address[2]), - .D8(soc_a7ddrphy_dfi_p3_address[2]), + .D1(a7ddrphy_dfi_p0_address[2]), + .D2(a7ddrphy_dfi_p0_address[2]), + .D3(a7ddrphy_dfi_p1_address[2]), + .D4(a7ddrphy_dfi_p1_address[2]), + .D5(a7ddrphy_dfi_p2_address[2]), + .D6(a7ddrphy_dfi_p2_address[2]), + .D7(a7ddrphy_dfi_p3_address[2]), + .D8(a7ddrphy_dfi_p3_address[2]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[2]) @@ -17818,14 +14867,14 @@ OSERDESE2 #( ) OSERDESE2_4 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[3]), - .D2(soc_a7ddrphy_dfi_p0_address[3]), - .D3(soc_a7ddrphy_dfi_p1_address[3]), - .D4(soc_a7ddrphy_dfi_p1_address[3]), - .D5(soc_a7ddrphy_dfi_p2_address[3]), - .D6(soc_a7ddrphy_dfi_p2_address[3]), - .D7(soc_a7ddrphy_dfi_p3_address[3]), - .D8(soc_a7ddrphy_dfi_p3_address[3]), + .D1(a7ddrphy_dfi_p0_address[3]), + .D2(a7ddrphy_dfi_p0_address[3]), + .D3(a7ddrphy_dfi_p1_address[3]), + .D4(a7ddrphy_dfi_p1_address[3]), + .D5(a7ddrphy_dfi_p2_address[3]), + .D6(a7ddrphy_dfi_p2_address[3]), + .D7(a7ddrphy_dfi_p3_address[3]), + .D8(a7ddrphy_dfi_p3_address[3]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[3]) @@ -17840,14 +14889,14 @@ OSERDESE2 #( ) OSERDESE2_5 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[4]), - .D2(soc_a7ddrphy_dfi_p0_address[4]), - .D3(soc_a7ddrphy_dfi_p1_address[4]), - .D4(soc_a7ddrphy_dfi_p1_address[4]), - .D5(soc_a7ddrphy_dfi_p2_address[4]), - .D6(soc_a7ddrphy_dfi_p2_address[4]), - .D7(soc_a7ddrphy_dfi_p3_address[4]), - .D8(soc_a7ddrphy_dfi_p3_address[4]), + .D1(a7ddrphy_dfi_p0_address[4]), + .D2(a7ddrphy_dfi_p0_address[4]), + .D3(a7ddrphy_dfi_p1_address[4]), + .D4(a7ddrphy_dfi_p1_address[4]), + .D5(a7ddrphy_dfi_p2_address[4]), + .D6(a7ddrphy_dfi_p2_address[4]), + .D7(a7ddrphy_dfi_p3_address[4]), + .D8(a7ddrphy_dfi_p3_address[4]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[4]) @@ -17862,14 +14911,14 @@ OSERDESE2 #( ) OSERDESE2_6 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[5]), - .D2(soc_a7ddrphy_dfi_p0_address[5]), - .D3(soc_a7ddrphy_dfi_p1_address[5]), - .D4(soc_a7ddrphy_dfi_p1_address[5]), - .D5(soc_a7ddrphy_dfi_p2_address[5]), - .D6(soc_a7ddrphy_dfi_p2_address[5]), - .D7(soc_a7ddrphy_dfi_p3_address[5]), - .D8(soc_a7ddrphy_dfi_p3_address[5]), + .D1(a7ddrphy_dfi_p0_address[5]), + .D2(a7ddrphy_dfi_p0_address[5]), + .D3(a7ddrphy_dfi_p1_address[5]), + .D4(a7ddrphy_dfi_p1_address[5]), + .D5(a7ddrphy_dfi_p2_address[5]), + .D6(a7ddrphy_dfi_p2_address[5]), + .D7(a7ddrphy_dfi_p3_address[5]), + .D8(a7ddrphy_dfi_p3_address[5]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[5]) @@ -17884,14 +14933,14 @@ OSERDESE2 #( ) OSERDESE2_7 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[6]), - .D2(soc_a7ddrphy_dfi_p0_address[6]), - .D3(soc_a7ddrphy_dfi_p1_address[6]), - .D4(soc_a7ddrphy_dfi_p1_address[6]), - .D5(soc_a7ddrphy_dfi_p2_address[6]), - .D6(soc_a7ddrphy_dfi_p2_address[6]), - .D7(soc_a7ddrphy_dfi_p3_address[6]), - .D8(soc_a7ddrphy_dfi_p3_address[6]), + .D1(a7ddrphy_dfi_p0_address[6]), + .D2(a7ddrphy_dfi_p0_address[6]), + .D3(a7ddrphy_dfi_p1_address[6]), + .D4(a7ddrphy_dfi_p1_address[6]), + .D5(a7ddrphy_dfi_p2_address[6]), + .D6(a7ddrphy_dfi_p2_address[6]), + .D7(a7ddrphy_dfi_p3_address[6]), + .D8(a7ddrphy_dfi_p3_address[6]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[6]) @@ -17906,14 +14955,14 @@ OSERDESE2 #( ) OSERDESE2_8 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[7]), - .D2(soc_a7ddrphy_dfi_p0_address[7]), - .D3(soc_a7ddrphy_dfi_p1_address[7]), - .D4(soc_a7ddrphy_dfi_p1_address[7]), - .D5(soc_a7ddrphy_dfi_p2_address[7]), - .D6(soc_a7ddrphy_dfi_p2_address[7]), - .D7(soc_a7ddrphy_dfi_p3_address[7]), - .D8(soc_a7ddrphy_dfi_p3_address[7]), + .D1(a7ddrphy_dfi_p0_address[7]), + .D2(a7ddrphy_dfi_p0_address[7]), + .D3(a7ddrphy_dfi_p1_address[7]), + .D4(a7ddrphy_dfi_p1_address[7]), + .D5(a7ddrphy_dfi_p2_address[7]), + .D6(a7ddrphy_dfi_p2_address[7]), + .D7(a7ddrphy_dfi_p3_address[7]), + .D8(a7ddrphy_dfi_p3_address[7]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[7]) @@ -17928,14 +14977,14 @@ OSERDESE2 #( ) OSERDESE2_9 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[8]), - .D2(soc_a7ddrphy_dfi_p0_address[8]), - .D3(soc_a7ddrphy_dfi_p1_address[8]), - .D4(soc_a7ddrphy_dfi_p1_address[8]), - .D5(soc_a7ddrphy_dfi_p2_address[8]), - .D6(soc_a7ddrphy_dfi_p2_address[8]), - .D7(soc_a7ddrphy_dfi_p3_address[8]), - .D8(soc_a7ddrphy_dfi_p3_address[8]), + .D1(a7ddrphy_dfi_p0_address[8]), + .D2(a7ddrphy_dfi_p0_address[8]), + .D3(a7ddrphy_dfi_p1_address[8]), + .D4(a7ddrphy_dfi_p1_address[8]), + .D5(a7ddrphy_dfi_p2_address[8]), + .D6(a7ddrphy_dfi_p2_address[8]), + .D7(a7ddrphy_dfi_p3_address[8]), + .D8(a7ddrphy_dfi_p3_address[8]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[8]) @@ -17950,14 +14999,14 @@ OSERDESE2 #( ) OSERDESE2_10 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[9]), - .D2(soc_a7ddrphy_dfi_p0_address[9]), - .D3(soc_a7ddrphy_dfi_p1_address[9]), - .D4(soc_a7ddrphy_dfi_p1_address[9]), - .D5(soc_a7ddrphy_dfi_p2_address[9]), - .D6(soc_a7ddrphy_dfi_p2_address[9]), - .D7(soc_a7ddrphy_dfi_p3_address[9]), - .D8(soc_a7ddrphy_dfi_p3_address[9]), + .D1(a7ddrphy_dfi_p0_address[9]), + .D2(a7ddrphy_dfi_p0_address[9]), + .D3(a7ddrphy_dfi_p1_address[9]), + .D4(a7ddrphy_dfi_p1_address[9]), + .D5(a7ddrphy_dfi_p2_address[9]), + .D6(a7ddrphy_dfi_p2_address[9]), + .D7(a7ddrphy_dfi_p3_address[9]), + .D8(a7ddrphy_dfi_p3_address[9]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[9]) @@ -17972,14 +15021,14 @@ OSERDESE2 #( ) OSERDESE2_11 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[10]), - .D2(soc_a7ddrphy_dfi_p0_address[10]), - .D3(soc_a7ddrphy_dfi_p1_address[10]), - .D4(soc_a7ddrphy_dfi_p1_address[10]), - .D5(soc_a7ddrphy_dfi_p2_address[10]), - .D6(soc_a7ddrphy_dfi_p2_address[10]), - .D7(soc_a7ddrphy_dfi_p3_address[10]), - .D8(soc_a7ddrphy_dfi_p3_address[10]), + .D1(a7ddrphy_dfi_p0_address[10]), + .D2(a7ddrphy_dfi_p0_address[10]), + .D3(a7ddrphy_dfi_p1_address[10]), + .D4(a7ddrphy_dfi_p1_address[10]), + .D5(a7ddrphy_dfi_p2_address[10]), + .D6(a7ddrphy_dfi_p2_address[10]), + .D7(a7ddrphy_dfi_p3_address[10]), + .D8(a7ddrphy_dfi_p3_address[10]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[10]) @@ -17994,14 +15043,14 @@ OSERDESE2 #( ) OSERDESE2_12 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[11]), - .D2(soc_a7ddrphy_dfi_p0_address[11]), - .D3(soc_a7ddrphy_dfi_p1_address[11]), - .D4(soc_a7ddrphy_dfi_p1_address[11]), - .D5(soc_a7ddrphy_dfi_p2_address[11]), - .D6(soc_a7ddrphy_dfi_p2_address[11]), - .D7(soc_a7ddrphy_dfi_p3_address[11]), - .D8(soc_a7ddrphy_dfi_p3_address[11]), + .D1(a7ddrphy_dfi_p0_address[11]), + .D2(a7ddrphy_dfi_p0_address[11]), + .D3(a7ddrphy_dfi_p1_address[11]), + .D4(a7ddrphy_dfi_p1_address[11]), + .D5(a7ddrphy_dfi_p2_address[11]), + .D6(a7ddrphy_dfi_p2_address[11]), + .D7(a7ddrphy_dfi_p3_address[11]), + .D8(a7ddrphy_dfi_p3_address[11]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[11]) @@ -18016,14 +15065,14 @@ OSERDESE2 #( ) OSERDESE2_13 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[12]), - .D2(soc_a7ddrphy_dfi_p0_address[12]), - .D3(soc_a7ddrphy_dfi_p1_address[12]), - .D4(soc_a7ddrphy_dfi_p1_address[12]), - .D5(soc_a7ddrphy_dfi_p2_address[12]), - .D6(soc_a7ddrphy_dfi_p2_address[12]), - .D7(soc_a7ddrphy_dfi_p3_address[12]), - .D8(soc_a7ddrphy_dfi_p3_address[12]), + .D1(a7ddrphy_dfi_p0_address[12]), + .D2(a7ddrphy_dfi_p0_address[12]), + .D3(a7ddrphy_dfi_p1_address[12]), + .D4(a7ddrphy_dfi_p1_address[12]), + .D5(a7ddrphy_dfi_p2_address[12]), + .D6(a7ddrphy_dfi_p2_address[12]), + .D7(a7ddrphy_dfi_p3_address[12]), + .D8(a7ddrphy_dfi_p3_address[12]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[12]) @@ -18038,14 +15087,14 @@ OSERDESE2 #( ) OSERDESE2_14 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[13]), - .D2(soc_a7ddrphy_dfi_p0_address[13]), - .D3(soc_a7ddrphy_dfi_p1_address[13]), - .D4(soc_a7ddrphy_dfi_p1_address[13]), - .D5(soc_a7ddrphy_dfi_p2_address[13]), - .D6(soc_a7ddrphy_dfi_p2_address[13]), - .D7(soc_a7ddrphy_dfi_p3_address[13]), - .D8(soc_a7ddrphy_dfi_p3_address[13]), + .D1(a7ddrphy_dfi_p0_address[13]), + .D2(a7ddrphy_dfi_p0_address[13]), + .D3(a7ddrphy_dfi_p1_address[13]), + .D4(a7ddrphy_dfi_p1_address[13]), + .D5(a7ddrphy_dfi_p2_address[13]), + .D6(a7ddrphy_dfi_p2_address[13]), + .D7(a7ddrphy_dfi_p3_address[13]), + .D8(a7ddrphy_dfi_p3_address[13]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[13]) @@ -18060,14 +15109,14 @@ OSERDESE2 #( ) OSERDESE2_15 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_bank[0]), - .D2(soc_a7ddrphy_dfi_p0_bank[0]), - .D3(soc_a7ddrphy_dfi_p1_bank[0]), - .D4(soc_a7ddrphy_dfi_p1_bank[0]), - .D5(soc_a7ddrphy_dfi_p2_bank[0]), - .D6(soc_a7ddrphy_dfi_p2_bank[0]), - .D7(soc_a7ddrphy_dfi_p3_bank[0]), - .D8(soc_a7ddrphy_dfi_p3_bank[0]), + .D1(a7ddrphy_dfi_p0_bank[0]), + .D2(a7ddrphy_dfi_p0_bank[0]), + .D3(a7ddrphy_dfi_p1_bank[0]), + .D4(a7ddrphy_dfi_p1_bank[0]), + .D5(a7ddrphy_dfi_p2_bank[0]), + .D6(a7ddrphy_dfi_p2_bank[0]), + .D7(a7ddrphy_dfi_p3_bank[0]), + .D8(a7ddrphy_dfi_p3_bank[0]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_ba[0]) @@ -18082,14 +15131,14 @@ OSERDESE2 #( ) OSERDESE2_16 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_bank[1]), - .D2(soc_a7ddrphy_dfi_p0_bank[1]), - .D3(soc_a7ddrphy_dfi_p1_bank[1]), - .D4(soc_a7ddrphy_dfi_p1_bank[1]), - .D5(soc_a7ddrphy_dfi_p2_bank[1]), - .D6(soc_a7ddrphy_dfi_p2_bank[1]), - .D7(soc_a7ddrphy_dfi_p3_bank[1]), - .D8(soc_a7ddrphy_dfi_p3_bank[1]), + .D1(a7ddrphy_dfi_p0_bank[1]), + .D2(a7ddrphy_dfi_p0_bank[1]), + .D3(a7ddrphy_dfi_p1_bank[1]), + .D4(a7ddrphy_dfi_p1_bank[1]), + .D5(a7ddrphy_dfi_p2_bank[1]), + .D6(a7ddrphy_dfi_p2_bank[1]), + .D7(a7ddrphy_dfi_p3_bank[1]), + .D8(a7ddrphy_dfi_p3_bank[1]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_ba[1]) @@ -18104,14 +15153,14 @@ OSERDESE2 #( ) OSERDESE2_17 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_bank[2]), - .D2(soc_a7ddrphy_dfi_p0_bank[2]), - .D3(soc_a7ddrphy_dfi_p1_bank[2]), - .D4(soc_a7ddrphy_dfi_p1_bank[2]), - .D5(soc_a7ddrphy_dfi_p2_bank[2]), - .D6(soc_a7ddrphy_dfi_p2_bank[2]), - .D7(soc_a7ddrphy_dfi_p3_bank[2]), - .D8(soc_a7ddrphy_dfi_p3_bank[2]), + .D1(a7ddrphy_dfi_p0_bank[2]), + .D2(a7ddrphy_dfi_p0_bank[2]), + .D3(a7ddrphy_dfi_p1_bank[2]), + .D4(a7ddrphy_dfi_p1_bank[2]), + .D5(a7ddrphy_dfi_p2_bank[2]), + .D6(a7ddrphy_dfi_p2_bank[2]), + .D7(a7ddrphy_dfi_p3_bank[2]), + .D8(a7ddrphy_dfi_p3_bank[2]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_ba[2]) @@ -18126,14 +15175,14 @@ OSERDESE2 #( ) OSERDESE2_18 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_ras_n), - .D2(soc_a7ddrphy_dfi_p0_ras_n), - .D3(soc_a7ddrphy_dfi_p1_ras_n), - .D4(soc_a7ddrphy_dfi_p1_ras_n), - .D5(soc_a7ddrphy_dfi_p2_ras_n), - .D6(soc_a7ddrphy_dfi_p2_ras_n), - .D7(soc_a7ddrphy_dfi_p3_ras_n), - .D8(soc_a7ddrphy_dfi_p3_ras_n), + .D1(a7ddrphy_dfi_p0_ras_n), + .D2(a7ddrphy_dfi_p0_ras_n), + .D3(a7ddrphy_dfi_p1_ras_n), + .D4(a7ddrphy_dfi_p1_ras_n), + .D5(a7ddrphy_dfi_p2_ras_n), + .D6(a7ddrphy_dfi_p2_ras_n), + .D7(a7ddrphy_dfi_p3_ras_n), + .D8(a7ddrphy_dfi_p3_ras_n), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_ras_n) @@ -18148,14 +15197,14 @@ OSERDESE2 #( ) OSERDESE2_19 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_cas_n), - .D2(soc_a7ddrphy_dfi_p0_cas_n), - .D3(soc_a7ddrphy_dfi_p1_cas_n), - .D4(soc_a7ddrphy_dfi_p1_cas_n), - .D5(soc_a7ddrphy_dfi_p2_cas_n), - .D6(soc_a7ddrphy_dfi_p2_cas_n), - .D7(soc_a7ddrphy_dfi_p3_cas_n), - .D8(soc_a7ddrphy_dfi_p3_cas_n), + .D1(a7ddrphy_dfi_p0_cas_n), + .D2(a7ddrphy_dfi_p0_cas_n), + .D3(a7ddrphy_dfi_p1_cas_n), + .D4(a7ddrphy_dfi_p1_cas_n), + .D5(a7ddrphy_dfi_p2_cas_n), + .D6(a7ddrphy_dfi_p2_cas_n), + .D7(a7ddrphy_dfi_p3_cas_n), + .D8(a7ddrphy_dfi_p3_cas_n), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_cas_n) @@ -18170,14 +15219,14 @@ OSERDESE2 #( ) OSERDESE2_20 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_we_n), - .D2(soc_a7ddrphy_dfi_p0_we_n), - .D3(soc_a7ddrphy_dfi_p1_we_n), - .D4(soc_a7ddrphy_dfi_p1_we_n), - .D5(soc_a7ddrphy_dfi_p2_we_n), - .D6(soc_a7ddrphy_dfi_p2_we_n), - .D7(soc_a7ddrphy_dfi_p3_we_n), - .D8(soc_a7ddrphy_dfi_p3_we_n), + .D1(a7ddrphy_dfi_p0_we_n), + .D2(a7ddrphy_dfi_p0_we_n), + .D3(a7ddrphy_dfi_p1_we_n), + .D4(a7ddrphy_dfi_p1_we_n), + .D5(a7ddrphy_dfi_p2_we_n), + .D6(a7ddrphy_dfi_p2_we_n), + .D7(a7ddrphy_dfi_p3_we_n), + .D8(a7ddrphy_dfi_p3_we_n), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_we_n) @@ -18192,14 +15241,14 @@ OSERDESE2 #( ) OSERDESE2_21 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_cke), - .D2(soc_a7ddrphy_dfi_p0_cke), - .D3(soc_a7ddrphy_dfi_p1_cke), - .D4(soc_a7ddrphy_dfi_p1_cke), - .D5(soc_a7ddrphy_dfi_p2_cke), - .D6(soc_a7ddrphy_dfi_p2_cke), - .D7(soc_a7ddrphy_dfi_p3_cke), - .D8(soc_a7ddrphy_dfi_p3_cke), + .D1(a7ddrphy_dfi_p0_cke), + .D2(a7ddrphy_dfi_p0_cke), + .D3(a7ddrphy_dfi_p1_cke), + .D4(a7ddrphy_dfi_p1_cke), + .D5(a7ddrphy_dfi_p2_cke), + .D6(a7ddrphy_dfi_p2_cke), + .D7(a7ddrphy_dfi_p3_cke), + .D8(a7ddrphy_dfi_p3_cke), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_cke) @@ -18214,14 +15263,14 @@ OSERDESE2 #( ) OSERDESE2_22 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_odt), - .D2(soc_a7ddrphy_dfi_p0_odt), - .D3(soc_a7ddrphy_dfi_p1_odt), - .D4(soc_a7ddrphy_dfi_p1_odt), - .D5(soc_a7ddrphy_dfi_p2_odt), - .D6(soc_a7ddrphy_dfi_p2_odt), - .D7(soc_a7ddrphy_dfi_p3_odt), - .D8(soc_a7ddrphy_dfi_p3_odt), + .D1(a7ddrphy_dfi_p0_odt), + .D2(a7ddrphy_dfi_p0_odt), + .D3(a7ddrphy_dfi_p1_odt), + .D4(a7ddrphy_dfi_p1_odt), + .D5(a7ddrphy_dfi_p2_odt), + .D6(a7ddrphy_dfi_p2_odt), + .D7(a7ddrphy_dfi_p3_odt), + .D8(a7ddrphy_dfi_p3_odt), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_odt) @@ -18236,14 +15285,14 @@ OSERDESE2 #( ) OSERDESE2_23 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_reset_n), - .D2(soc_a7ddrphy_dfi_p0_reset_n), - .D3(soc_a7ddrphy_dfi_p1_reset_n), - .D4(soc_a7ddrphy_dfi_p1_reset_n), - .D5(soc_a7ddrphy_dfi_p2_reset_n), - .D6(soc_a7ddrphy_dfi_p2_reset_n), - .D7(soc_a7ddrphy_dfi_p3_reset_n), - .D8(soc_a7ddrphy_dfi_p3_reset_n), + .D1(a7ddrphy_dfi_p0_reset_n), + .D2(a7ddrphy_dfi_p0_reset_n), + .D3(a7ddrphy_dfi_p1_reset_n), + .D4(a7ddrphy_dfi_p1_reset_n), + .D5(a7ddrphy_dfi_p2_reset_n), + .D6(a7ddrphy_dfi_p2_reset_n), + .D7(a7ddrphy_dfi_p3_reset_n), + .D8(a7ddrphy_dfi_p3_reset_n), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_reset_n) @@ -18258,14 +15307,14 @@ OSERDESE2 #( ) OSERDESE2_24 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_cs_n), - .D2(soc_a7ddrphy_dfi_p0_cs_n), - .D3(soc_a7ddrphy_dfi_p1_cs_n), - .D4(soc_a7ddrphy_dfi_p1_cs_n), - .D5(soc_a7ddrphy_dfi_p2_cs_n), - .D6(soc_a7ddrphy_dfi_p2_cs_n), - .D7(soc_a7ddrphy_dfi_p3_cs_n), - .D8(soc_a7ddrphy_dfi_p3_cs_n), + .D1(a7ddrphy_dfi_p0_cs_n), + .D2(a7ddrphy_dfi_p0_cs_n), + .D3(a7ddrphy_dfi_p1_cs_n), + .D4(a7ddrphy_dfi_p1_cs_n), + .D5(a7ddrphy_dfi_p2_cs_n), + .D6(a7ddrphy_dfi_p2_cs_n), + .D7(a7ddrphy_dfi_p3_cs_n), + .D8(a7ddrphy_dfi_p3_cs_n), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_cs_n) @@ -18280,14 +15329,14 @@ OSERDESE2 #( ) OSERDESE2_25 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[0]), - .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[2]), - .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[0]), - .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[2]), - .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[0]), - .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[2]), - .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[0]), - .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[2]), + .D1(a7ddrphy_dfi_p0_wrdata_mask[0]), + .D2(a7ddrphy_dfi_p0_wrdata_mask[2]), + .D3(a7ddrphy_dfi_p1_wrdata_mask[0]), + .D4(a7ddrphy_dfi_p1_wrdata_mask[2]), + .D5(a7ddrphy_dfi_p2_wrdata_mask[0]), + .D6(a7ddrphy_dfi_p2_wrdata_mask[2]), + .D7(a7ddrphy_dfi_p3_wrdata_mask[0]), + .D8(a7ddrphy_dfi_p3_wrdata_mask[2]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_dm[0]) @@ -18302,14 +15351,14 @@ OSERDESE2 #( ) OSERDESE2_26 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[1]), - .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[3]), - .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[1]), - .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[3]), - .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[1]), - .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[3]), - .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[1]), - .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[3]), + .D1(a7ddrphy_dfi_p0_wrdata_mask[1]), + .D2(a7ddrphy_dfi_p0_wrdata_mask[3]), + .D3(a7ddrphy_dfi_p1_wrdata_mask[1]), + .D4(a7ddrphy_dfi_p1_wrdata_mask[3]), + .D5(a7ddrphy_dfi_p2_wrdata_mask[1]), + .D6(a7ddrphy_dfi_p2_wrdata_mask[3]), + .D7(a7ddrphy_dfi_p3_wrdata_mask[1]), + .D8(a7ddrphy_dfi_p3_wrdata_mask[3]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_dm[1]) @@ -18324,21 +15373,21 @@ OSERDESE2 #( ) OSERDESE2_27 ( .CLK(sys4x_dqs_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dqspattern_o1[0]), - .D2(soc_a7ddrphy_dqspattern_o1[1]), - .D3(soc_a7ddrphy_dqspattern_o1[2]), - .D4(soc_a7ddrphy_dqspattern_o1[3]), - .D5(soc_a7ddrphy_dqspattern_o1[4]), - .D6(soc_a7ddrphy_dqspattern_o1[5]), - .D7(soc_a7ddrphy_dqspattern_o1[6]), - .D8(soc_a7ddrphy_dqspattern_o1[7]), + .D1(a7ddrphy_dqspattern_o1[0]), + .D2(a7ddrphy_dqspattern_o1[1]), + .D3(a7ddrphy_dqspattern_o1[2]), + .D4(a7ddrphy_dqspattern_o1[3]), + .D5(a7ddrphy_dqspattern_o1[4]), + .D6(a7ddrphy_dqspattern_o1[5]), + .D7(a7ddrphy_dqspattern_o1[6]), + .D8(a7ddrphy_dqspattern_o1[7]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dqs_oe_delayed)), + .T1((~a7ddrphy_dqs_oe_delayed)), .TCE(1'd1), - .OFB(soc_a7ddrphy0), - .OQ(soc_a7ddrphy_dqs_o_no_delay0), - .TQ(soc_a7ddrphy_dqs_t0) + .OFB(a7ddrphy0), + .OQ(a7ddrphy_dqs_o_no_delay0), + .TQ(a7ddrphy_dqs_t0) ); IDELAYE2 #( @@ -18351,16 +15400,16 @@ IDELAYE2 #( .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2 ( - .IDATAIN(soc_a7ddrphy_dqs_i[0]), - .DATAOUT(soc_a7ddrphy_dqs_i_delayed[0]) + .IDATAIN(a7ddrphy_dqs_i[0]), + .DATAOUT(a7ddrphy_dqs_i_delayed[0]) ); IOBUFDS IOBUFDS( - .I(soc_a7ddrphy_dqs_o_no_delay0), - .T(soc_a7ddrphy_dqs_t0), + .I(a7ddrphy_dqs_o_no_delay0), + .T(a7ddrphy_dqs_t0), .IO(ddram_dqs_p[0]), .IOB(ddram_dqs_n[0]), - .O(soc_a7ddrphy_dqs_i[0]) + .O(a7ddrphy_dqs_i[0]) ); OSERDESE2 #( @@ -18372,21 +15421,21 @@ OSERDESE2 #( ) OSERDESE2_28 ( .CLK(sys4x_dqs_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dqspattern_o1[0]), - .D2(soc_a7ddrphy_dqspattern_o1[1]), - .D3(soc_a7ddrphy_dqspattern_o1[2]), - .D4(soc_a7ddrphy_dqspattern_o1[3]), - .D5(soc_a7ddrphy_dqspattern_o1[4]), - .D6(soc_a7ddrphy_dqspattern_o1[5]), - .D7(soc_a7ddrphy_dqspattern_o1[6]), - .D8(soc_a7ddrphy_dqspattern_o1[7]), + .D1(a7ddrphy_dqspattern_o1[0]), + .D2(a7ddrphy_dqspattern_o1[1]), + .D3(a7ddrphy_dqspattern_o1[2]), + .D4(a7ddrphy_dqspattern_o1[3]), + .D5(a7ddrphy_dqspattern_o1[4]), + .D6(a7ddrphy_dqspattern_o1[5]), + .D7(a7ddrphy_dqspattern_o1[6]), + .D8(a7ddrphy_dqspattern_o1[7]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dqs_oe_delayed)), + .T1((~a7ddrphy_dqs_oe_delayed)), .TCE(1'd1), - .OFB(soc_a7ddrphy1), - .OQ(soc_a7ddrphy_dqs_o_no_delay1), - .TQ(soc_a7ddrphy_dqs_t1) + .OFB(a7ddrphy1), + .OQ(a7ddrphy_dqs_o_no_delay1), + .TQ(a7ddrphy_dqs_t1) ); IDELAYE2 #( @@ -18399,16 +15448,16 @@ IDELAYE2 #( .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_1 ( - .IDATAIN(soc_a7ddrphy_dqs_i[1]), - .DATAOUT(soc_a7ddrphy_dqs_i_delayed[1]) + .IDATAIN(a7ddrphy_dqs_i[1]), + .DATAOUT(a7ddrphy_dqs_i_delayed[1]) ); IOBUFDS IOBUFDS_1( - .I(soc_a7ddrphy_dqs_o_no_delay1), - .T(soc_a7ddrphy_dqs_t1), + .I(a7ddrphy_dqs_o_no_delay1), + .T(a7ddrphy_dqs_t1), .IO(ddram_dqs_p[1]), .IOB(ddram_dqs_n[1]), - .O(soc_a7ddrphy_dqs_i[1]) + .O(a7ddrphy_dqs_i[1]) ); OSERDESE2 #( @@ -18420,20 +15469,20 @@ OSERDESE2 #( ) OSERDESE2_29 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[0]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[16]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[0]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[16]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[0]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[16]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[0]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[16]), + .D1(a7ddrphy_dfi_p0_wrdata[0]), + .D2(a7ddrphy_dfi_p0_wrdata[16]), + .D3(a7ddrphy_dfi_p1_wrdata[0]), + .D4(a7ddrphy_dfi_p1_wrdata[16]), + .D5(a7ddrphy_dfi_p2_wrdata[0]), + .D6(a7ddrphy_dfi_p2_wrdata[16]), + .D7(a7ddrphy_dfi_p3_wrdata[0]), + .D8(a7ddrphy_dfi_p3_wrdata[16]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay0), - .TQ(soc_a7ddrphy_dq_t0) + .OQ(a7ddrphy_dq_o_nodelay0), + .TQ(a7ddrphy_dq_t0) ); ISERDESE2 #( @@ -18449,16 +15498,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed0), + .DDLY(a7ddrphy_dq_i_delayed0), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data0[7]), - .Q2(soc_a7ddrphy_dq_i_data0[6]), - .Q3(soc_a7ddrphy_dq_i_data0[5]), - .Q4(soc_a7ddrphy_dq_i_data0[4]), - .Q5(soc_a7ddrphy_dq_i_data0[3]), - .Q6(soc_a7ddrphy_dq_i_data0[2]), - .Q7(soc_a7ddrphy_dq_i_data0[1]), - .Q8(soc_a7ddrphy_dq_i_data0[0]) + .Q1(a7ddrphy_dq_i_data0[7]), + .Q2(a7ddrphy_dq_i_data0[6]), + .Q3(a7ddrphy_dq_i_data0[5]), + .Q4(a7ddrphy_dq_i_data0[4]), + .Q5(a7ddrphy_dq_i_data0[3]), + .Q6(a7ddrphy_dq_i_data0[2]), + .Q7(a7ddrphy_dq_i_data0[1]), + .Q8(a7ddrphy_dq_i_data0[0]) ); IDELAYE2 #( @@ -18472,19 +15521,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_2 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay0), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay0), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed0) + .DATAOUT(a7ddrphy_dq_i_delayed0) ); IOBUF IOBUF( - .I(soc_a7ddrphy_dq_o_nodelay0), - .T(soc_a7ddrphy_dq_t0), + .I(a7ddrphy_dq_o_nodelay0), + .T(a7ddrphy_dq_t0), .IO(ddram_dq[0]), - .O(soc_a7ddrphy_dq_i_nodelay0) + .O(a7ddrphy_dq_i_nodelay0) ); OSERDESE2 #( @@ -18496,20 +15545,20 @@ OSERDESE2 #( ) OSERDESE2_30 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[1]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[17]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[1]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[17]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[1]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[17]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[1]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[17]), + .D1(a7ddrphy_dfi_p0_wrdata[1]), + .D2(a7ddrphy_dfi_p0_wrdata[17]), + .D3(a7ddrphy_dfi_p1_wrdata[1]), + .D4(a7ddrphy_dfi_p1_wrdata[17]), + .D5(a7ddrphy_dfi_p2_wrdata[1]), + .D6(a7ddrphy_dfi_p2_wrdata[17]), + .D7(a7ddrphy_dfi_p3_wrdata[1]), + .D8(a7ddrphy_dfi_p3_wrdata[17]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay1), - .TQ(soc_a7ddrphy_dq_t1) + .OQ(a7ddrphy_dq_o_nodelay1), + .TQ(a7ddrphy_dq_t1) ); ISERDESE2 #( @@ -18525,16 +15574,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed1), + .DDLY(a7ddrphy_dq_i_delayed1), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data1[7]), - .Q2(soc_a7ddrphy_dq_i_data1[6]), - .Q3(soc_a7ddrphy_dq_i_data1[5]), - .Q4(soc_a7ddrphy_dq_i_data1[4]), - .Q5(soc_a7ddrphy_dq_i_data1[3]), - .Q6(soc_a7ddrphy_dq_i_data1[2]), - .Q7(soc_a7ddrphy_dq_i_data1[1]), - .Q8(soc_a7ddrphy_dq_i_data1[0]) + .Q1(a7ddrphy_dq_i_data1[7]), + .Q2(a7ddrphy_dq_i_data1[6]), + .Q3(a7ddrphy_dq_i_data1[5]), + .Q4(a7ddrphy_dq_i_data1[4]), + .Q5(a7ddrphy_dq_i_data1[3]), + .Q6(a7ddrphy_dq_i_data1[2]), + .Q7(a7ddrphy_dq_i_data1[1]), + .Q8(a7ddrphy_dq_i_data1[0]) ); IDELAYE2 #( @@ -18548,19 +15597,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_3 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay1), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay1), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed1) + .DATAOUT(a7ddrphy_dq_i_delayed1) ); IOBUF IOBUF_1( - .I(soc_a7ddrphy_dq_o_nodelay1), - .T(soc_a7ddrphy_dq_t1), + .I(a7ddrphy_dq_o_nodelay1), + .T(a7ddrphy_dq_t1), .IO(ddram_dq[1]), - .O(soc_a7ddrphy_dq_i_nodelay1) + .O(a7ddrphy_dq_i_nodelay1) ); OSERDESE2 #( @@ -18572,20 +15621,20 @@ OSERDESE2 #( ) OSERDESE2_31 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[2]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[18]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[2]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[18]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[2]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[18]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[2]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[18]), + .D1(a7ddrphy_dfi_p0_wrdata[2]), + .D2(a7ddrphy_dfi_p0_wrdata[18]), + .D3(a7ddrphy_dfi_p1_wrdata[2]), + .D4(a7ddrphy_dfi_p1_wrdata[18]), + .D5(a7ddrphy_dfi_p2_wrdata[2]), + .D6(a7ddrphy_dfi_p2_wrdata[18]), + .D7(a7ddrphy_dfi_p3_wrdata[2]), + .D8(a7ddrphy_dfi_p3_wrdata[18]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay2), - .TQ(soc_a7ddrphy_dq_t2) + .OQ(a7ddrphy_dq_o_nodelay2), + .TQ(a7ddrphy_dq_t2) ); ISERDESE2 #( @@ -18601,16 +15650,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed2), + .DDLY(a7ddrphy_dq_i_delayed2), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data2[7]), - .Q2(soc_a7ddrphy_dq_i_data2[6]), - .Q3(soc_a7ddrphy_dq_i_data2[5]), - .Q4(soc_a7ddrphy_dq_i_data2[4]), - .Q5(soc_a7ddrphy_dq_i_data2[3]), - .Q6(soc_a7ddrphy_dq_i_data2[2]), - .Q7(soc_a7ddrphy_dq_i_data2[1]), - .Q8(soc_a7ddrphy_dq_i_data2[0]) + .Q1(a7ddrphy_dq_i_data2[7]), + .Q2(a7ddrphy_dq_i_data2[6]), + .Q3(a7ddrphy_dq_i_data2[5]), + .Q4(a7ddrphy_dq_i_data2[4]), + .Q5(a7ddrphy_dq_i_data2[3]), + .Q6(a7ddrphy_dq_i_data2[2]), + .Q7(a7ddrphy_dq_i_data2[1]), + .Q8(a7ddrphy_dq_i_data2[0]) ); IDELAYE2 #( @@ -18624,19 +15673,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_4 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay2), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay2), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed2) + .DATAOUT(a7ddrphy_dq_i_delayed2) ); IOBUF IOBUF_2( - .I(soc_a7ddrphy_dq_o_nodelay2), - .T(soc_a7ddrphy_dq_t2), + .I(a7ddrphy_dq_o_nodelay2), + .T(a7ddrphy_dq_t2), .IO(ddram_dq[2]), - .O(soc_a7ddrphy_dq_i_nodelay2) + .O(a7ddrphy_dq_i_nodelay2) ); OSERDESE2 #( @@ -18648,20 +15697,20 @@ OSERDESE2 #( ) OSERDESE2_32 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[3]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[19]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[3]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[19]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[3]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[19]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[3]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[19]), + .D1(a7ddrphy_dfi_p0_wrdata[3]), + .D2(a7ddrphy_dfi_p0_wrdata[19]), + .D3(a7ddrphy_dfi_p1_wrdata[3]), + .D4(a7ddrphy_dfi_p1_wrdata[19]), + .D5(a7ddrphy_dfi_p2_wrdata[3]), + .D6(a7ddrphy_dfi_p2_wrdata[19]), + .D7(a7ddrphy_dfi_p3_wrdata[3]), + .D8(a7ddrphy_dfi_p3_wrdata[19]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay3), - .TQ(soc_a7ddrphy_dq_t3) + .OQ(a7ddrphy_dq_o_nodelay3), + .TQ(a7ddrphy_dq_t3) ); ISERDESE2 #( @@ -18677,16 +15726,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed3), + .DDLY(a7ddrphy_dq_i_delayed3), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data3[7]), - .Q2(soc_a7ddrphy_dq_i_data3[6]), - .Q3(soc_a7ddrphy_dq_i_data3[5]), - .Q4(soc_a7ddrphy_dq_i_data3[4]), - .Q5(soc_a7ddrphy_dq_i_data3[3]), - .Q6(soc_a7ddrphy_dq_i_data3[2]), - .Q7(soc_a7ddrphy_dq_i_data3[1]), - .Q8(soc_a7ddrphy_dq_i_data3[0]) + .Q1(a7ddrphy_dq_i_data3[7]), + .Q2(a7ddrphy_dq_i_data3[6]), + .Q3(a7ddrphy_dq_i_data3[5]), + .Q4(a7ddrphy_dq_i_data3[4]), + .Q5(a7ddrphy_dq_i_data3[3]), + .Q6(a7ddrphy_dq_i_data3[2]), + .Q7(a7ddrphy_dq_i_data3[1]), + .Q8(a7ddrphy_dq_i_data3[0]) ); IDELAYE2 #( @@ -18700,19 +15749,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_5 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay3), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay3), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed3) + .DATAOUT(a7ddrphy_dq_i_delayed3) ); IOBUF IOBUF_3( - .I(soc_a7ddrphy_dq_o_nodelay3), - .T(soc_a7ddrphy_dq_t3), + .I(a7ddrphy_dq_o_nodelay3), + .T(a7ddrphy_dq_t3), .IO(ddram_dq[3]), - .O(soc_a7ddrphy_dq_i_nodelay3) + .O(a7ddrphy_dq_i_nodelay3) ); OSERDESE2 #( @@ -18724,20 +15773,20 @@ OSERDESE2 #( ) OSERDESE2_33 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[4]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[20]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[4]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[20]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[4]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[20]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[4]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[20]), + .D1(a7ddrphy_dfi_p0_wrdata[4]), + .D2(a7ddrphy_dfi_p0_wrdata[20]), + .D3(a7ddrphy_dfi_p1_wrdata[4]), + .D4(a7ddrphy_dfi_p1_wrdata[20]), + .D5(a7ddrphy_dfi_p2_wrdata[4]), + .D6(a7ddrphy_dfi_p2_wrdata[20]), + .D7(a7ddrphy_dfi_p3_wrdata[4]), + .D8(a7ddrphy_dfi_p3_wrdata[20]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay4), - .TQ(soc_a7ddrphy_dq_t4) + .OQ(a7ddrphy_dq_o_nodelay4), + .TQ(a7ddrphy_dq_t4) ); ISERDESE2 #( @@ -18753,16 +15802,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed4), + .DDLY(a7ddrphy_dq_i_delayed4), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data4[7]), - .Q2(soc_a7ddrphy_dq_i_data4[6]), - .Q3(soc_a7ddrphy_dq_i_data4[5]), - .Q4(soc_a7ddrphy_dq_i_data4[4]), - .Q5(soc_a7ddrphy_dq_i_data4[3]), - .Q6(soc_a7ddrphy_dq_i_data4[2]), - .Q7(soc_a7ddrphy_dq_i_data4[1]), - .Q8(soc_a7ddrphy_dq_i_data4[0]) + .Q1(a7ddrphy_dq_i_data4[7]), + .Q2(a7ddrphy_dq_i_data4[6]), + .Q3(a7ddrphy_dq_i_data4[5]), + .Q4(a7ddrphy_dq_i_data4[4]), + .Q5(a7ddrphy_dq_i_data4[3]), + .Q6(a7ddrphy_dq_i_data4[2]), + .Q7(a7ddrphy_dq_i_data4[1]), + .Q8(a7ddrphy_dq_i_data4[0]) ); IDELAYE2 #( @@ -18776,19 +15825,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_6 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay4), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay4), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed4) + .DATAOUT(a7ddrphy_dq_i_delayed4) ); IOBUF IOBUF_4( - .I(soc_a7ddrphy_dq_o_nodelay4), - .T(soc_a7ddrphy_dq_t4), + .I(a7ddrphy_dq_o_nodelay4), + .T(a7ddrphy_dq_t4), .IO(ddram_dq[4]), - .O(soc_a7ddrphy_dq_i_nodelay4) + .O(a7ddrphy_dq_i_nodelay4) ); OSERDESE2 #( @@ -18800,20 +15849,20 @@ OSERDESE2 #( ) OSERDESE2_34 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[5]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[21]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[5]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[21]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[5]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[21]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[5]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[21]), + .D1(a7ddrphy_dfi_p0_wrdata[5]), + .D2(a7ddrphy_dfi_p0_wrdata[21]), + .D3(a7ddrphy_dfi_p1_wrdata[5]), + .D4(a7ddrphy_dfi_p1_wrdata[21]), + .D5(a7ddrphy_dfi_p2_wrdata[5]), + .D6(a7ddrphy_dfi_p2_wrdata[21]), + .D7(a7ddrphy_dfi_p3_wrdata[5]), + .D8(a7ddrphy_dfi_p3_wrdata[21]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay5), - .TQ(soc_a7ddrphy_dq_t5) + .OQ(a7ddrphy_dq_o_nodelay5), + .TQ(a7ddrphy_dq_t5) ); ISERDESE2 #( @@ -18829,16 +15878,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed5), + .DDLY(a7ddrphy_dq_i_delayed5), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data5[7]), - .Q2(soc_a7ddrphy_dq_i_data5[6]), - .Q3(soc_a7ddrphy_dq_i_data5[5]), - .Q4(soc_a7ddrphy_dq_i_data5[4]), - .Q5(soc_a7ddrphy_dq_i_data5[3]), - .Q6(soc_a7ddrphy_dq_i_data5[2]), - .Q7(soc_a7ddrphy_dq_i_data5[1]), - .Q8(soc_a7ddrphy_dq_i_data5[0]) + .Q1(a7ddrphy_dq_i_data5[7]), + .Q2(a7ddrphy_dq_i_data5[6]), + .Q3(a7ddrphy_dq_i_data5[5]), + .Q4(a7ddrphy_dq_i_data5[4]), + .Q5(a7ddrphy_dq_i_data5[3]), + .Q6(a7ddrphy_dq_i_data5[2]), + .Q7(a7ddrphy_dq_i_data5[1]), + .Q8(a7ddrphy_dq_i_data5[0]) ); IDELAYE2 #( @@ -18852,19 +15901,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_7 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay5), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay5), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed5) + .DATAOUT(a7ddrphy_dq_i_delayed5) ); IOBUF IOBUF_5( - .I(soc_a7ddrphy_dq_o_nodelay5), - .T(soc_a7ddrphy_dq_t5), + .I(a7ddrphy_dq_o_nodelay5), + .T(a7ddrphy_dq_t5), .IO(ddram_dq[5]), - .O(soc_a7ddrphy_dq_i_nodelay5) + .O(a7ddrphy_dq_i_nodelay5) ); OSERDESE2 #( @@ -18876,20 +15925,20 @@ OSERDESE2 #( ) OSERDESE2_35 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[6]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[22]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[6]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[22]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[6]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[22]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[6]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[22]), + .D1(a7ddrphy_dfi_p0_wrdata[6]), + .D2(a7ddrphy_dfi_p0_wrdata[22]), + .D3(a7ddrphy_dfi_p1_wrdata[6]), + .D4(a7ddrphy_dfi_p1_wrdata[22]), + .D5(a7ddrphy_dfi_p2_wrdata[6]), + .D6(a7ddrphy_dfi_p2_wrdata[22]), + .D7(a7ddrphy_dfi_p3_wrdata[6]), + .D8(a7ddrphy_dfi_p3_wrdata[22]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay6), - .TQ(soc_a7ddrphy_dq_t6) + .OQ(a7ddrphy_dq_o_nodelay6), + .TQ(a7ddrphy_dq_t6) ); ISERDESE2 #( @@ -18905,16 +15954,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed6), + .DDLY(a7ddrphy_dq_i_delayed6), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data6[7]), - .Q2(soc_a7ddrphy_dq_i_data6[6]), - .Q3(soc_a7ddrphy_dq_i_data6[5]), - .Q4(soc_a7ddrphy_dq_i_data6[4]), - .Q5(soc_a7ddrphy_dq_i_data6[3]), - .Q6(soc_a7ddrphy_dq_i_data6[2]), - .Q7(soc_a7ddrphy_dq_i_data6[1]), - .Q8(soc_a7ddrphy_dq_i_data6[0]) + .Q1(a7ddrphy_dq_i_data6[7]), + .Q2(a7ddrphy_dq_i_data6[6]), + .Q3(a7ddrphy_dq_i_data6[5]), + .Q4(a7ddrphy_dq_i_data6[4]), + .Q5(a7ddrphy_dq_i_data6[3]), + .Q6(a7ddrphy_dq_i_data6[2]), + .Q7(a7ddrphy_dq_i_data6[1]), + .Q8(a7ddrphy_dq_i_data6[0]) ); IDELAYE2 #( @@ -18928,19 +15977,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_8 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay6), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay6), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed6) + .DATAOUT(a7ddrphy_dq_i_delayed6) ); IOBUF IOBUF_6( - .I(soc_a7ddrphy_dq_o_nodelay6), - .T(soc_a7ddrphy_dq_t6), + .I(a7ddrphy_dq_o_nodelay6), + .T(a7ddrphy_dq_t6), .IO(ddram_dq[6]), - .O(soc_a7ddrphy_dq_i_nodelay6) + .O(a7ddrphy_dq_i_nodelay6) ); OSERDESE2 #( @@ -18952,20 +16001,20 @@ OSERDESE2 #( ) OSERDESE2_36 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[7]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[23]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[7]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[23]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[7]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[23]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[7]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[23]), + .D1(a7ddrphy_dfi_p0_wrdata[7]), + .D2(a7ddrphy_dfi_p0_wrdata[23]), + .D3(a7ddrphy_dfi_p1_wrdata[7]), + .D4(a7ddrphy_dfi_p1_wrdata[23]), + .D5(a7ddrphy_dfi_p2_wrdata[7]), + .D6(a7ddrphy_dfi_p2_wrdata[23]), + .D7(a7ddrphy_dfi_p3_wrdata[7]), + .D8(a7ddrphy_dfi_p3_wrdata[23]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay7), - .TQ(soc_a7ddrphy_dq_t7) + .OQ(a7ddrphy_dq_o_nodelay7), + .TQ(a7ddrphy_dq_t7) ); ISERDESE2 #( @@ -18981,16 +16030,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed7), + .DDLY(a7ddrphy_dq_i_delayed7), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data7[7]), - .Q2(soc_a7ddrphy_dq_i_data7[6]), - .Q3(soc_a7ddrphy_dq_i_data7[5]), - .Q4(soc_a7ddrphy_dq_i_data7[4]), - .Q5(soc_a7ddrphy_dq_i_data7[3]), - .Q6(soc_a7ddrphy_dq_i_data7[2]), - .Q7(soc_a7ddrphy_dq_i_data7[1]), - .Q8(soc_a7ddrphy_dq_i_data7[0]) + .Q1(a7ddrphy_dq_i_data7[7]), + .Q2(a7ddrphy_dq_i_data7[6]), + .Q3(a7ddrphy_dq_i_data7[5]), + .Q4(a7ddrphy_dq_i_data7[4]), + .Q5(a7ddrphy_dq_i_data7[3]), + .Q6(a7ddrphy_dq_i_data7[2]), + .Q7(a7ddrphy_dq_i_data7[1]), + .Q8(a7ddrphy_dq_i_data7[0]) ); IDELAYE2 #( @@ -19004,19 +16053,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_9 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay7), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay7), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed7) + .DATAOUT(a7ddrphy_dq_i_delayed7) ); IOBUF IOBUF_7( - .I(soc_a7ddrphy_dq_o_nodelay7), - .T(soc_a7ddrphy_dq_t7), + .I(a7ddrphy_dq_o_nodelay7), + .T(a7ddrphy_dq_t7), .IO(ddram_dq[7]), - .O(soc_a7ddrphy_dq_i_nodelay7) + .O(a7ddrphy_dq_i_nodelay7) ); OSERDESE2 #( @@ -19028,20 +16077,20 @@ OSERDESE2 #( ) OSERDESE2_37 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[8]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[24]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[8]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[24]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[8]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[24]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[8]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[24]), + .D1(a7ddrphy_dfi_p0_wrdata[8]), + .D2(a7ddrphy_dfi_p0_wrdata[24]), + .D3(a7ddrphy_dfi_p1_wrdata[8]), + .D4(a7ddrphy_dfi_p1_wrdata[24]), + .D5(a7ddrphy_dfi_p2_wrdata[8]), + .D6(a7ddrphy_dfi_p2_wrdata[24]), + .D7(a7ddrphy_dfi_p3_wrdata[8]), + .D8(a7ddrphy_dfi_p3_wrdata[24]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay8), - .TQ(soc_a7ddrphy_dq_t8) + .OQ(a7ddrphy_dq_o_nodelay8), + .TQ(a7ddrphy_dq_t8) ); ISERDESE2 #( @@ -19057,16 +16106,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed8), + .DDLY(a7ddrphy_dq_i_delayed8), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data8[7]), - .Q2(soc_a7ddrphy_dq_i_data8[6]), - .Q3(soc_a7ddrphy_dq_i_data8[5]), - .Q4(soc_a7ddrphy_dq_i_data8[4]), - .Q5(soc_a7ddrphy_dq_i_data8[3]), - .Q6(soc_a7ddrphy_dq_i_data8[2]), - .Q7(soc_a7ddrphy_dq_i_data8[1]), - .Q8(soc_a7ddrphy_dq_i_data8[0]) + .Q1(a7ddrphy_dq_i_data8[7]), + .Q2(a7ddrphy_dq_i_data8[6]), + .Q3(a7ddrphy_dq_i_data8[5]), + .Q4(a7ddrphy_dq_i_data8[4]), + .Q5(a7ddrphy_dq_i_data8[3]), + .Q6(a7ddrphy_dq_i_data8[2]), + .Q7(a7ddrphy_dq_i_data8[1]), + .Q8(a7ddrphy_dq_i_data8[0]) ); IDELAYE2 #( @@ -19080,19 +16129,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_10 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay8), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay8), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed8) + .DATAOUT(a7ddrphy_dq_i_delayed8) ); IOBUF IOBUF_8( - .I(soc_a7ddrphy_dq_o_nodelay8), - .T(soc_a7ddrphy_dq_t8), + .I(a7ddrphy_dq_o_nodelay8), + .T(a7ddrphy_dq_t8), .IO(ddram_dq[8]), - .O(soc_a7ddrphy_dq_i_nodelay8) + .O(a7ddrphy_dq_i_nodelay8) ); OSERDESE2 #( @@ -19104,20 +16153,20 @@ OSERDESE2 #( ) OSERDESE2_38 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[9]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[25]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[9]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[25]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[9]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[25]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[9]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[25]), + .D1(a7ddrphy_dfi_p0_wrdata[9]), + .D2(a7ddrphy_dfi_p0_wrdata[25]), + .D3(a7ddrphy_dfi_p1_wrdata[9]), + .D4(a7ddrphy_dfi_p1_wrdata[25]), + .D5(a7ddrphy_dfi_p2_wrdata[9]), + .D6(a7ddrphy_dfi_p2_wrdata[25]), + .D7(a7ddrphy_dfi_p3_wrdata[9]), + .D8(a7ddrphy_dfi_p3_wrdata[25]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay9), - .TQ(soc_a7ddrphy_dq_t9) + .OQ(a7ddrphy_dq_o_nodelay9), + .TQ(a7ddrphy_dq_t9) ); ISERDESE2 #( @@ -19133,16 +16182,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed9), + .DDLY(a7ddrphy_dq_i_delayed9), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data9[7]), - .Q2(soc_a7ddrphy_dq_i_data9[6]), - .Q3(soc_a7ddrphy_dq_i_data9[5]), - .Q4(soc_a7ddrphy_dq_i_data9[4]), - .Q5(soc_a7ddrphy_dq_i_data9[3]), - .Q6(soc_a7ddrphy_dq_i_data9[2]), - .Q7(soc_a7ddrphy_dq_i_data9[1]), - .Q8(soc_a7ddrphy_dq_i_data9[0]) + .Q1(a7ddrphy_dq_i_data9[7]), + .Q2(a7ddrphy_dq_i_data9[6]), + .Q3(a7ddrphy_dq_i_data9[5]), + .Q4(a7ddrphy_dq_i_data9[4]), + .Q5(a7ddrphy_dq_i_data9[3]), + .Q6(a7ddrphy_dq_i_data9[2]), + .Q7(a7ddrphy_dq_i_data9[1]), + .Q8(a7ddrphy_dq_i_data9[0]) ); IDELAYE2 #( @@ -19156,19 +16205,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_11 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay9), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay9), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed9) + .DATAOUT(a7ddrphy_dq_i_delayed9) ); IOBUF IOBUF_9( - .I(soc_a7ddrphy_dq_o_nodelay9), - .T(soc_a7ddrphy_dq_t9), + .I(a7ddrphy_dq_o_nodelay9), + .T(a7ddrphy_dq_t9), .IO(ddram_dq[9]), - .O(soc_a7ddrphy_dq_i_nodelay9) + .O(a7ddrphy_dq_i_nodelay9) ); OSERDESE2 #( @@ -19180,20 +16229,20 @@ OSERDESE2 #( ) OSERDESE2_39 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[10]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[26]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[10]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[26]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[10]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[26]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[10]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[26]), + .D1(a7ddrphy_dfi_p0_wrdata[10]), + .D2(a7ddrphy_dfi_p0_wrdata[26]), + .D3(a7ddrphy_dfi_p1_wrdata[10]), + .D4(a7ddrphy_dfi_p1_wrdata[26]), + .D5(a7ddrphy_dfi_p2_wrdata[10]), + .D6(a7ddrphy_dfi_p2_wrdata[26]), + .D7(a7ddrphy_dfi_p3_wrdata[10]), + .D8(a7ddrphy_dfi_p3_wrdata[26]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay10), - .TQ(soc_a7ddrphy_dq_t10) + .OQ(a7ddrphy_dq_o_nodelay10), + .TQ(a7ddrphy_dq_t10) ); ISERDESE2 #( @@ -19209,16 +16258,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed10), + .DDLY(a7ddrphy_dq_i_delayed10), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data10[7]), - .Q2(soc_a7ddrphy_dq_i_data10[6]), - .Q3(soc_a7ddrphy_dq_i_data10[5]), - .Q4(soc_a7ddrphy_dq_i_data10[4]), - .Q5(soc_a7ddrphy_dq_i_data10[3]), - .Q6(soc_a7ddrphy_dq_i_data10[2]), - .Q7(soc_a7ddrphy_dq_i_data10[1]), - .Q8(soc_a7ddrphy_dq_i_data10[0]) + .Q1(a7ddrphy_dq_i_data10[7]), + .Q2(a7ddrphy_dq_i_data10[6]), + .Q3(a7ddrphy_dq_i_data10[5]), + .Q4(a7ddrphy_dq_i_data10[4]), + .Q5(a7ddrphy_dq_i_data10[3]), + .Q6(a7ddrphy_dq_i_data10[2]), + .Q7(a7ddrphy_dq_i_data10[1]), + .Q8(a7ddrphy_dq_i_data10[0]) ); IDELAYE2 #( @@ -19232,19 +16281,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_12 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay10), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay10), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed10) + .DATAOUT(a7ddrphy_dq_i_delayed10) ); IOBUF IOBUF_10( - .I(soc_a7ddrphy_dq_o_nodelay10), - .T(soc_a7ddrphy_dq_t10), + .I(a7ddrphy_dq_o_nodelay10), + .T(a7ddrphy_dq_t10), .IO(ddram_dq[10]), - .O(soc_a7ddrphy_dq_i_nodelay10) + .O(a7ddrphy_dq_i_nodelay10) ); OSERDESE2 #( @@ -19256,20 +16305,20 @@ OSERDESE2 #( ) OSERDESE2_40 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[11]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[27]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[11]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[27]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[11]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[27]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[11]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[27]), + .D1(a7ddrphy_dfi_p0_wrdata[11]), + .D2(a7ddrphy_dfi_p0_wrdata[27]), + .D3(a7ddrphy_dfi_p1_wrdata[11]), + .D4(a7ddrphy_dfi_p1_wrdata[27]), + .D5(a7ddrphy_dfi_p2_wrdata[11]), + .D6(a7ddrphy_dfi_p2_wrdata[27]), + .D7(a7ddrphy_dfi_p3_wrdata[11]), + .D8(a7ddrphy_dfi_p3_wrdata[27]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay11), - .TQ(soc_a7ddrphy_dq_t11) + .OQ(a7ddrphy_dq_o_nodelay11), + .TQ(a7ddrphy_dq_t11) ); ISERDESE2 #( @@ -19285,16 +16334,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed11), + .DDLY(a7ddrphy_dq_i_delayed11), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data11[7]), - .Q2(soc_a7ddrphy_dq_i_data11[6]), - .Q3(soc_a7ddrphy_dq_i_data11[5]), - .Q4(soc_a7ddrphy_dq_i_data11[4]), - .Q5(soc_a7ddrphy_dq_i_data11[3]), - .Q6(soc_a7ddrphy_dq_i_data11[2]), - .Q7(soc_a7ddrphy_dq_i_data11[1]), - .Q8(soc_a7ddrphy_dq_i_data11[0]) + .Q1(a7ddrphy_dq_i_data11[7]), + .Q2(a7ddrphy_dq_i_data11[6]), + .Q3(a7ddrphy_dq_i_data11[5]), + .Q4(a7ddrphy_dq_i_data11[4]), + .Q5(a7ddrphy_dq_i_data11[3]), + .Q6(a7ddrphy_dq_i_data11[2]), + .Q7(a7ddrphy_dq_i_data11[1]), + .Q8(a7ddrphy_dq_i_data11[0]) ); IDELAYE2 #( @@ -19308,19 +16357,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_13 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay11), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay11), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed11) + .DATAOUT(a7ddrphy_dq_i_delayed11) ); IOBUF IOBUF_11( - .I(soc_a7ddrphy_dq_o_nodelay11), - .T(soc_a7ddrphy_dq_t11), + .I(a7ddrphy_dq_o_nodelay11), + .T(a7ddrphy_dq_t11), .IO(ddram_dq[11]), - .O(soc_a7ddrphy_dq_i_nodelay11) + .O(a7ddrphy_dq_i_nodelay11) ); OSERDESE2 #( @@ -19332,20 +16381,20 @@ OSERDESE2 #( ) OSERDESE2_41 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[12]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[28]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[12]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[28]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[12]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[28]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[12]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[28]), + .D1(a7ddrphy_dfi_p0_wrdata[12]), + .D2(a7ddrphy_dfi_p0_wrdata[28]), + .D3(a7ddrphy_dfi_p1_wrdata[12]), + .D4(a7ddrphy_dfi_p1_wrdata[28]), + .D5(a7ddrphy_dfi_p2_wrdata[12]), + .D6(a7ddrphy_dfi_p2_wrdata[28]), + .D7(a7ddrphy_dfi_p3_wrdata[12]), + .D8(a7ddrphy_dfi_p3_wrdata[28]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay12), - .TQ(soc_a7ddrphy_dq_t12) + .OQ(a7ddrphy_dq_o_nodelay12), + .TQ(a7ddrphy_dq_t12) ); ISERDESE2 #( @@ -19361,16 +16410,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed12), + .DDLY(a7ddrphy_dq_i_delayed12), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data12[7]), - .Q2(soc_a7ddrphy_dq_i_data12[6]), - .Q3(soc_a7ddrphy_dq_i_data12[5]), - .Q4(soc_a7ddrphy_dq_i_data12[4]), - .Q5(soc_a7ddrphy_dq_i_data12[3]), - .Q6(soc_a7ddrphy_dq_i_data12[2]), - .Q7(soc_a7ddrphy_dq_i_data12[1]), - .Q8(soc_a7ddrphy_dq_i_data12[0]) + .Q1(a7ddrphy_dq_i_data12[7]), + .Q2(a7ddrphy_dq_i_data12[6]), + .Q3(a7ddrphy_dq_i_data12[5]), + .Q4(a7ddrphy_dq_i_data12[4]), + .Q5(a7ddrphy_dq_i_data12[3]), + .Q6(a7ddrphy_dq_i_data12[2]), + .Q7(a7ddrphy_dq_i_data12[1]), + .Q8(a7ddrphy_dq_i_data12[0]) ); IDELAYE2 #( @@ -19384,19 +16433,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_14 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay12), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay12), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed12) + .DATAOUT(a7ddrphy_dq_i_delayed12) ); IOBUF IOBUF_12( - .I(soc_a7ddrphy_dq_o_nodelay12), - .T(soc_a7ddrphy_dq_t12), + .I(a7ddrphy_dq_o_nodelay12), + .T(a7ddrphy_dq_t12), .IO(ddram_dq[12]), - .O(soc_a7ddrphy_dq_i_nodelay12) + .O(a7ddrphy_dq_i_nodelay12) ); OSERDESE2 #( @@ -19408,20 +16457,20 @@ OSERDESE2 #( ) OSERDESE2_42 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[13]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[29]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[13]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[29]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[13]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[29]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[13]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[29]), + .D1(a7ddrphy_dfi_p0_wrdata[13]), + .D2(a7ddrphy_dfi_p0_wrdata[29]), + .D3(a7ddrphy_dfi_p1_wrdata[13]), + .D4(a7ddrphy_dfi_p1_wrdata[29]), + .D5(a7ddrphy_dfi_p2_wrdata[13]), + .D6(a7ddrphy_dfi_p2_wrdata[29]), + .D7(a7ddrphy_dfi_p3_wrdata[13]), + .D8(a7ddrphy_dfi_p3_wrdata[29]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay13), - .TQ(soc_a7ddrphy_dq_t13) + .OQ(a7ddrphy_dq_o_nodelay13), + .TQ(a7ddrphy_dq_t13) ); ISERDESE2 #( @@ -19437,16 +16486,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed13), + .DDLY(a7ddrphy_dq_i_delayed13), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data13[7]), - .Q2(soc_a7ddrphy_dq_i_data13[6]), - .Q3(soc_a7ddrphy_dq_i_data13[5]), - .Q4(soc_a7ddrphy_dq_i_data13[4]), - .Q5(soc_a7ddrphy_dq_i_data13[3]), - .Q6(soc_a7ddrphy_dq_i_data13[2]), - .Q7(soc_a7ddrphy_dq_i_data13[1]), - .Q8(soc_a7ddrphy_dq_i_data13[0]) + .Q1(a7ddrphy_dq_i_data13[7]), + .Q2(a7ddrphy_dq_i_data13[6]), + .Q3(a7ddrphy_dq_i_data13[5]), + .Q4(a7ddrphy_dq_i_data13[4]), + .Q5(a7ddrphy_dq_i_data13[3]), + .Q6(a7ddrphy_dq_i_data13[2]), + .Q7(a7ddrphy_dq_i_data13[1]), + .Q8(a7ddrphy_dq_i_data13[0]) ); IDELAYE2 #( @@ -19460,19 +16509,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_15 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay13), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay13), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed13) + .DATAOUT(a7ddrphy_dq_i_delayed13) ); IOBUF IOBUF_13( - .I(soc_a7ddrphy_dq_o_nodelay13), - .T(soc_a7ddrphy_dq_t13), + .I(a7ddrphy_dq_o_nodelay13), + .T(a7ddrphy_dq_t13), .IO(ddram_dq[13]), - .O(soc_a7ddrphy_dq_i_nodelay13) + .O(a7ddrphy_dq_i_nodelay13) ); OSERDESE2 #( @@ -19484,20 +16533,20 @@ OSERDESE2 #( ) OSERDESE2_43 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[14]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[30]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[14]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[30]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[14]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[30]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[14]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[30]), + .D1(a7ddrphy_dfi_p0_wrdata[14]), + .D2(a7ddrphy_dfi_p0_wrdata[30]), + .D3(a7ddrphy_dfi_p1_wrdata[14]), + .D4(a7ddrphy_dfi_p1_wrdata[30]), + .D5(a7ddrphy_dfi_p2_wrdata[14]), + .D6(a7ddrphy_dfi_p2_wrdata[30]), + .D7(a7ddrphy_dfi_p3_wrdata[14]), + .D8(a7ddrphy_dfi_p3_wrdata[30]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay14), - .TQ(soc_a7ddrphy_dq_t14) + .OQ(a7ddrphy_dq_o_nodelay14), + .TQ(a7ddrphy_dq_t14) ); ISERDESE2 #( @@ -19513,16 +16562,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed14), + .DDLY(a7ddrphy_dq_i_delayed14), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data14[7]), - .Q2(soc_a7ddrphy_dq_i_data14[6]), - .Q3(soc_a7ddrphy_dq_i_data14[5]), - .Q4(soc_a7ddrphy_dq_i_data14[4]), - .Q5(soc_a7ddrphy_dq_i_data14[3]), - .Q6(soc_a7ddrphy_dq_i_data14[2]), - .Q7(soc_a7ddrphy_dq_i_data14[1]), - .Q8(soc_a7ddrphy_dq_i_data14[0]) + .Q1(a7ddrphy_dq_i_data14[7]), + .Q2(a7ddrphy_dq_i_data14[6]), + .Q3(a7ddrphy_dq_i_data14[5]), + .Q4(a7ddrphy_dq_i_data14[4]), + .Q5(a7ddrphy_dq_i_data14[3]), + .Q6(a7ddrphy_dq_i_data14[2]), + .Q7(a7ddrphy_dq_i_data14[1]), + .Q8(a7ddrphy_dq_i_data14[0]) ); IDELAYE2 #( @@ -19536,19 +16585,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_16 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay14), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay14), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed14) + .DATAOUT(a7ddrphy_dq_i_delayed14) ); IOBUF IOBUF_14( - .I(soc_a7ddrphy_dq_o_nodelay14), - .T(soc_a7ddrphy_dq_t14), + .I(a7ddrphy_dq_o_nodelay14), + .T(a7ddrphy_dq_t14), .IO(ddram_dq[14]), - .O(soc_a7ddrphy_dq_i_nodelay14) + .O(a7ddrphy_dq_i_nodelay14) ); OSERDESE2 #( @@ -19560,20 +16609,20 @@ OSERDESE2 #( ) OSERDESE2_44 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[15]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[31]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[15]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[31]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[15]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[31]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[15]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[31]), + .D1(a7ddrphy_dfi_p0_wrdata[15]), + .D2(a7ddrphy_dfi_p0_wrdata[31]), + .D3(a7ddrphy_dfi_p1_wrdata[15]), + .D4(a7ddrphy_dfi_p1_wrdata[31]), + .D5(a7ddrphy_dfi_p2_wrdata[15]), + .D6(a7ddrphy_dfi_p2_wrdata[31]), + .D7(a7ddrphy_dfi_p3_wrdata[15]), + .D8(a7ddrphy_dfi_p3_wrdata[31]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay15), - .TQ(soc_a7ddrphy_dq_t15) + .OQ(a7ddrphy_dq_o_nodelay15), + .TQ(a7ddrphy_dq_t15) ); ISERDESE2 #( @@ -19589,16 +16638,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed15), + .DDLY(a7ddrphy_dq_i_delayed15), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data15[7]), - .Q2(soc_a7ddrphy_dq_i_data15[6]), - .Q3(soc_a7ddrphy_dq_i_data15[5]), - .Q4(soc_a7ddrphy_dq_i_data15[4]), - .Q5(soc_a7ddrphy_dq_i_data15[3]), - .Q6(soc_a7ddrphy_dq_i_data15[2]), - .Q7(soc_a7ddrphy_dq_i_data15[1]), - .Q8(soc_a7ddrphy_dq_i_data15[0]) + .Q1(a7ddrphy_dq_i_data15[7]), + .Q2(a7ddrphy_dq_i_data15[6]), + .Q3(a7ddrphy_dq_i_data15[5]), + .Q4(a7ddrphy_dq_i_data15[4]), + .Q5(a7ddrphy_dq_i_data15[3]), + .Q6(a7ddrphy_dq_i_data15[2]), + .Q7(a7ddrphy_dq_i_data15[1]), + .Q8(a7ddrphy_dq_i_data15[0]) ); IDELAYE2 #( @@ -19612,163 +16661,132 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_17 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay15), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay15), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed15) + .DATAOUT(a7ddrphy_dq_i_delayed15) ); IOBUF IOBUF_15( - .I(soc_a7ddrphy_dq_o_nodelay15), - .T(soc_a7ddrphy_dq_t15), + .I(a7ddrphy_dq_o_nodelay15), + .T(a7ddrphy_dq_t15), .IO(ddram_dq[15]), - .O(soc_a7ddrphy_dq_i_nodelay15) + .O(a7ddrphy_dq_i_nodelay15) ); -reg [23:0] storage_2[0:15]; -reg [23:0] memdat_5; +reg [23:0] storage[0:15]; +reg [23:0] memdat; always @(posedge sys_clk) begin - if (soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we) - storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; - memdat_5 <= storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) + storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; + memdat <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat_5; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; -reg [23:0] storage_3[0:15]; -reg [23:0] memdat_6; +reg [23:0] storage_1[0:15]; +reg [23:0] memdat_1; always @(posedge sys_clk) begin - if (soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we) - storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; - memdat_6 <= storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) + storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; + memdat_1 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_6; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; -reg [23:0] storage_4[0:15]; -reg [23:0] memdat_7; +reg [23:0] storage_2[0:15]; +reg [23:0] memdat_2; always @(posedge sys_clk) begin - if (soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we) - storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; - memdat_7 <= storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) + storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; + memdat_2 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_7; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; -reg [23:0] storage_5[0:15]; -reg [23:0] memdat_8; +reg [23:0] storage_3[0:15]; +reg [23:0] memdat_3; always @(posedge sys_clk) begin - if (soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we) - storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; - memdat_8 <= storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) + storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; + memdat_3 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_8; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; -reg [23:0] storage_6[0:15]; -reg [23:0] memdat_9; +reg [23:0] storage_4[0:15]; +reg [23:0] memdat_4; always @(posedge sys_clk) begin - if (soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we) - storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; - memdat_9 <= storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) + storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; + memdat_4 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_9; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; -reg [23:0] storage_7[0:15]; -reg [23:0] memdat_10; +reg [23:0] storage_5[0:15]; +reg [23:0] memdat_5; always @(posedge sys_clk) begin - if (soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we) - storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; - memdat_10 <= storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) + storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; + memdat_5 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_10; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; -reg [23:0] storage_8[0:15]; -reg [23:0] memdat_11; +reg [23:0] storage_6[0:15]; +reg [23:0] memdat_6; always @(posedge sys_clk) begin - if (soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we) - storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; - memdat_11 <= storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) + storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; + memdat_6 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_11; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; -reg [23:0] storage_9[0:15]; -reg [23:0] memdat_12; +reg [23:0] storage_7[0:15]; +reg [23:0] memdat_7; always @(posedge sys_clk) begin - if (soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we) - storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; - memdat_12 <= storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) + storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; + memdat_7 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_12; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr]; - -VexRiscv VexRiscv( - .clk(sys_clk), - .dBusWishbone_ACK(soc_litedramcore_cpu_dbus_ack), - .dBusWishbone_DAT_MISO(soc_litedramcore_cpu_dbus_dat_r), - .dBusWishbone_ERR(soc_litedramcore_cpu_dbus_err), - .externalInterruptArray(soc_litedramcore_cpu_interrupt), - .externalResetVector(soc_litedramcore_vexriscv), - .iBusWishbone_ACK(soc_litedramcore_cpu_ibus_ack), - .iBusWishbone_DAT_MISO(soc_litedramcore_cpu_ibus_dat_r), - .iBusWishbone_ERR(soc_litedramcore_cpu_ibus_err), - .reset((sys_rst | soc_litedramcore_cpu_reset)), - .softwareInterrupt(1'd0), - .timerInterrupt(1'd0), - .dBusWishbone_ADR(soc_litedramcore_cpu_dbus_adr), - .dBusWishbone_BTE(soc_litedramcore_cpu_dbus_bte), - .dBusWishbone_CTI(soc_litedramcore_cpu_dbus_cti), - .dBusWishbone_CYC(soc_litedramcore_cpu_dbus_cyc), - .dBusWishbone_DAT_MOSI(soc_litedramcore_cpu_dbus_dat_w), - .dBusWishbone_SEL(soc_litedramcore_cpu_dbus_sel), - .dBusWishbone_STB(soc_litedramcore_cpu_dbus_stb), - .dBusWishbone_WE(soc_litedramcore_cpu_dbus_we), - .iBusWishbone_ADR(soc_litedramcore_cpu_ibus_adr), - .iBusWishbone_BTE(soc_litedramcore_cpu_ibus_bte), - .iBusWishbone_CTI(soc_litedramcore_cpu_ibus_cti), - .iBusWishbone_CYC(soc_litedramcore_cpu_ibus_cyc), - .iBusWishbone_DAT_MOSI(soc_litedramcore_cpu_ibus_dat_w), - .iBusWishbone_SEL(soc_litedramcore_cpu_ibus_sel), - .iBusWishbone_STB(soc_litedramcore_cpu_ibus_stb), - .iBusWishbone_WE(soc_litedramcore_cpu_ibus_we) -); +assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; PLLE2_ADV #( .CLKFBOUT_MULT(5'd16), @@ -19783,14 +16801,14 @@ PLLE2_ADV #( .REF_JITTER1(0.01), .STARTUP_WAIT("FALSE") ) PLLE2_ADV ( - .CLKFBIN(vns_pll_fb0), - .CLKIN1(soc_s7pll0_clkin), - .RST(soc_sys_pll_reset), - .CLKFBOUT(vns_pll_fb0), - .CLKOUT0(soc_s7pll0_clkout0), - .CLKOUT1(soc_s7pll0_clkout1), - .CLKOUT2(soc_s7pll0_clkout2), - .LOCKED(soc_sys_pll_locked) + .CLKFBIN(pll_fb0), + .CLKIN1(s7pll0_clkin), + .RST(sys_pll_reset), + .CLKFBOUT(pll_fb0), + .CLKOUT0(s7pll0_clkout0), + .CLKOUT1(s7pll0_clkout1), + .CLKOUT2(s7pll0_clkout2), + .LOCKED(sys_pll_locked) ); PLLE2_ADV #( @@ -19802,12 +16820,12 @@ PLLE2_ADV #( .REF_JITTER1(0.01), .STARTUP_WAIT("FALSE") ) PLLE2_ADV_1 ( - .CLKFBIN(vns_pll_fb1), - .CLKIN1(soc_s7pll1_clkin), - .RST(soc_iodelay_pll_reset), - .CLKFBOUT(vns_pll_fb1), - .CLKOUT0(soc_s7pll1_clkout), - .LOCKED(soc_iodelay_pll_locked) + .CLKFBIN(pll_fb1), + .CLKIN1(s7pll1_clkin), + .RST(iodelay_pll_reset), + .CLKFBOUT(pll_fb1), + .CLKOUT0(s7pll1_clkout), + .LOCKED(iodelay_pll_locked) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( @@ -19816,8 +16834,8 @@ PLLE2_ADV #( .C(sys_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl0), - .Q(vns_xilinxasyncresetsynchronizerimpl0_rst_meta) + .PRE(xilinxasyncresetsynchronizerimpl0), + .Q(xilinxasyncresetsynchronizerimpl0_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -19825,8 +16843,8 @@ PLLE2_ADV #( ) FDPE_1 ( .C(sys_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl0_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl0), + .D(xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl0), .Q(sys_rst) ); @@ -19836,8 +16854,8 @@ PLLE2_ADV #( .C(sys4x_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl1), - .Q(vns_xilinxasyncresetsynchronizerimpl1_rst_meta) + .PRE(xilinxasyncresetsynchronizerimpl1), + .Q(xilinxasyncresetsynchronizerimpl1_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -19845,9 +16863,9 @@ PLLE2_ADV #( ) FDPE_3 ( .C(sys4x_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl1_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl1), - .Q(vns_xilinxasyncresetsynchronizerimpl1_expr) + .D(xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl1), + .Q(xilinxasyncresetsynchronizerimpl1_expr) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( @@ -19856,8 +16874,8 @@ PLLE2_ADV #( .C(sys4x_dqs_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl2), - .Q(vns_xilinxasyncresetsynchronizerimpl2_rst_meta) + .PRE(xilinxasyncresetsynchronizerimpl2), + .Q(xilinxasyncresetsynchronizerimpl2_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -19865,9 +16883,9 @@ PLLE2_ADV #( ) FDPE_5 ( .C(sys4x_dqs_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl2_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl2), - .Q(vns_xilinxasyncresetsynchronizerimpl2_expr) + .D(xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl2), + .Q(xilinxasyncresetsynchronizerimpl2_expr) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( @@ -19876,8 +16894,8 @@ PLLE2_ADV #( .C(iodelay_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl3), - .Q(vns_xilinxasyncresetsynchronizerimpl3_rst_meta) + .PRE(xilinxasyncresetsynchronizerimpl3), + .Q(xilinxasyncresetsynchronizerimpl3_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -19885,8 +16903,8 @@ PLLE2_ADV #( ) FDPE_7 ( .C(iodelay_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl3_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl3), + .D(xilinxasyncresetsynchronizerimpl3_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl3), .Q(iodelay_rst) ); diff --git a/litedram/generated/nexys-video/init-cpu.txt b/litedram/generated/nexys-video/init-cpu.txt deleted file mode 100644 index b0b6e79..0000000 --- a/litedram/generated/nexys-video/init-cpu.txt +++ /dev/null @@ -1 +0,0 @@ -vexriscv \ No newline at end of file diff --git a/litedram/generated/nexys-video/litedram-wrapper.vhdl b/litedram/generated/nexys-video/litedram-wrapper.vhdl index 0664866..475e088 100644 --- a/litedram/generated/nexys-video/litedram-wrapper.vhdl +++ b/litedram/generated/nexys-video/litedram-wrapper.vhdl @@ -60,8 +60,6 @@ architecture behaviour of litedram_wrapper is component litedram_core port ( clk : in std_ulogic; rst : in std_ulogic; - serial_tx : out std_ulogic; - serial_rx : in std_ulogic; pll_locked : out std_ulogic; ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); ddram_ba : out std_ulogic_vector(2 downto 0); @@ -82,6 +80,10 @@ architecture behaviour of litedram_wrapper is init_error : out std_ulogic; user_clk : out std_ulogic; user_rst : out std_ulogic; + csr_port0_adr : in std_ulogic_vector(13 downto 0); + csr_port0_we : in std_ulogic; + csr_port0_dat_w : in std_ulogic_vector(7 downto 0); + csr_port0_dat_r : out std_ulogic_vector(7 downto 0); user_port_native_0_cmd_valid : in std_ulogic; user_port_native_0_cmd_ready : out std_ulogic; user_port_native_0_cmd_we : in std_ulogic; @@ -112,17 +114,84 @@ architecture behaviour of litedram_wrapper is signal dram_user_reset : std_ulogic; - type state_t is (CMD, MWRITE, MREAD); + signal csr_port0_adr : std_ulogic_vector(13 downto 0); + signal csr_port0_we : std_ulogic; + signal csr_port0_dat_w : std_ulogic_vector(7 downto 0); + signal csr_port0_dat_r : std_ulogic_vector(7 downto 0); + signal csr_port_read_comb : std_ulogic_vector(63 downto 0); + signal csr_valid : std_ulogic; + signal csr_write_valid : std_ulogic; + + signal wb_init_in : wishbone_master_out; + signal wb_init_out : wishbone_slave_out; + + type state_t is (CMD, MWRITE, MREAD, CSR); signal state : state_t; + constant INIT_RAM_SIZE : integer := 16384; + constant INIT_RAM_ABITS :integer := 14; + constant INIT_RAM_FILE : string := "litedram_core.init"; + + type ram_t is array(0 to (INIT_RAM_SIZE / 8) - 1) of std_logic_vector(63 downto 0); + + impure function init_load_ram(name : string) return ram_t is + file ram_file : text open read_mode is name; + variable temp_word : std_logic_vector(63 downto 0); + variable temp_ram : ram_t := (others => (others => '0')); + variable ram_line : line; + begin + for i in 0 to (INIT_RAM_SIZE/8)-1 loop + exit when endfile(ram_file); + readline(ram_file, ram_line); + hread(ram_line, temp_word); + temp_ram(i) := temp_word; + end loop; + return temp_ram; + end function; + + signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE); + + attribute ram_style : string; + attribute ram_style of init_ram: signal is "block"; + begin - -- Address bit 3 selects the top or bottom half of the data + -- BRAM Memory slave + init_ram_0: process(system_clk) + variable adr : integer; + begin + if rising_edge(system_clk) then + wb_init_out.ack <= '0'; + if (wb_init_in.cyc and wb_init_in.stb) = '1' then + adr := to_integer((unsigned(wb_init_in.adr(INIT_RAM_ABITS-1 downto 3)))); + if wb_init_in.we = '0' then + wb_init_out.dat <= init_ram(adr); + else + for i in 0 to 7 loop + if wb_init_in.sel(i) = '1' then + init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= + wb_init_in.dat(((i + 1) * 8) - 1 downto i * 8); + end if; + end loop; + end if; + wb_init_out.ack <= not wb_init_out.ack; + end if; + end if; + end process; + + wb_init_in.adr <= wb_in.adr; + wb_init_in.dat <= wb_in.dat; + wb_init_in.sel <= wb_in.sel; + wb_init_in.we <= wb_in.we; + wb_init_in.stb <= wb_in.stb; + wb_init_in.cyc <= wb_in.cyc and wb_is_init; + + -- Address bit 3 selects the top or bottom half of the data -- bus (64-bit wishbone vs. 128-bit DRAM interface) -- ad3 <= wb_in.adr(3); - -- DRAM interface signals + -- DRAM data interface signals user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init) when state = CMD else '0'; user_port0_cmd_we <= wb_in.we when state = CMD else '0'; @@ -133,18 +202,32 @@ begin user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else "00000000" & wb_in.sel; - -- Wishbone out signals. CSR and init memory do nothing, just ack - wb_out.ack <= '1' when (wb_is_csr = '1' or wb_is_init = '1') else + -- DRAM CSR interface signals. We only support access to the bottom byte + csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; + csr_write_valid <= wb_in.we and wb_in.sel(0); + csr_port0_adr <= wb_in.adr(13 downto 0) when wb_is_csr = '1' else (others => '0'); + csr_port0_dat_w <= wb_in.dat(7 downto 0); + csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; + + -- Wishbone out signals + wb_out.ack <= '1' when state = CSR else + wb_init_out.ack when wb_is_init = '1' else user_port0_wdata_ready when state = MWRITE else user_port0_rdata_valid when state = MREAD else '0'; - wb_out.dat <= (others => '0') when (wb_is_csr = '1' or wb_is_init = '1') else + + csr_port_read_comb <= x"00000000000000" & csr_port0_dat_r; + wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else + wb_init_out.dat when wb_is_init = '1' else user_port0_rdata_data(127 downto 64) when ad3 = '1' else user_port0_rdata_data(63 downto 0); + -- We don't do pipelining yet. wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack; - -- Reset, lift it when init done, no alt core reset - system_reset <= dram_user_reset or not init_done; - core_alt_reset <= '0'; + -- Reset ignored, the reset controller use the pll lock signal, + -- and alternate core reset address set when DRAM is not initialized. + -- + system_reset <= '0'; + core_alt_reset <= not init_done; -- State machine sm: process(system_clk) @@ -156,7 +239,9 @@ begin else case state is when CMD => - if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then + if csr_valid = '1' then + state <= CSR; + elsif (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then state <= MWRITE when wb_in.we = '1' else MREAD; end if; when MWRITE => @@ -167,6 +252,8 @@ begin if user_port0_rdata_valid = '1' then state <= CMD; end if; + when CSR => + state <= CMD; end case; end if; end if; @@ -176,8 +263,6 @@ begin port map( clk => clk_in, rst => rst, - serial_tx => serial_tx, - serial_rx => serial_rx, pll_locked => pll_locked, ddram_a => ddram_a, ddram_ba => ddram_ba, @@ -198,6 +283,10 @@ begin init_error => init_error, user_clk => system_clk, user_rst => dram_user_reset, + csr_port0_adr => csr_port0_adr, + csr_port0_we => csr_port0_we, + csr_port0_dat_w => csr_port0_dat_w, + csr_port0_dat_r => csr_port0_dat_r, user_port_native_0_cmd_valid => user_port0_cmd_valid, user_port_native_0_cmd_ready => user_port0_cmd_ready, user_port_native_0_cmd_we => user_port0_cmd_we, diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init index b1daa3c..d07879f 100644 --- a/litedram/generated/nexys-video/litedram_core.init +++ b/litedram/generated/nexys-video/litedram_core.init @@ -1,5817 +1,1448 @@ -b00006f -13 -13 -13 -13 -13 -13 -13 -fe112e23 -fe512c23 -fe612a23 -fe712823 -fea12623 -feb12423 -fec12223 -fed12023 -fce12e23 -fcf12c23 -fd012a23 -fd112823 -fdc12623 -fdd12423 -fde12223 -fdf12023 -fc010113 -94000ef -3c12083 -3812283 -3412303 -3012383 -2c12503 -2812583 -2412603 -2012683 -1c12703 -1812783 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+ffffffffffffffff +0000000000007830 diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v index b1c8965..dd74efd 100644 --- a/litedram/generated/nexys-video/litedram_core.v +++ b/litedram/generated/nexys-video/litedram_core.v @@ -1,9 +1,7 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (dc9cfe6) & LiteX (79ee135f) on 2020-05-08 01:29:22 +// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 10:54:05 //-------------------------------------------------------------------------------- module litedram_core( - output reg serial_tx, - input wire serial_rx, input wire clk, input wire rst, output wire pll_locked, @@ -24,6 +22,10 @@ module litedram_core( output wire ddram_reset_n, output wire init_done, output wire init_error, + input wire [13:0] csr_port0_adr, + input wire csr_port0_we, + input wire [7:0] csr_port0_dat_w, + output wire [7:0] csr_port0_dat_r, output wire user_clk, output wire user_rst, input wire user_port_native_0_cmd_valid, @@ -39,2520 +41,2000 @@ module litedram_core( output wire [127:0] user_port_native_0_rdata_data ); -reg soc_litedramcore_soccontroller_reset_storage = 1'd0; -reg soc_litedramcore_soccontroller_reset_re = 1'd0; -reg [31:0] soc_litedramcore_soccontroller_scratch_storage = 32'd305419896; -reg soc_litedramcore_soccontroller_scratch_re = 1'd0; -wire [31:0] soc_litedramcore_soccontroller_bus_errors_status; -wire soc_litedramcore_soccontroller_bus_errors_we; -wire soc_litedramcore_soccontroller_reset; -wire soc_litedramcore_soccontroller_bus_error; -reg [31:0] soc_litedramcore_soccontroller_bus_errors = 32'd0; -wire soc_litedramcore_cpu_reset; -reg [31:0] soc_litedramcore_cpu_interrupt = 32'd0; -wire [29:0] soc_litedramcore_cpu_ibus_adr; -wire [31:0] soc_litedramcore_cpu_ibus_dat_w; -wire [31:0] soc_litedramcore_cpu_ibus_dat_r; -wire [3:0] soc_litedramcore_cpu_ibus_sel; -wire soc_litedramcore_cpu_ibus_cyc; -wire soc_litedramcore_cpu_ibus_stb; -wire soc_litedramcore_cpu_ibus_ack; -wire soc_litedramcore_cpu_ibus_we; -wire [2:0] soc_litedramcore_cpu_ibus_cti; -wire [1:0] soc_litedramcore_cpu_ibus_bte; -wire soc_litedramcore_cpu_ibus_err; -wire [29:0] soc_litedramcore_cpu_dbus_adr; -wire [31:0] soc_litedramcore_cpu_dbus_dat_w; -wire [31:0] soc_litedramcore_cpu_dbus_dat_r; -wire [3:0] soc_litedramcore_cpu_dbus_sel; -wire soc_litedramcore_cpu_dbus_cyc; -wire soc_litedramcore_cpu_dbus_stb; -wire soc_litedramcore_cpu_dbus_ack; -wire soc_litedramcore_cpu_dbus_we; -wire [2:0] soc_litedramcore_cpu_dbus_cti; -wire [1:0] soc_litedramcore_cpu_dbus_bte; -wire soc_litedramcore_cpu_dbus_err; -reg [31:0] soc_litedramcore_vexriscv = 32'd0; -wire [29:0] soc_litedramcore_litedramcore_ram_bus_adr; -wire [31:0] soc_litedramcore_litedramcore_ram_bus_dat_w; -wire [31:0] soc_litedramcore_litedramcore_ram_bus_dat_r; -wire [3:0] soc_litedramcore_litedramcore_ram_bus_sel; -wire soc_litedramcore_litedramcore_ram_bus_cyc; -wire soc_litedramcore_litedramcore_ram_bus_stb; -reg soc_litedramcore_litedramcore_ram_bus_ack = 1'd0; -wire soc_litedramcore_litedramcore_ram_bus_we; -wire [2:0] soc_litedramcore_litedramcore_ram_bus_cti; -wire [1:0] soc_litedramcore_litedramcore_ram_bus_bte; -reg soc_litedramcore_litedramcore_ram_bus_err = 1'd0; -wire [12:0] soc_litedramcore_litedramcore_adr; -wire [31:0] soc_litedramcore_litedramcore_dat_r; -wire [29:0] soc_litedramcore_ram_bus_ram_bus_adr; -wire [31:0] soc_litedramcore_ram_bus_ram_bus_dat_w; -wire [31:0] soc_litedramcore_ram_bus_ram_bus_dat_r; -wire [3:0] soc_litedramcore_ram_bus_ram_bus_sel; -wire soc_litedramcore_ram_bus_ram_bus_cyc; -wire soc_litedramcore_ram_bus_ram_bus_stb; -reg soc_litedramcore_ram_bus_ram_bus_ack = 1'd0; -wire soc_litedramcore_ram_bus_ram_bus_we; -wire [2:0] soc_litedramcore_ram_bus_ram_bus_cti; -wire [1:0] soc_litedramcore_ram_bus_ram_bus_bte; -reg soc_litedramcore_ram_bus_ram_bus_err = 1'd0; -wire [9:0] soc_litedramcore_ram_adr; -wire [31:0] soc_litedramcore_ram_dat_r; -reg [3:0] soc_litedramcore_ram_we = 4'd0; -wire [31:0] soc_litedramcore_ram_dat_w; -reg [31:0] soc_litedramcore_storage = 32'd4947802; -reg soc_litedramcore_re = 1'd0; -wire soc_litedramcore_sink_valid; -reg soc_litedramcore_sink_ready = 1'd0; -wire soc_litedramcore_sink_first; -wire soc_litedramcore_sink_last; -wire [7:0] soc_litedramcore_sink_payload_data; -reg soc_litedramcore_uart_clk_txen = 1'd0; -reg [31:0] soc_litedramcore_phase_accumulator_tx = 32'd0; -reg [7:0] soc_litedramcore_tx_reg = 8'd0; -reg [3:0] soc_litedramcore_tx_bitcount = 4'd0; -reg soc_litedramcore_tx_busy = 1'd0; -reg soc_litedramcore_source_valid = 1'd0; -wire soc_litedramcore_source_ready; -reg soc_litedramcore_source_first = 1'd0; -reg soc_litedramcore_source_last = 1'd0; -reg [7:0] soc_litedramcore_source_payload_data = 8'd0; -reg soc_litedramcore_uart_clk_rxen = 1'd0; -reg [31:0] soc_litedramcore_phase_accumulator_rx = 32'd0; -wire soc_litedramcore_rx; -reg soc_litedramcore_rx_r = 1'd0; -reg [7:0] soc_litedramcore_rx_reg = 8'd0; -reg [3:0] soc_litedramcore_rx_bitcount = 4'd0; -reg soc_litedramcore_rx_busy = 1'd0; -wire soc_litedramcore_uart_rxtx_re; -wire [7:0] soc_litedramcore_uart_rxtx_r; -wire soc_litedramcore_uart_rxtx_we; -wire [7:0] soc_litedramcore_uart_rxtx_w; -wire soc_litedramcore_uart_txfull_status; -wire soc_litedramcore_uart_txfull_we; -wire soc_litedramcore_uart_rxempty_status; -wire soc_litedramcore_uart_rxempty_we; -wire soc_litedramcore_uart_irq; -wire soc_litedramcore_uart_tx_status; -reg soc_litedramcore_uart_tx_pending = 1'd0; -wire soc_litedramcore_uart_tx_trigger; -reg soc_litedramcore_uart_tx_clear = 1'd0; -reg soc_litedramcore_uart_tx_old_trigger = 1'd0; -wire soc_litedramcore_uart_rx_status; -reg soc_litedramcore_uart_rx_pending = 1'd0; -wire soc_litedramcore_uart_rx_trigger; -reg soc_litedramcore_uart_rx_clear = 1'd0; -reg soc_litedramcore_uart_rx_old_trigger = 1'd0; -wire soc_litedramcore_uart_eventmanager_status_re; -wire [1:0] soc_litedramcore_uart_eventmanager_status_r; -wire soc_litedramcore_uart_eventmanager_status_we; -reg [1:0] soc_litedramcore_uart_eventmanager_status_w = 2'd0; -wire soc_litedramcore_uart_eventmanager_pending_re; -wire [1:0] soc_litedramcore_uart_eventmanager_pending_r; -wire soc_litedramcore_uart_eventmanager_pending_we; -reg [1:0] soc_litedramcore_uart_eventmanager_pending_w = 2'd0; -reg [1:0] soc_litedramcore_uart_eventmanager_storage = 2'd0; -reg soc_litedramcore_uart_eventmanager_re = 1'd0; -wire soc_litedramcore_uart_uart_sink_valid; -wire soc_litedramcore_uart_uart_sink_ready; -wire soc_litedramcore_uart_uart_sink_first; -wire soc_litedramcore_uart_uart_sink_last; -wire [7:0] soc_litedramcore_uart_uart_sink_payload_data; -wire soc_litedramcore_uart_uart_source_valid; -wire soc_litedramcore_uart_uart_source_ready; -wire soc_litedramcore_uart_uart_source_first; -wire soc_litedramcore_uart_uart_source_last; -wire [7:0] soc_litedramcore_uart_uart_source_payload_data; -wire soc_litedramcore_uart_tx_fifo_sink_valid; -wire soc_litedramcore_uart_tx_fifo_sink_ready; -reg soc_litedramcore_uart_tx_fifo_sink_first = 1'd0; -reg soc_litedramcore_uart_tx_fifo_sink_last = 1'd0; -wire [7:0] soc_litedramcore_uart_tx_fifo_sink_payload_data; -wire soc_litedramcore_uart_tx_fifo_source_valid; -wire soc_litedramcore_uart_tx_fifo_source_ready; -wire soc_litedramcore_uart_tx_fifo_source_first; -wire soc_litedramcore_uart_tx_fifo_source_last; -wire [7:0] soc_litedramcore_uart_tx_fifo_source_payload_data; -wire soc_litedramcore_uart_tx_fifo_re; -reg soc_litedramcore_uart_tx_fifo_readable = 1'd0; -wire soc_litedramcore_uart_tx_fifo_syncfifo_we; -wire soc_litedramcore_uart_tx_fifo_syncfifo_writable; -wire soc_litedramcore_uart_tx_fifo_syncfifo_re; -wire soc_litedramcore_uart_tx_fifo_syncfifo_readable; -wire [9:0] soc_litedramcore_uart_tx_fifo_syncfifo_din; -wire [9:0] soc_litedramcore_uart_tx_fifo_syncfifo_dout; -reg [4:0] soc_litedramcore_uart_tx_fifo_level0 = 5'd0; -reg soc_litedramcore_uart_tx_fifo_replace = 1'd0; -reg [3:0] soc_litedramcore_uart_tx_fifo_produce = 4'd0; -reg [3:0] soc_litedramcore_uart_tx_fifo_consume = 4'd0; -reg [3:0] soc_litedramcore_uart_tx_fifo_wrport_adr = 4'd0; -wire [9:0] soc_litedramcore_uart_tx_fifo_wrport_dat_r; -wire soc_litedramcore_uart_tx_fifo_wrport_we; -wire [9:0] soc_litedramcore_uart_tx_fifo_wrport_dat_w; -wire soc_litedramcore_uart_tx_fifo_do_read; -wire [3:0] soc_litedramcore_uart_tx_fifo_rdport_adr; -wire [9:0] soc_litedramcore_uart_tx_fifo_rdport_dat_r; -wire soc_litedramcore_uart_tx_fifo_rdport_re; -wire [4:0] soc_litedramcore_uart_tx_fifo_level1; -wire [7:0] soc_litedramcore_uart_tx_fifo_fifo_in_payload_data; -wire soc_litedramcore_uart_tx_fifo_fifo_in_first; -wire soc_litedramcore_uart_tx_fifo_fifo_in_last; -wire [7:0] soc_litedramcore_uart_tx_fifo_fifo_out_payload_data; -wire soc_litedramcore_uart_tx_fifo_fifo_out_first; -wire soc_litedramcore_uart_tx_fifo_fifo_out_last; -wire soc_litedramcore_uart_rx_fifo_sink_valid; -wire soc_litedramcore_uart_rx_fifo_sink_ready; -wire soc_litedramcore_uart_rx_fifo_sink_first; -wire soc_litedramcore_uart_rx_fifo_sink_last; -wire [7:0] soc_litedramcore_uart_rx_fifo_sink_payload_data; -wire soc_litedramcore_uart_rx_fifo_source_valid; -wire soc_litedramcore_uart_rx_fifo_source_ready; -wire soc_litedramcore_uart_rx_fifo_source_first; -wire soc_litedramcore_uart_rx_fifo_source_last; -wire [7:0] soc_litedramcore_uart_rx_fifo_source_payload_data; -wire soc_litedramcore_uart_rx_fifo_re; -reg soc_litedramcore_uart_rx_fifo_readable = 1'd0; -wire soc_litedramcore_uart_rx_fifo_syncfifo_we; -wire soc_litedramcore_uart_rx_fifo_syncfifo_writable; -wire soc_litedramcore_uart_rx_fifo_syncfifo_re; -wire soc_litedramcore_uart_rx_fifo_syncfifo_readable; -wire [9:0] soc_litedramcore_uart_rx_fifo_syncfifo_din; -wire [9:0] soc_litedramcore_uart_rx_fifo_syncfifo_dout; -reg [4:0] soc_litedramcore_uart_rx_fifo_level0 = 5'd0; -reg soc_litedramcore_uart_rx_fifo_replace = 1'd0; -reg [3:0] soc_litedramcore_uart_rx_fifo_produce = 4'd0; -reg [3:0] soc_litedramcore_uart_rx_fifo_consume = 4'd0; -reg [3:0] soc_litedramcore_uart_rx_fifo_wrport_adr = 4'd0; -wire [9:0] soc_litedramcore_uart_rx_fifo_wrport_dat_r; -wire soc_litedramcore_uart_rx_fifo_wrport_we; -wire [9:0] soc_litedramcore_uart_rx_fifo_wrport_dat_w; -wire soc_litedramcore_uart_rx_fifo_do_read; -wire [3:0] soc_litedramcore_uart_rx_fifo_rdport_adr; -wire [9:0] soc_litedramcore_uart_rx_fifo_rdport_dat_r; -wire soc_litedramcore_uart_rx_fifo_rdport_re; -wire [4:0] soc_litedramcore_uart_rx_fifo_level1; -wire [7:0] soc_litedramcore_uart_rx_fifo_fifo_in_payload_data; -wire soc_litedramcore_uart_rx_fifo_fifo_in_first; -wire soc_litedramcore_uart_rx_fifo_fifo_in_last; -wire [7:0] soc_litedramcore_uart_rx_fifo_fifo_out_payload_data; -wire soc_litedramcore_uart_rx_fifo_fifo_out_first; -wire soc_litedramcore_uart_rx_fifo_fifo_out_last; -reg soc_litedramcore_uart_reset = 1'd0; -reg [31:0] soc_litedramcore_timer_load_storage = 32'd0; -reg soc_litedramcore_timer_load_re = 1'd0; -reg [31:0] soc_litedramcore_timer_reload_storage = 32'd0; -reg soc_litedramcore_timer_reload_re = 1'd0; -reg soc_litedramcore_timer_en_storage = 1'd0; -reg soc_litedramcore_timer_en_re = 1'd0; -reg soc_litedramcore_timer_update_value_storage = 1'd0; -reg soc_litedramcore_timer_update_value_re = 1'd0; -reg [31:0] soc_litedramcore_timer_value_status = 32'd0; -wire soc_litedramcore_timer_value_we; -wire soc_litedramcore_timer_irq; -wire soc_litedramcore_timer_zero_status; -reg soc_litedramcore_timer_zero_pending = 1'd0; -wire soc_litedramcore_timer_zero_trigger; -reg soc_litedramcore_timer_zero_clear = 1'd0; -reg soc_litedramcore_timer_zero_old_trigger = 1'd0; -wire soc_litedramcore_timer_eventmanager_status_re; -wire soc_litedramcore_timer_eventmanager_status_r; -wire soc_litedramcore_timer_eventmanager_status_we; -wire soc_litedramcore_timer_eventmanager_status_w; -wire soc_litedramcore_timer_eventmanager_pending_re; -wire soc_litedramcore_timer_eventmanager_pending_r; -wire soc_litedramcore_timer_eventmanager_pending_we; -wire soc_litedramcore_timer_eventmanager_pending_w; -reg soc_litedramcore_timer_eventmanager_storage = 1'd0; -reg soc_litedramcore_timer_eventmanager_re = 1'd0; -reg [31:0] soc_litedramcore_timer_value = 32'd0; -reg [13:0] soc_litedramcore_interface_adr = 14'd0; -reg soc_litedramcore_interface_we = 1'd0; -wire [7:0] soc_litedramcore_interface_dat_w; -wire [7:0] soc_litedramcore_interface_dat_r; -wire [29:0] soc_litedramcore_bus_wishbone_adr; -wire [31:0] soc_litedramcore_bus_wishbone_dat_w; -wire [31:0] soc_litedramcore_bus_wishbone_dat_r; -wire [3:0] soc_litedramcore_bus_wishbone_sel; -wire soc_litedramcore_bus_wishbone_cyc; -wire soc_litedramcore_bus_wishbone_stb; -reg soc_litedramcore_bus_wishbone_ack = 1'd0; -wire soc_litedramcore_bus_wishbone_we; -wire [2:0] soc_litedramcore_bus_wishbone_cti; -wire [1:0] soc_litedramcore_bus_wishbone_bte; -reg soc_litedramcore_bus_wishbone_err = 1'd0; wire sys_clk; wire sys_rst; wire sys4x_clk; wire sys4x_dqs_clk; wire iodelay_clk; wire iodelay_rst; -wire soc_sys_pll_reset; -wire soc_sys_pll_locked; -wire soc_s7pll0_clkin; -wire soc_s7pll0_clkout0; -wire soc_s7pll0_clkout_buf0; -wire soc_s7pll0_clkout1; -wire soc_s7pll0_clkout_buf1; -wire soc_s7pll0_clkout2; -wire soc_s7pll0_clkout_buf2; -wire soc_iodelay_pll_reset; -wire soc_iodelay_pll_locked; -wire soc_s7pll1_clkin; -wire soc_s7pll1_clkout; -wire soc_s7pll1_clkout_buf; -reg [3:0] soc_reset_counter = 4'd15; -reg soc_ic_reset = 1'd1; -reg [4:0] soc_a7ddrphy_half_sys8x_taps_storage = 5'd8; -reg soc_a7ddrphy_half_sys8x_taps_re = 1'd0; -reg soc_a7ddrphy_wlevel_en_storage = 1'd0; -reg soc_a7ddrphy_wlevel_en_re = 1'd0; -wire soc_a7ddrphy_wlevel_strobe_re; -wire soc_a7ddrphy_wlevel_strobe_r; -wire soc_a7ddrphy_wlevel_strobe_we; -reg soc_a7ddrphy_wlevel_strobe_w = 1'd0; -wire soc_a7ddrphy_cdly_rst_re; -wire soc_a7ddrphy_cdly_rst_r; -wire soc_a7ddrphy_cdly_rst_we; -reg soc_a7ddrphy_cdly_rst_w = 1'd0; -wire soc_a7ddrphy_cdly_inc_re; -wire soc_a7ddrphy_cdly_inc_r; -wire soc_a7ddrphy_cdly_inc_we; -reg soc_a7ddrphy_cdly_inc_w = 1'd0; -reg [1:0] soc_a7ddrphy_dly_sel_storage = 2'd0; -reg soc_a7ddrphy_dly_sel_re = 1'd0; -wire soc_a7ddrphy_rdly_dq_rst_re; -wire soc_a7ddrphy_rdly_dq_rst_r; -wire soc_a7ddrphy_rdly_dq_rst_we; -reg soc_a7ddrphy_rdly_dq_rst_w = 1'd0; -wire soc_a7ddrphy_rdly_dq_inc_re; -wire soc_a7ddrphy_rdly_dq_inc_r; -wire soc_a7ddrphy_rdly_dq_inc_we; -reg soc_a7ddrphy_rdly_dq_inc_w = 1'd0; -wire soc_a7ddrphy_rdly_dq_bitslip_rst_re; -wire soc_a7ddrphy_rdly_dq_bitslip_rst_r; -wire soc_a7ddrphy_rdly_dq_bitslip_rst_we; -reg soc_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -wire soc_a7ddrphy_rdly_dq_bitslip_re; -wire soc_a7ddrphy_rdly_dq_bitslip_r; -wire soc_a7ddrphy_rdly_dq_bitslip_we; -reg soc_a7ddrphy_rdly_dq_bitslip_w = 1'd0; -wire [14:0] soc_a7ddrphy_dfi_p0_address; -wire [2:0] soc_a7ddrphy_dfi_p0_bank; -wire soc_a7ddrphy_dfi_p0_cas_n; -wire soc_a7ddrphy_dfi_p0_cs_n; -wire soc_a7ddrphy_dfi_p0_ras_n; -wire soc_a7ddrphy_dfi_p0_we_n; -wire soc_a7ddrphy_dfi_p0_cke; -wire soc_a7ddrphy_dfi_p0_odt; -wire soc_a7ddrphy_dfi_p0_reset_n; -wire soc_a7ddrphy_dfi_p0_act_n; -wire [31:0] soc_a7ddrphy_dfi_p0_wrdata; -wire soc_a7ddrphy_dfi_p0_wrdata_en; -wire [3:0] soc_a7ddrphy_dfi_p0_wrdata_mask; -wire soc_a7ddrphy_dfi_p0_rddata_en; -reg [31:0] soc_a7ddrphy_dfi_p0_rddata = 32'd0; -reg soc_a7ddrphy_dfi_p0_rddata_valid = 1'd0; -wire [14:0] soc_a7ddrphy_dfi_p1_address; -wire [2:0] soc_a7ddrphy_dfi_p1_bank; -wire soc_a7ddrphy_dfi_p1_cas_n; -wire soc_a7ddrphy_dfi_p1_cs_n; -wire soc_a7ddrphy_dfi_p1_ras_n; -wire soc_a7ddrphy_dfi_p1_we_n; -wire soc_a7ddrphy_dfi_p1_cke; -wire soc_a7ddrphy_dfi_p1_odt; -wire soc_a7ddrphy_dfi_p1_reset_n; -wire soc_a7ddrphy_dfi_p1_act_n; -wire [31:0] soc_a7ddrphy_dfi_p1_wrdata; -wire soc_a7ddrphy_dfi_p1_wrdata_en; -wire [3:0] soc_a7ddrphy_dfi_p1_wrdata_mask; -wire soc_a7ddrphy_dfi_p1_rddata_en; -reg [31:0] soc_a7ddrphy_dfi_p1_rddata = 32'd0; -reg soc_a7ddrphy_dfi_p1_rddata_valid = 1'd0; -wire [14:0] soc_a7ddrphy_dfi_p2_address; -wire [2:0] soc_a7ddrphy_dfi_p2_bank; -wire soc_a7ddrphy_dfi_p2_cas_n; -wire soc_a7ddrphy_dfi_p2_cs_n; -wire soc_a7ddrphy_dfi_p2_ras_n; -wire soc_a7ddrphy_dfi_p2_we_n; -wire soc_a7ddrphy_dfi_p2_cke; -wire soc_a7ddrphy_dfi_p2_odt; -wire soc_a7ddrphy_dfi_p2_reset_n; -wire soc_a7ddrphy_dfi_p2_act_n; -wire [31:0] soc_a7ddrphy_dfi_p2_wrdata; -wire soc_a7ddrphy_dfi_p2_wrdata_en; -wire [3:0] soc_a7ddrphy_dfi_p2_wrdata_mask; -wire soc_a7ddrphy_dfi_p2_rddata_en; -reg [31:0] soc_a7ddrphy_dfi_p2_rddata = 32'd0; -reg soc_a7ddrphy_dfi_p2_rddata_valid = 1'd0; -wire [14:0] soc_a7ddrphy_dfi_p3_address; -wire [2:0] soc_a7ddrphy_dfi_p3_bank; -wire soc_a7ddrphy_dfi_p3_cas_n; -wire soc_a7ddrphy_dfi_p3_cs_n; -wire soc_a7ddrphy_dfi_p3_ras_n; -wire soc_a7ddrphy_dfi_p3_we_n; -wire soc_a7ddrphy_dfi_p3_cke; -wire soc_a7ddrphy_dfi_p3_odt; -wire soc_a7ddrphy_dfi_p3_reset_n; -wire soc_a7ddrphy_dfi_p3_act_n; -wire [31:0] soc_a7ddrphy_dfi_p3_wrdata; -wire soc_a7ddrphy_dfi_p3_wrdata_en; -wire [3:0] soc_a7ddrphy_dfi_p3_wrdata_mask; -wire soc_a7ddrphy_dfi_p3_rddata_en; -reg [31:0] soc_a7ddrphy_dfi_p3_rddata = 32'd0; -reg soc_a7ddrphy_dfi_p3_rddata_valid = 1'd0; -wire soc_a7ddrphy_sd_clk_se_nodelay; -reg soc_a7ddrphy_dqs_oe = 1'd0; -reg soc_a7ddrphy_dqs_oe_delayed = 1'd0; -wire soc_a7ddrphy_dqspattern0; -wire soc_a7ddrphy_dqspattern1; -reg [7:0] soc_a7ddrphy_dqspattern_o0 = 8'd0; -reg [7:0] soc_a7ddrphy_dqspattern_o1 = 8'd0; -wire [1:0] soc_a7ddrphy_dqs_i; -wire [1:0] soc_a7ddrphy_dqs_i_delayed; -wire soc_a7ddrphy_dqs_o_no_delay0; -wire soc_a7ddrphy_dqs_t0; -wire soc_a7ddrphy0; -wire soc_a7ddrphy_dqs_o_no_delay1; -wire soc_a7ddrphy_dqs_t1; -wire soc_a7ddrphy1; -wire soc_a7ddrphy_dq_oe; -reg soc_a7ddrphy_dq_oe_delayed = 1'd0; -wire soc_a7ddrphy_dq_o_nodelay0; -wire soc_a7ddrphy_dq_i_nodelay0; -wire soc_a7ddrphy_dq_i_delayed0; -wire soc_a7ddrphy_dq_t0; -wire [7:0] soc_a7ddrphy_dq_i_data0; -wire [7:0] soc_a7ddrphy_bitslip0_i; -reg [7:0] soc_a7ddrphy_bitslip0_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip0_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip0_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay1; -wire soc_a7ddrphy_dq_i_nodelay1; -wire soc_a7ddrphy_dq_i_delayed1; -wire soc_a7ddrphy_dq_t1; -wire [7:0] soc_a7ddrphy_dq_i_data1; -wire [7:0] soc_a7ddrphy_bitslip1_i; -reg [7:0] soc_a7ddrphy_bitslip1_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip1_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip1_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay2; -wire soc_a7ddrphy_dq_i_nodelay2; -wire soc_a7ddrphy_dq_i_delayed2; -wire soc_a7ddrphy_dq_t2; -wire [7:0] soc_a7ddrphy_dq_i_data2; -wire [7:0] soc_a7ddrphy_bitslip2_i; -reg [7:0] soc_a7ddrphy_bitslip2_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip2_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip2_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay3; -wire soc_a7ddrphy_dq_i_nodelay3; -wire soc_a7ddrphy_dq_i_delayed3; -wire soc_a7ddrphy_dq_t3; -wire [7:0] soc_a7ddrphy_dq_i_data3; -wire [7:0] soc_a7ddrphy_bitslip3_i; -reg [7:0] soc_a7ddrphy_bitslip3_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip3_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip3_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay4; -wire soc_a7ddrphy_dq_i_nodelay4; -wire soc_a7ddrphy_dq_i_delayed4; -wire soc_a7ddrphy_dq_t4; -wire [7:0] soc_a7ddrphy_dq_i_data4; -wire [7:0] soc_a7ddrphy_bitslip4_i; -reg [7:0] soc_a7ddrphy_bitslip4_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip4_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip4_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay5; -wire soc_a7ddrphy_dq_i_nodelay5; -wire soc_a7ddrphy_dq_i_delayed5; -wire soc_a7ddrphy_dq_t5; -wire [7:0] soc_a7ddrphy_dq_i_data5; -wire [7:0] soc_a7ddrphy_bitslip5_i; -reg [7:0] soc_a7ddrphy_bitslip5_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip5_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip5_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay6; -wire soc_a7ddrphy_dq_i_nodelay6; -wire soc_a7ddrphy_dq_i_delayed6; -wire soc_a7ddrphy_dq_t6; -wire [7:0] soc_a7ddrphy_dq_i_data6; -wire [7:0] soc_a7ddrphy_bitslip6_i; -reg [7:0] soc_a7ddrphy_bitslip6_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip6_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip6_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay7; -wire soc_a7ddrphy_dq_i_nodelay7; -wire soc_a7ddrphy_dq_i_delayed7; -wire soc_a7ddrphy_dq_t7; -wire [7:0] soc_a7ddrphy_dq_i_data7; -wire [7:0] soc_a7ddrphy_bitslip7_i; -reg [7:0] soc_a7ddrphy_bitslip7_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip7_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip7_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay8; -wire soc_a7ddrphy_dq_i_nodelay8; -wire soc_a7ddrphy_dq_i_delayed8; -wire soc_a7ddrphy_dq_t8; -wire [7:0] soc_a7ddrphy_dq_i_data8; -wire [7:0] soc_a7ddrphy_bitslip8_i; -reg [7:0] soc_a7ddrphy_bitslip8_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip8_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip8_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay9; -wire soc_a7ddrphy_dq_i_nodelay9; -wire soc_a7ddrphy_dq_i_delayed9; -wire soc_a7ddrphy_dq_t9; -wire [7:0] soc_a7ddrphy_dq_i_data9; -wire [7:0] soc_a7ddrphy_bitslip9_i; -reg [7:0] soc_a7ddrphy_bitslip9_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip9_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip9_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay10; -wire soc_a7ddrphy_dq_i_nodelay10; -wire soc_a7ddrphy_dq_i_delayed10; -wire soc_a7ddrphy_dq_t10; -wire [7:0] soc_a7ddrphy_dq_i_data10; -wire [7:0] soc_a7ddrphy_bitslip10_i; -reg [7:0] soc_a7ddrphy_bitslip10_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip10_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip10_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay11; -wire soc_a7ddrphy_dq_i_nodelay11; -wire soc_a7ddrphy_dq_i_delayed11; -wire soc_a7ddrphy_dq_t11; -wire [7:0] soc_a7ddrphy_dq_i_data11; -wire [7:0] soc_a7ddrphy_bitslip11_i; -reg [7:0] soc_a7ddrphy_bitslip11_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip11_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip11_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay12; -wire soc_a7ddrphy_dq_i_nodelay12; -wire soc_a7ddrphy_dq_i_delayed12; -wire soc_a7ddrphy_dq_t12; -wire [7:0] soc_a7ddrphy_dq_i_data12; -wire [7:0] soc_a7ddrphy_bitslip12_i; -reg [7:0] soc_a7ddrphy_bitslip12_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip12_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip12_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay13; -wire soc_a7ddrphy_dq_i_nodelay13; -wire soc_a7ddrphy_dq_i_delayed13; -wire soc_a7ddrphy_dq_t13; -wire [7:0] soc_a7ddrphy_dq_i_data13; -wire [7:0] soc_a7ddrphy_bitslip13_i; -reg [7:0] soc_a7ddrphy_bitslip13_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip13_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip13_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay14; -wire soc_a7ddrphy_dq_i_nodelay14; -wire soc_a7ddrphy_dq_i_delayed14; -wire soc_a7ddrphy_dq_t14; -wire [7:0] soc_a7ddrphy_dq_i_data14; -wire [7:0] soc_a7ddrphy_bitslip14_i; -reg [7:0] soc_a7ddrphy_bitslip14_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip14_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip14_r = 16'd0; -wire soc_a7ddrphy_dq_o_nodelay15; -wire soc_a7ddrphy_dq_i_nodelay15; -wire soc_a7ddrphy_dq_i_delayed15; -wire soc_a7ddrphy_dq_t15; -wire [7:0] soc_a7ddrphy_dq_i_data15; -wire [7:0] soc_a7ddrphy_bitslip15_i; -reg [7:0] soc_a7ddrphy_bitslip15_o = 8'd0; -reg [2:0] soc_a7ddrphy_bitslip15_value = 3'd0; -reg [15:0] soc_a7ddrphy_bitslip15_r = 16'd0; -wire [7:0] soc_a7ddrphy_rddata_en; -reg [7:0] soc_a7ddrphy_rddata_en_last = 8'd0; -wire [3:0] soc_a7ddrphy_wrdata_en; -reg [3:0] soc_a7ddrphy_wrdata_en_last = 4'd0; -wire [14:0] soc_sdram_inti_p0_address; -wire [2:0] soc_sdram_inti_p0_bank; -reg soc_sdram_inti_p0_cas_n = 1'd1; -reg soc_sdram_inti_p0_cs_n = 1'd1; -reg soc_sdram_inti_p0_ras_n = 1'd1; -reg soc_sdram_inti_p0_we_n = 1'd1; -wire soc_sdram_inti_p0_cke; -wire soc_sdram_inti_p0_odt; -wire soc_sdram_inti_p0_reset_n; -reg soc_sdram_inti_p0_act_n = 1'd1; -wire [31:0] soc_sdram_inti_p0_wrdata; -wire soc_sdram_inti_p0_wrdata_en; -wire [3:0] soc_sdram_inti_p0_wrdata_mask; -wire soc_sdram_inti_p0_rddata_en; -reg [31:0] soc_sdram_inti_p0_rddata = 32'd0; -reg soc_sdram_inti_p0_rddata_valid = 1'd0; -wire [14:0] soc_sdram_inti_p1_address; -wire [2:0] soc_sdram_inti_p1_bank; -reg soc_sdram_inti_p1_cas_n = 1'd1; -reg soc_sdram_inti_p1_cs_n = 1'd1; -reg soc_sdram_inti_p1_ras_n = 1'd1; -reg soc_sdram_inti_p1_we_n = 1'd1; -wire soc_sdram_inti_p1_cke; -wire soc_sdram_inti_p1_odt; -wire soc_sdram_inti_p1_reset_n; -reg soc_sdram_inti_p1_act_n = 1'd1; -wire [31:0] soc_sdram_inti_p1_wrdata; -wire soc_sdram_inti_p1_wrdata_en; -wire [3:0] soc_sdram_inti_p1_wrdata_mask; -wire soc_sdram_inti_p1_rddata_en; -reg [31:0] soc_sdram_inti_p1_rddata = 32'd0; -reg soc_sdram_inti_p1_rddata_valid = 1'd0; -wire [14:0] soc_sdram_inti_p2_address; -wire [2:0] soc_sdram_inti_p2_bank; -reg soc_sdram_inti_p2_cas_n = 1'd1; -reg soc_sdram_inti_p2_cs_n = 1'd1; -reg soc_sdram_inti_p2_ras_n = 1'd1; -reg soc_sdram_inti_p2_we_n = 1'd1; -wire soc_sdram_inti_p2_cke; -wire soc_sdram_inti_p2_odt; -wire soc_sdram_inti_p2_reset_n; -reg soc_sdram_inti_p2_act_n = 1'd1; -wire [31:0] soc_sdram_inti_p2_wrdata; -wire soc_sdram_inti_p2_wrdata_en; -wire [3:0] soc_sdram_inti_p2_wrdata_mask; -wire soc_sdram_inti_p2_rddata_en; -reg [31:0] soc_sdram_inti_p2_rddata = 32'd0; -reg soc_sdram_inti_p2_rddata_valid = 1'd0; -wire [14:0] soc_sdram_inti_p3_address; -wire [2:0] soc_sdram_inti_p3_bank; -reg soc_sdram_inti_p3_cas_n = 1'd1; -reg soc_sdram_inti_p3_cs_n = 1'd1; -reg soc_sdram_inti_p3_ras_n = 1'd1; -reg soc_sdram_inti_p3_we_n = 1'd1; -wire soc_sdram_inti_p3_cke; -wire soc_sdram_inti_p3_odt; -wire soc_sdram_inti_p3_reset_n; -reg soc_sdram_inti_p3_act_n = 1'd1; -wire [31:0] soc_sdram_inti_p3_wrdata; -wire soc_sdram_inti_p3_wrdata_en; -wire [3:0] soc_sdram_inti_p3_wrdata_mask; -wire soc_sdram_inti_p3_rddata_en; -reg [31:0] soc_sdram_inti_p3_rddata = 32'd0; -reg soc_sdram_inti_p3_rddata_valid = 1'd0; -wire [14:0] soc_sdram_slave_p0_address; -wire [2:0] soc_sdram_slave_p0_bank; -wire soc_sdram_slave_p0_cas_n; -wire soc_sdram_slave_p0_cs_n; -wire soc_sdram_slave_p0_ras_n; -wire soc_sdram_slave_p0_we_n; -wire soc_sdram_slave_p0_cke; -wire soc_sdram_slave_p0_odt; -wire soc_sdram_slave_p0_reset_n; -wire soc_sdram_slave_p0_act_n; -wire [31:0] soc_sdram_slave_p0_wrdata; -wire soc_sdram_slave_p0_wrdata_en; -wire [3:0] soc_sdram_slave_p0_wrdata_mask; -wire soc_sdram_slave_p0_rddata_en; -reg [31:0] soc_sdram_slave_p0_rddata = 32'd0; -reg soc_sdram_slave_p0_rddata_valid = 1'd0; -wire [14:0] soc_sdram_slave_p1_address; -wire [2:0] soc_sdram_slave_p1_bank; -wire soc_sdram_slave_p1_cas_n; -wire soc_sdram_slave_p1_cs_n; -wire soc_sdram_slave_p1_ras_n; -wire soc_sdram_slave_p1_we_n; -wire soc_sdram_slave_p1_cke; -wire soc_sdram_slave_p1_odt; -wire soc_sdram_slave_p1_reset_n; -wire soc_sdram_slave_p1_act_n; -wire [31:0] soc_sdram_slave_p1_wrdata; -wire soc_sdram_slave_p1_wrdata_en; -wire [3:0] soc_sdram_slave_p1_wrdata_mask; -wire soc_sdram_slave_p1_rddata_en; -reg [31:0] soc_sdram_slave_p1_rddata = 32'd0; -reg soc_sdram_slave_p1_rddata_valid = 1'd0; -wire [14:0] soc_sdram_slave_p2_address; -wire [2:0] soc_sdram_slave_p2_bank; -wire soc_sdram_slave_p2_cas_n; -wire soc_sdram_slave_p2_cs_n; -wire soc_sdram_slave_p2_ras_n; -wire soc_sdram_slave_p2_we_n; -wire soc_sdram_slave_p2_cke; -wire soc_sdram_slave_p2_odt; -wire soc_sdram_slave_p2_reset_n; -wire soc_sdram_slave_p2_act_n; -wire [31:0] soc_sdram_slave_p2_wrdata; -wire soc_sdram_slave_p2_wrdata_en; -wire [3:0] soc_sdram_slave_p2_wrdata_mask; -wire soc_sdram_slave_p2_rddata_en; -reg [31:0] soc_sdram_slave_p2_rddata = 32'd0; -reg soc_sdram_slave_p2_rddata_valid = 1'd0; -wire [14:0] soc_sdram_slave_p3_address; -wire [2:0] soc_sdram_slave_p3_bank; -wire soc_sdram_slave_p3_cas_n; -wire soc_sdram_slave_p3_cs_n; -wire soc_sdram_slave_p3_ras_n; -wire soc_sdram_slave_p3_we_n; -wire soc_sdram_slave_p3_cke; -wire soc_sdram_slave_p3_odt; -wire soc_sdram_slave_p3_reset_n; -wire soc_sdram_slave_p3_act_n; -wire [31:0] soc_sdram_slave_p3_wrdata; -wire soc_sdram_slave_p3_wrdata_en; -wire [3:0] soc_sdram_slave_p3_wrdata_mask; -wire soc_sdram_slave_p3_rddata_en; -reg [31:0] soc_sdram_slave_p3_rddata = 32'd0; -reg soc_sdram_slave_p3_rddata_valid = 1'd0; -reg [14:0] soc_sdram_master_p0_address = 15'd0; -reg [2:0] soc_sdram_master_p0_bank = 3'd0; -reg soc_sdram_master_p0_cas_n = 1'd1; -reg soc_sdram_master_p0_cs_n = 1'd1; -reg soc_sdram_master_p0_ras_n = 1'd1; -reg soc_sdram_master_p0_we_n = 1'd1; -reg soc_sdram_master_p0_cke = 1'd0; -reg soc_sdram_master_p0_odt = 1'd0; -reg soc_sdram_master_p0_reset_n = 1'd0; -reg soc_sdram_master_p0_act_n = 1'd1; -reg [31:0] soc_sdram_master_p0_wrdata = 32'd0; -reg soc_sdram_master_p0_wrdata_en = 1'd0; -reg [3:0] soc_sdram_master_p0_wrdata_mask = 4'd0; -reg soc_sdram_master_p0_rddata_en = 1'd0; -wire [31:0] soc_sdram_master_p0_rddata; -wire soc_sdram_master_p0_rddata_valid; -reg [14:0] soc_sdram_master_p1_address = 15'd0; -reg [2:0] soc_sdram_master_p1_bank = 3'd0; -reg soc_sdram_master_p1_cas_n = 1'd1; -reg soc_sdram_master_p1_cs_n = 1'd1; -reg soc_sdram_master_p1_ras_n = 1'd1; -reg soc_sdram_master_p1_we_n = 1'd1; -reg soc_sdram_master_p1_cke = 1'd0; -reg soc_sdram_master_p1_odt = 1'd0; -reg soc_sdram_master_p1_reset_n = 1'd0; -reg soc_sdram_master_p1_act_n = 1'd1; -reg [31:0] soc_sdram_master_p1_wrdata = 32'd0; -reg soc_sdram_master_p1_wrdata_en = 1'd0; -reg [3:0] soc_sdram_master_p1_wrdata_mask = 4'd0; -reg soc_sdram_master_p1_rddata_en = 1'd0; -wire [31:0] soc_sdram_master_p1_rddata; -wire soc_sdram_master_p1_rddata_valid; -reg [14:0] soc_sdram_master_p2_address = 15'd0; -reg [2:0] soc_sdram_master_p2_bank = 3'd0; -reg soc_sdram_master_p2_cas_n = 1'd1; -reg soc_sdram_master_p2_cs_n = 1'd1; -reg soc_sdram_master_p2_ras_n = 1'd1; -reg soc_sdram_master_p2_we_n = 1'd1; -reg soc_sdram_master_p2_cke = 1'd0; -reg soc_sdram_master_p2_odt = 1'd0; -reg soc_sdram_master_p2_reset_n = 1'd0; -reg soc_sdram_master_p2_act_n = 1'd1; -reg [31:0] soc_sdram_master_p2_wrdata = 32'd0; -reg soc_sdram_master_p2_wrdata_en = 1'd0; -reg [3:0] soc_sdram_master_p2_wrdata_mask = 4'd0; -reg soc_sdram_master_p2_rddata_en = 1'd0; -wire [31:0] soc_sdram_master_p2_rddata; -wire soc_sdram_master_p2_rddata_valid; -reg [14:0] soc_sdram_master_p3_address = 15'd0; -reg [2:0] soc_sdram_master_p3_bank = 3'd0; -reg soc_sdram_master_p3_cas_n = 1'd1; -reg soc_sdram_master_p3_cs_n = 1'd1; -reg soc_sdram_master_p3_ras_n = 1'd1; -reg soc_sdram_master_p3_we_n = 1'd1; -reg soc_sdram_master_p3_cke = 1'd0; -reg soc_sdram_master_p3_odt = 1'd0; -reg soc_sdram_master_p3_reset_n = 1'd0; -reg soc_sdram_master_p3_act_n = 1'd1; -reg [31:0] soc_sdram_master_p3_wrdata = 32'd0; -reg soc_sdram_master_p3_wrdata_en = 1'd0; -reg [3:0] soc_sdram_master_p3_wrdata_mask = 4'd0; -reg soc_sdram_master_p3_rddata_en = 1'd0; -wire [31:0] soc_sdram_master_p3_rddata; -wire soc_sdram_master_p3_rddata_valid; -reg [3:0] soc_sdram_storage = 4'd0; -reg soc_sdram_re = 1'd0; -reg [5:0] soc_sdram_phaseinjector0_command_storage = 6'd0; -reg soc_sdram_phaseinjector0_command_re = 1'd0; -wire soc_sdram_phaseinjector0_command_issue_re; -wire soc_sdram_phaseinjector0_command_issue_r; -wire soc_sdram_phaseinjector0_command_issue_we; -reg soc_sdram_phaseinjector0_command_issue_w = 1'd0; -reg [14:0] soc_sdram_phaseinjector0_address_storage = 15'd0; -reg soc_sdram_phaseinjector0_address_re = 1'd0; -reg [2:0] soc_sdram_phaseinjector0_baddress_storage = 3'd0; -reg soc_sdram_phaseinjector0_baddress_re = 1'd0; -reg [31:0] soc_sdram_phaseinjector0_wrdata_storage = 32'd0; -reg soc_sdram_phaseinjector0_wrdata_re = 1'd0; -reg [31:0] soc_sdram_phaseinjector0_status = 32'd0; -wire soc_sdram_phaseinjector0_we; -reg [5:0] soc_sdram_phaseinjector1_command_storage = 6'd0; -reg soc_sdram_phaseinjector1_command_re = 1'd0; -wire soc_sdram_phaseinjector1_command_issue_re; -wire soc_sdram_phaseinjector1_command_issue_r; -wire soc_sdram_phaseinjector1_command_issue_we; -reg soc_sdram_phaseinjector1_command_issue_w = 1'd0; -reg [14:0] soc_sdram_phaseinjector1_address_storage = 15'd0; -reg soc_sdram_phaseinjector1_address_re = 1'd0; -reg [2:0] soc_sdram_phaseinjector1_baddress_storage = 3'd0; -reg soc_sdram_phaseinjector1_baddress_re = 1'd0; -reg [31:0] soc_sdram_phaseinjector1_wrdata_storage = 32'd0; -reg soc_sdram_phaseinjector1_wrdata_re = 1'd0; -reg [31:0] soc_sdram_phaseinjector1_status = 32'd0; -wire soc_sdram_phaseinjector1_we; -reg [5:0] soc_sdram_phaseinjector2_command_storage = 6'd0; -reg soc_sdram_phaseinjector2_command_re = 1'd0; -wire soc_sdram_phaseinjector2_command_issue_re; -wire soc_sdram_phaseinjector2_command_issue_r; -wire soc_sdram_phaseinjector2_command_issue_we; -reg soc_sdram_phaseinjector2_command_issue_w = 1'd0; -reg [14:0] soc_sdram_phaseinjector2_address_storage = 15'd0; -reg soc_sdram_phaseinjector2_address_re = 1'd0; -reg [2:0] soc_sdram_phaseinjector2_baddress_storage = 3'd0; -reg soc_sdram_phaseinjector2_baddress_re = 1'd0; -reg [31:0] soc_sdram_phaseinjector2_wrdata_storage = 32'd0; -reg soc_sdram_phaseinjector2_wrdata_re = 1'd0; -reg [31:0] soc_sdram_phaseinjector2_status = 32'd0; -wire soc_sdram_phaseinjector2_we; -reg [5:0] soc_sdram_phaseinjector3_command_storage = 6'd0; -reg soc_sdram_phaseinjector3_command_re = 1'd0; -wire soc_sdram_phaseinjector3_command_issue_re; -wire soc_sdram_phaseinjector3_command_issue_r; -wire soc_sdram_phaseinjector3_command_issue_we; -reg soc_sdram_phaseinjector3_command_issue_w = 1'd0; -reg [14:0] soc_sdram_phaseinjector3_address_storage = 15'd0; -reg soc_sdram_phaseinjector3_address_re = 1'd0; -reg [2:0] soc_sdram_phaseinjector3_baddress_storage = 3'd0; -reg soc_sdram_phaseinjector3_baddress_re = 1'd0; -reg [31:0] soc_sdram_phaseinjector3_wrdata_storage = 32'd0; -reg soc_sdram_phaseinjector3_wrdata_re = 1'd0; -reg [31:0] soc_sdram_phaseinjector3_status = 32'd0; -wire soc_sdram_phaseinjector3_we; -wire soc_sdram_interface_bank0_valid; -wire soc_sdram_interface_bank0_ready; -wire soc_sdram_interface_bank0_we; -wire [21:0] soc_sdram_interface_bank0_addr; -wire soc_sdram_interface_bank0_lock; -wire soc_sdram_interface_bank0_wdata_ready; -wire soc_sdram_interface_bank0_rdata_valid; -wire soc_sdram_interface_bank1_valid; -wire soc_sdram_interface_bank1_ready; -wire soc_sdram_interface_bank1_we; -wire [21:0] soc_sdram_interface_bank1_addr; -wire soc_sdram_interface_bank1_lock; -wire soc_sdram_interface_bank1_wdata_ready; -wire soc_sdram_interface_bank1_rdata_valid; -wire soc_sdram_interface_bank2_valid; -wire soc_sdram_interface_bank2_ready; -wire soc_sdram_interface_bank2_we; -wire [21:0] soc_sdram_interface_bank2_addr; -wire soc_sdram_interface_bank2_lock; -wire soc_sdram_interface_bank2_wdata_ready; -wire soc_sdram_interface_bank2_rdata_valid; -wire soc_sdram_interface_bank3_valid; -wire soc_sdram_interface_bank3_ready; -wire soc_sdram_interface_bank3_we; -wire [21:0] soc_sdram_interface_bank3_addr; -wire soc_sdram_interface_bank3_lock; -wire soc_sdram_interface_bank3_wdata_ready; -wire soc_sdram_interface_bank3_rdata_valid; -wire soc_sdram_interface_bank4_valid; -wire soc_sdram_interface_bank4_ready; -wire soc_sdram_interface_bank4_we; -wire [21:0] soc_sdram_interface_bank4_addr; -wire soc_sdram_interface_bank4_lock; -wire soc_sdram_interface_bank4_wdata_ready; -wire soc_sdram_interface_bank4_rdata_valid; -wire soc_sdram_interface_bank5_valid; -wire soc_sdram_interface_bank5_ready; -wire soc_sdram_interface_bank5_we; -wire [21:0] soc_sdram_interface_bank5_addr; -wire soc_sdram_interface_bank5_lock; -wire soc_sdram_interface_bank5_wdata_ready; -wire soc_sdram_interface_bank5_rdata_valid; -wire soc_sdram_interface_bank6_valid; -wire soc_sdram_interface_bank6_ready; -wire soc_sdram_interface_bank6_we; -wire [21:0] soc_sdram_interface_bank6_addr; -wire soc_sdram_interface_bank6_lock; -wire soc_sdram_interface_bank6_wdata_ready; -wire soc_sdram_interface_bank6_rdata_valid; -wire soc_sdram_interface_bank7_valid; -wire soc_sdram_interface_bank7_ready; -wire soc_sdram_interface_bank7_we; -wire [21:0] soc_sdram_interface_bank7_addr; -wire soc_sdram_interface_bank7_lock; -wire soc_sdram_interface_bank7_wdata_ready; -wire soc_sdram_interface_bank7_rdata_valid; -reg [127:0] soc_sdram_interface_wdata = 128'd0; -reg [15:0] soc_sdram_interface_wdata_we = 16'd0; -wire [127:0] soc_sdram_interface_rdata; -reg [14:0] soc_sdram_dfi_p0_address = 15'd0; -reg [2:0] soc_sdram_dfi_p0_bank = 3'd0; -reg soc_sdram_dfi_p0_cas_n = 1'd1; -reg soc_sdram_dfi_p0_cs_n = 1'd1; -reg soc_sdram_dfi_p0_ras_n = 1'd1; -reg soc_sdram_dfi_p0_we_n = 1'd1; -wire soc_sdram_dfi_p0_cke; -wire soc_sdram_dfi_p0_odt; -wire soc_sdram_dfi_p0_reset_n; -reg soc_sdram_dfi_p0_act_n = 1'd1; -wire [31:0] soc_sdram_dfi_p0_wrdata; -reg soc_sdram_dfi_p0_wrdata_en = 1'd0; -wire [3:0] soc_sdram_dfi_p0_wrdata_mask; -reg soc_sdram_dfi_p0_rddata_en = 1'd0; -wire [31:0] soc_sdram_dfi_p0_rddata; -wire soc_sdram_dfi_p0_rddata_valid; -reg [14:0] soc_sdram_dfi_p1_address = 15'd0; -reg [2:0] soc_sdram_dfi_p1_bank = 3'd0; -reg soc_sdram_dfi_p1_cas_n = 1'd1; -reg soc_sdram_dfi_p1_cs_n = 1'd1; -reg soc_sdram_dfi_p1_ras_n = 1'd1; -reg soc_sdram_dfi_p1_we_n = 1'd1; -wire soc_sdram_dfi_p1_cke; -wire soc_sdram_dfi_p1_odt; -wire soc_sdram_dfi_p1_reset_n; -reg soc_sdram_dfi_p1_act_n = 1'd1; -wire [31:0] soc_sdram_dfi_p1_wrdata; -reg soc_sdram_dfi_p1_wrdata_en = 1'd0; -wire [3:0] soc_sdram_dfi_p1_wrdata_mask; -reg soc_sdram_dfi_p1_rddata_en = 1'd0; -wire [31:0] soc_sdram_dfi_p1_rddata; -wire soc_sdram_dfi_p1_rddata_valid; -reg [14:0] soc_sdram_dfi_p2_address = 15'd0; -reg [2:0] soc_sdram_dfi_p2_bank = 3'd0; -reg soc_sdram_dfi_p2_cas_n = 1'd1; -reg soc_sdram_dfi_p2_cs_n = 1'd1; -reg soc_sdram_dfi_p2_ras_n = 1'd1; -reg soc_sdram_dfi_p2_we_n = 1'd1; -wire soc_sdram_dfi_p2_cke; -wire soc_sdram_dfi_p2_odt; -wire soc_sdram_dfi_p2_reset_n; -reg soc_sdram_dfi_p2_act_n = 1'd1; -wire [31:0] soc_sdram_dfi_p2_wrdata; -reg soc_sdram_dfi_p2_wrdata_en = 1'd0; -wire [3:0] soc_sdram_dfi_p2_wrdata_mask; -reg soc_sdram_dfi_p2_rddata_en = 1'd0; -wire [31:0] soc_sdram_dfi_p2_rddata; -wire soc_sdram_dfi_p2_rddata_valid; -reg [14:0] soc_sdram_dfi_p3_address = 15'd0; -reg [2:0] soc_sdram_dfi_p3_bank = 3'd0; -reg soc_sdram_dfi_p3_cas_n = 1'd1; -reg soc_sdram_dfi_p3_cs_n = 1'd1; -reg soc_sdram_dfi_p3_ras_n = 1'd1; -reg soc_sdram_dfi_p3_we_n = 1'd1; -wire soc_sdram_dfi_p3_cke; -wire soc_sdram_dfi_p3_odt; -wire soc_sdram_dfi_p3_reset_n; -reg soc_sdram_dfi_p3_act_n = 1'd1; -wire [31:0] soc_sdram_dfi_p3_wrdata; -reg soc_sdram_dfi_p3_wrdata_en = 1'd0; -wire [3:0] soc_sdram_dfi_p3_wrdata_mask; -reg soc_sdram_dfi_p3_rddata_en = 1'd0; -wire [31:0] soc_sdram_dfi_p3_rddata; -wire soc_sdram_dfi_p3_rddata_valid; -reg soc_sdram_cmd_valid = 1'd0; -reg soc_sdram_cmd_ready = 1'd0; -reg soc_sdram_cmd_last = 1'd0; -reg [14:0] soc_sdram_cmd_payload_a = 15'd0; -reg [2:0] soc_sdram_cmd_payload_ba = 3'd0; -reg soc_sdram_cmd_payload_cas = 1'd0; -reg soc_sdram_cmd_payload_ras = 1'd0; -reg soc_sdram_cmd_payload_we = 1'd0; -reg soc_sdram_cmd_payload_is_read = 1'd0; -reg soc_sdram_cmd_payload_is_write = 1'd0; -wire soc_sdram_wants_refresh; -wire soc_sdram_wants_zqcs; -wire soc_sdram_timer_wait; -wire soc_sdram_timer_done0; -wire [9:0] soc_sdram_timer_count0; -wire soc_sdram_timer_done1; -reg [9:0] soc_sdram_timer_count1 = 10'd781; -wire soc_sdram_postponer_req_i; -reg soc_sdram_postponer_req_o = 1'd0; -reg soc_sdram_postponer_count = 1'd0; -reg soc_sdram_sequencer_start0 = 1'd0; -wire soc_sdram_sequencer_done0; -wire soc_sdram_sequencer_start1; -reg soc_sdram_sequencer_done1 = 1'd0; -reg [5:0] soc_sdram_sequencer_counter = 6'd0; -reg soc_sdram_sequencer_count = 1'd0; -wire soc_sdram_zqcs_timer_wait; -wire soc_sdram_zqcs_timer_done0; -wire [26:0] soc_sdram_zqcs_timer_count0; -wire soc_sdram_zqcs_timer_done1; -reg [26:0] soc_sdram_zqcs_timer_count1 = 27'd99999999; -reg soc_sdram_zqcs_executer_start = 1'd0; -reg soc_sdram_zqcs_executer_done = 1'd0; -reg [4:0] soc_sdram_zqcs_executer_counter = 5'd0; -wire soc_sdram_bankmachine0_req_valid; -wire soc_sdram_bankmachine0_req_ready; -wire soc_sdram_bankmachine0_req_we; -wire [21:0] soc_sdram_bankmachine0_req_addr; -wire soc_sdram_bankmachine0_req_lock; -reg soc_sdram_bankmachine0_req_wdata_ready = 1'd0; -reg soc_sdram_bankmachine0_req_rdata_valid = 1'd0; -wire soc_sdram_bankmachine0_refresh_req; -reg soc_sdram_bankmachine0_refresh_gnt = 1'd0; -reg soc_sdram_bankmachine0_cmd_valid = 1'd0; -reg soc_sdram_bankmachine0_cmd_ready = 1'd0; -reg [14:0] soc_sdram_bankmachine0_cmd_payload_a = 15'd0; -wire [2:0] soc_sdram_bankmachine0_cmd_payload_ba; -reg soc_sdram_bankmachine0_cmd_payload_cas = 1'd0; -reg soc_sdram_bankmachine0_cmd_payload_ras = 1'd0; -reg soc_sdram_bankmachine0_cmd_payload_we = 1'd0; -reg soc_sdram_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg soc_sdram_bankmachine0_cmd_payload_is_read = 1'd0; -reg soc_sdram_bankmachine0_cmd_payload_is_write = 1'd0; -reg soc_sdram_bankmachine0_auto_precharge = 1'd0; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready; -reg soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -wire [24:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -wire [24:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -reg [4:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_level = 5'd0; -reg soc_sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read; -wire [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -wire soc_sdram_bankmachine0_cmd_buffer_sink_valid; -wire soc_sdram_bankmachine0_cmd_buffer_sink_ready; -wire soc_sdram_bankmachine0_cmd_buffer_sink_first; -wire soc_sdram_bankmachine0_cmd_buffer_sink_last; -wire soc_sdram_bankmachine0_cmd_buffer_sink_payload_we; -wire [21:0] soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr; -reg soc_sdram_bankmachine0_cmd_buffer_source_valid = 1'd0; -wire soc_sdram_bankmachine0_cmd_buffer_source_ready; -reg soc_sdram_bankmachine0_cmd_buffer_source_first = 1'd0; -reg soc_sdram_bankmachine0_cmd_buffer_source_last = 1'd0; -reg soc_sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_sdram_bankmachine0_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_sdram_bankmachine0_row = 15'd0; -reg soc_sdram_bankmachine0_row_opened = 1'd0; -wire soc_sdram_bankmachine0_row_hit; -reg soc_sdram_bankmachine0_row_open = 1'd0; -reg soc_sdram_bankmachine0_row_close = 1'd0; -reg soc_sdram_bankmachine0_row_col_n_addr_sel = 1'd0; -wire soc_sdram_bankmachine0_twtpcon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine0_twtpcon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine0_twtpcon_count = 3'd0; -wire soc_sdram_bankmachine0_trccon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine0_trccon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine0_trccon_count = 3'd0; -wire soc_sdram_bankmachine0_trascon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine0_trascon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine0_trascon_count = 3'd0; -wire soc_sdram_bankmachine1_req_valid; -wire soc_sdram_bankmachine1_req_ready; -wire soc_sdram_bankmachine1_req_we; -wire [21:0] soc_sdram_bankmachine1_req_addr; -wire soc_sdram_bankmachine1_req_lock; -reg soc_sdram_bankmachine1_req_wdata_ready = 1'd0; -reg soc_sdram_bankmachine1_req_rdata_valid = 1'd0; -wire soc_sdram_bankmachine1_refresh_req; -reg soc_sdram_bankmachine1_refresh_gnt = 1'd0; -reg soc_sdram_bankmachine1_cmd_valid = 1'd0; -reg soc_sdram_bankmachine1_cmd_ready = 1'd0; -reg [14:0] soc_sdram_bankmachine1_cmd_payload_a = 15'd0; -wire [2:0] soc_sdram_bankmachine1_cmd_payload_ba; -reg soc_sdram_bankmachine1_cmd_payload_cas = 1'd0; -reg soc_sdram_bankmachine1_cmd_payload_ras = 1'd0; -reg soc_sdram_bankmachine1_cmd_payload_we = 1'd0; -reg soc_sdram_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg soc_sdram_bankmachine1_cmd_payload_is_read = 1'd0; -reg soc_sdram_bankmachine1_cmd_payload_is_write = 1'd0; -reg soc_sdram_bankmachine1_auto_precharge = 1'd0; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready; -reg soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -wire [24:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -wire [24:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -reg [4:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_level = 5'd0; -reg soc_sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read; -wire [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -wire soc_sdram_bankmachine1_cmd_buffer_sink_valid; -wire soc_sdram_bankmachine1_cmd_buffer_sink_ready; -wire soc_sdram_bankmachine1_cmd_buffer_sink_first; -wire soc_sdram_bankmachine1_cmd_buffer_sink_last; -wire soc_sdram_bankmachine1_cmd_buffer_sink_payload_we; -wire [21:0] soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr; -reg soc_sdram_bankmachine1_cmd_buffer_source_valid = 1'd0; -wire soc_sdram_bankmachine1_cmd_buffer_source_ready; -reg soc_sdram_bankmachine1_cmd_buffer_source_first = 1'd0; -reg soc_sdram_bankmachine1_cmd_buffer_source_last = 1'd0; -reg soc_sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_sdram_bankmachine1_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_sdram_bankmachine1_row = 15'd0; -reg soc_sdram_bankmachine1_row_opened = 1'd0; -wire soc_sdram_bankmachine1_row_hit; -reg soc_sdram_bankmachine1_row_open = 1'd0; -reg soc_sdram_bankmachine1_row_close = 1'd0; -reg soc_sdram_bankmachine1_row_col_n_addr_sel = 1'd0; -wire soc_sdram_bankmachine1_twtpcon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine1_twtpcon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine1_twtpcon_count = 3'd0; -wire soc_sdram_bankmachine1_trccon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine1_trccon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine1_trccon_count = 3'd0; -wire soc_sdram_bankmachine1_trascon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine1_trascon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine1_trascon_count = 3'd0; -wire soc_sdram_bankmachine2_req_valid; -wire soc_sdram_bankmachine2_req_ready; -wire soc_sdram_bankmachine2_req_we; -wire [21:0] soc_sdram_bankmachine2_req_addr; -wire soc_sdram_bankmachine2_req_lock; -reg soc_sdram_bankmachine2_req_wdata_ready = 1'd0; -reg soc_sdram_bankmachine2_req_rdata_valid = 1'd0; -wire soc_sdram_bankmachine2_refresh_req; -reg soc_sdram_bankmachine2_refresh_gnt = 1'd0; -reg soc_sdram_bankmachine2_cmd_valid = 1'd0; -reg soc_sdram_bankmachine2_cmd_ready = 1'd0; -reg [14:0] soc_sdram_bankmachine2_cmd_payload_a = 15'd0; -wire [2:0] soc_sdram_bankmachine2_cmd_payload_ba; -reg soc_sdram_bankmachine2_cmd_payload_cas = 1'd0; -reg soc_sdram_bankmachine2_cmd_payload_ras = 1'd0; -reg soc_sdram_bankmachine2_cmd_payload_we = 1'd0; -reg soc_sdram_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg soc_sdram_bankmachine2_cmd_payload_is_read = 1'd0; -reg soc_sdram_bankmachine2_cmd_payload_is_write = 1'd0; -reg soc_sdram_bankmachine2_auto_precharge = 1'd0; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready; -reg soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -wire [24:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -wire [24:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -reg [4:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_level = 5'd0; -reg soc_sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read; -wire [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -wire soc_sdram_bankmachine2_cmd_buffer_sink_valid; -wire soc_sdram_bankmachine2_cmd_buffer_sink_ready; -wire soc_sdram_bankmachine2_cmd_buffer_sink_first; -wire soc_sdram_bankmachine2_cmd_buffer_sink_last; -wire soc_sdram_bankmachine2_cmd_buffer_sink_payload_we; -wire [21:0] soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr; -reg soc_sdram_bankmachine2_cmd_buffer_source_valid = 1'd0; -wire soc_sdram_bankmachine2_cmd_buffer_source_ready; -reg soc_sdram_bankmachine2_cmd_buffer_source_first = 1'd0; -reg soc_sdram_bankmachine2_cmd_buffer_source_last = 1'd0; -reg soc_sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_sdram_bankmachine2_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_sdram_bankmachine2_row = 15'd0; -reg soc_sdram_bankmachine2_row_opened = 1'd0; -wire soc_sdram_bankmachine2_row_hit; -reg soc_sdram_bankmachine2_row_open = 1'd0; -reg soc_sdram_bankmachine2_row_close = 1'd0; -reg soc_sdram_bankmachine2_row_col_n_addr_sel = 1'd0; -wire soc_sdram_bankmachine2_twtpcon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine2_twtpcon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine2_twtpcon_count = 3'd0; -wire soc_sdram_bankmachine2_trccon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine2_trccon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine2_trccon_count = 3'd0; -wire soc_sdram_bankmachine2_trascon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine2_trascon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine2_trascon_count = 3'd0; -wire soc_sdram_bankmachine3_req_valid; -wire soc_sdram_bankmachine3_req_ready; -wire soc_sdram_bankmachine3_req_we; -wire [21:0] soc_sdram_bankmachine3_req_addr; -wire soc_sdram_bankmachine3_req_lock; -reg soc_sdram_bankmachine3_req_wdata_ready = 1'd0; -reg soc_sdram_bankmachine3_req_rdata_valid = 1'd0; -wire soc_sdram_bankmachine3_refresh_req; -reg soc_sdram_bankmachine3_refresh_gnt = 1'd0; -reg soc_sdram_bankmachine3_cmd_valid = 1'd0; -reg soc_sdram_bankmachine3_cmd_ready = 1'd0; -reg [14:0] soc_sdram_bankmachine3_cmd_payload_a = 15'd0; -wire [2:0] soc_sdram_bankmachine3_cmd_payload_ba; -reg soc_sdram_bankmachine3_cmd_payload_cas = 1'd0; -reg soc_sdram_bankmachine3_cmd_payload_ras = 1'd0; -reg soc_sdram_bankmachine3_cmd_payload_we = 1'd0; -reg soc_sdram_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg soc_sdram_bankmachine3_cmd_payload_is_read = 1'd0; -reg soc_sdram_bankmachine3_cmd_payload_is_write = 1'd0; -reg soc_sdram_bankmachine3_auto_precharge = 1'd0; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready; -reg soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -wire [24:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -wire [24:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -reg [4:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_level = 5'd0; -reg soc_sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read; -wire [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -wire soc_sdram_bankmachine3_cmd_buffer_sink_valid; -wire soc_sdram_bankmachine3_cmd_buffer_sink_ready; -wire soc_sdram_bankmachine3_cmd_buffer_sink_first; -wire soc_sdram_bankmachine3_cmd_buffer_sink_last; -wire soc_sdram_bankmachine3_cmd_buffer_sink_payload_we; -wire [21:0] soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr; -reg soc_sdram_bankmachine3_cmd_buffer_source_valid = 1'd0; -wire soc_sdram_bankmachine3_cmd_buffer_source_ready; -reg soc_sdram_bankmachine3_cmd_buffer_source_first = 1'd0; -reg soc_sdram_bankmachine3_cmd_buffer_source_last = 1'd0; -reg soc_sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_sdram_bankmachine3_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_sdram_bankmachine3_row = 15'd0; -reg soc_sdram_bankmachine3_row_opened = 1'd0; -wire soc_sdram_bankmachine3_row_hit; -reg soc_sdram_bankmachine3_row_open = 1'd0; -reg soc_sdram_bankmachine3_row_close = 1'd0; -reg soc_sdram_bankmachine3_row_col_n_addr_sel = 1'd0; -wire soc_sdram_bankmachine3_twtpcon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine3_twtpcon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine3_twtpcon_count = 3'd0; -wire soc_sdram_bankmachine3_trccon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine3_trccon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine3_trccon_count = 3'd0; -wire soc_sdram_bankmachine3_trascon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine3_trascon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine3_trascon_count = 3'd0; -wire soc_sdram_bankmachine4_req_valid; -wire soc_sdram_bankmachine4_req_ready; -wire soc_sdram_bankmachine4_req_we; -wire [21:0] soc_sdram_bankmachine4_req_addr; -wire soc_sdram_bankmachine4_req_lock; -reg soc_sdram_bankmachine4_req_wdata_ready = 1'd0; -reg soc_sdram_bankmachine4_req_rdata_valid = 1'd0; -wire soc_sdram_bankmachine4_refresh_req; -reg soc_sdram_bankmachine4_refresh_gnt = 1'd0; -reg soc_sdram_bankmachine4_cmd_valid = 1'd0; -reg soc_sdram_bankmachine4_cmd_ready = 1'd0; -reg [14:0] soc_sdram_bankmachine4_cmd_payload_a = 15'd0; -wire [2:0] soc_sdram_bankmachine4_cmd_payload_ba; -reg soc_sdram_bankmachine4_cmd_payload_cas = 1'd0; -reg soc_sdram_bankmachine4_cmd_payload_ras = 1'd0; -reg soc_sdram_bankmachine4_cmd_payload_we = 1'd0; -reg soc_sdram_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg soc_sdram_bankmachine4_cmd_payload_is_read = 1'd0; -reg soc_sdram_bankmachine4_cmd_payload_is_write = 1'd0; -reg soc_sdram_bankmachine4_auto_precharge = 1'd0; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready; -reg soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -wire [24:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -wire [24:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -reg [4:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_level = 5'd0; -reg soc_sdram_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read; -wire [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -wire soc_sdram_bankmachine4_cmd_buffer_sink_valid; -wire soc_sdram_bankmachine4_cmd_buffer_sink_ready; -wire soc_sdram_bankmachine4_cmd_buffer_sink_first; -wire soc_sdram_bankmachine4_cmd_buffer_sink_last; -wire soc_sdram_bankmachine4_cmd_buffer_sink_payload_we; -wire [21:0] soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr; -reg soc_sdram_bankmachine4_cmd_buffer_source_valid = 1'd0; -wire soc_sdram_bankmachine4_cmd_buffer_source_ready; -reg soc_sdram_bankmachine4_cmd_buffer_source_first = 1'd0; -reg soc_sdram_bankmachine4_cmd_buffer_source_last = 1'd0; -reg soc_sdram_bankmachine4_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_sdram_bankmachine4_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_sdram_bankmachine4_row = 15'd0; -reg soc_sdram_bankmachine4_row_opened = 1'd0; -wire soc_sdram_bankmachine4_row_hit; -reg soc_sdram_bankmachine4_row_open = 1'd0; -reg soc_sdram_bankmachine4_row_close = 1'd0; -reg soc_sdram_bankmachine4_row_col_n_addr_sel = 1'd0; -wire soc_sdram_bankmachine4_twtpcon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine4_twtpcon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine4_twtpcon_count = 3'd0; -wire soc_sdram_bankmachine4_trccon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine4_trccon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine4_trccon_count = 3'd0; -wire soc_sdram_bankmachine4_trascon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine4_trascon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine4_trascon_count = 3'd0; -wire soc_sdram_bankmachine5_req_valid; -wire soc_sdram_bankmachine5_req_ready; -wire soc_sdram_bankmachine5_req_we; -wire [21:0] soc_sdram_bankmachine5_req_addr; -wire soc_sdram_bankmachine5_req_lock; -reg soc_sdram_bankmachine5_req_wdata_ready = 1'd0; -reg soc_sdram_bankmachine5_req_rdata_valid = 1'd0; -wire soc_sdram_bankmachine5_refresh_req; -reg soc_sdram_bankmachine5_refresh_gnt = 1'd0; -reg soc_sdram_bankmachine5_cmd_valid = 1'd0; -reg soc_sdram_bankmachine5_cmd_ready = 1'd0; -reg [14:0] soc_sdram_bankmachine5_cmd_payload_a = 15'd0; -wire [2:0] soc_sdram_bankmachine5_cmd_payload_ba; -reg soc_sdram_bankmachine5_cmd_payload_cas = 1'd0; -reg soc_sdram_bankmachine5_cmd_payload_ras = 1'd0; -reg soc_sdram_bankmachine5_cmd_payload_we = 1'd0; -reg soc_sdram_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg soc_sdram_bankmachine5_cmd_payload_is_read = 1'd0; -reg soc_sdram_bankmachine5_cmd_payload_is_write = 1'd0; -reg soc_sdram_bankmachine5_auto_precharge = 1'd0; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready; -reg soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -wire [24:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -wire [24:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -reg [4:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_level = 5'd0; -reg soc_sdram_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read; -wire [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -wire soc_sdram_bankmachine5_cmd_buffer_sink_valid; -wire soc_sdram_bankmachine5_cmd_buffer_sink_ready; -wire soc_sdram_bankmachine5_cmd_buffer_sink_first; -wire soc_sdram_bankmachine5_cmd_buffer_sink_last; -wire soc_sdram_bankmachine5_cmd_buffer_sink_payload_we; -wire [21:0] soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr; -reg soc_sdram_bankmachine5_cmd_buffer_source_valid = 1'd0; -wire soc_sdram_bankmachine5_cmd_buffer_source_ready; -reg soc_sdram_bankmachine5_cmd_buffer_source_first = 1'd0; -reg soc_sdram_bankmachine5_cmd_buffer_source_last = 1'd0; -reg soc_sdram_bankmachine5_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_sdram_bankmachine5_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_sdram_bankmachine5_row = 15'd0; -reg soc_sdram_bankmachine5_row_opened = 1'd0; -wire soc_sdram_bankmachine5_row_hit; -reg soc_sdram_bankmachine5_row_open = 1'd0; -reg soc_sdram_bankmachine5_row_close = 1'd0; -reg soc_sdram_bankmachine5_row_col_n_addr_sel = 1'd0; -wire soc_sdram_bankmachine5_twtpcon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine5_twtpcon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine5_twtpcon_count = 3'd0; -wire soc_sdram_bankmachine5_trccon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine5_trccon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine5_trccon_count = 3'd0; -wire soc_sdram_bankmachine5_trascon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine5_trascon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine5_trascon_count = 3'd0; -wire soc_sdram_bankmachine6_req_valid; -wire soc_sdram_bankmachine6_req_ready; -wire soc_sdram_bankmachine6_req_we; -wire [21:0] soc_sdram_bankmachine6_req_addr; -wire soc_sdram_bankmachine6_req_lock; -reg soc_sdram_bankmachine6_req_wdata_ready = 1'd0; -reg soc_sdram_bankmachine6_req_rdata_valid = 1'd0; -wire soc_sdram_bankmachine6_refresh_req; -reg soc_sdram_bankmachine6_refresh_gnt = 1'd0; -reg soc_sdram_bankmachine6_cmd_valid = 1'd0; -reg soc_sdram_bankmachine6_cmd_ready = 1'd0; -reg [14:0] soc_sdram_bankmachine6_cmd_payload_a = 15'd0; -wire [2:0] soc_sdram_bankmachine6_cmd_payload_ba; -reg soc_sdram_bankmachine6_cmd_payload_cas = 1'd0; -reg soc_sdram_bankmachine6_cmd_payload_ras = 1'd0; -reg soc_sdram_bankmachine6_cmd_payload_we = 1'd0; -reg soc_sdram_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg soc_sdram_bankmachine6_cmd_payload_is_read = 1'd0; -reg soc_sdram_bankmachine6_cmd_payload_is_write = 1'd0; -reg soc_sdram_bankmachine6_auto_precharge = 1'd0; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready; -reg soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -wire [24:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -wire [24:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -reg [4:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_level = 5'd0; -reg soc_sdram_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read; -wire [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -wire soc_sdram_bankmachine6_cmd_buffer_sink_valid; -wire soc_sdram_bankmachine6_cmd_buffer_sink_ready; -wire soc_sdram_bankmachine6_cmd_buffer_sink_first; -wire soc_sdram_bankmachine6_cmd_buffer_sink_last; -wire soc_sdram_bankmachine6_cmd_buffer_sink_payload_we; -wire [21:0] soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr; -reg soc_sdram_bankmachine6_cmd_buffer_source_valid = 1'd0; -wire soc_sdram_bankmachine6_cmd_buffer_source_ready; -reg soc_sdram_bankmachine6_cmd_buffer_source_first = 1'd0; -reg soc_sdram_bankmachine6_cmd_buffer_source_last = 1'd0; -reg soc_sdram_bankmachine6_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_sdram_bankmachine6_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_sdram_bankmachine6_row = 15'd0; -reg soc_sdram_bankmachine6_row_opened = 1'd0; -wire soc_sdram_bankmachine6_row_hit; -reg soc_sdram_bankmachine6_row_open = 1'd0; -reg soc_sdram_bankmachine6_row_close = 1'd0; -reg soc_sdram_bankmachine6_row_col_n_addr_sel = 1'd0; -wire soc_sdram_bankmachine6_twtpcon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine6_twtpcon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine6_twtpcon_count = 3'd0; -wire soc_sdram_bankmachine6_trccon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine6_trccon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine6_trccon_count = 3'd0; -wire soc_sdram_bankmachine6_trascon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine6_trascon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine6_trascon_count = 3'd0; -wire soc_sdram_bankmachine7_req_valid; -wire soc_sdram_bankmachine7_req_ready; -wire soc_sdram_bankmachine7_req_we; -wire [21:0] soc_sdram_bankmachine7_req_addr; -wire soc_sdram_bankmachine7_req_lock; -reg soc_sdram_bankmachine7_req_wdata_ready = 1'd0; -reg soc_sdram_bankmachine7_req_rdata_valid = 1'd0; -wire soc_sdram_bankmachine7_refresh_req; -reg soc_sdram_bankmachine7_refresh_gnt = 1'd0; -reg soc_sdram_bankmachine7_cmd_valid = 1'd0; -reg soc_sdram_bankmachine7_cmd_ready = 1'd0; -reg [14:0] soc_sdram_bankmachine7_cmd_payload_a = 15'd0; -wire [2:0] soc_sdram_bankmachine7_cmd_payload_ba; -reg soc_sdram_bankmachine7_cmd_payload_cas = 1'd0; -reg soc_sdram_bankmachine7_cmd_payload_ras = 1'd0; -reg soc_sdram_bankmachine7_cmd_payload_we = 1'd0; -reg soc_sdram_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg soc_sdram_bankmachine7_cmd_payload_is_read = 1'd0; -reg soc_sdram_bankmachine7_cmd_payload_is_write = 1'd0; -reg soc_sdram_bankmachine7_auto_precharge = 1'd0; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready; -reg soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we; -wire [21:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -wire [24:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -wire [24:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -reg [4:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_level = 5'd0; -reg soc_sdram_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we; -wire [24:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read; -wire [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr; -wire [24:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -wire soc_sdram_bankmachine7_cmd_buffer_sink_valid; -wire soc_sdram_bankmachine7_cmd_buffer_sink_ready; -wire soc_sdram_bankmachine7_cmd_buffer_sink_first; -wire soc_sdram_bankmachine7_cmd_buffer_sink_last; -wire soc_sdram_bankmachine7_cmd_buffer_sink_payload_we; -wire [21:0] soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr; -reg soc_sdram_bankmachine7_cmd_buffer_source_valid = 1'd0; -wire soc_sdram_bankmachine7_cmd_buffer_source_ready; -reg soc_sdram_bankmachine7_cmd_buffer_source_first = 1'd0; -reg soc_sdram_bankmachine7_cmd_buffer_source_last = 1'd0; -reg soc_sdram_bankmachine7_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] soc_sdram_bankmachine7_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] soc_sdram_bankmachine7_row = 15'd0; -reg soc_sdram_bankmachine7_row_opened = 1'd0; -wire soc_sdram_bankmachine7_row_hit; -reg soc_sdram_bankmachine7_row_open = 1'd0; -reg soc_sdram_bankmachine7_row_close = 1'd0; -reg soc_sdram_bankmachine7_row_col_n_addr_sel = 1'd0; -wire soc_sdram_bankmachine7_twtpcon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine7_twtpcon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine7_twtpcon_count = 3'd0; -wire soc_sdram_bankmachine7_trccon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine7_trccon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine7_trccon_count = 3'd0; -wire soc_sdram_bankmachine7_trascon_valid; -(* dont_touch = "true" *) reg soc_sdram_bankmachine7_trascon_ready = 1'd1; -reg [2:0] soc_sdram_bankmachine7_trascon_count = 3'd0; -wire soc_sdram_ras_allowed; -wire soc_sdram_cas_allowed; -reg soc_sdram_choose_cmd_want_reads = 1'd0; -reg soc_sdram_choose_cmd_want_writes = 1'd0; -reg soc_sdram_choose_cmd_want_cmds = 1'd0; -reg soc_sdram_choose_cmd_want_activates = 1'd0; -wire soc_sdram_choose_cmd_cmd_valid; -reg soc_sdram_choose_cmd_cmd_ready = 1'd0; -wire [14:0] soc_sdram_choose_cmd_cmd_payload_a; -wire [2:0] soc_sdram_choose_cmd_cmd_payload_ba; -reg soc_sdram_choose_cmd_cmd_payload_cas = 1'd0; -reg soc_sdram_choose_cmd_cmd_payload_ras = 1'd0; -reg soc_sdram_choose_cmd_cmd_payload_we = 1'd0; -wire soc_sdram_choose_cmd_cmd_payload_is_cmd; -wire soc_sdram_choose_cmd_cmd_payload_is_read; -wire soc_sdram_choose_cmd_cmd_payload_is_write; -reg [7:0] soc_sdram_choose_cmd_valids = 8'd0; -wire [7:0] soc_sdram_choose_cmd_request; -reg [2:0] soc_sdram_choose_cmd_grant = 3'd0; -wire soc_sdram_choose_cmd_ce; -reg soc_sdram_choose_req_want_reads = 1'd0; -reg soc_sdram_choose_req_want_writes = 1'd0; -reg soc_sdram_choose_req_want_cmds = 1'd0; -reg soc_sdram_choose_req_want_activates = 1'd0; -wire soc_sdram_choose_req_cmd_valid; -reg soc_sdram_choose_req_cmd_ready = 1'd0; -wire [14:0] soc_sdram_choose_req_cmd_payload_a; -wire [2:0] soc_sdram_choose_req_cmd_payload_ba; -reg soc_sdram_choose_req_cmd_payload_cas = 1'd0; -reg soc_sdram_choose_req_cmd_payload_ras = 1'd0; -reg soc_sdram_choose_req_cmd_payload_we = 1'd0; -wire soc_sdram_choose_req_cmd_payload_is_cmd; -wire soc_sdram_choose_req_cmd_payload_is_read; -wire soc_sdram_choose_req_cmd_payload_is_write; -reg [7:0] soc_sdram_choose_req_valids = 8'd0; -wire [7:0] soc_sdram_choose_req_request; -reg [2:0] soc_sdram_choose_req_grant = 3'd0; -wire soc_sdram_choose_req_ce; -reg [14:0] soc_sdram_nop_a = 15'd0; -reg [2:0] soc_sdram_nop_ba = 3'd0; -reg [1:0] soc_sdram_steerer_sel0 = 2'd0; -reg [1:0] soc_sdram_steerer_sel1 = 2'd0; -reg [1:0] soc_sdram_steerer_sel2 = 2'd0; -reg [1:0] soc_sdram_steerer_sel3 = 2'd0; -reg soc_sdram_steerer0 = 1'd1; -reg soc_sdram_steerer1 = 1'd1; -reg soc_sdram_steerer2 = 1'd1; -reg soc_sdram_steerer3 = 1'd1; -reg soc_sdram_steerer4 = 1'd1; -reg soc_sdram_steerer5 = 1'd1; -reg soc_sdram_steerer6 = 1'd1; -reg soc_sdram_steerer7 = 1'd1; -wire soc_sdram_trrdcon_valid; -(* dont_touch = "true" *) reg soc_sdram_trrdcon_ready = 1'd1; -reg soc_sdram_trrdcon_count = 1'd0; -wire soc_sdram_tfawcon_valid; -(* dont_touch = "true" *) reg soc_sdram_tfawcon_ready = 1'd1; -wire [2:0] soc_sdram_tfawcon_count; -reg [4:0] soc_sdram_tfawcon_window = 5'd0; -wire soc_sdram_tccdcon_valid; -(* dont_touch = "true" *) reg soc_sdram_tccdcon_ready = 1'd1; -reg soc_sdram_tccdcon_count = 1'd0; -wire soc_sdram_twtrcon_valid; -(* dont_touch = "true" *) reg soc_sdram_twtrcon_ready = 1'd1; -reg [2:0] soc_sdram_twtrcon_count = 3'd0; -wire soc_sdram_read_available; -wire soc_sdram_write_available; -reg soc_sdram_en0 = 1'd0; -wire soc_sdram_max_time0; -reg [4:0] soc_sdram_time0 = 5'd0; -reg soc_sdram_en1 = 1'd0; -wire soc_sdram_max_time1; -reg [3:0] soc_sdram_time1 = 4'd0; -wire soc_sdram_go_to_refresh; -reg soc_port_cmd_valid = 1'd0; -wire soc_port_cmd_ready; -reg soc_port_cmd_payload_we = 1'd0; -reg [24:0] soc_port_cmd_payload_addr = 25'd0; -wire soc_port_wdata_valid; -wire soc_port_wdata_ready; -wire soc_port_wdata_first; -wire soc_port_wdata_last; -wire [127:0] soc_port_wdata_payload_data; -wire [15:0] soc_port_wdata_payload_we; -wire soc_port_rdata_valid; -wire soc_port_rdata_ready; -reg soc_port_rdata_first = 1'd0; -reg soc_port_rdata_last = 1'd0; -wire [127:0] soc_port_rdata_payload_data; -wire [29:0] soc_wb_sdram_adr; -wire [31:0] soc_wb_sdram_dat_w; -reg [31:0] soc_wb_sdram_dat_r = 32'd0; -wire [3:0] soc_wb_sdram_sel; -wire soc_wb_sdram_cyc; -wire soc_wb_sdram_stb; -reg soc_wb_sdram_ack = 1'd0; -wire soc_wb_sdram_we; -wire [2:0] soc_wb_sdram_cti; -wire [1:0] soc_wb_sdram_bte; -reg soc_wb_sdram_err = 1'd0; -wire [29:0] soc_litedram_wb_adr; -reg [127:0] soc_litedram_wb_dat_w = 128'd0; -wire [127:0] soc_litedram_wb_dat_r; -reg [15:0] soc_litedram_wb_sel = 16'd0; -reg soc_litedram_wb_cyc = 1'd0; -reg soc_litedram_wb_stb = 1'd0; -reg soc_litedram_wb_ack = 1'd0; -reg soc_litedram_wb_we = 1'd0; -wire [2:0] soc_litedram_wb_cti; -reg soc_write = 1'd0; -reg soc_evict = 1'd0; -reg soc_refill = 1'd0; -reg soc_read = 1'd0; -wire [29:0] soc_address_d; -reg [29:0] soc_address_q = 30'd0; -reg soc_address_ce = 1'd0; -reg soc_address_reset = 1'd0; -reg [1:0] soc_counter = 2'd0; -reg soc_counter_ce = 1'd0; -reg soc_counter_reset = 1'd0; -wire [1:0] soc_counter_offset; -wire soc_counter_done; -wire [127:0] soc_cached_data; -wire [15:0] soc_cached_sel; -wire soc_end_of_burst; -wire soc_need_refill_d; -reg soc_need_refill_q = 1'd1; -reg soc_need_refill_ce = 1'd0; -wire soc_need_refill_reset; -reg [31:0] soc_cached_datas_flipflop0_d = 32'd0; -reg [31:0] soc_cached_datas_flipflop0_q = 32'd0; -reg soc_cached_datas_ce0 = 1'd0; -reg soc_cached_datas_reset0 = 1'd0; -reg [31:0] soc_cached_datas_flipflop1_d = 32'd0; -reg [31:0] soc_cached_datas_flipflop1_q = 32'd0; -reg soc_cached_datas_ce1 = 1'd0; -reg soc_cached_datas_reset1 = 1'd0; -reg [31:0] soc_cached_datas_flipflop2_d = 32'd0; -reg [31:0] soc_cached_datas_flipflop2_q = 32'd0; -reg soc_cached_datas_ce2 = 1'd0; -reg soc_cached_datas_reset2 = 1'd0; -reg [31:0] soc_cached_datas_flipflop3_d = 32'd0; -reg [31:0] soc_cached_datas_flipflop3_q = 32'd0; -reg soc_cached_datas_ce3 = 1'd0; -reg soc_cached_datas_reset3 = 1'd0; -wire [3:0] soc_cached_sels_flipflop0_d; -reg [3:0] soc_cached_sels_flipflop0_q = 4'd0; -reg soc_cached_sels_ce0 = 1'd0; -wire soc_cached_sels_reset0; -wire [3:0] soc_cached_sels_flipflop1_d; -reg [3:0] soc_cached_sels_flipflop1_q = 4'd0; -reg soc_cached_sels_ce1 = 1'd0; -wire soc_cached_sels_reset1; -wire [3:0] soc_cached_sels_flipflop2_d; -reg [3:0] soc_cached_sels_flipflop2_q = 4'd0; -reg soc_cached_sels_ce2 = 1'd0; -wire soc_cached_sels_reset2; -wire [3:0] soc_cached_sels_flipflop3_d; -reg [3:0] soc_cached_sels_flipflop3_q = 4'd0; -reg soc_cached_sels_ce3 = 1'd0; -wire soc_cached_sels_reset3; -reg soc_write_sel0 = 1'd0; -reg soc_write_sel1 = 1'd0; -reg soc_write_sel2 = 1'd0; -reg soc_write_sel3 = 1'd0; -wire soc_wdata_converter_sink_valid; -wire soc_wdata_converter_sink_ready; -reg soc_wdata_converter_sink_first = 1'd0; -reg soc_wdata_converter_sink_last = 1'd0; -wire [127:0] soc_wdata_converter_sink_payload_data; -wire [15:0] soc_wdata_converter_sink_payload_we; -wire soc_wdata_converter_source_valid; -wire soc_wdata_converter_source_ready; -wire soc_wdata_converter_source_first; -wire soc_wdata_converter_source_last; -wire [127:0] soc_wdata_converter_source_payload_data; -wire [15:0] soc_wdata_converter_source_payload_we; -wire soc_wdata_converter_converter_sink_valid; -wire soc_wdata_converter_converter_sink_ready; -wire soc_wdata_converter_converter_sink_first; -wire soc_wdata_converter_converter_sink_last; -wire [143:0] soc_wdata_converter_converter_sink_payload_data; -wire soc_wdata_converter_converter_source_valid; -wire soc_wdata_converter_converter_source_ready; -wire soc_wdata_converter_converter_source_first; -wire soc_wdata_converter_converter_source_last; -wire [143:0] soc_wdata_converter_converter_source_payload_data; -wire soc_wdata_converter_converter_source_payload_valid_token_count; -wire soc_wdata_converter_source_source_valid; -wire soc_wdata_converter_source_source_ready; -wire soc_wdata_converter_source_source_first; -wire soc_wdata_converter_source_source_last; -wire [143:0] soc_wdata_converter_source_source_payload_data; -wire soc_rdata_converter_sink_valid; -wire soc_rdata_converter_sink_ready; -wire soc_rdata_converter_sink_first; -wire soc_rdata_converter_sink_last; -wire [127:0] soc_rdata_converter_sink_payload_data; -wire soc_rdata_converter_source_valid; -wire soc_rdata_converter_source_ready; -wire soc_rdata_converter_source_first; -wire soc_rdata_converter_source_last; -wire [127:0] soc_rdata_converter_source_payload_data; -wire soc_rdata_converter_converter_sink_valid; -wire soc_rdata_converter_converter_sink_ready; -wire soc_rdata_converter_converter_sink_first; -wire soc_rdata_converter_converter_sink_last; -wire [127:0] soc_rdata_converter_converter_sink_payload_data; -wire soc_rdata_converter_converter_source_valid; -wire soc_rdata_converter_converter_source_ready; -wire soc_rdata_converter_converter_source_first; -wire soc_rdata_converter_converter_source_last; -wire [127:0] soc_rdata_converter_converter_source_payload_data; -wire soc_rdata_converter_converter_source_payload_valid_token_count; -wire soc_rdata_converter_source_source_valid; -wire soc_rdata_converter_source_source_ready; -wire soc_rdata_converter_source_source_first; -wire soc_rdata_converter_source_source_last; -wire [127:0] soc_rdata_converter_source_source_payload_data; -reg soc_count = 1'd0; -reg soc_init_done_storage = 1'd0; -reg soc_init_done_re = 1'd0; -reg soc_init_error_storage = 1'd0; -reg soc_init_error_re = 1'd0; -wire soc_cmd_valid; -wire soc_cmd_ready; -wire soc_cmd_payload_we; -wire [24:0] soc_cmd_payload_addr; -wire soc_wdata_valid; -wire soc_wdata_ready; -wire [127:0] soc_wdata_payload_data; -wire [15:0] soc_wdata_payload_we; -wire soc_rdata_valid; -wire soc_rdata_ready; -wire [127:0] soc_rdata_payload_data; -reg vns_wb2csr_state = 1'd0; -reg vns_wb2csr_next_state = 1'd0; -wire vns_pll_fb0; -wire vns_pll_fb1; -reg [1:0] vns_refresher_state = 2'd0; -reg [1:0] vns_refresher_next_state = 2'd0; -reg [3:0] vns_bankmachine0_state = 4'd0; -reg [3:0] vns_bankmachine0_next_state = 4'd0; -reg [3:0] vns_bankmachine1_state = 4'd0; -reg [3:0] vns_bankmachine1_next_state = 4'd0; -reg [3:0] vns_bankmachine2_state = 4'd0; -reg [3:0] vns_bankmachine2_next_state = 4'd0; -reg [3:0] vns_bankmachine3_state = 4'd0; -reg [3:0] vns_bankmachine3_next_state = 4'd0; -reg [3:0] vns_bankmachine4_state = 4'd0; -reg [3:0] vns_bankmachine4_next_state = 4'd0; -reg [3:0] vns_bankmachine5_state = 4'd0; -reg [3:0] vns_bankmachine5_next_state = 4'd0; -reg [3:0] vns_bankmachine6_state = 4'd0; -reg [3:0] vns_bankmachine6_next_state = 4'd0; -reg [3:0] vns_bankmachine7_state = 4'd0; -reg [3:0] vns_bankmachine7_next_state = 4'd0; -reg [3:0] vns_multiplexer_state = 4'd0; -reg [3:0] vns_multiplexer_next_state = 4'd0; -wire [1:0] vns_roundrobin0_request; -reg vns_roundrobin0_grant = 1'd0; -wire vns_roundrobin0_ce; -wire [1:0] vns_roundrobin1_request; -reg vns_roundrobin1_grant = 1'd0; -wire vns_roundrobin1_ce; -wire [1:0] vns_roundrobin2_request; -reg vns_roundrobin2_grant = 1'd0; -wire vns_roundrobin2_ce; -wire [1:0] vns_roundrobin3_request; -reg vns_roundrobin3_grant = 1'd0; -wire vns_roundrobin3_ce; -wire [1:0] vns_roundrobin4_request; -reg vns_roundrobin4_grant = 1'd0; -wire vns_roundrobin4_ce; -wire [1:0] vns_roundrobin5_request; -reg vns_roundrobin5_grant = 1'd0; -wire vns_roundrobin5_ce; -wire [1:0] vns_roundrobin6_request; -reg vns_roundrobin6_grant = 1'd0; -wire vns_roundrobin6_ce; -wire [1:0] vns_roundrobin7_request; -reg vns_roundrobin7_grant = 1'd0; -wire vns_roundrobin7_ce; -reg vns_locked0 = 1'd0; -reg vns_locked1 = 1'd0; -reg vns_locked2 = 1'd0; -reg vns_locked3 = 1'd0; -reg vns_locked4 = 1'd0; -reg vns_locked5 = 1'd0; -reg vns_locked6 = 1'd0; -reg vns_locked7 = 1'd0; -reg vns_locked8 = 1'd0; -reg vns_locked9 = 1'd0; -reg vns_locked10 = 1'd0; -reg vns_locked11 = 1'd0; -reg vns_locked12 = 1'd0; -reg vns_locked13 = 1'd0; -reg vns_locked14 = 1'd0; -reg vns_locked15 = 1'd0; -reg vns_new_master_wdata_ready0 = 1'd0; -reg vns_new_master_wdata_ready1 = 1'd0; -reg vns_new_master_wdata_ready2 = 1'd0; -reg vns_new_master_wdata_ready3 = 1'd0; -reg vns_new_master_wdata_ready4 = 1'd0; -reg vns_new_master_wdata_ready5 = 1'd0; -reg vns_new_master_rdata_valid0 = 1'd0; -reg vns_new_master_rdata_valid1 = 1'd0; -reg vns_new_master_rdata_valid2 = 1'd0; -reg vns_new_master_rdata_valid3 = 1'd0; -reg vns_new_master_rdata_valid4 = 1'd0; -reg vns_new_master_rdata_valid5 = 1'd0; -reg vns_new_master_rdata_valid6 = 1'd0; -reg vns_new_master_rdata_valid7 = 1'd0; -reg vns_new_master_rdata_valid8 = 1'd0; -reg vns_new_master_rdata_valid9 = 1'd0; -reg vns_new_master_rdata_valid10 = 1'd0; -reg vns_new_master_rdata_valid11 = 1'd0; -reg vns_new_master_rdata_valid12 = 1'd0; -reg vns_new_master_rdata_valid13 = 1'd0; -reg vns_new_master_rdata_valid14 = 1'd0; -reg vns_new_master_rdata_valid15 = 1'd0; -reg vns_new_master_rdata_valid16 = 1'd0; -reg vns_new_master_rdata_valid17 = 1'd0; -reg [2:0] vns_converter_state = 3'd0; -reg [2:0] vns_converter_next_state = 3'd0; -reg [1:0] vns_litedramwishbone2native_state = 2'd0; -reg [1:0] vns_litedramwishbone2native_next_state = 2'd0; -reg soc_count_next_value = 1'd0; -reg soc_count_next_value_ce = 1'd0; -wire [29:0] vns_shared_adr; -wire [31:0] vns_shared_dat_w; -reg [31:0] vns_shared_dat_r = 32'd0; -wire [3:0] vns_shared_sel; -wire vns_shared_cyc; -wire vns_shared_stb; -reg vns_shared_ack = 1'd0; -wire vns_shared_we; -wire [2:0] vns_shared_cti; -wire [1:0] vns_shared_bte; -wire vns_shared_err; -wire [1:0] vns_request; -reg vns_grant = 1'd0; -reg [3:0] vns_slave_sel = 4'd0; -reg [3:0] vns_slave_sel_r = 4'd0; -reg vns_error = 1'd0; -wire vns_wait; -wire vns_done; -reg [19:0] vns_count = 20'd1000000; -wire [13:0] vns_interface0_bank_bus_adr; -wire vns_interface0_bank_bus_we; -wire [7:0] vns_interface0_bank_bus_dat_w; -reg [7:0] vns_interface0_bank_bus_dat_r = 8'd0; -wire vns_csrbank0_reset0_re; -wire vns_csrbank0_reset0_r; -wire vns_csrbank0_reset0_we; -wire vns_csrbank0_reset0_w; -wire vns_csrbank0_scratch3_re; -wire [7:0] vns_csrbank0_scratch3_r; -wire vns_csrbank0_scratch3_we; -wire [7:0] vns_csrbank0_scratch3_w; -wire vns_csrbank0_scratch2_re; -wire [7:0] vns_csrbank0_scratch2_r; -wire vns_csrbank0_scratch2_we; -wire [7:0] vns_csrbank0_scratch2_w; -wire vns_csrbank0_scratch1_re; -wire [7:0] vns_csrbank0_scratch1_r; -wire vns_csrbank0_scratch1_we; -wire [7:0] vns_csrbank0_scratch1_w; -wire vns_csrbank0_scratch0_re; -wire [7:0] vns_csrbank0_scratch0_r; -wire vns_csrbank0_scratch0_we; -wire [7:0] vns_csrbank0_scratch0_w; -wire vns_csrbank0_bus_errors3_re; -wire [7:0] vns_csrbank0_bus_errors3_r; -wire vns_csrbank0_bus_errors3_we; -wire [7:0] vns_csrbank0_bus_errors3_w; -wire vns_csrbank0_bus_errors2_re; -wire [7:0] vns_csrbank0_bus_errors2_r; -wire vns_csrbank0_bus_errors2_we; -wire [7:0] vns_csrbank0_bus_errors2_w; -wire vns_csrbank0_bus_errors1_re; -wire [7:0] vns_csrbank0_bus_errors1_r; -wire vns_csrbank0_bus_errors1_we; -wire [7:0] vns_csrbank0_bus_errors1_w; -wire vns_csrbank0_bus_errors0_re; -wire [7:0] vns_csrbank0_bus_errors0_r; -wire vns_csrbank0_bus_errors0_we; -wire [7:0] vns_csrbank0_bus_errors0_w; -wire vns_csrbank0_sel; -wire [13:0] vns_interface1_bank_bus_adr; -wire vns_interface1_bank_bus_we; -wire [7:0] vns_interface1_bank_bus_dat_w; -reg [7:0] vns_interface1_bank_bus_dat_r = 8'd0; -wire vns_csrbank1_init_done0_re; -wire vns_csrbank1_init_done0_r; -wire vns_csrbank1_init_done0_we; -wire vns_csrbank1_init_done0_w; -wire vns_csrbank1_init_error0_re; -wire vns_csrbank1_init_error0_r; -wire vns_csrbank1_init_error0_we; -wire vns_csrbank1_init_error0_w; -wire vns_csrbank1_sel; -wire [13:0] vns_interface2_bank_bus_adr; -wire vns_interface2_bank_bus_we; -wire [7:0] vns_interface2_bank_bus_dat_w; -reg [7:0] vns_interface2_bank_bus_dat_r = 8'd0; -wire vns_csrbank2_half_sys8x_taps0_re; -wire [4:0] vns_csrbank2_half_sys8x_taps0_r; -wire vns_csrbank2_half_sys8x_taps0_we; -wire [4:0] vns_csrbank2_half_sys8x_taps0_w; -wire vns_csrbank2_wlevel_en0_re; -wire vns_csrbank2_wlevel_en0_r; -wire vns_csrbank2_wlevel_en0_we; -wire vns_csrbank2_wlevel_en0_w; -wire vns_csrbank2_dly_sel0_re; -wire [1:0] vns_csrbank2_dly_sel0_r; -wire vns_csrbank2_dly_sel0_we; -wire [1:0] vns_csrbank2_dly_sel0_w; -wire vns_csrbank2_sel; -wire [13:0] vns_interface3_bank_bus_adr; -wire vns_interface3_bank_bus_we; -wire [7:0] vns_interface3_bank_bus_dat_w; -reg [7:0] vns_interface3_bank_bus_dat_r = 8'd0; -wire vns_csrbank3_dfii_control0_re; -wire [3:0] vns_csrbank3_dfii_control0_r; -wire vns_csrbank3_dfii_control0_we; -wire [3:0] vns_csrbank3_dfii_control0_w; -wire vns_csrbank3_dfii_pi0_command0_re; -wire [5:0] vns_csrbank3_dfii_pi0_command0_r; -wire vns_csrbank3_dfii_pi0_command0_we; -wire [5:0] vns_csrbank3_dfii_pi0_command0_w; -wire vns_csrbank3_dfii_pi0_address1_re; -wire [6:0] vns_csrbank3_dfii_pi0_address1_r; -wire vns_csrbank3_dfii_pi0_address1_we; -wire [6:0] vns_csrbank3_dfii_pi0_address1_w; -wire vns_csrbank3_dfii_pi0_address0_re; -wire [7:0] vns_csrbank3_dfii_pi0_address0_r; -wire vns_csrbank3_dfii_pi0_address0_we; -wire [7:0] vns_csrbank3_dfii_pi0_address0_w; -wire vns_csrbank3_dfii_pi0_baddress0_re; -wire [2:0] vns_csrbank3_dfii_pi0_baddress0_r; -wire vns_csrbank3_dfii_pi0_baddress0_we; -wire [2:0] vns_csrbank3_dfii_pi0_baddress0_w; -wire vns_csrbank3_dfii_pi0_wrdata3_re; -wire [7:0] vns_csrbank3_dfii_pi0_wrdata3_r; -wire vns_csrbank3_dfii_pi0_wrdata3_we; -wire [7:0] vns_csrbank3_dfii_pi0_wrdata3_w; -wire vns_csrbank3_dfii_pi0_wrdata2_re; -wire [7:0] vns_csrbank3_dfii_pi0_wrdata2_r; -wire vns_csrbank3_dfii_pi0_wrdata2_we; -wire [7:0] vns_csrbank3_dfii_pi0_wrdata2_w; -wire vns_csrbank3_dfii_pi0_wrdata1_re; -wire [7:0] vns_csrbank3_dfii_pi0_wrdata1_r; -wire vns_csrbank3_dfii_pi0_wrdata1_we; -wire [7:0] vns_csrbank3_dfii_pi0_wrdata1_w; -wire vns_csrbank3_dfii_pi0_wrdata0_re; -wire [7:0] vns_csrbank3_dfii_pi0_wrdata0_r; -wire vns_csrbank3_dfii_pi0_wrdata0_we; -wire [7:0] vns_csrbank3_dfii_pi0_wrdata0_w; -wire vns_csrbank3_dfii_pi0_rddata3_re; -wire [7:0] vns_csrbank3_dfii_pi0_rddata3_r; -wire vns_csrbank3_dfii_pi0_rddata3_we; -wire [7:0] vns_csrbank3_dfii_pi0_rddata3_w; -wire vns_csrbank3_dfii_pi0_rddata2_re; -wire [7:0] vns_csrbank3_dfii_pi0_rddata2_r; -wire vns_csrbank3_dfii_pi0_rddata2_we; -wire [7:0] vns_csrbank3_dfii_pi0_rddata2_w; -wire vns_csrbank3_dfii_pi0_rddata1_re; -wire [7:0] vns_csrbank3_dfii_pi0_rddata1_r; -wire vns_csrbank3_dfii_pi0_rddata1_we; -wire [7:0] vns_csrbank3_dfii_pi0_rddata1_w; -wire vns_csrbank3_dfii_pi0_rddata0_re; -wire [7:0] vns_csrbank3_dfii_pi0_rddata0_r; -wire vns_csrbank3_dfii_pi0_rddata0_we; -wire [7:0] vns_csrbank3_dfii_pi0_rddata0_w; -wire vns_csrbank3_dfii_pi1_command0_re; -wire [5:0] vns_csrbank3_dfii_pi1_command0_r; -wire vns_csrbank3_dfii_pi1_command0_we; -wire [5:0] vns_csrbank3_dfii_pi1_command0_w; -wire vns_csrbank3_dfii_pi1_address1_re; -wire [6:0] vns_csrbank3_dfii_pi1_address1_r; -wire vns_csrbank3_dfii_pi1_address1_we; -wire [6:0] vns_csrbank3_dfii_pi1_address1_w; -wire vns_csrbank3_dfii_pi1_address0_re; -wire [7:0] vns_csrbank3_dfii_pi1_address0_r; -wire vns_csrbank3_dfii_pi1_address0_we; -wire [7:0] vns_csrbank3_dfii_pi1_address0_w; -wire vns_csrbank3_dfii_pi1_baddress0_re; -wire [2:0] vns_csrbank3_dfii_pi1_baddress0_r; -wire vns_csrbank3_dfii_pi1_baddress0_we; -wire [2:0] vns_csrbank3_dfii_pi1_baddress0_w; -wire vns_csrbank3_dfii_pi1_wrdata3_re; -wire [7:0] vns_csrbank3_dfii_pi1_wrdata3_r; -wire vns_csrbank3_dfii_pi1_wrdata3_we; -wire [7:0] vns_csrbank3_dfii_pi1_wrdata3_w; -wire vns_csrbank3_dfii_pi1_wrdata2_re; -wire [7:0] vns_csrbank3_dfii_pi1_wrdata2_r; -wire vns_csrbank3_dfii_pi1_wrdata2_we; -wire [7:0] vns_csrbank3_dfii_pi1_wrdata2_w; -wire vns_csrbank3_dfii_pi1_wrdata1_re; -wire [7:0] vns_csrbank3_dfii_pi1_wrdata1_r; -wire vns_csrbank3_dfii_pi1_wrdata1_we; -wire [7:0] vns_csrbank3_dfii_pi1_wrdata1_w; -wire vns_csrbank3_dfii_pi1_wrdata0_re; -wire [7:0] vns_csrbank3_dfii_pi1_wrdata0_r; -wire vns_csrbank3_dfii_pi1_wrdata0_we; -wire [7:0] vns_csrbank3_dfii_pi1_wrdata0_w; -wire vns_csrbank3_dfii_pi1_rddata3_re; -wire [7:0] vns_csrbank3_dfii_pi1_rddata3_r; -wire vns_csrbank3_dfii_pi1_rddata3_we; -wire [7:0] vns_csrbank3_dfii_pi1_rddata3_w; -wire vns_csrbank3_dfii_pi1_rddata2_re; -wire [7:0] vns_csrbank3_dfii_pi1_rddata2_r; -wire vns_csrbank3_dfii_pi1_rddata2_we; -wire [7:0] vns_csrbank3_dfii_pi1_rddata2_w; -wire vns_csrbank3_dfii_pi1_rddata1_re; -wire [7:0] vns_csrbank3_dfii_pi1_rddata1_r; -wire vns_csrbank3_dfii_pi1_rddata1_we; -wire [7:0] vns_csrbank3_dfii_pi1_rddata1_w; -wire vns_csrbank3_dfii_pi1_rddata0_re; -wire [7:0] vns_csrbank3_dfii_pi1_rddata0_r; -wire vns_csrbank3_dfii_pi1_rddata0_we; -wire [7:0] vns_csrbank3_dfii_pi1_rddata0_w; -wire vns_csrbank3_dfii_pi2_command0_re; -wire [5:0] vns_csrbank3_dfii_pi2_command0_r; -wire vns_csrbank3_dfii_pi2_command0_we; -wire [5:0] vns_csrbank3_dfii_pi2_command0_w; -wire vns_csrbank3_dfii_pi2_address1_re; -wire [6:0] vns_csrbank3_dfii_pi2_address1_r; -wire vns_csrbank3_dfii_pi2_address1_we; -wire [6:0] vns_csrbank3_dfii_pi2_address1_w; -wire vns_csrbank3_dfii_pi2_address0_re; -wire [7:0] vns_csrbank3_dfii_pi2_address0_r; -wire vns_csrbank3_dfii_pi2_address0_we; -wire [7:0] vns_csrbank3_dfii_pi2_address0_w; -wire vns_csrbank3_dfii_pi2_baddress0_re; -wire [2:0] vns_csrbank3_dfii_pi2_baddress0_r; -wire vns_csrbank3_dfii_pi2_baddress0_we; -wire [2:0] vns_csrbank3_dfii_pi2_baddress0_w; -wire vns_csrbank3_dfii_pi2_wrdata3_re; -wire [7:0] vns_csrbank3_dfii_pi2_wrdata3_r; -wire vns_csrbank3_dfii_pi2_wrdata3_we; -wire [7:0] vns_csrbank3_dfii_pi2_wrdata3_w; -wire vns_csrbank3_dfii_pi2_wrdata2_re; -wire [7:0] vns_csrbank3_dfii_pi2_wrdata2_r; -wire vns_csrbank3_dfii_pi2_wrdata2_we; -wire [7:0] vns_csrbank3_dfii_pi2_wrdata2_w; -wire vns_csrbank3_dfii_pi2_wrdata1_re; -wire [7:0] vns_csrbank3_dfii_pi2_wrdata1_r; -wire vns_csrbank3_dfii_pi2_wrdata1_we; -wire [7:0] vns_csrbank3_dfii_pi2_wrdata1_w; -wire vns_csrbank3_dfii_pi2_wrdata0_re; -wire [7:0] vns_csrbank3_dfii_pi2_wrdata0_r; -wire vns_csrbank3_dfii_pi2_wrdata0_we; -wire [7:0] vns_csrbank3_dfii_pi2_wrdata0_w; -wire vns_csrbank3_dfii_pi2_rddata3_re; -wire [7:0] vns_csrbank3_dfii_pi2_rddata3_r; -wire vns_csrbank3_dfii_pi2_rddata3_we; -wire [7:0] vns_csrbank3_dfii_pi2_rddata3_w; -wire vns_csrbank3_dfii_pi2_rddata2_re; -wire [7:0] vns_csrbank3_dfii_pi2_rddata2_r; -wire vns_csrbank3_dfii_pi2_rddata2_we; -wire [7:0] vns_csrbank3_dfii_pi2_rddata2_w; -wire vns_csrbank3_dfii_pi2_rddata1_re; -wire [7:0] vns_csrbank3_dfii_pi2_rddata1_r; -wire vns_csrbank3_dfii_pi2_rddata1_we; -wire [7:0] vns_csrbank3_dfii_pi2_rddata1_w; -wire vns_csrbank3_dfii_pi2_rddata0_re; -wire [7:0] vns_csrbank3_dfii_pi2_rddata0_r; -wire vns_csrbank3_dfii_pi2_rddata0_we; -wire [7:0] vns_csrbank3_dfii_pi2_rddata0_w; -wire vns_csrbank3_dfii_pi3_command0_re; -wire [5:0] vns_csrbank3_dfii_pi3_command0_r; -wire vns_csrbank3_dfii_pi3_command0_we; -wire [5:0] vns_csrbank3_dfii_pi3_command0_w; -wire vns_csrbank3_dfii_pi3_address1_re; -wire [6:0] vns_csrbank3_dfii_pi3_address1_r; -wire vns_csrbank3_dfii_pi3_address1_we; -wire [6:0] vns_csrbank3_dfii_pi3_address1_w; -wire vns_csrbank3_dfii_pi3_address0_re; -wire [7:0] vns_csrbank3_dfii_pi3_address0_r; -wire vns_csrbank3_dfii_pi3_address0_we; -wire [7:0] vns_csrbank3_dfii_pi3_address0_w; -wire vns_csrbank3_dfii_pi3_baddress0_re; -wire [2:0] vns_csrbank3_dfii_pi3_baddress0_r; -wire vns_csrbank3_dfii_pi3_baddress0_we; -wire [2:0] vns_csrbank3_dfii_pi3_baddress0_w; -wire vns_csrbank3_dfii_pi3_wrdata3_re; -wire [7:0] vns_csrbank3_dfii_pi3_wrdata3_r; -wire vns_csrbank3_dfii_pi3_wrdata3_we; -wire [7:0] vns_csrbank3_dfii_pi3_wrdata3_w; -wire vns_csrbank3_dfii_pi3_wrdata2_re; -wire [7:0] vns_csrbank3_dfii_pi3_wrdata2_r; -wire vns_csrbank3_dfii_pi3_wrdata2_we; -wire [7:0] vns_csrbank3_dfii_pi3_wrdata2_w; -wire vns_csrbank3_dfii_pi3_wrdata1_re; -wire [7:0] vns_csrbank3_dfii_pi3_wrdata1_r; -wire vns_csrbank3_dfii_pi3_wrdata1_we; -wire [7:0] vns_csrbank3_dfii_pi3_wrdata1_w; -wire vns_csrbank3_dfii_pi3_wrdata0_re; -wire [7:0] vns_csrbank3_dfii_pi3_wrdata0_r; -wire vns_csrbank3_dfii_pi3_wrdata0_we; -wire [7:0] vns_csrbank3_dfii_pi3_wrdata0_w; -wire vns_csrbank3_dfii_pi3_rddata3_re; -wire [7:0] vns_csrbank3_dfii_pi3_rddata3_r; -wire vns_csrbank3_dfii_pi3_rddata3_we; -wire [7:0] vns_csrbank3_dfii_pi3_rddata3_w; -wire vns_csrbank3_dfii_pi3_rddata2_re; -wire [7:0] vns_csrbank3_dfii_pi3_rddata2_r; -wire vns_csrbank3_dfii_pi3_rddata2_we; -wire [7:0] vns_csrbank3_dfii_pi3_rddata2_w; -wire vns_csrbank3_dfii_pi3_rddata1_re; -wire [7:0] vns_csrbank3_dfii_pi3_rddata1_r; -wire vns_csrbank3_dfii_pi3_rddata1_we; -wire [7:0] vns_csrbank3_dfii_pi3_rddata1_w; -wire vns_csrbank3_dfii_pi3_rddata0_re; -wire [7:0] vns_csrbank3_dfii_pi3_rddata0_r; -wire vns_csrbank3_dfii_pi3_rddata0_we; -wire [7:0] vns_csrbank3_dfii_pi3_rddata0_w; -wire vns_csrbank3_sel; -wire [13:0] vns_interface4_bank_bus_adr; -wire vns_interface4_bank_bus_we; -wire [7:0] vns_interface4_bank_bus_dat_w; -reg [7:0] vns_interface4_bank_bus_dat_r = 8'd0; -wire vns_csrbank4_load3_re; -wire [7:0] vns_csrbank4_load3_r; -wire vns_csrbank4_load3_we; -wire [7:0] vns_csrbank4_load3_w; -wire vns_csrbank4_load2_re; -wire [7:0] vns_csrbank4_load2_r; -wire vns_csrbank4_load2_we; -wire [7:0] vns_csrbank4_load2_w; -wire vns_csrbank4_load1_re; -wire [7:0] vns_csrbank4_load1_r; -wire vns_csrbank4_load1_we; -wire [7:0] vns_csrbank4_load1_w; -wire vns_csrbank4_load0_re; -wire [7:0] vns_csrbank4_load0_r; -wire vns_csrbank4_load0_we; -wire [7:0] vns_csrbank4_load0_w; -wire vns_csrbank4_reload3_re; -wire [7:0] vns_csrbank4_reload3_r; -wire vns_csrbank4_reload3_we; -wire [7:0] vns_csrbank4_reload3_w; -wire vns_csrbank4_reload2_re; -wire [7:0] vns_csrbank4_reload2_r; -wire vns_csrbank4_reload2_we; -wire [7:0] vns_csrbank4_reload2_w; -wire vns_csrbank4_reload1_re; -wire [7:0] vns_csrbank4_reload1_r; -wire vns_csrbank4_reload1_we; -wire [7:0] vns_csrbank4_reload1_w; -wire vns_csrbank4_reload0_re; -wire [7:0] vns_csrbank4_reload0_r; -wire vns_csrbank4_reload0_we; -wire [7:0] vns_csrbank4_reload0_w; -wire vns_csrbank4_en0_re; -wire vns_csrbank4_en0_r; -wire vns_csrbank4_en0_we; -wire vns_csrbank4_en0_w; -wire vns_csrbank4_update_value0_re; -wire vns_csrbank4_update_value0_r; -wire vns_csrbank4_update_value0_we; -wire vns_csrbank4_update_value0_w; -wire vns_csrbank4_value3_re; -wire [7:0] vns_csrbank4_value3_r; -wire vns_csrbank4_value3_we; -wire [7:0] vns_csrbank4_value3_w; -wire vns_csrbank4_value2_re; -wire [7:0] vns_csrbank4_value2_r; -wire vns_csrbank4_value2_we; -wire [7:0] vns_csrbank4_value2_w; -wire vns_csrbank4_value1_re; -wire [7:0] vns_csrbank4_value1_r; -wire vns_csrbank4_value1_we; -wire [7:0] vns_csrbank4_value1_w; -wire vns_csrbank4_value0_re; -wire [7:0] vns_csrbank4_value0_r; -wire vns_csrbank4_value0_we; -wire [7:0] vns_csrbank4_value0_w; -wire vns_csrbank4_ev_enable0_re; -wire vns_csrbank4_ev_enable0_r; -wire vns_csrbank4_ev_enable0_we; -wire vns_csrbank4_ev_enable0_w; -wire vns_csrbank4_sel; -wire [13:0] vns_interface5_bank_bus_adr; -wire vns_interface5_bank_bus_we; -wire [7:0] vns_interface5_bank_bus_dat_w; -reg [7:0] vns_interface5_bank_bus_dat_r = 8'd0; -wire vns_csrbank5_txfull_re; -wire vns_csrbank5_txfull_r; -wire vns_csrbank5_txfull_we; -wire vns_csrbank5_txfull_w; -wire vns_csrbank5_rxempty_re; -wire vns_csrbank5_rxempty_r; -wire vns_csrbank5_rxempty_we; -wire vns_csrbank5_rxempty_w; -wire vns_csrbank5_ev_enable0_re; -wire [1:0] vns_csrbank5_ev_enable0_r; -wire vns_csrbank5_ev_enable0_we; -wire [1:0] vns_csrbank5_ev_enable0_w; -wire vns_csrbank5_sel; -wire [13:0] vns_interface6_bank_bus_adr; -wire vns_interface6_bank_bus_we; -wire [7:0] vns_interface6_bank_bus_dat_w; -reg [7:0] vns_interface6_bank_bus_dat_r = 8'd0; -wire vns_csrbank6_tuning_word3_re; -wire [7:0] vns_csrbank6_tuning_word3_r; -wire vns_csrbank6_tuning_word3_we; -wire [7:0] vns_csrbank6_tuning_word3_w; -wire vns_csrbank6_tuning_word2_re; -wire [7:0] vns_csrbank6_tuning_word2_r; -wire vns_csrbank6_tuning_word2_we; -wire [7:0] vns_csrbank6_tuning_word2_w; -wire vns_csrbank6_tuning_word1_re; -wire [7:0] vns_csrbank6_tuning_word1_r; -wire vns_csrbank6_tuning_word1_we; -wire [7:0] vns_csrbank6_tuning_word1_w; -wire vns_csrbank6_tuning_word0_re; -wire [7:0] vns_csrbank6_tuning_word0_r; -wire vns_csrbank6_tuning_word0_we; -wire [7:0] vns_csrbank6_tuning_word0_w; -wire vns_csrbank6_sel; -wire [13:0] vns_adr; -wire vns_we; -wire [7:0] vns_dat_w; -wire [7:0] vns_dat_r; -reg vns_rhs_array_muxed0 = 1'd0; -reg [14:0] vns_rhs_array_muxed1 = 15'd0; -reg [2:0] vns_rhs_array_muxed2 = 3'd0; -reg vns_rhs_array_muxed3 = 1'd0; -reg vns_rhs_array_muxed4 = 1'd0; -reg vns_rhs_array_muxed5 = 1'd0; -reg vns_t_array_muxed0 = 1'd0; -reg vns_t_array_muxed1 = 1'd0; -reg vns_t_array_muxed2 = 1'd0; -reg vns_rhs_array_muxed6 = 1'd0; -reg [14:0] vns_rhs_array_muxed7 = 15'd0; -reg [2:0] vns_rhs_array_muxed8 = 3'd0; -reg vns_rhs_array_muxed9 = 1'd0; -reg vns_rhs_array_muxed10 = 1'd0; -reg vns_rhs_array_muxed11 = 1'd0; -reg vns_t_array_muxed3 = 1'd0; -reg vns_t_array_muxed4 = 1'd0; -reg vns_t_array_muxed5 = 1'd0; -reg [21:0] vns_rhs_array_muxed12 = 22'd0; -reg vns_rhs_array_muxed13 = 1'd0; -reg vns_rhs_array_muxed14 = 1'd0; -reg [21:0] vns_rhs_array_muxed15 = 22'd0; -reg vns_rhs_array_muxed16 = 1'd0; -reg vns_rhs_array_muxed17 = 1'd0; -reg [21:0] vns_rhs_array_muxed18 = 22'd0; -reg vns_rhs_array_muxed19 = 1'd0; -reg vns_rhs_array_muxed20 = 1'd0; -reg [21:0] vns_rhs_array_muxed21 = 22'd0; -reg vns_rhs_array_muxed22 = 1'd0; -reg vns_rhs_array_muxed23 = 1'd0; -reg [21:0] vns_rhs_array_muxed24 = 22'd0; -reg vns_rhs_array_muxed25 = 1'd0; -reg vns_rhs_array_muxed26 = 1'd0; -reg [21:0] vns_rhs_array_muxed27 = 22'd0; -reg vns_rhs_array_muxed28 = 1'd0; -reg vns_rhs_array_muxed29 = 1'd0; -reg [21:0] vns_rhs_array_muxed30 = 22'd0; -reg vns_rhs_array_muxed31 = 1'd0; -reg vns_rhs_array_muxed32 = 1'd0; -reg [21:0] vns_rhs_array_muxed33 = 22'd0; -reg vns_rhs_array_muxed34 = 1'd0; -reg vns_rhs_array_muxed35 = 1'd0; -reg [29:0] vns_rhs_array_muxed36 = 30'd0; -reg [31:0] vns_rhs_array_muxed37 = 32'd0; -reg [3:0] vns_rhs_array_muxed38 = 4'd0; -reg vns_rhs_array_muxed39 = 1'd0; -reg vns_rhs_array_muxed40 = 1'd0; -reg vns_rhs_array_muxed41 = 1'd0; -reg [2:0] vns_rhs_array_muxed42 = 3'd0; -reg [1:0] vns_rhs_array_muxed43 = 2'd0; -reg [2:0] vns_array_muxed0 = 3'd0; -reg [14:0] vns_array_muxed1 = 15'd0; -reg vns_array_muxed2 = 1'd0; -reg vns_array_muxed3 = 1'd0; -reg vns_array_muxed4 = 1'd0; -reg vns_array_muxed5 = 1'd0; -reg vns_array_muxed6 = 1'd0; -reg [2:0] vns_array_muxed7 = 3'd0; -reg [14:0] vns_array_muxed8 = 15'd0; -reg vns_array_muxed9 = 1'd0; -reg vns_array_muxed10 = 1'd0; -reg vns_array_muxed11 = 1'd0; -reg vns_array_muxed12 = 1'd0; -reg vns_array_muxed13 = 1'd0; -reg [2:0] vns_array_muxed14 = 3'd0; -reg [14:0] vns_array_muxed15 = 15'd0; -reg vns_array_muxed16 = 1'd0; -reg vns_array_muxed17 = 1'd0; -reg vns_array_muxed18 = 1'd0; -reg vns_array_muxed19 = 1'd0; -reg vns_array_muxed20 = 1'd0; -reg [2:0] vns_array_muxed21 = 3'd0; -reg [14:0] vns_array_muxed22 = 15'd0; -reg vns_array_muxed23 = 1'd0; -reg vns_array_muxed24 = 1'd0; -reg vns_array_muxed25 = 1'd0; -reg vns_array_muxed26 = 1'd0; -reg vns_array_muxed27 = 1'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg vns_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg vns_regs1 = 1'd0; -wire vns_xilinxasyncresetsynchronizerimpl0; -wire vns_xilinxasyncresetsynchronizerimpl0_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl1; -wire vns_xilinxasyncresetsynchronizerimpl1_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl1_expr; -wire vns_xilinxasyncresetsynchronizerimpl2; -wire vns_xilinxasyncresetsynchronizerimpl2_rst_meta; -wire vns_xilinxasyncresetsynchronizerimpl2_expr; -wire vns_xilinxasyncresetsynchronizerimpl3; -wire vns_xilinxasyncresetsynchronizerimpl3_rst_meta; +wire sys_pll_reset; +wire sys_pll_locked; +wire s7pll0_clkin; +wire s7pll0_clkout0; +wire s7pll0_clkout_buf0; +wire s7pll0_clkout1; +wire s7pll0_clkout_buf1; +wire s7pll0_clkout2; +wire s7pll0_clkout_buf2; +wire iodelay_pll_reset; +wire iodelay_pll_locked; +wire s7pll1_clkin; +wire s7pll1_clkout; +wire s7pll1_clkout_buf; +reg [3:0] reset_counter = 4'd15; +reg ic_reset = 1'd1; +reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8; +reg a7ddrphy_half_sys8x_taps_re = 1'd0; +reg a7ddrphy_wlevel_en_storage = 1'd0; +reg a7ddrphy_wlevel_en_re = 1'd0; +wire a7ddrphy_wlevel_strobe_re; +wire a7ddrphy_wlevel_strobe_r; +wire a7ddrphy_wlevel_strobe_we; +reg a7ddrphy_wlevel_strobe_w = 1'd0; +wire a7ddrphy_cdly_rst_re; +wire a7ddrphy_cdly_rst_r; +wire a7ddrphy_cdly_rst_we; +reg a7ddrphy_cdly_rst_w = 1'd0; +wire a7ddrphy_cdly_inc_re; +wire a7ddrphy_cdly_inc_r; +wire a7ddrphy_cdly_inc_we; +reg a7ddrphy_cdly_inc_w = 1'd0; +reg [1:0] a7ddrphy_dly_sel_storage = 2'd0; +reg a7ddrphy_dly_sel_re = 1'd0; +wire a7ddrphy_rdly_dq_rst_re; +wire a7ddrphy_rdly_dq_rst_r; +wire a7ddrphy_rdly_dq_rst_we; +reg a7ddrphy_rdly_dq_rst_w = 1'd0; +wire a7ddrphy_rdly_dq_inc_re; +wire a7ddrphy_rdly_dq_inc_r; +wire a7ddrphy_rdly_dq_inc_we; +reg a7ddrphy_rdly_dq_inc_w = 1'd0; +wire a7ddrphy_rdly_dq_bitslip_rst_re; +wire a7ddrphy_rdly_dq_bitslip_rst_r; +wire a7ddrphy_rdly_dq_bitslip_rst_we; +reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +wire a7ddrphy_rdly_dq_bitslip_re; +wire a7ddrphy_rdly_dq_bitslip_r; +wire a7ddrphy_rdly_dq_bitslip_we; +reg a7ddrphy_rdly_dq_bitslip_w = 1'd0; +wire [14:0] a7ddrphy_dfi_p0_address; +wire [2:0] a7ddrphy_dfi_p0_bank; +wire a7ddrphy_dfi_p0_cas_n; +wire a7ddrphy_dfi_p0_cs_n; +wire a7ddrphy_dfi_p0_ras_n; +wire a7ddrphy_dfi_p0_we_n; +wire a7ddrphy_dfi_p0_cke; +wire a7ddrphy_dfi_p0_odt; +wire a7ddrphy_dfi_p0_reset_n; +wire a7ddrphy_dfi_p0_act_n; +wire [31:0] a7ddrphy_dfi_p0_wrdata; +wire a7ddrphy_dfi_p0_wrdata_en; +wire [3:0] a7ddrphy_dfi_p0_wrdata_mask; +wire a7ddrphy_dfi_p0_rddata_en; +reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0; +reg a7ddrphy_dfi_p0_rddata_valid = 1'd0; +wire [14:0] a7ddrphy_dfi_p1_address; +wire [2:0] a7ddrphy_dfi_p1_bank; +wire a7ddrphy_dfi_p1_cas_n; +wire a7ddrphy_dfi_p1_cs_n; +wire a7ddrphy_dfi_p1_ras_n; +wire a7ddrphy_dfi_p1_we_n; +wire a7ddrphy_dfi_p1_cke; +wire a7ddrphy_dfi_p1_odt; +wire a7ddrphy_dfi_p1_reset_n; +wire a7ddrphy_dfi_p1_act_n; +wire [31:0] a7ddrphy_dfi_p1_wrdata; +wire a7ddrphy_dfi_p1_wrdata_en; +wire [3:0] a7ddrphy_dfi_p1_wrdata_mask; +wire a7ddrphy_dfi_p1_rddata_en; +reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0; +reg a7ddrphy_dfi_p1_rddata_valid = 1'd0; +wire [14:0] a7ddrphy_dfi_p2_address; +wire [2:0] a7ddrphy_dfi_p2_bank; +wire a7ddrphy_dfi_p2_cas_n; +wire a7ddrphy_dfi_p2_cs_n; +wire a7ddrphy_dfi_p2_ras_n; +wire a7ddrphy_dfi_p2_we_n; +wire a7ddrphy_dfi_p2_cke; +wire a7ddrphy_dfi_p2_odt; +wire a7ddrphy_dfi_p2_reset_n; +wire a7ddrphy_dfi_p2_act_n; +wire [31:0] a7ddrphy_dfi_p2_wrdata; +wire a7ddrphy_dfi_p2_wrdata_en; +wire [3:0] a7ddrphy_dfi_p2_wrdata_mask; +wire a7ddrphy_dfi_p2_rddata_en; +reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0; +reg a7ddrphy_dfi_p2_rddata_valid = 1'd0; +wire [14:0] a7ddrphy_dfi_p3_address; +wire [2:0] a7ddrphy_dfi_p3_bank; +wire a7ddrphy_dfi_p3_cas_n; +wire a7ddrphy_dfi_p3_cs_n; +wire a7ddrphy_dfi_p3_ras_n; +wire a7ddrphy_dfi_p3_we_n; +wire a7ddrphy_dfi_p3_cke; +wire a7ddrphy_dfi_p3_odt; +wire a7ddrphy_dfi_p3_reset_n; +wire a7ddrphy_dfi_p3_act_n; +wire [31:0] a7ddrphy_dfi_p3_wrdata; +wire a7ddrphy_dfi_p3_wrdata_en; +wire [3:0] a7ddrphy_dfi_p3_wrdata_mask; +wire a7ddrphy_dfi_p3_rddata_en; +reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0; +reg a7ddrphy_dfi_p3_rddata_valid = 1'd0; +wire a7ddrphy_sd_clk_se_nodelay; +reg a7ddrphy_dqs_oe = 1'd0; +reg a7ddrphy_dqs_oe_delayed = 1'd0; +wire a7ddrphy_dqspattern0; +wire a7ddrphy_dqspattern1; +reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0; +wire [1:0] a7ddrphy_dqs_i; +wire [1:0] a7ddrphy_dqs_i_delayed; +wire a7ddrphy_dqs_o_no_delay0; +wire a7ddrphy_dqs_t0; +wire a7ddrphy0; +wire a7ddrphy_dqs_o_no_delay1; +wire a7ddrphy_dqs_t1; +wire a7ddrphy1; +wire a7ddrphy_dq_oe; +reg a7ddrphy_dq_oe_delayed = 1'd0; +wire a7ddrphy_dq_o_nodelay0; +wire a7ddrphy_dq_i_nodelay0; +wire a7ddrphy_dq_i_delayed0; +wire a7ddrphy_dq_t0; +wire [7:0] a7ddrphy_dq_i_data0; +wire [7:0] a7ddrphy_bitslip0_i; +reg [7:0] a7ddrphy_bitslip0_o = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value = 3'd0; +reg [15:0] a7ddrphy_bitslip0_r = 16'd0; +wire a7ddrphy_dq_o_nodelay1; +wire a7ddrphy_dq_i_nodelay1; +wire a7ddrphy_dq_i_delayed1; +wire a7ddrphy_dq_t1; +wire [7:0] a7ddrphy_dq_i_data1; +wire [7:0] a7ddrphy_bitslip1_i; +reg [7:0] a7ddrphy_bitslip1_o = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value = 3'd0; +reg [15:0] a7ddrphy_bitslip1_r = 16'd0; +wire a7ddrphy_dq_o_nodelay2; +wire a7ddrphy_dq_i_nodelay2; +wire a7ddrphy_dq_i_delayed2; +wire a7ddrphy_dq_t2; +wire [7:0] a7ddrphy_dq_i_data2; +wire [7:0] a7ddrphy_bitslip2_i; +reg [7:0] a7ddrphy_bitslip2_o = 8'd0; +reg [2:0] a7ddrphy_bitslip2_value = 3'd0; +reg [15:0] a7ddrphy_bitslip2_r = 16'd0; +wire a7ddrphy_dq_o_nodelay3; +wire a7ddrphy_dq_i_nodelay3; +wire a7ddrphy_dq_i_delayed3; +wire a7ddrphy_dq_t3; +wire [7:0] a7ddrphy_dq_i_data3; +wire [7:0] a7ddrphy_bitslip3_i; +reg [7:0] a7ddrphy_bitslip3_o = 8'd0; +reg [2:0] a7ddrphy_bitslip3_value = 3'd0; +reg [15:0] a7ddrphy_bitslip3_r = 16'd0; +wire a7ddrphy_dq_o_nodelay4; +wire a7ddrphy_dq_i_nodelay4; +wire a7ddrphy_dq_i_delayed4; +wire a7ddrphy_dq_t4; +wire [7:0] a7ddrphy_dq_i_data4; +wire [7:0] a7ddrphy_bitslip4_i; +reg [7:0] a7ddrphy_bitslip4_o = 8'd0; +reg [2:0] a7ddrphy_bitslip4_value = 3'd0; +reg [15:0] a7ddrphy_bitslip4_r = 16'd0; +wire a7ddrphy_dq_o_nodelay5; +wire a7ddrphy_dq_i_nodelay5; +wire a7ddrphy_dq_i_delayed5; +wire a7ddrphy_dq_t5; +wire [7:0] a7ddrphy_dq_i_data5; +wire [7:0] a7ddrphy_bitslip5_i; +reg [7:0] a7ddrphy_bitslip5_o = 8'd0; +reg [2:0] a7ddrphy_bitslip5_value = 3'd0; +reg [15:0] a7ddrphy_bitslip5_r = 16'd0; +wire a7ddrphy_dq_o_nodelay6; +wire a7ddrphy_dq_i_nodelay6; +wire a7ddrphy_dq_i_delayed6; +wire a7ddrphy_dq_t6; +wire [7:0] a7ddrphy_dq_i_data6; +wire [7:0] a7ddrphy_bitslip6_i; +reg [7:0] a7ddrphy_bitslip6_o = 8'd0; +reg [2:0] a7ddrphy_bitslip6_value = 3'd0; +reg [15:0] a7ddrphy_bitslip6_r = 16'd0; +wire a7ddrphy_dq_o_nodelay7; +wire a7ddrphy_dq_i_nodelay7; +wire a7ddrphy_dq_i_delayed7; +wire a7ddrphy_dq_t7; +wire [7:0] a7ddrphy_dq_i_data7; +wire [7:0] a7ddrphy_bitslip7_i; +reg [7:0] a7ddrphy_bitslip7_o = 8'd0; +reg [2:0] a7ddrphy_bitslip7_value = 3'd0; +reg [15:0] a7ddrphy_bitslip7_r = 16'd0; +wire a7ddrphy_dq_o_nodelay8; +wire a7ddrphy_dq_i_nodelay8; +wire a7ddrphy_dq_i_delayed8; +wire a7ddrphy_dq_t8; +wire [7:0] a7ddrphy_dq_i_data8; +wire [7:0] a7ddrphy_bitslip8_i; +reg [7:0] a7ddrphy_bitslip8_o = 8'd0; +reg [2:0] a7ddrphy_bitslip8_value = 3'd0; +reg [15:0] a7ddrphy_bitslip8_r = 16'd0; +wire a7ddrphy_dq_o_nodelay9; +wire a7ddrphy_dq_i_nodelay9; +wire a7ddrphy_dq_i_delayed9; +wire a7ddrphy_dq_t9; +wire [7:0] a7ddrphy_dq_i_data9; +wire [7:0] a7ddrphy_bitslip9_i; +reg [7:0] a7ddrphy_bitslip9_o = 8'd0; +reg [2:0] a7ddrphy_bitslip9_value = 3'd0; +reg [15:0] a7ddrphy_bitslip9_r = 16'd0; +wire a7ddrphy_dq_o_nodelay10; +wire a7ddrphy_dq_i_nodelay10; +wire a7ddrphy_dq_i_delayed10; +wire a7ddrphy_dq_t10; +wire [7:0] a7ddrphy_dq_i_data10; +wire [7:0] a7ddrphy_bitslip10_i; +reg [7:0] a7ddrphy_bitslip10_o = 8'd0; +reg [2:0] a7ddrphy_bitslip10_value = 3'd0; +reg [15:0] a7ddrphy_bitslip10_r = 16'd0; +wire a7ddrphy_dq_o_nodelay11; +wire a7ddrphy_dq_i_nodelay11; +wire a7ddrphy_dq_i_delayed11; +wire a7ddrphy_dq_t11; +wire [7:0] a7ddrphy_dq_i_data11; +wire [7:0] a7ddrphy_bitslip11_i; +reg [7:0] a7ddrphy_bitslip11_o = 8'd0; +reg [2:0] a7ddrphy_bitslip11_value = 3'd0; +reg [15:0] a7ddrphy_bitslip11_r = 16'd0; +wire a7ddrphy_dq_o_nodelay12; +wire a7ddrphy_dq_i_nodelay12; +wire a7ddrphy_dq_i_delayed12; +wire a7ddrphy_dq_t12; +wire [7:0] a7ddrphy_dq_i_data12; +wire [7:0] a7ddrphy_bitslip12_i; +reg [7:0] a7ddrphy_bitslip12_o = 8'd0; +reg [2:0] a7ddrphy_bitslip12_value = 3'd0; +reg [15:0] a7ddrphy_bitslip12_r = 16'd0; +wire a7ddrphy_dq_o_nodelay13; +wire a7ddrphy_dq_i_nodelay13; +wire a7ddrphy_dq_i_delayed13; +wire a7ddrphy_dq_t13; +wire [7:0] a7ddrphy_dq_i_data13; +wire [7:0] a7ddrphy_bitslip13_i; +reg [7:0] a7ddrphy_bitslip13_o = 8'd0; +reg [2:0] a7ddrphy_bitslip13_value = 3'd0; +reg [15:0] a7ddrphy_bitslip13_r = 16'd0; +wire a7ddrphy_dq_o_nodelay14; +wire a7ddrphy_dq_i_nodelay14; +wire a7ddrphy_dq_i_delayed14; +wire a7ddrphy_dq_t14; +wire [7:0] a7ddrphy_dq_i_data14; +wire [7:0] a7ddrphy_bitslip14_i; +reg [7:0] a7ddrphy_bitslip14_o = 8'd0; +reg [2:0] a7ddrphy_bitslip14_value = 3'd0; +reg [15:0] a7ddrphy_bitslip14_r = 16'd0; +wire a7ddrphy_dq_o_nodelay15; +wire a7ddrphy_dq_i_nodelay15; +wire a7ddrphy_dq_i_delayed15; +wire a7ddrphy_dq_t15; +wire [7:0] a7ddrphy_dq_i_data15; +wire [7:0] a7ddrphy_bitslip15_i; +reg [7:0] a7ddrphy_bitslip15_o = 8'd0; +reg [2:0] a7ddrphy_bitslip15_value = 3'd0; +reg [15:0] a7ddrphy_bitslip15_r = 16'd0; +wire [7:0] a7ddrphy_rddata_en; +reg [7:0] a7ddrphy_rddata_en_last = 8'd0; +wire [3:0] a7ddrphy_wrdata_en; +reg [3:0] a7ddrphy_wrdata_en_last = 4'd0; +wire [14:0] litedramcore_inti_p0_address; +wire [2:0] litedramcore_inti_p0_bank; +reg litedramcore_inti_p0_cas_n = 1'd1; +reg litedramcore_inti_p0_cs_n = 1'd1; +reg litedramcore_inti_p0_ras_n = 1'd1; +reg litedramcore_inti_p0_we_n = 1'd1; +wire litedramcore_inti_p0_cke; +wire litedramcore_inti_p0_odt; +wire litedramcore_inti_p0_reset_n; +reg litedramcore_inti_p0_act_n = 1'd1; +wire [31:0] litedramcore_inti_p0_wrdata; +wire litedramcore_inti_p0_wrdata_en; +wire [3:0] litedramcore_inti_p0_wrdata_mask; +wire litedramcore_inti_p0_rddata_en; +reg [31:0] litedramcore_inti_p0_rddata = 32'd0; +reg litedramcore_inti_p0_rddata_valid = 1'd0; +wire [14:0] litedramcore_inti_p1_address; +wire [2:0] litedramcore_inti_p1_bank; +reg litedramcore_inti_p1_cas_n = 1'd1; +reg litedramcore_inti_p1_cs_n = 1'd1; +reg litedramcore_inti_p1_ras_n = 1'd1; +reg litedramcore_inti_p1_we_n = 1'd1; +wire litedramcore_inti_p1_cke; +wire litedramcore_inti_p1_odt; +wire litedramcore_inti_p1_reset_n; +reg litedramcore_inti_p1_act_n = 1'd1; +wire [31:0] litedramcore_inti_p1_wrdata; +wire litedramcore_inti_p1_wrdata_en; +wire [3:0] litedramcore_inti_p1_wrdata_mask; +wire litedramcore_inti_p1_rddata_en; +reg [31:0] litedramcore_inti_p1_rddata = 32'd0; +reg litedramcore_inti_p1_rddata_valid = 1'd0; +wire [14:0] litedramcore_inti_p2_address; +wire [2:0] litedramcore_inti_p2_bank; +reg litedramcore_inti_p2_cas_n = 1'd1; +reg litedramcore_inti_p2_cs_n = 1'd1; +reg litedramcore_inti_p2_ras_n = 1'd1; +reg litedramcore_inti_p2_we_n = 1'd1; +wire litedramcore_inti_p2_cke; +wire litedramcore_inti_p2_odt; +wire litedramcore_inti_p2_reset_n; +reg litedramcore_inti_p2_act_n = 1'd1; +wire [31:0] litedramcore_inti_p2_wrdata; +wire litedramcore_inti_p2_wrdata_en; +wire [3:0] litedramcore_inti_p2_wrdata_mask; +wire litedramcore_inti_p2_rddata_en; +reg [31:0] litedramcore_inti_p2_rddata = 32'd0; +reg litedramcore_inti_p2_rddata_valid = 1'd0; +wire [14:0] litedramcore_inti_p3_address; +wire [2:0] litedramcore_inti_p3_bank; +reg litedramcore_inti_p3_cas_n = 1'd1; +reg litedramcore_inti_p3_cs_n = 1'd1; +reg litedramcore_inti_p3_ras_n = 1'd1; +reg litedramcore_inti_p3_we_n = 1'd1; +wire litedramcore_inti_p3_cke; +wire litedramcore_inti_p3_odt; +wire litedramcore_inti_p3_reset_n; +reg litedramcore_inti_p3_act_n = 1'd1; +wire [31:0] litedramcore_inti_p3_wrdata; +wire litedramcore_inti_p3_wrdata_en; +wire [3:0] litedramcore_inti_p3_wrdata_mask; +wire litedramcore_inti_p3_rddata_en; +reg [31:0] litedramcore_inti_p3_rddata = 32'd0; +reg litedramcore_inti_p3_rddata_valid = 1'd0; +wire [14:0] litedramcore_slave_p0_address; +wire [2:0] litedramcore_slave_p0_bank; +wire litedramcore_slave_p0_cas_n; +wire litedramcore_slave_p0_cs_n; +wire litedramcore_slave_p0_ras_n; +wire litedramcore_slave_p0_we_n; +wire litedramcore_slave_p0_cke; +wire litedramcore_slave_p0_odt; +wire litedramcore_slave_p0_reset_n; +wire litedramcore_slave_p0_act_n; +wire [31:0] litedramcore_slave_p0_wrdata; +wire litedramcore_slave_p0_wrdata_en; +wire [3:0] litedramcore_slave_p0_wrdata_mask; +wire litedramcore_slave_p0_rddata_en; +reg [31:0] litedramcore_slave_p0_rddata = 32'd0; +reg litedramcore_slave_p0_rddata_valid = 1'd0; +wire [14:0] litedramcore_slave_p1_address; +wire [2:0] litedramcore_slave_p1_bank; +wire litedramcore_slave_p1_cas_n; +wire litedramcore_slave_p1_cs_n; +wire litedramcore_slave_p1_ras_n; +wire litedramcore_slave_p1_we_n; +wire litedramcore_slave_p1_cke; +wire litedramcore_slave_p1_odt; +wire litedramcore_slave_p1_reset_n; +wire litedramcore_slave_p1_act_n; +wire [31:0] litedramcore_slave_p1_wrdata; +wire litedramcore_slave_p1_wrdata_en; +wire [3:0] litedramcore_slave_p1_wrdata_mask; +wire litedramcore_slave_p1_rddata_en; +reg [31:0] litedramcore_slave_p1_rddata = 32'd0; +reg litedramcore_slave_p1_rddata_valid = 1'd0; +wire [14:0] litedramcore_slave_p2_address; +wire [2:0] litedramcore_slave_p2_bank; +wire litedramcore_slave_p2_cas_n; +wire litedramcore_slave_p2_cs_n; +wire litedramcore_slave_p2_ras_n; +wire litedramcore_slave_p2_we_n; +wire litedramcore_slave_p2_cke; +wire litedramcore_slave_p2_odt; +wire litedramcore_slave_p2_reset_n; +wire litedramcore_slave_p2_act_n; +wire [31:0] litedramcore_slave_p2_wrdata; +wire litedramcore_slave_p2_wrdata_en; +wire [3:0] litedramcore_slave_p2_wrdata_mask; +wire litedramcore_slave_p2_rddata_en; +reg [31:0] litedramcore_slave_p2_rddata = 32'd0; +reg litedramcore_slave_p2_rddata_valid = 1'd0; +wire [14:0] litedramcore_slave_p3_address; +wire [2:0] litedramcore_slave_p3_bank; +wire litedramcore_slave_p3_cas_n; +wire litedramcore_slave_p3_cs_n; +wire litedramcore_slave_p3_ras_n; +wire litedramcore_slave_p3_we_n; +wire litedramcore_slave_p3_cke; +wire litedramcore_slave_p3_odt; +wire litedramcore_slave_p3_reset_n; +wire litedramcore_slave_p3_act_n; +wire [31:0] litedramcore_slave_p3_wrdata; +wire litedramcore_slave_p3_wrdata_en; +wire [3:0] litedramcore_slave_p3_wrdata_mask; +wire litedramcore_slave_p3_rddata_en; +reg [31:0] litedramcore_slave_p3_rddata = 32'd0; +reg litedramcore_slave_p3_rddata_valid = 1'd0; +reg [14:0] litedramcore_master_p0_address = 15'd0; +reg [2:0] litedramcore_master_p0_bank = 3'd0; +reg litedramcore_master_p0_cas_n = 1'd1; +reg litedramcore_master_p0_cs_n = 1'd1; +reg litedramcore_master_p0_ras_n = 1'd1; +reg litedramcore_master_p0_we_n = 1'd1; +reg litedramcore_master_p0_cke = 1'd0; +reg litedramcore_master_p0_odt = 1'd0; +reg litedramcore_master_p0_reset_n = 1'd0; +reg litedramcore_master_p0_act_n = 1'd1; +reg [31:0] litedramcore_master_p0_wrdata = 32'd0; +reg litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0; +reg litedramcore_master_p0_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p0_rddata; +wire litedramcore_master_p0_rddata_valid; +reg [14:0] litedramcore_master_p1_address = 15'd0; +reg [2:0] litedramcore_master_p1_bank = 3'd0; +reg litedramcore_master_p1_cas_n = 1'd1; +reg litedramcore_master_p1_cs_n = 1'd1; +reg litedramcore_master_p1_ras_n = 1'd1; +reg litedramcore_master_p1_we_n = 1'd1; +reg litedramcore_master_p1_cke = 1'd0; +reg litedramcore_master_p1_odt = 1'd0; +reg litedramcore_master_p1_reset_n = 1'd0; +reg litedramcore_master_p1_act_n = 1'd1; +reg [31:0] litedramcore_master_p1_wrdata = 32'd0; +reg litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0; +reg litedramcore_master_p1_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p1_rddata; +wire litedramcore_master_p1_rddata_valid; +reg [14:0] litedramcore_master_p2_address = 15'd0; +reg [2:0] litedramcore_master_p2_bank = 3'd0; +reg litedramcore_master_p2_cas_n = 1'd1; +reg litedramcore_master_p2_cs_n = 1'd1; +reg litedramcore_master_p2_ras_n = 1'd1; +reg litedramcore_master_p2_we_n = 1'd1; +reg litedramcore_master_p2_cke = 1'd0; +reg litedramcore_master_p2_odt = 1'd0; +reg litedramcore_master_p2_reset_n = 1'd0; +reg litedramcore_master_p2_act_n = 1'd1; +reg [31:0] litedramcore_master_p2_wrdata = 32'd0; +reg litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0; +reg litedramcore_master_p2_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p2_rddata; +wire litedramcore_master_p2_rddata_valid; +reg [14:0] litedramcore_master_p3_address = 15'd0; +reg [2:0] litedramcore_master_p3_bank = 3'd0; +reg litedramcore_master_p3_cas_n = 1'd1; +reg litedramcore_master_p3_cs_n = 1'd1; +reg litedramcore_master_p3_ras_n = 1'd1; +reg litedramcore_master_p3_we_n = 1'd1; +reg litedramcore_master_p3_cke = 1'd0; +reg litedramcore_master_p3_odt = 1'd0; +reg litedramcore_master_p3_reset_n = 1'd0; +reg litedramcore_master_p3_act_n = 1'd1; +reg [31:0] litedramcore_master_p3_wrdata = 32'd0; +reg litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0; +reg litedramcore_master_p3_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p3_rddata; +wire litedramcore_master_p3_rddata_valid; +reg [3:0] litedramcore_storage = 4'd0; +reg litedramcore_re = 1'd0; +reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; +reg litedramcore_phaseinjector0_command_re = 1'd0; +wire litedramcore_phaseinjector0_command_issue_re; +wire litedramcore_phaseinjector0_command_issue_r; +wire litedramcore_phaseinjector0_command_issue_we; +reg litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0; +reg litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector0_status = 32'd0; +wire litedramcore_phaseinjector0_we; +reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; +reg litedramcore_phaseinjector1_command_re = 1'd0; +wire litedramcore_phaseinjector1_command_issue_re; +wire litedramcore_phaseinjector1_command_issue_r; +wire litedramcore_phaseinjector1_command_issue_we; +reg litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0; +reg litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector1_status = 32'd0; +wire litedramcore_phaseinjector1_we; +reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0; +reg litedramcore_phaseinjector2_command_re = 1'd0; +wire litedramcore_phaseinjector2_command_issue_re; +wire litedramcore_phaseinjector2_command_issue_r; +wire litedramcore_phaseinjector2_command_issue_we; +reg litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [14:0] litedramcore_phaseinjector2_address_storage = 15'd0; +reg litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector2_status = 32'd0; +wire litedramcore_phaseinjector2_we; +reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0; +reg litedramcore_phaseinjector3_command_re = 1'd0; +wire litedramcore_phaseinjector3_command_issue_re; +wire litedramcore_phaseinjector3_command_issue_r; +wire litedramcore_phaseinjector3_command_issue_we; +reg litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [14:0] litedramcore_phaseinjector3_address_storage = 15'd0; +reg litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector3_status = 32'd0; +wire litedramcore_phaseinjector3_we; +wire litedramcore_interface_bank0_valid; +wire litedramcore_interface_bank0_ready; +wire litedramcore_interface_bank0_we; +wire [21:0] litedramcore_interface_bank0_addr; +wire litedramcore_interface_bank0_lock; +wire litedramcore_interface_bank0_wdata_ready; +wire litedramcore_interface_bank0_rdata_valid; +wire litedramcore_interface_bank1_valid; +wire litedramcore_interface_bank1_ready; +wire litedramcore_interface_bank1_we; +wire [21:0] litedramcore_interface_bank1_addr; +wire litedramcore_interface_bank1_lock; +wire litedramcore_interface_bank1_wdata_ready; +wire litedramcore_interface_bank1_rdata_valid; +wire litedramcore_interface_bank2_valid; +wire litedramcore_interface_bank2_ready; +wire litedramcore_interface_bank2_we; +wire [21:0] litedramcore_interface_bank2_addr; +wire litedramcore_interface_bank2_lock; +wire litedramcore_interface_bank2_wdata_ready; +wire litedramcore_interface_bank2_rdata_valid; +wire litedramcore_interface_bank3_valid; +wire litedramcore_interface_bank3_ready; +wire litedramcore_interface_bank3_we; +wire [21:0] litedramcore_interface_bank3_addr; +wire litedramcore_interface_bank3_lock; +wire litedramcore_interface_bank3_wdata_ready; +wire litedramcore_interface_bank3_rdata_valid; +wire litedramcore_interface_bank4_valid; +wire litedramcore_interface_bank4_ready; +wire litedramcore_interface_bank4_we; +wire [21:0] litedramcore_interface_bank4_addr; +wire litedramcore_interface_bank4_lock; +wire litedramcore_interface_bank4_wdata_ready; +wire litedramcore_interface_bank4_rdata_valid; +wire litedramcore_interface_bank5_valid; +wire litedramcore_interface_bank5_ready; +wire litedramcore_interface_bank5_we; +wire [21:0] litedramcore_interface_bank5_addr; +wire litedramcore_interface_bank5_lock; +wire litedramcore_interface_bank5_wdata_ready; +wire litedramcore_interface_bank5_rdata_valid; +wire litedramcore_interface_bank6_valid; +wire litedramcore_interface_bank6_ready; +wire litedramcore_interface_bank6_we; +wire [21:0] litedramcore_interface_bank6_addr; +wire litedramcore_interface_bank6_lock; +wire litedramcore_interface_bank6_wdata_ready; +wire litedramcore_interface_bank6_rdata_valid; +wire litedramcore_interface_bank7_valid; +wire litedramcore_interface_bank7_ready; +wire litedramcore_interface_bank7_we; +wire [21:0] litedramcore_interface_bank7_addr; +wire litedramcore_interface_bank7_lock; +wire litedramcore_interface_bank7_wdata_ready; +wire litedramcore_interface_bank7_rdata_valid; +reg [127:0] litedramcore_interface_wdata = 128'd0; +reg [15:0] litedramcore_interface_wdata_we = 16'd0; +wire [127:0] litedramcore_interface_rdata; +reg [14:0] litedramcore_dfi_p0_address = 15'd0; +reg [2:0] litedramcore_dfi_p0_bank = 3'd0; +reg litedramcore_dfi_p0_cas_n = 1'd1; +reg litedramcore_dfi_p0_cs_n = 1'd1; +reg litedramcore_dfi_p0_ras_n = 1'd1; +reg litedramcore_dfi_p0_we_n = 1'd1; +wire litedramcore_dfi_p0_cke; +wire litedramcore_dfi_p0_odt; +wire litedramcore_dfi_p0_reset_n; +reg litedramcore_dfi_p0_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p0_wrdata; +reg litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p0_wrdata_mask; +reg litedramcore_dfi_p0_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p0_rddata; +wire litedramcore_dfi_p0_rddata_valid; +reg [14:0] litedramcore_dfi_p1_address = 15'd0; +reg [2:0] litedramcore_dfi_p1_bank = 3'd0; +reg litedramcore_dfi_p1_cas_n = 1'd1; +reg litedramcore_dfi_p1_cs_n = 1'd1; +reg litedramcore_dfi_p1_ras_n = 1'd1; +reg litedramcore_dfi_p1_we_n = 1'd1; +wire litedramcore_dfi_p1_cke; +wire litedramcore_dfi_p1_odt; +wire litedramcore_dfi_p1_reset_n; +reg litedramcore_dfi_p1_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p1_wrdata; +reg litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p1_wrdata_mask; +reg litedramcore_dfi_p1_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p1_rddata; +wire litedramcore_dfi_p1_rddata_valid; +reg [14:0] litedramcore_dfi_p2_address = 15'd0; +reg [2:0] litedramcore_dfi_p2_bank = 3'd0; +reg litedramcore_dfi_p2_cas_n = 1'd1; +reg litedramcore_dfi_p2_cs_n = 1'd1; +reg litedramcore_dfi_p2_ras_n = 1'd1; +reg litedramcore_dfi_p2_we_n = 1'd1; +wire litedramcore_dfi_p2_cke; +wire litedramcore_dfi_p2_odt; +wire litedramcore_dfi_p2_reset_n; +reg litedramcore_dfi_p2_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p2_wrdata; +reg litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p2_wrdata_mask; +reg litedramcore_dfi_p2_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p2_rddata; +wire litedramcore_dfi_p2_rddata_valid; +reg [14:0] litedramcore_dfi_p3_address = 15'd0; +reg [2:0] litedramcore_dfi_p3_bank = 3'd0; +reg litedramcore_dfi_p3_cas_n = 1'd1; +reg litedramcore_dfi_p3_cs_n = 1'd1; +reg litedramcore_dfi_p3_ras_n = 1'd1; +reg litedramcore_dfi_p3_we_n = 1'd1; +wire litedramcore_dfi_p3_cke; +wire litedramcore_dfi_p3_odt; +wire litedramcore_dfi_p3_reset_n; +reg litedramcore_dfi_p3_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p3_wrdata; +reg litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p3_wrdata_mask; +reg litedramcore_dfi_p3_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p3_rddata; +wire litedramcore_dfi_p3_rddata_valid; +reg litedramcore_cmd_valid = 1'd0; +reg litedramcore_cmd_ready = 1'd0; +reg litedramcore_cmd_last = 1'd0; +reg [14:0] litedramcore_cmd_payload_a = 15'd0; +reg [2:0] litedramcore_cmd_payload_ba = 3'd0; +reg litedramcore_cmd_payload_cas = 1'd0; +reg litedramcore_cmd_payload_ras = 1'd0; +reg litedramcore_cmd_payload_we = 1'd0; +reg litedramcore_cmd_payload_is_read = 1'd0; +reg litedramcore_cmd_payload_is_write = 1'd0; +wire litedramcore_wants_refresh; +wire litedramcore_wants_zqcs; +wire litedramcore_timer_wait; +wire litedramcore_timer_done0; +wire [9:0] litedramcore_timer_count0; +wire litedramcore_timer_done1; +reg [9:0] litedramcore_timer_count1 = 10'd781; +wire litedramcore_postponer_req_i; +reg litedramcore_postponer_req_o = 1'd0; +reg litedramcore_postponer_count = 1'd0; +reg litedramcore_sequencer_start0 = 1'd0; +wire litedramcore_sequencer_done0; +wire litedramcore_sequencer_start1; +reg litedramcore_sequencer_done1 = 1'd0; +reg [5:0] litedramcore_sequencer_counter = 6'd0; +reg litedramcore_sequencer_count = 1'd0; +wire litedramcore_zqcs_timer_wait; +wire litedramcore_zqcs_timer_done0; +wire [26:0] litedramcore_zqcs_timer_count0; +wire litedramcore_zqcs_timer_done1; +reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999; +reg litedramcore_zqcs_executer_start = 1'd0; +reg litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] litedramcore_zqcs_executer_counter = 5'd0; +wire litedramcore_bankmachine0_req_valid; +wire litedramcore_bankmachine0_req_ready; +wire litedramcore_bankmachine0_req_we; +wire [21:0] litedramcore_bankmachine0_req_addr; +wire litedramcore_bankmachine0_req_lock; +reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine0_refresh_req; +reg litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg litedramcore_bankmachine0_cmd_valid = 1'd0; +reg litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; +reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine0_auto_precharge = 1'd0; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; +wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; +wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine0_cmd_buffer_sink_valid; +wire litedramcore_bankmachine0_cmd_buffer_sink_ready; +wire litedramcore_bankmachine0_cmd_buffer_sink_first; +wire litedramcore_bankmachine0_cmd_buffer_sink_last; +wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we; +wire [21:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine0_cmd_buffer_source_ready; +reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine0_row = 15'd0; +reg litedramcore_bankmachine0_row_opened = 1'd0; +wire litedramcore_bankmachine0_row_hit; +reg litedramcore_bankmachine0_row_open = 1'd0; +reg litedramcore_bankmachine0_row_close = 1'd0; +reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine0_twtpcon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; +wire litedramcore_bankmachine0_trccon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0; +wire litedramcore_bankmachine0_trascon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0; +wire litedramcore_bankmachine1_req_valid; +wire litedramcore_bankmachine1_req_ready; +wire litedramcore_bankmachine1_req_we; +wire [21:0] litedramcore_bankmachine1_req_addr; +wire litedramcore_bankmachine1_req_lock; +reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine1_refresh_req; +reg litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg litedramcore_bankmachine1_cmd_valid = 1'd0; +reg litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; +reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine1_auto_precharge = 1'd0; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; +wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; +wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine1_cmd_buffer_sink_valid; +wire litedramcore_bankmachine1_cmd_buffer_sink_ready; +wire litedramcore_bankmachine1_cmd_buffer_sink_first; +wire litedramcore_bankmachine1_cmd_buffer_sink_last; +wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we; +wire [21:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine1_cmd_buffer_source_ready; +reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine1_row = 15'd0; +reg litedramcore_bankmachine1_row_opened = 1'd0; +wire litedramcore_bankmachine1_row_hit; +reg litedramcore_bankmachine1_row_open = 1'd0; +reg litedramcore_bankmachine1_row_close = 1'd0; +reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine1_twtpcon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; +wire litedramcore_bankmachine1_trccon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0; +wire litedramcore_bankmachine1_trascon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0; +wire litedramcore_bankmachine2_req_valid; +wire litedramcore_bankmachine2_req_ready; +wire litedramcore_bankmachine2_req_we; +wire [21:0] litedramcore_bankmachine2_req_addr; +wire litedramcore_bankmachine2_req_lock; +reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine2_refresh_req; +reg litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg litedramcore_bankmachine2_cmd_valid = 1'd0; +reg litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; +reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine2_auto_precharge = 1'd0; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; +wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; +wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine2_cmd_buffer_sink_valid; +wire litedramcore_bankmachine2_cmd_buffer_sink_ready; +wire litedramcore_bankmachine2_cmd_buffer_sink_first; +wire litedramcore_bankmachine2_cmd_buffer_sink_last; +wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we; +wire [21:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine2_cmd_buffer_source_ready; +reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine2_row = 15'd0; +reg litedramcore_bankmachine2_row_opened = 1'd0; +wire litedramcore_bankmachine2_row_hit; +reg litedramcore_bankmachine2_row_open = 1'd0; +reg litedramcore_bankmachine2_row_close = 1'd0; +reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine2_twtpcon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; +wire litedramcore_bankmachine2_trccon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0; +wire litedramcore_bankmachine2_trascon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0; +wire litedramcore_bankmachine3_req_valid; +wire litedramcore_bankmachine3_req_ready; +wire litedramcore_bankmachine3_req_we; +wire [21:0] litedramcore_bankmachine3_req_addr; +wire litedramcore_bankmachine3_req_lock; +reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine3_refresh_req; +reg litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg litedramcore_bankmachine3_cmd_valid = 1'd0; +reg litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; +reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine3_auto_precharge = 1'd0; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; +wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; +wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine3_cmd_buffer_sink_valid; +wire litedramcore_bankmachine3_cmd_buffer_sink_ready; +wire litedramcore_bankmachine3_cmd_buffer_sink_first; +wire litedramcore_bankmachine3_cmd_buffer_sink_last; +wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we; +wire [21:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine3_cmd_buffer_source_ready; +reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine3_row = 15'd0; +reg litedramcore_bankmachine3_row_opened = 1'd0; +wire litedramcore_bankmachine3_row_hit; +reg litedramcore_bankmachine3_row_open = 1'd0; +reg litedramcore_bankmachine3_row_close = 1'd0; +reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine3_twtpcon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; +wire litedramcore_bankmachine3_trccon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0; +wire litedramcore_bankmachine3_trascon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0; +wire litedramcore_bankmachine4_req_valid; +wire litedramcore_bankmachine4_req_ready; +wire litedramcore_bankmachine4_req_we; +wire [21:0] litedramcore_bankmachine4_req_addr; +wire litedramcore_bankmachine4_req_lock; +reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine4_refresh_req; +reg litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg litedramcore_bankmachine4_cmd_valid = 1'd0; +reg litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; +reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine4_auto_precharge = 1'd0; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; +wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; +wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine4_cmd_buffer_sink_valid; +wire litedramcore_bankmachine4_cmd_buffer_sink_ready; +wire litedramcore_bankmachine4_cmd_buffer_sink_first; +wire litedramcore_bankmachine4_cmd_buffer_sink_last; +wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we; +wire [21:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine4_cmd_buffer_source_ready; +reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine4_row = 15'd0; +reg litedramcore_bankmachine4_row_opened = 1'd0; +wire litedramcore_bankmachine4_row_hit; +reg litedramcore_bankmachine4_row_open = 1'd0; +reg litedramcore_bankmachine4_row_close = 1'd0; +reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine4_twtpcon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; +wire litedramcore_bankmachine4_trccon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0; +wire litedramcore_bankmachine4_trascon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0; +wire litedramcore_bankmachine5_req_valid; +wire litedramcore_bankmachine5_req_ready; +wire litedramcore_bankmachine5_req_we; +wire [21:0] litedramcore_bankmachine5_req_addr; +wire litedramcore_bankmachine5_req_lock; +reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine5_refresh_req; +reg litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg litedramcore_bankmachine5_cmd_valid = 1'd0; +reg litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; +reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine5_auto_precharge = 1'd0; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; +wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; +wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine5_cmd_buffer_sink_valid; +wire litedramcore_bankmachine5_cmd_buffer_sink_ready; +wire litedramcore_bankmachine5_cmd_buffer_sink_first; +wire litedramcore_bankmachine5_cmd_buffer_sink_last; +wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we; +wire [21:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine5_cmd_buffer_source_ready; +reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine5_row = 15'd0; +reg litedramcore_bankmachine5_row_opened = 1'd0; +wire litedramcore_bankmachine5_row_hit; +reg litedramcore_bankmachine5_row_open = 1'd0; +reg litedramcore_bankmachine5_row_close = 1'd0; +reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine5_twtpcon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; +wire litedramcore_bankmachine5_trccon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0; +wire litedramcore_bankmachine5_trascon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0; +wire litedramcore_bankmachine6_req_valid; +wire litedramcore_bankmachine6_req_ready; +wire litedramcore_bankmachine6_req_we; +wire [21:0] litedramcore_bankmachine6_req_addr; +wire litedramcore_bankmachine6_req_lock; +reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine6_refresh_req; +reg litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg litedramcore_bankmachine6_cmd_valid = 1'd0; +reg litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; +reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine6_auto_precharge = 1'd0; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; +wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; +wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine6_cmd_buffer_sink_valid; +wire litedramcore_bankmachine6_cmd_buffer_sink_ready; +wire litedramcore_bankmachine6_cmd_buffer_sink_first; +wire litedramcore_bankmachine6_cmd_buffer_sink_last; +wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we; +wire [21:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine6_cmd_buffer_source_ready; +reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine6_row = 15'd0; +reg litedramcore_bankmachine6_row_opened = 1'd0; +wire litedramcore_bankmachine6_row_hit; +reg litedramcore_bankmachine6_row_open = 1'd0; +reg litedramcore_bankmachine6_row_close = 1'd0; +reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine6_twtpcon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; +wire litedramcore_bankmachine6_trccon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0; +wire litedramcore_bankmachine6_trascon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0; +wire litedramcore_bankmachine7_req_valid; +wire litedramcore_bankmachine7_req_ready; +wire litedramcore_bankmachine7_req_we; +wire [21:0] litedramcore_bankmachine7_req_addr; +wire litedramcore_bankmachine7_req_lock; +reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine7_refresh_req; +reg litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg litedramcore_bankmachine7_cmd_valid = 1'd0; +reg litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; +reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine7_auto_precharge = 1'd0; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; +wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; +wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine7_cmd_buffer_sink_valid; +wire litedramcore_bankmachine7_cmd_buffer_sink_ready; +wire litedramcore_bankmachine7_cmd_buffer_sink_first; +wire litedramcore_bankmachine7_cmd_buffer_sink_last; +wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we; +wire [21:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine7_cmd_buffer_source_ready; +reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine7_row = 15'd0; +reg litedramcore_bankmachine7_row_opened = 1'd0; +wire litedramcore_bankmachine7_row_hit; +reg litedramcore_bankmachine7_row_open = 1'd0; +reg litedramcore_bankmachine7_row_close = 1'd0; +reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine7_twtpcon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; +wire litedramcore_bankmachine7_trccon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0; +wire litedramcore_bankmachine7_trascon_valid; +(* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd1; +reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0; +wire litedramcore_ras_allowed; +wire litedramcore_cas_allowed; +reg litedramcore_choose_cmd_want_reads = 1'd0; +reg litedramcore_choose_cmd_want_writes = 1'd0; +reg litedramcore_choose_cmd_want_cmds = 1'd0; +reg litedramcore_choose_cmd_want_activates = 1'd0; +wire litedramcore_choose_cmd_cmd_valid; +reg litedramcore_choose_cmd_cmd_ready = 1'd0; +wire [14:0] litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; +reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; +wire litedramcore_choose_cmd_cmd_payload_is_cmd; +wire litedramcore_choose_cmd_cmd_payload_is_read; +wire litedramcore_choose_cmd_cmd_payload_is_write; +reg [7:0] litedramcore_choose_cmd_valids = 8'd0; +wire [7:0] litedramcore_choose_cmd_request; +reg [2:0] litedramcore_choose_cmd_grant = 3'd0; +wire litedramcore_choose_cmd_ce; +reg litedramcore_choose_req_want_reads = 1'd0; +reg litedramcore_choose_req_want_writes = 1'd0; +reg litedramcore_choose_req_want_cmds = 1'd0; +reg litedramcore_choose_req_want_activates = 1'd0; +wire litedramcore_choose_req_cmd_valid; +reg litedramcore_choose_req_cmd_ready = 1'd0; +wire [14:0] litedramcore_choose_req_cmd_payload_a; +wire [2:0] litedramcore_choose_req_cmd_payload_ba; +reg litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg litedramcore_choose_req_cmd_payload_we = 1'd0; +wire litedramcore_choose_req_cmd_payload_is_cmd; +wire litedramcore_choose_req_cmd_payload_is_read; +wire litedramcore_choose_req_cmd_payload_is_write; +reg [7:0] litedramcore_choose_req_valids = 8'd0; +wire [7:0] litedramcore_choose_req_request; +reg [2:0] litedramcore_choose_req_grant = 3'd0; +wire litedramcore_choose_req_ce; +reg [14:0] litedramcore_nop_a = 15'd0; +reg [2:0] litedramcore_nop_ba = 3'd0; +reg [1:0] litedramcore_steerer_sel0 = 2'd0; +reg [1:0] litedramcore_steerer_sel1 = 2'd0; +reg [1:0] litedramcore_steerer_sel2 = 2'd0; +reg [1:0] litedramcore_steerer_sel3 = 2'd0; +reg litedramcore_steerer0 = 1'd1; +reg litedramcore_steerer1 = 1'd1; +reg litedramcore_steerer2 = 1'd1; +reg litedramcore_steerer3 = 1'd1; +reg litedramcore_steerer4 = 1'd1; +reg litedramcore_steerer5 = 1'd1; +reg litedramcore_steerer6 = 1'd1; +reg litedramcore_steerer7 = 1'd1; +wire litedramcore_trrdcon_valid; +(* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd1; +reg litedramcore_trrdcon_count = 1'd0; +wire litedramcore_tfawcon_valid; +(* dont_touch = "true" *) reg litedramcore_tfawcon_ready = 1'd1; +wire [2:0] litedramcore_tfawcon_count; +reg [4:0] litedramcore_tfawcon_window = 5'd0; +wire litedramcore_tccdcon_valid; +(* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd1; +reg litedramcore_tccdcon_count = 1'd0; +wire litedramcore_twtrcon_valid; +(* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd1; +reg [2:0] litedramcore_twtrcon_count = 3'd0; +wire litedramcore_read_available; +wire litedramcore_write_available; +reg litedramcore_en0 = 1'd0; +wire litedramcore_max_time0; +reg [4:0] litedramcore_time0 = 5'd0; +reg litedramcore_en1 = 1'd0; +wire litedramcore_max_time1; +reg [3:0] litedramcore_time1 = 4'd0; +wire litedramcore_go_to_refresh; +reg init_done_storage = 1'd0; +reg init_done_re = 1'd0; +reg init_error_storage = 1'd0; +reg init_error_re = 1'd0; +wire [13:0] csr_port_adr; +wire csr_port_we; +wire [7:0] csr_port_dat_w; +wire [7:0] csr_port_dat_r; +wire user_port_cmd_valid; +wire user_port_cmd_ready; +wire user_port_cmd_payload_we; +wire [24:0] user_port_cmd_payload_addr; +wire user_port_wdata_valid; +wire user_port_wdata_ready; +wire [127:0] user_port_wdata_payload_data; +wire [15:0] user_port_wdata_payload_we; +wire user_port_rdata_valid; +wire user_port_rdata_ready; +wire [127:0] user_port_rdata_payload_data; +wire pll_fb0; +wire pll_fb1; +reg [1:0] refresher_state = 2'd0; +reg [1:0] refresher_next_state = 2'd0; +reg [3:0] bankmachine0_state = 4'd0; +reg [3:0] bankmachine0_next_state = 4'd0; +reg [3:0] bankmachine1_state = 4'd0; +reg [3:0] bankmachine1_next_state = 4'd0; +reg [3:0] bankmachine2_state = 4'd0; +reg [3:0] bankmachine2_next_state = 4'd0; +reg [3:0] bankmachine3_state = 4'd0; +reg [3:0] bankmachine3_next_state = 4'd0; +reg [3:0] bankmachine4_state = 4'd0; +reg [3:0] bankmachine4_next_state = 4'd0; +reg [3:0] bankmachine5_state = 4'd0; +reg [3:0] bankmachine5_next_state = 4'd0; +reg [3:0] bankmachine6_state = 4'd0; +reg [3:0] bankmachine6_next_state = 4'd0; +reg [3:0] bankmachine7_state = 4'd0; +reg [3:0] bankmachine7_next_state = 4'd0; +reg [3:0] multiplexer_state = 4'd0; +reg [3:0] multiplexer_next_state = 4'd0; +wire roundrobin0_request; +wire roundrobin0_grant; +wire roundrobin0_ce; +wire roundrobin1_request; +wire roundrobin1_grant; +wire roundrobin1_ce; +wire roundrobin2_request; +wire roundrobin2_grant; +wire roundrobin2_ce; +wire roundrobin3_request; +wire roundrobin3_grant; +wire roundrobin3_ce; +wire roundrobin4_request; +wire roundrobin4_grant; +wire roundrobin4_ce; +wire roundrobin5_request; +wire roundrobin5_grant; +wire roundrobin5_ce; +wire roundrobin6_request; +wire roundrobin6_grant; +wire roundrobin6_ce; +wire roundrobin7_request; +wire roundrobin7_grant; +wire roundrobin7_ce; +reg locked0 = 1'd0; +reg locked1 = 1'd0; +reg locked2 = 1'd0; +reg locked3 = 1'd0; +reg locked4 = 1'd0; +reg locked5 = 1'd0; +reg locked6 = 1'd0; +reg locked7 = 1'd0; +reg new_master_wdata_ready0 = 1'd0; +reg new_master_wdata_ready1 = 1'd0; +reg new_master_wdata_ready2 = 1'd0; +reg new_master_rdata_valid0 = 1'd0; +reg new_master_rdata_valid1 = 1'd0; +reg new_master_rdata_valid2 = 1'd0; +reg new_master_rdata_valid3 = 1'd0; +reg new_master_rdata_valid4 = 1'd0; +reg new_master_rdata_valid5 = 1'd0; +reg new_master_rdata_valid6 = 1'd0; +reg new_master_rdata_valid7 = 1'd0; +reg new_master_rdata_valid8 = 1'd0; +wire [13:0] interface0_bank_bus_adr; +wire interface0_bank_bus_we; +wire [7:0] interface0_bank_bus_dat_w; +reg [7:0] interface0_bank_bus_dat_r = 8'd0; +wire csrbank0_init_done0_re; +wire csrbank0_init_done0_r; +wire csrbank0_init_done0_we; +wire csrbank0_init_done0_w; +wire csrbank0_init_error0_re; +wire csrbank0_init_error0_r; +wire csrbank0_init_error0_we; +wire csrbank0_init_error0_w; +reg csrbank0_sel = 1'd0; +wire [13:0] interface1_bank_bus_adr; +wire interface1_bank_bus_we; +wire [7:0] interface1_bank_bus_dat_w; +reg [7:0] interface1_bank_bus_dat_r = 8'd0; +wire csrbank1_half_sys8x_taps0_re; +wire [4:0] csrbank1_half_sys8x_taps0_r; +wire csrbank1_half_sys8x_taps0_we; +wire [4:0] csrbank1_half_sys8x_taps0_w; +wire csrbank1_wlevel_en0_re; +wire csrbank1_wlevel_en0_r; +wire csrbank1_wlevel_en0_we; +wire csrbank1_wlevel_en0_w; +wire csrbank1_dly_sel0_re; +wire [1:0] csrbank1_dly_sel0_r; +wire csrbank1_dly_sel0_we; +wire [1:0] csrbank1_dly_sel0_w; +reg csrbank1_sel = 1'd0; +wire [13:0] interface2_bank_bus_adr; +wire interface2_bank_bus_we; +wire [7:0] interface2_bank_bus_dat_w; +reg [7:0] interface2_bank_bus_dat_r = 8'd0; +wire csrbank2_dfii_control0_re; +wire [3:0] csrbank2_dfii_control0_r; +wire csrbank2_dfii_control0_we; +wire [3:0] csrbank2_dfii_control0_w; +wire csrbank2_dfii_pi0_command0_re; +wire [5:0] csrbank2_dfii_pi0_command0_r; +wire csrbank2_dfii_pi0_command0_we; +wire [5:0] csrbank2_dfii_pi0_command0_w; +wire csrbank2_dfii_pi0_address1_re; +wire [6:0] csrbank2_dfii_pi0_address1_r; +wire csrbank2_dfii_pi0_address1_we; +wire [6:0] csrbank2_dfii_pi0_address1_w; +wire csrbank2_dfii_pi0_address0_re; +wire [7:0] csrbank2_dfii_pi0_address0_r; +wire csrbank2_dfii_pi0_address0_we; +wire [7:0] csrbank2_dfii_pi0_address0_w; +wire csrbank2_dfii_pi0_baddress0_re; +wire [2:0] csrbank2_dfii_pi0_baddress0_r; +wire csrbank2_dfii_pi0_baddress0_we; +wire [2:0] csrbank2_dfii_pi0_baddress0_w; +wire csrbank2_dfii_pi0_wrdata3_re; +wire [7:0] csrbank2_dfii_pi0_wrdata3_r; +wire csrbank2_dfii_pi0_wrdata3_we; +wire [7:0] csrbank2_dfii_pi0_wrdata3_w; +wire csrbank2_dfii_pi0_wrdata2_re; +wire [7:0] csrbank2_dfii_pi0_wrdata2_r; +wire csrbank2_dfii_pi0_wrdata2_we; +wire [7:0] csrbank2_dfii_pi0_wrdata2_w; +wire csrbank2_dfii_pi0_wrdata1_re; +wire [7:0] csrbank2_dfii_pi0_wrdata1_r; +wire csrbank2_dfii_pi0_wrdata1_we; +wire [7:0] csrbank2_dfii_pi0_wrdata1_w; +wire csrbank2_dfii_pi0_wrdata0_re; +wire [7:0] csrbank2_dfii_pi0_wrdata0_r; +wire csrbank2_dfii_pi0_wrdata0_we; +wire [7:0] csrbank2_dfii_pi0_wrdata0_w; +wire csrbank2_dfii_pi0_rddata3_re; +wire [7:0] csrbank2_dfii_pi0_rddata3_r; +wire csrbank2_dfii_pi0_rddata3_we; +wire [7:0] csrbank2_dfii_pi0_rddata3_w; +wire csrbank2_dfii_pi0_rddata2_re; +wire [7:0] csrbank2_dfii_pi0_rddata2_r; +wire csrbank2_dfii_pi0_rddata2_we; +wire [7:0] csrbank2_dfii_pi0_rddata2_w; +wire csrbank2_dfii_pi0_rddata1_re; +wire [7:0] csrbank2_dfii_pi0_rddata1_r; +wire csrbank2_dfii_pi0_rddata1_we; +wire [7:0] csrbank2_dfii_pi0_rddata1_w; +wire csrbank2_dfii_pi0_rddata0_re; +wire [7:0] csrbank2_dfii_pi0_rddata0_r; +wire csrbank2_dfii_pi0_rddata0_we; +wire [7:0] csrbank2_dfii_pi0_rddata0_w; +wire csrbank2_dfii_pi1_command0_re; +wire [5:0] csrbank2_dfii_pi1_command0_r; +wire csrbank2_dfii_pi1_command0_we; +wire [5:0] csrbank2_dfii_pi1_command0_w; +wire csrbank2_dfii_pi1_address1_re; +wire [6:0] csrbank2_dfii_pi1_address1_r; +wire csrbank2_dfii_pi1_address1_we; +wire [6:0] csrbank2_dfii_pi1_address1_w; +wire csrbank2_dfii_pi1_address0_re; +wire [7:0] csrbank2_dfii_pi1_address0_r; +wire csrbank2_dfii_pi1_address0_we; +wire [7:0] csrbank2_dfii_pi1_address0_w; +wire csrbank2_dfii_pi1_baddress0_re; +wire [2:0] csrbank2_dfii_pi1_baddress0_r; +wire csrbank2_dfii_pi1_baddress0_we; +wire [2:0] csrbank2_dfii_pi1_baddress0_w; +wire csrbank2_dfii_pi1_wrdata3_re; +wire [7:0] csrbank2_dfii_pi1_wrdata3_r; +wire csrbank2_dfii_pi1_wrdata3_we; +wire [7:0] csrbank2_dfii_pi1_wrdata3_w; +wire csrbank2_dfii_pi1_wrdata2_re; +wire [7:0] csrbank2_dfii_pi1_wrdata2_r; +wire csrbank2_dfii_pi1_wrdata2_we; +wire [7:0] csrbank2_dfii_pi1_wrdata2_w; +wire csrbank2_dfii_pi1_wrdata1_re; +wire [7:0] csrbank2_dfii_pi1_wrdata1_r; +wire csrbank2_dfii_pi1_wrdata1_we; +wire [7:0] csrbank2_dfii_pi1_wrdata1_w; +wire csrbank2_dfii_pi1_wrdata0_re; +wire [7:0] csrbank2_dfii_pi1_wrdata0_r; +wire csrbank2_dfii_pi1_wrdata0_we; +wire [7:0] csrbank2_dfii_pi1_wrdata0_w; +wire csrbank2_dfii_pi1_rddata3_re; +wire [7:0] csrbank2_dfii_pi1_rddata3_r; +wire csrbank2_dfii_pi1_rddata3_we; +wire [7:0] csrbank2_dfii_pi1_rddata3_w; +wire csrbank2_dfii_pi1_rddata2_re; +wire [7:0] csrbank2_dfii_pi1_rddata2_r; +wire csrbank2_dfii_pi1_rddata2_we; +wire [7:0] csrbank2_dfii_pi1_rddata2_w; +wire csrbank2_dfii_pi1_rddata1_re; +wire [7:0] csrbank2_dfii_pi1_rddata1_r; +wire csrbank2_dfii_pi1_rddata1_we; +wire [7:0] csrbank2_dfii_pi1_rddata1_w; +wire csrbank2_dfii_pi1_rddata0_re; +wire [7:0] csrbank2_dfii_pi1_rddata0_r; +wire csrbank2_dfii_pi1_rddata0_we; +wire [7:0] csrbank2_dfii_pi1_rddata0_w; +wire csrbank2_dfii_pi2_command0_re; +wire [5:0] csrbank2_dfii_pi2_command0_r; +wire csrbank2_dfii_pi2_command0_we; +wire [5:0] csrbank2_dfii_pi2_command0_w; +wire csrbank2_dfii_pi2_address1_re; +wire [6:0] csrbank2_dfii_pi2_address1_r; +wire csrbank2_dfii_pi2_address1_we; +wire [6:0] csrbank2_dfii_pi2_address1_w; +wire csrbank2_dfii_pi2_address0_re; +wire [7:0] csrbank2_dfii_pi2_address0_r; +wire csrbank2_dfii_pi2_address0_we; +wire [7:0] csrbank2_dfii_pi2_address0_w; +wire csrbank2_dfii_pi2_baddress0_re; +wire [2:0] csrbank2_dfii_pi2_baddress0_r; +wire csrbank2_dfii_pi2_baddress0_we; +wire [2:0] csrbank2_dfii_pi2_baddress0_w; +wire csrbank2_dfii_pi2_wrdata3_re; +wire [7:0] csrbank2_dfii_pi2_wrdata3_r; +wire csrbank2_dfii_pi2_wrdata3_we; +wire [7:0] csrbank2_dfii_pi2_wrdata3_w; +wire csrbank2_dfii_pi2_wrdata2_re; +wire [7:0] csrbank2_dfii_pi2_wrdata2_r; +wire csrbank2_dfii_pi2_wrdata2_we; +wire [7:0] csrbank2_dfii_pi2_wrdata2_w; +wire csrbank2_dfii_pi2_wrdata1_re; +wire [7:0] csrbank2_dfii_pi2_wrdata1_r; +wire csrbank2_dfii_pi2_wrdata1_we; +wire [7:0] csrbank2_dfii_pi2_wrdata1_w; +wire csrbank2_dfii_pi2_wrdata0_re; +wire [7:0] csrbank2_dfii_pi2_wrdata0_r; +wire csrbank2_dfii_pi2_wrdata0_we; +wire [7:0] csrbank2_dfii_pi2_wrdata0_w; +wire csrbank2_dfii_pi2_rddata3_re; +wire [7:0] csrbank2_dfii_pi2_rddata3_r; +wire csrbank2_dfii_pi2_rddata3_we; +wire [7:0] csrbank2_dfii_pi2_rddata3_w; +wire csrbank2_dfii_pi2_rddata2_re; +wire [7:0] csrbank2_dfii_pi2_rddata2_r; +wire csrbank2_dfii_pi2_rddata2_we; +wire [7:0] csrbank2_dfii_pi2_rddata2_w; +wire csrbank2_dfii_pi2_rddata1_re; +wire [7:0] csrbank2_dfii_pi2_rddata1_r; +wire csrbank2_dfii_pi2_rddata1_we; +wire [7:0] csrbank2_dfii_pi2_rddata1_w; +wire csrbank2_dfii_pi2_rddata0_re; +wire [7:0] csrbank2_dfii_pi2_rddata0_r; +wire csrbank2_dfii_pi2_rddata0_we; +wire [7:0] csrbank2_dfii_pi2_rddata0_w; +wire csrbank2_dfii_pi3_command0_re; +wire [5:0] csrbank2_dfii_pi3_command0_r; +wire csrbank2_dfii_pi3_command0_we; +wire [5:0] csrbank2_dfii_pi3_command0_w; +wire csrbank2_dfii_pi3_address1_re; +wire [6:0] csrbank2_dfii_pi3_address1_r; +wire csrbank2_dfii_pi3_address1_we; +wire [6:0] csrbank2_dfii_pi3_address1_w; +wire csrbank2_dfii_pi3_address0_re; +wire [7:0] csrbank2_dfii_pi3_address0_r; +wire csrbank2_dfii_pi3_address0_we; +wire [7:0] csrbank2_dfii_pi3_address0_w; +wire csrbank2_dfii_pi3_baddress0_re; +wire [2:0] csrbank2_dfii_pi3_baddress0_r; +wire csrbank2_dfii_pi3_baddress0_we; +wire [2:0] csrbank2_dfii_pi3_baddress0_w; +wire csrbank2_dfii_pi3_wrdata3_re; +wire [7:0] csrbank2_dfii_pi3_wrdata3_r; +wire csrbank2_dfii_pi3_wrdata3_we; +wire [7:0] csrbank2_dfii_pi3_wrdata3_w; +wire csrbank2_dfii_pi3_wrdata2_re; +wire [7:0] csrbank2_dfii_pi3_wrdata2_r; +wire csrbank2_dfii_pi3_wrdata2_we; +wire [7:0] csrbank2_dfii_pi3_wrdata2_w; +wire csrbank2_dfii_pi3_wrdata1_re; +wire [7:0] csrbank2_dfii_pi3_wrdata1_r; +wire csrbank2_dfii_pi3_wrdata1_we; +wire [7:0] csrbank2_dfii_pi3_wrdata1_w; +wire csrbank2_dfii_pi3_wrdata0_re; +wire [7:0] csrbank2_dfii_pi3_wrdata0_r; +wire csrbank2_dfii_pi3_wrdata0_we; +wire [7:0] csrbank2_dfii_pi3_wrdata0_w; +wire csrbank2_dfii_pi3_rddata3_re; +wire [7:0] csrbank2_dfii_pi3_rddata3_r; +wire csrbank2_dfii_pi3_rddata3_we; +wire [7:0] csrbank2_dfii_pi3_rddata3_w; +wire csrbank2_dfii_pi3_rddata2_re; +wire [7:0] csrbank2_dfii_pi3_rddata2_r; +wire csrbank2_dfii_pi3_rddata2_we; +wire [7:0] csrbank2_dfii_pi3_rddata2_w; +wire csrbank2_dfii_pi3_rddata1_re; +wire [7:0] csrbank2_dfii_pi3_rddata1_r; +wire csrbank2_dfii_pi3_rddata1_we; +wire [7:0] csrbank2_dfii_pi3_rddata1_w; +wire csrbank2_dfii_pi3_rddata0_re; +wire [7:0] csrbank2_dfii_pi3_rddata0_r; +wire csrbank2_dfii_pi3_rddata0_we; +wire [7:0] csrbank2_dfii_pi3_rddata0_w; +reg csrbank2_sel = 1'd0; +wire [13:0] adr; +wire we; +wire [7:0] dat_w; +wire [7:0] dat_r; +reg rhs_array_muxed0 = 1'd0; +reg [14:0] rhs_array_muxed1 = 15'd0; +reg [2:0] rhs_array_muxed2 = 3'd0; +reg rhs_array_muxed3 = 1'd0; +reg rhs_array_muxed4 = 1'd0; +reg rhs_array_muxed5 = 1'd0; +reg t_array_muxed0 = 1'd0; +reg t_array_muxed1 = 1'd0; +reg t_array_muxed2 = 1'd0; +reg rhs_array_muxed6 = 1'd0; +reg [14:0] rhs_array_muxed7 = 15'd0; +reg [2:0] rhs_array_muxed8 = 3'd0; +reg rhs_array_muxed9 = 1'd0; +reg rhs_array_muxed10 = 1'd0; +reg rhs_array_muxed11 = 1'd0; +reg t_array_muxed3 = 1'd0; +reg t_array_muxed4 = 1'd0; +reg t_array_muxed5 = 1'd0; +reg [21:0] rhs_array_muxed12 = 22'd0; +reg rhs_array_muxed13 = 1'd0; +reg rhs_array_muxed14 = 1'd0; +reg [21:0] rhs_array_muxed15 = 22'd0; +reg rhs_array_muxed16 = 1'd0; +reg rhs_array_muxed17 = 1'd0; +reg [21:0] rhs_array_muxed18 = 22'd0; +reg rhs_array_muxed19 = 1'd0; +reg rhs_array_muxed20 = 1'd0; +reg [21:0] rhs_array_muxed21 = 22'd0; +reg rhs_array_muxed22 = 1'd0; +reg rhs_array_muxed23 = 1'd0; +reg [21:0] rhs_array_muxed24 = 22'd0; +reg rhs_array_muxed25 = 1'd0; +reg rhs_array_muxed26 = 1'd0; +reg [21:0] rhs_array_muxed27 = 22'd0; +reg rhs_array_muxed28 = 1'd0; +reg rhs_array_muxed29 = 1'd0; +reg [21:0] rhs_array_muxed30 = 22'd0; +reg rhs_array_muxed31 = 1'd0; +reg rhs_array_muxed32 = 1'd0; +reg [21:0] rhs_array_muxed33 = 22'd0; +reg rhs_array_muxed34 = 1'd0; +reg rhs_array_muxed35 = 1'd0; +reg [2:0] array_muxed0 = 3'd0; +reg [14:0] array_muxed1 = 15'd0; +reg array_muxed2 = 1'd0; +reg array_muxed3 = 1'd0; +reg array_muxed4 = 1'd0; +reg array_muxed5 = 1'd0; +reg array_muxed6 = 1'd0; +reg [2:0] array_muxed7 = 3'd0; +reg [14:0] array_muxed8 = 15'd0; +reg array_muxed9 = 1'd0; +reg array_muxed10 = 1'd0; +reg array_muxed11 = 1'd0; +reg array_muxed12 = 1'd0; +reg array_muxed13 = 1'd0; +reg [2:0] array_muxed14 = 3'd0; +reg [14:0] array_muxed15 = 15'd0; +reg array_muxed16 = 1'd0; +reg array_muxed17 = 1'd0; +reg array_muxed18 = 1'd0; +reg array_muxed19 = 1'd0; +reg array_muxed20 = 1'd0; +reg [2:0] array_muxed21 = 3'd0; +reg [14:0] array_muxed22 = 15'd0; +reg array_muxed23 = 1'd0; +reg array_muxed24 = 1'd0; +reg array_muxed25 = 1'd0; +reg array_muxed26 = 1'd0; +reg array_muxed27 = 1'd0; +wire xilinxasyncresetsynchronizerimpl0; +wire xilinxasyncresetsynchronizerimpl0_rst_meta; +wire xilinxasyncresetsynchronizerimpl1; +wire xilinxasyncresetsynchronizerimpl1_rst_meta; +wire xilinxasyncresetsynchronizerimpl1_expr; +wire xilinxasyncresetsynchronizerimpl2; +wire xilinxasyncresetsynchronizerimpl2_rst_meta; +wire xilinxasyncresetsynchronizerimpl2_expr; +wire xilinxasyncresetsynchronizerimpl3; +wire xilinxasyncresetsynchronizerimpl3_rst_meta; // synthesis translate_off reg dummy_s; initial dummy_s <= 1'd0; // synthesis translate_on -assign soc_litedramcore_cpu_reset = soc_litedramcore_soccontroller_reset; -assign init_done = soc_init_done_storage; -assign init_error = soc_init_error_storage; +assign init_done = init_done_storage; +assign init_error = init_error_storage; +assign csr_port_adr = csr_port0_adr; +assign csr_port_we = csr_port0_we; +assign csr_port_dat_w = csr_port0_dat_w; +assign csr_port0_dat_r = csr_port_dat_r; assign user_clk = sys_clk; assign user_rst = sys_rst; -assign soc_cmd_valid = user_port_native_0_cmd_valid; -assign user_port_native_0_cmd_ready = soc_cmd_ready; -assign soc_cmd_payload_we = user_port_native_0_cmd_we; -assign soc_cmd_payload_addr = user_port_native_0_cmd_addr; -assign soc_wdata_valid = user_port_native_0_wdata_valid; -assign user_port_native_0_wdata_ready = soc_wdata_ready; -assign soc_wdata_payload_we = user_port_native_0_wdata_we; -assign soc_wdata_payload_data = user_port_native_0_wdata_data; -assign user_port_native_0_rdata_valid = soc_rdata_valid; -assign soc_rdata_ready = user_port_native_0_rdata_ready; -assign user_port_native_0_rdata_data = soc_rdata_payload_data; -assign soc_litedramcore_soccontroller_bus_error = vns_error; +assign user_port_cmd_valid = user_port_native_0_cmd_valid; +assign user_port_native_0_cmd_ready = user_port_cmd_ready; +assign user_port_cmd_payload_we = user_port_native_0_cmd_we; +assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr; +assign user_port_wdata_valid = user_port_native_0_wdata_valid; +assign user_port_native_0_wdata_ready = user_port_wdata_ready; +assign user_port_wdata_payload_we = user_port_native_0_wdata_we; +assign user_port_wdata_payload_data = user_port_native_0_wdata_data; +assign user_port_native_0_rdata_valid = user_port_rdata_valid; +assign user_port_rdata_ready = user_port_native_0_rdata_ready; +assign user_port_native_0_rdata_data = user_port_rdata_payload_data; +assign sys_pll_reset = rst; +assign pll_locked = sys_pll_locked; +assign iodelay_pll_reset = rst; +assign s7pll0_clkin = clk; +assign sys_clk = s7pll0_clkout_buf0; +assign sys4x_clk = s7pll0_clkout_buf1; +assign sys4x_dqs_clk = s7pll0_clkout_buf2; +assign s7pll1_clkin = clk; +assign iodelay_clk = s7pll1_clkout_buf; +assign a7ddrphy_bitslip0_i = a7ddrphy_dq_i_data0; // synthesis translate_off reg dummy_d; // synthesis translate_on always @(*) begin - soc_litedramcore_cpu_interrupt <= 32'd0; - soc_litedramcore_cpu_interrupt[1] <= soc_litedramcore_timer_irq; - soc_litedramcore_cpu_interrupt[0] <= soc_litedramcore_uart_irq; + a7ddrphy_dfi_p0_rddata <= 32'd0; + a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip0_o[0]; + a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip0_o[1]; + a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip1_o[0]; + a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip1_o[1]; + a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip2_o[0]; + a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip2_o[1]; + a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip3_o[0]; + a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip3_o[1]; + a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip4_o[0]; + a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip4_o[1]; + a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip5_o[0]; + a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip5_o[1]; + a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip6_o[0]; + a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip6_o[1]; + a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip7_o[0]; + a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip7_o[1]; + a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip8_o[0]; + a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip8_o[1]; + a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip9_o[0]; + a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip9_o[1]; + a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip10_o[0]; + a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip10_o[1]; + a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip11_o[0]; + a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip11_o[1]; + a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip12_o[0]; + a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip12_o[1]; + a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip13_o[0]; + a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip13_o[1]; + a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip14_o[0]; + a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip14_o[1]; + a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip15_o[0]; + a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip15_o[1]; // synthesis translate_off dummy_d = dummy_s; // synthesis translate_on end -assign soc_litedramcore_soccontroller_reset = soc_litedramcore_soccontroller_reset_re; -assign soc_litedramcore_soccontroller_bus_errors_status = soc_litedramcore_soccontroller_bus_errors; -assign soc_litedramcore_litedramcore_adr = soc_litedramcore_litedramcore_ram_bus_adr[12:0]; -assign soc_litedramcore_litedramcore_ram_bus_dat_r = soc_litedramcore_litedramcore_dat_r; // synthesis translate_off reg dummy_d_1; // synthesis translate_on always @(*) begin - soc_litedramcore_ram_we <= 4'd0; - soc_litedramcore_ram_we[0] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[0]); - soc_litedramcore_ram_we[1] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[1]); - soc_litedramcore_ram_we[2] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[2]); - soc_litedramcore_ram_we[3] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[3]); + a7ddrphy_dfi_p1_rddata <= 32'd0; + a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip0_o[2]; + a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip0_o[3]; + a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip1_o[2]; + a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip1_o[3]; + a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip2_o[2]; + a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip2_o[3]; + a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip3_o[2]; + a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip3_o[3]; + a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip4_o[2]; + a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip4_o[3]; + a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip5_o[2]; + a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip5_o[3]; + a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip6_o[2]; + a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip6_o[3]; + a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip7_o[2]; + a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip7_o[3]; + a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip8_o[2]; + a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip8_o[3]; + a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip9_o[2]; + a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip9_o[3]; + a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip10_o[2]; + a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip10_o[3]; + a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip11_o[2]; + a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip11_o[3]; + a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip12_o[2]; + a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip12_o[3]; + a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip13_o[2]; + a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip13_o[3]; + a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip14_o[2]; + a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip14_o[3]; + a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip15_o[2]; + a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip15_o[3]; // synthesis translate_off dummy_d_1 = dummy_s; // synthesis translate_on end -assign soc_litedramcore_ram_adr = soc_litedramcore_ram_bus_ram_bus_adr[9:0]; -assign soc_litedramcore_ram_bus_ram_bus_dat_r = soc_litedramcore_ram_dat_r; -assign soc_litedramcore_ram_dat_w = soc_litedramcore_ram_bus_ram_bus_dat_w; -assign soc_litedramcore_uart_uart_sink_valid = soc_litedramcore_source_valid; -assign soc_litedramcore_source_ready = soc_litedramcore_uart_uart_sink_ready; -assign soc_litedramcore_uart_uart_sink_first = soc_litedramcore_source_first; -assign soc_litedramcore_uart_uart_sink_last = soc_litedramcore_source_last; -assign soc_litedramcore_uart_uart_sink_payload_data = soc_litedramcore_source_payload_data; -assign soc_litedramcore_sink_valid = soc_litedramcore_uart_uart_source_valid; -assign soc_litedramcore_uart_uart_source_ready = soc_litedramcore_sink_ready; -assign soc_litedramcore_sink_first = soc_litedramcore_uart_uart_source_first; -assign soc_litedramcore_sink_last = soc_litedramcore_uart_uart_source_last; -assign soc_litedramcore_sink_payload_data = soc_litedramcore_uart_uart_source_payload_data; -assign soc_litedramcore_uart_tx_fifo_sink_valid = soc_litedramcore_uart_rxtx_re; -assign soc_litedramcore_uart_tx_fifo_sink_payload_data = soc_litedramcore_uart_rxtx_r; -assign soc_litedramcore_uart_txfull_status = (~soc_litedramcore_uart_tx_fifo_sink_ready); -assign soc_litedramcore_uart_uart_source_valid = soc_litedramcore_uart_tx_fifo_source_valid; -assign soc_litedramcore_uart_tx_fifo_source_ready = soc_litedramcore_uart_uart_source_ready; -assign soc_litedramcore_uart_uart_source_first = soc_litedramcore_uart_tx_fifo_source_first; -assign soc_litedramcore_uart_uart_source_last = soc_litedramcore_uart_tx_fifo_source_last; -assign soc_litedramcore_uart_uart_source_payload_data = soc_litedramcore_uart_tx_fifo_source_payload_data; -assign soc_litedramcore_uart_tx_trigger = (~soc_litedramcore_uart_tx_fifo_sink_ready); -assign soc_litedramcore_uart_rx_fifo_sink_valid = soc_litedramcore_uart_uart_sink_valid; -assign soc_litedramcore_uart_uart_sink_ready = soc_litedramcore_uart_rx_fifo_sink_ready; -assign soc_litedramcore_uart_rx_fifo_sink_first = soc_litedramcore_uart_uart_sink_first; -assign soc_litedramcore_uart_rx_fifo_sink_last = soc_litedramcore_uart_uart_sink_last; -assign soc_litedramcore_uart_rx_fifo_sink_payload_data = soc_litedramcore_uart_uart_sink_payload_data; -assign soc_litedramcore_uart_rxempty_status = (~soc_litedramcore_uart_rx_fifo_source_valid); -assign soc_litedramcore_uart_rxtx_w = soc_litedramcore_uart_rx_fifo_source_payload_data; -assign soc_litedramcore_uart_rx_fifo_source_ready = (soc_litedramcore_uart_rx_clear | (1'd0 & soc_litedramcore_uart_rxtx_we)); -assign soc_litedramcore_uart_rx_trigger = (~soc_litedramcore_uart_rx_fifo_source_valid); // synthesis translate_off reg dummy_d_2; // synthesis translate_on always @(*) begin - soc_litedramcore_uart_eventmanager_status_w <= 2'd0; - soc_litedramcore_uart_eventmanager_status_w[0] <= soc_litedramcore_uart_tx_status; - soc_litedramcore_uart_eventmanager_status_w[1] <= soc_litedramcore_uart_rx_status; + a7ddrphy_dfi_p2_rddata <= 32'd0; + a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip0_o[4]; + a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip0_o[5]; + a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip1_o[4]; + a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip1_o[5]; + a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip2_o[4]; + a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip2_o[5]; + a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip3_o[4]; + a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip3_o[5]; + a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip4_o[4]; + a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip4_o[5]; + a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip5_o[4]; + a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip5_o[5]; + a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip6_o[4]; + a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip6_o[5]; + a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip7_o[4]; + a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip7_o[5]; + a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip8_o[4]; + a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip8_o[5]; + a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip9_o[4]; + a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip9_o[5]; + a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip10_o[4]; + a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip10_o[5]; + a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip11_o[4]; + a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip11_o[5]; + a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip12_o[4]; + a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip12_o[5]; + a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip13_o[4]; + a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip13_o[5]; + a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip14_o[4]; + a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip14_o[5]; + a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip15_o[4]; + a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip15_o[5]; // synthesis translate_off dummy_d_2 = dummy_s; // synthesis translate_on @@ -2562,1302 +2044,1142 @@ end reg dummy_d_3; // synthesis translate_on always @(*) begin - soc_litedramcore_uart_tx_clear <= 1'd0; - if ((soc_litedramcore_uart_eventmanager_pending_re & soc_litedramcore_uart_eventmanager_pending_r[0])) begin - soc_litedramcore_uart_tx_clear <= 1'd1; - end + a7ddrphy_dfi_p3_rddata <= 32'd0; + a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip0_o[6]; + a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip0_o[7]; + a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip1_o[6]; + a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip1_o[7]; + a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip2_o[6]; + a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip2_o[7]; + a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip3_o[6]; + a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip3_o[7]; + a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip4_o[6]; + a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip4_o[7]; + a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip5_o[6]; + a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip5_o[7]; + a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip6_o[6]; + a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip6_o[7]; + a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip7_o[6]; + a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip7_o[7]; + a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip8_o[6]; + a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip8_o[7]; + a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip9_o[6]; + a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip9_o[7]; + a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip10_o[6]; + a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip10_o[7]; + a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip11_o[6]; + a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip11_o[7]; + a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip12_o[6]; + a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip12_o[7]; + a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip13_o[6]; + a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip13_o[7]; + a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip14_o[6]; + a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip14_o[7]; + a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip15_o[6]; + a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip15_o[7]; // synthesis translate_off dummy_d_3 = dummy_s; // synthesis translate_on end +assign a7ddrphy_bitslip1_i = a7ddrphy_dq_i_data1; +assign a7ddrphy_bitslip2_i = a7ddrphy_dq_i_data2; +assign a7ddrphy_bitslip3_i = a7ddrphy_dq_i_data3; +assign a7ddrphy_bitslip4_i = a7ddrphy_dq_i_data4; +assign a7ddrphy_bitslip5_i = a7ddrphy_dq_i_data5; +assign a7ddrphy_bitslip6_i = a7ddrphy_dq_i_data6; +assign a7ddrphy_bitslip7_i = a7ddrphy_dq_i_data7; +assign a7ddrphy_bitslip8_i = a7ddrphy_dq_i_data8; +assign a7ddrphy_bitslip9_i = a7ddrphy_dq_i_data9; +assign a7ddrphy_bitslip10_i = a7ddrphy_dq_i_data10; +assign a7ddrphy_bitslip11_i = a7ddrphy_dq_i_data11; +assign a7ddrphy_bitslip12_i = a7ddrphy_dq_i_data12; +assign a7ddrphy_bitslip13_i = a7ddrphy_dq_i_data13; +assign a7ddrphy_bitslip14_i = a7ddrphy_dq_i_data14; +assign a7ddrphy_bitslip15_i = a7ddrphy_dq_i_data15; +assign a7ddrphy_rddata_en = {a7ddrphy_rddata_en_last, a7ddrphy_dfi_p2_rddata_en}; +assign a7ddrphy_wrdata_en = {a7ddrphy_wrdata_en_last, a7ddrphy_dfi_p3_wrdata_en}; +assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en[2]; // synthesis translate_off reg dummy_d_4; // synthesis translate_on always @(*) begin - soc_litedramcore_uart_eventmanager_pending_w <= 2'd0; - soc_litedramcore_uart_eventmanager_pending_w[0] <= soc_litedramcore_uart_tx_pending; - soc_litedramcore_uart_eventmanager_pending_w[1] <= soc_litedramcore_uart_rx_pending; -// synthesis translate_off - dummy_d_4 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_5; -// synthesis translate_on -always @(*) begin - soc_litedramcore_uart_rx_clear <= 1'd0; - if ((soc_litedramcore_uart_eventmanager_pending_re & soc_litedramcore_uart_eventmanager_pending_r[1])) begin - soc_litedramcore_uart_rx_clear <= 1'd1; - end -// synthesis translate_off - dummy_d_5 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_uart_irq = ((soc_litedramcore_uart_eventmanager_pending_w[0] & soc_litedramcore_uart_eventmanager_storage[0]) | (soc_litedramcore_uart_eventmanager_pending_w[1] & soc_litedramcore_uart_eventmanager_storage[1])); -assign soc_litedramcore_uart_tx_status = soc_litedramcore_uart_tx_trigger; -assign soc_litedramcore_uart_rx_status = soc_litedramcore_uart_rx_trigger; -assign soc_litedramcore_uart_tx_fifo_syncfifo_din = {soc_litedramcore_uart_tx_fifo_fifo_in_last, soc_litedramcore_uart_tx_fifo_fifo_in_first, soc_litedramcore_uart_tx_fifo_fifo_in_payload_data}; -assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout; -assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout; -assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout; -assign soc_litedramcore_uart_tx_fifo_sink_ready = soc_litedramcore_uart_tx_fifo_syncfifo_writable; -assign soc_litedramcore_uart_tx_fifo_syncfifo_we = soc_litedramcore_uart_tx_fifo_sink_valid; -assign soc_litedramcore_uart_tx_fifo_fifo_in_first = soc_litedramcore_uart_tx_fifo_sink_first; -assign soc_litedramcore_uart_tx_fifo_fifo_in_last = soc_litedramcore_uart_tx_fifo_sink_last; -assign soc_litedramcore_uart_tx_fifo_fifo_in_payload_data = soc_litedramcore_uart_tx_fifo_sink_payload_data; -assign soc_litedramcore_uart_tx_fifo_source_valid = soc_litedramcore_uart_tx_fifo_readable; -assign soc_litedramcore_uart_tx_fifo_source_first = soc_litedramcore_uart_tx_fifo_fifo_out_first; -assign soc_litedramcore_uart_tx_fifo_source_last = soc_litedramcore_uart_tx_fifo_fifo_out_last; -assign soc_litedramcore_uart_tx_fifo_source_payload_data = soc_litedramcore_uart_tx_fifo_fifo_out_payload_data; -assign soc_litedramcore_uart_tx_fifo_re = soc_litedramcore_uart_tx_fifo_source_ready; -assign soc_litedramcore_uart_tx_fifo_syncfifo_re = (soc_litedramcore_uart_tx_fifo_syncfifo_readable & ((~soc_litedramcore_uart_tx_fifo_readable) | soc_litedramcore_uart_tx_fifo_re)); -assign soc_litedramcore_uart_tx_fifo_level1 = (soc_litedramcore_uart_tx_fifo_level0 + soc_litedramcore_uart_tx_fifo_readable); - -// synthesis translate_off -reg dummy_d_6; -// synthesis translate_on -always @(*) begin - soc_litedramcore_uart_tx_fifo_wrport_adr <= 4'd0; - if (soc_litedramcore_uart_tx_fifo_replace) begin - soc_litedramcore_uart_tx_fifo_wrport_adr <= (soc_litedramcore_uart_tx_fifo_produce - 1'd1); - end else begin - soc_litedramcore_uart_tx_fifo_wrport_adr <= soc_litedramcore_uart_tx_fifo_produce; - end -// synthesis translate_off - dummy_d_6 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_uart_tx_fifo_wrport_dat_w = soc_litedramcore_uart_tx_fifo_syncfifo_din; -assign soc_litedramcore_uart_tx_fifo_wrport_we = (soc_litedramcore_uart_tx_fifo_syncfifo_we & (soc_litedramcore_uart_tx_fifo_syncfifo_writable | soc_litedramcore_uart_tx_fifo_replace)); -assign soc_litedramcore_uart_tx_fifo_do_read = (soc_litedramcore_uart_tx_fifo_syncfifo_readable & soc_litedramcore_uart_tx_fifo_syncfifo_re); -assign soc_litedramcore_uart_tx_fifo_rdport_adr = soc_litedramcore_uart_tx_fifo_consume; -assign soc_litedramcore_uart_tx_fifo_syncfifo_dout = soc_litedramcore_uart_tx_fifo_rdport_dat_r; -assign soc_litedramcore_uart_tx_fifo_rdport_re = soc_litedramcore_uart_tx_fifo_do_read; -assign soc_litedramcore_uart_tx_fifo_syncfifo_writable = (soc_litedramcore_uart_tx_fifo_level0 != 5'd16); -assign soc_litedramcore_uart_tx_fifo_syncfifo_readable = (soc_litedramcore_uart_tx_fifo_level0 != 1'd0); -assign soc_litedramcore_uart_rx_fifo_syncfifo_din = {soc_litedramcore_uart_rx_fifo_fifo_in_last, soc_litedramcore_uart_rx_fifo_fifo_in_first, soc_litedramcore_uart_rx_fifo_fifo_in_payload_data}; -assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout; -assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout; -assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout; -assign soc_litedramcore_uart_rx_fifo_sink_ready = soc_litedramcore_uart_rx_fifo_syncfifo_writable; -assign soc_litedramcore_uart_rx_fifo_syncfifo_we = soc_litedramcore_uart_rx_fifo_sink_valid; -assign soc_litedramcore_uart_rx_fifo_fifo_in_first = soc_litedramcore_uart_rx_fifo_sink_first; -assign soc_litedramcore_uart_rx_fifo_fifo_in_last = soc_litedramcore_uart_rx_fifo_sink_last; -assign soc_litedramcore_uart_rx_fifo_fifo_in_payload_data = soc_litedramcore_uart_rx_fifo_sink_payload_data; -assign soc_litedramcore_uart_rx_fifo_source_valid = soc_litedramcore_uart_rx_fifo_readable; -assign soc_litedramcore_uart_rx_fifo_source_first = soc_litedramcore_uart_rx_fifo_fifo_out_first; -assign soc_litedramcore_uart_rx_fifo_source_last = soc_litedramcore_uart_rx_fifo_fifo_out_last; -assign soc_litedramcore_uart_rx_fifo_source_payload_data = soc_litedramcore_uart_rx_fifo_fifo_out_payload_data; -assign soc_litedramcore_uart_rx_fifo_re = soc_litedramcore_uart_rx_fifo_source_ready; -assign soc_litedramcore_uart_rx_fifo_syncfifo_re = (soc_litedramcore_uart_rx_fifo_syncfifo_readable & ((~soc_litedramcore_uart_rx_fifo_readable) | soc_litedramcore_uart_rx_fifo_re)); -assign soc_litedramcore_uart_rx_fifo_level1 = (soc_litedramcore_uart_rx_fifo_level0 + soc_litedramcore_uart_rx_fifo_readable); - -// synthesis translate_off -reg dummy_d_7; -// synthesis translate_on -always @(*) begin - soc_litedramcore_uart_rx_fifo_wrport_adr <= 4'd0; - if (soc_litedramcore_uart_rx_fifo_replace) begin - soc_litedramcore_uart_rx_fifo_wrport_adr <= (soc_litedramcore_uart_rx_fifo_produce - 1'd1); - end else begin - soc_litedramcore_uart_rx_fifo_wrport_adr <= soc_litedramcore_uart_rx_fifo_produce; - end -// synthesis translate_off - dummy_d_7 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_uart_rx_fifo_wrport_dat_w = soc_litedramcore_uart_rx_fifo_syncfifo_din; -assign soc_litedramcore_uart_rx_fifo_wrport_we = (soc_litedramcore_uart_rx_fifo_syncfifo_we & (soc_litedramcore_uart_rx_fifo_syncfifo_writable | soc_litedramcore_uart_rx_fifo_replace)); -assign soc_litedramcore_uart_rx_fifo_do_read = (soc_litedramcore_uart_rx_fifo_syncfifo_readable & soc_litedramcore_uart_rx_fifo_syncfifo_re); -assign soc_litedramcore_uart_rx_fifo_rdport_adr = soc_litedramcore_uart_rx_fifo_consume; -assign soc_litedramcore_uart_rx_fifo_syncfifo_dout = soc_litedramcore_uart_rx_fifo_rdport_dat_r; -assign soc_litedramcore_uart_rx_fifo_rdport_re = soc_litedramcore_uart_rx_fifo_do_read; -assign soc_litedramcore_uart_rx_fifo_syncfifo_writable = (soc_litedramcore_uart_rx_fifo_level0 != 5'd16); -assign soc_litedramcore_uart_rx_fifo_syncfifo_readable = (soc_litedramcore_uart_rx_fifo_level0 != 1'd0); -assign soc_litedramcore_timer_zero_trigger = (soc_litedramcore_timer_value != 1'd0); -assign soc_litedramcore_timer_eventmanager_status_w = soc_litedramcore_timer_zero_status; - -// synthesis translate_off -reg dummy_d_8; -// synthesis translate_on -always @(*) begin - soc_litedramcore_timer_zero_clear <= 1'd0; - if ((soc_litedramcore_timer_eventmanager_pending_re & soc_litedramcore_timer_eventmanager_pending_r)) begin - soc_litedramcore_timer_zero_clear <= 1'd1; - end -// synthesis translate_off - dummy_d_8 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_timer_eventmanager_pending_w = soc_litedramcore_timer_zero_pending; -assign soc_litedramcore_timer_irq = (soc_litedramcore_timer_eventmanager_pending_w & soc_litedramcore_timer_eventmanager_storage); -assign soc_litedramcore_timer_zero_status = soc_litedramcore_timer_zero_trigger; -assign soc_litedramcore_interface_dat_w = soc_litedramcore_bus_wishbone_dat_w; -assign soc_litedramcore_bus_wishbone_dat_r = soc_litedramcore_interface_dat_r; - -// synthesis translate_off -reg dummy_d_9; -// synthesis translate_on -always @(*) begin - vns_wb2csr_next_state <= 1'd0; - vns_wb2csr_next_state <= vns_wb2csr_state; - case (vns_wb2csr_state) - 1'd1: begin - vns_wb2csr_next_state <= 1'd0; - end - default: begin - if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin - vns_wb2csr_next_state <= 1'd1; - end - end - endcase -// synthesis translate_off - dummy_d_9 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_10; -// synthesis translate_on -always @(*) begin - soc_litedramcore_interface_adr <= 14'd0; - case (vns_wb2csr_state) - 1'd1: begin - end - default: begin - if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin - soc_litedramcore_interface_adr <= soc_litedramcore_bus_wishbone_adr; - end - end - endcase -// synthesis translate_off - dummy_d_10 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_11; -// synthesis translate_on -always @(*) begin - soc_litedramcore_interface_we <= 1'd0; - case (vns_wb2csr_state) - 1'd1: begin - end - default: begin - if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin - soc_litedramcore_interface_we <= soc_litedramcore_bus_wishbone_we; - end - end - endcase -// synthesis translate_off - dummy_d_11 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_12; -// synthesis translate_on -always @(*) begin - soc_litedramcore_bus_wishbone_ack <= 1'd0; - case (vns_wb2csr_state) - 1'd1: begin - soc_litedramcore_bus_wishbone_ack <= 1'd1; - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_12 = dummy_s; -// synthesis translate_on -end -assign soc_sys_pll_reset = rst; -assign pll_locked = soc_sys_pll_locked; -assign soc_iodelay_pll_reset = rst; -assign soc_s7pll0_clkin = clk; -assign sys_clk = soc_s7pll0_clkout_buf0; -assign sys4x_clk = soc_s7pll0_clkout_buf1; -assign sys4x_dqs_clk = soc_s7pll0_clkout_buf2; -assign soc_s7pll1_clkin = clk; -assign iodelay_clk = soc_s7pll1_clkout_buf; -assign soc_a7ddrphy_bitslip0_i = soc_a7ddrphy_dq_i_data0; - -// synthesis translate_off -reg dummy_d_13; -// synthesis translate_on -always @(*) begin - soc_a7ddrphy_dfi_p0_rddata <= 32'd0; - soc_a7ddrphy_dfi_p0_rddata[0] <= soc_a7ddrphy_bitslip0_o[0]; - soc_a7ddrphy_dfi_p0_rddata[16] <= soc_a7ddrphy_bitslip0_o[1]; - soc_a7ddrphy_dfi_p0_rddata[1] <= soc_a7ddrphy_bitslip1_o[0]; - soc_a7ddrphy_dfi_p0_rddata[17] <= soc_a7ddrphy_bitslip1_o[1]; - soc_a7ddrphy_dfi_p0_rddata[2] <= soc_a7ddrphy_bitslip2_o[0]; - soc_a7ddrphy_dfi_p0_rddata[18] <= soc_a7ddrphy_bitslip2_o[1]; - soc_a7ddrphy_dfi_p0_rddata[3] <= soc_a7ddrphy_bitslip3_o[0]; - soc_a7ddrphy_dfi_p0_rddata[19] <= soc_a7ddrphy_bitslip3_o[1]; - soc_a7ddrphy_dfi_p0_rddata[4] <= soc_a7ddrphy_bitslip4_o[0]; - soc_a7ddrphy_dfi_p0_rddata[20] <= soc_a7ddrphy_bitslip4_o[1]; - soc_a7ddrphy_dfi_p0_rddata[5] <= soc_a7ddrphy_bitslip5_o[0]; - soc_a7ddrphy_dfi_p0_rddata[21] <= soc_a7ddrphy_bitslip5_o[1]; - soc_a7ddrphy_dfi_p0_rddata[6] <= soc_a7ddrphy_bitslip6_o[0]; - soc_a7ddrphy_dfi_p0_rddata[22] <= soc_a7ddrphy_bitslip6_o[1]; - soc_a7ddrphy_dfi_p0_rddata[7] <= soc_a7ddrphy_bitslip7_o[0]; - soc_a7ddrphy_dfi_p0_rddata[23] <= soc_a7ddrphy_bitslip7_o[1]; - soc_a7ddrphy_dfi_p0_rddata[8] <= soc_a7ddrphy_bitslip8_o[0]; - soc_a7ddrphy_dfi_p0_rddata[24] <= soc_a7ddrphy_bitslip8_o[1]; - soc_a7ddrphy_dfi_p0_rddata[9] <= soc_a7ddrphy_bitslip9_o[0]; - soc_a7ddrphy_dfi_p0_rddata[25] <= soc_a7ddrphy_bitslip9_o[1]; - soc_a7ddrphy_dfi_p0_rddata[10] <= soc_a7ddrphy_bitslip10_o[0]; - soc_a7ddrphy_dfi_p0_rddata[26] <= soc_a7ddrphy_bitslip10_o[1]; - soc_a7ddrphy_dfi_p0_rddata[11] <= soc_a7ddrphy_bitslip11_o[0]; - soc_a7ddrphy_dfi_p0_rddata[27] <= soc_a7ddrphy_bitslip11_o[1]; - soc_a7ddrphy_dfi_p0_rddata[12] <= soc_a7ddrphy_bitslip12_o[0]; - soc_a7ddrphy_dfi_p0_rddata[28] <= soc_a7ddrphy_bitslip12_o[1]; - soc_a7ddrphy_dfi_p0_rddata[13] <= soc_a7ddrphy_bitslip13_o[0]; - soc_a7ddrphy_dfi_p0_rddata[29] <= soc_a7ddrphy_bitslip13_o[1]; - soc_a7ddrphy_dfi_p0_rddata[14] <= soc_a7ddrphy_bitslip14_o[0]; - soc_a7ddrphy_dfi_p0_rddata[30] <= soc_a7ddrphy_bitslip14_o[1]; - soc_a7ddrphy_dfi_p0_rddata[15] <= soc_a7ddrphy_bitslip15_o[0]; - soc_a7ddrphy_dfi_p0_rddata[31] <= soc_a7ddrphy_bitslip15_o[1]; -// synthesis translate_off - dummy_d_13 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_14; -// synthesis translate_on -always @(*) begin - soc_a7ddrphy_dfi_p1_rddata <= 32'd0; - soc_a7ddrphy_dfi_p1_rddata[0] <= soc_a7ddrphy_bitslip0_o[2]; - soc_a7ddrphy_dfi_p1_rddata[16] <= soc_a7ddrphy_bitslip0_o[3]; - soc_a7ddrphy_dfi_p1_rddata[1] <= soc_a7ddrphy_bitslip1_o[2]; - soc_a7ddrphy_dfi_p1_rddata[17] <= soc_a7ddrphy_bitslip1_o[3]; - soc_a7ddrphy_dfi_p1_rddata[2] <= soc_a7ddrphy_bitslip2_o[2]; - soc_a7ddrphy_dfi_p1_rddata[18] <= soc_a7ddrphy_bitslip2_o[3]; - soc_a7ddrphy_dfi_p1_rddata[3] <= soc_a7ddrphy_bitslip3_o[2]; - soc_a7ddrphy_dfi_p1_rddata[19] <= soc_a7ddrphy_bitslip3_o[3]; - soc_a7ddrphy_dfi_p1_rddata[4] <= soc_a7ddrphy_bitslip4_o[2]; - soc_a7ddrphy_dfi_p1_rddata[20] <= soc_a7ddrphy_bitslip4_o[3]; - soc_a7ddrphy_dfi_p1_rddata[5] <= soc_a7ddrphy_bitslip5_o[2]; - soc_a7ddrphy_dfi_p1_rddata[21] <= soc_a7ddrphy_bitslip5_o[3]; - soc_a7ddrphy_dfi_p1_rddata[6] <= soc_a7ddrphy_bitslip6_o[2]; - soc_a7ddrphy_dfi_p1_rddata[22] <= soc_a7ddrphy_bitslip6_o[3]; - soc_a7ddrphy_dfi_p1_rddata[7] <= soc_a7ddrphy_bitslip7_o[2]; - soc_a7ddrphy_dfi_p1_rddata[23] <= soc_a7ddrphy_bitslip7_o[3]; - soc_a7ddrphy_dfi_p1_rddata[8] <= soc_a7ddrphy_bitslip8_o[2]; - soc_a7ddrphy_dfi_p1_rddata[24] <= soc_a7ddrphy_bitslip8_o[3]; - soc_a7ddrphy_dfi_p1_rddata[9] <= soc_a7ddrphy_bitslip9_o[2]; - soc_a7ddrphy_dfi_p1_rddata[25] <= soc_a7ddrphy_bitslip9_o[3]; - soc_a7ddrphy_dfi_p1_rddata[10] <= soc_a7ddrphy_bitslip10_o[2]; - soc_a7ddrphy_dfi_p1_rddata[26] <= soc_a7ddrphy_bitslip10_o[3]; - soc_a7ddrphy_dfi_p1_rddata[11] <= soc_a7ddrphy_bitslip11_o[2]; - soc_a7ddrphy_dfi_p1_rddata[27] <= soc_a7ddrphy_bitslip11_o[3]; - soc_a7ddrphy_dfi_p1_rddata[12] <= soc_a7ddrphy_bitslip12_o[2]; - soc_a7ddrphy_dfi_p1_rddata[28] <= soc_a7ddrphy_bitslip12_o[3]; - soc_a7ddrphy_dfi_p1_rddata[13] <= soc_a7ddrphy_bitslip13_o[2]; - soc_a7ddrphy_dfi_p1_rddata[29] <= soc_a7ddrphy_bitslip13_o[3]; - soc_a7ddrphy_dfi_p1_rddata[14] <= soc_a7ddrphy_bitslip14_o[2]; - soc_a7ddrphy_dfi_p1_rddata[30] <= soc_a7ddrphy_bitslip14_o[3]; - soc_a7ddrphy_dfi_p1_rddata[15] <= soc_a7ddrphy_bitslip15_o[2]; - soc_a7ddrphy_dfi_p1_rddata[31] <= soc_a7ddrphy_bitslip15_o[3]; -// synthesis translate_off - dummy_d_14 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_15; -// synthesis translate_on -always @(*) begin - soc_a7ddrphy_dfi_p2_rddata <= 32'd0; - soc_a7ddrphy_dfi_p2_rddata[0] <= soc_a7ddrphy_bitslip0_o[4]; - soc_a7ddrphy_dfi_p2_rddata[16] <= soc_a7ddrphy_bitslip0_o[5]; - soc_a7ddrphy_dfi_p2_rddata[1] <= soc_a7ddrphy_bitslip1_o[4]; - soc_a7ddrphy_dfi_p2_rddata[17] <= soc_a7ddrphy_bitslip1_o[5]; - soc_a7ddrphy_dfi_p2_rddata[2] <= soc_a7ddrphy_bitslip2_o[4]; - soc_a7ddrphy_dfi_p2_rddata[18] <= soc_a7ddrphy_bitslip2_o[5]; - soc_a7ddrphy_dfi_p2_rddata[3] <= soc_a7ddrphy_bitslip3_o[4]; - soc_a7ddrphy_dfi_p2_rddata[19] <= soc_a7ddrphy_bitslip3_o[5]; - soc_a7ddrphy_dfi_p2_rddata[4] <= soc_a7ddrphy_bitslip4_o[4]; - soc_a7ddrphy_dfi_p2_rddata[20] <= soc_a7ddrphy_bitslip4_o[5]; - soc_a7ddrphy_dfi_p2_rddata[5] <= soc_a7ddrphy_bitslip5_o[4]; - soc_a7ddrphy_dfi_p2_rddata[21] <= soc_a7ddrphy_bitslip5_o[5]; - soc_a7ddrphy_dfi_p2_rddata[6] <= soc_a7ddrphy_bitslip6_o[4]; - soc_a7ddrphy_dfi_p2_rddata[22] <= soc_a7ddrphy_bitslip6_o[5]; - soc_a7ddrphy_dfi_p2_rddata[7] <= soc_a7ddrphy_bitslip7_o[4]; - soc_a7ddrphy_dfi_p2_rddata[23] <= soc_a7ddrphy_bitslip7_o[5]; - soc_a7ddrphy_dfi_p2_rddata[8] <= soc_a7ddrphy_bitslip8_o[4]; - soc_a7ddrphy_dfi_p2_rddata[24] <= soc_a7ddrphy_bitslip8_o[5]; - soc_a7ddrphy_dfi_p2_rddata[9] <= soc_a7ddrphy_bitslip9_o[4]; - soc_a7ddrphy_dfi_p2_rddata[25] <= soc_a7ddrphy_bitslip9_o[5]; - soc_a7ddrphy_dfi_p2_rddata[10] <= soc_a7ddrphy_bitslip10_o[4]; - soc_a7ddrphy_dfi_p2_rddata[26] <= soc_a7ddrphy_bitslip10_o[5]; - soc_a7ddrphy_dfi_p2_rddata[11] <= soc_a7ddrphy_bitslip11_o[4]; - soc_a7ddrphy_dfi_p2_rddata[27] <= soc_a7ddrphy_bitslip11_o[5]; - soc_a7ddrphy_dfi_p2_rddata[12] <= soc_a7ddrphy_bitslip12_o[4]; - soc_a7ddrphy_dfi_p2_rddata[28] <= soc_a7ddrphy_bitslip12_o[5]; - soc_a7ddrphy_dfi_p2_rddata[13] <= soc_a7ddrphy_bitslip13_o[4]; - soc_a7ddrphy_dfi_p2_rddata[29] <= soc_a7ddrphy_bitslip13_o[5]; - soc_a7ddrphy_dfi_p2_rddata[14] <= soc_a7ddrphy_bitslip14_o[4]; - soc_a7ddrphy_dfi_p2_rddata[30] <= soc_a7ddrphy_bitslip14_o[5]; - soc_a7ddrphy_dfi_p2_rddata[15] <= soc_a7ddrphy_bitslip15_o[4]; - soc_a7ddrphy_dfi_p2_rddata[31] <= soc_a7ddrphy_bitslip15_o[5]; -// synthesis translate_off - dummy_d_15 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_16; -// synthesis translate_on -always @(*) begin - soc_a7ddrphy_dfi_p3_rddata <= 32'd0; - soc_a7ddrphy_dfi_p3_rddata[0] <= soc_a7ddrphy_bitslip0_o[6]; - soc_a7ddrphy_dfi_p3_rddata[16] <= soc_a7ddrphy_bitslip0_o[7]; - soc_a7ddrphy_dfi_p3_rddata[1] <= soc_a7ddrphy_bitslip1_o[6]; - soc_a7ddrphy_dfi_p3_rddata[17] <= soc_a7ddrphy_bitslip1_o[7]; - soc_a7ddrphy_dfi_p3_rddata[2] <= soc_a7ddrphy_bitslip2_o[6]; - soc_a7ddrphy_dfi_p3_rddata[18] <= soc_a7ddrphy_bitslip2_o[7]; - soc_a7ddrphy_dfi_p3_rddata[3] <= soc_a7ddrphy_bitslip3_o[6]; - soc_a7ddrphy_dfi_p3_rddata[19] <= soc_a7ddrphy_bitslip3_o[7]; - soc_a7ddrphy_dfi_p3_rddata[4] <= soc_a7ddrphy_bitslip4_o[6]; - soc_a7ddrphy_dfi_p3_rddata[20] <= soc_a7ddrphy_bitslip4_o[7]; - soc_a7ddrphy_dfi_p3_rddata[5] <= soc_a7ddrphy_bitslip5_o[6]; - soc_a7ddrphy_dfi_p3_rddata[21] <= soc_a7ddrphy_bitslip5_o[7]; - soc_a7ddrphy_dfi_p3_rddata[6] <= soc_a7ddrphy_bitslip6_o[6]; - soc_a7ddrphy_dfi_p3_rddata[22] <= soc_a7ddrphy_bitslip6_o[7]; - soc_a7ddrphy_dfi_p3_rddata[7] <= soc_a7ddrphy_bitslip7_o[6]; - soc_a7ddrphy_dfi_p3_rddata[23] <= soc_a7ddrphy_bitslip7_o[7]; - soc_a7ddrphy_dfi_p3_rddata[8] <= soc_a7ddrphy_bitslip8_o[6]; - soc_a7ddrphy_dfi_p3_rddata[24] <= soc_a7ddrphy_bitslip8_o[7]; - soc_a7ddrphy_dfi_p3_rddata[9] <= soc_a7ddrphy_bitslip9_o[6]; - soc_a7ddrphy_dfi_p3_rddata[25] <= soc_a7ddrphy_bitslip9_o[7]; - soc_a7ddrphy_dfi_p3_rddata[10] <= soc_a7ddrphy_bitslip10_o[6]; - soc_a7ddrphy_dfi_p3_rddata[26] <= soc_a7ddrphy_bitslip10_o[7]; - soc_a7ddrphy_dfi_p3_rddata[11] <= soc_a7ddrphy_bitslip11_o[6]; - soc_a7ddrphy_dfi_p3_rddata[27] <= soc_a7ddrphy_bitslip11_o[7]; - soc_a7ddrphy_dfi_p3_rddata[12] <= soc_a7ddrphy_bitslip12_o[6]; - soc_a7ddrphy_dfi_p3_rddata[28] <= soc_a7ddrphy_bitslip12_o[7]; - soc_a7ddrphy_dfi_p3_rddata[13] <= soc_a7ddrphy_bitslip13_o[6]; - soc_a7ddrphy_dfi_p3_rddata[29] <= soc_a7ddrphy_bitslip13_o[7]; - soc_a7ddrphy_dfi_p3_rddata[14] <= soc_a7ddrphy_bitslip14_o[6]; - soc_a7ddrphy_dfi_p3_rddata[30] <= soc_a7ddrphy_bitslip14_o[7]; - soc_a7ddrphy_dfi_p3_rddata[15] <= soc_a7ddrphy_bitslip15_o[6]; - soc_a7ddrphy_dfi_p3_rddata[31] <= soc_a7ddrphy_bitslip15_o[7]; -// synthesis translate_off - dummy_d_16 = dummy_s; -// synthesis translate_on -end -assign soc_a7ddrphy_bitslip1_i = soc_a7ddrphy_dq_i_data1; -assign soc_a7ddrphy_bitslip2_i = soc_a7ddrphy_dq_i_data2; -assign soc_a7ddrphy_bitslip3_i = soc_a7ddrphy_dq_i_data3; -assign soc_a7ddrphy_bitslip4_i = soc_a7ddrphy_dq_i_data4; -assign soc_a7ddrphy_bitslip5_i = soc_a7ddrphy_dq_i_data5; -assign soc_a7ddrphy_bitslip6_i = soc_a7ddrphy_dq_i_data6; -assign soc_a7ddrphy_bitslip7_i = soc_a7ddrphy_dq_i_data7; -assign soc_a7ddrphy_bitslip8_i = soc_a7ddrphy_dq_i_data8; -assign soc_a7ddrphy_bitslip9_i = soc_a7ddrphy_dq_i_data9; -assign soc_a7ddrphy_bitslip10_i = soc_a7ddrphy_dq_i_data10; -assign soc_a7ddrphy_bitslip11_i = soc_a7ddrphy_dq_i_data11; -assign soc_a7ddrphy_bitslip12_i = soc_a7ddrphy_dq_i_data12; -assign soc_a7ddrphy_bitslip13_i = soc_a7ddrphy_dq_i_data13; -assign soc_a7ddrphy_bitslip14_i = soc_a7ddrphy_dq_i_data14; -assign soc_a7ddrphy_bitslip15_i = soc_a7ddrphy_dq_i_data15; -assign soc_a7ddrphy_rddata_en = {soc_a7ddrphy_rddata_en_last, soc_a7ddrphy_dfi_p2_rddata_en}; -assign soc_a7ddrphy_wrdata_en = {soc_a7ddrphy_wrdata_en_last, soc_a7ddrphy_dfi_p3_wrdata_en}; -assign soc_a7ddrphy_dq_oe = soc_a7ddrphy_wrdata_en[2]; - -// synthesis translate_off -reg dummy_d_17; -// synthesis translate_on -always @(*) begin - soc_a7ddrphy_dqs_oe <= 1'd0; - if (soc_a7ddrphy_wlevel_en_storage) begin - soc_a7ddrphy_dqs_oe <= 1'd1; + a7ddrphy_dqs_oe <= 1'd0; + if (a7ddrphy_wlevel_en_storage) begin + a7ddrphy_dqs_oe <= 1'd1; end else begin - soc_a7ddrphy_dqs_oe <= soc_a7ddrphy_dq_oe; + a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; end // synthesis translate_off - dummy_d_17 = dummy_s; + dummy_d_4 = dummy_s; // synthesis translate_on end -assign soc_a7ddrphy_dqspattern0 = (soc_a7ddrphy_wrdata_en[1] & (~soc_a7ddrphy_wrdata_en[2])); -assign soc_a7ddrphy_dqspattern1 = (soc_a7ddrphy_wrdata_en[3] & (~soc_a7ddrphy_wrdata_en[2])); +assign a7ddrphy_dqspattern0 = (a7ddrphy_wrdata_en[1] & (~a7ddrphy_wrdata_en[2])); +assign a7ddrphy_dqspattern1 = (a7ddrphy_wrdata_en[3] & (~a7ddrphy_wrdata_en[2])); // synthesis translate_off -reg dummy_d_18; +reg dummy_d_5; // synthesis translate_on always @(*) begin - soc_a7ddrphy_dqspattern_o0 <= 8'd0; - soc_a7ddrphy_dqspattern_o0 <= 7'd85; - if (soc_a7ddrphy_dqspattern0) begin - soc_a7ddrphy_dqspattern_o0 <= 5'd21; + a7ddrphy_dqspattern_o0 <= 8'd0; + a7ddrphy_dqspattern_o0 <= 7'd85; + if (a7ddrphy_dqspattern0) begin + a7ddrphy_dqspattern_o0 <= 5'd21; end - if (soc_a7ddrphy_dqspattern1) begin - soc_a7ddrphy_dqspattern_o0 <= 7'd84; + if (a7ddrphy_dqspattern1) begin + a7ddrphy_dqspattern_o0 <= 7'd84; end - if (soc_a7ddrphy_wlevel_en_storage) begin - soc_a7ddrphy_dqspattern_o0 <= 1'd0; - if (soc_a7ddrphy_wlevel_strobe_re) begin - soc_a7ddrphy_dqspattern_o0 <= 1'd1; + if (a7ddrphy_wlevel_en_storage) begin + a7ddrphy_dqspattern_o0 <= 1'd0; + if (a7ddrphy_wlevel_strobe_re) begin + a7ddrphy_dqspattern_o0 <= 1'd1; end end // synthesis translate_off - dummy_d_18 = dummy_s; + dummy_d_5 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_19; +reg dummy_d_6; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip0_o <= 8'd0; - case (soc_a7ddrphy_bitslip0_value) + a7ddrphy_bitslip0_o <= 8'd0; + case (a7ddrphy_bitslip0_value) 1'd0: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[7:0]; + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[8:1]; + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[9:2]; + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[10:3]; + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[11:4]; + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[12:5]; + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[13:6]; + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[14:7]; + a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[14:7]; end endcase // synthesis translate_off - dummy_d_19 = dummy_s; + dummy_d_6 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_20; +reg dummy_d_7; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip1_o <= 8'd0; - case (soc_a7ddrphy_bitslip1_value) + a7ddrphy_bitslip1_o <= 8'd0; + case (a7ddrphy_bitslip1_value) 1'd0: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[7:0]; + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[8:1]; + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[9:2]; + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[10:3]; + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[11:4]; + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[12:5]; + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[13:6]; + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[14:7]; + a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[14:7]; end endcase // synthesis translate_off - dummy_d_20 = dummy_s; + dummy_d_7 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_21; +reg dummy_d_8; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip2_o <= 8'd0; - case (soc_a7ddrphy_bitslip2_value) + a7ddrphy_bitslip2_o <= 8'd0; + case (a7ddrphy_bitslip2_value) 1'd0: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[7:0]; + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[8:1]; + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[9:2]; + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[10:3]; + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[11:4]; + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[12:5]; + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[13:6]; + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[14:7]; + a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[14:7]; end endcase // synthesis translate_off - dummy_d_21 = dummy_s; + dummy_d_8 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_22; +reg dummy_d_9; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip3_o <= 8'd0; - case (soc_a7ddrphy_bitslip3_value) + a7ddrphy_bitslip3_o <= 8'd0; + case (a7ddrphy_bitslip3_value) 1'd0: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[7:0]; + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[8:1]; + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[9:2]; + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[10:3]; + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[11:4]; + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[12:5]; + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[13:6]; + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[14:7]; + a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[14:7]; end endcase // synthesis translate_off - dummy_d_22 = dummy_s; + dummy_d_9 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_23; +reg dummy_d_10; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip4_o <= 8'd0; - case (soc_a7ddrphy_bitslip4_value) + a7ddrphy_bitslip4_o <= 8'd0; + case (a7ddrphy_bitslip4_value) 1'd0: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[7:0]; + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[8:1]; + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[9:2]; + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[10:3]; + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[11:4]; + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[12:5]; + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[13:6]; + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[14:7]; + a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[14:7]; end endcase // synthesis translate_off - dummy_d_23 = dummy_s; + dummy_d_10 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_24; +reg dummy_d_11; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip5_o <= 8'd0; - case (soc_a7ddrphy_bitslip5_value) + a7ddrphy_bitslip5_o <= 8'd0; + case (a7ddrphy_bitslip5_value) 1'd0: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[7:0]; + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[8:1]; + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[9:2]; + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[10:3]; + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[11:4]; + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[12:5]; + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[13:6]; + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[14:7]; + a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[14:7]; end endcase // synthesis translate_off - dummy_d_24 = dummy_s; + dummy_d_11 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_25; +reg dummy_d_12; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip6_o <= 8'd0; - case (soc_a7ddrphy_bitslip6_value) + a7ddrphy_bitslip6_o <= 8'd0; + case (a7ddrphy_bitslip6_value) 1'd0: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[7:0]; + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[8:1]; + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[9:2]; + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[10:3]; + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[11:4]; + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[12:5]; + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[13:6]; + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[14:7]; + a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[14:7]; end endcase // synthesis translate_off - dummy_d_25 = dummy_s; + dummy_d_12 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_26; +reg dummy_d_13; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip7_o <= 8'd0; - case (soc_a7ddrphy_bitslip7_value) + a7ddrphy_bitslip7_o <= 8'd0; + case (a7ddrphy_bitslip7_value) 1'd0: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[7:0]; + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[8:1]; + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[9:2]; + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[10:3]; + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[11:4]; + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[12:5]; + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[13:6]; + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[14:7]; + a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[14:7]; end endcase // synthesis translate_off - dummy_d_26 = dummy_s; + dummy_d_13 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_27; +reg dummy_d_14; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip8_o <= 8'd0; - case (soc_a7ddrphy_bitslip8_value) + a7ddrphy_bitslip8_o <= 8'd0; + case (a7ddrphy_bitslip8_value) 1'd0: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[7:0]; + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[8:1]; + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[9:2]; + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[10:3]; + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[11:4]; + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[12:5]; + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[13:6]; + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[14:7]; + a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[14:7]; end endcase // synthesis translate_off - dummy_d_27 = dummy_s; + dummy_d_14 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_28; +reg dummy_d_15; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip9_o <= 8'd0; - case (soc_a7ddrphy_bitslip9_value) + a7ddrphy_bitslip9_o <= 8'd0; + case (a7ddrphy_bitslip9_value) 1'd0: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[7:0]; + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[8:1]; + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[9:2]; + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[10:3]; + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[11:4]; + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[12:5]; + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[13:6]; + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[14:7]; + a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[14:7]; end endcase // synthesis translate_off - dummy_d_28 = dummy_s; + dummy_d_15 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_29; +reg dummy_d_16; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip10_o <= 8'd0; - case (soc_a7ddrphy_bitslip10_value) + a7ddrphy_bitslip10_o <= 8'd0; + case (a7ddrphy_bitslip10_value) 1'd0: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[7:0]; + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[8:1]; + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[9:2]; + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[10:3]; + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[11:4]; + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[12:5]; + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[13:6]; + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[14:7]; + a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[14:7]; end endcase // synthesis translate_off - dummy_d_29 = dummy_s; + dummy_d_16 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_30; +reg dummy_d_17; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip11_o <= 8'd0; - case (soc_a7ddrphy_bitslip11_value) + a7ddrphy_bitslip11_o <= 8'd0; + case (a7ddrphy_bitslip11_value) 1'd0: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[7:0]; + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[8:1]; + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[9:2]; + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[10:3]; + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[11:4]; + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[12:5]; + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[13:6]; + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[14:7]; + a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[14:7]; end endcase // synthesis translate_off - dummy_d_30 = dummy_s; + dummy_d_17 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_31; +reg dummy_d_18; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip12_o <= 8'd0; - case (soc_a7ddrphy_bitslip12_value) + a7ddrphy_bitslip12_o <= 8'd0; + case (a7ddrphy_bitslip12_value) 1'd0: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[7:0]; + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[8:1]; + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[9:2]; + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[10:3]; + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[11:4]; + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[12:5]; + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[13:6]; + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[14:7]; + a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[14:7]; end endcase // synthesis translate_off - dummy_d_31 = dummy_s; + dummy_d_18 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_32; +reg dummy_d_19; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip13_o <= 8'd0; - case (soc_a7ddrphy_bitslip13_value) + a7ddrphy_bitslip13_o <= 8'd0; + case (a7ddrphy_bitslip13_value) 1'd0: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[7:0]; + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[8:1]; + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[9:2]; + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[10:3]; + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[11:4]; + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[12:5]; + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[13:6]; + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[14:7]; + a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[14:7]; end endcase // synthesis translate_off - dummy_d_32 = dummy_s; + dummy_d_19 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_33; +reg dummy_d_20; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip14_o <= 8'd0; - case (soc_a7ddrphy_bitslip14_value) + a7ddrphy_bitslip14_o <= 8'd0; + case (a7ddrphy_bitslip14_value) 1'd0: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[7:0]; + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[8:1]; + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[9:2]; + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[10:3]; + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[11:4]; + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[12:5]; + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[13:6]; + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[14:7]; + a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[14:7]; end endcase // synthesis translate_off - dummy_d_33 = dummy_s; + dummy_d_20 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_34; +reg dummy_d_21; // synthesis translate_on always @(*) begin - soc_a7ddrphy_bitslip15_o <= 8'd0; - case (soc_a7ddrphy_bitslip15_value) + a7ddrphy_bitslip15_o <= 8'd0; + case (a7ddrphy_bitslip15_value) 1'd0: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[7:0]; + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[7:0]; end 1'd1: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[8:1]; + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[8:1]; end 2'd2: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[9:2]; + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[9:2]; end 2'd3: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[10:3]; + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[10:3]; end 3'd4: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[11:4]; + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[11:4]; end 3'd5: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[12:5]; + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[12:5]; end 3'd6: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[13:6]; + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[13:6]; end 3'd7: begin - soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[14:7]; + a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[14:7]; end endcase // synthesis translate_off - dummy_d_34 = dummy_s; + dummy_d_21 = dummy_s; // synthesis translate_on end -assign soc_a7ddrphy_dfi_p0_address = soc_sdram_master_p0_address; -assign soc_a7ddrphy_dfi_p0_bank = soc_sdram_master_p0_bank; -assign soc_a7ddrphy_dfi_p0_cas_n = soc_sdram_master_p0_cas_n; -assign soc_a7ddrphy_dfi_p0_cs_n = soc_sdram_master_p0_cs_n; -assign soc_a7ddrphy_dfi_p0_ras_n = soc_sdram_master_p0_ras_n; -assign soc_a7ddrphy_dfi_p0_we_n = soc_sdram_master_p0_we_n; -assign soc_a7ddrphy_dfi_p0_cke = soc_sdram_master_p0_cke; -assign soc_a7ddrphy_dfi_p0_odt = soc_sdram_master_p0_odt; -assign soc_a7ddrphy_dfi_p0_reset_n = soc_sdram_master_p0_reset_n; -assign soc_a7ddrphy_dfi_p0_act_n = soc_sdram_master_p0_act_n; -assign soc_a7ddrphy_dfi_p0_wrdata = soc_sdram_master_p0_wrdata; -assign soc_a7ddrphy_dfi_p0_wrdata_en = soc_sdram_master_p0_wrdata_en; -assign soc_a7ddrphy_dfi_p0_wrdata_mask = soc_sdram_master_p0_wrdata_mask; -assign soc_a7ddrphy_dfi_p0_rddata_en = soc_sdram_master_p0_rddata_en; -assign soc_sdram_master_p0_rddata = soc_a7ddrphy_dfi_p0_rddata; -assign soc_sdram_master_p0_rddata_valid = soc_a7ddrphy_dfi_p0_rddata_valid; -assign soc_a7ddrphy_dfi_p1_address = soc_sdram_master_p1_address; -assign soc_a7ddrphy_dfi_p1_bank = soc_sdram_master_p1_bank; -assign soc_a7ddrphy_dfi_p1_cas_n = soc_sdram_master_p1_cas_n; -assign soc_a7ddrphy_dfi_p1_cs_n = soc_sdram_master_p1_cs_n; -assign soc_a7ddrphy_dfi_p1_ras_n = soc_sdram_master_p1_ras_n; -assign soc_a7ddrphy_dfi_p1_we_n = soc_sdram_master_p1_we_n; -assign soc_a7ddrphy_dfi_p1_cke = soc_sdram_master_p1_cke; -assign soc_a7ddrphy_dfi_p1_odt = soc_sdram_master_p1_odt; -assign soc_a7ddrphy_dfi_p1_reset_n = soc_sdram_master_p1_reset_n; -assign soc_a7ddrphy_dfi_p1_act_n = soc_sdram_master_p1_act_n; -assign soc_a7ddrphy_dfi_p1_wrdata = soc_sdram_master_p1_wrdata; -assign soc_a7ddrphy_dfi_p1_wrdata_en = soc_sdram_master_p1_wrdata_en; -assign soc_a7ddrphy_dfi_p1_wrdata_mask = soc_sdram_master_p1_wrdata_mask; -assign soc_a7ddrphy_dfi_p1_rddata_en = soc_sdram_master_p1_rddata_en; -assign soc_sdram_master_p1_rddata = soc_a7ddrphy_dfi_p1_rddata; -assign soc_sdram_master_p1_rddata_valid = soc_a7ddrphy_dfi_p1_rddata_valid; -assign soc_a7ddrphy_dfi_p2_address = soc_sdram_master_p2_address; -assign soc_a7ddrphy_dfi_p2_bank = soc_sdram_master_p2_bank; -assign soc_a7ddrphy_dfi_p2_cas_n = soc_sdram_master_p2_cas_n; -assign soc_a7ddrphy_dfi_p2_cs_n = soc_sdram_master_p2_cs_n; -assign soc_a7ddrphy_dfi_p2_ras_n = soc_sdram_master_p2_ras_n; -assign soc_a7ddrphy_dfi_p2_we_n = soc_sdram_master_p2_we_n; -assign soc_a7ddrphy_dfi_p2_cke = soc_sdram_master_p2_cke; -assign soc_a7ddrphy_dfi_p2_odt = soc_sdram_master_p2_odt; -assign soc_a7ddrphy_dfi_p2_reset_n = soc_sdram_master_p2_reset_n; -assign soc_a7ddrphy_dfi_p2_act_n = soc_sdram_master_p2_act_n; -assign soc_a7ddrphy_dfi_p2_wrdata = soc_sdram_master_p2_wrdata; -assign soc_a7ddrphy_dfi_p2_wrdata_en = soc_sdram_master_p2_wrdata_en; -assign soc_a7ddrphy_dfi_p2_wrdata_mask = soc_sdram_master_p2_wrdata_mask; -assign soc_a7ddrphy_dfi_p2_rddata_en = soc_sdram_master_p2_rddata_en; -assign soc_sdram_master_p2_rddata = soc_a7ddrphy_dfi_p2_rddata; -assign soc_sdram_master_p2_rddata_valid = soc_a7ddrphy_dfi_p2_rddata_valid; -assign soc_a7ddrphy_dfi_p3_address = soc_sdram_master_p3_address; -assign soc_a7ddrphy_dfi_p3_bank = soc_sdram_master_p3_bank; -assign soc_a7ddrphy_dfi_p3_cas_n = soc_sdram_master_p3_cas_n; -assign soc_a7ddrphy_dfi_p3_cs_n = soc_sdram_master_p3_cs_n; -assign soc_a7ddrphy_dfi_p3_ras_n = soc_sdram_master_p3_ras_n; -assign soc_a7ddrphy_dfi_p3_we_n = soc_sdram_master_p3_we_n; -assign soc_a7ddrphy_dfi_p3_cke = soc_sdram_master_p3_cke; -assign soc_a7ddrphy_dfi_p3_odt = soc_sdram_master_p3_odt; -assign soc_a7ddrphy_dfi_p3_reset_n = soc_sdram_master_p3_reset_n; -assign soc_a7ddrphy_dfi_p3_act_n = soc_sdram_master_p3_act_n; -assign soc_a7ddrphy_dfi_p3_wrdata = soc_sdram_master_p3_wrdata; -assign soc_a7ddrphy_dfi_p3_wrdata_en = soc_sdram_master_p3_wrdata_en; -assign soc_a7ddrphy_dfi_p3_wrdata_mask = soc_sdram_master_p3_wrdata_mask; -assign soc_a7ddrphy_dfi_p3_rddata_en = soc_sdram_master_p3_rddata_en; -assign soc_sdram_master_p3_rddata = soc_a7ddrphy_dfi_p3_rddata; -assign soc_sdram_master_p3_rddata_valid = soc_a7ddrphy_dfi_p3_rddata_valid; -assign soc_sdram_slave_p0_address = soc_sdram_dfi_p0_address; -assign soc_sdram_slave_p0_bank = soc_sdram_dfi_p0_bank; -assign soc_sdram_slave_p0_cas_n = soc_sdram_dfi_p0_cas_n; -assign soc_sdram_slave_p0_cs_n = soc_sdram_dfi_p0_cs_n; -assign soc_sdram_slave_p0_ras_n = soc_sdram_dfi_p0_ras_n; -assign soc_sdram_slave_p0_we_n = soc_sdram_dfi_p0_we_n; -assign soc_sdram_slave_p0_cke = soc_sdram_dfi_p0_cke; -assign soc_sdram_slave_p0_odt = soc_sdram_dfi_p0_odt; -assign soc_sdram_slave_p0_reset_n = soc_sdram_dfi_p0_reset_n; -assign soc_sdram_slave_p0_act_n = soc_sdram_dfi_p0_act_n; -assign soc_sdram_slave_p0_wrdata = soc_sdram_dfi_p0_wrdata; -assign soc_sdram_slave_p0_wrdata_en = soc_sdram_dfi_p0_wrdata_en; -assign soc_sdram_slave_p0_wrdata_mask = soc_sdram_dfi_p0_wrdata_mask; -assign soc_sdram_slave_p0_rddata_en = soc_sdram_dfi_p0_rddata_en; -assign soc_sdram_dfi_p0_rddata = soc_sdram_slave_p0_rddata; -assign soc_sdram_dfi_p0_rddata_valid = soc_sdram_slave_p0_rddata_valid; -assign soc_sdram_slave_p1_address = soc_sdram_dfi_p1_address; -assign soc_sdram_slave_p1_bank = soc_sdram_dfi_p1_bank; -assign soc_sdram_slave_p1_cas_n = soc_sdram_dfi_p1_cas_n; -assign soc_sdram_slave_p1_cs_n = soc_sdram_dfi_p1_cs_n; -assign soc_sdram_slave_p1_ras_n = soc_sdram_dfi_p1_ras_n; -assign soc_sdram_slave_p1_we_n = soc_sdram_dfi_p1_we_n; -assign soc_sdram_slave_p1_cke = soc_sdram_dfi_p1_cke; -assign soc_sdram_slave_p1_odt = soc_sdram_dfi_p1_odt; -assign soc_sdram_slave_p1_reset_n = soc_sdram_dfi_p1_reset_n; -assign soc_sdram_slave_p1_act_n = soc_sdram_dfi_p1_act_n; -assign soc_sdram_slave_p1_wrdata = soc_sdram_dfi_p1_wrdata; -assign soc_sdram_slave_p1_wrdata_en = soc_sdram_dfi_p1_wrdata_en; -assign soc_sdram_slave_p1_wrdata_mask = soc_sdram_dfi_p1_wrdata_mask; -assign soc_sdram_slave_p1_rddata_en = soc_sdram_dfi_p1_rddata_en; -assign soc_sdram_dfi_p1_rddata = soc_sdram_slave_p1_rddata; -assign soc_sdram_dfi_p1_rddata_valid = soc_sdram_slave_p1_rddata_valid; -assign soc_sdram_slave_p2_address = soc_sdram_dfi_p2_address; -assign soc_sdram_slave_p2_bank = soc_sdram_dfi_p2_bank; -assign soc_sdram_slave_p2_cas_n = soc_sdram_dfi_p2_cas_n; -assign soc_sdram_slave_p2_cs_n = soc_sdram_dfi_p2_cs_n; -assign soc_sdram_slave_p2_ras_n = soc_sdram_dfi_p2_ras_n; -assign soc_sdram_slave_p2_we_n = soc_sdram_dfi_p2_we_n; -assign soc_sdram_slave_p2_cke = soc_sdram_dfi_p2_cke; -assign soc_sdram_slave_p2_odt = soc_sdram_dfi_p2_odt; -assign soc_sdram_slave_p2_reset_n = soc_sdram_dfi_p2_reset_n; -assign soc_sdram_slave_p2_act_n = soc_sdram_dfi_p2_act_n; -assign soc_sdram_slave_p2_wrdata = soc_sdram_dfi_p2_wrdata; -assign soc_sdram_slave_p2_wrdata_en = soc_sdram_dfi_p2_wrdata_en; -assign soc_sdram_slave_p2_wrdata_mask = soc_sdram_dfi_p2_wrdata_mask; -assign soc_sdram_slave_p2_rddata_en = soc_sdram_dfi_p2_rddata_en; -assign soc_sdram_dfi_p2_rddata = soc_sdram_slave_p2_rddata; -assign soc_sdram_dfi_p2_rddata_valid = soc_sdram_slave_p2_rddata_valid; -assign soc_sdram_slave_p3_address = soc_sdram_dfi_p3_address; -assign soc_sdram_slave_p3_bank = soc_sdram_dfi_p3_bank; -assign soc_sdram_slave_p3_cas_n = soc_sdram_dfi_p3_cas_n; -assign soc_sdram_slave_p3_cs_n = soc_sdram_dfi_p3_cs_n; -assign soc_sdram_slave_p3_ras_n = soc_sdram_dfi_p3_ras_n; -assign soc_sdram_slave_p3_we_n = soc_sdram_dfi_p3_we_n; -assign soc_sdram_slave_p3_cke = soc_sdram_dfi_p3_cke; -assign soc_sdram_slave_p3_odt = soc_sdram_dfi_p3_odt; -assign soc_sdram_slave_p3_reset_n = soc_sdram_dfi_p3_reset_n; -assign soc_sdram_slave_p3_act_n = soc_sdram_dfi_p3_act_n; -assign soc_sdram_slave_p3_wrdata = soc_sdram_dfi_p3_wrdata; -assign soc_sdram_slave_p3_wrdata_en = soc_sdram_dfi_p3_wrdata_en; -assign soc_sdram_slave_p3_wrdata_mask = soc_sdram_dfi_p3_wrdata_mask; -assign soc_sdram_slave_p3_rddata_en = soc_sdram_dfi_p3_rddata_en; -assign soc_sdram_dfi_p3_rddata = soc_sdram_slave_p3_rddata; -assign soc_sdram_dfi_p3_rddata_valid = soc_sdram_slave_p3_rddata_valid; +assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address; +assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank; +assign a7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n; +assign a7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n; +assign a7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n; +assign a7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n; +assign a7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke; +assign a7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt; +assign a7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n; +assign a7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n; +assign a7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata; +assign a7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en; +assign a7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask; +assign a7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en; +assign litedramcore_master_p0_rddata = a7ddrphy_dfi_p0_rddata; +assign litedramcore_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid; +assign a7ddrphy_dfi_p1_address = litedramcore_master_p1_address; +assign a7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank; +assign a7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n; +assign a7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n; +assign a7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n; +assign a7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n; +assign a7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke; +assign a7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt; +assign a7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n; +assign a7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n; +assign a7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata; +assign a7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en; +assign a7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask; +assign a7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en; +assign litedramcore_master_p1_rddata = a7ddrphy_dfi_p1_rddata; +assign litedramcore_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid; +assign a7ddrphy_dfi_p2_address = litedramcore_master_p2_address; +assign a7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank; +assign a7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n; +assign a7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n; +assign a7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n; +assign a7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n; +assign a7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke; +assign a7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt; +assign a7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n; +assign a7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n; +assign a7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata; +assign a7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en; +assign a7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask; +assign a7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en; +assign litedramcore_master_p2_rddata = a7ddrphy_dfi_p2_rddata; +assign litedramcore_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid; +assign a7ddrphy_dfi_p3_address = litedramcore_master_p3_address; +assign a7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank; +assign a7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n; +assign a7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n; +assign a7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n; +assign a7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n; +assign a7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke; +assign a7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt; +assign a7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n; +assign a7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n; +assign a7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata; +assign a7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en; +assign a7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask; +assign a7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en; +assign litedramcore_master_p3_rddata = a7ddrphy_dfi_p3_rddata; +assign litedramcore_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid; +assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address; +assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank; +assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n; +assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n; +assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n; +assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n; +assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke; +assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt; +assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n; +assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n; +assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata; +assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en; +assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask; +assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en; +assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata; +assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid; +assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address; +assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank; +assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n; +assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n; +assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n; +assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n; +assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke; +assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt; +assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n; +assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n; +assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata; +assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en; +assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask; +assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en; +assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata; +assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid; +assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address; +assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank; +assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n; +assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n; +assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n; +assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n; +assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke; +assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt; +assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n; +assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n; +assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata; +assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en; +assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask; +assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en; +assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata; +assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid; +assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address; +assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank; +assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n; +assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n; +assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n; +assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n; +assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke; +assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt; +assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n; +assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n; +assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata; +assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en; +assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask; +assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en; +assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata; +assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; // synthesis translate_off -reg dummy_d_35; +reg dummy_d_22; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_cas_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_cas_n <= soc_sdram_slave_p2_cas_n; + litedramcore_master_p2_ras_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; end else begin - soc_sdram_master_p2_cas_n <= soc_sdram_inti_p2_cas_n; + litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n; end // synthesis translate_off - dummy_d_35 = dummy_s; + dummy_d_22 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_36; +reg dummy_d_23; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_cs_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_cs_n <= soc_sdram_slave_p2_cs_n; + litedramcore_slave_p2_rddata <= 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; end else begin - soc_sdram_master_p2_cs_n <= soc_sdram_inti_p2_cs_n; end // synthesis translate_off - dummy_d_36 = dummy_s; + dummy_d_23 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_37; +reg dummy_d_24; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_ras_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_ras_n <= soc_sdram_slave_p2_ras_n; + litedramcore_master_p2_we_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; end else begin - soc_sdram_master_p2_ras_n <= soc_sdram_inti_p2_ras_n; + litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; end // synthesis translate_off - dummy_d_37 = dummy_s; + dummy_d_24 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_38; +reg dummy_d_25; // synthesis translate_on always @(*) begin - soc_sdram_slave_p2_rddata <= 32'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_slave_p2_rddata <= soc_sdram_master_p2_rddata; + litedramcore_slave_p2_rddata_valid <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end else begin end // synthesis translate_off - dummy_d_38 = dummy_s; + dummy_d_25 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_39; +reg dummy_d_26; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_we_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_we_n <= soc_sdram_slave_p2_we_n; + litedramcore_master_p2_cke <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; end else begin - soc_sdram_master_p2_we_n <= soc_sdram_inti_p2_we_n; + litedramcore_master_p2_cke <= litedramcore_inti_p2_cke; end // synthesis translate_off - dummy_d_39 = dummy_s; + dummy_d_26 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_40; +reg dummy_d_27; // synthesis translate_on always @(*) begin - soc_sdram_slave_p2_rddata_valid <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_slave_p2_rddata_valid <= soc_sdram_master_p2_rddata_valid; + litedramcore_master_p2_odt <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; end else begin + litedramcore_master_p2_odt <= litedramcore_inti_p2_odt; end // synthesis translate_off - dummy_d_40 = dummy_s; + dummy_d_27 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_41; +reg dummy_d_28; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_cke <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_cke <= soc_sdram_slave_p2_cke; + litedramcore_master_p2_reset_n <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; end else begin - soc_sdram_master_p2_cke <= soc_sdram_inti_p2_cke; + litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n; end // synthesis translate_off - dummy_d_41 = dummy_s; + dummy_d_28 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_42; +reg dummy_d_29; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_odt <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_odt <= soc_sdram_slave_p2_odt; + litedramcore_master_p2_act_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; end else begin - soc_sdram_master_p2_odt <= soc_sdram_inti_p2_odt; + litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n; end // synthesis translate_off - dummy_d_42 = dummy_s; + dummy_d_29 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_43; +reg dummy_d_30; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_reset_n <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_reset_n <= soc_sdram_slave_p2_reset_n; + litedramcore_master_p2_wrdata <= 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; end else begin - soc_sdram_master_p2_reset_n <= soc_sdram_inti_p2_reset_n; + litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata; end // synthesis translate_off - dummy_d_43 = dummy_s; + dummy_d_30 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_44; +reg dummy_d_31; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_act_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_act_n <= soc_sdram_slave_p2_act_n; + litedramcore_inti_p3_rddata <= 32'd0; + if (litedramcore_storage[0]) begin end else begin - soc_sdram_master_p2_act_n <= soc_sdram_inti_p2_act_n; + litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata; end // synthesis translate_off - dummy_d_44 = dummy_s; + dummy_d_31 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_32; +// synthesis translate_on +always @(*) begin + litedramcore_master_p2_wrdata_en <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; + end else begin + litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en; + end +// synthesis translate_off + dummy_d_32 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_33; +// synthesis translate_on +always @(*) begin + litedramcore_inti_p3_rddata_valid <= 1'd0; + if (litedramcore_storage[0]) begin + end else begin + litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + end +// synthesis translate_off + dummy_d_33 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_34; +// synthesis translate_on +always @(*) begin + litedramcore_master_p2_wrdata_mask <= 4'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; + end else begin + litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask; + end +// synthesis translate_off + dummy_d_34 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_35; +// synthesis translate_on +always @(*) begin + litedramcore_master_p2_rddata_en <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; + end else begin + litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en; + end +// synthesis translate_off + dummy_d_35 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_36; +// synthesis translate_on +always @(*) begin + litedramcore_master_p3_address <= 15'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_address <= litedramcore_slave_p3_address; + end else begin + litedramcore_master_p3_address <= litedramcore_inti_p3_address; + end +// synthesis translate_off + dummy_d_36 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_37; +// synthesis translate_on +always @(*) begin + litedramcore_master_p3_bank <= 3'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; + end else begin + litedramcore_master_p3_bank <= litedramcore_inti_p3_bank; + end +// synthesis translate_off + dummy_d_37 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_38; +// synthesis translate_on +always @(*) begin + litedramcore_master_p3_cas_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; + end else begin + litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n; + end +// synthesis translate_off + dummy_d_38 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_39; +// synthesis translate_on +always @(*) begin + litedramcore_master_p3_cs_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; + end else begin + litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n; + end +// synthesis translate_off + dummy_d_39 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_40; +// synthesis translate_on +always @(*) begin + litedramcore_master_p3_ras_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; + end else begin + litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n; + end +// synthesis translate_off + dummy_d_40 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_41; +// synthesis translate_on +always @(*) begin + litedramcore_slave_p3_rddata <= 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; + end else begin + end +// synthesis translate_off + dummy_d_41 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_42; +// synthesis translate_on +always @(*) begin + litedramcore_master_p3_we_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; + end else begin + litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n; + end +// synthesis translate_off + dummy_d_42 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_43; +// synthesis translate_on +always @(*) begin + litedramcore_slave_p3_rddata_valid <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + end else begin + end +// synthesis translate_off + dummy_d_43 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_44; +// synthesis translate_on +always @(*) begin + litedramcore_master_p3_cke <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; + end else begin + litedramcore_master_p3_cke <= litedramcore_inti_p3_cke; + end +// synthesis translate_off + dummy_d_44 = dummy_s; // synthesis translate_on end @@ -3865,11 +3187,11 @@ end reg dummy_d_45; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_wrdata <= 32'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_wrdata <= soc_sdram_slave_p2_wrdata; + litedramcore_master_p3_odt <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; end else begin - soc_sdram_master_p2_wrdata <= soc_sdram_inti_p2_wrdata; + litedramcore_master_p3_odt <= litedramcore_inti_p3_odt; end // synthesis translate_off dummy_d_45 = dummy_s; @@ -3880,10 +3202,11 @@ end reg dummy_d_46; // synthesis translate_on always @(*) begin - soc_sdram_inti_p3_rddata <= 32'd0; - if (soc_sdram_storage[0]) begin + litedramcore_master_p3_reset_n <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; end else begin - soc_sdram_inti_p3_rddata <= soc_sdram_master_p3_rddata; + litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n; end // synthesis translate_off dummy_d_46 = dummy_s; @@ -3894,11 +3217,11 @@ end reg dummy_d_47; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_wrdata_en <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_wrdata_en <= soc_sdram_slave_p2_wrdata_en; + litedramcore_master_p3_act_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; end else begin - soc_sdram_master_p2_wrdata_en <= soc_sdram_inti_p2_wrdata_en; + litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n; end // synthesis translate_off dummy_d_47 = dummy_s; @@ -3909,10 +3232,11 @@ end reg dummy_d_48; // synthesis translate_on always @(*) begin - soc_sdram_inti_p3_rddata_valid <= 1'd0; - if (soc_sdram_storage[0]) begin + litedramcore_master_p3_wrdata <= 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; end else begin - soc_sdram_inti_p3_rddata_valid <= soc_sdram_master_p3_rddata_valid; + litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata; end // synthesis translate_off dummy_d_48 = dummy_s; @@ -3923,11 +3247,10 @@ end reg dummy_d_49; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_wrdata_mask <= 4'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_wrdata_mask <= soc_sdram_slave_p2_wrdata_mask; + litedramcore_inti_p0_rddata <= 32'd0; + if (litedramcore_storage[0]) begin end else begin - soc_sdram_master_p2_wrdata_mask <= soc_sdram_inti_p2_wrdata_mask; + litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata; end // synthesis translate_off dummy_d_49 = dummy_s; @@ -3938,11 +3261,11 @@ end reg dummy_d_50; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_rddata_en <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_rddata_en <= soc_sdram_slave_p2_rddata_en; + litedramcore_master_p3_wrdata_en <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; end else begin - soc_sdram_master_p2_rddata_en <= soc_sdram_inti_p2_rddata_en; + litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en; end // synthesis translate_off dummy_d_50 = dummy_s; @@ -3953,11 +3276,10 @@ end reg dummy_d_51; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_address <= 15'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_address <= soc_sdram_slave_p3_address; + litedramcore_inti_p0_rddata_valid <= 1'd0; + if (litedramcore_storage[0]) begin end else begin - soc_sdram_master_p3_address <= soc_sdram_inti_p3_address; + litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end // synthesis translate_off dummy_d_51 = dummy_s; @@ -3968,11 +3290,11 @@ end reg dummy_d_52; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_bank <= 3'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_bank <= soc_sdram_slave_p3_bank; + litedramcore_master_p3_wrdata_mask <= 4'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; end else begin - soc_sdram_master_p3_bank <= soc_sdram_inti_p3_bank; + litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask; end // synthesis translate_off dummy_d_52 = dummy_s; @@ -3983,11 +3305,11 @@ end reg dummy_d_53; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_cas_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_cas_n <= soc_sdram_slave_p3_cas_n; + litedramcore_master_p3_rddata_en <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; end else begin - soc_sdram_master_p3_cas_n <= soc_sdram_inti_p3_cas_n; + litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en; end // synthesis translate_off dummy_d_53 = dummy_s; @@ -3998,11 +3320,11 @@ end reg dummy_d_54; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_cs_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_cs_n <= soc_sdram_slave_p3_cs_n; + litedramcore_master_p0_address <= 15'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_address <= litedramcore_slave_p0_address; end else begin - soc_sdram_master_p3_cs_n <= soc_sdram_inti_p3_cs_n; + litedramcore_master_p0_address <= litedramcore_inti_p0_address; end // synthesis translate_off dummy_d_54 = dummy_s; @@ -4013,11 +3335,11 @@ end reg dummy_d_55; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_ras_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_ras_n <= soc_sdram_slave_p3_ras_n; + litedramcore_master_p0_bank <= 3'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; end else begin - soc_sdram_master_p3_ras_n <= soc_sdram_inti_p3_ras_n; + litedramcore_master_p0_bank <= litedramcore_inti_p0_bank; end // synthesis translate_off dummy_d_55 = dummy_s; @@ -4028,10 +3350,11 @@ end reg dummy_d_56; // synthesis translate_on always @(*) begin - soc_sdram_slave_p3_rddata <= 32'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_slave_p3_rddata <= soc_sdram_master_p3_rddata; + litedramcore_master_p0_cas_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; end else begin + litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n; end // synthesis translate_off dummy_d_56 = dummy_s; @@ -4042,11 +3365,11 @@ end reg dummy_d_57; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_we_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_we_n <= soc_sdram_slave_p3_we_n; + litedramcore_master_p0_cs_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; end else begin - soc_sdram_master_p3_we_n <= soc_sdram_inti_p3_we_n; + litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n; end // synthesis translate_off dummy_d_57 = dummy_s; @@ -4057,10 +3380,11 @@ end reg dummy_d_58; // synthesis translate_on always @(*) begin - soc_sdram_slave_p3_rddata_valid <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_slave_p3_rddata_valid <= soc_sdram_master_p3_rddata_valid; + litedramcore_master_p0_ras_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; end else begin + litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n; end // synthesis translate_off dummy_d_58 = dummy_s; @@ -4071,11 +3395,10 @@ end reg dummy_d_59; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_cke <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_cke <= soc_sdram_slave_p3_cke; + litedramcore_slave_p0_rddata <= 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; end else begin - soc_sdram_master_p3_cke <= soc_sdram_inti_p3_cke; end // synthesis translate_off dummy_d_59 = dummy_s; @@ -4086,11 +3409,11 @@ end reg dummy_d_60; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_odt <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_odt <= soc_sdram_slave_p3_odt; + litedramcore_master_p0_we_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; end else begin - soc_sdram_master_p3_odt <= soc_sdram_inti_p3_odt; + litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; end // synthesis translate_off dummy_d_60 = dummy_s; @@ -4101,11 +3424,10 @@ end reg dummy_d_61; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_reset_n <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_reset_n <= soc_sdram_slave_p3_reset_n; + litedramcore_slave_p0_rddata_valid <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end else begin - soc_sdram_master_p3_reset_n <= soc_sdram_inti_p3_reset_n; end // synthesis translate_off dummy_d_61 = dummy_s; @@ -4116,11 +3438,11 @@ end reg dummy_d_62; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_act_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_act_n <= soc_sdram_slave_p3_act_n; + litedramcore_master_p0_cke <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; end else begin - soc_sdram_master_p3_act_n <= soc_sdram_inti_p3_act_n; + litedramcore_master_p0_cke <= litedramcore_inti_p0_cke; end // synthesis translate_off dummy_d_62 = dummy_s; @@ -4131,11 +3453,11 @@ end reg dummy_d_63; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_wrdata <= 32'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_wrdata <= soc_sdram_slave_p3_wrdata; + litedramcore_master_p0_odt <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; end else begin - soc_sdram_master_p3_wrdata <= soc_sdram_inti_p3_wrdata; + litedramcore_master_p0_odt <= litedramcore_inti_p0_odt; end // synthesis translate_off dummy_d_63 = dummy_s; @@ -4146,10 +3468,11 @@ end reg dummy_d_64; // synthesis translate_on always @(*) begin - soc_sdram_inti_p0_rddata <= 32'd0; - if (soc_sdram_storage[0]) begin + litedramcore_master_p0_reset_n <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; end else begin - soc_sdram_inti_p0_rddata <= soc_sdram_master_p0_rddata; + litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n; end // synthesis translate_off dummy_d_64 = dummy_s; @@ -4160,11 +3483,11 @@ end reg dummy_d_65; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_wrdata_en <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_wrdata_en <= soc_sdram_slave_p3_wrdata_en; + litedramcore_master_p0_act_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; end else begin - soc_sdram_master_p3_wrdata_en <= soc_sdram_inti_p3_wrdata_en; + litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n; end // synthesis translate_off dummy_d_65 = dummy_s; @@ -4175,10 +3498,11 @@ end reg dummy_d_66; // synthesis translate_on always @(*) begin - soc_sdram_inti_p0_rddata_valid <= 1'd0; - if (soc_sdram_storage[0]) begin + litedramcore_master_p0_wrdata <= 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; end else begin - soc_sdram_inti_p0_rddata_valid <= soc_sdram_master_p0_rddata_valid; + litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata; end // synthesis translate_off dummy_d_66 = dummy_s; @@ -4189,11 +3513,10 @@ end reg dummy_d_67; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_wrdata_mask <= 4'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_wrdata_mask <= soc_sdram_slave_p3_wrdata_mask; + litedramcore_inti_p1_rddata <= 32'd0; + if (litedramcore_storage[0]) begin end else begin - soc_sdram_master_p3_wrdata_mask <= soc_sdram_inti_p3_wrdata_mask; + litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata; end // synthesis translate_off dummy_d_67 = dummy_s; @@ -4204,11 +3527,11 @@ end reg dummy_d_68; // synthesis translate_on always @(*) begin - soc_sdram_master_p3_rddata_en <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p3_rddata_en <= soc_sdram_slave_p3_rddata_en; + litedramcore_master_p0_wrdata_en <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; end else begin - soc_sdram_master_p3_rddata_en <= soc_sdram_inti_p3_rddata_en; + litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en; end // synthesis translate_off dummy_d_68 = dummy_s; @@ -4219,11 +3542,10 @@ end reg dummy_d_69; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_address <= 15'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_address <= soc_sdram_slave_p0_address; + litedramcore_inti_p1_rddata_valid <= 1'd0; + if (litedramcore_storage[0]) begin end else begin - soc_sdram_master_p0_address <= soc_sdram_inti_p0_address; + litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end // synthesis translate_off dummy_d_69 = dummy_s; @@ -4234,11 +3556,11 @@ end reg dummy_d_70; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_bank <= 3'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_bank <= soc_sdram_slave_p0_bank; + litedramcore_master_p0_wrdata_mask <= 4'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; end else begin - soc_sdram_master_p0_bank <= soc_sdram_inti_p0_bank; + litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask; end // synthesis translate_off dummy_d_70 = dummy_s; @@ -4249,11 +3571,11 @@ end reg dummy_d_71; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_cas_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_cas_n <= soc_sdram_slave_p0_cas_n; + litedramcore_master_p0_rddata_en <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; end else begin - soc_sdram_master_p0_cas_n <= soc_sdram_inti_p0_cas_n; + litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en; end // synthesis translate_off dummy_d_71 = dummy_s; @@ -4264,11 +3586,11 @@ end reg dummy_d_72; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_cs_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_cs_n <= soc_sdram_slave_p0_cs_n; + litedramcore_master_p1_address <= 15'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_address <= litedramcore_slave_p1_address; end else begin - soc_sdram_master_p0_cs_n <= soc_sdram_inti_p0_cs_n; + litedramcore_master_p1_address <= litedramcore_inti_p1_address; end // synthesis translate_off dummy_d_72 = dummy_s; @@ -4279,11 +3601,11 @@ end reg dummy_d_73; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_ras_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_ras_n <= soc_sdram_slave_p0_ras_n; + litedramcore_master_p1_bank <= 3'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; end else begin - soc_sdram_master_p0_ras_n <= soc_sdram_inti_p0_ras_n; + litedramcore_master_p1_bank <= litedramcore_inti_p1_bank; end // synthesis translate_off dummy_d_73 = dummy_s; @@ -4294,10 +3616,11 @@ end reg dummy_d_74; // synthesis translate_on always @(*) begin - soc_sdram_slave_p0_rddata <= 32'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_slave_p0_rddata <= soc_sdram_master_p0_rddata; + litedramcore_master_p1_cas_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; end else begin + litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n; end // synthesis translate_off dummy_d_74 = dummy_s; @@ -4308,11 +3631,11 @@ end reg dummy_d_75; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_we_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_we_n <= soc_sdram_slave_p0_we_n; + litedramcore_master_p1_cs_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; end else begin - soc_sdram_master_p0_we_n <= soc_sdram_inti_p0_we_n; + litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n; end // synthesis translate_off dummy_d_75 = dummy_s; @@ -4323,10 +3646,11 @@ end reg dummy_d_76; // synthesis translate_on always @(*) begin - soc_sdram_slave_p0_rddata_valid <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_slave_p0_rddata_valid <= soc_sdram_master_p0_rddata_valid; + litedramcore_master_p1_ras_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; end else begin + litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n; end // synthesis translate_off dummy_d_76 = dummy_s; @@ -4337,11 +3661,10 @@ end reg dummy_d_77; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_cke <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_cke <= soc_sdram_slave_p0_cke; + litedramcore_slave_p1_rddata <= 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; end else begin - soc_sdram_master_p0_cke <= soc_sdram_inti_p0_cke; end // synthesis translate_off dummy_d_77 = dummy_s; @@ -4352,11 +3675,11 @@ end reg dummy_d_78; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_odt <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_odt <= soc_sdram_slave_p0_odt; + litedramcore_master_p1_we_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; end else begin - soc_sdram_master_p0_odt <= soc_sdram_inti_p0_odt; + litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n; end // synthesis translate_off dummy_d_78 = dummy_s; @@ -4367,11 +3690,10 @@ end reg dummy_d_79; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_reset_n <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_reset_n <= soc_sdram_slave_p0_reset_n; + litedramcore_slave_p1_rddata_valid <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end else begin - soc_sdram_master_p0_reset_n <= soc_sdram_inti_p0_reset_n; end // synthesis translate_off dummy_d_79 = dummy_s; @@ -4382,11 +3704,11 @@ end reg dummy_d_80; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_act_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_act_n <= soc_sdram_slave_p0_act_n; + litedramcore_master_p1_cke <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; end else begin - soc_sdram_master_p0_act_n <= soc_sdram_inti_p0_act_n; + litedramcore_master_p1_cke <= litedramcore_inti_p1_cke; end // synthesis translate_off dummy_d_80 = dummy_s; @@ -4397,11 +3719,11 @@ end reg dummy_d_81; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_wrdata <= 32'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_wrdata <= soc_sdram_slave_p0_wrdata; + litedramcore_master_p1_odt <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; end else begin - soc_sdram_master_p0_wrdata <= soc_sdram_inti_p0_wrdata; + litedramcore_master_p1_odt <= litedramcore_inti_p1_odt; end // synthesis translate_off dummy_d_81 = dummy_s; @@ -4412,10 +3734,11 @@ end reg dummy_d_82; // synthesis translate_on always @(*) begin - soc_sdram_inti_p1_rddata <= 32'd0; - if (soc_sdram_storage[0]) begin + litedramcore_master_p1_reset_n <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; end else begin - soc_sdram_inti_p1_rddata <= soc_sdram_master_p1_rddata; + litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; end // synthesis translate_off dummy_d_82 = dummy_s; @@ -4426,11 +3749,11 @@ end reg dummy_d_83; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_wrdata_en <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_wrdata_en <= soc_sdram_slave_p0_wrdata_en; + litedramcore_master_p1_act_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; end else begin - soc_sdram_master_p0_wrdata_en <= soc_sdram_inti_p0_wrdata_en; + litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n; end // synthesis translate_off dummy_d_83 = dummy_s; @@ -4441,10 +3764,11 @@ end reg dummy_d_84; // synthesis translate_on always @(*) begin - soc_sdram_inti_p1_rddata_valid <= 1'd0; - if (soc_sdram_storage[0]) begin + litedramcore_master_p1_wrdata <= 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; end else begin - soc_sdram_inti_p1_rddata_valid <= soc_sdram_master_p1_rddata_valid; + litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata; end // synthesis translate_off dummy_d_84 = dummy_s; @@ -4455,11 +3779,10 @@ end reg dummy_d_85; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_wrdata_mask <= 4'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_wrdata_mask <= soc_sdram_slave_p0_wrdata_mask; + litedramcore_inti_p2_rddata <= 32'd0; + if (litedramcore_storage[0]) begin end else begin - soc_sdram_master_p0_wrdata_mask <= soc_sdram_inti_p0_wrdata_mask; + litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; end // synthesis translate_off dummy_d_85 = dummy_s; @@ -4470,11 +3793,11 @@ end reg dummy_d_86; // synthesis translate_on always @(*) begin - soc_sdram_master_p0_rddata_en <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p0_rddata_en <= soc_sdram_slave_p0_rddata_en; + litedramcore_master_p1_wrdata_en <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; end else begin - soc_sdram_master_p0_rddata_en <= soc_sdram_inti_p0_rddata_en; + litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; end // synthesis translate_off dummy_d_86 = dummy_s; @@ -4485,11 +3808,10 @@ end reg dummy_d_87; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_address <= 15'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_address <= soc_sdram_slave_p1_address; + litedramcore_inti_p2_rddata_valid <= 1'd0; + if (litedramcore_storage[0]) begin end else begin - soc_sdram_master_p1_address <= soc_sdram_inti_p1_address; + litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end // synthesis translate_off dummy_d_87 = dummy_s; @@ -4500,11 +3822,11 @@ end reg dummy_d_88; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_bank <= 3'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_bank <= soc_sdram_slave_p1_bank; + litedramcore_master_p1_wrdata_mask <= 4'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; end else begin - soc_sdram_master_p1_bank <= soc_sdram_inti_p1_bank; + litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; end // synthesis translate_off dummy_d_88 = dummy_s; @@ -4515,11 +3837,11 @@ end reg dummy_d_89; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_cas_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_cas_n <= soc_sdram_slave_p1_cas_n; + litedramcore_master_p1_rddata_en <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; end else begin - soc_sdram_master_p1_cas_n <= soc_sdram_inti_p1_cas_n; + litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; end // synthesis translate_off dummy_d_89 = dummy_s; @@ -4530,11 +3852,11 @@ end reg dummy_d_90; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_cs_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_cs_n <= soc_sdram_slave_p1_cs_n; + litedramcore_master_p2_address <= 15'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_address <= litedramcore_slave_p2_address; end else begin - soc_sdram_master_p1_cs_n <= soc_sdram_inti_p1_cs_n; + litedramcore_master_p2_address <= litedramcore_inti_p2_address; end // synthesis translate_off dummy_d_90 = dummy_s; @@ -4545,11 +3867,11 @@ end reg dummy_d_91; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_ras_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_ras_n <= soc_sdram_slave_p1_ras_n; + litedramcore_master_p2_bank <= 3'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; end else begin - soc_sdram_master_p1_ras_n <= soc_sdram_inti_p1_ras_n; + litedramcore_master_p2_bank <= litedramcore_inti_p2_bank; end // synthesis translate_off dummy_d_91 = dummy_s; @@ -4560,10 +3882,11 @@ end reg dummy_d_92; // synthesis translate_on always @(*) begin - soc_sdram_slave_p1_rddata <= 32'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_slave_p1_rddata <= soc_sdram_master_p1_rddata; + litedramcore_master_p2_cas_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; end else begin + litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n; end // synthesis translate_off dummy_d_92 = dummy_s; @@ -4574,25 +3897,38 @@ end reg dummy_d_93; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_we_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_we_n <= soc_sdram_slave_p1_we_n; + litedramcore_master_p2_cs_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; end else begin - soc_sdram_master_p1_we_n <= soc_sdram_inti_p1_we_n; + litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n; end // synthesis translate_off dummy_d_93 = dummy_s; // synthesis translate_on end +assign litedramcore_inti_p0_cke = litedramcore_storage[1]; +assign litedramcore_inti_p1_cke = litedramcore_storage[1]; +assign litedramcore_inti_p2_cke = litedramcore_storage[1]; +assign litedramcore_inti_p3_cke = litedramcore_storage[1]; +assign litedramcore_inti_p0_odt = litedramcore_storage[2]; +assign litedramcore_inti_p1_odt = litedramcore_storage[2]; +assign litedramcore_inti_p2_odt = litedramcore_storage[2]; +assign litedramcore_inti_p3_odt = litedramcore_storage[2]; +assign litedramcore_inti_p0_reset_n = litedramcore_storage[3]; +assign litedramcore_inti_p1_reset_n = litedramcore_storage[3]; +assign litedramcore_inti_p2_reset_n = litedramcore_storage[3]; +assign litedramcore_inti_p3_reset_n = litedramcore_storage[3]; // synthesis translate_off reg dummy_d_94; // synthesis translate_on always @(*) begin - soc_sdram_slave_p1_rddata_valid <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_slave_p1_rddata_valid <= soc_sdram_master_p1_rddata_valid; + litedramcore_inti_p0_ras_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]); end else begin + litedramcore_inti_p0_ras_n <= 1'd1; end // synthesis translate_off dummy_d_94 = dummy_s; @@ -4603,11 +3939,11 @@ end reg dummy_d_95; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_cke <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_cke <= soc_sdram_slave_p1_cke; + litedramcore_inti_p0_we_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]); end else begin - soc_sdram_master_p1_cke <= soc_sdram_inti_p1_cke; + litedramcore_inti_p0_we_n <= 1'd1; end // synthesis translate_off dummy_d_95 = dummy_s; @@ -4618,11 +3954,11 @@ end reg dummy_d_96; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_odt <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_odt <= soc_sdram_slave_p1_odt; + litedramcore_inti_p0_cas_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]); end else begin - soc_sdram_master_p1_odt <= soc_sdram_inti_p1_odt; + litedramcore_inti_p0_cas_n <= 1'd1; end // synthesis translate_off dummy_d_96 = dummy_s; @@ -4633,26 +3969,32 @@ end reg dummy_d_97; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_reset_n <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_reset_n <= soc_sdram_slave_p1_reset_n; + litedramcore_inti_p0_cs_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}}; end else begin - soc_sdram_master_p1_reset_n <= soc_sdram_inti_p1_reset_n; + litedramcore_inti_p0_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_97 = dummy_s; // synthesis translate_on end +assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage; +assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage; +assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]); +assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]); +assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; +assign litedramcore_inti_p0_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_98; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_act_n <= 1'd1; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_act_n <= soc_sdram_slave_p1_act_n; + litedramcore_inti_p1_ras_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]); end else begin - soc_sdram_master_p1_act_n <= soc_sdram_inti_p1_act_n; + litedramcore_inti_p1_ras_n <= 1'd1; end // synthesis translate_off dummy_d_98 = dummy_s; @@ -4663,11 +4005,11 @@ end reg dummy_d_99; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_wrdata <= 32'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_wrdata <= soc_sdram_slave_p1_wrdata; + litedramcore_inti_p1_we_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]); end else begin - soc_sdram_master_p1_wrdata <= soc_sdram_inti_p1_wrdata; + litedramcore_inti_p1_we_n <= 1'd1; end // synthesis translate_off dummy_d_99 = dummy_s; @@ -4678,10 +4020,11 @@ end reg dummy_d_100; // synthesis translate_on always @(*) begin - soc_sdram_inti_p2_rddata <= 32'd0; - if (soc_sdram_storage[0]) begin + litedramcore_inti_p1_cas_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]); end else begin - soc_sdram_inti_p2_rddata <= soc_sdram_master_p2_rddata; + litedramcore_inti_p1_cas_n <= 1'd1; end // synthesis translate_off dummy_d_100 = dummy_s; @@ -4692,25 +4035,32 @@ end reg dummy_d_101; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_wrdata_en <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_wrdata_en <= soc_sdram_slave_p1_wrdata_en; + litedramcore_inti_p1_cs_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}}; end else begin - soc_sdram_master_p1_wrdata_en <= soc_sdram_inti_p1_wrdata_en; + litedramcore_inti_p1_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_101 = dummy_s; // synthesis translate_on end +assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage; +assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage; +assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]); +assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]); +assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; +assign litedramcore_inti_p1_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_102; // synthesis translate_on always @(*) begin - soc_sdram_inti_p2_rddata_valid <= 1'd0; - if (soc_sdram_storage[0]) begin + litedramcore_inti_p2_ras_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_inti_p2_ras_n <= (~litedramcore_phaseinjector2_command_storage[3]); end else begin - soc_sdram_inti_p2_rddata_valid <= soc_sdram_master_p2_rddata_valid; + litedramcore_inti_p2_ras_n <= 1'd1; end // synthesis translate_off dummy_d_102 = dummy_s; @@ -4721,11 +4071,11 @@ end reg dummy_d_103; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_wrdata_mask <= 4'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_wrdata_mask <= soc_sdram_slave_p1_wrdata_mask; + litedramcore_inti_p2_we_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_inti_p2_we_n <= (~litedramcore_phaseinjector2_command_storage[1]); end else begin - soc_sdram_master_p1_wrdata_mask <= soc_sdram_inti_p1_wrdata_mask; + litedramcore_inti_p2_we_n <= 1'd1; end // synthesis translate_off dummy_d_103 = dummy_s; @@ -4736,11 +4086,11 @@ end reg dummy_d_104; // synthesis translate_on always @(*) begin - soc_sdram_master_p1_rddata_en <= 1'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p1_rddata_en <= soc_sdram_slave_p1_rddata_en; + litedramcore_inti_p2_cas_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_inti_p2_cas_n <= (~litedramcore_phaseinjector2_command_storage[2]); end else begin - soc_sdram_master_p1_rddata_en <= soc_sdram_inti_p1_rddata_en; + litedramcore_inti_p2_cas_n <= 1'd1; end // synthesis translate_off dummy_d_104 = dummy_s; @@ -4751,53 +4101,47 @@ end reg dummy_d_105; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_address <= 15'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_address <= soc_sdram_slave_p2_address; + litedramcore_inti_p2_cs_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}}; end else begin - soc_sdram_master_p2_address <= soc_sdram_inti_p2_address; + litedramcore_inti_p2_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_105 = dummy_s; // synthesis translate_on end +assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage; +assign litedramcore_inti_p2_bank = litedramcore_phaseinjector2_baddress_storage; +assign litedramcore_inti_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[4]); +assign litedramcore_inti_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[5]); +assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; +assign litedramcore_inti_p2_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_106; // synthesis translate_on always @(*) begin - soc_sdram_master_p2_bank <= 3'd0; - if (soc_sdram_storage[0]) begin - soc_sdram_master_p2_bank <= soc_sdram_slave_p2_bank; + litedramcore_inti_p3_ras_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_inti_p3_ras_n <= (~litedramcore_phaseinjector3_command_storage[3]); end else begin - soc_sdram_master_p2_bank <= soc_sdram_inti_p2_bank; + litedramcore_inti_p3_ras_n <= 1'd1; end // synthesis translate_off dummy_d_106 = dummy_s; // synthesis translate_on end -assign soc_sdram_inti_p0_cke = soc_sdram_storage[1]; -assign soc_sdram_inti_p1_cke = soc_sdram_storage[1]; -assign soc_sdram_inti_p2_cke = soc_sdram_storage[1]; -assign soc_sdram_inti_p3_cke = soc_sdram_storage[1]; -assign soc_sdram_inti_p0_odt = soc_sdram_storage[2]; -assign soc_sdram_inti_p1_odt = soc_sdram_storage[2]; -assign soc_sdram_inti_p2_odt = soc_sdram_storage[2]; -assign soc_sdram_inti_p3_odt = soc_sdram_storage[2]; -assign soc_sdram_inti_p0_reset_n = soc_sdram_storage[3]; -assign soc_sdram_inti_p1_reset_n = soc_sdram_storage[3]; -assign soc_sdram_inti_p2_reset_n = soc_sdram_storage[3]; -assign soc_sdram_inti_p3_reset_n = soc_sdram_storage[3]; // synthesis translate_off reg dummy_d_107; // synthesis translate_on always @(*) begin - soc_sdram_inti_p0_cas_n <= 1'd1; - if (soc_sdram_phaseinjector0_command_issue_re) begin - soc_sdram_inti_p0_cas_n <= (~soc_sdram_phaseinjector0_command_storage[2]); + litedramcore_inti_p3_we_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_inti_p3_we_n <= (~litedramcore_phaseinjector3_command_storage[1]); end else begin - soc_sdram_inti_p0_cas_n <= 1'd1; + litedramcore_inti_p3_we_n <= 1'd1; end // synthesis translate_off dummy_d_107 = dummy_s; @@ -4808,11 +4152,11 @@ end reg dummy_d_108; // synthesis translate_on always @(*) begin - soc_sdram_inti_p0_cs_n <= 1'd1; - if (soc_sdram_phaseinjector0_command_issue_re) begin - soc_sdram_inti_p0_cs_n <= {1{(~soc_sdram_phaseinjector0_command_storage[0])}}; + litedramcore_inti_p3_cas_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_inti_p3_cas_n <= (~litedramcore_phaseinjector3_command_storage[2]); end else begin - soc_sdram_inti_p0_cs_n <= {1{1'd1}}; + litedramcore_inti_p3_cas_n <= 1'd1; end // synthesis translate_off dummy_d_108 = dummy_s; @@ -4823,48 +4167,158 @@ end reg dummy_d_109; // synthesis translate_on always @(*) begin - soc_sdram_inti_p0_ras_n <= 1'd1; - if (soc_sdram_phaseinjector0_command_issue_re) begin - soc_sdram_inti_p0_ras_n <= (~soc_sdram_phaseinjector0_command_storage[3]); + litedramcore_inti_p3_cs_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}}; end else begin - soc_sdram_inti_p0_ras_n <= 1'd1; + litedramcore_inti_p3_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_109 = dummy_s; // synthesis translate_on end +assign litedramcore_inti_p3_address = litedramcore_phaseinjector3_address_storage; +assign litedramcore_inti_p3_bank = litedramcore_phaseinjector3_baddress_storage; +assign litedramcore_inti_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[4]); +assign litedramcore_inti_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[5]); +assign litedramcore_inti_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage; +assign litedramcore_inti_p3_wrdata_mask = 1'd0; +assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid; +assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready; +assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we; +assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr; +assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock; +assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready; +assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid; +assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid; +assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready; +assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we; +assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr; +assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock; +assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready; +assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid; +assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid; +assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready; +assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we; +assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr; +assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock; +assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready; +assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid; +assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid; +assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready; +assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we; +assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr; +assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock; +assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready; +assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid; +assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid; +assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready; +assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we; +assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr; +assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock; +assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready; +assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid; +assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid; +assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready; +assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we; +assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr; +assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock; +assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready; +assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid; +assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid; +assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready; +assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we; +assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr; +assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock; +assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready; +assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid; +assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid; +assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready; +assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we; +assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr; +assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock; +assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready; +assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid; +assign litedramcore_timer_wait = (~litedramcore_timer_done0); +assign litedramcore_postponer_req_i = litedramcore_timer_done0; +assign litedramcore_wants_refresh = litedramcore_postponer_req_o; +assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0; +assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done); +assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0); +assign litedramcore_timer_done0 = litedramcore_timer_done1; +assign litedramcore_timer_count0 = litedramcore_timer_count1; +assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0)); +assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0)); +assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0); +assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; +assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; // synthesis translate_off reg dummy_d_110; // synthesis translate_on always @(*) begin - soc_sdram_inti_p0_we_n <= 1'd1; - if (soc_sdram_phaseinjector0_command_issue_re) begin - soc_sdram_inti_p0_we_n <= (~soc_sdram_phaseinjector0_command_storage[1]); - end else begin - soc_sdram_inti_p0_we_n <= 1'd1; - end + refresher_next_state <= 2'd0; + refresher_next_state <= refresher_state; + case (refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + refresher_next_state <= 2'd2; + end + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + refresher_next_state <= 2'd3; + end else begin + refresher_next_state <= 1'd0; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + refresher_next_state <= 1'd0; + end + end + default: begin + if (1'd1) begin + if (litedramcore_wants_refresh) begin + refresher_next_state <= 1'd1; + end + end + end + endcase // synthesis translate_off dummy_d_110 = dummy_s; // synthesis translate_on end -assign soc_sdram_inti_p0_address = soc_sdram_phaseinjector0_address_storage; -assign soc_sdram_inti_p0_bank = soc_sdram_phaseinjector0_baddress_storage; -assign soc_sdram_inti_p0_wrdata_en = (soc_sdram_phaseinjector0_command_issue_re & soc_sdram_phaseinjector0_command_storage[4]); -assign soc_sdram_inti_p0_rddata_en = (soc_sdram_phaseinjector0_command_issue_re & soc_sdram_phaseinjector0_command_storage[5]); -assign soc_sdram_inti_p0_wrdata = soc_sdram_phaseinjector0_wrdata_storage; -assign soc_sdram_inti_p0_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_111; // synthesis translate_on always @(*) begin - soc_sdram_inti_p1_cas_n <= 1'd1; - if (soc_sdram_phaseinjector1_command_issue_re) begin - soc_sdram_inti_p1_cas_n <= (~soc_sdram_phaseinjector1_command_storage[2]); - end else begin - soc_sdram_inti_p1_cas_n <= 1'd1; - end + litedramcore_cmd_valid <= 1'd0; + case (refresher_state) + 1'd1: begin + litedramcore_cmd_valid <= 1'd1; + end + 2'd2: begin + litedramcore_cmd_valid <= 1'd1; + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_valid <= 1'd0; + end + end + end + 2'd3: begin + litedramcore_cmd_valid <= 1'd1; + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_valid <= 1'd0; + end + end + default: begin + end + endcase // synthesis translate_off dummy_d_111 = dummy_s; // synthesis translate_on @@ -4874,12 +4328,23 @@ end reg dummy_d_112; // synthesis translate_on always @(*) begin - soc_sdram_inti_p1_cs_n <= 1'd1; - if (soc_sdram_phaseinjector1_command_issue_re) begin - soc_sdram_inti_p1_cs_n <= {1{(~soc_sdram_phaseinjector1_command_storage[0])}}; - end else begin - soc_sdram_inti_p1_cs_n <= {1{1'd1}}; - end + litedramcore_zqcs_executer_start <= 1'd0; + case (refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + litedramcore_zqcs_executer_start <= 1'd1; + end else begin + end + end + end + 2'd3: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_112 = dummy_s; // synthesis translate_on @@ -4889,12 +4354,26 @@ end reg dummy_d_113; // synthesis translate_on always @(*) begin - soc_sdram_inti_p1_ras_n <= 1'd1; - if (soc_sdram_phaseinjector1_command_issue_re) begin - soc_sdram_inti_p1_ras_n <= (~soc_sdram_phaseinjector1_command_storage[3]); - end else begin - soc_sdram_inti_p1_ras_n <= 1'd1; - end + litedramcore_cmd_last <= 1'd0; + case (refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_last <= 1'd1; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_last <= 1'd1; + end + end + default: begin + end + endcase // synthesis translate_off dummy_d_113 = dummy_s; // synthesis translate_on @@ -4904,542 +4383,365 @@ end reg dummy_d_114; // synthesis translate_on always @(*) begin - soc_sdram_inti_p1_we_n <= 1'd1; - if (soc_sdram_phaseinjector1_command_issue_re) begin - soc_sdram_inti_p1_we_n <= (~soc_sdram_phaseinjector1_command_storage[1]); - end else begin - soc_sdram_inti_p1_we_n <= 1'd1; - end + litedramcore_sequencer_start0 <= 1'd0; + case (refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_sequencer_start0 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_114 = dummy_s; // synthesis translate_on end -assign soc_sdram_inti_p1_address = soc_sdram_phaseinjector1_address_storage; -assign soc_sdram_inti_p1_bank = soc_sdram_phaseinjector1_baddress_storage; -assign soc_sdram_inti_p1_wrdata_en = (soc_sdram_phaseinjector1_command_issue_re & soc_sdram_phaseinjector1_command_storage[4]); -assign soc_sdram_inti_p1_rddata_en = (soc_sdram_phaseinjector1_command_issue_re & soc_sdram_phaseinjector1_command_storage[5]); -assign soc_sdram_inti_p1_wrdata = soc_sdram_phaseinjector1_wrdata_storage; -assign soc_sdram_inti_p1_wrdata_mask = 1'd0; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid; +assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr; +assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready; +assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); +assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid); +assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]); +assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; // synthesis translate_off reg dummy_d_115; // synthesis translate_on always @(*) begin - soc_sdram_inti_p2_cas_n <= 1'd1; - if (soc_sdram_phaseinjector2_command_issue_re) begin - soc_sdram_inti_p2_cas_n <= (~soc_sdram_phaseinjector2_command_storage[2]); + litedramcore_bankmachine0_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine0_row_col_n_addr_sel) begin + litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]; end else begin - soc_sdram_inti_p2_cas_n <= 1'd1; + litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off dummy_d_115 = dummy_s; // synthesis translate_on end +assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); +assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); +assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); // synthesis translate_off reg dummy_d_116; // synthesis translate_on always @(*) begin - soc_sdram_inti_p2_cs_n <= 1'd1; - if (soc_sdram_phaseinjector2_command_issue_re) begin - soc_sdram_inti_p2_cs_n <= {1{(~soc_sdram_phaseinjector2_command_storage[0])}}; - end else begin - soc_sdram_inti_p2_cs_n <= {1{1'd1}}; + litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin + litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); + end end // synthesis translate_off dummy_d_116 = dummy_s; // synthesis translate_on end +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; // synthesis translate_off reg dummy_d_117; // synthesis translate_on always @(*) begin - soc_sdram_inti_p2_ras_n <= 1'd1; - if (soc_sdram_phaseinjector2_command_issue_re) begin - soc_sdram_inti_p2_ras_n <= (~soc_sdram_phaseinjector2_command_storage[3]); + litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_sdram_inti_p2_ras_n <= 1'd1; + litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce; end // synthesis translate_off dummy_d_117 = dummy_s; // synthesis translate_on end +assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); +assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready); // synthesis translate_off reg dummy_d_118; // synthesis translate_on always @(*) begin - soc_sdram_inti_p2_we_n <= 1'd1; - if (soc_sdram_phaseinjector2_command_issue_re) begin - soc_sdram_inti_p2_we_n <= (~soc_sdram_phaseinjector2_command_storage[1]); - end else begin - soc_sdram_inti_p2_we_n <= 1'd1; - end + bankmachine0_next_state <= 4'd0; + bankmachine0_next_state <= bankmachine0_state; + case (bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + if (litedramcore_bankmachine0_cmd_ready) begin + bankmachine0_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + bankmachine0_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + if (litedramcore_bankmachine0_cmd_ready) begin + bankmachine0_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine0_refresh_req)) begin + bankmachine0_next_state <= 1'd0; + end + end + 3'd5: begin + bankmachine0_next_state <= 3'd6; + end + 3'd6: begin + bankmachine0_next_state <= 2'd3; + end + 3'd7: begin + bankmachine0_next_state <= 4'd8; + end + 4'd8: begin + bankmachine0_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + bankmachine0_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin + bankmachine0_next_state <= 2'd2; + end + end else begin + bankmachine0_next_state <= 1'd1; + end + end else begin + bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase // synthesis translate_off dummy_d_118 = dummy_s; // synthesis translate_on end -assign soc_sdram_inti_p2_address = soc_sdram_phaseinjector2_address_storage; -assign soc_sdram_inti_p2_bank = soc_sdram_phaseinjector2_baddress_storage; -assign soc_sdram_inti_p2_wrdata_en = (soc_sdram_phaseinjector2_command_issue_re & soc_sdram_phaseinjector2_command_storage[4]); -assign soc_sdram_inti_p2_rddata_en = (soc_sdram_phaseinjector2_command_issue_re & soc_sdram_phaseinjector2_command_storage[5]); -assign soc_sdram_inti_p2_wrdata = soc_sdram_phaseinjector2_wrdata_storage; -assign soc_sdram_inti_p2_wrdata_mask = 1'd0; // synthesis translate_off reg dummy_d_119; // synthesis translate_on always @(*) begin - soc_sdram_inti_p3_cas_n <= 1'd1; - if (soc_sdram_phaseinjector3_command_issue_re) begin - soc_sdram_inti_p3_cas_n <= (~soc_sdram_phaseinjector3_command_storage[2]); - end else begin - soc_sdram_inti_p3_cas_n <= 1'd1; - end -// synthesis translate_off - dummy_d_119 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_120; -// synthesis translate_on -always @(*) begin - soc_sdram_inti_p3_cs_n <= 1'd1; - if (soc_sdram_phaseinjector3_command_issue_re) begin - soc_sdram_inti_p3_cs_n <= {1{(~soc_sdram_phaseinjector3_command_storage[0])}}; - end else begin - soc_sdram_inti_p3_cs_n <= {1{1'd1}}; - end -// synthesis translate_off - dummy_d_120 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_121; -// synthesis translate_on -always @(*) begin - soc_sdram_inti_p3_ras_n <= 1'd1; - if (soc_sdram_phaseinjector3_command_issue_re) begin - soc_sdram_inti_p3_ras_n <= (~soc_sdram_phaseinjector3_command_storage[3]); - end else begin - soc_sdram_inti_p3_ras_n <= 1'd1; - end -// synthesis translate_off - dummy_d_121 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_122; -// synthesis translate_on -always @(*) begin - soc_sdram_inti_p3_we_n <= 1'd1; - if (soc_sdram_phaseinjector3_command_issue_re) begin - soc_sdram_inti_p3_we_n <= (~soc_sdram_phaseinjector3_command_storage[1]); - end else begin - soc_sdram_inti_p3_we_n <= 1'd1; - end -// synthesis translate_off - dummy_d_122 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_inti_p3_address = soc_sdram_phaseinjector3_address_storage; -assign soc_sdram_inti_p3_bank = soc_sdram_phaseinjector3_baddress_storage; -assign soc_sdram_inti_p3_wrdata_en = (soc_sdram_phaseinjector3_command_issue_re & soc_sdram_phaseinjector3_command_storage[4]); -assign soc_sdram_inti_p3_rddata_en = (soc_sdram_phaseinjector3_command_issue_re & soc_sdram_phaseinjector3_command_storage[5]); -assign soc_sdram_inti_p3_wrdata = soc_sdram_phaseinjector3_wrdata_storage; -assign soc_sdram_inti_p3_wrdata_mask = 1'd0; -assign soc_sdram_bankmachine0_req_valid = soc_sdram_interface_bank0_valid; -assign soc_sdram_interface_bank0_ready = soc_sdram_bankmachine0_req_ready; -assign soc_sdram_bankmachine0_req_we = soc_sdram_interface_bank0_we; -assign soc_sdram_bankmachine0_req_addr = soc_sdram_interface_bank0_addr; -assign soc_sdram_interface_bank0_lock = soc_sdram_bankmachine0_req_lock; -assign soc_sdram_interface_bank0_wdata_ready = soc_sdram_bankmachine0_req_wdata_ready; -assign soc_sdram_interface_bank0_rdata_valid = soc_sdram_bankmachine0_req_rdata_valid; -assign soc_sdram_bankmachine1_req_valid = soc_sdram_interface_bank1_valid; -assign soc_sdram_interface_bank1_ready = soc_sdram_bankmachine1_req_ready; -assign soc_sdram_bankmachine1_req_we = soc_sdram_interface_bank1_we; -assign soc_sdram_bankmachine1_req_addr = soc_sdram_interface_bank1_addr; -assign soc_sdram_interface_bank1_lock = soc_sdram_bankmachine1_req_lock; -assign soc_sdram_interface_bank1_wdata_ready = soc_sdram_bankmachine1_req_wdata_ready; -assign soc_sdram_interface_bank1_rdata_valid = soc_sdram_bankmachine1_req_rdata_valid; -assign soc_sdram_bankmachine2_req_valid = soc_sdram_interface_bank2_valid; -assign soc_sdram_interface_bank2_ready = soc_sdram_bankmachine2_req_ready; -assign soc_sdram_bankmachine2_req_we = soc_sdram_interface_bank2_we; -assign soc_sdram_bankmachine2_req_addr = soc_sdram_interface_bank2_addr; -assign soc_sdram_interface_bank2_lock = soc_sdram_bankmachine2_req_lock; -assign soc_sdram_interface_bank2_wdata_ready = soc_sdram_bankmachine2_req_wdata_ready; -assign soc_sdram_interface_bank2_rdata_valid = soc_sdram_bankmachine2_req_rdata_valid; -assign soc_sdram_bankmachine3_req_valid = soc_sdram_interface_bank3_valid; -assign soc_sdram_interface_bank3_ready = soc_sdram_bankmachine3_req_ready; -assign soc_sdram_bankmachine3_req_we = soc_sdram_interface_bank3_we; -assign soc_sdram_bankmachine3_req_addr = soc_sdram_interface_bank3_addr; -assign soc_sdram_interface_bank3_lock = soc_sdram_bankmachine3_req_lock; -assign soc_sdram_interface_bank3_wdata_ready = soc_sdram_bankmachine3_req_wdata_ready; -assign soc_sdram_interface_bank3_rdata_valid = soc_sdram_bankmachine3_req_rdata_valid; -assign soc_sdram_bankmachine4_req_valid = soc_sdram_interface_bank4_valid; -assign soc_sdram_interface_bank4_ready = soc_sdram_bankmachine4_req_ready; -assign soc_sdram_bankmachine4_req_we = soc_sdram_interface_bank4_we; -assign soc_sdram_bankmachine4_req_addr = soc_sdram_interface_bank4_addr; -assign soc_sdram_interface_bank4_lock = soc_sdram_bankmachine4_req_lock; -assign soc_sdram_interface_bank4_wdata_ready = soc_sdram_bankmachine4_req_wdata_ready; -assign soc_sdram_interface_bank4_rdata_valid = soc_sdram_bankmachine4_req_rdata_valid; -assign soc_sdram_bankmachine5_req_valid = soc_sdram_interface_bank5_valid; -assign soc_sdram_interface_bank5_ready = soc_sdram_bankmachine5_req_ready; -assign soc_sdram_bankmachine5_req_we = soc_sdram_interface_bank5_we; -assign soc_sdram_bankmachine5_req_addr = soc_sdram_interface_bank5_addr; -assign soc_sdram_interface_bank5_lock = soc_sdram_bankmachine5_req_lock; -assign soc_sdram_interface_bank5_wdata_ready = soc_sdram_bankmachine5_req_wdata_ready; -assign soc_sdram_interface_bank5_rdata_valid = soc_sdram_bankmachine5_req_rdata_valid; -assign soc_sdram_bankmachine6_req_valid = soc_sdram_interface_bank6_valid; -assign soc_sdram_interface_bank6_ready = soc_sdram_bankmachine6_req_ready; -assign soc_sdram_bankmachine6_req_we = soc_sdram_interface_bank6_we; -assign soc_sdram_bankmachine6_req_addr = soc_sdram_interface_bank6_addr; -assign soc_sdram_interface_bank6_lock = soc_sdram_bankmachine6_req_lock; -assign soc_sdram_interface_bank6_wdata_ready = soc_sdram_bankmachine6_req_wdata_ready; -assign soc_sdram_interface_bank6_rdata_valid = soc_sdram_bankmachine6_req_rdata_valid; -assign soc_sdram_bankmachine7_req_valid = soc_sdram_interface_bank7_valid; -assign soc_sdram_interface_bank7_ready = soc_sdram_bankmachine7_req_ready; -assign soc_sdram_bankmachine7_req_we = soc_sdram_interface_bank7_we; -assign soc_sdram_bankmachine7_req_addr = soc_sdram_interface_bank7_addr; -assign soc_sdram_interface_bank7_lock = soc_sdram_bankmachine7_req_lock; -assign soc_sdram_interface_bank7_wdata_ready = soc_sdram_bankmachine7_req_wdata_ready; -assign soc_sdram_interface_bank7_rdata_valid = soc_sdram_bankmachine7_req_rdata_valid; -assign soc_sdram_timer_wait = (~soc_sdram_timer_done0); -assign soc_sdram_postponer_req_i = soc_sdram_timer_done0; -assign soc_sdram_wants_refresh = soc_sdram_postponer_req_o; -assign soc_sdram_wants_zqcs = soc_sdram_zqcs_timer_done0; -assign soc_sdram_zqcs_timer_wait = (~soc_sdram_zqcs_executer_done); -assign soc_sdram_timer_done1 = (soc_sdram_timer_count1 == 1'd0); -assign soc_sdram_timer_done0 = soc_sdram_timer_done1; -assign soc_sdram_timer_count0 = soc_sdram_timer_count1; -assign soc_sdram_sequencer_start1 = (soc_sdram_sequencer_start0 | (soc_sdram_sequencer_count != 1'd0)); -assign soc_sdram_sequencer_done0 = (soc_sdram_sequencer_done1 & (soc_sdram_sequencer_count == 1'd0)); -assign soc_sdram_zqcs_timer_done1 = (soc_sdram_zqcs_timer_count1 == 1'd0); -assign soc_sdram_zqcs_timer_done0 = soc_sdram_zqcs_timer_done1; -assign soc_sdram_zqcs_timer_count0 = soc_sdram_zqcs_timer_count1; - -// synthesis translate_off -reg dummy_d_123; -// synthesis translate_on -always @(*) begin - vns_refresher_next_state <= 2'd0; - vns_refresher_next_state <= vns_refresher_state; - case (vns_refresher_state) + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (bankmachine0_state) 1'd1: begin - if (soc_sdram_cmd_ready) begin - vns_refresher_next_state <= 2'd2; - end end 2'd2: begin - if (soc_sdram_sequencer_done0) begin - if (soc_sdram_wants_zqcs) begin - vns_refresher_next_state <= 2'd3; - end else begin - vns_refresher_next_state <= 1'd0; - end - end end 2'd3: begin - if (soc_sdram_zqcs_executer_done) begin - vns_refresher_next_state <= 1'd0; - end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin end default: begin - if (1'd1) begin - if (soc_sdram_wants_refresh) begin - vns_refresher_next_state <= 1'd1; + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end end end end endcase // synthesis translate_off - dummy_d_123 = dummy_s; + dummy_d_119 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_124; +reg dummy_d_120; // synthesis translate_on always @(*) begin - soc_sdram_sequencer_start0 <= 1'd0; - case (vns_refresher_state) + litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (bankmachine0_state) 1'd1: begin - if (soc_sdram_cmd_ready) begin - soc_sdram_sequencer_start0 <= 1'd1; - end end 2'd2: begin end 2'd3: begin end - default: begin + 3'd4: begin end - endcase -// synthesis translate_off - dummy_d_124 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_125; -// synthesis translate_on -always @(*) begin - soc_sdram_cmd_valid <= 1'd0; - case (vns_refresher_state) - 1'd1: begin - soc_sdram_cmd_valid <= 1'd1; + 3'd5: begin end - 2'd2: begin - soc_sdram_cmd_valid <= 1'd1; - if (soc_sdram_sequencer_done0) begin - if (soc_sdram_wants_zqcs) begin - end else begin - soc_sdram_cmd_valid <= 1'd0; - end - end + 3'd6: begin end - 2'd3: begin - soc_sdram_cmd_valid <= 1'd1; - if (soc_sdram_zqcs_executer_done) begin - soc_sdram_cmd_valid <= 1'd0; - end + 3'd7: begin + end + 4'd8: begin end default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_125 = dummy_s; + dummy_d_120 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_126; +reg dummy_d_121; // synthesis translate_on always @(*) begin - soc_sdram_zqcs_executer_start <= 1'd0; - case (vns_refresher_state) + litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (bankmachine0_state) 1'd1: begin end 2'd2: begin - if (soc_sdram_sequencer_done0) begin - if (soc_sdram_wants_zqcs) begin - soc_sdram_zqcs_executer_start <= 1'd1; - end else begin - end - end end 2'd3: begin end - default: begin + 3'd4: begin end - endcase -// synthesis translate_off - dummy_d_126 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_127; -// synthesis translate_on -always @(*) begin - soc_sdram_cmd_last <= 1'd0; - case (vns_refresher_state) - 1'd1: begin + 3'd5: begin end - 2'd2: begin - if (soc_sdram_sequencer_done0) begin - if (soc_sdram_wants_zqcs) begin - end else begin - soc_sdram_cmd_last <= 1'd1; - end - end + 3'd6: begin end - 2'd3: begin - if (soc_sdram_zqcs_executer_done) begin - soc_sdram_cmd_last <= 1'd1; - end + 3'd7: begin + end + 4'd8: begin end default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_127 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine0_req_valid; -assign soc_sdram_bankmachine0_req_ready = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine0_req_we; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine0_req_addr; -assign soc_sdram_bankmachine0_cmd_buffer_sink_valid = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine0_cmd_buffer_sink_ready; -assign soc_sdram_bankmachine0_cmd_buffer_sink_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first; -assign soc_sdram_bankmachine0_cmd_buffer_sink_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last; -assign soc_sdram_bankmachine0_cmd_buffer_sink_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we; -assign soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -assign soc_sdram_bankmachine0_cmd_buffer_source_ready = (soc_sdram_bankmachine0_req_wdata_ready | soc_sdram_bankmachine0_req_rdata_valid); -assign soc_sdram_bankmachine0_req_lock = (soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine0_cmd_buffer_source_valid); -assign soc_sdram_bankmachine0_row_hit = (soc_sdram_bankmachine0_row == soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:7]); -assign soc_sdram_bankmachine0_cmd_payload_ba = 1'd0; - -// synthesis translate_off -reg dummy_d_128; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine0_cmd_payload_a <= 15'd0; - if (soc_sdram_bankmachine0_row_col_n_addr_sel) begin - soc_sdram_bankmachine0_cmd_payload_a <= soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:7]; - end else begin - soc_sdram_bankmachine0_cmd_payload_a <= ((soc_sdram_bankmachine0_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_128 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine0_twtpcon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_cmd_payload_is_write); -assign soc_sdram_bankmachine0_trccon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_row_open); -assign soc_sdram_bankmachine0_trascon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_row_open); - -// synthesis translate_off -reg dummy_d_129; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine0_auto_precharge <= 1'd0; - if ((soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine0_cmd_buffer_source_valid)) begin - if ((soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin - soc_sdram_bankmachine0_auto_precharge <= (soc_sdram_bankmachine0_row_close == 1'd0); - end - end -// synthesis translate_off - dummy_d_129 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_first; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_last; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_130; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_sdram_bankmachine0_cmd_buffer_lookahead_replace) begin - soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine0_cmd_buffer_lookahead_produce; - end -// synthesis translate_off - dummy_d_130 = dummy_s; + dummy_d_121 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_sdram_bankmachine0_cmd_buffer_lookahead_replace)); -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine0_cmd_buffer_lookahead_consume; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_sdram_bankmachine0_cmd_buffer_lookahead_level != 5'd16); -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0); -assign soc_sdram_bankmachine0_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine0_cmd_buffer_source_valid) | soc_sdram_bankmachine0_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_131; +reg dummy_d_122; // synthesis translate_on always @(*) begin - vns_bankmachine0_next_state <= 4'd0; - vns_bankmachine0_next_state <= vns_bankmachine0_state; - case (vns_bankmachine0_state) + litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (bankmachine0_state) 1'd1: begin - if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin - if (soc_sdram_bankmachine0_cmd_ready) begin - vns_bankmachine0_next_state <= 3'd5; - end - end end 2'd2: begin - if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin - vns_bankmachine0_next_state <= 3'd5; - end end 2'd3: begin - if (soc_sdram_bankmachine0_trccon_ready) begin - if (soc_sdram_bankmachine0_cmd_ready) begin - vns_bankmachine0_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~soc_sdram_bankmachine0_refresh_req)) begin - vns_bankmachine0_next_state <= 1'd0; + if (litedramcore_bankmachine0_twtpcon_ready) begin + litedramcore_bankmachine0_refresh_gnt <= 1'd1; end end 3'd5: begin - vns_bankmachine0_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine0_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine0_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine0_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine0_refresh_req) begin - vns_bankmachine0_next_state <= 3'd4; - end else begin - if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine0_row_opened) begin - if (soc_sdram_bankmachine0_row_hit) begin - if ((soc_sdram_bankmachine0_cmd_ready & soc_sdram_bankmachine0_auto_precharge)) begin - vns_bankmachine0_next_state <= 2'd2; - end - end else begin - vns_bankmachine0_next_state <= 1'd1; - end - end else begin - vns_bankmachine0_next_state <= 2'd3; - end - end - end end endcase // synthesis translate_off - dummy_d_131 = dummy_s; + dummy_d_122 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_132; +reg dummy_d_123; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_cmd_payload_we <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (bankmachine0_state) 1'd1: begin - if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin - soc_sdram_bankmachine0_cmd_payload_we <= 1'd1; + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -5452,15 +4754,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine0_refresh_req) begin + if (litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine0_row_opened) begin - if (soc_sdram_bankmachine0_row_hit) begin - if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine0_cmd_payload_we <= 1'd1; - end else begin - end + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; end else begin end end else begin @@ -5470,23 +4769,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_132 = dummy_s; + dummy_d_123 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_133; +reg dummy_d_124; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine0_row_open <= 1'd0; + case (bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine0_trccon_ready) begin - soc_sdram_bankmachine0_row_col_n_addr_sel <= 1'd1; + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_open <= 1'd1; end end 3'd4: begin @@ -5503,30 +4802,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_133 = dummy_s; + dummy_d_124 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_134; +reg dummy_d_125; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine0_row_close <= 1'd0; + case (bankmachine0_state) 1'd1: begin - if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin - soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end + litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin - if (soc_sdram_bankmachine0_trccon_ready) begin - soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -5540,16 +4835,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_134 = dummy_s; + dummy_d_125 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_135; +reg dummy_d_126; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (bankmachine0_state) 1'd1: begin end 2'd2: begin @@ -5567,15 +4862,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine0_refresh_req) begin + if (litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine0_row_opened) begin - if (soc_sdram_bankmachine0_row_hit) begin - if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - soc_sdram_bankmachine0_cmd_payload_is_read <= 1'd1; - end + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -5585,21 +4877,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_135 = dummy_s; + dummy_d_126 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_136; +reg dummy_d_127; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -5612,39 +4907,30 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine0_refresh_req) begin - end else begin - if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine0_row_opened) begin - if (soc_sdram_bankmachine0_row_hit) begin - if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine0_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_136 = dummy_s; + dummy_d_127 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_137; +reg dummy_d_128; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_req_wdata_ready <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (bankmachine0_state) 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -5657,35 +4943,23 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine0_refresh_req) begin - end else begin - if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine0_row_opened) begin - if (soc_sdram_bankmachine0_row_hit) begin - if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine0_req_wdata_ready <= soc_sdram_bankmachine0_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_137 = dummy_s; + dummy_d_128 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_138; +reg dummy_d_129; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_req_rdata_valid <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (bankmachine0_state) 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -5702,14 +4976,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine0_refresh_req) begin + if (litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine0_row_opened) begin - if (soc_sdram_bankmachine0_row_hit) begin - if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; end else begin - soc_sdram_bankmachine0_req_rdata_valid <= soc_sdram_bankmachine0_cmd_ready; end end else begin end @@ -5720,26 +4994,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_138 = dummy_s; + dummy_d_129 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_139; +reg dummy_d_130; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_refresh_gnt <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (bankmachine0_state) 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin - if (soc_sdram_bankmachine0_twtpcon_ready) begin - soc_sdram_bankmachine0_refresh_gnt <= 1'd1; - end + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5753,27 +5031,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_139 = dummy_s; + dummy_d_130 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_140; +reg dummy_d_131; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_cmd_valid <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (bankmachine0_state) 1'd1: begin - if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin - soc_sdram_bankmachine0_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine0_trccon_ready) begin - soc_sdram_bankmachine0_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -5786,12 +5058,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine0_refresh_req) begin + if (litedramcore_bankmachine0_refresh_req) begin end else begin - if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine0_row_opened) begin - if (soc_sdram_bankmachine0_row_hit) begin - soc_sdram_bankmachine0_cmd_valid <= 1'd1; + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + end end else begin end end else begin @@ -5801,135 +5076,176 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_140 = dummy_s; + dummy_d_131 = dummy_s; // synthesis translate_on end +assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid; +assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr; +assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready; +assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); +assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid); +assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]); +assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; // synthesis translate_off -reg dummy_d_141; +reg dummy_d_132; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_row_open <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_sdram_bankmachine0_trccon_ready) begin - soc_sdram_bankmachine0_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase + litedramcore_bankmachine1_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine1_row_col_n_addr_sel) begin + litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end // synthesis translate_off - dummy_d_141 = dummy_s; + dummy_d_132 = dummy_s; // synthesis translate_on end +assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); +assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); +assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); // synthesis translate_off -reg dummy_d_142; +reg dummy_d_133; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_row_close <= 1'd0; - case (vns_bankmachine0_state) - 1'd1: begin - soc_sdram_bankmachine0_row_close <= 1'd1; - end - 2'd2: begin - soc_sdram_bankmachine0_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - soc_sdram_bankmachine0_row_close <= 1'd1; + litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin + litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase + end // synthesis translate_off - dummy_d_142 = dummy_s; + dummy_d_133 = dummy_s; // synthesis translate_on end +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_143; +reg dummy_d_134; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_cmd_payload_cas <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce; + end +// synthesis translate_off + dummy_d_134 = dummy_s; +// synthesis translate_on +end +assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); +assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready); + +// synthesis translate_off +reg dummy_d_135; +// synthesis translate_on +always @(*) begin + bankmachine1_next_state <= 4'd0; + bankmachine1_next_state <= bankmachine1_state; + case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + if (litedramcore_bankmachine1_cmd_ready) begin + bankmachine1_next_state <= 3'd5; + end + end end 2'd2: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + bankmachine1_next_state <= 3'd5; + end end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + if (litedramcore_bankmachine1_cmd_ready) begin + bankmachine1_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~litedramcore_bankmachine1_refresh_req)) begin + bankmachine1_next_state <= 1'd0; + end end 3'd5: begin + bankmachine1_next_state <= 3'd6; end 3'd6: begin + bankmachine1_next_state <= 2'd3; end 3'd7: begin + bankmachine1_next_state <= 4'd8; end 4'd8: begin + bankmachine1_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine0_refresh_req) begin + if (litedramcore_bankmachine1_refresh_req) begin + bankmachine1_next_state <= 3'd4; end else begin - if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine0_row_opened) begin - if (soc_sdram_bankmachine0_row_hit) begin - soc_sdram_bankmachine0_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin + bankmachine1_next_state <= 2'd2; + end end else begin + bankmachine1_next_state <= 1'd1; end end else begin + bankmachine1_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_143 = dummy_s; + dummy_d_135 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_144; +reg dummy_d_136; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_cmd_payload_ras <= 1'd0; - case (vns_bankmachine0_state) + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (bankmachine1_state) 1'd1: begin - if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin - soc_sdram_bankmachine0_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine0_trccon_ready) begin - soc_sdram_bankmachine0_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -5942,182 +5258,87 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_144 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine1_req_valid; -assign soc_sdram_bankmachine1_req_ready = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine1_req_we; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine1_req_addr; -assign soc_sdram_bankmachine1_cmd_buffer_sink_valid = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine1_cmd_buffer_sink_ready; -assign soc_sdram_bankmachine1_cmd_buffer_sink_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first; -assign soc_sdram_bankmachine1_cmd_buffer_sink_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last; -assign soc_sdram_bankmachine1_cmd_buffer_sink_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we; -assign soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -assign soc_sdram_bankmachine1_cmd_buffer_source_ready = (soc_sdram_bankmachine1_req_wdata_ready | soc_sdram_bankmachine1_req_rdata_valid); -assign soc_sdram_bankmachine1_req_lock = (soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine1_cmd_buffer_source_valid); -assign soc_sdram_bankmachine1_row_hit = (soc_sdram_bankmachine1_row == soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:7]); -assign soc_sdram_bankmachine1_cmd_payload_ba = 1'd1; - -// synthesis translate_off -reg dummy_d_145; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine1_cmd_payload_a <= 15'd0; - if (soc_sdram_bankmachine1_row_col_n_addr_sel) begin - soc_sdram_bankmachine1_cmd_payload_a <= soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:7]; - end else begin - soc_sdram_bankmachine1_cmd_payload_a <= ((soc_sdram_bankmachine1_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -// synthesis translate_off - dummy_d_145 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine1_twtpcon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_cmd_payload_is_write); -assign soc_sdram_bankmachine1_trccon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_row_open); -assign soc_sdram_bankmachine1_trascon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_row_open); - -// synthesis translate_off -reg dummy_d_146; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine1_auto_precharge <= 1'd0; - if ((soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine1_cmd_buffer_source_valid)) begin - if ((soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin - soc_sdram_bankmachine1_auto_precharge <= (soc_sdram_bankmachine1_row_close == 1'd0); - end - end -// synthesis translate_off - dummy_d_146 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_first; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_last; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_147; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_sdram_bankmachine1_cmd_buffer_lookahead_replace) begin - soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine1_cmd_buffer_lookahead_produce; - end -// synthesis translate_off - dummy_d_147 = dummy_s; + dummy_d_136 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_sdram_bankmachine1_cmd_buffer_lookahead_replace)); -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine1_cmd_buffer_lookahead_consume; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_sdram_bankmachine1_cmd_buffer_lookahead_level != 5'd16); -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0); -assign soc_sdram_bankmachine1_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine1_cmd_buffer_source_valid) | soc_sdram_bankmachine1_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_148; +reg dummy_d_137; // synthesis translate_on always @(*) begin - vns_bankmachine1_next_state <= 4'd0; - vns_bankmachine1_next_state <= vns_bankmachine1_state; - case (vns_bankmachine1_state) + litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (bankmachine1_state) 1'd1: begin - if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin - if (soc_sdram_bankmachine1_cmd_ready) begin - vns_bankmachine1_next_state <= 3'd5; - end - end end 2'd2: begin - if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin - vns_bankmachine1_next_state <= 3'd5; - end end 2'd3: begin - if (soc_sdram_bankmachine1_trccon_ready) begin - if (soc_sdram_bankmachine1_cmd_ready) begin - vns_bankmachine1_next_state <= 3'd7; - end - end end 3'd4: begin - if ((~soc_sdram_bankmachine1_refresh_req)) begin - vns_bankmachine1_next_state <= 1'd0; - end end 3'd5: begin - vns_bankmachine1_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine1_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine1_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine1_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine1_refresh_req) begin - vns_bankmachine1_next_state <= 3'd4; + if (litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine1_row_opened) begin - if (soc_sdram_bankmachine1_row_hit) begin - if ((soc_sdram_bankmachine1_cmd_ready & soc_sdram_bankmachine1_auto_precharge)) begin - vns_bankmachine1_next_state <= 2'd2; + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; + end else begin end end else begin - vns_bankmachine1_next_state <= 1'd1; end end else begin - vns_bankmachine1_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_148 = dummy_s; + dummy_d_137 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_149; +reg dummy_d_138; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_cmd_payload_we <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (bankmachine1_state) 1'd1: begin - if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin - soc_sdram_bankmachine1_cmd_payload_we <= 1'd1; - end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -6130,42 +5351,24 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine1_refresh_req) begin - end else begin - if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine1_row_opened) begin - if (soc_sdram_bankmachine1_row_hit) begin - if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine1_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_149 = dummy_s; + dummy_d_138 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_150; +reg dummy_d_139; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine1_trccon_ready) begin - soc_sdram_bankmachine1_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -6178,33 +5381,44 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_150 = dummy_s; + dummy_d_139 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_151; +reg dummy_d_140; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (bankmachine1_state) 1'd1: begin - if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin - soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine1_trccon_ready) begin - soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6218,21 +5432,27 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_151 = dummy_s; + dummy_d_140 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_152; +reg dummy_d_141; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -6245,15 +5465,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine1_refresh_req) begin + if (litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine1_row_opened) begin - if (soc_sdram_bankmachine1_row_hit) begin - if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - soc_sdram_bankmachine1_cmd_payload_is_read <= 1'd1; - end + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; end else begin end end else begin @@ -6263,21 +5480,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_152 = dummy_s; + dummy_d_141 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_153; +reg dummy_d_142; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine1_row_open <= 1'd0; + case (bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_open <= 1'd1; + end end 3'd4: begin end @@ -6290,41 +5510,29 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine1_refresh_req) begin - end else begin - if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine1_row_opened) begin - if (soc_sdram_bankmachine1_row_hit) begin - if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine1_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_153 = dummy_s; + dummy_d_142 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_154; +reg dummy_d_143; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_req_wdata_ready <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine1_row_close <= 1'd0; + case (bankmachine1_state) 1'd1: begin + litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -6335,34 +5543,19 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine1_refresh_req) begin - end else begin - if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine1_row_opened) begin - if (soc_sdram_bankmachine1_row_hit) begin - if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine1_req_wdata_ready <= soc_sdram_bankmachine1_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_154 = dummy_s; + dummy_d_143 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_155; +reg dummy_d_144; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_req_rdata_valid <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (bankmachine1_state) 1'd1: begin end 2'd2: begin @@ -6380,15 +5573,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine1_refresh_req) begin + if (litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine1_row_opened) begin - if (soc_sdram_bankmachine1_row_hit) begin - if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - soc_sdram_bankmachine1_req_rdata_valid <= soc_sdram_bankmachine1_cmd_ready; - end + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -6398,26 +5588,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_155 = dummy_s; + dummy_d_144 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_156; +reg dummy_d_145; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_refresh_gnt <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end end 3'd4: begin - if (soc_sdram_bankmachine1_twtpcon_ready) begin - soc_sdram_bankmachine1_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -6431,27 +5624,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_156 = dummy_s; + dummy_d_145 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_157; +reg dummy_d_146; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_cmd_valid <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (bankmachine1_state) 1'd1: begin - if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin - soc_sdram_bankmachine1_cmd_valid <= 1'd1; + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine1_trccon_ready) begin - soc_sdram_bankmachine1_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -6464,12 +5654,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine1_refresh_req) begin + if (litedramcore_bankmachine1_refresh_req) begin end else begin - if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine1_row_opened) begin - if (soc_sdram_bankmachine1_row_hit) begin - soc_sdram_bankmachine1_cmd_valid <= 1'd1; + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -6479,26 +5672,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_157 = dummy_s; + dummy_d_146 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_158; +reg dummy_d_147; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_row_open <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine1_trccon_ready) begin - soc_sdram_bankmachine1_row_open <= 1'd1; + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6512,26 +5709,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_158 = dummy_s; + dummy_d_147 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_159; +reg dummy_d_148; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_row_close <= 1'd0; - case (vns_bankmachine1_state) + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (bankmachine1_state) 1'd1: begin - soc_sdram_bankmachine1_row_close <= 1'd1; end 2'd2: begin - soc_sdram_bankmachine1_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_sdram_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -6542,256 +5736,190 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_159 = dummy_s; + dummy_d_148 = dummy_s; // synthesis translate_on end +assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid; +assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr; +assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready; +assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); +assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid); +assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]); +assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; // synthesis translate_off -reg dummy_d_160; +reg dummy_d_149; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_cmd_payload_cas <= 1'd0; - case (vns_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_sdram_bankmachine1_refresh_req) begin - end else begin - if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine1_row_opened) begin - if (soc_sdram_bankmachine1_row_hit) begin - soc_sdram_bankmachine1_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -// synthesis translate_off - dummy_d_160 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_161; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine1_cmd_payload_ras <= 1'd0; - case (vns_bankmachine1_state) - 1'd1: begin - if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin - soc_sdram_bankmachine1_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_sdram_bankmachine1_trccon_ready) begin - soc_sdram_bankmachine1_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_161 = dummy_s; -// synthesis translate_on -end -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine2_req_valid; -assign soc_sdram_bankmachine2_req_ready = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine2_req_we; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine2_req_addr; -assign soc_sdram_bankmachine2_cmd_buffer_sink_valid = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine2_cmd_buffer_sink_ready; -assign soc_sdram_bankmachine2_cmd_buffer_sink_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first; -assign soc_sdram_bankmachine2_cmd_buffer_sink_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last; -assign soc_sdram_bankmachine2_cmd_buffer_sink_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we; -assign soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -assign soc_sdram_bankmachine2_cmd_buffer_source_ready = (soc_sdram_bankmachine2_req_wdata_ready | soc_sdram_bankmachine2_req_rdata_valid); -assign soc_sdram_bankmachine2_req_lock = (soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine2_cmd_buffer_source_valid); -assign soc_sdram_bankmachine2_row_hit = (soc_sdram_bankmachine2_row == soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:7]); -assign soc_sdram_bankmachine2_cmd_payload_ba = 2'd2; - -// synthesis translate_off -reg dummy_d_162; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine2_cmd_payload_a <= 15'd0; - if (soc_sdram_bankmachine2_row_col_n_addr_sel) begin - soc_sdram_bankmachine2_cmd_payload_a <= soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:7]; + litedramcore_bankmachine2_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine2_row_col_n_addr_sel) begin + litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]; end else begin - soc_sdram_bankmachine2_cmd_payload_a <= ((soc_sdram_bankmachine2_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_162 = dummy_s; + dummy_d_149 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine2_twtpcon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_cmd_payload_is_write); -assign soc_sdram_bankmachine2_trccon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_row_open); -assign soc_sdram_bankmachine2_trascon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_row_open); +assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); +assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); +assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); // synthesis translate_off -reg dummy_d_163; +reg dummy_d_150; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_auto_precharge <= 1'd0; - if ((soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine2_cmd_buffer_source_valid)) begin - if ((soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin - soc_sdram_bankmachine2_auto_precharge <= (soc_sdram_bankmachine2_row_close == 1'd0); + litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin + litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); end end // synthesis translate_off - dummy_d_163 = dummy_s; + dummy_d_150 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_first; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_last; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_164; +reg dummy_d_151; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_sdram_bankmachine2_cmd_buffer_lookahead_replace) begin - soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); + litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine2_cmd_buffer_lookahead_produce; + litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_164 = dummy_s; + dummy_d_151 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_sdram_bankmachine2_cmd_buffer_lookahead_replace)); -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine2_cmd_buffer_lookahead_consume; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_sdram_bankmachine2_cmd_buffer_lookahead_level != 5'd16); -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0); -assign soc_sdram_bankmachine2_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine2_cmd_buffer_source_valid) | soc_sdram_bankmachine2_cmd_buffer_source_ready); +assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); +assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_165; +reg dummy_d_152; // synthesis translate_on always @(*) begin - vns_bankmachine2_next_state <= 4'd0; - vns_bankmachine2_next_state <= vns_bankmachine2_state; - case (vns_bankmachine2_state) + bankmachine2_next_state <= 4'd0; + bankmachine2_next_state <= bankmachine2_state; + case (bankmachine2_state) 1'd1: begin - if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin - if (soc_sdram_bankmachine2_cmd_ready) begin - vns_bankmachine2_next_state <= 3'd5; + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + if (litedramcore_bankmachine2_cmd_ready) begin + bankmachine2_next_state <= 3'd5; end end end 2'd2: begin - if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin - vns_bankmachine2_next_state <= 3'd5; + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + bankmachine2_next_state <= 3'd5; end end 2'd3: begin - if (soc_sdram_bankmachine2_trccon_ready) begin - if (soc_sdram_bankmachine2_cmd_ready) begin - vns_bankmachine2_next_state <= 3'd7; + if (litedramcore_bankmachine2_trccon_ready) begin + if (litedramcore_bankmachine2_cmd_ready) begin + bankmachine2_next_state <= 3'd7; end end end 3'd4: begin - if ((~soc_sdram_bankmachine2_refresh_req)) begin - vns_bankmachine2_next_state <= 1'd0; + if ((~litedramcore_bankmachine2_refresh_req)) begin + bankmachine2_next_state <= 1'd0; end end 3'd5: begin - vns_bankmachine2_next_state <= 3'd6; + bankmachine2_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine2_next_state <= 2'd3; + bankmachine2_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine2_next_state <= 4'd8; + bankmachine2_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine2_next_state <= 1'd0; + bankmachine2_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine2_refresh_req) begin - vns_bankmachine2_next_state <= 3'd4; + if (litedramcore_bankmachine2_refresh_req) begin + bankmachine2_next_state <= 3'd4; end else begin - if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine2_row_opened) begin - if (soc_sdram_bankmachine2_row_hit) begin - if ((soc_sdram_bankmachine2_cmd_ready & soc_sdram_bankmachine2_auto_precharge)) begin - vns_bankmachine2_next_state <= 2'd2; + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin + bankmachine2_next_state <= 2'd2; end end else begin - vns_bankmachine2_next_state <= 1'd1; + bankmachine2_next_state <= 1'd1; end end else begin - vns_bankmachine2_next_state <= 2'd3; + bankmachine2_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_165 = dummy_s; + dummy_d_152 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_166; +reg dummy_d_153; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_cmd_payload_we <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (bankmachine2_state) 1'd1: begin - if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin - soc_sdram_bankmachine2_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -6808,13 +5936,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine2_refresh_req) begin + if (litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine2_row_opened) begin - if (soc_sdram_bankmachine2_row_hit) begin - if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine2_cmd_payload_we <= 1'd1; + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -6826,24 +5954,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_166 = dummy_s; + dummy_d_153 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_167; +reg dummy_d_154; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine2_trccon_ready) begin - soc_sdram_bankmachine2_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -6856,33 +5981,41 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_167 = dummy_s; + dummy_d_154 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_168; +reg dummy_d_155; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (bankmachine2_state) 1'd1: begin - if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin - soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine2_trccon_ready) begin - soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6893,19 +6026,34 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_168 = dummy_s; + dummy_d_155 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_169; +reg dummy_d_156; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (bankmachine2_state) 1'd1: begin end 2'd2: begin @@ -6913,6 +6061,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (litedramcore_bankmachine2_twtpcon_ready) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6923,39 +6074,30 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine2_refresh_req) begin - end else begin - if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine2_row_opened) begin - if (soc_sdram_bankmachine2_row_hit) begin - if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - soc_sdram_bankmachine2_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_169 = dummy_s; + dummy_d_156 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_170; +reg dummy_d_157; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (bankmachine2_state) 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -6968,15 +6110,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine2_refresh_req) begin + if (litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine2_row_opened) begin - if (soc_sdram_bankmachine2_row_hit) begin - if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine2_cmd_payload_is_write <= 1'd1; - end else begin - end + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; end else begin end end else begin @@ -6986,21 +6125,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_170 = dummy_s; + dummy_d_157 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_171; +reg dummy_d_158; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_req_wdata_ready <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -7013,39 +6155,27 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine2_refresh_req) begin - end else begin - if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine2_row_opened) begin - if (soc_sdram_bankmachine2_row_hit) begin - if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine2_req_wdata_ready <= soc_sdram_bankmachine2_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_171 = dummy_s; + dummy_d_158 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_172; +reg dummy_d_159; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_req_rdata_valid <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine2_row_open <= 1'd0; + case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_open <= 1'd1; + end end 3'd4: begin end @@ -7058,44 +6188,29 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine2_refresh_req) begin - end else begin - if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine2_row_opened) begin - if (soc_sdram_bankmachine2_row_hit) begin - if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - soc_sdram_bankmachine2_req_rdata_valid <= soc_sdram_bankmachine2_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_172 = dummy_s; + dummy_d_159 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_173; +reg dummy_d_160; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_refresh_gnt <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine2_row_close <= 1'd0; + case (bankmachine2_state) 1'd1: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - if (soc_sdram_bankmachine2_twtpcon_ready) begin - soc_sdram_bankmachine2_refresh_gnt <= 1'd1; - end + litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -7109,27 +6224,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_173 = dummy_s; + dummy_d_160 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_174; +reg dummy_d_161; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_cmd_valid <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (bankmachine2_state) 1'd1: begin - if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin - soc_sdram_bankmachine2_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine2_trccon_ready) begin - soc_sdram_bankmachine2_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -7142,12 +6251,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine2_refresh_req) begin + if (litedramcore_bankmachine2_refresh_req) begin end else begin - if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine2_row_opened) begin - if (soc_sdram_bankmachine2_row_hit) begin - soc_sdram_bankmachine2_cmd_valid <= 1'd1; + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7157,23 +6266,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_174 = dummy_s; + dummy_d_161 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_175; +reg dummy_d_162; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_row_open <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (bankmachine2_state) 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine2_trccon_ready) begin - soc_sdram_bankmachine2_row_open <= 1'd1; + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -7190,26 +6302,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_175 = dummy_s; + dummy_d_162 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_176; +reg dummy_d_163; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_row_close <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (bankmachine2_state) 1'd1: begin - soc_sdram_bankmachine2_row_close <= 1'd1; + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end end 2'd2: begin - soc_sdram_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_sdram_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -7220,26 +6332,48 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_176 = dummy_s; + dummy_d_163 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_177; +reg dummy_d_164; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_cmd_payload_cas <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (bankmachine2_state) 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7250,42 +6384,24 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine2_refresh_req) begin - end else begin - if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine2_row_opened) begin - if (soc_sdram_bankmachine2_row_hit) begin - soc_sdram_bankmachine2_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_177 = dummy_s; + dummy_d_164 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_178; +reg dummy_d_165; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_cmd_payload_ras <= 1'd0; - case (vns_bankmachine2_state) + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (bankmachine2_state) 1'd1: begin - if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin - soc_sdram_bankmachine2_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine2_trccon_ready) begin - soc_sdram_bankmachine2_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -7298,178 +6414,190 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_178 = dummy_s; + dummy_d_165 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine3_req_valid; -assign soc_sdram_bankmachine3_req_ready = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine3_req_we; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine3_req_addr; -assign soc_sdram_bankmachine3_cmd_buffer_sink_valid = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine3_cmd_buffer_sink_ready; -assign soc_sdram_bankmachine3_cmd_buffer_sink_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first; -assign soc_sdram_bankmachine3_cmd_buffer_sink_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last; -assign soc_sdram_bankmachine3_cmd_buffer_sink_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we; -assign soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -assign soc_sdram_bankmachine3_cmd_buffer_source_ready = (soc_sdram_bankmachine3_req_wdata_ready | soc_sdram_bankmachine3_req_rdata_valid); -assign soc_sdram_bankmachine3_req_lock = (soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine3_cmd_buffer_source_valid); -assign soc_sdram_bankmachine3_row_hit = (soc_sdram_bankmachine3_row == soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:7]); -assign soc_sdram_bankmachine3_cmd_payload_ba = 2'd3; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid; +assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr; +assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready; +assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); +assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid); +assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]); +assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; // synthesis translate_off -reg dummy_d_179; +reg dummy_d_166; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_cmd_payload_a <= 15'd0; - if (soc_sdram_bankmachine3_row_col_n_addr_sel) begin - soc_sdram_bankmachine3_cmd_payload_a <= soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:7]; + litedramcore_bankmachine3_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine3_row_col_n_addr_sel) begin + litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]; end else begin - soc_sdram_bankmachine3_cmd_payload_a <= ((soc_sdram_bankmachine3_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_179 = dummy_s; + dummy_d_166 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine3_twtpcon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_cmd_payload_is_write); -assign soc_sdram_bankmachine3_trccon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_row_open); -assign soc_sdram_bankmachine3_trascon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_row_open); +assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); +assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); +assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); // synthesis translate_off -reg dummy_d_180; +reg dummy_d_167; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_auto_precharge <= 1'd0; - if ((soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine3_cmd_buffer_source_valid)) begin - if ((soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin - soc_sdram_bankmachine3_auto_precharge <= (soc_sdram_bankmachine3_row_close == 1'd0); + litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin + litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); end end // synthesis translate_off - dummy_d_180 = dummy_s; + dummy_d_167 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_first; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_last; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_181; +reg dummy_d_168; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_sdram_bankmachine3_cmd_buffer_lookahead_replace) begin - soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); + litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine3_cmd_buffer_lookahead_produce; + litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_181 = dummy_s; + dummy_d_168 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_sdram_bankmachine3_cmd_buffer_lookahead_replace)); -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine3_cmd_buffer_lookahead_consume; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_sdram_bankmachine3_cmd_buffer_lookahead_level != 5'd16); -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0); -assign soc_sdram_bankmachine3_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine3_cmd_buffer_source_valid) | soc_sdram_bankmachine3_cmd_buffer_source_ready); +assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); +assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_182; +reg dummy_d_169; // synthesis translate_on always @(*) begin - vns_bankmachine3_next_state <= 4'd0; - vns_bankmachine3_next_state <= vns_bankmachine3_state; - case (vns_bankmachine3_state) + bankmachine3_next_state <= 4'd0; + bankmachine3_next_state <= bankmachine3_state; + case (bankmachine3_state) 1'd1: begin - if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin - if (soc_sdram_bankmachine3_cmd_ready) begin - vns_bankmachine3_next_state <= 3'd5; + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + if (litedramcore_bankmachine3_cmd_ready) begin + bankmachine3_next_state <= 3'd5; end end end 2'd2: begin - if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin - vns_bankmachine3_next_state <= 3'd5; + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + bankmachine3_next_state <= 3'd5; end end 2'd3: begin - if (soc_sdram_bankmachine3_trccon_ready) begin - if (soc_sdram_bankmachine3_cmd_ready) begin - vns_bankmachine3_next_state <= 3'd7; + if (litedramcore_bankmachine3_trccon_ready) begin + if (litedramcore_bankmachine3_cmd_ready) begin + bankmachine3_next_state <= 3'd7; end end end 3'd4: begin - if ((~soc_sdram_bankmachine3_refresh_req)) begin - vns_bankmachine3_next_state <= 1'd0; + if ((~litedramcore_bankmachine3_refresh_req)) begin + bankmachine3_next_state <= 1'd0; end end 3'd5: begin - vns_bankmachine3_next_state <= 3'd6; + bankmachine3_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine3_next_state <= 2'd3; + bankmachine3_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine3_next_state <= 4'd8; + bankmachine3_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine3_next_state <= 1'd0; + bankmachine3_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine3_refresh_req) begin - vns_bankmachine3_next_state <= 3'd4; + if (litedramcore_bankmachine3_refresh_req) begin + bankmachine3_next_state <= 3'd4; end else begin - if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine3_row_opened) begin - if (soc_sdram_bankmachine3_row_hit) begin - if ((soc_sdram_bankmachine3_cmd_ready & soc_sdram_bankmachine3_auto_precharge)) begin - vns_bankmachine3_next_state <= 2'd2; + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin + bankmachine3_next_state <= 2'd2; end end else begin - vns_bankmachine3_next_state <= 1'd1; + bankmachine3_next_state <= 1'd1; end end else begin - vns_bankmachine3_next_state <= 2'd3; + bankmachine3_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_182 = dummy_s; + dummy_d_169 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_183; +reg dummy_d_170; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_cmd_payload_we <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (bankmachine3_state) 1'd1: begin - if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin - soc_sdram_bankmachine3_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -7486,13 +6614,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine3_refresh_req) begin + if (litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine3_row_opened) begin - if (soc_sdram_bankmachine3_row_hit) begin - if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine3_cmd_payload_we <= 1'd1; + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -7504,24 +6632,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_183 = dummy_s; + dummy_d_170 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_184; +reg dummy_d_171; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine3_trccon_ready) begin - soc_sdram_bankmachine3_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -7534,33 +6659,41 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_184 = dummy_s; + dummy_d_171 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_185; +reg dummy_d_172; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (bankmachine3_state) 1'd1: begin - if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin - soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine3_trccon_ready) begin - soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7571,19 +6704,34 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_185 = dummy_s; + dummy_d_172 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_186; +reg dummy_d_173; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (bankmachine3_state) 1'd1: begin end 2'd2: begin @@ -7591,6 +6739,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (litedramcore_bankmachine3_twtpcon_ready) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7601,39 +6752,30 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine3_refresh_req) begin - end else begin - if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine3_row_opened) begin - if (soc_sdram_bankmachine3_row_hit) begin - if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - soc_sdram_bankmachine3_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_186 = dummy_s; + dummy_d_173 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_187; +reg dummy_d_174; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -7646,15 +6788,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine3_refresh_req) begin + if (litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine3_row_opened) begin - if (soc_sdram_bankmachine3_row_hit) begin - if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine3_cmd_payload_is_write <= 1'd1; - end else begin - end + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; end else begin end end else begin @@ -7664,21 +6803,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_187 = dummy_s; + dummy_d_174 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_188; +reg dummy_d_175; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_req_wdata_ready <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine3_row_open <= 1'd0; + case (bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_open <= 1'd1; + end end 3'd4: begin end @@ -7691,41 +6833,29 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine3_refresh_req) begin - end else begin - if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine3_row_opened) begin - if (soc_sdram_bankmachine3_row_hit) begin - if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine3_req_wdata_ready <= soc_sdram_bankmachine3_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_188 = dummy_s; + dummy_d_175 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_189; +reg dummy_d_176; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_req_rdata_valid <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine3_row_close <= 1'd0; + case (bankmachine3_state) 1'd1: begin + litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -7736,44 +6866,29 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine3_refresh_req) begin - end else begin - if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine3_row_opened) begin - if (soc_sdram_bankmachine3_row_hit) begin - if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - soc_sdram_bankmachine3_req_rdata_valid <= soc_sdram_bankmachine3_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_189 = dummy_s; + dummy_d_176 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_190; +reg dummy_d_177; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_refresh_gnt <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin - if (soc_sdram_bankmachine3_twtpcon_ready) begin - soc_sdram_bankmachine3_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7787,27 +6902,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_190 = dummy_s; + dummy_d_177 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_191; +reg dummy_d_178; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_cmd_valid <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (bankmachine3_state) 1'd1: begin - if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin - soc_sdram_bankmachine3_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine3_trccon_ready) begin - soc_sdram_bankmachine3_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -7820,12 +6929,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine3_refresh_req) begin + if (litedramcore_bankmachine3_refresh_req) begin end else begin - if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine3_row_opened) begin - if (soc_sdram_bankmachine3_row_hit) begin - soc_sdram_bankmachine3_cmd_valid <= 1'd1; + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7835,23 +6944,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_191 = dummy_s; + dummy_d_178 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_192; +reg dummy_d_179; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_row_open <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine3_trccon_ready) begin - soc_sdram_bankmachine3_row_open <= 1'd1; + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -7868,26 +6980,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_192 = dummy_s; + dummy_d_179 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_193; +reg dummy_d_180; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_row_close <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (bankmachine3_state) 1'd1: begin - soc_sdram_bankmachine3_row_close <= 1'd1; + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end end 2'd2: begin - soc_sdram_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_sdram_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -7898,26 +7010,48 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_193 = dummy_s; + dummy_d_180 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_194; +reg dummy_d_181; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_cmd_payload_cas <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7928,42 +7062,24 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine3_refresh_req) begin - end else begin - if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine3_row_opened) begin - if (soc_sdram_bankmachine3_row_hit) begin - soc_sdram_bankmachine3_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_194 = dummy_s; + dummy_d_181 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_195; +reg dummy_d_182; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_cmd_payload_ras <= 1'd0; - case (vns_bankmachine3_state) + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (bankmachine3_state) 1'd1: begin - if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin - soc_sdram_bankmachine3_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine3_trccon_ready) begin - soc_sdram_bankmachine3_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -7976,178 +7092,190 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_195 = dummy_s; + dummy_d_182 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine4_req_valid; -assign soc_sdram_bankmachine4_req_ready = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine4_req_we; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine4_req_addr; -assign soc_sdram_bankmachine4_cmd_buffer_sink_valid = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine4_cmd_buffer_sink_ready; -assign soc_sdram_bankmachine4_cmd_buffer_sink_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first; -assign soc_sdram_bankmachine4_cmd_buffer_sink_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last; -assign soc_sdram_bankmachine4_cmd_buffer_sink_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we; -assign soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -assign soc_sdram_bankmachine4_cmd_buffer_source_ready = (soc_sdram_bankmachine4_req_wdata_ready | soc_sdram_bankmachine4_req_rdata_valid); -assign soc_sdram_bankmachine4_req_lock = (soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine4_cmd_buffer_source_valid); -assign soc_sdram_bankmachine4_row_hit = (soc_sdram_bankmachine4_row == soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[21:7]); -assign soc_sdram_bankmachine4_cmd_payload_ba = 3'd4; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid; +assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr; +assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready; +assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); +assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid); +assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]); +assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; // synthesis translate_off -reg dummy_d_196; +reg dummy_d_183; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_cmd_payload_a <= 15'd0; - if (soc_sdram_bankmachine4_row_col_n_addr_sel) begin - soc_sdram_bankmachine4_cmd_payload_a <= soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[21:7]; + litedramcore_bankmachine4_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine4_row_col_n_addr_sel) begin + litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]; end else begin - soc_sdram_bankmachine4_cmd_payload_a <= ((soc_sdram_bankmachine4_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_196 = dummy_s; + dummy_d_183 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine4_twtpcon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_cmd_payload_is_write); -assign soc_sdram_bankmachine4_trccon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_row_open); -assign soc_sdram_bankmachine4_trascon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_row_open); +assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); +assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); +assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); // synthesis translate_off -reg dummy_d_197; +reg dummy_d_184; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_auto_precharge <= 1'd0; - if ((soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine4_cmd_buffer_source_valid)) begin - if ((soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin - soc_sdram_bankmachine4_auto_precharge <= (soc_sdram_bankmachine4_row_close == 1'd0); + litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin + litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); end end // synthesis translate_off - dummy_d_197 = dummy_s; + dummy_d_184 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_first; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_last; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_198; +reg dummy_d_185; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_sdram_bankmachine4_cmd_buffer_lookahead_replace) begin - soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); + litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine4_cmd_buffer_lookahead_produce; + litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_198 = dummy_s; + dummy_d_185 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_sdram_bankmachine4_cmd_buffer_lookahead_replace)); -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine4_cmd_buffer_lookahead_consume; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_sdram_bankmachine4_cmd_buffer_lookahead_level != 5'd16); -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_sdram_bankmachine4_cmd_buffer_lookahead_level != 1'd0); -assign soc_sdram_bankmachine4_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine4_cmd_buffer_source_valid) | soc_sdram_bankmachine4_cmd_buffer_source_ready); +assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); +assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_199; +reg dummy_d_186; // synthesis translate_on always @(*) begin - vns_bankmachine4_next_state <= 4'd0; - vns_bankmachine4_next_state <= vns_bankmachine4_state; - case (vns_bankmachine4_state) + bankmachine4_next_state <= 4'd0; + bankmachine4_next_state <= bankmachine4_state; + case (bankmachine4_state) 1'd1: begin - if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin - if (soc_sdram_bankmachine4_cmd_ready) begin - vns_bankmachine4_next_state <= 3'd5; + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + if (litedramcore_bankmachine4_cmd_ready) begin + bankmachine4_next_state <= 3'd5; end end end 2'd2: begin - if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin - vns_bankmachine4_next_state <= 3'd5; + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + bankmachine4_next_state <= 3'd5; end end 2'd3: begin - if (soc_sdram_bankmachine4_trccon_ready) begin - if (soc_sdram_bankmachine4_cmd_ready) begin - vns_bankmachine4_next_state <= 3'd7; + if (litedramcore_bankmachine4_trccon_ready) begin + if (litedramcore_bankmachine4_cmd_ready) begin + bankmachine4_next_state <= 3'd7; end end end 3'd4: begin - if ((~soc_sdram_bankmachine4_refresh_req)) begin - vns_bankmachine4_next_state <= 1'd0; + if ((~litedramcore_bankmachine4_refresh_req)) begin + bankmachine4_next_state <= 1'd0; end end 3'd5: begin - vns_bankmachine4_next_state <= 3'd6; + bankmachine4_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine4_next_state <= 2'd3; + bankmachine4_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine4_next_state <= 4'd8; + bankmachine4_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine4_next_state <= 1'd0; + bankmachine4_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine4_refresh_req) begin - vns_bankmachine4_next_state <= 3'd4; + if (litedramcore_bankmachine4_refresh_req) begin + bankmachine4_next_state <= 3'd4; end else begin - if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine4_row_opened) begin - if (soc_sdram_bankmachine4_row_hit) begin - if ((soc_sdram_bankmachine4_cmd_ready & soc_sdram_bankmachine4_auto_precharge)) begin - vns_bankmachine4_next_state <= 2'd2; + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin + bankmachine4_next_state <= 2'd2; end end else begin - vns_bankmachine4_next_state <= 1'd1; + bankmachine4_next_state <= 1'd1; end end else begin - vns_bankmachine4_next_state <= 2'd3; + bankmachine4_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_199 = dummy_s; + dummy_d_186 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_200; +reg dummy_d_187; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_cmd_payload_we <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (bankmachine4_state) 1'd1: begin - if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin - soc_sdram_bankmachine4_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -8164,13 +7292,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine4_refresh_req) begin + if (litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine4_row_opened) begin - if (soc_sdram_bankmachine4_row_hit) begin - if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine4_cmd_payload_we <= 1'd1; + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -8182,24 +7310,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_200 = dummy_s; + dummy_d_187 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_201; +reg dummy_d_188; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine4_trccon_ready) begin - soc_sdram_bankmachine4_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -8212,33 +7337,41 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_201 = dummy_s; + dummy_d_188 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_202; +reg dummy_d_189; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (bankmachine4_state) 1'd1: begin - if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin - soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine4_trccon_ready) begin - soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8249,19 +7382,34 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_202 = dummy_s; + dummy_d_189 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_203; +reg dummy_d_190; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (bankmachine4_state) 1'd1: begin end 2'd2: begin @@ -8269,6 +7417,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (litedramcore_bankmachine4_twtpcon_ready) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8279,39 +7430,30 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine4_refresh_req) begin - end else begin - if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine4_row_opened) begin - if (soc_sdram_bankmachine4_row_hit) begin - if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - soc_sdram_bankmachine4_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_203 = dummy_s; + dummy_d_190 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_204; +reg dummy_d_191; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -8324,15 +7466,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine4_refresh_req) begin + if (litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine4_row_opened) begin - if (soc_sdram_bankmachine4_row_hit) begin - if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine4_cmd_payload_is_write <= 1'd1; - end else begin - end + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; end else begin end end else begin @@ -8342,21 +7481,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_204 = dummy_s; + dummy_d_191 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_205; +reg dummy_d_192; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_req_wdata_ready <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -8369,39 +7511,27 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine4_refresh_req) begin - end else begin - if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine4_row_opened) begin - if (soc_sdram_bankmachine4_row_hit) begin - if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine4_req_wdata_ready <= soc_sdram_bankmachine4_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_205 = dummy_s; + dummy_d_192 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_206; +reg dummy_d_193; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_req_rdata_valid <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine4_row_open <= 1'd0; + case (bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_open <= 1'd1; + end end 3'd4: begin end @@ -8414,44 +7544,29 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine4_refresh_req) begin - end else begin - if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine4_row_opened) begin - if (soc_sdram_bankmachine4_row_hit) begin - if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - soc_sdram_bankmachine4_req_rdata_valid <= soc_sdram_bankmachine4_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_206 = dummy_s; + dummy_d_193 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_207; +reg dummy_d_194; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_refresh_gnt <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine4_row_close <= 1'd0; + case (bankmachine4_state) 1'd1: begin + litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - if (soc_sdram_bankmachine4_twtpcon_ready) begin - soc_sdram_bankmachine4_refresh_gnt <= 1'd1; - end + litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -8465,27 +7580,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_207 = dummy_s; + dummy_d_194 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_208; +reg dummy_d_195; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_cmd_valid <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (bankmachine4_state) 1'd1: begin - if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin - soc_sdram_bankmachine4_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine4_trccon_ready) begin - soc_sdram_bankmachine4_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -8498,12 +7607,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine4_refresh_req) begin + if (litedramcore_bankmachine4_refresh_req) begin end else begin - if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine4_row_opened) begin - if (soc_sdram_bankmachine4_row_hit) begin - soc_sdram_bankmachine4_cmd_valid <= 1'd1; + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -8513,23 +7622,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_208 = dummy_s; + dummy_d_195 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_209; +reg dummy_d_196; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_row_open <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine4_trccon_ready) begin - soc_sdram_bankmachine4_row_open <= 1'd1; + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -8546,26 +7658,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_209 = dummy_s; + dummy_d_196 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_210; +reg dummy_d_197; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_row_close <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (bankmachine4_state) 1'd1: begin - soc_sdram_bankmachine4_row_close <= 1'd1; + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end end 2'd2: begin - soc_sdram_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_sdram_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -8576,26 +7688,48 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_210 = dummy_s; + dummy_d_197 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_211; +reg dummy_d_198; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_cmd_payload_cas <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8606,42 +7740,24 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine4_refresh_req) begin - end else begin - if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine4_row_opened) begin - if (soc_sdram_bankmachine4_row_hit) begin - soc_sdram_bankmachine4_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_211 = dummy_s; + dummy_d_198 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_212; +reg dummy_d_199; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_cmd_payload_ras <= 1'd0; - case (vns_bankmachine4_state) + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (bankmachine4_state) 1'd1: begin - if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin - soc_sdram_bankmachine4_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine4_trccon_ready) begin - soc_sdram_bankmachine4_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -8654,178 +7770,190 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_212 = dummy_s; + dummy_d_199 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine5_req_valid; -assign soc_sdram_bankmachine5_req_ready = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine5_req_we; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine5_req_addr; -assign soc_sdram_bankmachine5_cmd_buffer_sink_valid = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine5_cmd_buffer_sink_ready; -assign soc_sdram_bankmachine5_cmd_buffer_sink_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first; -assign soc_sdram_bankmachine5_cmd_buffer_sink_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last; -assign soc_sdram_bankmachine5_cmd_buffer_sink_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we; -assign soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -assign soc_sdram_bankmachine5_cmd_buffer_source_ready = (soc_sdram_bankmachine5_req_wdata_ready | soc_sdram_bankmachine5_req_rdata_valid); -assign soc_sdram_bankmachine5_req_lock = (soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine5_cmd_buffer_source_valid); -assign soc_sdram_bankmachine5_row_hit = (soc_sdram_bankmachine5_row == soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[21:7]); -assign soc_sdram_bankmachine5_cmd_payload_ba = 3'd5; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid; +assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr; +assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready; +assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); +assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid); +assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]); +assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; // synthesis translate_off -reg dummy_d_213; +reg dummy_d_200; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_cmd_payload_a <= 15'd0; - if (soc_sdram_bankmachine5_row_col_n_addr_sel) begin - soc_sdram_bankmachine5_cmd_payload_a <= soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[21:7]; + litedramcore_bankmachine5_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine5_row_col_n_addr_sel) begin + litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]; end else begin - soc_sdram_bankmachine5_cmd_payload_a <= ((soc_sdram_bankmachine5_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_213 = dummy_s; + dummy_d_200 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine5_twtpcon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_cmd_payload_is_write); -assign soc_sdram_bankmachine5_trccon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_row_open); -assign soc_sdram_bankmachine5_trascon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_row_open); +assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); +assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); +assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); // synthesis translate_off -reg dummy_d_214; +reg dummy_d_201; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_auto_precharge <= 1'd0; - if ((soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine5_cmd_buffer_source_valid)) begin - if ((soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin - soc_sdram_bankmachine5_auto_precharge <= (soc_sdram_bankmachine5_row_close == 1'd0); + litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin + litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); end end // synthesis translate_off - dummy_d_214 = dummy_s; + dummy_d_201 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_first; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_last; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_215; +reg dummy_d_202; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_sdram_bankmachine5_cmd_buffer_lookahead_replace) begin - soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); + litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine5_cmd_buffer_lookahead_produce; + litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_215 = dummy_s; + dummy_d_202 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_sdram_bankmachine5_cmd_buffer_lookahead_replace)); -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine5_cmd_buffer_lookahead_consume; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_sdram_bankmachine5_cmd_buffer_lookahead_level != 5'd16); -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_sdram_bankmachine5_cmd_buffer_lookahead_level != 1'd0); -assign soc_sdram_bankmachine5_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine5_cmd_buffer_source_valid) | soc_sdram_bankmachine5_cmd_buffer_source_ready); +assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); +assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_216; +reg dummy_d_203; // synthesis translate_on always @(*) begin - vns_bankmachine5_next_state <= 4'd0; - vns_bankmachine5_next_state <= vns_bankmachine5_state; - case (vns_bankmachine5_state) + bankmachine5_next_state <= 4'd0; + bankmachine5_next_state <= bankmachine5_state; + case (bankmachine5_state) 1'd1: begin - if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin - if (soc_sdram_bankmachine5_cmd_ready) begin - vns_bankmachine5_next_state <= 3'd5; + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + if (litedramcore_bankmachine5_cmd_ready) begin + bankmachine5_next_state <= 3'd5; end end end 2'd2: begin - if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin - vns_bankmachine5_next_state <= 3'd5; + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + bankmachine5_next_state <= 3'd5; end end 2'd3: begin - if (soc_sdram_bankmachine5_trccon_ready) begin - if (soc_sdram_bankmachine5_cmd_ready) begin - vns_bankmachine5_next_state <= 3'd7; + if (litedramcore_bankmachine5_trccon_ready) begin + if (litedramcore_bankmachine5_cmd_ready) begin + bankmachine5_next_state <= 3'd7; end end end 3'd4: begin - if ((~soc_sdram_bankmachine5_refresh_req)) begin - vns_bankmachine5_next_state <= 1'd0; + if ((~litedramcore_bankmachine5_refresh_req)) begin + bankmachine5_next_state <= 1'd0; end end 3'd5: begin - vns_bankmachine5_next_state <= 3'd6; + bankmachine5_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine5_next_state <= 2'd3; + bankmachine5_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine5_next_state <= 4'd8; + bankmachine5_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine5_next_state <= 1'd0; + bankmachine5_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine5_refresh_req) begin - vns_bankmachine5_next_state <= 3'd4; + if (litedramcore_bankmachine5_refresh_req) begin + bankmachine5_next_state <= 3'd4; end else begin - if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine5_row_opened) begin - if (soc_sdram_bankmachine5_row_hit) begin - if ((soc_sdram_bankmachine5_cmd_ready & soc_sdram_bankmachine5_auto_precharge)) begin - vns_bankmachine5_next_state <= 2'd2; + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin + bankmachine5_next_state <= 2'd2; end end else begin - vns_bankmachine5_next_state <= 1'd1; + bankmachine5_next_state <= 1'd1; end end else begin - vns_bankmachine5_next_state <= 2'd3; + bankmachine5_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_216 = dummy_s; + dummy_d_203 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_217; +reg dummy_d_204; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_cmd_payload_we <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (bankmachine5_state) 1'd1: begin - if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin - soc_sdram_bankmachine5_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -8842,13 +7970,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine5_refresh_req) begin + if (litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine5_row_opened) begin - if (soc_sdram_bankmachine5_row_hit) begin - if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine5_cmd_payload_we <= 1'd1; + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -8860,24 +7988,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_217 = dummy_s; + dummy_d_204 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_218; +reg dummy_d_205; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine5_trccon_ready) begin - soc_sdram_bankmachine5_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -8890,33 +8015,41 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_218 = dummy_s; + dummy_d_205 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_219; +reg dummy_d_206; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (bankmachine5_state) 1'd1: begin - if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin - soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine5_trccon_ready) begin - soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8927,24 +8060,42 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_219 = dummy_s; + dummy_d_206 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_220; +reg dummy_d_207; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -8957,34 +8108,19 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine5_refresh_req) begin - end else begin - if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine5_row_opened) begin - if (soc_sdram_bankmachine5_row_hit) begin - if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - soc_sdram_bankmachine5_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_220 = dummy_s; + dummy_d_207 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_221; +reg dummy_d_208; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (bankmachine5_state) 1'd1: begin end 2'd2: begin @@ -8992,6 +8128,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9002,39 +8141,30 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine5_refresh_req) begin - end else begin - if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine5_row_opened) begin - if (soc_sdram_bankmachine5_row_hit) begin - if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine5_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_221 = dummy_s; + dummy_d_208 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_222; +reg dummy_d_209; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_req_wdata_ready <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -9047,15 +8177,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine5_refresh_req) begin + if (litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine5_row_opened) begin - if (soc_sdram_bankmachine5_row_hit) begin - if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine5_req_wdata_ready <= soc_sdram_bankmachine5_cmd_ready; - end else begin - end + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; end else begin end end else begin @@ -9065,21 +8192,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_222 = dummy_s; + dummy_d_209 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_223; +reg dummy_d_210; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_req_rdata_valid <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine5_row_open <= 1'd0; + case (bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_open <= 1'd1; + end end 3'd4: begin end @@ -9092,44 +8222,29 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine5_refresh_req) begin - end else begin - if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine5_row_opened) begin - if (soc_sdram_bankmachine5_row_hit) begin - if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - soc_sdram_bankmachine5_req_rdata_valid <= soc_sdram_bankmachine5_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_223 = dummy_s; + dummy_d_210 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_224; +reg dummy_d_211; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_refresh_gnt <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine5_row_close <= 1'd0; + case (bankmachine5_state) 1'd1: begin + litedramcore_bankmachine5_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - if (soc_sdram_bankmachine5_twtpcon_ready) begin - soc_sdram_bankmachine5_refresh_gnt <= 1'd1; - end + litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -9143,27 +8258,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_224 = dummy_s; + dummy_d_211 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_225; +reg dummy_d_212; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_cmd_valid <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (bankmachine5_state) 1'd1: begin - if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin - soc_sdram_bankmachine5_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine5_trccon_ready) begin - soc_sdram_bankmachine5_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -9176,12 +8285,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine5_refresh_req) begin + if (litedramcore_bankmachine5_refresh_req) begin end else begin - if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine5_row_opened) begin - if (soc_sdram_bankmachine5_row_hit) begin - soc_sdram_bankmachine5_cmd_valid <= 1'd1; + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -9191,23 +8300,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_225 = dummy_s; + dummy_d_212 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_226; +reg dummy_d_213; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_row_open <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine5_trccon_ready) begin - soc_sdram_bankmachine5_row_open <= 1'd1; + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -9224,26 +8336,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_226 = dummy_s; + dummy_d_213 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_227; +reg dummy_d_214; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_row_close <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (bankmachine5_state) 1'd1: begin - soc_sdram_bankmachine5_row_close <= 1'd1; + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end end 2'd2: begin - soc_sdram_bankmachine5_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_sdram_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -9254,26 +8366,48 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_227 = dummy_s; + dummy_d_214 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_228; +reg dummy_d_215; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_cmd_payload_cas <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9284,42 +8418,24 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine5_refresh_req) begin - end else begin - if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine5_row_opened) begin - if (soc_sdram_bankmachine5_row_hit) begin - soc_sdram_bankmachine5_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_228 = dummy_s; + dummy_d_215 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_229; +reg dummy_d_216; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_cmd_payload_ras <= 1'd0; - case (vns_bankmachine5_state) + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (bankmachine5_state) 1'd1: begin - if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin - soc_sdram_bankmachine5_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine5_trccon_ready) begin - soc_sdram_bankmachine5_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -9332,178 +8448,190 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_229 = dummy_s; + dummy_d_216 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine6_req_valid; -assign soc_sdram_bankmachine6_req_ready = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine6_req_we; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine6_req_addr; -assign soc_sdram_bankmachine6_cmd_buffer_sink_valid = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine6_cmd_buffer_sink_ready; -assign soc_sdram_bankmachine6_cmd_buffer_sink_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first; -assign soc_sdram_bankmachine6_cmd_buffer_sink_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last; -assign soc_sdram_bankmachine6_cmd_buffer_sink_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we; -assign soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -assign soc_sdram_bankmachine6_cmd_buffer_source_ready = (soc_sdram_bankmachine6_req_wdata_ready | soc_sdram_bankmachine6_req_rdata_valid); -assign soc_sdram_bankmachine6_req_lock = (soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine6_cmd_buffer_source_valid); -assign soc_sdram_bankmachine6_row_hit = (soc_sdram_bankmachine6_row == soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[21:7]); -assign soc_sdram_bankmachine6_cmd_payload_ba = 3'd6; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid; +assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr; +assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready; +assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); +assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid); +assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]); +assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; // synthesis translate_off -reg dummy_d_230; +reg dummy_d_217; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_cmd_payload_a <= 15'd0; - if (soc_sdram_bankmachine6_row_col_n_addr_sel) begin - soc_sdram_bankmachine6_cmd_payload_a <= soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[21:7]; + litedramcore_bankmachine6_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine6_row_col_n_addr_sel) begin + litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]; end else begin - soc_sdram_bankmachine6_cmd_payload_a <= ((soc_sdram_bankmachine6_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_230 = dummy_s; + dummy_d_217 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine6_twtpcon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_cmd_payload_is_write); -assign soc_sdram_bankmachine6_trccon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_row_open); -assign soc_sdram_bankmachine6_trascon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_row_open); +assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); +assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); +assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); // synthesis translate_off -reg dummy_d_231; +reg dummy_d_218; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_auto_precharge <= 1'd0; - if ((soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine6_cmd_buffer_source_valid)) begin - if ((soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin - soc_sdram_bankmachine6_auto_precharge <= (soc_sdram_bankmachine6_row_close == 1'd0); + litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin + litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); end end // synthesis translate_off - dummy_d_231 = dummy_s; + dummy_d_218 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_first; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_last; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_232; +reg dummy_d_219; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_sdram_bankmachine6_cmd_buffer_lookahead_replace) begin - soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); + litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine6_cmd_buffer_lookahead_produce; + litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_232 = dummy_s; + dummy_d_219 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_sdram_bankmachine6_cmd_buffer_lookahead_replace)); -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine6_cmd_buffer_lookahead_consume; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_sdram_bankmachine6_cmd_buffer_lookahead_level != 5'd16); -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_sdram_bankmachine6_cmd_buffer_lookahead_level != 1'd0); -assign soc_sdram_bankmachine6_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine6_cmd_buffer_source_valid) | soc_sdram_bankmachine6_cmd_buffer_source_ready); +assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); +assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_233; +reg dummy_d_220; // synthesis translate_on always @(*) begin - vns_bankmachine6_next_state <= 4'd0; - vns_bankmachine6_next_state <= vns_bankmachine6_state; - case (vns_bankmachine6_state) + bankmachine6_next_state <= 4'd0; + bankmachine6_next_state <= bankmachine6_state; + case (bankmachine6_state) 1'd1: begin - if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin - if (soc_sdram_bankmachine6_cmd_ready) begin - vns_bankmachine6_next_state <= 3'd5; + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + if (litedramcore_bankmachine6_cmd_ready) begin + bankmachine6_next_state <= 3'd5; end end end 2'd2: begin - if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin - vns_bankmachine6_next_state <= 3'd5; + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + bankmachine6_next_state <= 3'd5; end end 2'd3: begin - if (soc_sdram_bankmachine6_trccon_ready) begin - if (soc_sdram_bankmachine6_cmd_ready) begin - vns_bankmachine6_next_state <= 3'd7; + if (litedramcore_bankmachine6_trccon_ready) begin + if (litedramcore_bankmachine6_cmd_ready) begin + bankmachine6_next_state <= 3'd7; end end end 3'd4: begin - if ((~soc_sdram_bankmachine6_refresh_req)) begin - vns_bankmachine6_next_state <= 1'd0; + if ((~litedramcore_bankmachine6_refresh_req)) begin + bankmachine6_next_state <= 1'd0; end end 3'd5: begin - vns_bankmachine6_next_state <= 3'd6; + bankmachine6_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine6_next_state <= 2'd3; + bankmachine6_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine6_next_state <= 4'd8; + bankmachine6_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine6_next_state <= 1'd0; + bankmachine6_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine6_refresh_req) begin - vns_bankmachine6_next_state <= 3'd4; + if (litedramcore_bankmachine6_refresh_req) begin + bankmachine6_next_state <= 3'd4; end else begin - if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine6_row_opened) begin - if (soc_sdram_bankmachine6_row_hit) begin - if ((soc_sdram_bankmachine6_cmd_ready & soc_sdram_bankmachine6_auto_precharge)) begin - vns_bankmachine6_next_state <= 2'd2; + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin + bankmachine6_next_state <= 2'd2; end end else begin - vns_bankmachine6_next_state <= 1'd1; + bankmachine6_next_state <= 1'd1; end end else begin - vns_bankmachine6_next_state <= 2'd3; + bankmachine6_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_233 = dummy_s; + dummy_d_220 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_234; +reg dummy_d_221; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_cmd_payload_we <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (bankmachine6_state) 1'd1: begin - if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin - soc_sdram_bankmachine6_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -9520,13 +8648,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine6_refresh_req) begin + if (litedramcore_bankmachine6_refresh_req) begin end else begin - if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine6_row_opened) begin - if (soc_sdram_bankmachine6_row_hit) begin - if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine6_cmd_payload_we <= 1'd1; + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -9538,24 +8666,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_234 = dummy_s; + dummy_d_221 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_235; +reg dummy_d_222; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine6_trccon_ready) begin - soc_sdram_bankmachine6_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -9568,33 +8693,41 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_235 = dummy_s; + dummy_d_222 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_236; +reg dummy_d_223; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (bankmachine6_state) 1'd1: begin - if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin - soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine6_trccon_ready) begin - soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9605,19 +8738,34 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_236 = dummy_s; + dummy_d_223 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_237; +reg dummy_d_224; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (bankmachine6_state) 1'd1: begin end 2'd2: begin @@ -9625,6 +8773,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (litedramcore_bankmachine6_twtpcon_ready) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9635,39 +8786,30 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine6_refresh_req) begin - end else begin - if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine6_row_opened) begin - if (soc_sdram_bankmachine6_row_hit) begin - if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - soc_sdram_bankmachine6_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_237 = dummy_s; + dummy_d_224 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_238; +reg dummy_d_225; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -9680,15 +8822,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine6_refresh_req) begin + if (litedramcore_bankmachine6_refresh_req) begin end else begin - if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine6_row_opened) begin - if (soc_sdram_bankmachine6_row_hit) begin - if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine6_cmd_payload_is_write <= 1'd1; - end else begin - end + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; end else begin end end else begin @@ -9698,21 +8837,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_238 = dummy_s; + dummy_d_225 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_239; +reg dummy_d_226; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_req_wdata_ready <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -9725,39 +8867,27 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine6_refresh_req) begin - end else begin - if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine6_row_opened) begin - if (soc_sdram_bankmachine6_row_hit) begin - if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine6_req_wdata_ready <= soc_sdram_bankmachine6_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_239 = dummy_s; + dummy_d_226 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_240; +reg dummy_d_227; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_req_rdata_valid <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine6_row_open <= 1'd0; + case (bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_open <= 1'd1; + end end 3'd4: begin end @@ -9770,44 +8900,29 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine6_refresh_req) begin - end else begin - if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine6_row_opened) begin - if (soc_sdram_bankmachine6_row_hit) begin - if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - soc_sdram_bankmachine6_req_rdata_valid <= soc_sdram_bankmachine6_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_240 = dummy_s; + dummy_d_227 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_241; +reg dummy_d_228; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_refresh_gnt <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine6_row_close <= 1'd0; + case (bankmachine6_state) 1'd1: begin + litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - if (soc_sdram_bankmachine6_twtpcon_ready) begin - soc_sdram_bankmachine6_refresh_gnt <= 1'd1; - end + litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -9821,27 +8936,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_241 = dummy_s; + dummy_d_228 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_242; +reg dummy_d_229; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_cmd_valid <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (bankmachine6_state) 1'd1: begin - if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin - soc_sdram_bankmachine6_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine6_trccon_ready) begin - soc_sdram_bankmachine6_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -9854,12 +8963,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine6_refresh_req) begin + if (litedramcore_bankmachine6_refresh_req) begin end else begin - if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine6_row_opened) begin - if (soc_sdram_bankmachine6_row_hit) begin - soc_sdram_bankmachine6_cmd_valid <= 1'd1; + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -9869,23 +8978,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_242 = dummy_s; + dummy_d_229 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_243; +reg dummy_d_230; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_row_open <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine6_trccon_ready) begin - soc_sdram_bankmachine6_row_open <= 1'd1; + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -9902,26 +9014,26 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_243 = dummy_s; + dummy_d_230 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_244; +reg dummy_d_231; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_row_close <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (bankmachine6_state) 1'd1: begin - soc_sdram_bankmachine6_row_close <= 1'd1; + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end end 2'd2: begin - soc_sdram_bankmachine6_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_sdram_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -9932,26 +9044,48 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_244 = dummy_s; + dummy_d_231 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_245; +reg dummy_d_232; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_cmd_payload_cas <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9962,42 +9096,24 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine6_refresh_req) begin - end else begin - if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine6_row_opened) begin - if (soc_sdram_bankmachine6_row_hit) begin - soc_sdram_bankmachine6_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_245 = dummy_s; + dummy_d_232 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_246; +reg dummy_d_233; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_cmd_payload_ras <= 1'd0; - case (vns_bankmachine6_state) + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (bankmachine6_state) 1'd1: begin - if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin - soc_sdram_bankmachine6_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine6_trccon_ready) begin - soc_sdram_bankmachine6_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -10010,178 +9126,190 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_246 = dummy_s; + dummy_d_233 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine7_req_valid; -assign soc_sdram_bankmachine7_req_ready = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine7_req_we; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine7_req_addr; -assign soc_sdram_bankmachine7_cmd_buffer_sink_valid = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine7_cmd_buffer_sink_ready; -assign soc_sdram_bankmachine7_cmd_buffer_sink_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first; -assign soc_sdram_bankmachine7_cmd_buffer_sink_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last; -assign soc_sdram_bankmachine7_cmd_buffer_sink_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we; -assign soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -assign soc_sdram_bankmachine7_cmd_buffer_source_ready = (soc_sdram_bankmachine7_req_wdata_ready | soc_sdram_bankmachine7_req_rdata_valid); -assign soc_sdram_bankmachine7_req_lock = (soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine7_cmd_buffer_source_valid); -assign soc_sdram_bankmachine7_row_hit = (soc_sdram_bankmachine7_row == soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[21:7]); -assign soc_sdram_bankmachine7_cmd_payload_ba = 3'd7; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid; +assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr; +assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready; +assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); +assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid); +assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]); +assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; // synthesis translate_off -reg dummy_d_247; +reg dummy_d_234; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_cmd_payload_a <= 15'd0; - if (soc_sdram_bankmachine7_row_col_n_addr_sel) begin - soc_sdram_bankmachine7_cmd_payload_a <= soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[21:7]; + litedramcore_bankmachine7_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine7_row_col_n_addr_sel) begin + litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]; end else begin - soc_sdram_bankmachine7_cmd_payload_a <= ((soc_sdram_bankmachine7_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end // synthesis translate_off - dummy_d_247 = dummy_s; + dummy_d_234 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine7_twtpcon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_cmd_payload_is_write); -assign soc_sdram_bankmachine7_trccon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_row_open); -assign soc_sdram_bankmachine7_trascon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_row_open); +assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); +assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); +assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); // synthesis translate_off -reg dummy_d_248; +reg dummy_d_235; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_auto_precharge <= 1'd0; - if ((soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine7_cmd_buffer_source_valid)) begin - if ((soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin - soc_sdram_bankmachine7_auto_precharge <= (soc_sdram_bankmachine7_row_close == 1'd0); + litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin + litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); end end // synthesis translate_off - dummy_d_248 = dummy_s; + dummy_d_235 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_first; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_last; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; // synthesis translate_off -reg dummy_d_249; +reg dummy_d_236; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_sdram_bankmachine7_cmd_buffer_lookahead_replace) begin - soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); + litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine7_cmd_buffer_lookahead_produce; + litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce; end // synthesis translate_off - dummy_d_249 = dummy_s; + dummy_d_236 = dummy_s; // synthesis translate_on end -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_sdram_bankmachine7_cmd_buffer_lookahead_replace)); -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine7_cmd_buffer_lookahead_consume; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_sdram_bankmachine7_cmd_buffer_lookahead_level != 5'd16); -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_sdram_bankmachine7_cmd_buffer_lookahead_level != 1'd0); -assign soc_sdram_bankmachine7_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine7_cmd_buffer_source_valid) | soc_sdram_bankmachine7_cmd_buffer_source_ready); +assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); +assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready); // synthesis translate_off -reg dummy_d_250; +reg dummy_d_237; // synthesis translate_on always @(*) begin - vns_bankmachine7_next_state <= 4'd0; - vns_bankmachine7_next_state <= vns_bankmachine7_state; - case (vns_bankmachine7_state) + bankmachine7_next_state <= 4'd0; + bankmachine7_next_state <= bankmachine7_state; + case (bankmachine7_state) 1'd1: begin - if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin - if (soc_sdram_bankmachine7_cmd_ready) begin - vns_bankmachine7_next_state <= 3'd5; + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + if (litedramcore_bankmachine7_cmd_ready) begin + bankmachine7_next_state <= 3'd5; end end end 2'd2: begin - if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin - vns_bankmachine7_next_state <= 3'd5; + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + bankmachine7_next_state <= 3'd5; end end 2'd3: begin - if (soc_sdram_bankmachine7_trccon_ready) begin - if (soc_sdram_bankmachine7_cmd_ready) begin - vns_bankmachine7_next_state <= 3'd7; + if (litedramcore_bankmachine7_trccon_ready) begin + if (litedramcore_bankmachine7_cmd_ready) begin + bankmachine7_next_state <= 3'd7; end end end 3'd4: begin - if ((~soc_sdram_bankmachine7_refresh_req)) begin - vns_bankmachine7_next_state <= 1'd0; + if ((~litedramcore_bankmachine7_refresh_req)) begin + bankmachine7_next_state <= 1'd0; end end 3'd5: begin - vns_bankmachine7_next_state <= 3'd6; + bankmachine7_next_state <= 3'd6; end 3'd6: begin - vns_bankmachine7_next_state <= 2'd3; + bankmachine7_next_state <= 2'd3; end 3'd7: begin - vns_bankmachine7_next_state <= 4'd8; + bankmachine7_next_state <= 4'd8; end 4'd8: begin - vns_bankmachine7_next_state <= 1'd0; + bankmachine7_next_state <= 1'd0; end default: begin - if (soc_sdram_bankmachine7_refresh_req) begin - vns_bankmachine7_next_state <= 3'd4; + if (litedramcore_bankmachine7_refresh_req) begin + bankmachine7_next_state <= 3'd4; end else begin - if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine7_row_opened) begin - if (soc_sdram_bankmachine7_row_hit) begin - if ((soc_sdram_bankmachine7_cmd_ready & soc_sdram_bankmachine7_auto_precharge)) begin - vns_bankmachine7_next_state <= 2'd2; + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin + bankmachine7_next_state <= 2'd2; end end else begin - vns_bankmachine7_next_state <= 1'd1; + bankmachine7_next_state <= 1'd1; end end else begin - vns_bankmachine7_next_state <= 2'd3; + bankmachine7_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_250 = dummy_s; + dummy_d_237 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_251; +reg dummy_d_238; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_cmd_payload_we <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (bankmachine7_state) 1'd1: begin - if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin - soc_sdram_bankmachine7_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -10198,13 +9326,13 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine7_refresh_req) begin + if (litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine7_row_opened) begin - if (soc_sdram_bankmachine7_row_hit) begin - if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine7_cmd_payload_we <= 1'd1; + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -10216,24 +9344,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_251 = dummy_s; + dummy_d_238 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_252; +reg dummy_d_239; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine7_trccon_ready) begin - soc_sdram_bankmachine7_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -10246,56 +9371,34 @@ always @(*) begin 4'd8: begin end default: begin - end - endcase -// synthesis translate_off - dummy_d_252 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_253; -// synthesis translate_on -always @(*) begin - soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (vns_bankmachine7_state) - 1'd1: begin - if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin - soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_sdram_bankmachine7_trccon_ready) begin - soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end end end - 3'd4: begin - soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end endcase // synthesis translate_off - dummy_d_253 = dummy_s; + dummy_d_239 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_254; +reg dummy_d_240; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_cmd_payload_is_read <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -10313,14 +9416,14 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine7_refresh_req) begin + if (litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine7_row_opened) begin - if (soc_sdram_bankmachine7_row_hit) begin - if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin end else begin - soc_sdram_bankmachine7_cmd_payload_is_read <= 1'd1; + litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -10331,16 +9434,16 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_254 = dummy_s; + dummy_d_240 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_255; +reg dummy_d_241; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_cmd_payload_is_write <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (bankmachine7_state) 1'd1: begin end 2'd2: begin @@ -10348,6 +9451,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (litedramcore_bankmachine7_twtpcon_ready) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -10358,39 +9464,30 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine7_refresh_req) begin - end else begin - if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine7_row_opened) begin - if (soc_sdram_bankmachine7_row_hit) begin - if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine7_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_255 = dummy_s; + dummy_d_241 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_256; +reg dummy_d_242; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_req_wdata_ready <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -10403,15 +9500,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine7_refresh_req) begin + if (litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine7_row_opened) begin - if (soc_sdram_bankmachine7_row_hit) begin - if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin - soc_sdram_bankmachine7_req_wdata_ready <= soc_sdram_bankmachine7_cmd_ready; - end else begin - end + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; end else begin end end else begin @@ -10421,21 +9515,24 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_256 = dummy_s; + dummy_d_242 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_257; +reg dummy_d_243; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_req_rdata_valid <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_bankmachine7_row_open <= 1'd0; + case (bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_open <= 1'd1; + end end 3'd4: begin end @@ -10448,44 +9545,29 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine7_refresh_req) begin - end else begin - if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine7_row_opened) begin - if (soc_sdram_bankmachine7_row_hit) begin - if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - soc_sdram_bankmachine7_req_rdata_valid <= soc_sdram_bankmachine7_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off - dummy_d_257 = dummy_s; + dummy_d_243 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_258; +reg dummy_d_244; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_refresh_gnt <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_bankmachine7_row_close <= 1'd0; + case (bankmachine7_state) 1'd1: begin + litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - if (soc_sdram_bankmachine7_twtpcon_ready) begin - soc_sdram_bankmachine7_refresh_gnt <= 1'd1; - end + litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -10499,27 +9581,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_258 = dummy_s; + dummy_d_244 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_259; +reg dummy_d_245; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_cmd_valid <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (bankmachine7_state) 1'd1: begin - if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin - soc_sdram_bankmachine7_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine7_trccon_ready) begin - soc_sdram_bankmachine7_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -10532,12 +9608,12 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine7_refresh_req) begin + if (litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine7_row_opened) begin - if (soc_sdram_bankmachine7_row_hit) begin - soc_sdram_bankmachine7_cmd_valid <= 1'd1; + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -10547,23 +9623,23 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_259 = dummy_s; + dummy_d_245 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_260; +reg dummy_d_246; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_row_open <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine7_trccon_ready) begin - soc_sdram_bankmachine7_row_open <= 1'd1; + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -10580,26 +9656,29 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_260 = dummy_s; + dummy_d_246 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_261; +reg dummy_d_247; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_row_close <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (bankmachine7_state) 1'd1: begin - soc_sdram_bankmachine7_row_close <= 1'd1; + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end end 2'd2: begin - soc_sdram_bankmachine7_row_close <= 1'd1; end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end end 3'd4: begin - soc_sdram_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -10613,17 +9692,20 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_261 = dummy_s; + dummy_d_247 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_262; +reg dummy_d_248; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_cmd_payload_cas <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -10640,12 +9722,15 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_sdram_bankmachine7_refresh_req) begin + if (litedramcore_bankmachine7_refresh_req) begin end else begin - if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin - if (soc_sdram_bankmachine7_row_opened) begin - if (soc_sdram_bankmachine7_row_hit) begin - soc_sdram_bankmachine7_cmd_payload_cas <= 1'd1; + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -10655,29 +9740,30 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_262 = dummy_s; + dummy_d_248 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_263; +reg dummy_d_249; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_cmd_payload_ras <= 1'd0; - case (vns_bankmachine7_state) + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (bankmachine7_state) 1'd1: begin - if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin - soc_sdram_bankmachine7_cmd_payload_ras <= 1'd1; + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_sdram_bankmachine7_trccon_ready) begin - soc_sdram_bankmachine7_cmd_payload_ras <= 1'd1; + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -10691,454 +9777,426 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_263 = dummy_s; + dummy_d_249 = dummy_s; // synthesis translate_on end -assign soc_sdram_trrdcon_valid = ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & ((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))); -assign soc_sdram_tfawcon_valid = ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & ((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))); -assign soc_sdram_ras_allowed = (soc_sdram_trrdcon_ready & soc_sdram_tfawcon_ready); -assign soc_sdram_tccdcon_valid = ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_cmd_payload_is_write | soc_sdram_choose_req_cmd_payload_is_read)); -assign soc_sdram_cas_allowed = soc_sdram_tccdcon_ready; -assign soc_sdram_twtrcon_valid = ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write); -assign soc_sdram_read_available = ((((((((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_payload_is_read) | (soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_payload_is_read)) | (soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_payload_is_read)) | (soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_payload_is_read)) | (soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_payload_is_read)) | (soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_payload_is_read)) | (soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_payload_is_read)) | (soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_payload_is_read)); -assign soc_sdram_write_available = ((((((((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_payload_is_write) | (soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_payload_is_write)) | (soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_payload_is_write)) | (soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_payload_is_write)) | (soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_payload_is_write)) | (soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_payload_is_write)) | (soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_payload_is_write)) | (soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_payload_is_write)); -assign soc_sdram_max_time0 = (soc_sdram_time0 == 1'd0); -assign soc_sdram_max_time1 = (soc_sdram_time1 == 1'd0); -assign soc_sdram_bankmachine0_refresh_req = soc_sdram_cmd_valid; -assign soc_sdram_bankmachine1_refresh_req = soc_sdram_cmd_valid; -assign soc_sdram_bankmachine2_refresh_req = soc_sdram_cmd_valid; -assign soc_sdram_bankmachine3_refresh_req = soc_sdram_cmd_valid; -assign soc_sdram_bankmachine4_refresh_req = soc_sdram_cmd_valid; -assign soc_sdram_bankmachine5_refresh_req = soc_sdram_cmd_valid; -assign soc_sdram_bankmachine6_refresh_req = soc_sdram_cmd_valid; -assign soc_sdram_bankmachine7_refresh_req = soc_sdram_cmd_valid; -assign soc_sdram_go_to_refresh = (((((((soc_sdram_bankmachine0_refresh_gnt & soc_sdram_bankmachine1_refresh_gnt) & soc_sdram_bankmachine2_refresh_gnt) & soc_sdram_bankmachine3_refresh_gnt) & soc_sdram_bankmachine4_refresh_gnt) & soc_sdram_bankmachine5_refresh_gnt) & soc_sdram_bankmachine6_refresh_gnt) & soc_sdram_bankmachine7_refresh_gnt); -assign soc_sdram_interface_rdata = {soc_sdram_dfi_p3_rddata, soc_sdram_dfi_p2_rddata, soc_sdram_dfi_p1_rddata, soc_sdram_dfi_p0_rddata}; -assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata; -assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata; -assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata; -assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata; -assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we); -assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we); -assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we); -assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we); // synthesis translate_off -reg dummy_d_264; +reg dummy_d_250; // synthesis translate_on always @(*) begin - soc_sdram_choose_cmd_valids <= 8'd0; - soc_sdram_choose_cmd_valids[0] <= (soc_sdram_bankmachine0_cmd_valid & (((soc_sdram_bankmachine0_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine0_cmd_payload_ras & (~soc_sdram_bankmachine0_cmd_payload_cas)) & (~soc_sdram_bankmachine0_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine0_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine0_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); - soc_sdram_choose_cmd_valids[1] <= (soc_sdram_bankmachine1_cmd_valid & (((soc_sdram_bankmachine1_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine1_cmd_payload_ras & (~soc_sdram_bankmachine1_cmd_payload_cas)) & (~soc_sdram_bankmachine1_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine1_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine1_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); - soc_sdram_choose_cmd_valids[2] <= (soc_sdram_bankmachine2_cmd_valid & (((soc_sdram_bankmachine2_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine2_cmd_payload_ras & (~soc_sdram_bankmachine2_cmd_payload_cas)) & (~soc_sdram_bankmachine2_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine2_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine2_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); - soc_sdram_choose_cmd_valids[3] <= (soc_sdram_bankmachine3_cmd_valid & (((soc_sdram_bankmachine3_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine3_cmd_payload_ras & (~soc_sdram_bankmachine3_cmd_payload_cas)) & (~soc_sdram_bankmachine3_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine3_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine3_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); - soc_sdram_choose_cmd_valids[4] <= (soc_sdram_bankmachine4_cmd_valid & (((soc_sdram_bankmachine4_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine4_cmd_payload_ras & (~soc_sdram_bankmachine4_cmd_payload_cas)) & (~soc_sdram_bankmachine4_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine4_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine4_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); - soc_sdram_choose_cmd_valids[5] <= (soc_sdram_bankmachine5_cmd_valid & (((soc_sdram_bankmachine5_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine5_cmd_payload_ras & (~soc_sdram_bankmachine5_cmd_payload_cas)) & (~soc_sdram_bankmachine5_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine5_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine5_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); - soc_sdram_choose_cmd_valids[6] <= (soc_sdram_bankmachine6_cmd_valid & (((soc_sdram_bankmachine6_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine6_cmd_payload_ras & (~soc_sdram_bankmachine6_cmd_payload_cas)) & (~soc_sdram_bankmachine6_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine6_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine6_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); - soc_sdram_choose_cmd_valids[7] <= (soc_sdram_bankmachine7_cmd_valid & (((soc_sdram_bankmachine7_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine7_cmd_payload_ras & (~soc_sdram_bankmachine7_cmd_payload_cas)) & (~soc_sdram_bankmachine7_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine7_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine7_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes)))); + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase // synthesis translate_off - dummy_d_264 = dummy_s; + dummy_d_250 = dummy_s; // synthesis translate_on end -assign soc_sdram_choose_cmd_request = soc_sdram_choose_cmd_valids; -assign soc_sdram_choose_cmd_cmd_valid = vns_rhs_array_muxed0; -assign soc_sdram_choose_cmd_cmd_payload_a = vns_rhs_array_muxed1; -assign soc_sdram_choose_cmd_cmd_payload_ba = vns_rhs_array_muxed2; -assign soc_sdram_choose_cmd_cmd_payload_is_read = vns_rhs_array_muxed3; -assign soc_sdram_choose_cmd_cmd_payload_is_write = vns_rhs_array_muxed4; -assign soc_sdram_choose_cmd_cmd_payload_is_cmd = vns_rhs_array_muxed5; +assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); +assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); +assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready); +assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read)); +assign litedramcore_cas_allowed = litedramcore_tccdcon_ready; +assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); +assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read)); +assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write)); +assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0); +assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0); +assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid; +assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt); +assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata}; +assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; +assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; +assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; +assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; +assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); +assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); +assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); +assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); // synthesis translate_off -reg dummy_d_265; +reg dummy_d_251; // synthesis translate_on always @(*) begin - soc_sdram_choose_cmd_cmd_payload_cas <= 1'd0; - if (soc_sdram_choose_cmd_cmd_valid) begin - soc_sdram_choose_cmd_cmd_payload_cas <= vns_t_array_muxed0; - end + litedramcore_choose_cmd_valids <= 8'd0; + litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); // synthesis translate_off - dummy_d_265 = dummy_s; + dummy_d_251 = dummy_s; // synthesis translate_on end +assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; +assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; +assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1; +assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2; +assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; +assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; +assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; // synthesis translate_off -reg dummy_d_266; +reg dummy_d_252; // synthesis translate_on always @(*) begin - soc_sdram_choose_cmd_cmd_payload_ras <= 1'd0; - if (soc_sdram_choose_cmd_cmd_valid) begin - soc_sdram_choose_cmd_cmd_payload_ras <= vns_t_array_muxed1; + litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; end // synthesis translate_off - dummy_d_266 = dummy_s; + dummy_d_252 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_267; +reg dummy_d_253; // synthesis translate_on always @(*) begin - soc_sdram_choose_cmd_cmd_payload_we <= 1'd0; - if (soc_sdram_choose_cmd_cmd_valid) begin - soc_sdram_choose_cmd_cmd_payload_we <= vns_t_array_muxed2; + litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; end // synthesis translate_off - dummy_d_267 = dummy_s; + dummy_d_253 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_268; +reg dummy_d_254; +// synthesis translate_on +always @(*) begin + litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; + end +// synthesis translate_off + dummy_d_254 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_255; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine0_cmd_ready <= 1'd0; - if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 1'd0))) begin - soc_sdram_bankmachine0_cmd_ready <= 1'd1; + litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready <= 1'd1; end - if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 1'd0))) begin - soc_sdram_bankmachine0_cmd_ready <= 1'd1; + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_268 = dummy_s; + dummy_d_255 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_269; +reg dummy_d_256; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine1_cmd_ready <= 1'd0; - if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 1'd1))) begin - soc_sdram_bankmachine1_cmd_ready <= 1'd1; + litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready <= 1'd1; end - if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 1'd1))) begin - soc_sdram_bankmachine1_cmd_ready <= 1'd1; + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_269 = dummy_s; + dummy_d_256 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_270; +reg dummy_d_257; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine2_cmd_ready <= 1'd0; - if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 2'd2))) begin - soc_sdram_bankmachine2_cmd_ready <= 1'd1; + litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready <= 1'd1; end - if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 2'd2))) begin - soc_sdram_bankmachine2_cmd_ready <= 1'd1; + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_270 = dummy_s; + dummy_d_257 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_271; +reg dummy_d_258; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine3_cmd_ready <= 1'd0; - if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 2'd3))) begin - soc_sdram_bankmachine3_cmd_ready <= 1'd1; + litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready <= 1'd1; end - if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 2'd3))) begin - soc_sdram_bankmachine3_cmd_ready <= 1'd1; + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_271 = dummy_s; + dummy_d_258 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_272; +reg dummy_d_259; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine4_cmd_ready <= 1'd0; - if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd4))) begin - soc_sdram_bankmachine4_cmd_ready <= 1'd1; + litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready <= 1'd1; end - if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd4))) begin - soc_sdram_bankmachine4_cmd_ready <= 1'd1; + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_272 = dummy_s; + dummy_d_259 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_273; +reg dummy_d_260; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine5_cmd_ready <= 1'd0; - if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd5))) begin - soc_sdram_bankmachine5_cmd_ready <= 1'd1; + litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready <= 1'd1; end - if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd5))) begin - soc_sdram_bankmachine5_cmd_ready <= 1'd1; + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_273 = dummy_s; + dummy_d_260 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_274; +reg dummy_d_261; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine6_cmd_ready <= 1'd0; - if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd6))) begin - soc_sdram_bankmachine6_cmd_ready <= 1'd1; + litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready <= 1'd1; end - if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd6))) begin - soc_sdram_bankmachine6_cmd_ready <= 1'd1; + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_274 = dummy_s; + dummy_d_261 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_275; +reg dummy_d_262; // synthesis translate_on always @(*) begin - soc_sdram_bankmachine7_cmd_ready <= 1'd0; - if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd7))) begin - soc_sdram_bankmachine7_cmd_ready <= 1'd1; + litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready <= 1'd1; end - if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd7))) begin - soc_sdram_bankmachine7_cmd_ready <= 1'd1; + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready <= 1'd1; end // synthesis translate_off - dummy_d_275 = dummy_s; + dummy_d_262 = dummy_s; // synthesis translate_on end -assign soc_sdram_choose_cmd_ce = (soc_sdram_choose_cmd_cmd_ready | (~soc_sdram_choose_cmd_cmd_valid)); +assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); // synthesis translate_off -reg dummy_d_276; +reg dummy_d_263; // synthesis translate_on always @(*) begin - soc_sdram_choose_req_valids <= 8'd0; - soc_sdram_choose_req_valids[0] <= (soc_sdram_bankmachine0_cmd_valid & (((soc_sdram_bankmachine0_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine0_cmd_payload_ras & (~soc_sdram_bankmachine0_cmd_payload_cas)) & (~soc_sdram_bankmachine0_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine0_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine0_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); - soc_sdram_choose_req_valids[1] <= (soc_sdram_bankmachine1_cmd_valid & (((soc_sdram_bankmachine1_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine1_cmd_payload_ras & (~soc_sdram_bankmachine1_cmd_payload_cas)) & (~soc_sdram_bankmachine1_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine1_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine1_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); - soc_sdram_choose_req_valids[2] <= (soc_sdram_bankmachine2_cmd_valid & (((soc_sdram_bankmachine2_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine2_cmd_payload_ras & (~soc_sdram_bankmachine2_cmd_payload_cas)) & (~soc_sdram_bankmachine2_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine2_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine2_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); - soc_sdram_choose_req_valids[3] <= (soc_sdram_bankmachine3_cmd_valid & (((soc_sdram_bankmachine3_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine3_cmd_payload_ras & (~soc_sdram_bankmachine3_cmd_payload_cas)) & (~soc_sdram_bankmachine3_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine3_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine3_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); - soc_sdram_choose_req_valids[4] <= (soc_sdram_bankmachine4_cmd_valid & (((soc_sdram_bankmachine4_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine4_cmd_payload_ras & (~soc_sdram_bankmachine4_cmd_payload_cas)) & (~soc_sdram_bankmachine4_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine4_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine4_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); - soc_sdram_choose_req_valids[5] <= (soc_sdram_bankmachine5_cmd_valid & (((soc_sdram_bankmachine5_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine5_cmd_payload_ras & (~soc_sdram_bankmachine5_cmd_payload_cas)) & (~soc_sdram_bankmachine5_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine5_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine5_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); - soc_sdram_choose_req_valids[6] <= (soc_sdram_bankmachine6_cmd_valid & (((soc_sdram_bankmachine6_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine6_cmd_payload_ras & (~soc_sdram_bankmachine6_cmd_payload_cas)) & (~soc_sdram_bankmachine6_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine6_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine6_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); - soc_sdram_choose_req_valids[7] <= (soc_sdram_bankmachine7_cmd_valid & (((soc_sdram_bankmachine7_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine7_cmd_payload_ras & (~soc_sdram_bankmachine7_cmd_payload_cas)) & (~soc_sdram_bankmachine7_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine7_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine7_cmd_payload_is_write == soc_sdram_choose_req_want_writes)))); + litedramcore_choose_req_valids <= 8'd0; + litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); // synthesis translate_off - dummy_d_276 = dummy_s; + dummy_d_263 = dummy_s; // synthesis translate_on end -assign soc_sdram_choose_req_request = soc_sdram_choose_req_valids; -assign soc_sdram_choose_req_cmd_valid = vns_rhs_array_muxed6; -assign soc_sdram_choose_req_cmd_payload_a = vns_rhs_array_muxed7; -assign soc_sdram_choose_req_cmd_payload_ba = vns_rhs_array_muxed8; -assign soc_sdram_choose_req_cmd_payload_is_read = vns_rhs_array_muxed9; -assign soc_sdram_choose_req_cmd_payload_is_write = vns_rhs_array_muxed10; -assign soc_sdram_choose_req_cmd_payload_is_cmd = vns_rhs_array_muxed11; +assign litedramcore_choose_req_request = litedramcore_choose_req_valids; +assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6; +assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7; +assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8; +assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; +assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; +assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; // synthesis translate_off -reg dummy_d_277; +reg dummy_d_264; // synthesis translate_on always @(*) begin - soc_sdram_choose_req_cmd_payload_cas <= 1'd0; - if (soc_sdram_choose_req_cmd_valid) begin - soc_sdram_choose_req_cmd_payload_cas <= vns_t_array_muxed3; + litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; end // synthesis translate_off - dummy_d_277 = dummy_s; + dummy_d_264 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_278; +reg dummy_d_265; // synthesis translate_on always @(*) begin - soc_sdram_choose_req_cmd_payload_ras <= 1'd0; - if (soc_sdram_choose_req_cmd_valid) begin - soc_sdram_choose_req_cmd_payload_ras <= vns_t_array_muxed4; + litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; end // synthesis translate_off - dummy_d_278 = dummy_s; + dummy_d_265 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_279; +reg dummy_d_266; // synthesis translate_on always @(*) begin - soc_sdram_choose_req_cmd_payload_we <= 1'd0; - if (soc_sdram_choose_req_cmd_valid) begin - soc_sdram_choose_req_cmd_payload_we <= vns_t_array_muxed5; + litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; end // synthesis translate_off - dummy_d_279 = dummy_s; + dummy_d_266 = dummy_s; // synthesis translate_on end -assign soc_sdram_choose_req_ce = (soc_sdram_choose_req_cmd_ready | (~soc_sdram_choose_req_cmd_valid)); -assign soc_sdram_dfi_p0_reset_n = 1'd1; -assign soc_sdram_dfi_p0_cke = {1{soc_sdram_steerer0}}; -assign soc_sdram_dfi_p0_odt = {1{soc_sdram_steerer1}}; -assign soc_sdram_dfi_p1_reset_n = 1'd1; -assign soc_sdram_dfi_p1_cke = {1{soc_sdram_steerer2}}; -assign soc_sdram_dfi_p1_odt = {1{soc_sdram_steerer3}}; -assign soc_sdram_dfi_p2_reset_n = 1'd1; -assign soc_sdram_dfi_p2_cke = {1{soc_sdram_steerer4}}; -assign soc_sdram_dfi_p2_odt = {1{soc_sdram_steerer5}}; -assign soc_sdram_dfi_p3_reset_n = 1'd1; -assign soc_sdram_dfi_p3_cke = {1{soc_sdram_steerer6}}; -assign soc_sdram_dfi_p3_odt = {1{soc_sdram_steerer7}}; -assign soc_sdram_tfawcon_count = ((((soc_sdram_tfawcon_window[0] + soc_sdram_tfawcon_window[1]) + soc_sdram_tfawcon_window[2]) + soc_sdram_tfawcon_window[3]) + soc_sdram_tfawcon_window[4]); +assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); +assign litedramcore_dfi_p0_reset_n = 1'd1; +assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}}; +assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}}; +assign litedramcore_dfi_p1_reset_n = 1'd1; +assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}}; +assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}}; +assign litedramcore_dfi_p2_reset_n = 1'd1; +assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}}; +assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}}; +assign litedramcore_dfi_p3_reset_n = 1'd1; +assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}}; +assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}}; +assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]); // synthesis translate_off -reg dummy_d_280; +reg dummy_d_267; // synthesis translate_on always @(*) begin - vns_multiplexer_next_state <= 4'd0; - vns_multiplexer_next_state <= vns_multiplexer_state; - case (vns_multiplexer_state) + multiplexer_next_state <= 4'd0; + multiplexer_next_state <= multiplexer_state; + case (multiplexer_state) 1'd1: begin - if (soc_sdram_read_available) begin - if (((~soc_sdram_write_available) | soc_sdram_max_time1)) begin - vns_multiplexer_next_state <= 2'd3; + if (litedramcore_read_available) begin + if (((~litedramcore_write_available) | litedramcore_max_time1)) begin + multiplexer_next_state <= 2'd3; end end - if (soc_sdram_go_to_refresh) begin - vns_multiplexer_next_state <= 2'd2; + if (litedramcore_go_to_refresh) begin + multiplexer_next_state <= 2'd2; end end 2'd2: begin - if (soc_sdram_cmd_last) begin - vns_multiplexer_next_state <= 1'd0; + if (litedramcore_cmd_last) begin + multiplexer_next_state <= 1'd0; end end 2'd3: begin - if (soc_sdram_twtrcon_ready) begin - vns_multiplexer_next_state <= 1'd0; + if (litedramcore_twtrcon_ready) begin + multiplexer_next_state <= 1'd0; end end 3'd4: begin - vns_multiplexer_next_state <= 3'd5; + multiplexer_next_state <= 3'd5; end 3'd5: begin - vns_multiplexer_next_state <= 3'd6; + multiplexer_next_state <= 3'd6; end 3'd6: begin - vns_multiplexer_next_state <= 3'd7; + multiplexer_next_state <= 3'd7; end 3'd7: begin - vns_multiplexer_next_state <= 4'd8; + multiplexer_next_state <= 4'd8; end 4'd8: begin - vns_multiplexer_next_state <= 4'd9; + multiplexer_next_state <= 4'd9; end 4'd9: begin - vns_multiplexer_next_state <= 4'd10; + multiplexer_next_state <= 4'd10; end 4'd10: begin - vns_multiplexer_next_state <= 1'd1; + multiplexer_next_state <= 1'd1; end default: begin - if (soc_sdram_write_available) begin - if (((~soc_sdram_read_available) | soc_sdram_max_time0)) begin - vns_multiplexer_next_state <= 3'd4; + if (litedramcore_write_available) begin + if (((~litedramcore_read_available) | litedramcore_max_time0)) begin + multiplexer_next_state <= 3'd4; end end - if (soc_sdram_go_to_refresh) begin - vns_multiplexer_next_state <= 2'd2; + if (litedramcore_go_to_refresh) begin + multiplexer_next_state <= 2'd2; end end endcase // synthesis translate_off - dummy_d_280 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_281; -// synthesis translate_on -always @(*) begin - soc_sdram_steerer_sel0 <= 2'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_sdram_steerer_sel0 <= 1'd0; - end - 2'd2: begin - soc_sdram_steerer_sel0 <= 2'd3; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_sdram_steerer_sel0 <= 1'd0; - end - endcase -// synthesis translate_off - dummy_d_281 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_282; -// synthesis translate_on -always @(*) begin - soc_sdram_steerer_sel1 <= 2'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_sdram_steerer_sel1 <= 1'd0; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_sdram_steerer_sel1 <= 1'd1; - end - endcase -// synthesis translate_off - dummy_d_282 = dummy_s; + dummy_d_267 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_283; +reg dummy_d_268; // synthesis translate_on always @(*) begin - soc_sdram_steerer_sel2 <= 2'd0; - case (vns_multiplexer_state) + litedramcore_steerer_sel2 <= 2'd0; + case (multiplexer_state) 1'd1: begin - soc_sdram_steerer_sel2 <= 1'd1; + litedramcore_steerer_sel2 <= 1'd1; end 2'd2: begin end @@ -11159,24 +10217,24 @@ always @(*) begin 4'd10: begin end default: begin - soc_sdram_steerer_sel2 <= 2'd2; + litedramcore_steerer_sel2 <= 2'd2; end endcase // synthesis translate_off - dummy_d_283 = dummy_s; + dummy_d_268 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_284; +reg dummy_d_269; // synthesis translate_on always @(*) begin - soc_sdram_choose_cmd_want_activates <= 1'd0; - case (vns_multiplexer_state) + litedramcore_choose_cmd_want_activates <= 1'd0; + case (multiplexer_state) 1'd1: begin if (1'd0) begin end else begin - soc_sdram_choose_cmd_want_activates <= soc_sdram_ras_allowed; + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; end end 2'd2: begin @@ -11200,23 +10258,23 @@ always @(*) begin default: begin if (1'd0) begin end else begin - soc_sdram_choose_cmd_want_activates <= soc_sdram_ras_allowed; + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; end end endcase // synthesis translate_off - dummy_d_284 = dummy_s; + dummy_d_269 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_285; +reg dummy_d_270; // synthesis translate_on always @(*) begin - soc_sdram_steerer_sel3 <= 2'd0; - case (vns_multiplexer_state) + litedramcore_steerer_sel3 <= 2'd0; + case (multiplexer_state) 1'd1: begin - soc_sdram_steerer_sel3 <= 2'd2; + litedramcore_steerer_sel3 <= 2'd2; end 2'd2: begin end @@ -11237,20 +10295,20 @@ always @(*) begin 4'd10: begin end default: begin - soc_sdram_steerer_sel3 <= 1'd0; + litedramcore_steerer_sel3 <= 1'd0; end endcase // synthesis translate_off - dummy_d_285 = dummy_s; + dummy_d_270 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_286; +reg dummy_d_271; // synthesis translate_on always @(*) begin - soc_sdram_en0 <= 1'd0; - case (vns_multiplexer_state) + litedramcore_en0 <= 1'd0; + case (multiplexer_state) 1'd1: begin end 2'd2: begin @@ -11272,24 +10330,24 @@ always @(*) begin 4'd10: begin end default: begin - soc_sdram_en0 <= 1'd1; + litedramcore_en0 <= 1'd1; end endcase // synthesis translate_off - dummy_d_286 = dummy_s; + dummy_d_271 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_287; +reg dummy_d_272; // synthesis translate_on always @(*) begin - soc_sdram_cmd_ready <= 1'd0; - case (vns_multiplexer_state) + litedramcore_cmd_ready <= 1'd0; + case (multiplexer_state) 1'd1: begin end 2'd2: begin - soc_sdram_cmd_ready <= 1'd1; + litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -11311,96 +10369,22 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_287 = dummy_s; + dummy_d_272 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_288; +reg dummy_d_273; // synthesis translate_on always @(*) begin - soc_sdram_choose_cmd_cmd_ready <= 1'd0; - case (vns_multiplexer_state) + litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (multiplexer_state) 1'd1: begin if (1'd0) begin end else begin - soc_sdram_choose_cmd_cmd_ready <= ((~((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))) | soc_sdram_ras_allowed); - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - soc_sdram_choose_cmd_cmd_ready <= ((~((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))) | soc_sdram_ras_allowed); + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); end end - endcase -// synthesis translate_off - dummy_d_288 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_289; -// synthesis translate_on -always @(*) begin - soc_sdram_choose_req_want_reads <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_sdram_choose_req_want_reads <= 1'd1; - end - endcase -// synthesis translate_off - dummy_d_289 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_290; -// synthesis translate_on -always @(*) begin - soc_sdram_choose_req_want_writes <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_sdram_choose_req_want_writes <= 1'd1; - end 2'd2: begin end 2'd3: begin @@ -11418,4578 +10402,3214 @@ always @(*) begin 4'd9: begin end 4'd10: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_290 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_291; -// synthesis translate_on -always @(*) begin - soc_sdram_choose_req_cmd_ready <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - if (1'd0) begin - soc_sdram_choose_req_cmd_ready <= (soc_sdram_cas_allowed & ((~((soc_sdram_choose_req_cmd_payload_ras & (~soc_sdram_choose_req_cmd_payload_cas)) & (~soc_sdram_choose_req_cmd_payload_we))) | soc_sdram_ras_allowed)); - end else begin - soc_sdram_choose_req_cmd_ready <= soc_sdram_cas_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - soc_sdram_choose_req_cmd_ready <= (soc_sdram_cas_allowed & ((~((soc_sdram_choose_req_cmd_payload_ras & (~soc_sdram_choose_req_cmd_payload_cas)) & (~soc_sdram_choose_req_cmd_payload_we))) | soc_sdram_ras_allowed)); - end else begin - soc_sdram_choose_req_cmd_ready <= soc_sdram_cas_allowed; - end - end - endcase -// synthesis translate_off - dummy_d_291 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_292; -// synthesis translate_on -always @(*) begin - soc_sdram_en1 <= 1'd0; - case (vns_multiplexer_state) - 1'd1: begin - soc_sdram_en1 <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_292 = dummy_s; -// synthesis translate_on -end -assign vns_roundrobin0_request = {(((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; -assign vns_roundrobin0_ce = ((~soc_sdram_interface_bank0_valid) & (~soc_sdram_interface_bank0_lock)); -assign soc_sdram_interface_bank0_addr = vns_rhs_array_muxed12; -assign soc_sdram_interface_bank0_we = vns_rhs_array_muxed13; -assign soc_sdram_interface_bank0_valid = vns_rhs_array_muxed14; -assign vns_roundrobin1_request = {(((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; -assign vns_roundrobin1_ce = ((~soc_sdram_interface_bank1_valid) & (~soc_sdram_interface_bank1_lock)); -assign soc_sdram_interface_bank1_addr = vns_rhs_array_muxed15; -assign soc_sdram_interface_bank1_we = vns_rhs_array_muxed16; -assign soc_sdram_interface_bank1_valid = vns_rhs_array_muxed17; -assign vns_roundrobin2_request = {(((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; -assign vns_roundrobin2_ce = ((~soc_sdram_interface_bank2_valid) & (~soc_sdram_interface_bank2_lock)); -assign soc_sdram_interface_bank2_addr = vns_rhs_array_muxed18; -assign soc_sdram_interface_bank2_we = vns_rhs_array_muxed19; -assign soc_sdram_interface_bank2_valid = vns_rhs_array_muxed20; -assign vns_roundrobin3_request = {(((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; -assign vns_roundrobin3_ce = ((~soc_sdram_interface_bank3_valid) & (~soc_sdram_interface_bank3_lock)); -assign soc_sdram_interface_bank3_addr = vns_rhs_array_muxed21; -assign soc_sdram_interface_bank3_we = vns_rhs_array_muxed22; -assign soc_sdram_interface_bank3_valid = vns_rhs_array_muxed23; -assign vns_roundrobin4_request = {(((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; -assign vns_roundrobin4_ce = ((~soc_sdram_interface_bank4_valid) & (~soc_sdram_interface_bank4_lock)); -assign soc_sdram_interface_bank4_addr = vns_rhs_array_muxed24; -assign soc_sdram_interface_bank4_we = vns_rhs_array_muxed25; -assign soc_sdram_interface_bank4_valid = vns_rhs_array_muxed26; -assign vns_roundrobin5_request = {(((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; -assign vns_roundrobin5_ce = ((~soc_sdram_interface_bank5_valid) & (~soc_sdram_interface_bank5_lock)); -assign soc_sdram_interface_bank5_addr = vns_rhs_array_muxed27; -assign soc_sdram_interface_bank5_we = vns_rhs_array_muxed28; -assign soc_sdram_interface_bank5_valid = vns_rhs_array_muxed29; -assign vns_roundrobin6_request = {(((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)}; -assign vns_roundrobin6_ce = ((~soc_sdram_interface_bank6_valid) & (~soc_sdram_interface_bank6_lock)); -assign soc_sdram_interface_bank6_addr = vns_rhs_array_muxed30; -assign soc_sdram_interface_bank6_we = vns_rhs_array_muxed31; -assign soc_sdram_interface_bank6_valid = vns_rhs_array_muxed32; -assign vns_roundrobin7_request = {(((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_port_cmd_valid)}; -assign vns_roundrobin7_ce = ((~soc_sdram_interface_bank7_valid) & (~soc_sdram_interface_bank7_lock)); -assign soc_sdram_interface_bank7_addr = vns_rhs_array_muxed33; -assign soc_sdram_interface_bank7_we = vns_rhs_array_muxed34; -assign soc_sdram_interface_bank7_valid = vns_rhs_array_muxed35; -assign soc_port_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0)))))) & soc_sdram_interface_bank7_ready)); -assign soc_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1)))))) & soc_sdram_interface_bank7_ready)); -assign soc_port_wdata_ready = vns_new_master_wdata_ready2; -assign soc_wdata_ready = vns_new_master_wdata_ready5; -assign soc_port_rdata_valid = vns_new_master_rdata_valid8; -assign soc_rdata_valid = vns_new_master_rdata_valid17; - -// synthesis translate_off -reg dummy_d_293; -// synthesis translate_on -always @(*) begin - soc_sdram_interface_wdata_we <= 16'd0; - case ({vns_new_master_wdata_ready5, vns_new_master_wdata_ready2}) - 1'd1: begin - soc_sdram_interface_wdata_we <= soc_port_wdata_payload_we; - end - 2'd2: begin - soc_sdram_interface_wdata_we <= soc_wdata_payload_we; - end - default: begin - soc_sdram_interface_wdata_we <= 1'd0; - end - endcase -// synthesis translate_off - dummy_d_293 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_294; -// synthesis translate_on -always @(*) begin - soc_sdram_interface_wdata <= 128'd0; - case ({vns_new_master_wdata_ready5, vns_new_master_wdata_ready2}) - 1'd1: begin - soc_sdram_interface_wdata <= soc_port_wdata_payload_data; - end - 2'd2: begin - soc_sdram_interface_wdata <= soc_wdata_payload_data; - end - default: begin - soc_sdram_interface_wdata <= 1'd0; - end - endcase -// synthesis translate_off - dummy_d_294 = dummy_s; -// synthesis translate_on -end -assign soc_port_rdata_payload_data = soc_sdram_interface_rdata; -assign soc_rdata_payload_data = soc_sdram_interface_rdata; -assign soc_address_d = soc_wb_sdram_adr; -assign soc_counter_offset = soc_address_q; -assign soc_counter_done = ((soc_counter + soc_counter_offset) == 2'd3); -assign soc_end_of_burst = ((~soc_wb_sdram_cyc) | (((soc_wb_sdram_stb & soc_wb_sdram_cyc) & soc_wb_sdram_ack) & ((soc_wb_sdram_cti == 3'd7) | soc_counter_done))); -assign soc_need_refill_reset = soc_end_of_burst; -assign soc_need_refill_d = 1'd0; -assign soc_litedram_wb_cti = 3'd7; -assign soc_litedram_wb_adr = soc_address_q[29:2]; -assign soc_cached_sels_reset0 = soc_counter_reset; - -// synthesis translate_off -reg dummy_d_295; -// synthesis translate_on -always @(*) begin - soc_cached_datas_flipflop0_d <= 32'd0; - if (soc_write) begin - soc_cached_datas_flipflop0_d <= soc_wb_sdram_dat_w; - end else begin - soc_cached_datas_flipflop0_d <= soc_litedram_wb_dat_r[31:0]; - end -// synthesis translate_off - dummy_d_295 = dummy_s; -// synthesis translate_on -end -assign soc_cached_sels_flipflop0_d = soc_wb_sdram_sel; - -// synthesis translate_off -reg dummy_d_296; -// synthesis translate_on -always @(*) begin - soc_cached_sels_ce0 <= 1'd0; - if (((soc_write & soc_write_sel0) | soc_refill)) begin - soc_cached_sels_ce0 <= 1'd1; - end -// synthesis translate_off - dummy_d_296 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_297; -// synthesis translate_on -always @(*) begin - soc_cached_datas_ce0 <= 1'd0; - if (((soc_write & soc_write_sel0) | soc_refill)) begin - soc_cached_datas_ce0 <= 1'd1; - end -// synthesis translate_off - dummy_d_297 = dummy_s; -// synthesis translate_on -end -assign soc_cached_sels_reset1 = soc_counter_reset; - -// synthesis translate_off -reg dummy_d_298; -// synthesis translate_on -always @(*) begin - soc_cached_datas_flipflop1_d <= 32'd0; - if (soc_write) begin - soc_cached_datas_flipflop1_d <= soc_wb_sdram_dat_w; - end else begin - soc_cached_datas_flipflop1_d <= soc_litedram_wb_dat_r[63:32]; - end -// synthesis translate_off - dummy_d_298 = dummy_s; -// synthesis translate_on -end -assign soc_cached_sels_flipflop1_d = soc_wb_sdram_sel; - -// synthesis translate_off -reg dummy_d_299; -// synthesis translate_on -always @(*) begin - soc_cached_sels_ce1 <= 1'd0; - if (((soc_write & soc_write_sel1) | soc_refill)) begin - soc_cached_sels_ce1 <= 1'd1; - end -// synthesis translate_off - dummy_d_299 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_300; -// synthesis translate_on -always @(*) begin - soc_cached_datas_ce1 <= 1'd0; - if (((soc_write & soc_write_sel1) | soc_refill)) begin - soc_cached_datas_ce1 <= 1'd1; - end -// synthesis translate_off - dummy_d_300 = dummy_s; -// synthesis translate_on -end -assign soc_cached_sels_reset2 = soc_counter_reset; - -// synthesis translate_off -reg dummy_d_301; -// synthesis translate_on -always @(*) begin - soc_cached_datas_flipflop2_d <= 32'd0; - if (soc_write) begin - soc_cached_datas_flipflop2_d <= soc_wb_sdram_dat_w; - end else begin - soc_cached_datas_flipflop2_d <= soc_litedram_wb_dat_r[95:64]; - end -// synthesis translate_off - dummy_d_301 = dummy_s; -// synthesis translate_on -end -assign soc_cached_sels_flipflop2_d = soc_wb_sdram_sel; - -// synthesis translate_off -reg dummy_d_302; -// synthesis translate_on -always @(*) begin - soc_cached_sels_ce2 <= 1'd0; - if (((soc_write & soc_write_sel2) | soc_refill)) begin - soc_cached_sels_ce2 <= 1'd1; - end -// synthesis translate_off - dummy_d_302 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_303; -// synthesis translate_on -always @(*) begin - soc_cached_datas_ce2 <= 1'd0; - if (((soc_write & soc_write_sel2) | soc_refill)) begin - soc_cached_datas_ce2 <= 1'd1; - end -// synthesis translate_off - dummy_d_303 = dummy_s; -// synthesis translate_on -end -assign soc_cached_sels_reset3 = soc_counter_reset; - -// synthesis translate_off -reg dummy_d_304; -// synthesis translate_on -always @(*) begin - soc_cached_datas_flipflop3_d <= 32'd0; - if (soc_write) begin - soc_cached_datas_flipflop3_d <= soc_wb_sdram_dat_w; - end else begin - soc_cached_datas_flipflop3_d <= soc_litedram_wb_dat_r[127:96]; - end -// synthesis translate_off - dummy_d_304 = dummy_s; -// synthesis translate_on -end -assign soc_cached_sels_flipflop3_d = soc_wb_sdram_sel; - -// synthesis translate_off -reg dummy_d_305; -// synthesis translate_on -always @(*) begin - soc_cached_sels_ce3 <= 1'd0; - if (((soc_write & soc_write_sel3) | soc_refill)) begin - soc_cached_sels_ce3 <= 1'd1; - end -// synthesis translate_off - dummy_d_305 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_306; -// synthesis translate_on -always @(*) begin - soc_cached_datas_ce3 <= 1'd0; - if (((soc_write & soc_write_sel3) | soc_refill)) begin - soc_cached_datas_ce3 <= 1'd1; - end -// synthesis translate_off - dummy_d_306 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_307; -// synthesis translate_on -always @(*) begin - soc_write_sel1 <= 1'd0; - case ((soc_counter + soc_counter_offset)) - 1'd0: begin - end - 1'd1: begin - soc_write_sel1 <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - endcase -// synthesis translate_off - dummy_d_307 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_308; -// synthesis translate_on -always @(*) begin - soc_write_sel0 <= 1'd0; - case ((soc_counter + soc_counter_offset)) - 1'd0: begin - soc_write_sel0 <= 1'd1; - end - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - endcase -// synthesis translate_off - dummy_d_308 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_309; -// synthesis translate_on -always @(*) begin - soc_write_sel2 <= 1'd0; - case ((soc_counter + soc_counter_offset)) - 1'd0: begin - end - 1'd1: begin - end - 2'd2: begin - soc_write_sel2 <= 1'd1; - end - 2'd3: begin - end - endcase -// synthesis translate_off - dummy_d_309 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_310; -// synthesis translate_on -always @(*) begin - soc_write_sel3 <= 1'd0; - case ((soc_counter + soc_counter_offset)) - 1'd0: begin - end - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - soc_write_sel3 <= 1'd1; - end - endcase -// synthesis translate_off - dummy_d_310 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_311; -// synthesis translate_on -always @(*) begin - soc_wb_sdram_dat_r <= 32'd0; - case (soc_address_q[1:0]) - 1'd0: begin - soc_wb_sdram_dat_r <= soc_cached_datas_flipflop0_q; - end - 1'd1: begin - soc_wb_sdram_dat_r <= soc_cached_datas_flipflop1_q; - end - 2'd2: begin - soc_wb_sdram_dat_r <= soc_cached_datas_flipflop2_q; - end - 2'd3: begin - soc_wb_sdram_dat_r <= soc_cached_datas_flipflop3_q; - end - endcase -// synthesis translate_off - dummy_d_311 = dummy_s; -// synthesis translate_on -end -assign soc_cached_data = {soc_cached_datas_flipflop3_q, soc_cached_datas_flipflop2_q, soc_cached_datas_flipflop1_q, soc_cached_datas_flipflop0_q}; -assign soc_cached_sel = {soc_cached_sels_flipflop3_q, soc_cached_sels_flipflop2_q, soc_cached_sels_flipflop1_q, soc_cached_sels_flipflop0_q}; - -// synthesis translate_off -reg dummy_d_312; -// synthesis translate_on -always @(*) begin - vns_converter_next_state <= 3'd0; - vns_converter_next_state <= vns_converter_state; - case (vns_converter_state) - 1'd1: begin - if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin - if (soc_counter_done) begin - vns_converter_next_state <= 2'd2; - end - end else begin - if ((~soc_wb_sdram_cyc)) begin - vns_converter_next_state <= 2'd2; - end - end - end - 2'd2: begin - if (soc_litedram_wb_ack) begin - vns_converter_next_state <= 1'd0; - end - end - 2'd3: begin - if (soc_litedram_wb_ack) begin - vns_converter_next_state <= 3'd4; - end - end - 3'd4: begin - vns_converter_next_state <= 1'd0; - end - default: begin - if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin - if (soc_wb_sdram_we) begin - vns_converter_next_state <= 1'd1; - end else begin - if (soc_need_refill_q) begin - vns_converter_next_state <= 2'd3; - end else begin - vns_converter_next_state <= 3'd4; - end - end - end - end - endcase -// synthesis translate_off - dummy_d_312 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_313; -// synthesis translate_on -always @(*) begin - soc_address_ce <= 1'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - default: begin - if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin - soc_address_ce <= 1'd1; - end - end - endcase -// synthesis translate_off - dummy_d_313 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_314; -// synthesis translate_on -always @(*) begin - soc_litedram_wb_dat_w <= 128'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - soc_litedram_wb_dat_w <= soc_cached_data; - end - 2'd3: begin - end - 3'd4: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_314 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_315; -// synthesis translate_on -always @(*) begin - soc_litedram_wb_sel <= 16'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - soc_litedram_wb_sel <= soc_cached_sel; - end - 2'd3: begin - end - 3'd4: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_315 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_316; -// synthesis translate_on -always @(*) begin - soc_counter_ce <= 1'd0; - case (vns_converter_state) - 1'd1: begin - if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin - soc_counter_ce <= 1'd1; - end else begin - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_316 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_317; -// synthesis translate_on -always @(*) begin - soc_litedram_wb_cyc <= 1'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - soc_litedram_wb_cyc <= 1'd1; - end - 2'd3: begin - soc_litedram_wb_cyc <= 1'd1; - end - 3'd4: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_317 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_318; -// synthesis translate_on -always @(*) begin - soc_counter_reset <= 1'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - default: begin - soc_counter_reset <= 1'd1; - end - endcase -// synthesis translate_off - dummy_d_318 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_319; -// synthesis translate_on -always @(*) begin - soc_litedram_wb_stb <= 1'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - soc_litedram_wb_stb <= 1'd1; - end - 2'd3: begin - soc_litedram_wb_stb <= 1'd1; - end - 3'd4: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_319 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_320; -// synthesis translate_on -always @(*) begin - soc_need_refill_ce <= 1'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedram_wb_ack) begin - soc_need_refill_ce <= 1'd1; - end - end - 3'd4: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_320 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_321; -// synthesis translate_on -always @(*) begin - soc_litedram_wb_we <= 1'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - soc_litedram_wb_we <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_321 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_322; -// synthesis translate_on -always @(*) begin - soc_write <= 1'd0; - case (vns_converter_state) - 1'd1: begin - if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin - soc_write <= 1'd1; - end else begin - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_322 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_323; -// synthesis translate_on -always @(*) begin - soc_wb_sdram_ack <= 1'd0; - case (vns_converter_state) - 1'd1: begin - if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin - soc_wb_sdram_ack <= 1'd1; - end else begin - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin - soc_wb_sdram_ack <= 1'd1; - end - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_323 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_324; -// synthesis translate_on -always @(*) begin - soc_evict <= 1'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - soc_evict <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_324 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_325; -// synthesis translate_on -always @(*) begin - soc_refill <= 1'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - soc_refill <= 1'd1; - end - 3'd4: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_325 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_326; -// synthesis translate_on -always @(*) begin - soc_read <= 1'd0; - case (vns_converter_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - soc_read <= 1'd1; - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_326 = dummy_s; -// synthesis translate_on -end -assign soc_wdata_converter_sink_valid = ((soc_litedram_wb_cyc & soc_litedram_wb_stb) & soc_litedram_wb_we); -assign soc_wdata_converter_sink_payload_data = soc_litedram_wb_dat_w; -assign soc_wdata_converter_sink_payload_we = soc_litedram_wb_sel; -assign soc_port_wdata_valid = soc_wdata_converter_source_valid; -assign soc_wdata_converter_source_ready = soc_port_wdata_ready; -assign soc_port_wdata_first = soc_wdata_converter_source_first; -assign soc_port_wdata_last = soc_wdata_converter_source_last; -assign soc_port_wdata_payload_data = soc_wdata_converter_source_payload_data; -assign soc_port_wdata_payload_we = soc_wdata_converter_source_payload_we; -assign soc_rdata_converter_sink_valid = soc_port_rdata_valid; -assign soc_port_rdata_ready = soc_rdata_converter_sink_ready; -assign soc_rdata_converter_sink_first = soc_port_rdata_first; -assign soc_rdata_converter_sink_last = soc_port_rdata_last; -assign soc_rdata_converter_sink_payload_data = soc_port_rdata_payload_data; -assign soc_rdata_converter_source_ready = 1'd1; -assign soc_litedram_wb_dat_r = soc_rdata_converter_source_payload_data; -assign soc_wdata_converter_converter_sink_valid = soc_wdata_converter_sink_valid; -assign soc_wdata_converter_converter_sink_first = soc_wdata_converter_sink_first; -assign soc_wdata_converter_converter_sink_last = soc_wdata_converter_sink_last; -assign soc_wdata_converter_sink_ready = soc_wdata_converter_converter_sink_ready; -assign soc_wdata_converter_converter_sink_payload_data = {soc_wdata_converter_sink_payload_we, soc_wdata_converter_sink_payload_data}; -assign soc_wdata_converter_source_valid = soc_wdata_converter_source_source_valid; -assign soc_wdata_converter_source_first = soc_wdata_converter_source_source_first; -assign soc_wdata_converter_source_last = soc_wdata_converter_source_source_last; -assign soc_wdata_converter_source_source_ready = soc_wdata_converter_source_ready; -assign {soc_wdata_converter_source_payload_we, soc_wdata_converter_source_payload_data} = soc_wdata_converter_source_source_payload_data; -assign {soc_wdata_converter_source_payload_we, soc_wdata_converter_source_payload_data} = soc_wdata_converter_source_source_payload_data; -assign soc_wdata_converter_source_source_valid = soc_wdata_converter_converter_source_valid; -assign soc_wdata_converter_converter_source_ready = soc_wdata_converter_source_source_ready; -assign soc_wdata_converter_source_source_first = soc_wdata_converter_converter_source_first; -assign soc_wdata_converter_source_source_last = soc_wdata_converter_converter_source_last; -assign soc_wdata_converter_source_source_payload_data = soc_wdata_converter_converter_source_payload_data; -assign soc_wdata_converter_converter_source_valid = soc_wdata_converter_converter_sink_valid; -assign soc_wdata_converter_converter_sink_ready = soc_wdata_converter_converter_source_ready; -assign soc_wdata_converter_converter_source_first = soc_wdata_converter_converter_sink_first; -assign soc_wdata_converter_converter_source_last = soc_wdata_converter_converter_sink_last; -assign soc_wdata_converter_converter_source_payload_data = soc_wdata_converter_converter_sink_payload_data; -assign soc_wdata_converter_converter_source_payload_valid_token_count = 1'd1; -assign soc_rdata_converter_converter_sink_valid = soc_rdata_converter_sink_valid; -assign soc_rdata_converter_converter_sink_first = soc_rdata_converter_sink_first; -assign soc_rdata_converter_converter_sink_last = soc_rdata_converter_sink_last; -assign soc_rdata_converter_sink_ready = soc_rdata_converter_converter_sink_ready; -assign soc_rdata_converter_converter_sink_payload_data = {soc_rdata_converter_sink_payload_data}; -assign soc_rdata_converter_source_valid = soc_rdata_converter_source_source_valid; -assign soc_rdata_converter_source_first = soc_rdata_converter_source_source_first; -assign soc_rdata_converter_source_last = soc_rdata_converter_source_source_last; -assign soc_rdata_converter_source_source_ready = soc_rdata_converter_source_ready; -assign {soc_rdata_converter_source_payload_data} = soc_rdata_converter_source_source_payload_data; -assign soc_rdata_converter_source_source_valid = soc_rdata_converter_converter_source_valid; -assign soc_rdata_converter_converter_source_ready = soc_rdata_converter_source_source_ready; -assign soc_rdata_converter_source_source_first = soc_rdata_converter_converter_source_first; -assign soc_rdata_converter_source_source_last = soc_rdata_converter_converter_source_last; -assign soc_rdata_converter_source_source_payload_data = soc_rdata_converter_converter_source_payload_data; -assign soc_rdata_converter_converter_source_valid = soc_rdata_converter_converter_sink_valid; -assign soc_rdata_converter_converter_sink_ready = soc_rdata_converter_converter_source_ready; -assign soc_rdata_converter_converter_source_first = soc_rdata_converter_converter_sink_first; -assign soc_rdata_converter_converter_source_last = soc_rdata_converter_converter_sink_last; -assign soc_rdata_converter_converter_source_payload_data = soc_rdata_converter_converter_sink_payload_data; -assign soc_rdata_converter_converter_source_payload_valid_token_count = 1'd1; - -// synthesis translate_off -reg dummy_d_327; -// synthesis translate_on -always @(*) begin - vns_litedramwishbone2native_next_state <= 2'd0; - vns_litedramwishbone2native_next_state <= vns_litedramwishbone2native_state; - case (vns_litedramwishbone2native_state) - 1'd1: begin - if (soc_wdata_converter_sink_ready) begin - vns_litedramwishbone2native_next_state <= 1'd0; - end - end - 2'd2: begin - if (soc_rdata_converter_source_valid) begin - vns_litedramwishbone2native_next_state <= 1'd0; - end - end - default: begin - if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin - if ((soc_count == 1'd0)) begin - if (soc_litedram_wb_we) begin - vns_litedramwishbone2native_next_state <= 1'd1; - end else begin - vns_litedramwishbone2native_next_state <= 2'd2; - end - end - end - end - endcase -// synthesis translate_off - dummy_d_327 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_328; -// synthesis translate_on -always @(*) begin - soc_count_next_value_ce <= 1'd0; - case (vns_litedramwishbone2native_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin - soc_count_next_value_ce <= 1'd1; - if ((soc_count == 1'd0)) begin - soc_count_next_value_ce <= 1'd1; - end - end - end - endcase -// synthesis translate_off - dummy_d_328 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_329; -// synthesis translate_on -always @(*) begin - soc_port_cmd_valid <= 1'd0; - case (vns_litedramwishbone2native_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - soc_port_cmd_valid <= (soc_litedram_wb_cyc & soc_litedram_wb_stb); - end - endcase -// synthesis translate_off - dummy_d_329 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_330; -// synthesis translate_on -always @(*) begin - soc_litedram_wb_ack <= 1'd0; - case (vns_litedramwishbone2native_state) - 1'd1: begin - if (soc_wdata_converter_sink_ready) begin - soc_litedram_wb_ack <= 1'd1; - end - end - 2'd2: begin - if (soc_rdata_converter_source_valid) begin - soc_litedram_wb_ack <= 1'd1; - end - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_330 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_331; -// synthesis translate_on -always @(*) begin - soc_port_cmd_payload_we <= 1'd0; - case (vns_litedramwishbone2native_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - soc_port_cmd_payload_we <= soc_litedram_wb_we; - end - endcase -// synthesis translate_off - dummy_d_331 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_332; -// synthesis translate_on -always @(*) begin - soc_port_cmd_payload_addr <= 25'd0; - case (vns_litedramwishbone2native_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - soc_port_cmd_payload_addr <= (((soc_litedram_wb_adr * 1'd1) + soc_count) - 27'd67108864); - end - endcase -// synthesis translate_off - dummy_d_332 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_333; -// synthesis translate_on -always @(*) begin - soc_count_next_value <= 1'd0; - case (vns_litedramwishbone2native_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin - soc_count_next_value <= (soc_count + 1'd1); - if ((soc_count == 1'd0)) begin - soc_count_next_value <= 1'd0; - end - end - end - endcase -// synthesis translate_off - dummy_d_333 = dummy_s; -// synthesis translate_on -end -assign vns_shared_adr = vns_rhs_array_muxed36; -assign vns_shared_dat_w = vns_rhs_array_muxed37; -assign vns_shared_sel = vns_rhs_array_muxed38; -assign vns_shared_cyc = vns_rhs_array_muxed39; -assign vns_shared_stb = vns_rhs_array_muxed40; -assign vns_shared_we = vns_rhs_array_muxed41; -assign vns_shared_cti = vns_rhs_array_muxed42; -assign vns_shared_bte = vns_rhs_array_muxed43; -assign soc_litedramcore_cpu_ibus_dat_r = vns_shared_dat_r; -assign soc_litedramcore_cpu_dbus_dat_r = vns_shared_dat_r; -assign soc_litedramcore_cpu_ibus_ack = (vns_shared_ack & (vns_grant == 1'd0)); -assign soc_litedramcore_cpu_dbus_ack = (vns_shared_ack & (vns_grant == 1'd1)); -assign soc_litedramcore_cpu_ibus_err = (vns_shared_err & (vns_grant == 1'd0)); -assign soc_litedramcore_cpu_dbus_err = (vns_shared_err & (vns_grant == 1'd1)); -assign vns_request = {soc_litedramcore_cpu_dbus_cyc, soc_litedramcore_cpu_ibus_cyc}; - -// synthesis translate_off -reg dummy_d_334; -// synthesis translate_on -always @(*) begin - vns_slave_sel <= 4'd0; - vns_slave_sel[0] <= (vns_shared_adr[29:13] == 1'd0); - vns_slave_sel[1] <= (vns_shared_adr[29:10] == 13'd4096); - vns_slave_sel[2] <= (vns_shared_adr[29:14] == 16'd33280); - vns_slave_sel[3] <= (vns_shared_adr[29:22] == 7'd64); -// synthesis translate_off - dummy_d_334 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_litedramcore_ram_bus_adr = vns_shared_adr; -assign soc_litedramcore_litedramcore_ram_bus_dat_w = vns_shared_dat_w; -assign soc_litedramcore_litedramcore_ram_bus_sel = vns_shared_sel; -assign soc_litedramcore_litedramcore_ram_bus_stb = vns_shared_stb; -assign soc_litedramcore_litedramcore_ram_bus_we = vns_shared_we; -assign soc_litedramcore_litedramcore_ram_bus_cti = vns_shared_cti; -assign soc_litedramcore_litedramcore_ram_bus_bte = vns_shared_bte; -assign soc_litedramcore_ram_bus_ram_bus_adr = vns_shared_adr; -assign soc_litedramcore_ram_bus_ram_bus_dat_w = vns_shared_dat_w; -assign soc_litedramcore_ram_bus_ram_bus_sel = vns_shared_sel; -assign soc_litedramcore_ram_bus_ram_bus_stb = vns_shared_stb; -assign soc_litedramcore_ram_bus_ram_bus_we = vns_shared_we; -assign soc_litedramcore_ram_bus_ram_bus_cti = vns_shared_cti; -assign soc_litedramcore_ram_bus_ram_bus_bte = vns_shared_bte; -assign soc_litedramcore_bus_wishbone_adr = vns_shared_adr; -assign soc_litedramcore_bus_wishbone_dat_w = vns_shared_dat_w; -assign soc_litedramcore_bus_wishbone_sel = vns_shared_sel; -assign soc_litedramcore_bus_wishbone_stb = vns_shared_stb; -assign soc_litedramcore_bus_wishbone_we = vns_shared_we; -assign soc_litedramcore_bus_wishbone_cti = vns_shared_cti; -assign soc_litedramcore_bus_wishbone_bte = vns_shared_bte; -assign soc_wb_sdram_adr = vns_shared_adr; -assign soc_wb_sdram_dat_w = vns_shared_dat_w; -assign soc_wb_sdram_sel = vns_shared_sel; -assign soc_wb_sdram_stb = vns_shared_stb; -assign soc_wb_sdram_we = vns_shared_we; -assign soc_wb_sdram_cti = vns_shared_cti; -assign soc_wb_sdram_bte = vns_shared_bte; -assign soc_litedramcore_litedramcore_ram_bus_cyc = (vns_shared_cyc & vns_slave_sel[0]); -assign soc_litedramcore_ram_bus_ram_bus_cyc = (vns_shared_cyc & vns_slave_sel[1]); -assign soc_litedramcore_bus_wishbone_cyc = (vns_shared_cyc & vns_slave_sel[2]); -assign soc_wb_sdram_cyc = (vns_shared_cyc & vns_slave_sel[3]); - -// synthesis translate_off -reg dummy_d_335; -// synthesis translate_on -always @(*) begin - vns_shared_ack <= 1'd0; - vns_shared_ack <= (((soc_litedramcore_litedramcore_ram_bus_ack | soc_litedramcore_ram_bus_ram_bus_ack) | soc_litedramcore_bus_wishbone_ack) | soc_wb_sdram_ack); - if (vns_done) begin - vns_shared_ack <= 1'd1; - end -// synthesis translate_off - dummy_d_335 = dummy_s; -// synthesis translate_on -end -assign vns_shared_err = (((soc_litedramcore_litedramcore_ram_bus_err | soc_litedramcore_ram_bus_ram_bus_err) | soc_litedramcore_bus_wishbone_err) | soc_wb_sdram_err); - -// synthesis translate_off -reg dummy_d_336; -// synthesis translate_on -always @(*) begin - vns_shared_dat_r <= 32'd0; - vns_shared_dat_r <= (((({32{vns_slave_sel_r[0]}} & soc_litedramcore_litedramcore_ram_bus_dat_r) | ({32{vns_slave_sel_r[1]}} & soc_litedramcore_ram_bus_ram_bus_dat_r)) | ({32{vns_slave_sel_r[2]}} & soc_litedramcore_bus_wishbone_dat_r)) | ({32{vns_slave_sel_r[3]}} & soc_wb_sdram_dat_r)); - if (vns_done) begin - vns_shared_dat_r <= 32'd4294967295; - end -// synthesis translate_off - dummy_d_336 = dummy_s; -// synthesis translate_on -end -assign vns_wait = ((vns_shared_stb & vns_shared_cyc) & (~vns_shared_ack)); - -// synthesis translate_off -reg dummy_d_337; -// synthesis translate_on -always @(*) begin - vns_error <= 1'd0; - if (vns_done) begin - vns_error <= 1'd1; - end + end + default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end + end + endcase // synthesis translate_off - dummy_d_337 = dummy_s; + dummy_d_273 = dummy_s; // synthesis translate_on end -assign vns_done = (vns_count == 1'd0); -assign vns_csrbank0_sel = (vns_interface0_bank_bus_adr[13:9] == 1'd0); -assign vns_csrbank0_reset0_r = vns_interface0_bank_bus_dat_w[0]; -assign vns_csrbank0_reset0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 1'd0)); -assign vns_csrbank0_reset0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 1'd0)); -assign vns_csrbank0_scratch3_r = vns_interface0_bank_bus_dat_w[7:0]; -assign vns_csrbank0_scratch3_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 1'd1)); -assign vns_csrbank0_scratch3_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 1'd1)); -assign vns_csrbank0_scratch2_r = vns_interface0_bank_bus_dat_w[7:0]; -assign vns_csrbank0_scratch2_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 2'd2)); -assign vns_csrbank0_scratch2_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 2'd2)); -assign vns_csrbank0_scratch1_r = vns_interface0_bank_bus_dat_w[7:0]; -assign vns_csrbank0_scratch1_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 2'd3)); -assign vns_csrbank0_scratch1_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 2'd3)); -assign vns_csrbank0_scratch0_r = vns_interface0_bank_bus_dat_w[7:0]; -assign vns_csrbank0_scratch0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd4)); -assign vns_csrbank0_scratch0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd4)); -assign vns_csrbank0_bus_errors3_r = vns_interface0_bank_bus_dat_w[7:0]; -assign vns_csrbank0_bus_errors3_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd5)); -assign vns_csrbank0_bus_errors3_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd5)); -assign vns_csrbank0_bus_errors2_r = vns_interface0_bank_bus_dat_w[7:0]; -assign vns_csrbank0_bus_errors2_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd6)); -assign vns_csrbank0_bus_errors2_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd6)); -assign vns_csrbank0_bus_errors1_r = vns_interface0_bank_bus_dat_w[7:0]; -assign vns_csrbank0_bus_errors1_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd7)); -assign vns_csrbank0_bus_errors1_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd7)); -assign vns_csrbank0_bus_errors0_r = vns_interface0_bank_bus_dat_w[7:0]; -assign vns_csrbank0_bus_errors0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 4'd8)); -assign vns_csrbank0_bus_errors0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 4'd8)); -assign vns_csrbank0_reset0_w = soc_litedramcore_soccontroller_reset_storage; -assign vns_csrbank0_scratch3_w = soc_litedramcore_soccontroller_scratch_storage[31:24]; -assign vns_csrbank0_scratch2_w = soc_litedramcore_soccontroller_scratch_storage[23:16]; -assign vns_csrbank0_scratch1_w = soc_litedramcore_soccontroller_scratch_storage[15:8]; -assign vns_csrbank0_scratch0_w = soc_litedramcore_soccontroller_scratch_storage[7:0]; -assign vns_csrbank0_bus_errors3_w = soc_litedramcore_soccontroller_bus_errors_status[31:24]; -assign vns_csrbank0_bus_errors2_w = soc_litedramcore_soccontroller_bus_errors_status[23:16]; -assign vns_csrbank0_bus_errors1_w = soc_litedramcore_soccontroller_bus_errors_status[15:8]; -assign vns_csrbank0_bus_errors0_w = soc_litedramcore_soccontroller_bus_errors_status[7:0]; -assign soc_litedramcore_soccontroller_bus_errors_we = vns_csrbank0_bus_errors0_we; -assign vns_csrbank1_sel = (vns_interface1_bank_bus_adr[13:9] == 3'd7); -assign vns_csrbank1_init_done0_r = vns_interface1_bank_bus_dat_w[0]; -assign vns_csrbank1_init_done0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[0] == 1'd0)); -assign vns_csrbank1_init_done0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[0] == 1'd0)); -assign vns_csrbank1_init_error0_r = vns_interface1_bank_bus_dat_w[0]; -assign vns_csrbank1_init_error0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[0] == 1'd1)); -assign vns_csrbank1_init_error0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[0] == 1'd1)); -assign vns_csrbank1_init_done0_w = soc_init_done_storage; -assign vns_csrbank1_init_error0_w = soc_init_error_storage; -assign vns_csrbank2_sel = (vns_interface2_bank_bus_adr[13:9] == 3'd5); -assign vns_csrbank2_half_sys8x_taps0_r = vns_interface2_bank_bus_dat_w[4:0]; -assign vns_csrbank2_half_sys8x_taps0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 1'd0)); -assign vns_csrbank2_half_sys8x_taps0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 1'd0)); -assign vns_csrbank2_wlevel_en0_r = vns_interface2_bank_bus_dat_w[0]; -assign vns_csrbank2_wlevel_en0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 1'd1)); -assign vns_csrbank2_wlevel_en0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 1'd1)); -assign soc_a7ddrphy_wlevel_strobe_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_a7ddrphy_wlevel_strobe_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 2'd2)); -assign soc_a7ddrphy_wlevel_strobe_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 2'd2)); -assign soc_a7ddrphy_cdly_rst_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_a7ddrphy_cdly_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 2'd3)); -assign soc_a7ddrphy_cdly_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 2'd3)); -assign soc_a7ddrphy_cdly_inc_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_a7ddrphy_cdly_inc_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd4)); -assign soc_a7ddrphy_cdly_inc_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd4)); -assign vns_csrbank2_dly_sel0_r = vns_interface2_bank_bus_dat_w[1:0]; -assign vns_csrbank2_dly_sel0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd5)); -assign vns_csrbank2_dly_sel0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd5)); -assign soc_a7ddrphy_rdly_dq_rst_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_a7ddrphy_rdly_dq_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd6)); -assign soc_a7ddrphy_rdly_dq_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd6)); -assign soc_a7ddrphy_rdly_dq_inc_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_a7ddrphy_rdly_dq_inc_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd7)); -assign soc_a7ddrphy_rdly_dq_inc_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd7)); -assign soc_a7ddrphy_rdly_dq_bitslip_rst_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_a7ddrphy_rdly_dq_bitslip_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 4'd8)); -assign soc_a7ddrphy_rdly_dq_bitslip_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 4'd8)); -assign soc_a7ddrphy_rdly_dq_bitslip_r = vns_interface2_bank_bus_dat_w[0]; -assign soc_a7ddrphy_rdly_dq_bitslip_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 4'd9)); -assign soc_a7ddrphy_rdly_dq_bitslip_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 4'd9)); -assign vns_csrbank2_half_sys8x_taps0_w = soc_a7ddrphy_half_sys8x_taps_storage[4:0]; -assign vns_csrbank2_wlevel_en0_w = soc_a7ddrphy_wlevel_en_storage; -assign vns_csrbank2_dly_sel0_w = soc_a7ddrphy_dly_sel_storage[1:0]; -assign vns_csrbank3_sel = (vns_interface3_bank_bus_adr[13:9] == 3'd6); -assign vns_csrbank3_dfii_control0_r = vns_interface3_bank_bus_dat_w[3:0]; -assign vns_csrbank3_dfii_control0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 1'd0)); -assign vns_csrbank3_dfii_control0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 1'd0)); -assign vns_csrbank3_dfii_pi0_command0_r = vns_interface3_bank_bus_dat_w[5:0]; -assign vns_csrbank3_dfii_pi0_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 1'd1)); -assign vns_csrbank3_dfii_pi0_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 1'd1)); -assign soc_sdram_phaseinjector0_command_issue_r = vns_interface3_bank_bus_dat_w[0]; -assign soc_sdram_phaseinjector0_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 2'd2)); -assign soc_sdram_phaseinjector0_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 2'd2)); -assign vns_csrbank3_dfii_pi0_address1_r = vns_interface3_bank_bus_dat_w[6:0]; -assign vns_csrbank3_dfii_pi0_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 2'd3)); -assign vns_csrbank3_dfii_pi0_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 2'd3)); -assign vns_csrbank3_dfii_pi0_address0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi0_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd4)); -assign vns_csrbank3_dfii_pi0_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd4)); -assign vns_csrbank3_dfii_pi0_baddress0_r = vns_interface3_bank_bus_dat_w[2:0]; -assign vns_csrbank3_dfii_pi0_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd5)); -assign vns_csrbank3_dfii_pi0_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd5)); -assign vns_csrbank3_dfii_pi0_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi0_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd6)); -assign vns_csrbank3_dfii_pi0_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd6)); -assign vns_csrbank3_dfii_pi0_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi0_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd7)); -assign vns_csrbank3_dfii_pi0_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd7)); -assign vns_csrbank3_dfii_pi0_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi0_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd8)); -assign vns_csrbank3_dfii_pi0_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd8)); -assign vns_csrbank3_dfii_pi0_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi0_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd9)); -assign vns_csrbank3_dfii_pi0_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd9)); -assign vns_csrbank3_dfii_pi0_rddata3_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi0_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd10)); -assign vns_csrbank3_dfii_pi0_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd10)); -assign vns_csrbank3_dfii_pi0_rddata2_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi0_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd11)); -assign vns_csrbank3_dfii_pi0_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd11)); -assign vns_csrbank3_dfii_pi0_rddata1_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi0_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd12)); -assign vns_csrbank3_dfii_pi0_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd12)); -assign vns_csrbank3_dfii_pi0_rddata0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi0_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd13)); -assign vns_csrbank3_dfii_pi0_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd13)); -assign vns_csrbank3_dfii_pi1_command0_r = vns_interface3_bank_bus_dat_w[5:0]; -assign vns_csrbank3_dfii_pi1_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd14)); -assign vns_csrbank3_dfii_pi1_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd14)); -assign soc_sdram_phaseinjector1_command_issue_r = vns_interface3_bank_bus_dat_w[0]; -assign soc_sdram_phaseinjector1_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd15)); -assign soc_sdram_phaseinjector1_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd15)); -assign vns_csrbank3_dfii_pi1_address1_r = vns_interface3_bank_bus_dat_w[6:0]; -assign vns_csrbank3_dfii_pi1_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd16)); -assign vns_csrbank3_dfii_pi1_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd16)); -assign vns_csrbank3_dfii_pi1_address0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi1_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd17)); -assign vns_csrbank3_dfii_pi1_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd17)); -assign vns_csrbank3_dfii_pi1_baddress0_r = vns_interface3_bank_bus_dat_w[2:0]; -assign vns_csrbank3_dfii_pi1_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd18)); -assign vns_csrbank3_dfii_pi1_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd18)); -assign vns_csrbank3_dfii_pi1_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi1_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd19)); -assign vns_csrbank3_dfii_pi1_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd19)); -assign vns_csrbank3_dfii_pi1_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi1_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd20)); -assign vns_csrbank3_dfii_pi1_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd20)); -assign vns_csrbank3_dfii_pi1_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi1_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd21)); -assign vns_csrbank3_dfii_pi1_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd21)); -assign vns_csrbank3_dfii_pi1_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi1_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd22)); -assign vns_csrbank3_dfii_pi1_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd22)); -assign vns_csrbank3_dfii_pi1_rddata3_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi1_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd23)); -assign vns_csrbank3_dfii_pi1_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd23)); -assign vns_csrbank3_dfii_pi1_rddata2_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi1_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd24)); -assign vns_csrbank3_dfii_pi1_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd24)); -assign vns_csrbank3_dfii_pi1_rddata1_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi1_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd25)); -assign vns_csrbank3_dfii_pi1_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd25)); -assign vns_csrbank3_dfii_pi1_rddata0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi1_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd26)); -assign vns_csrbank3_dfii_pi1_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd26)); -assign vns_csrbank3_dfii_pi2_command0_r = vns_interface3_bank_bus_dat_w[5:0]; -assign vns_csrbank3_dfii_pi2_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd27)); -assign vns_csrbank3_dfii_pi2_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd27)); -assign soc_sdram_phaseinjector2_command_issue_r = vns_interface3_bank_bus_dat_w[0]; -assign soc_sdram_phaseinjector2_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd28)); -assign soc_sdram_phaseinjector2_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd28)); -assign vns_csrbank3_dfii_pi2_address1_r = vns_interface3_bank_bus_dat_w[6:0]; -assign vns_csrbank3_dfii_pi2_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd29)); -assign vns_csrbank3_dfii_pi2_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd29)); -assign vns_csrbank3_dfii_pi2_address0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi2_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd30)); -assign vns_csrbank3_dfii_pi2_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd30)); -assign vns_csrbank3_dfii_pi2_baddress0_r = vns_interface3_bank_bus_dat_w[2:0]; -assign vns_csrbank3_dfii_pi2_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd31)); -assign vns_csrbank3_dfii_pi2_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd31)); -assign vns_csrbank3_dfii_pi2_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi2_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd32)); -assign vns_csrbank3_dfii_pi2_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd32)); -assign vns_csrbank3_dfii_pi2_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi2_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd33)); -assign vns_csrbank3_dfii_pi2_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd33)); -assign vns_csrbank3_dfii_pi2_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi2_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd34)); -assign vns_csrbank3_dfii_pi2_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd34)); -assign vns_csrbank3_dfii_pi2_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi2_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd35)); -assign vns_csrbank3_dfii_pi2_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd35)); -assign vns_csrbank3_dfii_pi2_rddata3_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi2_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd36)); -assign vns_csrbank3_dfii_pi2_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd36)); -assign vns_csrbank3_dfii_pi2_rddata2_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi2_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd37)); -assign vns_csrbank3_dfii_pi2_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd37)); -assign vns_csrbank3_dfii_pi2_rddata1_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi2_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd38)); -assign vns_csrbank3_dfii_pi2_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd38)); -assign vns_csrbank3_dfii_pi2_rddata0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi2_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd39)); -assign vns_csrbank3_dfii_pi2_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd39)); -assign vns_csrbank3_dfii_pi3_command0_r = vns_interface3_bank_bus_dat_w[5:0]; -assign vns_csrbank3_dfii_pi3_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd40)); -assign vns_csrbank3_dfii_pi3_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd40)); -assign soc_sdram_phaseinjector3_command_issue_r = vns_interface3_bank_bus_dat_w[0]; -assign soc_sdram_phaseinjector3_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd41)); -assign soc_sdram_phaseinjector3_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd41)); -assign vns_csrbank3_dfii_pi3_address1_r = vns_interface3_bank_bus_dat_w[6:0]; -assign vns_csrbank3_dfii_pi3_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd42)); -assign vns_csrbank3_dfii_pi3_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd42)); -assign vns_csrbank3_dfii_pi3_address0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi3_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd43)); -assign vns_csrbank3_dfii_pi3_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd43)); -assign vns_csrbank3_dfii_pi3_baddress0_r = vns_interface3_bank_bus_dat_w[2:0]; -assign vns_csrbank3_dfii_pi3_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd44)); -assign vns_csrbank3_dfii_pi3_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd44)); -assign vns_csrbank3_dfii_pi3_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi3_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd45)); -assign vns_csrbank3_dfii_pi3_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd45)); -assign vns_csrbank3_dfii_pi3_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi3_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd46)); -assign vns_csrbank3_dfii_pi3_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd46)); -assign vns_csrbank3_dfii_pi3_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi3_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd47)); -assign vns_csrbank3_dfii_pi3_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd47)); -assign vns_csrbank3_dfii_pi3_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi3_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd48)); -assign vns_csrbank3_dfii_pi3_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd48)); -assign vns_csrbank3_dfii_pi3_rddata3_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi3_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd49)); -assign vns_csrbank3_dfii_pi3_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd49)); -assign vns_csrbank3_dfii_pi3_rddata2_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi3_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd50)); -assign vns_csrbank3_dfii_pi3_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd50)); -assign vns_csrbank3_dfii_pi3_rddata1_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi3_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd51)); -assign vns_csrbank3_dfii_pi3_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd51)); -assign vns_csrbank3_dfii_pi3_rddata0_r = vns_interface3_bank_bus_dat_w[7:0]; -assign vns_csrbank3_dfii_pi3_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd52)); -assign vns_csrbank3_dfii_pi3_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd52)); -assign vns_csrbank3_dfii_control0_w = soc_sdram_storage[3:0]; -assign vns_csrbank3_dfii_pi0_command0_w = soc_sdram_phaseinjector0_command_storage[5:0]; -assign vns_csrbank3_dfii_pi0_address1_w = soc_sdram_phaseinjector0_address_storage[14:8]; -assign vns_csrbank3_dfii_pi0_address0_w = soc_sdram_phaseinjector0_address_storage[7:0]; -assign vns_csrbank3_dfii_pi0_baddress0_w = soc_sdram_phaseinjector0_baddress_storage[2:0]; -assign vns_csrbank3_dfii_pi0_wrdata3_w = soc_sdram_phaseinjector0_wrdata_storage[31:24]; -assign vns_csrbank3_dfii_pi0_wrdata2_w = soc_sdram_phaseinjector0_wrdata_storage[23:16]; -assign vns_csrbank3_dfii_pi0_wrdata1_w = soc_sdram_phaseinjector0_wrdata_storage[15:8]; -assign vns_csrbank3_dfii_pi0_wrdata0_w = soc_sdram_phaseinjector0_wrdata_storage[7:0]; -assign vns_csrbank3_dfii_pi0_rddata3_w = soc_sdram_phaseinjector0_status[31:24]; -assign vns_csrbank3_dfii_pi0_rddata2_w = soc_sdram_phaseinjector0_status[23:16]; -assign vns_csrbank3_dfii_pi0_rddata1_w = soc_sdram_phaseinjector0_status[15:8]; -assign vns_csrbank3_dfii_pi0_rddata0_w = soc_sdram_phaseinjector0_status[7:0]; -assign soc_sdram_phaseinjector0_we = vns_csrbank3_dfii_pi0_rddata0_we; -assign vns_csrbank3_dfii_pi1_command0_w = soc_sdram_phaseinjector1_command_storage[5:0]; -assign vns_csrbank3_dfii_pi1_address1_w = soc_sdram_phaseinjector1_address_storage[14:8]; -assign vns_csrbank3_dfii_pi1_address0_w = soc_sdram_phaseinjector1_address_storage[7:0]; -assign vns_csrbank3_dfii_pi1_baddress0_w = soc_sdram_phaseinjector1_baddress_storage[2:0]; -assign vns_csrbank3_dfii_pi1_wrdata3_w = soc_sdram_phaseinjector1_wrdata_storage[31:24]; -assign vns_csrbank3_dfii_pi1_wrdata2_w = soc_sdram_phaseinjector1_wrdata_storage[23:16]; -assign vns_csrbank3_dfii_pi1_wrdata1_w = soc_sdram_phaseinjector1_wrdata_storage[15:8]; -assign vns_csrbank3_dfii_pi1_wrdata0_w = soc_sdram_phaseinjector1_wrdata_storage[7:0]; -assign vns_csrbank3_dfii_pi1_rddata3_w = soc_sdram_phaseinjector1_status[31:24]; -assign vns_csrbank3_dfii_pi1_rddata2_w = soc_sdram_phaseinjector1_status[23:16]; -assign vns_csrbank3_dfii_pi1_rddata1_w = soc_sdram_phaseinjector1_status[15:8]; -assign vns_csrbank3_dfii_pi1_rddata0_w = soc_sdram_phaseinjector1_status[7:0]; -assign soc_sdram_phaseinjector1_we = vns_csrbank3_dfii_pi1_rddata0_we; -assign vns_csrbank3_dfii_pi2_command0_w = soc_sdram_phaseinjector2_command_storage[5:0]; -assign vns_csrbank3_dfii_pi2_address1_w = soc_sdram_phaseinjector2_address_storage[14:8]; -assign vns_csrbank3_dfii_pi2_address0_w = soc_sdram_phaseinjector2_address_storage[7:0]; -assign vns_csrbank3_dfii_pi2_baddress0_w = soc_sdram_phaseinjector2_baddress_storage[2:0]; -assign vns_csrbank3_dfii_pi2_wrdata3_w = soc_sdram_phaseinjector2_wrdata_storage[31:24]; -assign vns_csrbank3_dfii_pi2_wrdata2_w = soc_sdram_phaseinjector2_wrdata_storage[23:16]; -assign vns_csrbank3_dfii_pi2_wrdata1_w = soc_sdram_phaseinjector2_wrdata_storage[15:8]; -assign vns_csrbank3_dfii_pi2_wrdata0_w = soc_sdram_phaseinjector2_wrdata_storage[7:0]; -assign vns_csrbank3_dfii_pi2_rddata3_w = soc_sdram_phaseinjector2_status[31:24]; -assign vns_csrbank3_dfii_pi2_rddata2_w = soc_sdram_phaseinjector2_status[23:16]; -assign vns_csrbank3_dfii_pi2_rddata1_w = soc_sdram_phaseinjector2_status[15:8]; -assign vns_csrbank3_dfii_pi2_rddata0_w = soc_sdram_phaseinjector2_status[7:0]; -assign soc_sdram_phaseinjector2_we = vns_csrbank3_dfii_pi2_rddata0_we; -assign vns_csrbank3_dfii_pi3_command0_w = soc_sdram_phaseinjector3_command_storage[5:0]; -assign vns_csrbank3_dfii_pi3_address1_w = soc_sdram_phaseinjector3_address_storage[14:8]; -assign vns_csrbank3_dfii_pi3_address0_w = soc_sdram_phaseinjector3_address_storage[7:0]; -assign vns_csrbank3_dfii_pi3_baddress0_w = soc_sdram_phaseinjector3_baddress_storage[2:0]; -assign vns_csrbank3_dfii_pi3_wrdata3_w = soc_sdram_phaseinjector3_wrdata_storage[31:24]; -assign vns_csrbank3_dfii_pi3_wrdata2_w = soc_sdram_phaseinjector3_wrdata_storage[23:16]; -assign vns_csrbank3_dfii_pi3_wrdata1_w = soc_sdram_phaseinjector3_wrdata_storage[15:8]; -assign vns_csrbank3_dfii_pi3_wrdata0_w = soc_sdram_phaseinjector3_wrdata_storage[7:0]; -assign vns_csrbank3_dfii_pi3_rddata3_w = soc_sdram_phaseinjector3_status[31:24]; -assign vns_csrbank3_dfii_pi3_rddata2_w = soc_sdram_phaseinjector3_status[23:16]; -assign vns_csrbank3_dfii_pi3_rddata1_w = soc_sdram_phaseinjector3_status[15:8]; -assign vns_csrbank3_dfii_pi3_rddata0_w = soc_sdram_phaseinjector3_status[7:0]; -assign soc_sdram_phaseinjector3_we = vns_csrbank3_dfii_pi3_rddata0_we; -assign vns_csrbank4_sel = (vns_interface4_bank_bus_adr[13:9] == 3'd4); -assign vns_csrbank4_load3_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_load3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 1'd0)); -assign vns_csrbank4_load3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 1'd0)); -assign vns_csrbank4_load2_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_load2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 1'd1)); -assign vns_csrbank4_load2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 1'd1)); -assign vns_csrbank4_load1_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_load1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 2'd2)); -assign vns_csrbank4_load1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 2'd2)); -assign vns_csrbank4_load0_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_load0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 2'd3)); -assign vns_csrbank4_load0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 2'd3)); -assign vns_csrbank4_reload3_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_reload3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd4)); -assign vns_csrbank4_reload3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd4)); -assign vns_csrbank4_reload2_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_reload2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd5)); -assign vns_csrbank4_reload2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd5)); -assign vns_csrbank4_reload1_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_reload1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd6)); -assign vns_csrbank4_reload1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd6)); -assign vns_csrbank4_reload0_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_reload0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd7)); -assign vns_csrbank4_reload0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd7)); -assign vns_csrbank4_en0_r = vns_interface4_bank_bus_dat_w[0]; -assign vns_csrbank4_en0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd8)); -assign vns_csrbank4_en0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd8)); -assign vns_csrbank4_update_value0_r = vns_interface4_bank_bus_dat_w[0]; -assign vns_csrbank4_update_value0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd9)); -assign vns_csrbank4_update_value0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd9)); -assign vns_csrbank4_value3_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_value3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd10)); -assign vns_csrbank4_value3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd10)); -assign vns_csrbank4_value2_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_value2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd11)); -assign vns_csrbank4_value2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd11)); -assign vns_csrbank4_value1_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_value1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd12)); -assign vns_csrbank4_value1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd12)); -assign vns_csrbank4_value0_r = vns_interface4_bank_bus_dat_w[7:0]; -assign vns_csrbank4_value0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd13)); -assign vns_csrbank4_value0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd13)); -assign soc_litedramcore_timer_eventmanager_status_r = vns_interface4_bank_bus_dat_w[0]; -assign soc_litedramcore_timer_eventmanager_status_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd14)); -assign soc_litedramcore_timer_eventmanager_status_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd14)); -assign soc_litedramcore_timer_eventmanager_pending_r = vns_interface4_bank_bus_dat_w[0]; -assign soc_litedramcore_timer_eventmanager_pending_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd15)); -assign soc_litedramcore_timer_eventmanager_pending_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd15)); -assign vns_csrbank4_ev_enable0_r = vns_interface4_bank_bus_dat_w[0]; -assign vns_csrbank4_ev_enable0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 5'd16)); -assign vns_csrbank4_ev_enable0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 5'd16)); -assign vns_csrbank4_load3_w = soc_litedramcore_timer_load_storage[31:24]; -assign vns_csrbank4_load2_w = soc_litedramcore_timer_load_storage[23:16]; -assign vns_csrbank4_load1_w = soc_litedramcore_timer_load_storage[15:8]; -assign vns_csrbank4_load0_w = soc_litedramcore_timer_load_storage[7:0]; -assign vns_csrbank4_reload3_w = soc_litedramcore_timer_reload_storage[31:24]; -assign vns_csrbank4_reload2_w = soc_litedramcore_timer_reload_storage[23:16]; -assign vns_csrbank4_reload1_w = soc_litedramcore_timer_reload_storage[15:8]; -assign vns_csrbank4_reload0_w = soc_litedramcore_timer_reload_storage[7:0]; -assign vns_csrbank4_en0_w = soc_litedramcore_timer_en_storage; -assign vns_csrbank4_update_value0_w = soc_litedramcore_timer_update_value_storage; -assign vns_csrbank4_value3_w = soc_litedramcore_timer_value_status[31:24]; -assign vns_csrbank4_value2_w = soc_litedramcore_timer_value_status[23:16]; -assign vns_csrbank4_value1_w = soc_litedramcore_timer_value_status[15:8]; -assign vns_csrbank4_value0_w = soc_litedramcore_timer_value_status[7:0]; -assign soc_litedramcore_timer_value_we = vns_csrbank4_value0_we; -assign vns_csrbank4_ev_enable0_w = soc_litedramcore_timer_eventmanager_storage; -assign vns_csrbank5_sel = (vns_interface5_bank_bus_adr[13:9] == 2'd3); -assign soc_litedramcore_uart_rxtx_r = vns_interface5_bank_bus_dat_w[7:0]; -assign soc_litedramcore_uart_rxtx_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 1'd0)); -assign soc_litedramcore_uart_rxtx_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 1'd0)); -assign vns_csrbank5_txfull_r = vns_interface5_bank_bus_dat_w[0]; -assign vns_csrbank5_txfull_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 1'd1)); -assign vns_csrbank5_txfull_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 1'd1)); -assign vns_csrbank5_rxempty_r = vns_interface5_bank_bus_dat_w[0]; -assign vns_csrbank5_rxempty_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 2'd2)); -assign vns_csrbank5_rxempty_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 2'd2)); -assign soc_litedramcore_uart_eventmanager_status_r = vns_interface5_bank_bus_dat_w[1:0]; -assign soc_litedramcore_uart_eventmanager_status_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 2'd3)); -assign soc_litedramcore_uart_eventmanager_status_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 2'd3)); -assign soc_litedramcore_uart_eventmanager_pending_r = vns_interface5_bank_bus_dat_w[1:0]; -assign soc_litedramcore_uart_eventmanager_pending_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 3'd4)); -assign soc_litedramcore_uart_eventmanager_pending_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 3'd4)); -assign vns_csrbank5_ev_enable0_r = vns_interface5_bank_bus_dat_w[1:0]; -assign vns_csrbank5_ev_enable0_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 3'd5)); -assign vns_csrbank5_ev_enable0_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 3'd5)); -assign vns_csrbank5_txfull_w = soc_litedramcore_uart_txfull_status; -assign soc_litedramcore_uart_txfull_we = vns_csrbank5_txfull_we; -assign vns_csrbank5_rxempty_w = soc_litedramcore_uart_rxempty_status; -assign soc_litedramcore_uart_rxempty_we = vns_csrbank5_rxempty_we; -assign vns_csrbank5_ev_enable0_w = soc_litedramcore_uart_eventmanager_storage[1:0]; -assign vns_csrbank6_sel = (vns_interface6_bank_bus_adr[13:9] == 2'd2); -assign vns_csrbank6_tuning_word3_r = vns_interface6_bank_bus_dat_w[7:0]; -assign vns_csrbank6_tuning_word3_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 1'd0)); -assign vns_csrbank6_tuning_word3_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 1'd0)); -assign vns_csrbank6_tuning_word2_r = vns_interface6_bank_bus_dat_w[7:0]; -assign vns_csrbank6_tuning_word2_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 1'd1)); -assign vns_csrbank6_tuning_word2_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 1'd1)); -assign vns_csrbank6_tuning_word1_r = vns_interface6_bank_bus_dat_w[7:0]; -assign vns_csrbank6_tuning_word1_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 2'd2)); -assign vns_csrbank6_tuning_word1_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 2'd2)); -assign vns_csrbank6_tuning_word0_r = vns_interface6_bank_bus_dat_w[7:0]; -assign vns_csrbank6_tuning_word0_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 2'd3)); -assign vns_csrbank6_tuning_word0_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 2'd3)); -assign vns_csrbank6_tuning_word3_w = soc_litedramcore_storage[31:24]; -assign vns_csrbank6_tuning_word2_w = soc_litedramcore_storage[23:16]; -assign vns_csrbank6_tuning_word1_w = soc_litedramcore_storage[15:8]; -assign vns_csrbank6_tuning_word0_w = soc_litedramcore_storage[7:0]; -assign vns_adr = soc_litedramcore_interface_adr; -assign vns_we = soc_litedramcore_interface_we; -assign vns_dat_w = soc_litedramcore_interface_dat_w; -assign soc_litedramcore_interface_dat_r = vns_dat_r; -assign vns_interface0_bank_bus_adr = vns_adr; -assign vns_interface1_bank_bus_adr = vns_adr; -assign vns_interface2_bank_bus_adr = vns_adr; -assign vns_interface3_bank_bus_adr = vns_adr; -assign vns_interface4_bank_bus_adr = vns_adr; -assign vns_interface5_bank_bus_adr = vns_adr; -assign vns_interface6_bank_bus_adr = vns_adr; -assign vns_interface0_bank_bus_we = vns_we; -assign vns_interface1_bank_bus_we = vns_we; -assign vns_interface2_bank_bus_we = vns_we; -assign vns_interface3_bank_bus_we = vns_we; -assign vns_interface4_bank_bus_we = vns_we; -assign vns_interface5_bank_bus_we = vns_we; -assign vns_interface6_bank_bus_we = vns_we; -assign vns_interface0_bank_bus_dat_w = vns_dat_w; -assign vns_interface1_bank_bus_dat_w = vns_dat_w; -assign vns_interface2_bank_bus_dat_w = vns_dat_w; -assign vns_interface3_bank_bus_dat_w = vns_dat_w; -assign vns_interface4_bank_bus_dat_w = vns_dat_w; -assign vns_interface5_bank_bus_dat_w = vns_dat_w; -assign vns_interface6_bank_bus_dat_w = vns_dat_w; -assign vns_dat_r = ((((((vns_interface0_bank_bus_dat_r | vns_interface1_bank_bus_dat_r) | vns_interface2_bank_bus_dat_r) | vns_interface3_bank_bus_dat_r) | vns_interface4_bank_bus_dat_r) | vns_interface5_bank_bus_dat_r) | vns_interface6_bank_bus_dat_r); // synthesis translate_off -reg dummy_d_338; +reg dummy_d_274; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed0 <= 1'd0; - case (soc_sdram_choose_cmd_grant) - 1'd0: begin - vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[0]; - end + litedramcore_choose_req_want_reads <= 1'd0; + case (multiplexer_state) 1'd1: begin - vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[1]; end 2'd2: begin - vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[2]; end 2'd3: begin - vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[3]; end 3'd4: begin - vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[4]; end 3'd5: begin - vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[5]; end 3'd6: begin - vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[6]; + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin end default: begin - vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[7]; + litedramcore_choose_req_want_reads <= 1'd1; end endcase // synthesis translate_off - dummy_d_338 = dummy_s; + dummy_d_274 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_339; +reg dummy_d_275; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed1 <= 15'd0; - case (soc_sdram_choose_cmd_grant) - 1'd0: begin - vns_rhs_array_muxed1 <= soc_sdram_bankmachine0_cmd_payload_a; - end + litedramcore_choose_req_want_writes <= 1'd0; + case (multiplexer_state) 1'd1: begin - vns_rhs_array_muxed1 <= soc_sdram_bankmachine1_cmd_payload_a; + litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin - vns_rhs_array_muxed1 <= soc_sdram_bankmachine2_cmd_payload_a; end 2'd3: begin - vns_rhs_array_muxed1 <= soc_sdram_bankmachine3_cmd_payload_a; end 3'd4: begin - vns_rhs_array_muxed1 <= soc_sdram_bankmachine4_cmd_payload_a; end 3'd5: begin - vns_rhs_array_muxed1 <= soc_sdram_bankmachine5_cmd_payload_a; end 3'd6: begin - vns_rhs_array_muxed1 <= soc_sdram_bankmachine6_cmd_payload_a; + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin end default: begin - vns_rhs_array_muxed1 <= soc_sdram_bankmachine7_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_339 = dummy_s; + dummy_d_275 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_340; +reg dummy_d_276; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed2 <= 3'd0; - case (soc_sdram_choose_cmd_grant) - 1'd0: begin - vns_rhs_array_muxed2 <= soc_sdram_bankmachine0_cmd_payload_ba; - end + litedramcore_choose_req_cmd_ready <= 1'd0; + case (multiplexer_state) 1'd1: begin - vns_rhs_array_muxed2 <= soc_sdram_bankmachine1_cmd_payload_ba; + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end 2'd2: begin - vns_rhs_array_muxed2 <= soc_sdram_bankmachine2_cmd_payload_ba; end 2'd3: begin - vns_rhs_array_muxed2 <= soc_sdram_bankmachine3_cmd_payload_ba; end 3'd4: begin - vns_rhs_array_muxed2 <= soc_sdram_bankmachine4_cmd_payload_ba; end 3'd5: begin - vns_rhs_array_muxed2 <= soc_sdram_bankmachine5_cmd_payload_ba; end 3'd6: begin - vns_rhs_array_muxed2 <= soc_sdram_bankmachine6_cmd_payload_ba; + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin end default: begin - vns_rhs_array_muxed2 <= soc_sdram_bankmachine7_cmd_payload_ba; + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end endcase // synthesis translate_off - dummy_d_340 = dummy_s; + dummy_d_276 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_341; +reg dummy_d_277; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed3 <= 1'd0; - case (soc_sdram_choose_cmd_grant) - 1'd0: begin - vns_rhs_array_muxed3 <= soc_sdram_bankmachine0_cmd_payload_is_read; - end + litedramcore_en1 <= 1'd0; + case (multiplexer_state) 1'd1: begin - vns_rhs_array_muxed3 <= soc_sdram_bankmachine1_cmd_payload_is_read; + litedramcore_en1 <= 1'd1; end 2'd2: begin - vns_rhs_array_muxed3 <= soc_sdram_bankmachine2_cmd_payload_is_read; end 2'd3: begin - vns_rhs_array_muxed3 <= soc_sdram_bankmachine3_cmd_payload_is_read; end 3'd4: begin - vns_rhs_array_muxed3 <= soc_sdram_bankmachine4_cmd_payload_is_read; end 3'd5: begin - vns_rhs_array_muxed3 <= soc_sdram_bankmachine5_cmd_payload_is_read; end 3'd6: begin - vns_rhs_array_muxed3 <= soc_sdram_bankmachine6_cmd_payload_is_read; + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin end default: begin - vns_rhs_array_muxed3 <= soc_sdram_bankmachine7_cmd_payload_is_read; end endcase // synthesis translate_off - dummy_d_341 = dummy_s; + dummy_d_277 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_342; +reg dummy_d_278; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed4 <= 1'd0; - case (soc_sdram_choose_cmd_grant) - 1'd0: begin - vns_rhs_array_muxed4 <= soc_sdram_bankmachine0_cmd_payload_is_write; - end + litedramcore_steerer_sel0 <= 2'd0; + case (multiplexer_state) 1'd1: begin - vns_rhs_array_muxed4 <= soc_sdram_bankmachine1_cmd_payload_is_write; + litedramcore_steerer_sel0 <= 1'd0; end 2'd2: begin - vns_rhs_array_muxed4 <= soc_sdram_bankmachine2_cmd_payload_is_write; + litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin - vns_rhs_array_muxed4 <= soc_sdram_bankmachine3_cmd_payload_is_write; end 3'd4: begin - vns_rhs_array_muxed4 <= soc_sdram_bankmachine4_cmd_payload_is_write; end 3'd5: begin - vns_rhs_array_muxed4 <= soc_sdram_bankmachine5_cmd_payload_is_write; end 3'd6: begin - vns_rhs_array_muxed4 <= soc_sdram_bankmachine6_cmd_payload_is_write; + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin end default: begin - vns_rhs_array_muxed4 <= soc_sdram_bankmachine7_cmd_payload_is_write; + litedramcore_steerer_sel0 <= 1'd0; end endcase // synthesis translate_off - dummy_d_342 = dummy_s; + dummy_d_278 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_343; +reg dummy_d_279; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed5 <= 1'd0; - case (soc_sdram_choose_cmd_grant) - 1'd0: begin - vns_rhs_array_muxed5 <= soc_sdram_bankmachine0_cmd_payload_is_cmd; - end + litedramcore_steerer_sel1 <= 2'd0; + case (multiplexer_state) 1'd1: begin - vns_rhs_array_muxed5 <= soc_sdram_bankmachine1_cmd_payload_is_cmd; + litedramcore_steerer_sel1 <= 1'd0; end 2'd2: begin - vns_rhs_array_muxed5 <= soc_sdram_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - vns_rhs_array_muxed5 <= soc_sdram_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - vns_rhs_array_muxed5 <= soc_sdram_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - vns_rhs_array_muxed5 <= soc_sdram_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - vns_rhs_array_muxed5 <= soc_sdram_bankmachine6_cmd_payload_is_cmd; + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin end default: begin - vns_rhs_array_muxed5 <= soc_sdram_bankmachine7_cmd_payload_is_cmd; + litedramcore_steerer_sel1 <= 1'd1; end endcase // synthesis translate_off - dummy_d_343 = dummy_s; + dummy_d_279 = dummy_s; // synthesis translate_on end +assign roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); +assign litedramcore_interface_bank0_addr = rhs_array_muxed12; +assign litedramcore_interface_bank0_we = rhs_array_muxed13; +assign litedramcore_interface_bank0_valid = rhs_array_muxed14; +assign roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock)); +assign litedramcore_interface_bank1_addr = rhs_array_muxed15; +assign litedramcore_interface_bank1_we = rhs_array_muxed16; +assign litedramcore_interface_bank1_valid = rhs_array_muxed17; +assign roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock)); +assign litedramcore_interface_bank2_addr = rhs_array_muxed18; +assign litedramcore_interface_bank2_we = rhs_array_muxed19; +assign litedramcore_interface_bank2_valid = rhs_array_muxed20; +assign roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock)); +assign litedramcore_interface_bank3_addr = rhs_array_muxed21; +assign litedramcore_interface_bank3_we = rhs_array_muxed22; +assign litedramcore_interface_bank3_valid = rhs_array_muxed23; +assign roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock)); +assign litedramcore_interface_bank4_addr = rhs_array_muxed24; +assign litedramcore_interface_bank4_we = rhs_array_muxed25; +assign litedramcore_interface_bank4_valid = rhs_array_muxed26; +assign roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock)); +assign litedramcore_interface_bank5_addr = rhs_array_muxed27; +assign litedramcore_interface_bank5_we = rhs_array_muxed28; +assign litedramcore_interface_bank5_valid = rhs_array_muxed29; +assign roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock)); +assign litedramcore_interface_bank6_addr = rhs_array_muxed30; +assign litedramcore_interface_bank6_we = rhs_array_muxed31; +assign litedramcore_interface_bank6_valid = rhs_array_muxed32; +assign roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock)); +assign litedramcore_interface_bank7_addr = rhs_array_muxed33; +assign litedramcore_interface_bank7_we = rhs_array_muxed34; +assign litedramcore_interface_bank7_valid = rhs_array_muxed35; +assign user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready)); +assign user_port_wdata_ready = new_master_wdata_ready2; +assign user_port_rdata_valid = new_master_rdata_valid8; // synthesis translate_off -reg dummy_d_344; +reg dummy_d_280; // synthesis translate_on always @(*) begin - vns_t_array_muxed0 <= 1'd0; - case (soc_sdram_choose_cmd_grant) - 1'd0: begin - vns_t_array_muxed0 <= soc_sdram_bankmachine0_cmd_payload_cas; - end + litedramcore_interface_wdata <= 128'd0; + case ({new_master_wdata_ready2}) 1'd1: begin - vns_t_array_muxed0 <= soc_sdram_bankmachine1_cmd_payload_cas; - end - 2'd2: begin - vns_t_array_muxed0 <= soc_sdram_bankmachine2_cmd_payload_cas; - end - 2'd3: begin - vns_t_array_muxed0 <= soc_sdram_bankmachine3_cmd_payload_cas; - end - 3'd4: begin - vns_t_array_muxed0 <= soc_sdram_bankmachine4_cmd_payload_cas; + litedramcore_interface_wdata <= user_port_wdata_payload_data; end - 3'd5: begin - vns_t_array_muxed0 <= soc_sdram_bankmachine5_cmd_payload_cas; + default: begin + litedramcore_interface_wdata <= 1'd0; end - 3'd6: begin - vns_t_array_muxed0 <= soc_sdram_bankmachine6_cmd_payload_cas; + endcase +// synthesis translate_off + dummy_d_280 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_281; +// synthesis translate_on +always @(*) begin + litedramcore_interface_wdata_we <= 16'd0; + case ({new_master_wdata_ready2}) + 1'd1: begin + litedramcore_interface_wdata_we <= user_port_wdata_payload_we; end default: begin - vns_t_array_muxed0 <= soc_sdram_bankmachine7_cmd_payload_cas; + litedramcore_interface_wdata_we <= 1'd0; end endcase // synthesis translate_off - dummy_d_344 = dummy_s; + dummy_d_281 = dummy_s; // synthesis translate_on end +assign user_port_rdata_payload_data = litedramcore_interface_rdata; +assign roundrobin0_grant = 1'd0; +assign roundrobin1_grant = 1'd0; +assign roundrobin2_grant = 1'd0; +assign roundrobin3_grant = 1'd0; +assign roundrobin4_grant = 1'd0; +assign roundrobin5_grant = 1'd0; +assign roundrobin6_grant = 1'd0; +assign roundrobin7_grant = 1'd0; // synthesis translate_off -reg dummy_d_345; +reg dummy_d_282; +// synthesis translate_on +always @(*) begin + csrbank0_sel <= 1'd0; + csrbank0_sel <= (interface0_bank_bus_adr[13:11] == 2'd2); + if (interface0_bank_bus_adr[0]) begin + csrbank0_sel <= 1'd0; + end +// synthesis translate_off + dummy_d_282 = dummy_s; +// synthesis translate_on +end +assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; +assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd0)); +assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd0)); +assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; +assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd1)); +assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd1)); +assign csrbank0_init_done0_w = init_done_storage; +assign csrbank0_init_error0_w = init_error_storage; + +// synthesis translate_off +reg dummy_d_283; +// synthesis translate_on +always @(*) begin + csrbank1_sel <= 1'd0; + csrbank1_sel <= (interface1_bank_bus_adr[13:11] == 1'd0); + if (interface1_bank_bus_adr[0]) begin + csrbank1_sel <= 1'd0; + end +// synthesis translate_off + dummy_d_283 = dummy_s; +// synthesis translate_on +end +assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; +assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd0)); +assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd0)); +assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; +assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd1)); +assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd1)); +assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; +assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd2)); +assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd2)); +assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0]; +assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd3)); +assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd3)); +assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0]; +assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd4)); +assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd4)); +assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; +assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd5)); +assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd5)); +assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; +assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd6)); +assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; +assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd7)); +assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; +assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; +assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd9)); +assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0]; +assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; +assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; + +// synthesis translate_off +reg dummy_d_284; +// synthesis translate_on +always @(*) begin + csrbank2_sel <= 1'd0; + csrbank2_sel <= (interface2_bank_bus_adr[13:11] == 1'd1); + if (interface2_bank_bus_adr[0]) begin + csrbank2_sel <= 1'd0; + end +// synthesis translate_off + dummy_d_284 = dummy_s; +// synthesis translate_on +end +assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; +assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd0)); +assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd0)); +assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; +assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd1)); +assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd1)); +assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; +assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd2)); +assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd2)); +assign csrbank2_dfii_pi0_address1_r = interface2_bank_bus_dat_w[6:0]; +assign csrbank2_dfii_pi0_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd3)); +assign csrbank2_dfii_pi0_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd3)); +assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd4)); +assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd4)); +assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd5)); +assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd5)); +assign csrbank2_dfii_pi0_wrdata3_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi0_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd6)); +assign csrbank2_dfii_pi0_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd6)); +assign csrbank2_dfii_pi0_wrdata2_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi0_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd7)); +assign csrbank2_dfii_pi0_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd7)); +assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi0_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd8)); +assign csrbank2_dfii_pi0_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd8)); +assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd9)); +assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd9)); +assign csrbank2_dfii_pi0_rddata3_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi0_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd10)); +assign csrbank2_dfii_pi0_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd10)); +assign csrbank2_dfii_pi0_rddata2_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi0_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd11)); +assign csrbank2_dfii_pi0_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd11)); +assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi0_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd12)); +assign csrbank2_dfii_pi0_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd12)); +assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi0_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd13)); +assign csrbank2_dfii_pi0_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd13)); +assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; +assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd14)); +assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd14)); +assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; +assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd15)); +assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd15)); +assign csrbank2_dfii_pi1_address1_r = interface2_bank_bus_dat_w[6:0]; +assign csrbank2_dfii_pi1_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd16)); +assign csrbank2_dfii_pi1_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd16)); +assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd17)); +assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd17)); +assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd18)); +assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd18)); +assign csrbank2_dfii_pi1_wrdata3_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi1_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd19)); +assign csrbank2_dfii_pi1_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd19)); +assign csrbank2_dfii_pi1_wrdata2_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi1_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd20)); +assign csrbank2_dfii_pi1_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd20)); +assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi1_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd21)); +assign csrbank2_dfii_pi1_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd21)); +assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd22)); +assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd22)); +assign csrbank2_dfii_pi1_rddata3_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi1_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd23)); +assign csrbank2_dfii_pi1_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd23)); +assign csrbank2_dfii_pi1_rddata2_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi1_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd24)); +assign csrbank2_dfii_pi1_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd24)); +assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi1_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd25)); +assign csrbank2_dfii_pi1_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd25)); +assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi1_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd26)); +assign csrbank2_dfii_pi1_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd26)); +assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; +assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd27)); +assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd27)); +assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; +assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd28)); +assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd28)); +assign csrbank2_dfii_pi2_address1_r = interface2_bank_bus_dat_w[6:0]; +assign csrbank2_dfii_pi2_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd29)); +assign csrbank2_dfii_pi2_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd29)); +assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd30)); +assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd30)); +assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd31)); +assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd31)); +assign csrbank2_dfii_pi2_wrdata3_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi2_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd32)); +assign csrbank2_dfii_pi2_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd32)); +assign csrbank2_dfii_pi2_wrdata2_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi2_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd33)); +assign csrbank2_dfii_pi2_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd33)); +assign csrbank2_dfii_pi2_wrdata1_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi2_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd34)); +assign csrbank2_dfii_pi2_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd34)); +assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd35)); +assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd35)); +assign csrbank2_dfii_pi2_rddata3_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi2_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd36)); +assign csrbank2_dfii_pi2_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd36)); +assign csrbank2_dfii_pi2_rddata2_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi2_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd37)); +assign csrbank2_dfii_pi2_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd37)); +assign csrbank2_dfii_pi2_rddata1_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi2_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd38)); +assign csrbank2_dfii_pi2_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd38)); +assign csrbank2_dfii_pi2_rddata0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi2_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd39)); +assign csrbank2_dfii_pi2_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd39)); +assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; +assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd40)); +assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd40)); +assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; +assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd41)); +assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd41)); +assign csrbank2_dfii_pi3_address1_r = interface2_bank_bus_dat_w[6:0]; +assign csrbank2_dfii_pi3_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd42)); +assign csrbank2_dfii_pi3_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd42)); +assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd43)); +assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd43)); +assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; +assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd44)); +assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd44)); +assign csrbank2_dfii_pi3_wrdata3_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi3_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd45)); +assign csrbank2_dfii_pi3_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd45)); +assign csrbank2_dfii_pi3_wrdata2_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi3_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd46)); +assign csrbank2_dfii_pi3_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd46)); +assign csrbank2_dfii_pi3_wrdata1_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi3_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd47)); +assign csrbank2_dfii_pi3_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd47)); +assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd48)); +assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd48)); +assign csrbank2_dfii_pi3_rddata3_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi3_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd49)); +assign csrbank2_dfii_pi3_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd49)); +assign csrbank2_dfii_pi3_rddata2_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi3_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd50)); +assign csrbank2_dfii_pi3_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd50)); +assign csrbank2_dfii_pi3_rddata1_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi3_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd51)); +assign csrbank2_dfii_pi3_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd51)); +assign csrbank2_dfii_pi3_rddata0_r = interface2_bank_bus_dat_w[7:0]; +assign csrbank2_dfii_pi3_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd52)); +assign csrbank2_dfii_pi3_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd52)); +assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; +assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; +assign csrbank2_dfii_pi0_address1_w = litedramcore_phaseinjector0_address_storage[14:8]; +assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[7:0]; +assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; +assign csrbank2_dfii_pi0_wrdata3_w = litedramcore_phaseinjector0_wrdata_storage[31:24]; +assign csrbank2_dfii_pi0_wrdata2_w = litedramcore_phaseinjector0_wrdata_storage[23:16]; +assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[15:8]; +assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[7:0]; +assign csrbank2_dfii_pi0_rddata3_w = litedramcore_phaseinjector0_status[31:24]; +assign csrbank2_dfii_pi0_rddata2_w = litedramcore_phaseinjector0_status[23:16]; +assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_status[15:8]; +assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_status[7:0]; +assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata0_we; +assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0]; +assign csrbank2_dfii_pi1_address1_w = litedramcore_phaseinjector1_address_storage[14:8]; +assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[7:0]; +assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; +assign csrbank2_dfii_pi1_wrdata3_w = litedramcore_phaseinjector1_wrdata_storage[31:24]; +assign csrbank2_dfii_pi1_wrdata2_w = litedramcore_phaseinjector1_wrdata_storage[23:16]; +assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[15:8]; +assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[7:0]; +assign csrbank2_dfii_pi1_rddata3_w = litedramcore_phaseinjector1_status[31:24]; +assign csrbank2_dfii_pi1_rddata2_w = litedramcore_phaseinjector1_status[23:16]; +assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_status[15:8]; +assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_status[7:0]; +assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata0_we; +assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0]; +assign csrbank2_dfii_pi2_address1_w = litedramcore_phaseinjector2_address_storage[14:8]; +assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[7:0]; +assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0]; +assign csrbank2_dfii_pi2_wrdata3_w = litedramcore_phaseinjector2_wrdata_storage[31:24]; +assign csrbank2_dfii_pi2_wrdata2_w = litedramcore_phaseinjector2_wrdata_storage[23:16]; +assign csrbank2_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[15:8]; +assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[7:0]; +assign csrbank2_dfii_pi2_rddata3_w = litedramcore_phaseinjector2_status[31:24]; +assign csrbank2_dfii_pi2_rddata2_w = litedramcore_phaseinjector2_status[23:16]; +assign csrbank2_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_status[15:8]; +assign csrbank2_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_status[7:0]; +assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata0_we; +assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0]; +assign csrbank2_dfii_pi3_address1_w = litedramcore_phaseinjector3_address_storage[14:8]; +assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[7:0]; +assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0]; +assign csrbank2_dfii_pi3_wrdata3_w = litedramcore_phaseinjector3_wrdata_storage[31:24]; +assign csrbank2_dfii_pi3_wrdata2_w = litedramcore_phaseinjector3_wrdata_storage[23:16]; +assign csrbank2_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[15:8]; +assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[7:0]; +assign csrbank2_dfii_pi3_rddata3_w = litedramcore_phaseinjector3_status[31:24]; +assign csrbank2_dfii_pi3_rddata2_w = litedramcore_phaseinjector3_status[23:16]; +assign csrbank2_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_status[15:8]; +assign csrbank2_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_status[7:0]; +assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata0_we; +assign adr = csr_port_adr; +assign we = csr_port_we; +assign dat_w = csr_port_dat_w; +assign csr_port_dat_r = dat_r; +assign interface0_bank_bus_adr = adr; +assign interface1_bank_bus_adr = adr; +assign interface2_bank_bus_adr = adr; +assign interface0_bank_bus_we = we; +assign interface1_bank_bus_we = we; +assign interface2_bank_bus_we = we; +assign interface0_bank_bus_dat_w = dat_w; +assign interface1_bank_bus_dat_w = dat_w; +assign interface2_bank_bus_dat_w = dat_w; +assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); + +// synthesis translate_off +reg dummy_d_285; // synthesis translate_on always @(*) begin - vns_t_array_muxed1 <= 1'd0; - case (soc_sdram_choose_cmd_grant) + rhs_array_muxed0 <= 1'd0; + case (litedramcore_choose_cmd_grant) 1'd0: begin - vns_t_array_muxed1 <= soc_sdram_bankmachine0_cmd_payload_ras; + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; end 1'd1: begin - vns_t_array_muxed1 <= soc_sdram_bankmachine1_cmd_payload_ras; + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; end 2'd2: begin - vns_t_array_muxed1 <= soc_sdram_bankmachine2_cmd_payload_ras; + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; end 2'd3: begin - vns_t_array_muxed1 <= soc_sdram_bankmachine3_cmd_payload_ras; + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; end 3'd4: begin - vns_t_array_muxed1 <= soc_sdram_bankmachine4_cmd_payload_ras; + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; end 3'd5: begin - vns_t_array_muxed1 <= soc_sdram_bankmachine5_cmd_payload_ras; + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; end 3'd6: begin - vns_t_array_muxed1 <= soc_sdram_bankmachine6_cmd_payload_ras; + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; end default: begin - vns_t_array_muxed1 <= soc_sdram_bankmachine7_cmd_payload_ras; + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; end endcase // synthesis translate_off - dummy_d_345 = dummy_s; + dummy_d_285 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_346; +reg dummy_d_286; // synthesis translate_on always @(*) begin - vns_t_array_muxed2 <= 1'd0; - case (soc_sdram_choose_cmd_grant) + rhs_array_muxed1 <= 15'd0; + case (litedramcore_choose_cmd_grant) 1'd0: begin - vns_t_array_muxed2 <= soc_sdram_bankmachine0_cmd_payload_we; + rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - vns_t_array_muxed2 <= soc_sdram_bankmachine1_cmd_payload_we; + rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - vns_t_array_muxed2 <= soc_sdram_bankmachine2_cmd_payload_we; + rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - vns_t_array_muxed2 <= soc_sdram_bankmachine3_cmd_payload_we; + rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - vns_t_array_muxed2 <= soc_sdram_bankmachine4_cmd_payload_we; + rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - vns_t_array_muxed2 <= soc_sdram_bankmachine5_cmd_payload_we; + rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - vns_t_array_muxed2 <= soc_sdram_bankmachine6_cmd_payload_we; + rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; end default: begin - vns_t_array_muxed2 <= soc_sdram_bankmachine7_cmd_payload_we; + rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_346 = dummy_s; + dummy_d_286 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_347; +reg dummy_d_287; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed6 <= 1'd0; - case (soc_sdram_choose_req_grant) + rhs_array_muxed2 <= 3'd0; + case (litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[0]; + rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[1]; + rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[2]; + rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[3]; + rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[4]; + rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[5]; + rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[6]; + rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; end default: begin - vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[7]; + rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; end endcase // synthesis translate_off - dummy_d_347 = dummy_s; + dummy_d_287 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_348; +reg dummy_d_288; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed7 <= 15'd0; - case (soc_sdram_choose_req_grant) + rhs_array_muxed3 <= 1'd0; + case (litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed7 <= soc_sdram_bankmachine0_cmd_payload_a; + rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - vns_rhs_array_muxed7 <= soc_sdram_bankmachine1_cmd_payload_a; + rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - vns_rhs_array_muxed7 <= soc_sdram_bankmachine2_cmd_payload_a; + rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - vns_rhs_array_muxed7 <= soc_sdram_bankmachine3_cmd_payload_a; + rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - vns_rhs_array_muxed7 <= soc_sdram_bankmachine4_cmd_payload_a; + rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - vns_rhs_array_muxed7 <= soc_sdram_bankmachine5_cmd_payload_a; + rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - vns_rhs_array_muxed7 <= soc_sdram_bankmachine6_cmd_payload_a; + rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - vns_rhs_array_muxed7 <= soc_sdram_bankmachine7_cmd_payload_a; + rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; end endcase // synthesis translate_off - dummy_d_348 = dummy_s; + dummy_d_288 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_349; +reg dummy_d_289; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed8 <= 3'd0; - case (soc_sdram_choose_req_grant) + rhs_array_muxed4 <= 1'd0; + case (litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed8 <= soc_sdram_bankmachine0_cmd_payload_ba; + rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - vns_rhs_array_muxed8 <= soc_sdram_bankmachine1_cmd_payload_ba; + rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - vns_rhs_array_muxed8 <= soc_sdram_bankmachine2_cmd_payload_ba; + rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - vns_rhs_array_muxed8 <= soc_sdram_bankmachine3_cmd_payload_ba; + rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - vns_rhs_array_muxed8 <= soc_sdram_bankmachine4_cmd_payload_ba; + rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - vns_rhs_array_muxed8 <= soc_sdram_bankmachine5_cmd_payload_ba; + rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - vns_rhs_array_muxed8 <= soc_sdram_bankmachine6_cmd_payload_ba; + rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - vns_rhs_array_muxed8 <= soc_sdram_bankmachine7_cmd_payload_ba; + rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; end endcase // synthesis translate_off - dummy_d_349 = dummy_s; + dummy_d_289 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_350; +reg dummy_d_290; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed9 <= 1'd0; - case (soc_sdram_choose_req_grant) + rhs_array_muxed5 <= 1'd0; + case (litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed9 <= soc_sdram_bankmachine0_cmd_payload_is_read; + rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - vns_rhs_array_muxed9 <= soc_sdram_bankmachine1_cmd_payload_is_read; + rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - vns_rhs_array_muxed9 <= soc_sdram_bankmachine2_cmd_payload_is_read; + rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - vns_rhs_array_muxed9 <= soc_sdram_bankmachine3_cmd_payload_is_read; + rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - vns_rhs_array_muxed9 <= soc_sdram_bankmachine4_cmd_payload_is_read; + rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - vns_rhs_array_muxed9 <= soc_sdram_bankmachine5_cmd_payload_is_read; + rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - vns_rhs_array_muxed9 <= soc_sdram_bankmachine6_cmd_payload_is_read; + rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - vns_rhs_array_muxed9 <= soc_sdram_bankmachine7_cmd_payload_is_read; + rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase // synthesis translate_off - dummy_d_350 = dummy_s; + dummy_d_290 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_351; +reg dummy_d_291; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed10 <= 1'd0; - case (soc_sdram_choose_req_grant) + t_array_muxed0 <= 1'd0; + case (litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed10 <= soc_sdram_bankmachine0_cmd_payload_is_write; + t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - vns_rhs_array_muxed10 <= soc_sdram_bankmachine1_cmd_payload_is_write; + t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - vns_rhs_array_muxed10 <= soc_sdram_bankmachine2_cmd_payload_is_write; + t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - vns_rhs_array_muxed10 <= soc_sdram_bankmachine3_cmd_payload_is_write; + t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - vns_rhs_array_muxed10 <= soc_sdram_bankmachine4_cmd_payload_is_write; + t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - vns_rhs_array_muxed10 <= soc_sdram_bankmachine5_cmd_payload_is_write; + t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - vns_rhs_array_muxed10 <= soc_sdram_bankmachine6_cmd_payload_is_write; + t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; end default: begin - vns_rhs_array_muxed10 <= soc_sdram_bankmachine7_cmd_payload_is_write; + t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; end endcase // synthesis translate_off - dummy_d_351 = dummy_s; + dummy_d_291 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_352; +reg dummy_d_292; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed11 <= 1'd0; - case (soc_sdram_choose_req_grant) + t_array_muxed1 <= 1'd0; + case (litedramcore_choose_cmd_grant) 1'd0: begin - vns_rhs_array_muxed11 <= soc_sdram_bankmachine0_cmd_payload_is_cmd; + t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - vns_rhs_array_muxed11 <= soc_sdram_bankmachine1_cmd_payload_is_cmd; + t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - vns_rhs_array_muxed11 <= soc_sdram_bankmachine2_cmd_payload_is_cmd; + t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - vns_rhs_array_muxed11 <= soc_sdram_bankmachine3_cmd_payload_is_cmd; + t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - vns_rhs_array_muxed11 <= soc_sdram_bankmachine4_cmd_payload_is_cmd; + t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - vns_rhs_array_muxed11 <= soc_sdram_bankmachine5_cmd_payload_is_cmd; + t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - vns_rhs_array_muxed11 <= soc_sdram_bankmachine6_cmd_payload_is_cmd; + t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; end default: begin - vns_rhs_array_muxed11 <= soc_sdram_bankmachine7_cmd_payload_is_cmd; + t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; end endcase // synthesis translate_off - dummy_d_352 = dummy_s; + dummy_d_292 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_353; +reg dummy_d_293; // synthesis translate_on always @(*) begin - vns_t_array_muxed3 <= 1'd0; - case (soc_sdram_choose_req_grant) + t_array_muxed2 <= 1'd0; + case (litedramcore_choose_cmd_grant) 1'd0: begin - vns_t_array_muxed3 <= soc_sdram_bankmachine0_cmd_payload_cas; + t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - vns_t_array_muxed3 <= soc_sdram_bankmachine1_cmd_payload_cas; + t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - vns_t_array_muxed3 <= soc_sdram_bankmachine2_cmd_payload_cas; + t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - vns_t_array_muxed3 <= soc_sdram_bankmachine3_cmd_payload_cas; + t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - vns_t_array_muxed3 <= soc_sdram_bankmachine4_cmd_payload_cas; + t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - vns_t_array_muxed3 <= soc_sdram_bankmachine5_cmd_payload_cas; + t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - vns_t_array_muxed3 <= soc_sdram_bankmachine6_cmd_payload_cas; + t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; end default: begin - vns_t_array_muxed3 <= soc_sdram_bankmachine7_cmd_payload_cas; + t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_353 = dummy_s; + dummy_d_293 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_354; +reg dummy_d_294; // synthesis translate_on always @(*) begin - vns_t_array_muxed4 <= 1'd0; - case (soc_sdram_choose_req_grant) + rhs_array_muxed6 <= 1'd0; + case (litedramcore_choose_req_grant) 1'd0: begin - vns_t_array_muxed4 <= soc_sdram_bankmachine0_cmd_payload_ras; + rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; end 1'd1: begin - vns_t_array_muxed4 <= soc_sdram_bankmachine1_cmd_payload_ras; + rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; end 2'd2: begin - vns_t_array_muxed4 <= soc_sdram_bankmachine2_cmd_payload_ras; + rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; end 2'd3: begin - vns_t_array_muxed4 <= soc_sdram_bankmachine3_cmd_payload_ras; + rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; end 3'd4: begin - vns_t_array_muxed4 <= soc_sdram_bankmachine4_cmd_payload_ras; + rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; end 3'd5: begin - vns_t_array_muxed4 <= soc_sdram_bankmachine5_cmd_payload_ras; + rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; end 3'd6: begin - vns_t_array_muxed4 <= soc_sdram_bankmachine6_cmd_payload_ras; + rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; end default: begin - vns_t_array_muxed4 <= soc_sdram_bankmachine7_cmd_payload_ras; + rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; end endcase // synthesis translate_off - dummy_d_354 = dummy_s; + dummy_d_294 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_355; +reg dummy_d_295; // synthesis translate_on always @(*) begin - vns_t_array_muxed5 <= 1'd0; - case (soc_sdram_choose_req_grant) + rhs_array_muxed7 <= 15'd0; + case (litedramcore_choose_req_grant) 1'd0: begin - vns_t_array_muxed5 <= soc_sdram_bankmachine0_cmd_payload_we; + rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - vns_t_array_muxed5 <= soc_sdram_bankmachine1_cmd_payload_we; + rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - vns_t_array_muxed5 <= soc_sdram_bankmachine2_cmd_payload_we; + rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - vns_t_array_muxed5 <= soc_sdram_bankmachine3_cmd_payload_we; + rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - vns_t_array_muxed5 <= soc_sdram_bankmachine4_cmd_payload_we; + rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - vns_t_array_muxed5 <= soc_sdram_bankmachine5_cmd_payload_we; + rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - vns_t_array_muxed5 <= soc_sdram_bankmachine6_cmd_payload_we; + rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; end default: begin - vns_t_array_muxed5 <= soc_sdram_bankmachine7_cmd_payload_we; + rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_355 = dummy_s; + dummy_d_295 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_356; +reg dummy_d_296; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed12 <= 22'd0; - case (vns_roundrobin0_grant) + rhs_array_muxed8 <= 3'd0; + case (litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed12 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]}; + rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; end - default: begin - vns_rhs_array_muxed12 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]}; + 1'd1: begin + rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; end - endcase -// synthesis translate_off - dummy_d_356 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_357; -// synthesis translate_on -always @(*) begin - vns_rhs_array_muxed13 <= 1'd0; - case (vns_roundrobin0_grant) - 1'd0: begin - vns_rhs_array_muxed13 <= soc_port_cmd_payload_we; + 2'd2: begin + rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; end default: begin - vns_rhs_array_muxed13 <= soc_cmd_payload_we; + rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; end endcase // synthesis translate_off - dummy_d_357 = dummy_s; + dummy_d_296 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_358; +reg dummy_d_297; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed14 <= 1'd0; - case (vns_roundrobin0_grant) + rhs_array_muxed9 <= 1'd0; + case (litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed14 <= (((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); + rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - vns_rhs_array_muxed14 <= (((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; end endcase // synthesis translate_off - dummy_d_358 = dummy_s; + dummy_d_297 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_359; +reg dummy_d_298; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed15 <= 22'd0; - case (vns_roundrobin1_grant) + rhs_array_muxed10 <= 1'd0; + case (litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed15 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]}; + rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - vns_rhs_array_muxed15 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]}; + rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; end endcase // synthesis translate_off - dummy_d_359 = dummy_s; + dummy_d_298 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_360; +reg dummy_d_299; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed16 <= 1'd0; - case (vns_roundrobin1_grant) + rhs_array_muxed11 <= 1'd0; + case (litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed16 <= soc_port_cmd_payload_we; + rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - vns_rhs_array_muxed16 <= soc_cmd_payload_we; + rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase // synthesis translate_off - dummy_d_360 = dummy_s; + dummy_d_299 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_361; +reg dummy_d_300; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed17 <= 1'd0; - case (vns_roundrobin1_grant) + t_array_muxed3 <= 1'd0; + case (litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed17 <= (((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); + t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; end default: begin - vns_rhs_array_muxed17 <= (((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; end endcase // synthesis translate_off - dummy_d_361 = dummy_s; + dummy_d_300 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_362; +reg dummy_d_301; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed18 <= 22'd0; - case (vns_roundrobin2_grant) + t_array_muxed4 <= 1'd0; + case (litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed18 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]}; + t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; end default: begin - vns_rhs_array_muxed18 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]}; + t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; end endcase // synthesis translate_off - dummy_d_362 = dummy_s; + dummy_d_301 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_363; +reg dummy_d_302; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed19 <= 1'd0; - case (vns_roundrobin2_grant) + t_array_muxed5 <= 1'd0; + case (litedramcore_choose_req_grant) 1'd0: begin - vns_rhs_array_muxed19 <= soc_port_cmd_payload_we; + t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; end default: begin - vns_rhs_array_muxed19 <= soc_cmd_payload_we; + t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_363 = dummy_s; + dummy_d_302 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_364; +reg dummy_d_303; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed20 <= 1'd0; - case (vns_roundrobin2_grant) - 1'd0: begin - vns_rhs_array_muxed20 <= (((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); - end + rhs_array_muxed12 <= 22'd0; + case (roundrobin0_grant) default: begin - vns_rhs_array_muxed20 <= (((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_364 = dummy_s; + dummy_d_303 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_365; +reg dummy_d_304; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed21 <= 22'd0; - case (vns_roundrobin3_grant) - 1'd0: begin - vns_rhs_array_muxed21 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]}; - end + rhs_array_muxed13 <= 1'd0; + case (roundrobin0_grant) default: begin - vns_rhs_array_muxed21 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]}; + rhs_array_muxed13 <= user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_365 = dummy_s; + dummy_d_304 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_366; +reg dummy_d_305; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed22 <= 1'd0; - case (vns_roundrobin3_grant) - 1'd0: begin - vns_rhs_array_muxed22 <= soc_port_cmd_payload_we; - end + rhs_array_muxed14 <= 1'd0; + case (roundrobin0_grant) default: begin - vns_rhs_array_muxed22 <= soc_cmd_payload_we; + rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_366 = dummy_s; + dummy_d_305 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_367; +reg dummy_d_306; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed23 <= 1'd0; - case (vns_roundrobin3_grant) - 1'd0: begin - vns_rhs_array_muxed23 <= (((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); - end + rhs_array_muxed15 <= 22'd0; + case (roundrobin1_grant) default: begin - vns_rhs_array_muxed23 <= (((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_367 = dummy_s; + dummy_d_306 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_368; +reg dummy_d_307; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed24 <= 22'd0; - case (vns_roundrobin4_grant) - 1'd0: begin - vns_rhs_array_muxed24 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]}; - end + rhs_array_muxed16 <= 1'd0; + case (roundrobin1_grant) default: begin - vns_rhs_array_muxed24 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]}; + rhs_array_muxed16 <= user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_368 = dummy_s; + dummy_d_307 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_369; +reg dummy_d_308; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed25 <= 1'd0; - case (vns_roundrobin4_grant) - 1'd0: begin - vns_rhs_array_muxed25 <= soc_port_cmd_payload_we; - end + rhs_array_muxed17 <= 1'd0; + case (roundrobin1_grant) default: begin - vns_rhs_array_muxed25 <= soc_cmd_payload_we; + rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_369 = dummy_s; + dummy_d_308 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_370; +reg dummy_d_309; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed26 <= 1'd0; - case (vns_roundrobin4_grant) - 1'd0: begin - vns_rhs_array_muxed26 <= (((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); - end + rhs_array_muxed18 <= 22'd0; + case (roundrobin2_grant) default: begin - vns_rhs_array_muxed26 <= (((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_370 = dummy_s; + dummy_d_309 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_371; +reg dummy_d_310; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed27 <= 22'd0; - case (vns_roundrobin5_grant) - 1'd0: begin - vns_rhs_array_muxed27 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]}; - end + rhs_array_muxed19 <= 1'd0; + case (roundrobin2_grant) default: begin - vns_rhs_array_muxed27 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]}; + rhs_array_muxed19 <= user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_371 = dummy_s; + dummy_d_310 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_372; +reg dummy_d_311; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed28 <= 1'd0; - case (vns_roundrobin5_grant) - 1'd0: begin - vns_rhs_array_muxed28 <= soc_port_cmd_payload_we; - end + rhs_array_muxed20 <= 1'd0; + case (roundrobin2_grant) default: begin - vns_rhs_array_muxed28 <= soc_cmd_payload_we; + rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_372 = dummy_s; + dummy_d_311 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_373; +reg dummy_d_312; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed29 <= 1'd0; - case (vns_roundrobin5_grant) - 1'd0: begin - vns_rhs_array_muxed29 <= (((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); - end + rhs_array_muxed21 <= 22'd0; + case (roundrobin3_grant) default: begin - vns_rhs_array_muxed29 <= (((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_373 = dummy_s; + dummy_d_312 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_374; +reg dummy_d_313; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed30 <= 22'd0; - case (vns_roundrobin6_grant) - 1'd0: begin - vns_rhs_array_muxed30 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]}; - end + rhs_array_muxed22 <= 1'd0; + case (roundrobin3_grant) default: begin - vns_rhs_array_muxed30 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]}; + rhs_array_muxed22 <= user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_374 = dummy_s; + dummy_d_313 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_375; +reg dummy_d_314; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed31 <= 1'd0; - case (vns_roundrobin6_grant) - 1'd0: begin - vns_rhs_array_muxed31 <= soc_port_cmd_payload_we; - end + rhs_array_muxed23 <= 1'd0; + case (roundrobin3_grant) default: begin - vns_rhs_array_muxed31 <= soc_cmd_payload_we; + rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_375 = dummy_s; + dummy_d_314 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_376; +reg dummy_d_315; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed32 <= 1'd0; - case (vns_roundrobin6_grant) - 1'd0: begin - vns_rhs_array_muxed32 <= (((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid); - end + rhs_array_muxed24 <= 22'd0; + case (roundrobin4_grant) default: begin - vns_rhs_array_muxed32 <= (((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid); + rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_376 = dummy_s; + dummy_d_315 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_377; +reg dummy_d_316; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed33 <= 22'd0; - case (vns_roundrobin7_grant) - 1'd0: begin - vns_rhs_array_muxed33 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]}; - end + rhs_array_muxed25 <= 1'd0; + case (roundrobin4_grant) default: begin - vns_rhs_array_muxed33 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]}; + rhs_array_muxed25 <= user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_377 = dummy_s; + dummy_d_316 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_378; +reg dummy_d_317; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed34 <= 1'd0; - case (vns_roundrobin7_grant) - 1'd0: begin - vns_rhs_array_muxed34 <= soc_port_cmd_payload_we; - end + rhs_array_muxed26 <= 1'd0; + case (roundrobin4_grant) default: begin - vns_rhs_array_muxed34 <= soc_cmd_payload_we; + rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_378 = dummy_s; + dummy_d_317 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_379; +reg dummy_d_318; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed35 <= 1'd0; - case (vns_roundrobin7_grant) - 1'd0: begin - vns_rhs_array_muxed35 <= (((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_port_cmd_valid); - end + rhs_array_muxed27 <= 22'd0; + case (roundrobin5_grant) default: begin - vns_rhs_array_muxed35 <= (((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))))) & soc_cmd_valid); + rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_379 = dummy_s; + dummy_d_318 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_380; +reg dummy_d_319; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed36 <= 30'd0; - case (vns_grant) - 1'd0: begin - vns_rhs_array_muxed36 <= soc_litedramcore_cpu_ibus_adr; - end + rhs_array_muxed28 <= 1'd0; + case (roundrobin5_grant) default: begin - vns_rhs_array_muxed36 <= soc_litedramcore_cpu_dbus_adr; + rhs_array_muxed28 <= user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_380 = dummy_s; + dummy_d_319 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_381; +reg dummy_d_320; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed37 <= 32'd0; - case (vns_grant) - 1'd0: begin - vns_rhs_array_muxed37 <= soc_litedramcore_cpu_ibus_dat_w; - end + rhs_array_muxed29 <= 1'd0; + case (roundrobin5_grant) default: begin - vns_rhs_array_muxed37 <= soc_litedramcore_cpu_dbus_dat_w; + rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_381 = dummy_s; + dummy_d_320 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_382; +reg dummy_d_321; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed38 <= 4'd0; - case (vns_grant) - 1'd0: begin - vns_rhs_array_muxed38 <= soc_litedramcore_cpu_ibus_sel; - end + rhs_array_muxed30 <= 22'd0; + case (roundrobin6_grant) default: begin - vns_rhs_array_muxed38 <= soc_litedramcore_cpu_dbus_sel; + rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_382 = dummy_s; + dummy_d_321 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_383; +reg dummy_d_322; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed39 <= 1'd0; - case (vns_grant) - 1'd0: begin - vns_rhs_array_muxed39 <= soc_litedramcore_cpu_ibus_cyc; - end + rhs_array_muxed31 <= 1'd0; + case (roundrobin6_grant) default: begin - vns_rhs_array_muxed39 <= soc_litedramcore_cpu_dbus_cyc; + rhs_array_muxed31 <= user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_383 = dummy_s; + dummy_d_322 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_384; +reg dummy_d_323; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed40 <= 1'd0; - case (vns_grant) - 1'd0: begin - vns_rhs_array_muxed40 <= soc_litedramcore_cpu_ibus_stb; - end + rhs_array_muxed32 <= 1'd0; + case (roundrobin6_grant) default: begin - vns_rhs_array_muxed40 <= soc_litedramcore_cpu_dbus_stb; + rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_384 = dummy_s; + dummy_d_323 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_385; +reg dummy_d_324; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed41 <= 1'd0; - case (vns_grant) - 1'd0: begin - vns_rhs_array_muxed41 <= soc_litedramcore_cpu_ibus_we; - end + rhs_array_muxed33 <= 22'd0; + case (roundrobin7_grant) default: begin - vns_rhs_array_muxed41 <= soc_litedramcore_cpu_dbus_we; + rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; end endcase // synthesis translate_off - dummy_d_385 = dummy_s; + dummy_d_324 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_386; +reg dummy_d_325; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed42 <= 3'd0; - case (vns_grant) - 1'd0: begin - vns_rhs_array_muxed42 <= soc_litedramcore_cpu_ibus_cti; - end + rhs_array_muxed34 <= 1'd0; + case (roundrobin7_grant) default: begin - vns_rhs_array_muxed42 <= soc_litedramcore_cpu_dbus_cti; + rhs_array_muxed34 <= user_port_cmd_payload_we; end endcase // synthesis translate_off - dummy_d_386 = dummy_s; + dummy_d_325 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_387; +reg dummy_d_326; // synthesis translate_on always @(*) begin - vns_rhs_array_muxed43 <= 2'd0; - case (vns_grant) - 1'd0: begin - vns_rhs_array_muxed43 <= soc_litedramcore_cpu_ibus_bte; - end + rhs_array_muxed35 <= 1'd0; + case (roundrobin7_grant) default: begin - vns_rhs_array_muxed43 <= soc_litedramcore_cpu_dbus_bte; + rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); end endcase // synthesis translate_off - dummy_d_387 = dummy_s; + dummy_d_326 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_388; +reg dummy_d_327; // synthesis translate_on always @(*) begin - vns_array_muxed0 <= 3'd0; - case (soc_sdram_steerer_sel0) + array_muxed0 <= 3'd0; + case (litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed0 <= soc_sdram_nop_ba[2:0]; + array_muxed0 <= litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed0 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0]; + array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed0 <= soc_sdram_choose_req_cmd_payload_ba[2:0]; + array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed0 <= soc_sdram_cmd_payload_ba[2:0]; + array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_388 = dummy_s; + dummy_d_327 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_389; +reg dummy_d_328; // synthesis translate_on always @(*) begin - vns_array_muxed1 <= 15'd0; - case (soc_sdram_steerer_sel0) + array_muxed1 <= 15'd0; + case (litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed1 <= soc_sdram_nop_a; + array_muxed1 <= litedramcore_nop_a; end 1'd1: begin - vns_array_muxed1 <= soc_sdram_choose_cmd_cmd_payload_a; + array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed1 <= soc_sdram_choose_req_cmd_payload_a; + array_muxed1 <= litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed1 <= soc_sdram_cmd_payload_a; + array_muxed1 <= litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_389 = dummy_s; + dummy_d_328 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_390; +reg dummy_d_329; // synthesis translate_on always @(*) begin - vns_array_muxed2 <= 1'd0; - case (soc_sdram_steerer_sel0) + array_muxed2 <= 1'd0; + case (litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed2 <= 1'd0; + array_muxed2 <= 1'd0; end 1'd1: begin - vns_array_muxed2 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas); + array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed2 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas); + array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed2 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas); + array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_390 = dummy_s; + dummy_d_329 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_391; +reg dummy_d_330; // synthesis translate_on always @(*) begin - vns_array_muxed3 <= 1'd0; - case (soc_sdram_steerer_sel0) + array_muxed3 <= 1'd0; + case (litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed3 <= 1'd0; + array_muxed3 <= 1'd0; end 1'd1: begin - vns_array_muxed3 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras); + array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed3 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras); + array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed3 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras); + array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_391 = dummy_s; + dummy_d_330 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_392; +reg dummy_d_331; // synthesis translate_on always @(*) begin - vns_array_muxed4 <= 1'd0; - case (soc_sdram_steerer_sel0) + array_muxed4 <= 1'd0; + case (litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed4 <= 1'd0; + array_muxed4 <= 1'd0; end 1'd1: begin - vns_array_muxed4 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we); + array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed4 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we); + array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed4 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we); + array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_392 = dummy_s; + dummy_d_331 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_393; +reg dummy_d_332; // synthesis translate_on always @(*) begin - vns_array_muxed5 <= 1'd0; - case (soc_sdram_steerer_sel0) + array_muxed5 <= 1'd0; + case (litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed5 <= 1'd0; + array_muxed5 <= 1'd0; end 1'd1: begin - vns_array_muxed5 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read); + array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed5 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read); + array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed5 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read); + array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_393 = dummy_s; + dummy_d_332 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_394; +reg dummy_d_333; // synthesis translate_on always @(*) begin - vns_array_muxed6 <= 1'd0; - case (soc_sdram_steerer_sel0) + array_muxed6 <= 1'd0; + case (litedramcore_steerer_sel0) 1'd0: begin - vns_array_muxed6 <= 1'd0; + array_muxed6 <= 1'd0; end 1'd1: begin - vns_array_muxed6 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write); + array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed6 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write); + array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed6 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write); + array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_394 = dummy_s; + dummy_d_333 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_395; +reg dummy_d_334; // synthesis translate_on always @(*) begin - vns_array_muxed7 <= 3'd0; - case (soc_sdram_steerer_sel1) + array_muxed7 <= 3'd0; + case (litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed7 <= soc_sdram_nop_ba[2:0]; + array_muxed7 <= litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed7 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0]; + array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed7 <= soc_sdram_choose_req_cmd_payload_ba[2:0]; + array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed7 <= soc_sdram_cmd_payload_ba[2:0]; + array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_395 = dummy_s; + dummy_d_334 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_396; +reg dummy_d_335; // synthesis translate_on always @(*) begin - vns_array_muxed8 <= 15'd0; - case (soc_sdram_steerer_sel1) + array_muxed8 <= 15'd0; + case (litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed8 <= soc_sdram_nop_a; + array_muxed8 <= litedramcore_nop_a; end 1'd1: begin - vns_array_muxed8 <= soc_sdram_choose_cmd_cmd_payload_a; + array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed8 <= soc_sdram_choose_req_cmd_payload_a; + array_muxed8 <= litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed8 <= soc_sdram_cmd_payload_a; + array_muxed8 <= litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_396 = dummy_s; + dummy_d_335 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_397; +reg dummy_d_336; // synthesis translate_on always @(*) begin - vns_array_muxed9 <= 1'd0; - case (soc_sdram_steerer_sel1) + array_muxed9 <= 1'd0; + case (litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed9 <= 1'd0; + array_muxed9 <= 1'd0; end 1'd1: begin - vns_array_muxed9 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas); + array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed9 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas); + array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed9 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas); + array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_397 = dummy_s; + dummy_d_336 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_398; +reg dummy_d_337; // synthesis translate_on always @(*) begin - vns_array_muxed10 <= 1'd0; - case (soc_sdram_steerer_sel1) + array_muxed10 <= 1'd0; + case (litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed10 <= 1'd0; + array_muxed10 <= 1'd0; end 1'd1: begin - vns_array_muxed10 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras); + array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed10 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras); + array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed10 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras); + array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_398 = dummy_s; + dummy_d_337 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_399; +reg dummy_d_338; // synthesis translate_on always @(*) begin - vns_array_muxed11 <= 1'd0; - case (soc_sdram_steerer_sel1) + array_muxed11 <= 1'd0; + case (litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed11 <= 1'd0; + array_muxed11 <= 1'd0; end 1'd1: begin - vns_array_muxed11 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we); + array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed11 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we); + array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed11 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we); + array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_399 = dummy_s; + dummy_d_338 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_400; +reg dummy_d_339; // synthesis translate_on always @(*) begin - vns_array_muxed12 <= 1'd0; - case (soc_sdram_steerer_sel1) + array_muxed12 <= 1'd0; + case (litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed12 <= 1'd0; + array_muxed12 <= 1'd0; end 1'd1: begin - vns_array_muxed12 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read); + array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed12 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read); + array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed12 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read); + array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_400 = dummy_s; + dummy_d_339 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_401; +reg dummy_d_340; // synthesis translate_on always @(*) begin - vns_array_muxed13 <= 1'd0; - case (soc_sdram_steerer_sel1) + array_muxed13 <= 1'd0; + case (litedramcore_steerer_sel1) 1'd0: begin - vns_array_muxed13 <= 1'd0; + array_muxed13 <= 1'd0; end 1'd1: begin - vns_array_muxed13 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write); + array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed13 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write); + array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed13 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write); + array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_401 = dummy_s; + dummy_d_340 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_402; +reg dummy_d_341; // synthesis translate_on always @(*) begin - vns_array_muxed14 <= 3'd0; - case (soc_sdram_steerer_sel2) + array_muxed14 <= 3'd0; + case (litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed14 <= soc_sdram_nop_ba[2:0]; + array_muxed14 <= litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed14 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0]; + array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed14 <= soc_sdram_choose_req_cmd_payload_ba[2:0]; + array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed14 <= soc_sdram_cmd_payload_ba[2:0]; + array_muxed14 <= litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_402 = dummy_s; + dummy_d_341 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_403; +reg dummy_d_342; // synthesis translate_on always @(*) begin - vns_array_muxed15 <= 15'd0; - case (soc_sdram_steerer_sel2) + array_muxed15 <= 15'd0; + case (litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed15 <= soc_sdram_nop_a; + array_muxed15 <= litedramcore_nop_a; end 1'd1: begin - vns_array_muxed15 <= soc_sdram_choose_cmd_cmd_payload_a; + array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed15 <= soc_sdram_choose_req_cmd_payload_a; + array_muxed15 <= litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed15 <= soc_sdram_cmd_payload_a; + array_muxed15 <= litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_403 = dummy_s; + dummy_d_342 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_404; +reg dummy_d_343; // synthesis translate_on always @(*) begin - vns_array_muxed16 <= 1'd0; - case (soc_sdram_steerer_sel2) + array_muxed16 <= 1'd0; + case (litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed16 <= 1'd0; + array_muxed16 <= 1'd0; end 1'd1: begin - vns_array_muxed16 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas); + array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed16 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas); + array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed16 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas); + array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_404 = dummy_s; + dummy_d_343 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_405; +reg dummy_d_344; // synthesis translate_on always @(*) begin - vns_array_muxed17 <= 1'd0; - case (soc_sdram_steerer_sel2) + array_muxed17 <= 1'd0; + case (litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed17 <= 1'd0; + array_muxed17 <= 1'd0; end 1'd1: begin - vns_array_muxed17 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras); + array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed17 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras); + array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed17 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras); + array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_405 = dummy_s; + dummy_d_344 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_406; +reg dummy_d_345; // synthesis translate_on always @(*) begin - vns_array_muxed18 <= 1'd0; - case (soc_sdram_steerer_sel2) + array_muxed18 <= 1'd0; + case (litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed18 <= 1'd0; + array_muxed18 <= 1'd0; end 1'd1: begin - vns_array_muxed18 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we); + array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed18 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we); + array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed18 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we); + array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_406 = dummy_s; + dummy_d_345 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_407; +reg dummy_d_346; // synthesis translate_on always @(*) begin - vns_array_muxed19 <= 1'd0; - case (soc_sdram_steerer_sel2) + array_muxed19 <= 1'd0; + case (litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed19 <= 1'd0; + array_muxed19 <= 1'd0; end 1'd1: begin - vns_array_muxed19 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read); + array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed19 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read); + array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed19 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read); + array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_407 = dummy_s; + dummy_d_346 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_408; +reg dummy_d_347; // synthesis translate_on always @(*) begin - vns_array_muxed20 <= 1'd0; - case (soc_sdram_steerer_sel2) + array_muxed20 <= 1'd0; + case (litedramcore_steerer_sel2) 1'd0: begin - vns_array_muxed20 <= 1'd0; + array_muxed20 <= 1'd0; end 1'd1: begin - vns_array_muxed20 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write); + array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed20 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write); + array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed20 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write); + array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_408 = dummy_s; + dummy_d_347 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_409; +reg dummy_d_348; // synthesis translate_on always @(*) begin - vns_array_muxed21 <= 3'd0; - case (soc_sdram_steerer_sel3) + array_muxed21 <= 3'd0; + case (litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed21 <= soc_sdram_nop_ba[2:0]; + array_muxed21 <= litedramcore_nop_ba[2:0]; end 1'd1: begin - vns_array_muxed21 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0]; + array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - vns_array_muxed21 <= soc_sdram_choose_req_cmd_payload_ba[2:0]; + array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - vns_array_muxed21 <= soc_sdram_cmd_payload_ba[2:0]; + array_muxed21 <= litedramcore_cmd_payload_ba[2:0]; end endcase // synthesis translate_off - dummy_d_409 = dummy_s; + dummy_d_348 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_410; +reg dummy_d_349; // synthesis translate_on always @(*) begin - vns_array_muxed22 <= 15'd0; - case (soc_sdram_steerer_sel3) + array_muxed22 <= 15'd0; + case (litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed22 <= soc_sdram_nop_a; + array_muxed22 <= litedramcore_nop_a; end 1'd1: begin - vns_array_muxed22 <= soc_sdram_choose_cmd_cmd_payload_a; + array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - vns_array_muxed22 <= soc_sdram_choose_req_cmd_payload_a; + array_muxed22 <= litedramcore_choose_req_cmd_payload_a; end default: begin - vns_array_muxed22 <= soc_sdram_cmd_payload_a; + array_muxed22 <= litedramcore_cmd_payload_a; end endcase // synthesis translate_off - dummy_d_410 = dummy_s; + dummy_d_349 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_411; +reg dummy_d_350; // synthesis translate_on always @(*) begin - vns_array_muxed23 <= 1'd0; - case (soc_sdram_steerer_sel3) + array_muxed23 <= 1'd0; + case (litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed23 <= 1'd0; + array_muxed23 <= 1'd0; end 1'd1: begin - vns_array_muxed23 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas); + array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - vns_array_muxed23 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas); + array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); end default: begin - vns_array_muxed23 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas); + array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); end endcase // synthesis translate_off - dummy_d_411 = dummy_s; + dummy_d_350 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_412; +reg dummy_d_351; // synthesis translate_on always @(*) begin - vns_array_muxed24 <= 1'd0; - case (soc_sdram_steerer_sel3) + array_muxed24 <= 1'd0; + case (litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed24 <= 1'd0; + array_muxed24 <= 1'd0; end 1'd1: begin - vns_array_muxed24 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras); + array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - vns_array_muxed24 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras); + array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); end default: begin - vns_array_muxed24 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras); + array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); end endcase // synthesis translate_off - dummy_d_412 = dummy_s; + dummy_d_351 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_413; +reg dummy_d_352; // synthesis translate_on always @(*) begin - vns_array_muxed25 <= 1'd0; - case (soc_sdram_steerer_sel3) + array_muxed25 <= 1'd0; + case (litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed25 <= 1'd0; + array_muxed25 <= 1'd0; end 1'd1: begin - vns_array_muxed25 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we); + array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - vns_array_muxed25 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we); + array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); end default: begin - vns_array_muxed25 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we); + array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); end endcase // synthesis translate_off - dummy_d_413 = dummy_s; + dummy_d_352 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_414; +reg dummy_d_353; // synthesis translate_on always @(*) begin - vns_array_muxed26 <= 1'd0; - case (soc_sdram_steerer_sel3) + array_muxed26 <= 1'd0; + case (litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed26 <= 1'd0; + array_muxed26 <= 1'd0; end 1'd1: begin - vns_array_muxed26 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read); + array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - vns_array_muxed26 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read); + array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); end default: begin - vns_array_muxed26 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read); + array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); end endcase // synthesis translate_off - dummy_d_414 = dummy_s; + dummy_d_353 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_415; +reg dummy_d_354; // synthesis translate_on always @(*) begin - vns_array_muxed27 <= 1'd0; - case (soc_sdram_steerer_sel3) + array_muxed27 <= 1'd0; + case (litedramcore_steerer_sel3) 1'd0: begin - vns_array_muxed27 <= 1'd0; + array_muxed27 <= 1'd0; end 1'd1: begin - vns_array_muxed27 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write); + array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - vns_array_muxed27 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write); + array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); end default: begin - vns_array_muxed27 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write); + array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); end endcase // synthesis translate_off - dummy_d_415 = dummy_s; -// synthesis translate_on -end -assign soc_litedramcore_rx = vns_regs1; -assign vns_xilinxasyncresetsynchronizerimpl0 = ((~soc_sys_pll_locked) | soc_sys_pll_reset); -assign vns_xilinxasyncresetsynchronizerimpl1 = ((~soc_sys_pll_locked) | soc_sys_pll_reset); -assign vns_xilinxasyncresetsynchronizerimpl2 = ((~soc_sys_pll_locked) | soc_sys_pll_reset); -assign vns_xilinxasyncresetsynchronizerimpl3 = ((~soc_iodelay_pll_locked) | soc_iodelay_pll_reset); - -always @(posedge iodelay_clk) begin - if ((soc_reset_counter != 1'd0)) begin - soc_reset_counter <= (soc_reset_counter - 1'd1); - end else begin - soc_ic_reset <= 1'd0; - end - if (iodelay_rst) begin - soc_reset_counter <= 4'd15; - soc_ic_reset <= 1'd1; - end -end - -always @(posedge sys_clk) begin - if ((soc_litedramcore_soccontroller_bus_errors != 32'd4294967295)) begin - if (soc_litedramcore_soccontroller_bus_error) begin - soc_litedramcore_soccontroller_bus_errors <= (soc_litedramcore_soccontroller_bus_errors + 1'd1); - end - end - soc_litedramcore_litedramcore_ram_bus_ack <= 1'd0; - if (((soc_litedramcore_litedramcore_ram_bus_cyc & soc_litedramcore_litedramcore_ram_bus_stb) & (~soc_litedramcore_litedramcore_ram_bus_ack))) begin - soc_litedramcore_litedramcore_ram_bus_ack <= 1'd1; - end - soc_litedramcore_ram_bus_ram_bus_ack <= 1'd0; - if (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & (~soc_litedramcore_ram_bus_ram_bus_ack))) begin - soc_litedramcore_ram_bus_ram_bus_ack <= 1'd1; - end - soc_litedramcore_sink_ready <= 1'd0; - if (((soc_litedramcore_sink_valid & (~soc_litedramcore_tx_busy)) & (~soc_litedramcore_sink_ready))) begin - soc_litedramcore_tx_reg <= soc_litedramcore_sink_payload_data; - soc_litedramcore_tx_bitcount <= 1'd0; - soc_litedramcore_tx_busy <= 1'd1; - serial_tx <= 1'd0; - end else begin - if ((soc_litedramcore_uart_clk_txen & soc_litedramcore_tx_busy)) begin - soc_litedramcore_tx_bitcount <= (soc_litedramcore_tx_bitcount + 1'd1); - if ((soc_litedramcore_tx_bitcount == 4'd8)) begin - serial_tx <= 1'd1; - end else begin - if ((soc_litedramcore_tx_bitcount == 4'd9)) begin - serial_tx <= 1'd1; - soc_litedramcore_tx_busy <= 1'd0; - soc_litedramcore_sink_ready <= 1'd1; - end else begin - serial_tx <= soc_litedramcore_tx_reg[0]; - soc_litedramcore_tx_reg <= {1'd0, soc_litedramcore_tx_reg[7:1]}; - end - end - end - end - if (soc_litedramcore_tx_busy) begin - {soc_litedramcore_uart_clk_txen, soc_litedramcore_phase_accumulator_tx} <= (soc_litedramcore_phase_accumulator_tx + soc_litedramcore_storage); - end else begin - {soc_litedramcore_uart_clk_txen, soc_litedramcore_phase_accumulator_tx} <= 1'd0; - end - soc_litedramcore_source_valid <= 1'd0; - soc_litedramcore_rx_r <= soc_litedramcore_rx; - if ((~soc_litedramcore_rx_busy)) begin - if (((~soc_litedramcore_rx) & soc_litedramcore_rx_r)) begin - soc_litedramcore_rx_busy <= 1'd1; - soc_litedramcore_rx_bitcount <= 1'd0; - end - end else begin - if (soc_litedramcore_uart_clk_rxen) begin - soc_litedramcore_rx_bitcount <= (soc_litedramcore_rx_bitcount + 1'd1); - if ((soc_litedramcore_rx_bitcount == 1'd0)) begin - if (soc_litedramcore_rx) begin - soc_litedramcore_rx_busy <= 1'd0; - end - end else begin - if ((soc_litedramcore_rx_bitcount == 4'd9)) begin - soc_litedramcore_rx_busy <= 1'd0; - if (soc_litedramcore_rx) begin - soc_litedramcore_source_payload_data <= soc_litedramcore_rx_reg; - soc_litedramcore_source_valid <= 1'd1; - end - end else begin - soc_litedramcore_rx_reg <= {soc_litedramcore_rx, soc_litedramcore_rx_reg[7:1]}; - end - end - end - end - if (soc_litedramcore_rx_busy) begin - {soc_litedramcore_uart_clk_rxen, soc_litedramcore_phase_accumulator_rx} <= (soc_litedramcore_phase_accumulator_rx + soc_litedramcore_storage); - end else begin - {soc_litedramcore_uart_clk_rxen, soc_litedramcore_phase_accumulator_rx} <= 32'd2147483648; - end - if (soc_litedramcore_uart_tx_clear) begin - soc_litedramcore_uart_tx_pending <= 1'd0; - end - soc_litedramcore_uart_tx_old_trigger <= soc_litedramcore_uart_tx_trigger; - if (((~soc_litedramcore_uart_tx_trigger) & soc_litedramcore_uart_tx_old_trigger)) begin - soc_litedramcore_uart_tx_pending <= 1'd1; - end - if (soc_litedramcore_uart_rx_clear) begin - soc_litedramcore_uart_rx_pending <= 1'd0; - end - soc_litedramcore_uart_rx_old_trigger <= soc_litedramcore_uart_rx_trigger; - if (((~soc_litedramcore_uart_rx_trigger) & soc_litedramcore_uart_rx_old_trigger)) begin - soc_litedramcore_uart_rx_pending <= 1'd1; - end - if (soc_litedramcore_uart_tx_fifo_syncfifo_re) begin - soc_litedramcore_uart_tx_fifo_readable <= 1'd1; - end else begin - if (soc_litedramcore_uart_tx_fifo_re) begin - soc_litedramcore_uart_tx_fifo_readable <= 1'd0; - end - end - if (((soc_litedramcore_uart_tx_fifo_syncfifo_we & soc_litedramcore_uart_tx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_tx_fifo_replace))) begin - soc_litedramcore_uart_tx_fifo_produce <= (soc_litedramcore_uart_tx_fifo_produce + 1'd1); - end - if (soc_litedramcore_uart_tx_fifo_do_read) begin - soc_litedramcore_uart_tx_fifo_consume <= (soc_litedramcore_uart_tx_fifo_consume + 1'd1); - end - if (((soc_litedramcore_uart_tx_fifo_syncfifo_we & soc_litedramcore_uart_tx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_tx_fifo_replace))) begin - if ((~soc_litedramcore_uart_tx_fifo_do_read)) begin - soc_litedramcore_uart_tx_fifo_level0 <= (soc_litedramcore_uart_tx_fifo_level0 + 1'd1); - end - end else begin - if (soc_litedramcore_uart_tx_fifo_do_read) begin - soc_litedramcore_uart_tx_fifo_level0 <= (soc_litedramcore_uart_tx_fifo_level0 - 1'd1); - end - end - if (soc_litedramcore_uart_rx_fifo_syncfifo_re) begin - soc_litedramcore_uart_rx_fifo_readable <= 1'd1; - end else begin - if (soc_litedramcore_uart_rx_fifo_re) begin - soc_litedramcore_uart_rx_fifo_readable <= 1'd0; - end - end - if (((soc_litedramcore_uart_rx_fifo_syncfifo_we & soc_litedramcore_uart_rx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_rx_fifo_replace))) begin - soc_litedramcore_uart_rx_fifo_produce <= (soc_litedramcore_uart_rx_fifo_produce + 1'd1); - end - if (soc_litedramcore_uart_rx_fifo_do_read) begin - soc_litedramcore_uart_rx_fifo_consume <= (soc_litedramcore_uart_rx_fifo_consume + 1'd1); - end - if (((soc_litedramcore_uart_rx_fifo_syncfifo_we & soc_litedramcore_uart_rx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_rx_fifo_replace))) begin - if ((~soc_litedramcore_uart_rx_fifo_do_read)) begin - soc_litedramcore_uart_rx_fifo_level0 <= (soc_litedramcore_uart_rx_fifo_level0 + 1'd1); - end - end else begin - if (soc_litedramcore_uart_rx_fifo_do_read) begin - soc_litedramcore_uart_rx_fifo_level0 <= (soc_litedramcore_uart_rx_fifo_level0 - 1'd1); - end - end - if (soc_litedramcore_uart_reset) begin - soc_litedramcore_uart_tx_pending <= 1'd0; - soc_litedramcore_uart_tx_old_trigger <= 1'd0; - soc_litedramcore_uart_rx_pending <= 1'd0; - soc_litedramcore_uart_rx_old_trigger <= 1'd0; - soc_litedramcore_uart_tx_fifo_readable <= 1'd0; - soc_litedramcore_uart_tx_fifo_level0 <= 5'd0; - soc_litedramcore_uart_tx_fifo_produce <= 4'd0; - soc_litedramcore_uart_tx_fifo_consume <= 4'd0; - soc_litedramcore_uart_rx_fifo_readable <= 1'd0; - soc_litedramcore_uart_rx_fifo_level0 <= 5'd0; - soc_litedramcore_uart_rx_fifo_produce <= 4'd0; - soc_litedramcore_uart_rx_fifo_consume <= 4'd0; - end - if (soc_litedramcore_timer_en_storage) begin - if ((soc_litedramcore_timer_value == 1'd0)) begin - soc_litedramcore_timer_value <= soc_litedramcore_timer_reload_storage; - end else begin - soc_litedramcore_timer_value <= (soc_litedramcore_timer_value - 1'd1); - end + dummy_d_354 = dummy_s; +// synthesis translate_on +end +assign xilinxasyncresetsynchronizerimpl0 = ((~sys_pll_locked) | sys_pll_reset); +assign xilinxasyncresetsynchronizerimpl1 = ((~sys_pll_locked) | sys_pll_reset); +assign xilinxasyncresetsynchronizerimpl2 = ((~sys_pll_locked) | sys_pll_reset); +assign xilinxasyncresetsynchronizerimpl3 = ((~iodelay_pll_locked) | iodelay_pll_reset); + +always @(posedge iodelay_clk) begin + if ((reset_counter != 1'd0)) begin + reset_counter <= (reset_counter - 1'd1); end else begin - soc_litedramcore_timer_value <= soc_litedramcore_timer_load_storage; - end - if (soc_litedramcore_timer_update_value_re) begin - soc_litedramcore_timer_value_status <= soc_litedramcore_timer_value; + ic_reset <= 1'd0; end - if (soc_litedramcore_timer_zero_clear) begin - soc_litedramcore_timer_zero_pending <= 1'd0; - end - soc_litedramcore_timer_zero_old_trigger <= soc_litedramcore_timer_zero_trigger; - if (((~soc_litedramcore_timer_zero_trigger) & soc_litedramcore_timer_zero_old_trigger)) begin - soc_litedramcore_timer_zero_pending <= 1'd1; + if (iodelay_rst) begin + reset_counter <= 4'd15; + ic_reset <= 1'd1; end - vns_wb2csr_state <= vns_wb2csr_next_state; - soc_a7ddrphy_dqs_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dqs_oe) | soc_a7ddrphy_dqspattern1); - soc_a7ddrphy_dq_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dq_oe) | soc_a7ddrphy_dqspattern1); - soc_a7ddrphy_rddata_en_last <= soc_a7ddrphy_rddata_en; - soc_a7ddrphy_dfi_p0_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); - soc_a7ddrphy_dfi_p1_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); - soc_a7ddrphy_dfi_p2_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); - soc_a7ddrphy_dfi_p3_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage); - soc_a7ddrphy_wrdata_en_last <= soc_a7ddrphy_wrdata_en; - soc_a7ddrphy_dqspattern_o1 <= soc_a7ddrphy_dqspattern_o0; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip0_value <= (soc_a7ddrphy_bitslip0_value + 1'd1); +end + +always @(posedge sys_clk) begin + a7ddrphy_dqs_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dqs_oe) | a7ddrphy_dqspattern1); + a7ddrphy_dq_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dq_oe) | a7ddrphy_dqspattern1); + a7ddrphy_rddata_en_last <= a7ddrphy_rddata_en; + a7ddrphy_dfi_p0_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage); + a7ddrphy_dfi_p1_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage); + a7ddrphy_dfi_p2_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage); + a7ddrphy_dfi_p3_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage); + a7ddrphy_wrdata_en_last <= a7ddrphy_wrdata_en; + a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value <= (a7ddrphy_bitslip0_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip0_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip0_value <= 1'd0; end - soc_a7ddrphy_bitslip0_r <= {soc_a7ddrphy_bitslip0_i, soc_a7ddrphy_bitslip0_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip1_value <= (soc_a7ddrphy_bitslip1_value + 1'd1); + a7ddrphy_bitslip0_r <= {a7ddrphy_bitslip0_i, a7ddrphy_bitslip0_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value <= (a7ddrphy_bitslip1_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip1_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip1_value <= 1'd0; end - soc_a7ddrphy_bitslip1_r <= {soc_a7ddrphy_bitslip1_i, soc_a7ddrphy_bitslip1_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip2_value <= (soc_a7ddrphy_bitslip2_value + 1'd1); + a7ddrphy_bitslip1_r <= {a7ddrphy_bitslip1_i, a7ddrphy_bitslip1_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip2_value <= (a7ddrphy_bitslip2_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip2_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip2_value <= 1'd0; end - soc_a7ddrphy_bitslip2_r <= {soc_a7ddrphy_bitslip2_i, soc_a7ddrphy_bitslip2_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip3_value <= (soc_a7ddrphy_bitslip3_value + 1'd1); + a7ddrphy_bitslip2_r <= {a7ddrphy_bitslip2_i, a7ddrphy_bitslip2_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip3_value <= (a7ddrphy_bitslip3_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip3_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip3_value <= 1'd0; end - soc_a7ddrphy_bitslip3_r <= {soc_a7ddrphy_bitslip3_i, soc_a7ddrphy_bitslip3_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip4_value <= (soc_a7ddrphy_bitslip4_value + 1'd1); + a7ddrphy_bitslip3_r <= {a7ddrphy_bitslip3_i, a7ddrphy_bitslip3_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip4_value <= (a7ddrphy_bitslip4_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip4_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip4_value <= 1'd0; end - soc_a7ddrphy_bitslip4_r <= {soc_a7ddrphy_bitslip4_i, soc_a7ddrphy_bitslip4_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip5_value <= (soc_a7ddrphy_bitslip5_value + 1'd1); + a7ddrphy_bitslip4_r <= {a7ddrphy_bitslip4_i, a7ddrphy_bitslip4_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip5_value <= (a7ddrphy_bitslip5_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip5_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip5_value <= 1'd0; end - soc_a7ddrphy_bitslip5_r <= {soc_a7ddrphy_bitslip5_i, soc_a7ddrphy_bitslip5_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip6_value <= (soc_a7ddrphy_bitslip6_value + 1'd1); + a7ddrphy_bitslip5_r <= {a7ddrphy_bitslip5_i, a7ddrphy_bitslip5_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip6_value <= (a7ddrphy_bitslip6_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip6_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip6_value <= 1'd0; end - soc_a7ddrphy_bitslip6_r <= {soc_a7ddrphy_bitslip6_i, soc_a7ddrphy_bitslip6_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip7_value <= (soc_a7ddrphy_bitslip7_value + 1'd1); + a7ddrphy_bitslip6_r <= {a7ddrphy_bitslip6_i, a7ddrphy_bitslip6_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip7_value <= (a7ddrphy_bitslip7_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip7_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip7_value <= 1'd0; end - soc_a7ddrphy_bitslip7_r <= {soc_a7ddrphy_bitslip7_i, soc_a7ddrphy_bitslip7_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip8_value <= (soc_a7ddrphy_bitslip8_value + 1'd1); + a7ddrphy_bitslip7_r <= {a7ddrphy_bitslip7_i, a7ddrphy_bitslip7_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip8_value <= (a7ddrphy_bitslip8_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip8_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip8_value <= 1'd0; end - soc_a7ddrphy_bitslip8_r <= {soc_a7ddrphy_bitslip8_i, soc_a7ddrphy_bitslip8_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip9_value <= (soc_a7ddrphy_bitslip9_value + 1'd1); + a7ddrphy_bitslip8_r <= {a7ddrphy_bitslip8_i, a7ddrphy_bitslip8_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip9_value <= (a7ddrphy_bitslip9_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip9_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip9_value <= 1'd0; end - soc_a7ddrphy_bitslip9_r <= {soc_a7ddrphy_bitslip9_i, soc_a7ddrphy_bitslip9_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip10_value <= (soc_a7ddrphy_bitslip10_value + 1'd1); + a7ddrphy_bitslip9_r <= {a7ddrphy_bitslip9_i, a7ddrphy_bitslip9_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip10_value <= (a7ddrphy_bitslip10_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip10_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip10_value <= 1'd0; end - soc_a7ddrphy_bitslip10_r <= {soc_a7ddrphy_bitslip10_i, soc_a7ddrphy_bitslip10_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip11_value <= (soc_a7ddrphy_bitslip11_value + 1'd1); + a7ddrphy_bitslip10_r <= {a7ddrphy_bitslip10_i, a7ddrphy_bitslip10_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip11_value <= (a7ddrphy_bitslip11_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip11_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip11_value <= 1'd0; end - soc_a7ddrphy_bitslip11_r <= {soc_a7ddrphy_bitslip11_i, soc_a7ddrphy_bitslip11_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip12_value <= (soc_a7ddrphy_bitslip12_value + 1'd1); + a7ddrphy_bitslip11_r <= {a7ddrphy_bitslip11_i, a7ddrphy_bitslip11_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip12_value <= (a7ddrphy_bitslip12_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip12_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip12_value <= 1'd0; end - soc_a7ddrphy_bitslip12_r <= {soc_a7ddrphy_bitslip12_i, soc_a7ddrphy_bitslip12_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip13_value <= (soc_a7ddrphy_bitslip13_value + 1'd1); + a7ddrphy_bitslip12_r <= {a7ddrphy_bitslip12_i, a7ddrphy_bitslip12_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip13_value <= (a7ddrphy_bitslip13_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip13_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip13_value <= 1'd0; end - soc_a7ddrphy_bitslip13_r <= {soc_a7ddrphy_bitslip13_i, soc_a7ddrphy_bitslip13_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip14_value <= (soc_a7ddrphy_bitslip14_value + 1'd1); + a7ddrphy_bitslip13_r <= {a7ddrphy_bitslip13_i, a7ddrphy_bitslip13_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip14_value <= (a7ddrphy_bitslip14_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip14_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip14_value <= 1'd0; end - soc_a7ddrphy_bitslip14_r <= {soc_a7ddrphy_bitslip14_i, soc_a7ddrphy_bitslip14_r[15:8]}; - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin - soc_a7ddrphy_bitslip15_value <= (soc_a7ddrphy_bitslip15_value + 1'd1); + a7ddrphy_bitslip14_r <= {a7ddrphy_bitslip14_i, a7ddrphy_bitslip14_r[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip15_value <= (a7ddrphy_bitslip15_value + 1'd1); end - if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin - soc_a7ddrphy_bitslip15_value <= 1'd0; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin + a7ddrphy_bitslip15_value <= 1'd0; end - soc_a7ddrphy_bitslip15_r <= {soc_a7ddrphy_bitslip15_i, soc_a7ddrphy_bitslip15_r[15:8]}; - if (soc_sdram_inti_p0_rddata_valid) begin - soc_sdram_phaseinjector0_status <= soc_sdram_inti_p0_rddata; + a7ddrphy_bitslip15_r <= {a7ddrphy_bitslip15_i, a7ddrphy_bitslip15_r[15:8]}; + if (litedramcore_inti_p0_rddata_valid) begin + litedramcore_phaseinjector0_status <= litedramcore_inti_p0_rddata; end - if (soc_sdram_inti_p1_rddata_valid) begin - soc_sdram_phaseinjector1_status <= soc_sdram_inti_p1_rddata; + if (litedramcore_inti_p1_rddata_valid) begin + litedramcore_phaseinjector1_status <= litedramcore_inti_p1_rddata; end - if (soc_sdram_inti_p2_rddata_valid) begin - soc_sdram_phaseinjector2_status <= soc_sdram_inti_p2_rddata; + if (litedramcore_inti_p2_rddata_valid) begin + litedramcore_phaseinjector2_status <= litedramcore_inti_p2_rddata; end - if (soc_sdram_inti_p3_rddata_valid) begin - soc_sdram_phaseinjector3_status <= soc_sdram_inti_p3_rddata; + if (litedramcore_inti_p3_rddata_valid) begin + litedramcore_phaseinjector3_status <= litedramcore_inti_p3_rddata; end - if ((soc_sdram_timer_wait & (~soc_sdram_timer_done0))) begin - soc_sdram_timer_count1 <= (soc_sdram_timer_count1 - 1'd1); + if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin + litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); end else begin - soc_sdram_timer_count1 <= 10'd781; + litedramcore_timer_count1 <= 10'd781; end - soc_sdram_postponer_req_o <= 1'd0; - if (soc_sdram_postponer_req_i) begin - soc_sdram_postponer_count <= (soc_sdram_postponer_count - 1'd1); - if ((soc_sdram_postponer_count == 1'd0)) begin - soc_sdram_postponer_count <= 1'd0; - soc_sdram_postponer_req_o <= 1'd1; + litedramcore_postponer_req_o <= 1'd0; + if (litedramcore_postponer_req_i) begin + litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); + if ((litedramcore_postponer_count == 1'd0)) begin + litedramcore_postponer_count <= 1'd0; + litedramcore_postponer_req_o <= 1'd1; end end - if (soc_sdram_sequencer_start0) begin - soc_sdram_sequencer_count <= 1'd0; + if (litedramcore_sequencer_start0) begin + litedramcore_sequencer_count <= 1'd0; end else begin - if (soc_sdram_sequencer_done1) begin - if ((soc_sdram_sequencer_count != 1'd0)) begin - soc_sdram_sequencer_count <= (soc_sdram_sequencer_count - 1'd1); - end - end - end - soc_sdram_cmd_payload_a <= 1'd0; - soc_sdram_cmd_payload_ba <= 1'd0; - soc_sdram_cmd_payload_cas <= 1'd0; - soc_sdram_cmd_payload_ras <= 1'd0; - soc_sdram_cmd_payload_we <= 1'd0; - soc_sdram_sequencer_done1 <= 1'd0; - if ((soc_sdram_sequencer_start1 & (soc_sdram_sequencer_counter == 1'd0))) begin - soc_sdram_cmd_payload_a <= 11'd1024; - soc_sdram_cmd_payload_ba <= 1'd0; - soc_sdram_cmd_payload_cas <= 1'd0; - soc_sdram_cmd_payload_ras <= 1'd1; - soc_sdram_cmd_payload_we <= 1'd1; - end - if ((soc_sdram_sequencer_counter == 2'd3)) begin - soc_sdram_cmd_payload_a <= 1'd0; - soc_sdram_cmd_payload_ba <= 1'd0; - soc_sdram_cmd_payload_cas <= 1'd1; - soc_sdram_cmd_payload_ras <= 1'd1; - soc_sdram_cmd_payload_we <= 1'd0; - end - if ((soc_sdram_sequencer_counter == 6'd55)) begin - soc_sdram_cmd_payload_a <= 1'd0; - soc_sdram_cmd_payload_ba <= 1'd0; - soc_sdram_cmd_payload_cas <= 1'd0; - soc_sdram_cmd_payload_ras <= 1'd0; - soc_sdram_cmd_payload_we <= 1'd0; - soc_sdram_sequencer_done1 <= 1'd1; - end - if ((soc_sdram_sequencer_counter == 6'd55)) begin - soc_sdram_sequencer_counter <= 1'd0; + if (litedramcore_sequencer_done1) begin + if ((litedramcore_sequencer_count != 1'd0)) begin + litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); + end + end + end + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_sequencer_counter == 2'd3)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd1; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd0; + end + if ((litedramcore_sequencer_counter == 6'd55)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd1; + end + if ((litedramcore_sequencer_counter == 6'd55)) begin + litedramcore_sequencer_counter <= 1'd0; end else begin - if ((soc_sdram_sequencer_counter != 1'd0)) begin - soc_sdram_sequencer_counter <= (soc_sdram_sequencer_counter + 1'd1); + if ((litedramcore_sequencer_counter != 1'd0)) begin + litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); end else begin - if (soc_sdram_sequencer_start1) begin - soc_sdram_sequencer_counter <= 1'd1; + if (litedramcore_sequencer_start1) begin + litedramcore_sequencer_counter <= 1'd1; end end end - if ((soc_sdram_zqcs_timer_wait & (~soc_sdram_zqcs_timer_done0))) begin - soc_sdram_zqcs_timer_count1 <= (soc_sdram_zqcs_timer_count1 - 1'd1); + if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin + litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); end else begin - soc_sdram_zqcs_timer_count1 <= 27'd99999999; - end - soc_sdram_zqcs_executer_done <= 1'd0; - if ((soc_sdram_zqcs_executer_start & (soc_sdram_zqcs_executer_counter == 1'd0))) begin - soc_sdram_cmd_payload_a <= 11'd1024; - soc_sdram_cmd_payload_ba <= 1'd0; - soc_sdram_cmd_payload_cas <= 1'd0; - soc_sdram_cmd_payload_ras <= 1'd1; - soc_sdram_cmd_payload_we <= 1'd1; - end - if ((soc_sdram_zqcs_executer_counter == 2'd3)) begin - soc_sdram_cmd_payload_a <= 1'd0; - soc_sdram_cmd_payload_ba <= 1'd0; - soc_sdram_cmd_payload_cas <= 1'd0; - soc_sdram_cmd_payload_ras <= 1'd0; - soc_sdram_cmd_payload_we <= 1'd1; - end - if ((soc_sdram_zqcs_executer_counter == 5'd19)) begin - soc_sdram_cmd_payload_a <= 1'd0; - soc_sdram_cmd_payload_ba <= 1'd0; - soc_sdram_cmd_payload_cas <= 1'd0; - soc_sdram_cmd_payload_ras <= 1'd0; - soc_sdram_cmd_payload_we <= 1'd0; - soc_sdram_zqcs_executer_done <= 1'd1; - end - if ((soc_sdram_zqcs_executer_counter == 5'd19)) begin - soc_sdram_zqcs_executer_counter <= 1'd0; + litedramcore_zqcs_timer_count1 <= 27'd99999999; + end + litedramcore_zqcs_executer_done <= 1'd0; + if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 2'd3)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 5'd19)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_zqcs_executer_done <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 5'd19)) begin + litedramcore_zqcs_executer_counter <= 1'd0; end else begin - if ((soc_sdram_zqcs_executer_counter != 1'd0)) begin - soc_sdram_zqcs_executer_counter <= (soc_sdram_zqcs_executer_counter + 1'd1); + if ((litedramcore_zqcs_executer_counter != 1'd0)) begin + litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); end else begin - if (soc_sdram_zqcs_executer_start) begin - soc_sdram_zqcs_executer_counter <= 1'd1; + if (litedramcore_zqcs_executer_start) begin + litedramcore_zqcs_executer_counter <= 1'd1; end end end - vns_refresher_state <= vns_refresher_next_state; - if (soc_sdram_bankmachine0_row_close) begin - soc_sdram_bankmachine0_row_opened <= 1'd0; + refresher_state <= refresher_next_state; + if (litedramcore_bankmachine0_row_close) begin + litedramcore_bankmachine0_row_opened <= 1'd0; end else begin - if (soc_sdram_bankmachine0_row_open) begin - soc_sdram_bankmachine0_row_opened <= 1'd1; - soc_sdram_bankmachine0_row <= soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:7]; + if (litedramcore_bankmachine0_row_open) begin + litedramcore_bankmachine0_row_opened <= 1'd1; + litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin - soc_sdram_bankmachine0_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); + if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine0_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); + if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin - if ((~soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin - soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1); + if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1); + if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_sdram_bankmachine0_cmd_buffer_source_valid) | soc_sdram_bankmachine0_cmd_buffer_source_ready)) begin - soc_sdram_bankmachine0_cmd_buffer_source_valid <= soc_sdram_bankmachine0_cmd_buffer_sink_valid; - soc_sdram_bankmachine0_cmd_buffer_source_first <= soc_sdram_bankmachine0_cmd_buffer_sink_first; - soc_sdram_bankmachine0_cmd_buffer_source_last <= soc_sdram_bankmachine0_cmd_buffer_sink_last; - soc_sdram_bankmachine0_cmd_buffer_source_payload_we <= soc_sdram_bankmachine0_cmd_buffer_sink_payload_we; - soc_sdram_bankmachine0_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr; + if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin + litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid; + litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first; + litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last; + litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we; + litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; end - if (soc_sdram_bankmachine0_twtpcon_valid) begin - soc_sdram_bankmachine0_twtpcon_count <= 3'd5; + if (litedramcore_bankmachine0_twtpcon_valid) begin + litedramcore_bankmachine0_twtpcon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine0_twtpcon_ready <= 1'd1; + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end else begin - soc_sdram_bankmachine0_twtpcon_ready <= 1'd0; + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine0_twtpcon_ready)) begin - soc_sdram_bankmachine0_twtpcon_count <= (soc_sdram_bankmachine0_twtpcon_count - 1'd1); - if ((soc_sdram_bankmachine0_twtpcon_count == 1'd1)) begin - soc_sdram_bankmachine0_twtpcon_ready <= 1'd1; + if ((~litedramcore_bankmachine0_twtpcon_ready)) begin + litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine0_trccon_valid) begin - soc_sdram_bankmachine0_trccon_count <= 3'd5; + if (litedramcore_bankmachine0_trccon_valid) begin + litedramcore_bankmachine0_trccon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine0_trccon_ready <= 1'd1; + litedramcore_bankmachine0_trccon_ready <= 1'd1; end else begin - soc_sdram_bankmachine0_trccon_ready <= 1'd0; + litedramcore_bankmachine0_trccon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine0_trccon_ready)) begin - soc_sdram_bankmachine0_trccon_count <= (soc_sdram_bankmachine0_trccon_count - 1'd1); - if ((soc_sdram_bankmachine0_trccon_count == 1'd1)) begin - soc_sdram_bankmachine0_trccon_ready <= 1'd1; + if ((~litedramcore_bankmachine0_trccon_ready)) begin + litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); + if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine0_trascon_valid) begin - soc_sdram_bankmachine0_trascon_count <= 3'd4; + if (litedramcore_bankmachine0_trascon_valid) begin + litedramcore_bankmachine0_trascon_count <= 3'd4; if (1'd0) begin - soc_sdram_bankmachine0_trascon_ready <= 1'd1; + litedramcore_bankmachine0_trascon_ready <= 1'd1; end else begin - soc_sdram_bankmachine0_trascon_ready <= 1'd0; + litedramcore_bankmachine0_trascon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine0_trascon_ready)) begin - soc_sdram_bankmachine0_trascon_count <= (soc_sdram_bankmachine0_trascon_count - 1'd1); - if ((soc_sdram_bankmachine0_trascon_count == 1'd1)) begin - soc_sdram_bankmachine0_trascon_ready <= 1'd1; + if ((~litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); + if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; end end end - vns_bankmachine0_state <= vns_bankmachine0_next_state; - if (soc_sdram_bankmachine1_row_close) begin - soc_sdram_bankmachine1_row_opened <= 1'd0; + bankmachine0_state <= bankmachine0_next_state; + if (litedramcore_bankmachine1_row_close) begin + litedramcore_bankmachine1_row_opened <= 1'd0; end else begin - if (soc_sdram_bankmachine1_row_open) begin - soc_sdram_bankmachine1_row_opened <= 1'd1; - soc_sdram_bankmachine1_row <= soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:7]; + if (litedramcore_bankmachine1_row_open) begin + litedramcore_bankmachine1_row_opened <= 1'd1; + litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin - soc_sdram_bankmachine1_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); + if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine1_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); + if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin - if ((~soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin - soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1); + if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1); + if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_sdram_bankmachine1_cmd_buffer_source_valid) | soc_sdram_bankmachine1_cmd_buffer_source_ready)) begin - soc_sdram_bankmachine1_cmd_buffer_source_valid <= soc_sdram_bankmachine1_cmd_buffer_sink_valid; - soc_sdram_bankmachine1_cmd_buffer_source_first <= soc_sdram_bankmachine1_cmd_buffer_sink_first; - soc_sdram_bankmachine1_cmd_buffer_source_last <= soc_sdram_bankmachine1_cmd_buffer_sink_last; - soc_sdram_bankmachine1_cmd_buffer_source_payload_we <= soc_sdram_bankmachine1_cmd_buffer_sink_payload_we; - soc_sdram_bankmachine1_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr; + if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin + litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid; + litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first; + litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last; + litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we; + litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; end - if (soc_sdram_bankmachine1_twtpcon_valid) begin - soc_sdram_bankmachine1_twtpcon_count <= 3'd5; + if (litedramcore_bankmachine1_twtpcon_valid) begin + litedramcore_bankmachine1_twtpcon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine1_twtpcon_ready <= 1'd1; + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end else begin - soc_sdram_bankmachine1_twtpcon_ready <= 1'd0; + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine1_twtpcon_ready)) begin - soc_sdram_bankmachine1_twtpcon_count <= (soc_sdram_bankmachine1_twtpcon_count - 1'd1); - if ((soc_sdram_bankmachine1_twtpcon_count == 1'd1)) begin - soc_sdram_bankmachine1_twtpcon_ready <= 1'd1; + if ((~litedramcore_bankmachine1_twtpcon_ready)) begin + litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine1_trccon_valid) begin - soc_sdram_bankmachine1_trccon_count <= 3'd5; + if (litedramcore_bankmachine1_trccon_valid) begin + litedramcore_bankmachine1_trccon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine1_trccon_ready <= 1'd1; + litedramcore_bankmachine1_trccon_ready <= 1'd1; end else begin - soc_sdram_bankmachine1_trccon_ready <= 1'd0; + litedramcore_bankmachine1_trccon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine1_trccon_ready)) begin - soc_sdram_bankmachine1_trccon_count <= (soc_sdram_bankmachine1_trccon_count - 1'd1); - if ((soc_sdram_bankmachine1_trccon_count == 1'd1)) begin - soc_sdram_bankmachine1_trccon_ready <= 1'd1; + if ((~litedramcore_bankmachine1_trccon_ready)) begin + litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); + if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine1_trascon_valid) begin - soc_sdram_bankmachine1_trascon_count <= 3'd4; + if (litedramcore_bankmachine1_trascon_valid) begin + litedramcore_bankmachine1_trascon_count <= 3'd4; if (1'd0) begin - soc_sdram_bankmachine1_trascon_ready <= 1'd1; + litedramcore_bankmachine1_trascon_ready <= 1'd1; end else begin - soc_sdram_bankmachine1_trascon_ready <= 1'd0; + litedramcore_bankmachine1_trascon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine1_trascon_ready)) begin - soc_sdram_bankmachine1_trascon_count <= (soc_sdram_bankmachine1_trascon_count - 1'd1); - if ((soc_sdram_bankmachine1_trascon_count == 1'd1)) begin - soc_sdram_bankmachine1_trascon_ready <= 1'd1; + if ((~litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); + if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; end end end - vns_bankmachine1_state <= vns_bankmachine1_next_state; - if (soc_sdram_bankmachine2_row_close) begin - soc_sdram_bankmachine2_row_opened <= 1'd0; + bankmachine1_state <= bankmachine1_next_state; + if (litedramcore_bankmachine2_row_close) begin + litedramcore_bankmachine2_row_opened <= 1'd0; end else begin - if (soc_sdram_bankmachine2_row_open) begin - soc_sdram_bankmachine2_row_opened <= 1'd1; - soc_sdram_bankmachine2_row <= soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:7]; + if (litedramcore_bankmachine2_row_open) begin + litedramcore_bankmachine2_row_opened <= 1'd1; + litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin - soc_sdram_bankmachine2_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); + if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine2_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); + if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin - if ((~soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin - soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1); + if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1); + if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_sdram_bankmachine2_cmd_buffer_source_valid) | soc_sdram_bankmachine2_cmd_buffer_source_ready)) begin - soc_sdram_bankmachine2_cmd_buffer_source_valid <= soc_sdram_bankmachine2_cmd_buffer_sink_valid; - soc_sdram_bankmachine2_cmd_buffer_source_first <= soc_sdram_bankmachine2_cmd_buffer_sink_first; - soc_sdram_bankmachine2_cmd_buffer_source_last <= soc_sdram_bankmachine2_cmd_buffer_sink_last; - soc_sdram_bankmachine2_cmd_buffer_source_payload_we <= soc_sdram_bankmachine2_cmd_buffer_sink_payload_we; - soc_sdram_bankmachine2_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr; + if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin + litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid; + litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first; + litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last; + litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we; + litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; end - if (soc_sdram_bankmachine2_twtpcon_valid) begin - soc_sdram_bankmachine2_twtpcon_count <= 3'd5; + if (litedramcore_bankmachine2_twtpcon_valid) begin + litedramcore_bankmachine2_twtpcon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine2_twtpcon_ready <= 1'd1; + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end else begin - soc_sdram_bankmachine2_twtpcon_ready <= 1'd0; + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine2_twtpcon_ready)) begin - soc_sdram_bankmachine2_twtpcon_count <= (soc_sdram_bankmachine2_twtpcon_count - 1'd1); - if ((soc_sdram_bankmachine2_twtpcon_count == 1'd1)) begin - soc_sdram_bankmachine2_twtpcon_ready <= 1'd1; + if ((~litedramcore_bankmachine2_twtpcon_ready)) begin + litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine2_trccon_valid) begin - soc_sdram_bankmachine2_trccon_count <= 3'd5; + if (litedramcore_bankmachine2_trccon_valid) begin + litedramcore_bankmachine2_trccon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine2_trccon_ready <= 1'd1; + litedramcore_bankmachine2_trccon_ready <= 1'd1; end else begin - soc_sdram_bankmachine2_trccon_ready <= 1'd0; + litedramcore_bankmachine2_trccon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine2_trccon_ready)) begin - soc_sdram_bankmachine2_trccon_count <= (soc_sdram_bankmachine2_trccon_count - 1'd1); - if ((soc_sdram_bankmachine2_trccon_count == 1'd1)) begin - soc_sdram_bankmachine2_trccon_ready <= 1'd1; + if ((~litedramcore_bankmachine2_trccon_ready)) begin + litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); + if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine2_trascon_valid) begin - soc_sdram_bankmachine2_trascon_count <= 3'd4; + if (litedramcore_bankmachine2_trascon_valid) begin + litedramcore_bankmachine2_trascon_count <= 3'd4; if (1'd0) begin - soc_sdram_bankmachine2_trascon_ready <= 1'd1; + litedramcore_bankmachine2_trascon_ready <= 1'd1; end else begin - soc_sdram_bankmachine2_trascon_ready <= 1'd0; + litedramcore_bankmachine2_trascon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine2_trascon_ready)) begin - soc_sdram_bankmachine2_trascon_count <= (soc_sdram_bankmachine2_trascon_count - 1'd1); - if ((soc_sdram_bankmachine2_trascon_count == 1'd1)) begin - soc_sdram_bankmachine2_trascon_ready <= 1'd1; + if ((~litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); + if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; end end end - vns_bankmachine2_state <= vns_bankmachine2_next_state; - if (soc_sdram_bankmachine3_row_close) begin - soc_sdram_bankmachine3_row_opened <= 1'd0; + bankmachine2_state <= bankmachine2_next_state; + if (litedramcore_bankmachine3_row_close) begin + litedramcore_bankmachine3_row_opened <= 1'd0; end else begin - if (soc_sdram_bankmachine3_row_open) begin - soc_sdram_bankmachine3_row_opened <= 1'd1; - soc_sdram_bankmachine3_row <= soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:7]; + if (litedramcore_bankmachine3_row_open) begin + litedramcore_bankmachine3_row_opened <= 1'd1; + litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin - soc_sdram_bankmachine3_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); + if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine3_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); + if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin - if ((~soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin - soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1); + if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1); + if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_sdram_bankmachine3_cmd_buffer_source_valid) | soc_sdram_bankmachine3_cmd_buffer_source_ready)) begin - soc_sdram_bankmachine3_cmd_buffer_source_valid <= soc_sdram_bankmachine3_cmd_buffer_sink_valid; - soc_sdram_bankmachine3_cmd_buffer_source_first <= soc_sdram_bankmachine3_cmd_buffer_sink_first; - soc_sdram_bankmachine3_cmd_buffer_source_last <= soc_sdram_bankmachine3_cmd_buffer_sink_last; - soc_sdram_bankmachine3_cmd_buffer_source_payload_we <= soc_sdram_bankmachine3_cmd_buffer_sink_payload_we; - soc_sdram_bankmachine3_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr; + if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin + litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid; + litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first; + litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last; + litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we; + litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; end - if (soc_sdram_bankmachine3_twtpcon_valid) begin - soc_sdram_bankmachine3_twtpcon_count <= 3'd5; + if (litedramcore_bankmachine3_twtpcon_valid) begin + litedramcore_bankmachine3_twtpcon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine3_twtpcon_ready <= 1'd1; + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end else begin - soc_sdram_bankmachine3_twtpcon_ready <= 1'd0; + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine3_twtpcon_ready)) begin - soc_sdram_bankmachine3_twtpcon_count <= (soc_sdram_bankmachine3_twtpcon_count - 1'd1); - if ((soc_sdram_bankmachine3_twtpcon_count == 1'd1)) begin - soc_sdram_bankmachine3_twtpcon_ready <= 1'd1; + if ((~litedramcore_bankmachine3_twtpcon_ready)) begin + litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine3_trccon_valid) begin - soc_sdram_bankmachine3_trccon_count <= 3'd5; + if (litedramcore_bankmachine3_trccon_valid) begin + litedramcore_bankmachine3_trccon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine3_trccon_ready <= 1'd1; + litedramcore_bankmachine3_trccon_ready <= 1'd1; end else begin - soc_sdram_bankmachine3_trccon_ready <= 1'd0; + litedramcore_bankmachine3_trccon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine3_trccon_ready)) begin - soc_sdram_bankmachine3_trccon_count <= (soc_sdram_bankmachine3_trccon_count - 1'd1); - if ((soc_sdram_bankmachine3_trccon_count == 1'd1)) begin - soc_sdram_bankmachine3_trccon_ready <= 1'd1; + if ((~litedramcore_bankmachine3_trccon_ready)) begin + litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); + if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine3_trascon_valid) begin - soc_sdram_bankmachine3_trascon_count <= 3'd4; + if (litedramcore_bankmachine3_trascon_valid) begin + litedramcore_bankmachine3_trascon_count <= 3'd4; if (1'd0) begin - soc_sdram_bankmachine3_trascon_ready <= 1'd1; + litedramcore_bankmachine3_trascon_ready <= 1'd1; end else begin - soc_sdram_bankmachine3_trascon_ready <= 1'd0; + litedramcore_bankmachine3_trascon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine3_trascon_ready)) begin - soc_sdram_bankmachine3_trascon_count <= (soc_sdram_bankmachine3_trascon_count - 1'd1); - if ((soc_sdram_bankmachine3_trascon_count == 1'd1)) begin - soc_sdram_bankmachine3_trascon_ready <= 1'd1; + if ((~litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); + if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; end end end - vns_bankmachine3_state <= vns_bankmachine3_next_state; - if (soc_sdram_bankmachine4_row_close) begin - soc_sdram_bankmachine4_row_opened <= 1'd0; + bankmachine3_state <= bankmachine3_next_state; + if (litedramcore_bankmachine4_row_close) begin + litedramcore_bankmachine4_row_opened <= 1'd0; end else begin - if (soc_sdram_bankmachine4_row_open) begin - soc_sdram_bankmachine4_row_opened <= 1'd1; - soc_sdram_bankmachine4_row <= soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[21:7]; + if (litedramcore_bankmachine4_row_open) begin + litedramcore_bankmachine4_row_opened <= 1'd1; + litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin - soc_sdram_bankmachine4_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); + if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine4_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); + if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin - if ((~soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read)) begin - soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_level + 1'd1); + if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_level - 1'd1); + if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_sdram_bankmachine4_cmd_buffer_source_valid) | soc_sdram_bankmachine4_cmd_buffer_source_ready)) begin - soc_sdram_bankmachine4_cmd_buffer_source_valid <= soc_sdram_bankmachine4_cmd_buffer_sink_valid; - soc_sdram_bankmachine4_cmd_buffer_source_first <= soc_sdram_bankmachine4_cmd_buffer_sink_first; - soc_sdram_bankmachine4_cmd_buffer_source_last <= soc_sdram_bankmachine4_cmd_buffer_sink_last; - soc_sdram_bankmachine4_cmd_buffer_source_payload_we <= soc_sdram_bankmachine4_cmd_buffer_sink_payload_we; - soc_sdram_bankmachine4_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr; + if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin + litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid; + litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first; + litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last; + litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we; + litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; end - if (soc_sdram_bankmachine4_twtpcon_valid) begin - soc_sdram_bankmachine4_twtpcon_count <= 3'd5; + if (litedramcore_bankmachine4_twtpcon_valid) begin + litedramcore_bankmachine4_twtpcon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine4_twtpcon_ready <= 1'd1; + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end else begin - soc_sdram_bankmachine4_twtpcon_ready <= 1'd0; + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine4_twtpcon_ready)) begin - soc_sdram_bankmachine4_twtpcon_count <= (soc_sdram_bankmachine4_twtpcon_count - 1'd1); - if ((soc_sdram_bankmachine4_twtpcon_count == 1'd1)) begin - soc_sdram_bankmachine4_twtpcon_ready <= 1'd1; + if ((~litedramcore_bankmachine4_twtpcon_ready)) begin + litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine4_trccon_valid) begin - soc_sdram_bankmachine4_trccon_count <= 3'd5; + if (litedramcore_bankmachine4_trccon_valid) begin + litedramcore_bankmachine4_trccon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine4_trccon_ready <= 1'd1; + litedramcore_bankmachine4_trccon_ready <= 1'd1; end else begin - soc_sdram_bankmachine4_trccon_ready <= 1'd0; + litedramcore_bankmachine4_trccon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine4_trccon_ready)) begin - soc_sdram_bankmachine4_trccon_count <= (soc_sdram_bankmachine4_trccon_count - 1'd1); - if ((soc_sdram_bankmachine4_trccon_count == 1'd1)) begin - soc_sdram_bankmachine4_trccon_ready <= 1'd1; + if ((~litedramcore_bankmachine4_trccon_ready)) begin + litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); + if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine4_trascon_valid) begin - soc_sdram_bankmachine4_trascon_count <= 3'd4; + if (litedramcore_bankmachine4_trascon_valid) begin + litedramcore_bankmachine4_trascon_count <= 3'd4; if (1'd0) begin - soc_sdram_bankmachine4_trascon_ready <= 1'd1; + litedramcore_bankmachine4_trascon_ready <= 1'd1; end else begin - soc_sdram_bankmachine4_trascon_ready <= 1'd0; + litedramcore_bankmachine4_trascon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine4_trascon_ready)) begin - soc_sdram_bankmachine4_trascon_count <= (soc_sdram_bankmachine4_trascon_count - 1'd1); - if ((soc_sdram_bankmachine4_trascon_count == 1'd1)) begin - soc_sdram_bankmachine4_trascon_ready <= 1'd1; + if ((~litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); + if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; end end end - vns_bankmachine4_state <= vns_bankmachine4_next_state; - if (soc_sdram_bankmachine5_row_close) begin - soc_sdram_bankmachine5_row_opened <= 1'd0; + bankmachine4_state <= bankmachine4_next_state; + if (litedramcore_bankmachine5_row_close) begin + litedramcore_bankmachine5_row_opened <= 1'd0; end else begin - if (soc_sdram_bankmachine5_row_open) begin - soc_sdram_bankmachine5_row_opened <= 1'd1; - soc_sdram_bankmachine5_row <= soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[21:7]; + if (litedramcore_bankmachine5_row_open) begin + litedramcore_bankmachine5_row_opened <= 1'd1; + litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin - soc_sdram_bankmachine5_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); + if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine5_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); + if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin - if ((~soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read)) begin - soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_level + 1'd1); + if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_level - 1'd1); + if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_sdram_bankmachine5_cmd_buffer_source_valid) | soc_sdram_bankmachine5_cmd_buffer_source_ready)) begin - soc_sdram_bankmachine5_cmd_buffer_source_valid <= soc_sdram_bankmachine5_cmd_buffer_sink_valid; - soc_sdram_bankmachine5_cmd_buffer_source_first <= soc_sdram_bankmachine5_cmd_buffer_sink_first; - soc_sdram_bankmachine5_cmd_buffer_source_last <= soc_sdram_bankmachine5_cmd_buffer_sink_last; - soc_sdram_bankmachine5_cmd_buffer_source_payload_we <= soc_sdram_bankmachine5_cmd_buffer_sink_payload_we; - soc_sdram_bankmachine5_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr; + if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin + litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid; + litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first; + litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last; + litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we; + litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; end - if (soc_sdram_bankmachine5_twtpcon_valid) begin - soc_sdram_bankmachine5_twtpcon_count <= 3'd5; + if (litedramcore_bankmachine5_twtpcon_valid) begin + litedramcore_bankmachine5_twtpcon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine5_twtpcon_ready <= 1'd1; + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end else begin - soc_sdram_bankmachine5_twtpcon_ready <= 1'd0; + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine5_twtpcon_ready)) begin - soc_sdram_bankmachine5_twtpcon_count <= (soc_sdram_bankmachine5_twtpcon_count - 1'd1); - if ((soc_sdram_bankmachine5_twtpcon_count == 1'd1)) begin - soc_sdram_bankmachine5_twtpcon_ready <= 1'd1; + if ((~litedramcore_bankmachine5_twtpcon_ready)) begin + litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine5_trccon_valid) begin - soc_sdram_bankmachine5_trccon_count <= 3'd5; + if (litedramcore_bankmachine5_trccon_valid) begin + litedramcore_bankmachine5_trccon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine5_trccon_ready <= 1'd1; + litedramcore_bankmachine5_trccon_ready <= 1'd1; end else begin - soc_sdram_bankmachine5_trccon_ready <= 1'd0; + litedramcore_bankmachine5_trccon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine5_trccon_ready)) begin - soc_sdram_bankmachine5_trccon_count <= (soc_sdram_bankmachine5_trccon_count - 1'd1); - if ((soc_sdram_bankmachine5_trccon_count == 1'd1)) begin - soc_sdram_bankmachine5_trccon_ready <= 1'd1; + if ((~litedramcore_bankmachine5_trccon_ready)) begin + litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); + if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine5_trascon_valid) begin - soc_sdram_bankmachine5_trascon_count <= 3'd4; + if (litedramcore_bankmachine5_trascon_valid) begin + litedramcore_bankmachine5_trascon_count <= 3'd4; if (1'd0) begin - soc_sdram_bankmachine5_trascon_ready <= 1'd1; + litedramcore_bankmachine5_trascon_ready <= 1'd1; end else begin - soc_sdram_bankmachine5_trascon_ready <= 1'd0; + litedramcore_bankmachine5_trascon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine5_trascon_ready)) begin - soc_sdram_bankmachine5_trascon_count <= (soc_sdram_bankmachine5_trascon_count - 1'd1); - if ((soc_sdram_bankmachine5_trascon_count == 1'd1)) begin - soc_sdram_bankmachine5_trascon_ready <= 1'd1; + if ((~litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); + if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; end end end - vns_bankmachine5_state <= vns_bankmachine5_next_state; - if (soc_sdram_bankmachine6_row_close) begin - soc_sdram_bankmachine6_row_opened <= 1'd0; + bankmachine5_state <= bankmachine5_next_state; + if (litedramcore_bankmachine6_row_close) begin + litedramcore_bankmachine6_row_opened <= 1'd0; end else begin - if (soc_sdram_bankmachine6_row_open) begin - soc_sdram_bankmachine6_row_opened <= 1'd1; - soc_sdram_bankmachine6_row <= soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[21:7]; + if (litedramcore_bankmachine6_row_open) begin + litedramcore_bankmachine6_row_opened <= 1'd1; + litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin - soc_sdram_bankmachine6_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); + if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine6_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); + if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin - if ((~soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read)) begin - soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_level + 1'd1); + if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_level - 1'd1); + if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_sdram_bankmachine6_cmd_buffer_source_valid) | soc_sdram_bankmachine6_cmd_buffer_source_ready)) begin - soc_sdram_bankmachine6_cmd_buffer_source_valid <= soc_sdram_bankmachine6_cmd_buffer_sink_valid; - soc_sdram_bankmachine6_cmd_buffer_source_first <= soc_sdram_bankmachine6_cmd_buffer_sink_first; - soc_sdram_bankmachine6_cmd_buffer_source_last <= soc_sdram_bankmachine6_cmd_buffer_sink_last; - soc_sdram_bankmachine6_cmd_buffer_source_payload_we <= soc_sdram_bankmachine6_cmd_buffer_sink_payload_we; - soc_sdram_bankmachine6_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr; + if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin + litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid; + litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first; + litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last; + litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we; + litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; end - if (soc_sdram_bankmachine6_twtpcon_valid) begin - soc_sdram_bankmachine6_twtpcon_count <= 3'd5; + if (litedramcore_bankmachine6_twtpcon_valid) begin + litedramcore_bankmachine6_twtpcon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine6_twtpcon_ready <= 1'd1; + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end else begin - soc_sdram_bankmachine6_twtpcon_ready <= 1'd0; + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine6_twtpcon_ready)) begin - soc_sdram_bankmachine6_twtpcon_count <= (soc_sdram_bankmachine6_twtpcon_count - 1'd1); - if ((soc_sdram_bankmachine6_twtpcon_count == 1'd1)) begin - soc_sdram_bankmachine6_twtpcon_ready <= 1'd1; + if ((~litedramcore_bankmachine6_twtpcon_ready)) begin + litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine6_trccon_valid) begin - soc_sdram_bankmachine6_trccon_count <= 3'd5; + if (litedramcore_bankmachine6_trccon_valid) begin + litedramcore_bankmachine6_trccon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine6_trccon_ready <= 1'd1; + litedramcore_bankmachine6_trccon_ready <= 1'd1; end else begin - soc_sdram_bankmachine6_trccon_ready <= 1'd0; + litedramcore_bankmachine6_trccon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine6_trccon_ready)) begin - soc_sdram_bankmachine6_trccon_count <= (soc_sdram_bankmachine6_trccon_count - 1'd1); - if ((soc_sdram_bankmachine6_trccon_count == 1'd1)) begin - soc_sdram_bankmachine6_trccon_ready <= 1'd1; + if ((~litedramcore_bankmachine6_trccon_ready)) begin + litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); + if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine6_trascon_valid) begin - soc_sdram_bankmachine6_trascon_count <= 3'd4; + if (litedramcore_bankmachine6_trascon_valid) begin + litedramcore_bankmachine6_trascon_count <= 3'd4; if (1'd0) begin - soc_sdram_bankmachine6_trascon_ready <= 1'd1; + litedramcore_bankmachine6_trascon_ready <= 1'd1; end else begin - soc_sdram_bankmachine6_trascon_ready <= 1'd0; + litedramcore_bankmachine6_trascon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine6_trascon_ready)) begin - soc_sdram_bankmachine6_trascon_count <= (soc_sdram_bankmachine6_trascon_count - 1'd1); - if ((soc_sdram_bankmachine6_trascon_count == 1'd1)) begin - soc_sdram_bankmachine6_trascon_ready <= 1'd1; + if ((~litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); + if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; end end end - vns_bankmachine6_state <= vns_bankmachine6_next_state; - if (soc_sdram_bankmachine7_row_close) begin - soc_sdram_bankmachine7_row_opened <= 1'd0; + bankmachine6_state <= bankmachine6_next_state; + if (litedramcore_bankmachine7_row_close) begin + litedramcore_bankmachine7_row_opened <= 1'd0; end else begin - if (soc_sdram_bankmachine7_row_open) begin - soc_sdram_bankmachine7_row_opened <= 1'd1; - soc_sdram_bankmachine7_row <= soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[21:7]; + if (litedramcore_bankmachine7_row_open) begin + litedramcore_bankmachine7_row_opened <= 1'd1; + litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]; end end - if (((soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin - soc_sdram_bankmachine7_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); + if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); end - if (soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine7_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); + if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); end - if (((soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin - if ((~soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read)) begin - soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_level + 1'd1); + if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); end end else begin - if (soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin - soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_level - 1'd1); + if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); end end - if (((~soc_sdram_bankmachine7_cmd_buffer_source_valid) | soc_sdram_bankmachine7_cmd_buffer_source_ready)) begin - soc_sdram_bankmachine7_cmd_buffer_source_valid <= soc_sdram_bankmachine7_cmd_buffer_sink_valid; - soc_sdram_bankmachine7_cmd_buffer_source_first <= soc_sdram_bankmachine7_cmd_buffer_sink_first; - soc_sdram_bankmachine7_cmd_buffer_source_last <= soc_sdram_bankmachine7_cmd_buffer_sink_last; - soc_sdram_bankmachine7_cmd_buffer_source_payload_we <= soc_sdram_bankmachine7_cmd_buffer_sink_payload_we; - soc_sdram_bankmachine7_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr; + if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin + litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid; + litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first; + litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last; + litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we; + litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; end - if (soc_sdram_bankmachine7_twtpcon_valid) begin - soc_sdram_bankmachine7_twtpcon_count <= 3'd5; + if (litedramcore_bankmachine7_twtpcon_valid) begin + litedramcore_bankmachine7_twtpcon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine7_twtpcon_ready <= 1'd1; + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end else begin - soc_sdram_bankmachine7_twtpcon_ready <= 1'd0; + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine7_twtpcon_ready)) begin - soc_sdram_bankmachine7_twtpcon_count <= (soc_sdram_bankmachine7_twtpcon_count - 1'd1); - if ((soc_sdram_bankmachine7_twtpcon_count == 1'd1)) begin - soc_sdram_bankmachine7_twtpcon_ready <= 1'd1; + if ((~litedramcore_bankmachine7_twtpcon_ready)) begin + litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine7_trccon_valid) begin - soc_sdram_bankmachine7_trccon_count <= 3'd5; + if (litedramcore_bankmachine7_trccon_valid) begin + litedramcore_bankmachine7_trccon_count <= 3'd5; if (1'd0) begin - soc_sdram_bankmachine7_trccon_ready <= 1'd1; + litedramcore_bankmachine7_trccon_ready <= 1'd1; end else begin - soc_sdram_bankmachine7_trccon_ready <= 1'd0; + litedramcore_bankmachine7_trccon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine7_trccon_ready)) begin - soc_sdram_bankmachine7_trccon_count <= (soc_sdram_bankmachine7_trccon_count - 1'd1); - if ((soc_sdram_bankmachine7_trccon_count == 1'd1)) begin - soc_sdram_bankmachine7_trccon_ready <= 1'd1; + if ((~litedramcore_bankmachine7_trccon_ready)) begin + litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); + if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; end end end - if (soc_sdram_bankmachine7_trascon_valid) begin - soc_sdram_bankmachine7_trascon_count <= 3'd4; + if (litedramcore_bankmachine7_trascon_valid) begin + litedramcore_bankmachine7_trascon_count <= 3'd4; if (1'd0) begin - soc_sdram_bankmachine7_trascon_ready <= 1'd1; + litedramcore_bankmachine7_trascon_ready <= 1'd1; end else begin - soc_sdram_bankmachine7_trascon_ready <= 1'd0; + litedramcore_bankmachine7_trascon_ready <= 1'd0; end end else begin - if ((~soc_sdram_bankmachine7_trascon_ready)) begin - soc_sdram_bankmachine7_trascon_count <= (soc_sdram_bankmachine7_trascon_count - 1'd1); - if ((soc_sdram_bankmachine7_trascon_count == 1'd1)) begin - soc_sdram_bankmachine7_trascon_ready <= 1'd1; + if ((~litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); + if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; end end end - vns_bankmachine7_state <= vns_bankmachine7_next_state; - if ((~soc_sdram_en0)) begin - soc_sdram_time0 <= 5'd31; + bankmachine7_state <= bankmachine7_next_state; + if ((~litedramcore_en0)) begin + litedramcore_time0 <= 5'd31; end else begin - if ((~soc_sdram_max_time0)) begin - soc_sdram_time0 <= (soc_sdram_time0 - 1'd1); + if ((~litedramcore_max_time0)) begin + litedramcore_time0 <= (litedramcore_time0 - 1'd1); end end - if ((~soc_sdram_en1)) begin - soc_sdram_time1 <= 4'd15; + if ((~litedramcore_en1)) begin + litedramcore_time1 <= 4'd15; end else begin - if ((~soc_sdram_max_time1)) begin - soc_sdram_time1 <= (soc_sdram_time1 - 1'd1); + if ((~litedramcore_max_time1)) begin + litedramcore_time1 <= (litedramcore_time1 - 1'd1); end end - if (soc_sdram_choose_cmd_ce) begin - case (soc_sdram_choose_cmd_grant) + if (litedramcore_choose_cmd_ce) begin + case (litedramcore_choose_cmd_grant) 1'd0: begin - if (soc_sdram_choose_cmd_request[1]) begin - soc_sdram_choose_cmd_grant <= 1'd1; + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_sdram_choose_cmd_request[2]) begin - soc_sdram_choose_cmd_grant <= 2'd2; + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_sdram_choose_cmd_request[3]) begin - soc_sdram_choose_cmd_grant <= 2'd3; + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_sdram_choose_cmd_request[4]) begin - soc_sdram_choose_cmd_grant <= 3'd4; + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_sdram_choose_cmd_request[5]) begin - soc_sdram_choose_cmd_grant <= 3'd5; + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_sdram_choose_cmd_request[6]) begin - soc_sdram_choose_cmd_grant <= 3'd6; + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_sdram_choose_cmd_request[7]) begin - soc_sdram_choose_cmd_grant <= 3'd7; + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; end end end @@ -15999,26 +13619,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (soc_sdram_choose_cmd_request[2]) begin - soc_sdram_choose_cmd_grant <= 2'd2; + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_sdram_choose_cmd_request[3]) begin - soc_sdram_choose_cmd_grant <= 2'd3; + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_sdram_choose_cmd_request[4]) begin - soc_sdram_choose_cmd_grant <= 3'd4; + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_sdram_choose_cmd_request[5]) begin - soc_sdram_choose_cmd_grant <= 3'd5; + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_sdram_choose_cmd_request[6]) begin - soc_sdram_choose_cmd_grant <= 3'd6; + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_sdram_choose_cmd_request[7]) begin - soc_sdram_choose_cmd_grant <= 3'd7; + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_sdram_choose_cmd_request[0]) begin - soc_sdram_choose_cmd_grant <= 1'd0; + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; end end end @@ -16028,26 +13648,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (soc_sdram_choose_cmd_request[3]) begin - soc_sdram_choose_cmd_grant <= 2'd3; + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_sdram_choose_cmd_request[4]) begin - soc_sdram_choose_cmd_grant <= 3'd4; + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_sdram_choose_cmd_request[5]) begin - soc_sdram_choose_cmd_grant <= 3'd5; + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_sdram_choose_cmd_request[6]) begin - soc_sdram_choose_cmd_grant <= 3'd6; + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_sdram_choose_cmd_request[7]) begin - soc_sdram_choose_cmd_grant <= 3'd7; + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_sdram_choose_cmd_request[0]) begin - soc_sdram_choose_cmd_grant <= 1'd0; + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_sdram_choose_cmd_request[1]) begin - soc_sdram_choose_cmd_grant <= 1'd1; + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; end end end @@ -16057,26 +13677,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (soc_sdram_choose_cmd_request[4]) begin - soc_sdram_choose_cmd_grant <= 3'd4; + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_sdram_choose_cmd_request[5]) begin - soc_sdram_choose_cmd_grant <= 3'd5; + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_sdram_choose_cmd_request[6]) begin - soc_sdram_choose_cmd_grant <= 3'd6; + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_sdram_choose_cmd_request[7]) begin - soc_sdram_choose_cmd_grant <= 3'd7; + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_sdram_choose_cmd_request[0]) begin - soc_sdram_choose_cmd_grant <= 1'd0; + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_sdram_choose_cmd_request[1]) begin - soc_sdram_choose_cmd_grant <= 1'd1; + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_sdram_choose_cmd_request[2]) begin - soc_sdram_choose_cmd_grant <= 2'd2; + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; end end end @@ -16086,26 +13706,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (soc_sdram_choose_cmd_request[5]) begin - soc_sdram_choose_cmd_grant <= 3'd5; + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_sdram_choose_cmd_request[6]) begin - soc_sdram_choose_cmd_grant <= 3'd6; + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_sdram_choose_cmd_request[7]) begin - soc_sdram_choose_cmd_grant <= 3'd7; + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_sdram_choose_cmd_request[0]) begin - soc_sdram_choose_cmd_grant <= 1'd0; + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_sdram_choose_cmd_request[1]) begin - soc_sdram_choose_cmd_grant <= 1'd1; + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_sdram_choose_cmd_request[2]) begin - soc_sdram_choose_cmd_grant <= 2'd2; + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_sdram_choose_cmd_request[3]) begin - soc_sdram_choose_cmd_grant <= 2'd3; + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; end end end @@ -16115,26 +13735,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (soc_sdram_choose_cmd_request[6]) begin - soc_sdram_choose_cmd_grant <= 3'd6; + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; end else begin - if (soc_sdram_choose_cmd_request[7]) begin - soc_sdram_choose_cmd_grant <= 3'd7; + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_sdram_choose_cmd_request[0]) begin - soc_sdram_choose_cmd_grant <= 1'd0; + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_sdram_choose_cmd_request[1]) begin - soc_sdram_choose_cmd_grant <= 1'd1; + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_sdram_choose_cmd_request[2]) begin - soc_sdram_choose_cmd_grant <= 2'd2; + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_sdram_choose_cmd_request[3]) begin - soc_sdram_choose_cmd_grant <= 2'd3; + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_sdram_choose_cmd_request[4]) begin - soc_sdram_choose_cmd_grant <= 3'd4; + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; end end end @@ -16144,26 +13764,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (soc_sdram_choose_cmd_request[7]) begin - soc_sdram_choose_cmd_grant <= 3'd7; + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; end else begin - if (soc_sdram_choose_cmd_request[0]) begin - soc_sdram_choose_cmd_grant <= 1'd0; + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_sdram_choose_cmd_request[1]) begin - soc_sdram_choose_cmd_grant <= 1'd1; + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_sdram_choose_cmd_request[2]) begin - soc_sdram_choose_cmd_grant <= 2'd2; + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_sdram_choose_cmd_request[3]) begin - soc_sdram_choose_cmd_grant <= 2'd3; + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_sdram_choose_cmd_request[4]) begin - soc_sdram_choose_cmd_grant <= 3'd4; + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_sdram_choose_cmd_request[5]) begin - soc_sdram_choose_cmd_grant <= 3'd5; + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; end end end @@ -16173,26 +13793,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (soc_sdram_choose_cmd_request[0]) begin - soc_sdram_choose_cmd_grant <= 1'd0; + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; end else begin - if (soc_sdram_choose_cmd_request[1]) begin - soc_sdram_choose_cmd_grant <= 1'd1; + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; end else begin - if (soc_sdram_choose_cmd_request[2]) begin - soc_sdram_choose_cmd_grant <= 2'd2; + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; end else begin - if (soc_sdram_choose_cmd_request[3]) begin - soc_sdram_choose_cmd_grant <= 2'd3; + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; end else begin - if (soc_sdram_choose_cmd_request[4]) begin - soc_sdram_choose_cmd_grant <= 3'd4; + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; end else begin - if (soc_sdram_choose_cmd_request[5]) begin - soc_sdram_choose_cmd_grant <= 3'd5; + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; end else begin - if (soc_sdram_choose_cmd_request[6]) begin - soc_sdram_choose_cmd_grant <= 3'd6; + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; end end end @@ -16203,29 +13823,29 @@ always @(posedge sys_clk) begin end endcase end - if (soc_sdram_choose_req_ce) begin - case (soc_sdram_choose_req_grant) + if (litedramcore_choose_req_ce) begin + case (litedramcore_choose_req_grant) 1'd0: begin - if (soc_sdram_choose_req_request[1]) begin - soc_sdram_choose_req_grant <= 1'd1; + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_sdram_choose_req_request[2]) begin - soc_sdram_choose_req_grant <= 2'd2; + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_sdram_choose_req_request[3]) begin - soc_sdram_choose_req_grant <= 2'd3; + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_sdram_choose_req_request[4]) begin - soc_sdram_choose_req_grant <= 3'd4; + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_sdram_choose_req_request[5]) begin - soc_sdram_choose_req_grant <= 3'd5; + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_sdram_choose_req_request[6]) begin - soc_sdram_choose_req_grant <= 3'd6; + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_sdram_choose_req_request[7]) begin - soc_sdram_choose_req_grant <= 3'd7; + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; end end end @@ -16235,26 +13855,26 @@ always @(posedge sys_clk) begin end end 1'd1: begin - if (soc_sdram_choose_req_request[2]) begin - soc_sdram_choose_req_grant <= 2'd2; + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_sdram_choose_req_request[3]) begin - soc_sdram_choose_req_grant <= 2'd3; + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_sdram_choose_req_request[4]) begin - soc_sdram_choose_req_grant <= 3'd4; + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_sdram_choose_req_request[5]) begin - soc_sdram_choose_req_grant <= 3'd5; + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_sdram_choose_req_request[6]) begin - soc_sdram_choose_req_grant <= 3'd6; + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_sdram_choose_req_request[7]) begin - soc_sdram_choose_req_grant <= 3'd7; + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_sdram_choose_req_request[0]) begin - soc_sdram_choose_req_grant <= 1'd0; + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; end end end @@ -16264,26 +13884,26 @@ always @(posedge sys_clk) begin end end 2'd2: begin - if (soc_sdram_choose_req_request[3]) begin - soc_sdram_choose_req_grant <= 2'd3; + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_sdram_choose_req_request[4]) begin - soc_sdram_choose_req_grant <= 3'd4; + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_sdram_choose_req_request[5]) begin - soc_sdram_choose_req_grant <= 3'd5; + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_sdram_choose_req_request[6]) begin - soc_sdram_choose_req_grant <= 3'd6; + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_sdram_choose_req_request[7]) begin - soc_sdram_choose_req_grant <= 3'd7; + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_sdram_choose_req_request[0]) begin - soc_sdram_choose_req_grant <= 1'd0; + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_sdram_choose_req_request[1]) begin - soc_sdram_choose_req_grant <= 1'd1; + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; end end end @@ -16293,26 +13913,26 @@ always @(posedge sys_clk) begin end end 2'd3: begin - if (soc_sdram_choose_req_request[4]) begin - soc_sdram_choose_req_grant <= 3'd4; + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_sdram_choose_req_request[5]) begin - soc_sdram_choose_req_grant <= 3'd5; + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_sdram_choose_req_request[6]) begin - soc_sdram_choose_req_grant <= 3'd6; + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_sdram_choose_req_request[7]) begin - soc_sdram_choose_req_grant <= 3'd7; + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_sdram_choose_req_request[0]) begin - soc_sdram_choose_req_grant <= 1'd0; + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_sdram_choose_req_request[1]) begin - soc_sdram_choose_req_grant <= 1'd1; + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_sdram_choose_req_request[2]) begin - soc_sdram_choose_req_grant <= 2'd2; + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; end end end @@ -16322,26 +13942,26 @@ always @(posedge sys_clk) begin end end 3'd4: begin - if (soc_sdram_choose_req_request[5]) begin - soc_sdram_choose_req_grant <= 3'd5; + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_sdram_choose_req_request[6]) begin - soc_sdram_choose_req_grant <= 3'd6; + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_sdram_choose_req_request[7]) begin - soc_sdram_choose_req_grant <= 3'd7; + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_sdram_choose_req_request[0]) begin - soc_sdram_choose_req_grant <= 1'd0; + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_sdram_choose_req_request[1]) begin - soc_sdram_choose_req_grant <= 1'd1; + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_sdram_choose_req_request[2]) begin - soc_sdram_choose_req_grant <= 2'd2; + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_sdram_choose_req_request[3]) begin - soc_sdram_choose_req_grant <= 2'd3; + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; end end end @@ -16351,26 +13971,26 @@ always @(posedge sys_clk) begin end end 3'd5: begin - if (soc_sdram_choose_req_request[6]) begin - soc_sdram_choose_req_grant <= 3'd6; + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; end else begin - if (soc_sdram_choose_req_request[7]) begin - soc_sdram_choose_req_grant <= 3'd7; + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_sdram_choose_req_request[0]) begin - soc_sdram_choose_req_grant <= 1'd0; + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_sdram_choose_req_request[1]) begin - soc_sdram_choose_req_grant <= 1'd1; + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_sdram_choose_req_request[2]) begin - soc_sdram_choose_req_grant <= 2'd2; + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_sdram_choose_req_request[3]) begin - soc_sdram_choose_req_grant <= 2'd3; + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_sdram_choose_req_request[4]) begin - soc_sdram_choose_req_grant <= 3'd4; + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; end end end @@ -16380,26 +14000,26 @@ always @(posedge sys_clk) begin end end 3'd6: begin - if (soc_sdram_choose_req_request[7]) begin - soc_sdram_choose_req_grant <= 3'd7; + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; end else begin - if (soc_sdram_choose_req_request[0]) begin - soc_sdram_choose_req_grant <= 1'd0; + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_sdram_choose_req_request[1]) begin - soc_sdram_choose_req_grant <= 1'd1; + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_sdram_choose_req_request[2]) begin - soc_sdram_choose_req_grant <= 2'd2; + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_sdram_choose_req_request[3]) begin - soc_sdram_choose_req_grant <= 2'd3; + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_sdram_choose_req_request[4]) begin - soc_sdram_choose_req_grant <= 3'd4; + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_sdram_choose_req_request[5]) begin - soc_sdram_choose_req_grant <= 3'd5; + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; end end end @@ -16409,26 +14029,26 @@ always @(posedge sys_clk) begin end end 3'd7: begin - if (soc_sdram_choose_req_request[0]) begin - soc_sdram_choose_req_grant <= 1'd0; + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; end else begin - if (soc_sdram_choose_req_request[1]) begin - soc_sdram_choose_req_grant <= 1'd1; + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; end else begin - if (soc_sdram_choose_req_request[2]) begin - soc_sdram_choose_req_grant <= 2'd2; + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; end else begin - if (soc_sdram_choose_req_request[3]) begin - soc_sdram_choose_req_grant <= 2'd3; + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; end else begin - if (soc_sdram_choose_req_request[4]) begin - soc_sdram_choose_req_grant <= 3'd4; + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; end else begin - if (soc_sdram_choose_req_request[5]) begin - soc_sdram_choose_req_grant <= 3'd5; + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; end else begin - if (soc_sdram_choose_req_request[6]) begin - soc_sdram_choose_req_grant <= 3'd6; + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; end end end @@ -16439,1280 +14059,709 @@ always @(posedge sys_clk) begin end endcase end - soc_sdram_dfi_p0_cs_n <= 1'd0; - soc_sdram_dfi_p0_bank <= vns_array_muxed0; - soc_sdram_dfi_p0_address <= vns_array_muxed1; - soc_sdram_dfi_p0_cas_n <= (~vns_array_muxed2); - soc_sdram_dfi_p0_ras_n <= (~vns_array_muxed3); - soc_sdram_dfi_p0_we_n <= (~vns_array_muxed4); - soc_sdram_dfi_p0_rddata_en <= vns_array_muxed5; - soc_sdram_dfi_p0_wrdata_en <= vns_array_muxed6; - soc_sdram_dfi_p1_cs_n <= 1'd0; - soc_sdram_dfi_p1_bank <= vns_array_muxed7; - soc_sdram_dfi_p1_address <= vns_array_muxed8; - soc_sdram_dfi_p1_cas_n <= (~vns_array_muxed9); - soc_sdram_dfi_p1_ras_n <= (~vns_array_muxed10); - soc_sdram_dfi_p1_we_n <= (~vns_array_muxed11); - soc_sdram_dfi_p1_rddata_en <= vns_array_muxed12; - soc_sdram_dfi_p1_wrdata_en <= vns_array_muxed13; - soc_sdram_dfi_p2_cs_n <= 1'd0; - soc_sdram_dfi_p2_bank <= vns_array_muxed14; - soc_sdram_dfi_p2_address <= vns_array_muxed15; - soc_sdram_dfi_p2_cas_n <= (~vns_array_muxed16); - soc_sdram_dfi_p2_ras_n <= (~vns_array_muxed17); - soc_sdram_dfi_p2_we_n <= (~vns_array_muxed18); - soc_sdram_dfi_p2_rddata_en <= vns_array_muxed19; - soc_sdram_dfi_p2_wrdata_en <= vns_array_muxed20; - soc_sdram_dfi_p3_cs_n <= 1'd0; - soc_sdram_dfi_p3_bank <= vns_array_muxed21; - soc_sdram_dfi_p3_address <= vns_array_muxed22; - soc_sdram_dfi_p3_cas_n <= (~vns_array_muxed23); - soc_sdram_dfi_p3_ras_n <= (~vns_array_muxed24); - soc_sdram_dfi_p3_we_n <= (~vns_array_muxed25); - soc_sdram_dfi_p3_rddata_en <= vns_array_muxed26; - soc_sdram_dfi_p3_wrdata_en <= vns_array_muxed27; - if (soc_sdram_trrdcon_valid) begin - soc_sdram_trrdcon_count <= 1'd1; + litedramcore_dfi_p0_cs_n <= 1'd0; + litedramcore_dfi_p0_bank <= array_muxed0; + litedramcore_dfi_p0_address <= array_muxed1; + litedramcore_dfi_p0_cas_n <= (~array_muxed2); + litedramcore_dfi_p0_ras_n <= (~array_muxed3); + litedramcore_dfi_p0_we_n <= (~array_muxed4); + litedramcore_dfi_p0_rddata_en <= array_muxed5; + litedramcore_dfi_p0_wrdata_en <= array_muxed6; + litedramcore_dfi_p1_cs_n <= 1'd0; + litedramcore_dfi_p1_bank <= array_muxed7; + litedramcore_dfi_p1_address <= array_muxed8; + litedramcore_dfi_p1_cas_n <= (~array_muxed9); + litedramcore_dfi_p1_ras_n <= (~array_muxed10); + litedramcore_dfi_p1_we_n <= (~array_muxed11); + litedramcore_dfi_p1_rddata_en <= array_muxed12; + litedramcore_dfi_p1_wrdata_en <= array_muxed13; + litedramcore_dfi_p2_cs_n <= 1'd0; + litedramcore_dfi_p2_bank <= array_muxed14; + litedramcore_dfi_p2_address <= array_muxed15; + litedramcore_dfi_p2_cas_n <= (~array_muxed16); + litedramcore_dfi_p2_ras_n <= (~array_muxed17); + litedramcore_dfi_p2_we_n <= (~array_muxed18); + litedramcore_dfi_p2_rddata_en <= array_muxed19; + litedramcore_dfi_p2_wrdata_en <= array_muxed20; + litedramcore_dfi_p3_cs_n <= 1'd0; + litedramcore_dfi_p3_bank <= array_muxed21; + litedramcore_dfi_p3_address <= array_muxed22; + litedramcore_dfi_p3_cas_n <= (~array_muxed23); + litedramcore_dfi_p3_ras_n <= (~array_muxed24); + litedramcore_dfi_p3_we_n <= (~array_muxed25); + litedramcore_dfi_p3_rddata_en <= array_muxed26; + litedramcore_dfi_p3_wrdata_en <= array_muxed27; + if (litedramcore_trrdcon_valid) begin + litedramcore_trrdcon_count <= 1'd1; if (1'd0) begin - soc_sdram_trrdcon_ready <= 1'd1; + litedramcore_trrdcon_ready <= 1'd1; end else begin - soc_sdram_trrdcon_ready <= 1'd0; + litedramcore_trrdcon_ready <= 1'd0; end end else begin - if ((~soc_sdram_trrdcon_ready)) begin - soc_sdram_trrdcon_count <= (soc_sdram_trrdcon_count - 1'd1); - if ((soc_sdram_trrdcon_count == 1'd1)) begin - soc_sdram_trrdcon_ready <= 1'd1; + if ((~litedramcore_trrdcon_ready)) begin + litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); + if ((litedramcore_trrdcon_count == 1'd1)) begin + litedramcore_trrdcon_ready <= 1'd1; end end end - soc_sdram_tfawcon_window <= {soc_sdram_tfawcon_window, soc_sdram_tfawcon_valid}; - if ((soc_sdram_tfawcon_count < 3'd4)) begin - if ((soc_sdram_tfawcon_count == 2'd3)) begin - soc_sdram_tfawcon_ready <= (~soc_sdram_tfawcon_valid); + litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; + if ((litedramcore_tfawcon_count < 3'd4)) begin + if ((litedramcore_tfawcon_count == 2'd3)) begin + litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); end else begin - soc_sdram_tfawcon_ready <= 1'd1; + litedramcore_tfawcon_ready <= 1'd1; end end - if (soc_sdram_tccdcon_valid) begin - soc_sdram_tccdcon_count <= 1'd0; + if (litedramcore_tccdcon_valid) begin + litedramcore_tccdcon_count <= 1'd0; if (1'd1) begin - soc_sdram_tccdcon_ready <= 1'd1; + litedramcore_tccdcon_ready <= 1'd1; end else begin - soc_sdram_tccdcon_ready <= 1'd0; + litedramcore_tccdcon_ready <= 1'd0; end end else begin - if ((~soc_sdram_tccdcon_ready)) begin - soc_sdram_tccdcon_count <= (soc_sdram_tccdcon_count - 1'd1); - if ((soc_sdram_tccdcon_count == 1'd1)) begin - soc_sdram_tccdcon_ready <= 1'd1; + if ((~litedramcore_tccdcon_ready)) begin + litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); + if ((litedramcore_tccdcon_count == 1'd1)) begin + litedramcore_tccdcon_ready <= 1'd1; end end end - if (soc_sdram_twtrcon_valid) begin - soc_sdram_twtrcon_count <= 3'd4; + if (litedramcore_twtrcon_valid) begin + litedramcore_twtrcon_count <= 3'd4; if (1'd0) begin - soc_sdram_twtrcon_ready <= 1'd1; + litedramcore_twtrcon_ready <= 1'd1; end else begin - soc_sdram_twtrcon_ready <= 1'd0; - end - end else begin - if ((~soc_sdram_twtrcon_ready)) begin - soc_sdram_twtrcon_count <= (soc_sdram_twtrcon_count - 1'd1); - if ((soc_sdram_twtrcon_count == 1'd1)) begin - soc_sdram_twtrcon_ready <= 1'd1; - end - end - end - vns_multiplexer_state <= vns_multiplexer_next_state; - vns_new_master_wdata_ready0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_sdram_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd0) & soc_sdram_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd0) & soc_sdram_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd0) & soc_sdram_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd0) & soc_sdram_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd0) & soc_sdram_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd0) & soc_sdram_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd0) & soc_sdram_interface_bank7_wdata_ready)); - vns_new_master_wdata_ready1 <= vns_new_master_wdata_ready0; - vns_new_master_wdata_ready2 <= vns_new_master_wdata_ready1; - vns_new_master_wdata_ready3 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd1) & soc_sdram_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd1) & soc_sdram_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd1) & soc_sdram_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd1) & soc_sdram_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd1) & soc_sdram_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd1) & soc_sdram_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd1) & soc_sdram_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd1) & soc_sdram_interface_bank7_wdata_ready)); - vns_new_master_wdata_ready4 <= vns_new_master_wdata_ready3; - vns_new_master_wdata_ready5 <= vns_new_master_wdata_ready4; - vns_new_master_rdata_valid0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_sdram_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd0) & soc_sdram_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd0) & soc_sdram_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd0) & soc_sdram_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd0) & soc_sdram_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd0) & soc_sdram_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd0) & soc_sdram_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd0) & soc_sdram_interface_bank7_rdata_valid)); - vns_new_master_rdata_valid1 <= vns_new_master_rdata_valid0; - vns_new_master_rdata_valid2 <= vns_new_master_rdata_valid1; - vns_new_master_rdata_valid3 <= vns_new_master_rdata_valid2; - vns_new_master_rdata_valid4 <= vns_new_master_rdata_valid3; - vns_new_master_rdata_valid5 <= vns_new_master_rdata_valid4; - vns_new_master_rdata_valid6 <= vns_new_master_rdata_valid5; - vns_new_master_rdata_valid7 <= vns_new_master_rdata_valid6; - vns_new_master_rdata_valid8 <= vns_new_master_rdata_valid7; - vns_new_master_rdata_valid9 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd1) & soc_sdram_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd1) & soc_sdram_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd1) & soc_sdram_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd1) & soc_sdram_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd1) & soc_sdram_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd1) & soc_sdram_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd1) & soc_sdram_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd1) & soc_sdram_interface_bank7_rdata_valid)); - vns_new_master_rdata_valid10 <= vns_new_master_rdata_valid9; - vns_new_master_rdata_valid11 <= vns_new_master_rdata_valid10; - vns_new_master_rdata_valid12 <= vns_new_master_rdata_valid11; - vns_new_master_rdata_valid13 <= vns_new_master_rdata_valid12; - vns_new_master_rdata_valid14 <= vns_new_master_rdata_valid13; - vns_new_master_rdata_valid15 <= vns_new_master_rdata_valid14; - vns_new_master_rdata_valid16 <= vns_new_master_rdata_valid15; - vns_new_master_rdata_valid17 <= vns_new_master_rdata_valid16; - if (vns_roundrobin0_ce) begin - case (vns_roundrobin0_grant) - 1'd0: begin - if (vns_roundrobin0_request[1]) begin - vns_roundrobin0_grant <= 1'd1; - end - end - 1'd1: begin - if (vns_roundrobin0_request[0]) begin - vns_roundrobin0_grant <= 1'd0; - end - end - endcase - end - if (vns_roundrobin1_ce) begin - case (vns_roundrobin1_grant) - 1'd0: begin - if (vns_roundrobin1_request[1]) begin - vns_roundrobin1_grant <= 1'd1; - end - end - 1'd1: begin - if (vns_roundrobin1_request[0]) begin - vns_roundrobin1_grant <= 1'd0; - end - end - endcase - end - if (vns_roundrobin2_ce) begin - case (vns_roundrobin2_grant) - 1'd0: begin - if (vns_roundrobin2_request[1]) begin - vns_roundrobin2_grant <= 1'd1; - end - end - 1'd1: begin - if (vns_roundrobin2_request[0]) begin - vns_roundrobin2_grant <= 1'd0; - end - end - endcase - end - if (vns_roundrobin3_ce) begin - case (vns_roundrobin3_grant) - 1'd0: begin - if (vns_roundrobin3_request[1]) begin - vns_roundrobin3_grant <= 1'd1; - end - end - 1'd1: begin - if (vns_roundrobin3_request[0]) begin - vns_roundrobin3_grant <= 1'd0; - end - end - endcase - end - if (vns_roundrobin4_ce) begin - case (vns_roundrobin4_grant) - 1'd0: begin - if (vns_roundrobin4_request[1]) begin - vns_roundrobin4_grant <= 1'd1; - end - end - 1'd1: begin - if (vns_roundrobin4_request[0]) begin - vns_roundrobin4_grant <= 1'd0; - end - end - endcase - end - if (vns_roundrobin5_ce) begin - case (vns_roundrobin5_grant) - 1'd0: begin - if (vns_roundrobin5_request[1]) begin - vns_roundrobin5_grant <= 1'd1; - end - end - 1'd1: begin - if (vns_roundrobin5_request[0]) begin - vns_roundrobin5_grant <= 1'd0; - end - end - endcase - end - if (vns_roundrobin6_ce) begin - case (vns_roundrobin6_grant) - 1'd0: begin - if (vns_roundrobin6_request[1]) begin - vns_roundrobin6_grant <= 1'd1; - end - end - 1'd1: begin - if (vns_roundrobin6_request[0]) begin - vns_roundrobin6_grant <= 1'd0; - end - end - endcase - end - if (vns_roundrobin7_ce) begin - case (vns_roundrobin7_grant) - 1'd0: begin - if (vns_roundrobin7_request[1]) begin - vns_roundrobin7_grant <= 1'd1; - end - end - 1'd1: begin - if (vns_roundrobin7_request[0]) begin - vns_roundrobin7_grant <= 1'd0; - end - end - endcase - end - if (soc_counter_reset) begin - soc_counter <= 1'd0; - end else begin - if (soc_counter_ce) begin - soc_counter <= (soc_counter + 1'd1); - end - end - if (soc_address_ce) begin - soc_address_q <= soc_address_d; - end - if (soc_address_reset) begin - soc_address_q <= 30'd0; - end - if (soc_need_refill_ce) begin - soc_need_refill_q <= soc_need_refill_d; - end - if (soc_need_refill_reset) begin - soc_need_refill_q <= 1'd1; - end - vns_converter_state <= vns_converter_next_state; - if (soc_cached_datas_ce0) begin - soc_cached_datas_flipflop0_q <= soc_cached_datas_flipflop0_d; - end - if (soc_cached_datas_reset0) begin - soc_cached_datas_flipflop0_q <= 32'd0; - end - if (soc_cached_datas_ce1) begin - soc_cached_datas_flipflop1_q <= soc_cached_datas_flipflop1_d; - end - if (soc_cached_datas_reset1) begin - soc_cached_datas_flipflop1_q <= 32'd0; - end - if (soc_cached_datas_ce2) begin - soc_cached_datas_flipflop2_q <= soc_cached_datas_flipflop2_d; - end - if (soc_cached_datas_reset2) begin - soc_cached_datas_flipflop2_q <= 32'd0; - end - if (soc_cached_datas_ce3) begin - soc_cached_datas_flipflop3_q <= soc_cached_datas_flipflop3_d; - end - if (soc_cached_datas_reset3) begin - soc_cached_datas_flipflop3_q <= 32'd0; - end - if (soc_cached_sels_ce0) begin - soc_cached_sels_flipflop0_q <= soc_cached_sels_flipflop0_d; - end - if (soc_cached_sels_reset0) begin - soc_cached_sels_flipflop0_q <= 4'd0; - end - if (soc_cached_sels_ce1) begin - soc_cached_sels_flipflop1_q <= soc_cached_sels_flipflop1_d; - end - if (soc_cached_sels_reset1) begin - soc_cached_sels_flipflop1_q <= 4'd0; - end - if (soc_cached_sels_ce2) begin - soc_cached_sels_flipflop2_q <= soc_cached_sels_flipflop2_d; - end - if (soc_cached_sels_reset2) begin - soc_cached_sels_flipflop2_q <= 4'd0; - end - if (soc_cached_sels_ce3) begin - soc_cached_sels_flipflop3_q <= soc_cached_sels_flipflop3_d; - end - if (soc_cached_sels_reset3) begin - soc_cached_sels_flipflop3_q <= 4'd0; - end - vns_litedramwishbone2native_state <= vns_litedramwishbone2native_next_state; - if (soc_count_next_value_ce) begin - soc_count <= soc_count_next_value; - end - case (vns_grant) - 1'd0: begin - if ((~vns_request[0])) begin - if (vns_request[1]) begin - vns_grant <= 1'd1; - end - end - end - 1'd1: begin - if ((~vns_request[1])) begin - if (vns_request[0]) begin - vns_grant <= 1'd0; - end - end - end - endcase - vns_slave_sel_r <= vns_slave_sel; - if (vns_wait) begin - if ((~vns_done)) begin - vns_count <= (vns_count - 1'd1); + litedramcore_twtrcon_ready <= 1'd0; end end else begin - vns_count <= 20'd1000000; - end - vns_interface0_bank_bus_dat_r <= 1'd0; - if (vns_csrbank0_sel) begin - case (vns_interface0_bank_bus_adr[3:0]) - 1'd0: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_reset0_w; - end - 1'd1: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch3_w; - end - 2'd2: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch2_w; - end - 2'd3: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch1_w; - end - 3'd4: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch0_w; - end - 3'd5: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors3_w; - end - 3'd6: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors2_w; - end - 3'd7: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors1_w; - end - 4'd8: begin - vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors0_w; - end - endcase - end - if (vns_csrbank0_reset0_re) begin - soc_litedramcore_soccontroller_reset_storage <= vns_csrbank0_reset0_r; - end - soc_litedramcore_soccontroller_reset_re <= vns_csrbank0_reset0_re; - if (vns_csrbank0_scratch3_re) begin - soc_litedramcore_soccontroller_scratch_storage[31:24] <= vns_csrbank0_scratch3_r; - end - if (vns_csrbank0_scratch2_re) begin - soc_litedramcore_soccontroller_scratch_storage[23:16] <= vns_csrbank0_scratch2_r; - end - if (vns_csrbank0_scratch1_re) begin - soc_litedramcore_soccontroller_scratch_storage[15:8] <= vns_csrbank0_scratch1_r; - end - if (vns_csrbank0_scratch0_re) begin - soc_litedramcore_soccontroller_scratch_storage[7:0] <= vns_csrbank0_scratch0_r; - end - soc_litedramcore_soccontroller_scratch_re <= vns_csrbank0_scratch0_re; - vns_interface1_bank_bus_dat_r <= 1'd0; - if (vns_csrbank1_sel) begin - case (vns_interface1_bank_bus_adr[0]) + if ((~litedramcore_twtrcon_ready)) begin + litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); + if ((litedramcore_twtrcon_count == 1'd1)) begin + litedramcore_twtrcon_ready <= 1'd1; + end + end + end + multiplexer_state <= multiplexer_next_state; + new_master_wdata_ready0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); + new_master_wdata_ready1 <= new_master_wdata_ready0; + new_master_wdata_ready2 <= new_master_wdata_ready1; + new_master_rdata_valid0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); + new_master_rdata_valid1 <= new_master_rdata_valid0; + new_master_rdata_valid2 <= new_master_rdata_valid1; + new_master_rdata_valid3 <= new_master_rdata_valid2; + new_master_rdata_valid4 <= new_master_rdata_valid3; + new_master_rdata_valid5 <= new_master_rdata_valid4; + new_master_rdata_valid6 <= new_master_rdata_valid5; + new_master_rdata_valid7 <= new_master_rdata_valid6; + new_master_rdata_valid8 <= new_master_rdata_valid7; + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[3]) 1'd0: begin - vns_interface1_bank_bus_dat_r <= vns_csrbank1_init_done0_w; + interface0_bank_bus_dat_r <= csrbank0_init_done0_w; end 1'd1: begin - vns_interface1_bank_bus_dat_r <= vns_csrbank1_init_error0_w; + interface0_bank_bus_dat_r <= csrbank0_init_error0_w; end endcase end - if (vns_csrbank1_init_done0_re) begin - soc_init_done_storage <= vns_csrbank1_init_done0_r; + if (csrbank0_init_done0_re) begin + init_done_storage <= csrbank0_init_done0_r; end - soc_init_done_re <= vns_csrbank1_init_done0_re; - if (vns_csrbank1_init_error0_re) begin - soc_init_error_storage <= vns_csrbank1_init_error0_r; + init_done_re <= csrbank0_init_done0_re; + if (csrbank0_init_error0_re) begin + init_error_storage <= csrbank0_init_error0_r; end - soc_init_error_re <= vns_csrbank1_init_error0_re; - vns_interface2_bank_bus_dat_r <= 1'd0; - if (vns_csrbank2_sel) begin - case (vns_interface2_bank_bus_adr[3:0]) + init_error_re <= csrbank0_init_error0_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[6:3]) 1'd0: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_half_sys8x_taps0_w; + interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; end 1'd1: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_wlevel_en0_w; + interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w; end 2'd2: begin - vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_wlevel_strobe_w; + interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w; end 2'd3: begin - vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_cdly_rst_w; + interface1_bank_bus_dat_r <= a7ddrphy_cdly_rst_w; end 3'd4: begin - vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_cdly_inc_w; + interface1_bank_bus_dat_r <= a7ddrphy_cdly_inc_w; end 3'd5: begin - vns_interface2_bank_bus_dat_r <= vns_csrbank2_dly_sel0_w; + interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; end 3'd6: begin - vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_rst_w; + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w; end 3'd7: begin - vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_inc_w; + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w; end 4'd8: begin - vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_rst_w; + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w; end 4'd9: begin - vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_w; + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w; end endcase end - if (vns_csrbank2_half_sys8x_taps0_re) begin - soc_a7ddrphy_half_sys8x_taps_storage[4:0] <= vns_csrbank2_half_sys8x_taps0_r; + if (csrbank1_half_sys8x_taps0_re) begin + a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r; end - soc_a7ddrphy_half_sys8x_taps_re <= vns_csrbank2_half_sys8x_taps0_re; - if (vns_csrbank2_wlevel_en0_re) begin - soc_a7ddrphy_wlevel_en_storage <= vns_csrbank2_wlevel_en0_r; + a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re; + if (csrbank1_wlevel_en0_re) begin + a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r; end - soc_a7ddrphy_wlevel_en_re <= vns_csrbank2_wlevel_en0_re; - if (vns_csrbank2_dly_sel0_re) begin - soc_a7ddrphy_dly_sel_storage[1:0] <= vns_csrbank2_dly_sel0_r; + a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re; + if (csrbank1_dly_sel0_re) begin + a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r; end - soc_a7ddrphy_dly_sel_re <= vns_csrbank2_dly_sel0_re; - vns_interface3_bank_bus_dat_r <= 1'd0; - if (vns_csrbank3_sel) begin - case (vns_interface3_bank_bus_adr[5:0]) + a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; + interface2_bank_bus_dat_r <= 1'd0; + if (csrbank2_sel) begin + case (interface2_bank_bus_adr[8:3]) 1'd0: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_control0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; end 1'd1: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_command0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; end 2'd2: begin - vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector0_command_issue_w; + interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_address1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address1_w; end 3'd4: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_address0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; end 3'd5: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_baddress0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; end 3'd6: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata3_w; end 3'd7: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata2_w; end 4'd8: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w; end 4'd9: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; end 4'd10: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata3_w; end 4'd11: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata2_w; end 4'd12: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w; end 4'd13: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w; end 4'd14: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_command0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; end 4'd15: begin - vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector1_command_issue_w; + interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; end 5'd16: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_address1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address1_w; end 5'd17: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_address0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; end 5'd18: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_baddress0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; end 5'd19: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata3_w; end 5'd20: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata2_w; end 5'd21: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w; end 5'd22: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; end 5'd23: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata3_w; end 5'd24: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata2_w; end 5'd25: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w; end 5'd26: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w; end 5'd27: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_command0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; end 5'd28: begin - vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector2_command_issue_w; + interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; end 5'd29: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_address1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address1_w; end 5'd30: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_address0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; end 5'd31: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_baddress0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; end 6'd32: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata3_w; end 6'd33: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata2_w; end 6'd34: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata1_w; end 6'd35: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; end 6'd36: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata3_w; end 6'd37: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata2_w; end 6'd38: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata1_w; end 6'd39: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata0_w; end 6'd40: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_command0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; end 6'd41: begin - vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector3_command_issue_w; + interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; end 6'd42: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_address1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address1_w; end 6'd43: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_address0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; end 6'd44: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_baddress0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; end 6'd45: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata3_w; end 6'd46: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata2_w; end 6'd47: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata1_w; end 6'd48: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; end 6'd49: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata3_w; end 6'd50: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata2_w; end 6'd51: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata1_w; end 6'd52: begin - vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata0_w; end endcase end - if (vns_csrbank3_dfii_control0_re) begin - soc_sdram_storage[3:0] <= vns_csrbank3_dfii_control0_r; - end - soc_sdram_re <= vns_csrbank3_dfii_control0_re; - if (vns_csrbank3_dfii_pi0_command0_re) begin - soc_sdram_phaseinjector0_command_storage[5:0] <= vns_csrbank3_dfii_pi0_command0_r; - end - soc_sdram_phaseinjector0_command_re <= vns_csrbank3_dfii_pi0_command0_re; - if (vns_csrbank3_dfii_pi0_address1_re) begin - soc_sdram_phaseinjector0_address_storage[14:8] <= vns_csrbank3_dfii_pi0_address1_r; - end - if (vns_csrbank3_dfii_pi0_address0_re) begin - soc_sdram_phaseinjector0_address_storage[7:0] <= vns_csrbank3_dfii_pi0_address0_r; - end - soc_sdram_phaseinjector0_address_re <= vns_csrbank3_dfii_pi0_address0_re; - if (vns_csrbank3_dfii_pi0_baddress0_re) begin - soc_sdram_phaseinjector0_baddress_storage[2:0] <= vns_csrbank3_dfii_pi0_baddress0_r; - end - soc_sdram_phaseinjector0_baddress_re <= vns_csrbank3_dfii_pi0_baddress0_re; - if (vns_csrbank3_dfii_pi0_wrdata3_re) begin - soc_sdram_phaseinjector0_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi0_wrdata3_r; - end - if (vns_csrbank3_dfii_pi0_wrdata2_re) begin - soc_sdram_phaseinjector0_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi0_wrdata2_r; - end - if (vns_csrbank3_dfii_pi0_wrdata1_re) begin - soc_sdram_phaseinjector0_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi0_wrdata1_r; - end - if (vns_csrbank3_dfii_pi0_wrdata0_re) begin - soc_sdram_phaseinjector0_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi0_wrdata0_r; + if (csrbank2_dfii_control0_re) begin + litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; end - soc_sdram_phaseinjector0_wrdata_re <= vns_csrbank3_dfii_pi0_wrdata0_re; - if (vns_csrbank3_dfii_pi1_command0_re) begin - soc_sdram_phaseinjector1_command_storage[5:0] <= vns_csrbank3_dfii_pi1_command0_r; + litedramcore_re <= csrbank2_dfii_control0_re; + if (csrbank2_dfii_pi0_command0_re) begin + litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; end - soc_sdram_phaseinjector1_command_re <= vns_csrbank3_dfii_pi1_command0_re; - if (vns_csrbank3_dfii_pi1_address1_re) begin - soc_sdram_phaseinjector1_address_storage[14:8] <= vns_csrbank3_dfii_pi1_address1_r; + litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; + if (csrbank2_dfii_pi0_address1_re) begin + litedramcore_phaseinjector0_address_storage[14:8] <= csrbank2_dfii_pi0_address1_r; end - if (vns_csrbank3_dfii_pi1_address0_re) begin - soc_sdram_phaseinjector1_address_storage[7:0] <= vns_csrbank3_dfii_pi1_address0_r; + if (csrbank2_dfii_pi0_address0_re) begin + litedramcore_phaseinjector0_address_storage[7:0] <= csrbank2_dfii_pi0_address0_r; end - soc_sdram_phaseinjector1_address_re <= vns_csrbank3_dfii_pi1_address0_re; - if (vns_csrbank3_dfii_pi1_baddress0_re) begin - soc_sdram_phaseinjector1_baddress_storage[2:0] <= vns_csrbank3_dfii_pi1_baddress0_r; + litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; + if (csrbank2_dfii_pi0_baddress0_re) begin + litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; end - soc_sdram_phaseinjector1_baddress_re <= vns_csrbank3_dfii_pi1_baddress0_re; - if (vns_csrbank3_dfii_pi1_wrdata3_re) begin - soc_sdram_phaseinjector1_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi1_wrdata3_r; + litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; + if (csrbank2_dfii_pi0_wrdata3_re) begin + litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank2_dfii_pi0_wrdata3_r; end - if (vns_csrbank3_dfii_pi1_wrdata2_re) begin - soc_sdram_phaseinjector1_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi1_wrdata2_r; + if (csrbank2_dfii_pi0_wrdata2_re) begin + litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank2_dfii_pi0_wrdata2_r; end - if (vns_csrbank3_dfii_pi1_wrdata1_re) begin - soc_sdram_phaseinjector1_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi1_wrdata1_r; + if (csrbank2_dfii_pi0_wrdata1_re) begin + litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank2_dfii_pi0_wrdata1_r; end - if (vns_csrbank3_dfii_pi1_wrdata0_re) begin - soc_sdram_phaseinjector1_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi1_wrdata0_r; + if (csrbank2_dfii_pi0_wrdata0_re) begin + litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank2_dfii_pi0_wrdata0_r; end - soc_sdram_phaseinjector1_wrdata_re <= vns_csrbank3_dfii_pi1_wrdata0_re; - if (vns_csrbank3_dfii_pi2_command0_re) begin - soc_sdram_phaseinjector2_command_storage[5:0] <= vns_csrbank3_dfii_pi2_command0_r; + litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; + if (csrbank2_dfii_pi1_command0_re) begin + litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; end - soc_sdram_phaseinjector2_command_re <= vns_csrbank3_dfii_pi2_command0_re; - if (vns_csrbank3_dfii_pi2_address1_re) begin - soc_sdram_phaseinjector2_address_storage[14:8] <= vns_csrbank3_dfii_pi2_address1_r; + litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; + if (csrbank2_dfii_pi1_address1_re) begin + litedramcore_phaseinjector1_address_storage[14:8] <= csrbank2_dfii_pi1_address1_r; end - if (vns_csrbank3_dfii_pi2_address0_re) begin - soc_sdram_phaseinjector2_address_storage[7:0] <= vns_csrbank3_dfii_pi2_address0_r; + if (csrbank2_dfii_pi1_address0_re) begin + litedramcore_phaseinjector1_address_storage[7:0] <= csrbank2_dfii_pi1_address0_r; end - soc_sdram_phaseinjector2_address_re <= vns_csrbank3_dfii_pi2_address0_re; - if (vns_csrbank3_dfii_pi2_baddress0_re) begin - soc_sdram_phaseinjector2_baddress_storage[2:0] <= vns_csrbank3_dfii_pi2_baddress0_r; + litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; + if (csrbank2_dfii_pi1_baddress0_re) begin + litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; end - soc_sdram_phaseinjector2_baddress_re <= vns_csrbank3_dfii_pi2_baddress0_re; - if (vns_csrbank3_dfii_pi2_wrdata3_re) begin - soc_sdram_phaseinjector2_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi2_wrdata3_r; + litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; + if (csrbank2_dfii_pi1_wrdata3_re) begin + litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank2_dfii_pi1_wrdata3_r; end - if (vns_csrbank3_dfii_pi2_wrdata2_re) begin - soc_sdram_phaseinjector2_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi2_wrdata2_r; - end - if (vns_csrbank3_dfii_pi2_wrdata1_re) begin - soc_sdram_phaseinjector2_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi2_wrdata1_r; - end - if (vns_csrbank3_dfii_pi2_wrdata0_re) begin - soc_sdram_phaseinjector2_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi2_wrdata0_r; - end - soc_sdram_phaseinjector2_wrdata_re <= vns_csrbank3_dfii_pi2_wrdata0_re; - if (vns_csrbank3_dfii_pi3_command0_re) begin - soc_sdram_phaseinjector3_command_storage[5:0] <= vns_csrbank3_dfii_pi3_command0_r; - end - soc_sdram_phaseinjector3_command_re <= vns_csrbank3_dfii_pi3_command0_re; - if (vns_csrbank3_dfii_pi3_address1_re) begin - soc_sdram_phaseinjector3_address_storage[14:8] <= vns_csrbank3_dfii_pi3_address1_r; - end - if (vns_csrbank3_dfii_pi3_address0_re) begin - soc_sdram_phaseinjector3_address_storage[7:0] <= vns_csrbank3_dfii_pi3_address0_r; - end - soc_sdram_phaseinjector3_address_re <= vns_csrbank3_dfii_pi3_address0_re; - if (vns_csrbank3_dfii_pi3_baddress0_re) begin - soc_sdram_phaseinjector3_baddress_storage[2:0] <= vns_csrbank3_dfii_pi3_baddress0_r; - end - soc_sdram_phaseinjector3_baddress_re <= vns_csrbank3_dfii_pi3_baddress0_re; - if (vns_csrbank3_dfii_pi3_wrdata3_re) begin - soc_sdram_phaseinjector3_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi3_wrdata3_r; - end - if (vns_csrbank3_dfii_pi3_wrdata2_re) begin - soc_sdram_phaseinjector3_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi3_wrdata2_r; - end - if (vns_csrbank3_dfii_pi3_wrdata1_re) begin - soc_sdram_phaseinjector3_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi3_wrdata1_r; - end - if (vns_csrbank3_dfii_pi3_wrdata0_re) begin - soc_sdram_phaseinjector3_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi3_wrdata0_r; - end - soc_sdram_phaseinjector3_wrdata_re <= vns_csrbank3_dfii_pi3_wrdata0_re; - vns_interface4_bank_bus_dat_r <= 1'd0; - if (vns_csrbank4_sel) begin - case (vns_interface4_bank_bus_adr[4:0]) - 1'd0: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_load3_w; - end - 1'd1: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_load2_w; - end - 2'd2: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_load1_w; - end - 2'd3: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_load0_w; - end - 3'd4: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload3_w; - end - 3'd5: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload2_w; - end - 3'd6: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload1_w; - end - 3'd7: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload0_w; - end - 4'd8: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_en0_w; - end - 4'd9: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_update_value0_w; - end - 4'd10: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_value3_w; - end - 4'd11: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_value2_w; - end - 4'd12: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_value1_w; - end - 4'd13: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_value0_w; - end - 4'd14: begin - vns_interface4_bank_bus_dat_r <= soc_litedramcore_timer_eventmanager_status_w; - end - 4'd15: begin - vns_interface4_bank_bus_dat_r <= soc_litedramcore_timer_eventmanager_pending_w; - end - 5'd16: begin - vns_interface4_bank_bus_dat_r <= vns_csrbank4_ev_enable0_w; - end - endcase + if (csrbank2_dfii_pi1_wrdata2_re) begin + litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank2_dfii_pi1_wrdata2_r; end - if (vns_csrbank4_load3_re) begin - soc_litedramcore_timer_load_storage[31:24] <= vns_csrbank4_load3_r; + if (csrbank2_dfii_pi1_wrdata1_re) begin + litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank2_dfii_pi1_wrdata1_r; end - if (vns_csrbank4_load2_re) begin - soc_litedramcore_timer_load_storage[23:16] <= vns_csrbank4_load2_r; + if (csrbank2_dfii_pi1_wrdata0_re) begin + litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank2_dfii_pi1_wrdata0_r; end - if (vns_csrbank4_load1_re) begin - soc_litedramcore_timer_load_storage[15:8] <= vns_csrbank4_load1_r; + litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; + if (csrbank2_dfii_pi2_command0_re) begin + litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; end - if (vns_csrbank4_load0_re) begin - soc_litedramcore_timer_load_storage[7:0] <= vns_csrbank4_load0_r; + litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; + if (csrbank2_dfii_pi2_address1_re) begin + litedramcore_phaseinjector2_address_storage[14:8] <= csrbank2_dfii_pi2_address1_r; end - soc_litedramcore_timer_load_re <= vns_csrbank4_load0_re; - if (vns_csrbank4_reload3_re) begin - soc_litedramcore_timer_reload_storage[31:24] <= vns_csrbank4_reload3_r; + if (csrbank2_dfii_pi2_address0_re) begin + litedramcore_phaseinjector2_address_storage[7:0] <= csrbank2_dfii_pi2_address0_r; end - if (vns_csrbank4_reload2_re) begin - soc_litedramcore_timer_reload_storage[23:16] <= vns_csrbank4_reload2_r; + litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; + if (csrbank2_dfii_pi2_baddress0_re) begin + litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; end - if (vns_csrbank4_reload1_re) begin - soc_litedramcore_timer_reload_storage[15:8] <= vns_csrbank4_reload1_r; + litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; + if (csrbank2_dfii_pi2_wrdata3_re) begin + litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank2_dfii_pi2_wrdata3_r; end - if (vns_csrbank4_reload0_re) begin - soc_litedramcore_timer_reload_storage[7:0] <= vns_csrbank4_reload0_r; + if (csrbank2_dfii_pi2_wrdata2_re) begin + litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank2_dfii_pi2_wrdata2_r; end - soc_litedramcore_timer_reload_re <= vns_csrbank4_reload0_re; - if (vns_csrbank4_en0_re) begin - soc_litedramcore_timer_en_storage <= vns_csrbank4_en0_r; + if (csrbank2_dfii_pi2_wrdata1_re) begin + litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank2_dfii_pi2_wrdata1_r; end - soc_litedramcore_timer_en_re <= vns_csrbank4_en0_re; - if (vns_csrbank4_update_value0_re) begin - soc_litedramcore_timer_update_value_storage <= vns_csrbank4_update_value0_r; + if (csrbank2_dfii_pi2_wrdata0_re) begin + litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank2_dfii_pi2_wrdata0_r; end - soc_litedramcore_timer_update_value_re <= vns_csrbank4_update_value0_re; - if (vns_csrbank4_ev_enable0_re) begin - soc_litedramcore_timer_eventmanager_storage <= vns_csrbank4_ev_enable0_r; + litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; + if (csrbank2_dfii_pi3_command0_re) begin + litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; end - soc_litedramcore_timer_eventmanager_re <= vns_csrbank4_ev_enable0_re; - vns_interface5_bank_bus_dat_r <= 1'd0; - if (vns_csrbank5_sel) begin - case (vns_interface5_bank_bus_adr[2:0]) - 1'd0: begin - vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_rxtx_w; - end - 1'd1: begin - vns_interface5_bank_bus_dat_r <= vns_csrbank5_txfull_w; - end - 2'd2: begin - vns_interface5_bank_bus_dat_r <= vns_csrbank5_rxempty_w; - end - 2'd3: begin - vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_eventmanager_status_w; - end - 3'd4: begin - vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_eventmanager_pending_w; - end - 3'd5: begin - vns_interface5_bank_bus_dat_r <= vns_csrbank5_ev_enable0_w; - end - endcase + litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; + if (csrbank2_dfii_pi3_address1_re) begin + litedramcore_phaseinjector3_address_storage[14:8] <= csrbank2_dfii_pi3_address1_r; end - if (vns_csrbank5_ev_enable0_re) begin - soc_litedramcore_uart_eventmanager_storage[1:0] <= vns_csrbank5_ev_enable0_r; + if (csrbank2_dfii_pi3_address0_re) begin + litedramcore_phaseinjector3_address_storage[7:0] <= csrbank2_dfii_pi3_address0_r; end - soc_litedramcore_uart_eventmanager_re <= vns_csrbank5_ev_enable0_re; - vns_interface6_bank_bus_dat_r <= 1'd0; - if (vns_csrbank6_sel) begin - case (vns_interface6_bank_bus_adr[1:0]) - 1'd0: begin - vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word3_w; - end - 1'd1: begin - vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word2_w; - end - 2'd2: begin - vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word1_w; - end - 2'd3: begin - vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word0_w; - end - endcase + litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; + if (csrbank2_dfii_pi3_baddress0_re) begin + litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; end - if (vns_csrbank6_tuning_word3_re) begin - soc_litedramcore_storage[31:24] <= vns_csrbank6_tuning_word3_r; + litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; + if (csrbank2_dfii_pi3_wrdata3_re) begin + litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank2_dfii_pi3_wrdata3_r; end - if (vns_csrbank6_tuning_word2_re) begin - soc_litedramcore_storage[23:16] <= vns_csrbank6_tuning_word2_r; + if (csrbank2_dfii_pi3_wrdata2_re) begin + litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank2_dfii_pi3_wrdata2_r; end - if (vns_csrbank6_tuning_word1_re) begin - soc_litedramcore_storage[15:8] <= vns_csrbank6_tuning_word1_r; + if (csrbank2_dfii_pi3_wrdata1_re) begin + litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank2_dfii_pi3_wrdata1_r; end - if (vns_csrbank6_tuning_word0_re) begin - soc_litedramcore_storage[7:0] <= vns_csrbank6_tuning_word0_r; + if (csrbank2_dfii_pi3_wrdata0_re) begin + litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank2_dfii_pi3_wrdata0_r; end - soc_litedramcore_re <= vns_csrbank6_tuning_word0_re; + litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; if (sys_rst) begin - soc_litedramcore_soccontroller_reset_storage <= 1'd0; - soc_litedramcore_soccontroller_reset_re <= 1'd0; - soc_litedramcore_soccontroller_scratch_storage <= 32'd305419896; - soc_litedramcore_soccontroller_scratch_re <= 1'd0; - soc_litedramcore_soccontroller_bus_errors <= 32'd0; - soc_litedramcore_litedramcore_ram_bus_ack <= 1'd0; - soc_litedramcore_ram_bus_ram_bus_ack <= 1'd0; - serial_tx <= 1'd1; - soc_litedramcore_storage <= 32'd4947802; - soc_litedramcore_re <= 1'd0; - soc_litedramcore_sink_ready <= 1'd0; - soc_litedramcore_uart_clk_txen <= 1'd0; - soc_litedramcore_tx_busy <= 1'd0; - soc_litedramcore_source_valid <= 1'd0; - soc_litedramcore_uart_clk_rxen <= 1'd0; - soc_litedramcore_rx_r <= 1'd0; - soc_litedramcore_rx_busy <= 1'd0; - soc_litedramcore_uart_tx_pending <= 1'd0; - soc_litedramcore_uart_tx_old_trigger <= 1'd0; - soc_litedramcore_uart_rx_pending <= 1'd0; - soc_litedramcore_uart_rx_old_trigger <= 1'd0; - soc_litedramcore_uart_eventmanager_storage <= 2'd0; - soc_litedramcore_uart_eventmanager_re <= 1'd0; - soc_litedramcore_uart_tx_fifo_readable <= 1'd0; - soc_litedramcore_uart_tx_fifo_level0 <= 5'd0; - soc_litedramcore_uart_tx_fifo_produce <= 4'd0; - soc_litedramcore_uart_tx_fifo_consume <= 4'd0; - soc_litedramcore_uart_rx_fifo_readable <= 1'd0; - soc_litedramcore_uart_rx_fifo_level0 <= 5'd0; - soc_litedramcore_uart_rx_fifo_produce <= 4'd0; - soc_litedramcore_uart_rx_fifo_consume <= 4'd0; - soc_litedramcore_timer_load_storage <= 32'd0; - soc_litedramcore_timer_load_re <= 1'd0; - soc_litedramcore_timer_reload_storage <= 32'd0; - soc_litedramcore_timer_reload_re <= 1'd0; - soc_litedramcore_timer_en_storage <= 1'd0; - soc_litedramcore_timer_en_re <= 1'd0; - soc_litedramcore_timer_update_value_storage <= 1'd0; - soc_litedramcore_timer_update_value_re <= 1'd0; - soc_litedramcore_timer_value_status <= 32'd0; - soc_litedramcore_timer_zero_pending <= 1'd0; - soc_litedramcore_timer_zero_old_trigger <= 1'd0; - soc_litedramcore_timer_eventmanager_storage <= 1'd0; - soc_litedramcore_timer_eventmanager_re <= 1'd0; - soc_litedramcore_timer_value <= 32'd0; - soc_a7ddrphy_half_sys8x_taps_storage <= 5'd8; - soc_a7ddrphy_half_sys8x_taps_re <= 1'd0; - soc_a7ddrphy_wlevel_en_storage <= 1'd0; - soc_a7ddrphy_wlevel_en_re <= 1'd0; - soc_a7ddrphy_dly_sel_storage <= 2'd0; - soc_a7ddrphy_dly_sel_re <= 1'd0; - soc_a7ddrphy_dfi_p0_rddata_valid <= 1'd0; - soc_a7ddrphy_dfi_p1_rddata_valid <= 1'd0; - soc_a7ddrphy_dfi_p2_rddata_valid <= 1'd0; - soc_a7ddrphy_dfi_p3_rddata_valid <= 1'd0; - soc_a7ddrphy_dqs_oe_delayed <= 1'd0; - soc_a7ddrphy_dqspattern_o1 <= 8'd0; - soc_a7ddrphy_dq_oe_delayed <= 1'd0; - soc_a7ddrphy_bitslip0_value <= 3'd0; - soc_a7ddrphy_bitslip1_value <= 3'd0; - soc_a7ddrphy_bitslip2_value <= 3'd0; - soc_a7ddrphy_bitslip3_value <= 3'd0; - soc_a7ddrphy_bitslip4_value <= 3'd0; - soc_a7ddrphy_bitslip5_value <= 3'd0; - soc_a7ddrphy_bitslip6_value <= 3'd0; - soc_a7ddrphy_bitslip7_value <= 3'd0; - soc_a7ddrphy_bitslip8_value <= 3'd0; - soc_a7ddrphy_bitslip9_value <= 3'd0; - soc_a7ddrphy_bitslip10_value <= 3'd0; - soc_a7ddrphy_bitslip11_value <= 3'd0; - soc_a7ddrphy_bitslip12_value <= 3'd0; - soc_a7ddrphy_bitslip13_value <= 3'd0; - soc_a7ddrphy_bitslip14_value <= 3'd0; - soc_a7ddrphy_bitslip15_value <= 3'd0; - soc_a7ddrphy_rddata_en_last <= 8'd0; - soc_a7ddrphy_wrdata_en_last <= 4'd0; - soc_sdram_storage <= 4'd0; - soc_sdram_re <= 1'd0; - soc_sdram_phaseinjector0_command_storage <= 6'd0; - soc_sdram_phaseinjector0_command_re <= 1'd0; - soc_sdram_phaseinjector0_address_re <= 1'd0; - soc_sdram_phaseinjector0_baddress_re <= 1'd0; - soc_sdram_phaseinjector0_wrdata_re <= 1'd0; - soc_sdram_phaseinjector0_status <= 32'd0; - soc_sdram_phaseinjector1_command_storage <= 6'd0; - soc_sdram_phaseinjector1_command_re <= 1'd0; - soc_sdram_phaseinjector1_address_re <= 1'd0; - soc_sdram_phaseinjector1_baddress_re <= 1'd0; - soc_sdram_phaseinjector1_wrdata_re <= 1'd0; - soc_sdram_phaseinjector1_status <= 32'd0; - soc_sdram_phaseinjector2_command_storage <= 6'd0; - soc_sdram_phaseinjector2_command_re <= 1'd0; - soc_sdram_phaseinjector2_address_re <= 1'd0; - soc_sdram_phaseinjector2_baddress_re <= 1'd0; - soc_sdram_phaseinjector2_wrdata_re <= 1'd0; - soc_sdram_phaseinjector2_status <= 32'd0; - soc_sdram_phaseinjector3_command_storage <= 6'd0; - soc_sdram_phaseinjector3_command_re <= 1'd0; - soc_sdram_phaseinjector3_address_re <= 1'd0; - soc_sdram_phaseinjector3_baddress_re <= 1'd0; - soc_sdram_phaseinjector3_wrdata_re <= 1'd0; - soc_sdram_phaseinjector3_status <= 32'd0; - soc_sdram_dfi_p0_address <= 15'd0; - soc_sdram_dfi_p0_bank <= 3'd0; - soc_sdram_dfi_p0_cas_n <= 1'd1; - soc_sdram_dfi_p0_cs_n <= 1'd1; - soc_sdram_dfi_p0_ras_n <= 1'd1; - soc_sdram_dfi_p0_we_n <= 1'd1; - soc_sdram_dfi_p0_wrdata_en <= 1'd0; - soc_sdram_dfi_p0_rddata_en <= 1'd0; - soc_sdram_dfi_p1_address <= 15'd0; - soc_sdram_dfi_p1_bank <= 3'd0; - soc_sdram_dfi_p1_cas_n <= 1'd1; - soc_sdram_dfi_p1_cs_n <= 1'd1; - soc_sdram_dfi_p1_ras_n <= 1'd1; - soc_sdram_dfi_p1_we_n <= 1'd1; - soc_sdram_dfi_p1_wrdata_en <= 1'd0; - soc_sdram_dfi_p1_rddata_en <= 1'd0; - soc_sdram_dfi_p2_address <= 15'd0; - soc_sdram_dfi_p2_bank <= 3'd0; - soc_sdram_dfi_p2_cas_n <= 1'd1; - soc_sdram_dfi_p2_cs_n <= 1'd1; - soc_sdram_dfi_p2_ras_n <= 1'd1; - soc_sdram_dfi_p2_we_n <= 1'd1; - soc_sdram_dfi_p2_wrdata_en <= 1'd0; - soc_sdram_dfi_p2_rddata_en <= 1'd0; - soc_sdram_dfi_p3_address <= 15'd0; - soc_sdram_dfi_p3_bank <= 3'd0; - soc_sdram_dfi_p3_cas_n <= 1'd1; - soc_sdram_dfi_p3_cs_n <= 1'd1; - soc_sdram_dfi_p3_ras_n <= 1'd1; - soc_sdram_dfi_p3_we_n <= 1'd1; - soc_sdram_dfi_p3_wrdata_en <= 1'd0; - soc_sdram_dfi_p3_rddata_en <= 1'd0; - soc_sdram_timer_count1 <= 10'd781; - soc_sdram_postponer_req_o <= 1'd0; - soc_sdram_postponer_count <= 1'd0; - soc_sdram_sequencer_done1 <= 1'd0; - soc_sdram_sequencer_counter <= 6'd0; - soc_sdram_sequencer_count <= 1'd0; - soc_sdram_zqcs_timer_count1 <= 27'd99999999; - soc_sdram_zqcs_executer_done <= 1'd0; - soc_sdram_zqcs_executer_counter <= 5'd0; - soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; - soc_sdram_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; - soc_sdram_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; - soc_sdram_bankmachine0_cmd_buffer_source_valid <= 1'd0; - soc_sdram_bankmachine0_row <= 15'd0; - soc_sdram_bankmachine0_row_opened <= 1'd0; - soc_sdram_bankmachine0_twtpcon_ready <= 1'd1; - soc_sdram_bankmachine0_twtpcon_count <= 3'd0; - soc_sdram_bankmachine0_trccon_ready <= 1'd1; - soc_sdram_bankmachine0_trccon_count <= 3'd0; - soc_sdram_bankmachine0_trascon_ready <= 1'd1; - soc_sdram_bankmachine0_trascon_count <= 3'd0; - soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; - soc_sdram_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; - soc_sdram_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; - soc_sdram_bankmachine1_cmd_buffer_source_valid <= 1'd0; - soc_sdram_bankmachine1_row <= 15'd0; - soc_sdram_bankmachine1_row_opened <= 1'd0; - soc_sdram_bankmachine1_twtpcon_ready <= 1'd1; - soc_sdram_bankmachine1_twtpcon_count <= 3'd0; - soc_sdram_bankmachine1_trccon_ready <= 1'd1; - soc_sdram_bankmachine1_trccon_count <= 3'd0; - soc_sdram_bankmachine1_trascon_ready <= 1'd1; - soc_sdram_bankmachine1_trascon_count <= 3'd0; - soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; - soc_sdram_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; - soc_sdram_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; - soc_sdram_bankmachine2_cmd_buffer_source_valid <= 1'd0; - soc_sdram_bankmachine2_row <= 15'd0; - soc_sdram_bankmachine2_row_opened <= 1'd0; - soc_sdram_bankmachine2_twtpcon_ready <= 1'd1; - soc_sdram_bankmachine2_twtpcon_count <= 3'd0; - soc_sdram_bankmachine2_trccon_ready <= 1'd1; - soc_sdram_bankmachine2_trccon_count <= 3'd0; - soc_sdram_bankmachine2_trascon_ready <= 1'd1; - soc_sdram_bankmachine2_trascon_count <= 3'd0; - soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; - soc_sdram_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; - soc_sdram_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; - soc_sdram_bankmachine3_cmd_buffer_source_valid <= 1'd0; - soc_sdram_bankmachine3_row <= 15'd0; - soc_sdram_bankmachine3_row_opened <= 1'd0; - soc_sdram_bankmachine3_twtpcon_ready <= 1'd1; - soc_sdram_bankmachine3_twtpcon_count <= 3'd0; - soc_sdram_bankmachine3_trccon_ready <= 1'd1; - soc_sdram_bankmachine3_trccon_count <= 3'd0; - soc_sdram_bankmachine3_trascon_ready <= 1'd1; - soc_sdram_bankmachine3_trascon_count <= 3'd0; - soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; - soc_sdram_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; - soc_sdram_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; - soc_sdram_bankmachine4_cmd_buffer_source_valid <= 1'd0; - soc_sdram_bankmachine4_row <= 15'd0; - soc_sdram_bankmachine4_row_opened <= 1'd0; - soc_sdram_bankmachine4_twtpcon_ready <= 1'd1; - soc_sdram_bankmachine4_twtpcon_count <= 3'd0; - soc_sdram_bankmachine4_trccon_ready <= 1'd1; - soc_sdram_bankmachine4_trccon_count <= 3'd0; - soc_sdram_bankmachine4_trascon_ready <= 1'd1; - soc_sdram_bankmachine4_trascon_count <= 3'd0; - soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; - soc_sdram_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; - soc_sdram_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; - soc_sdram_bankmachine5_cmd_buffer_source_valid <= 1'd0; - soc_sdram_bankmachine5_row <= 15'd0; - soc_sdram_bankmachine5_row_opened <= 1'd0; - soc_sdram_bankmachine5_twtpcon_ready <= 1'd1; - soc_sdram_bankmachine5_twtpcon_count <= 3'd0; - soc_sdram_bankmachine5_trccon_ready <= 1'd1; - soc_sdram_bankmachine5_trccon_count <= 3'd0; - soc_sdram_bankmachine5_trascon_ready <= 1'd1; - soc_sdram_bankmachine5_trascon_count <= 3'd0; - soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; - soc_sdram_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; - soc_sdram_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; - soc_sdram_bankmachine6_cmd_buffer_source_valid <= 1'd0; - soc_sdram_bankmachine6_row <= 15'd0; - soc_sdram_bankmachine6_row_opened <= 1'd0; - soc_sdram_bankmachine6_twtpcon_ready <= 1'd1; - soc_sdram_bankmachine6_twtpcon_count <= 3'd0; - soc_sdram_bankmachine6_trccon_ready <= 1'd1; - soc_sdram_bankmachine6_trccon_count <= 3'd0; - soc_sdram_bankmachine6_trascon_ready <= 1'd1; - soc_sdram_bankmachine6_trascon_count <= 3'd0; - soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; - soc_sdram_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; - soc_sdram_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; - soc_sdram_bankmachine7_cmd_buffer_source_valid <= 1'd0; - soc_sdram_bankmachine7_row <= 15'd0; - soc_sdram_bankmachine7_row_opened <= 1'd0; - soc_sdram_bankmachine7_twtpcon_ready <= 1'd1; - soc_sdram_bankmachine7_twtpcon_count <= 3'd0; - soc_sdram_bankmachine7_trccon_ready <= 1'd1; - soc_sdram_bankmachine7_trccon_count <= 3'd0; - soc_sdram_bankmachine7_trascon_ready <= 1'd1; - soc_sdram_bankmachine7_trascon_count <= 3'd0; - soc_sdram_choose_cmd_grant <= 3'd0; - soc_sdram_choose_req_grant <= 3'd0; - soc_sdram_trrdcon_ready <= 1'd1; - soc_sdram_trrdcon_count <= 1'd0; - soc_sdram_tfawcon_ready <= 1'd1; - soc_sdram_tfawcon_window <= 5'd0; - soc_sdram_tccdcon_ready <= 1'd1; - soc_sdram_tccdcon_count <= 1'd0; - soc_sdram_twtrcon_ready <= 1'd1; - soc_sdram_twtrcon_count <= 3'd0; - soc_sdram_time0 <= 5'd0; - soc_sdram_time1 <= 4'd0; - soc_address_q <= 30'd0; - soc_counter <= 2'd0; - soc_need_refill_q <= 1'd1; - soc_cached_datas_flipflop0_q <= 32'd0; - soc_cached_datas_flipflop1_q <= 32'd0; - soc_cached_datas_flipflop2_q <= 32'd0; - soc_cached_datas_flipflop3_q <= 32'd0; - soc_cached_sels_flipflop0_q <= 4'd0; - soc_cached_sels_flipflop1_q <= 4'd0; - soc_cached_sels_flipflop2_q <= 4'd0; - soc_cached_sels_flipflop3_q <= 4'd0; - soc_count <= 1'd0; - soc_init_done_storage <= 1'd0; - soc_init_done_re <= 1'd0; - soc_init_error_storage <= 1'd0; - soc_init_error_re <= 1'd0; - vns_wb2csr_state <= 1'd0; - vns_refresher_state <= 2'd0; - vns_bankmachine0_state <= 4'd0; - vns_bankmachine1_state <= 4'd0; - vns_bankmachine2_state <= 4'd0; - vns_bankmachine3_state <= 4'd0; - vns_bankmachine4_state <= 4'd0; - vns_bankmachine5_state <= 4'd0; - vns_bankmachine6_state <= 4'd0; - vns_bankmachine7_state <= 4'd0; - vns_multiplexer_state <= 4'd0; - vns_roundrobin0_grant <= 1'd0; - vns_roundrobin1_grant <= 1'd0; - vns_roundrobin2_grant <= 1'd0; - vns_roundrobin3_grant <= 1'd0; - vns_roundrobin4_grant <= 1'd0; - vns_roundrobin5_grant <= 1'd0; - vns_roundrobin6_grant <= 1'd0; - vns_roundrobin7_grant <= 1'd0; - vns_new_master_wdata_ready0 <= 1'd0; - vns_new_master_wdata_ready1 <= 1'd0; - vns_new_master_wdata_ready2 <= 1'd0; - vns_new_master_wdata_ready3 <= 1'd0; - vns_new_master_wdata_ready4 <= 1'd0; - vns_new_master_wdata_ready5 <= 1'd0; - vns_new_master_rdata_valid0 <= 1'd0; - vns_new_master_rdata_valid1 <= 1'd0; - vns_new_master_rdata_valid2 <= 1'd0; - vns_new_master_rdata_valid3 <= 1'd0; - vns_new_master_rdata_valid4 <= 1'd0; - vns_new_master_rdata_valid5 <= 1'd0; - vns_new_master_rdata_valid6 <= 1'd0; - vns_new_master_rdata_valid7 <= 1'd0; - vns_new_master_rdata_valid8 <= 1'd0; - vns_new_master_rdata_valid9 <= 1'd0; - vns_new_master_rdata_valid10 <= 1'd0; - vns_new_master_rdata_valid11 <= 1'd0; - vns_new_master_rdata_valid12 <= 1'd0; - vns_new_master_rdata_valid13 <= 1'd0; - vns_new_master_rdata_valid14 <= 1'd0; - vns_new_master_rdata_valid15 <= 1'd0; - vns_new_master_rdata_valid16 <= 1'd0; - vns_new_master_rdata_valid17 <= 1'd0; - vns_converter_state <= 3'd0; - vns_litedramwishbone2native_state <= 2'd0; - vns_grant <= 1'd0; - vns_slave_sel_r <= 4'd0; - vns_count <= 20'd1000000; - end - vns_regs0 <= serial_rx; - vns_regs1 <= vns_regs0; -end - -reg [31:0] mem[0:6143]; -reg [31:0] memdat; -always @(posedge sys_clk) begin - memdat <= mem[soc_litedramcore_litedramcore_adr]; -end - -assign soc_litedramcore_litedramcore_dat_r = memdat; - -initial begin - $readmemh("litedram_core.init", mem); -end - -reg [31:0] mem_1[0:1023]; -reg [9:0] memadr; -always @(posedge sys_clk) begin - if (soc_litedramcore_ram_we[0]) - mem_1[soc_litedramcore_ram_adr][7:0] <= soc_litedramcore_ram_dat_w[7:0]; - if (soc_litedramcore_ram_we[1]) - mem_1[soc_litedramcore_ram_adr][15:8] <= soc_litedramcore_ram_dat_w[15:8]; - if (soc_litedramcore_ram_we[2]) - mem_1[soc_litedramcore_ram_adr][23:16] <= soc_litedramcore_ram_dat_w[23:16]; - if (soc_litedramcore_ram_we[3]) - mem_1[soc_litedramcore_ram_adr][31:24] <= soc_litedramcore_ram_dat_w[31:24]; - memadr <= soc_litedramcore_ram_adr; -end - -assign soc_litedramcore_ram_dat_r = mem_1[memadr]; - -initial begin - $readmemh("mem_1.init", mem_1); -end - -reg [9:0] storage[0:15]; -reg [9:0] memdat_1; -reg [9:0] memdat_2; -always @(posedge sys_clk) begin - if (soc_litedramcore_uart_tx_fifo_wrport_we) - storage[soc_litedramcore_uart_tx_fifo_wrport_adr] <= soc_litedramcore_uart_tx_fifo_wrport_dat_w; - memdat_1 <= storage[soc_litedramcore_uart_tx_fifo_wrport_adr]; -end - -always @(posedge sys_clk) begin - if (soc_litedramcore_uart_tx_fifo_rdport_re) - memdat_2 <= storage[soc_litedramcore_uart_tx_fifo_rdport_adr]; -end - -assign soc_litedramcore_uart_tx_fifo_wrport_dat_r = memdat_1; -assign soc_litedramcore_uart_tx_fifo_rdport_dat_r = memdat_2; - -reg [9:0] storage_1[0:15]; -reg [9:0] memdat_3; -reg [9:0] memdat_4; -always @(posedge sys_clk) begin - if (soc_litedramcore_uart_rx_fifo_wrport_we) - storage_1[soc_litedramcore_uart_rx_fifo_wrport_adr] <= soc_litedramcore_uart_rx_fifo_wrport_dat_w; - memdat_3 <= storage_1[soc_litedramcore_uart_rx_fifo_wrport_adr]; -end - -always @(posedge sys_clk) begin - if (soc_litedramcore_uart_rx_fifo_rdport_re) - memdat_4 <= storage_1[soc_litedramcore_uart_rx_fifo_rdport_adr]; + a7ddrphy_half_sys8x_taps_storage <= 5'd8; + a7ddrphy_half_sys8x_taps_re <= 1'd0; + a7ddrphy_wlevel_en_storage <= 1'd0; + a7ddrphy_wlevel_en_re <= 1'd0; + a7ddrphy_dly_sel_storage <= 2'd0; + a7ddrphy_dly_sel_re <= 1'd0; + a7ddrphy_dfi_p0_rddata_valid <= 1'd0; + a7ddrphy_dfi_p1_rddata_valid <= 1'd0; + a7ddrphy_dfi_p2_rddata_valid <= 1'd0; + a7ddrphy_dfi_p3_rddata_valid <= 1'd0; + a7ddrphy_dqs_oe_delayed <= 1'd0; + a7ddrphy_dqspattern_o1 <= 8'd0; + a7ddrphy_dq_oe_delayed <= 1'd0; + a7ddrphy_bitslip0_value <= 3'd0; + a7ddrphy_bitslip1_value <= 3'd0; + a7ddrphy_bitslip2_value <= 3'd0; + a7ddrphy_bitslip3_value <= 3'd0; + a7ddrphy_bitslip4_value <= 3'd0; + a7ddrphy_bitslip5_value <= 3'd0; + a7ddrphy_bitslip6_value <= 3'd0; + a7ddrphy_bitslip7_value <= 3'd0; + a7ddrphy_bitslip8_value <= 3'd0; + a7ddrphy_bitslip9_value <= 3'd0; + a7ddrphy_bitslip10_value <= 3'd0; + a7ddrphy_bitslip11_value <= 3'd0; + a7ddrphy_bitslip12_value <= 3'd0; + a7ddrphy_bitslip13_value <= 3'd0; + a7ddrphy_bitslip14_value <= 3'd0; + a7ddrphy_bitslip15_value <= 3'd0; + a7ddrphy_rddata_en_last <= 8'd0; + a7ddrphy_wrdata_en_last <= 4'd0; + litedramcore_storage <= 4'd0; + litedramcore_re <= 1'd0; + litedramcore_phaseinjector0_command_storage <= 6'd0; + litedramcore_phaseinjector0_command_re <= 1'd0; + litedramcore_phaseinjector0_address_re <= 1'd0; + litedramcore_phaseinjector0_baddress_re <= 1'd0; + litedramcore_phaseinjector0_wrdata_re <= 1'd0; + litedramcore_phaseinjector0_status <= 32'd0; + litedramcore_phaseinjector1_command_storage <= 6'd0; + litedramcore_phaseinjector1_command_re <= 1'd0; + litedramcore_phaseinjector1_address_re <= 1'd0; + litedramcore_phaseinjector1_baddress_re <= 1'd0; + litedramcore_phaseinjector1_wrdata_re <= 1'd0; + litedramcore_phaseinjector1_status <= 32'd0; + litedramcore_phaseinjector2_command_storage <= 6'd0; + litedramcore_phaseinjector2_command_re <= 1'd0; + litedramcore_phaseinjector2_address_re <= 1'd0; + litedramcore_phaseinjector2_baddress_re <= 1'd0; + litedramcore_phaseinjector2_wrdata_re <= 1'd0; + litedramcore_phaseinjector2_status <= 32'd0; + litedramcore_phaseinjector3_command_storage <= 6'd0; + litedramcore_phaseinjector3_command_re <= 1'd0; + litedramcore_phaseinjector3_address_re <= 1'd0; + litedramcore_phaseinjector3_baddress_re <= 1'd0; + litedramcore_phaseinjector3_wrdata_re <= 1'd0; + litedramcore_phaseinjector3_status <= 32'd0; + litedramcore_dfi_p0_address <= 15'd0; + litedramcore_dfi_p0_bank <= 3'd0; + litedramcore_dfi_p0_cas_n <= 1'd1; + litedramcore_dfi_p0_cs_n <= 1'd1; + litedramcore_dfi_p0_ras_n <= 1'd1; + litedramcore_dfi_p0_we_n <= 1'd1; + litedramcore_dfi_p0_wrdata_en <= 1'd0; + litedramcore_dfi_p0_rddata_en <= 1'd0; + litedramcore_dfi_p1_address <= 15'd0; + litedramcore_dfi_p1_bank <= 3'd0; + litedramcore_dfi_p1_cas_n <= 1'd1; + litedramcore_dfi_p1_cs_n <= 1'd1; + litedramcore_dfi_p1_ras_n <= 1'd1; + litedramcore_dfi_p1_we_n <= 1'd1; + litedramcore_dfi_p1_wrdata_en <= 1'd0; + litedramcore_dfi_p1_rddata_en <= 1'd0; + litedramcore_dfi_p2_address <= 15'd0; + litedramcore_dfi_p2_bank <= 3'd0; + litedramcore_dfi_p2_cas_n <= 1'd1; + litedramcore_dfi_p2_cs_n <= 1'd1; + litedramcore_dfi_p2_ras_n <= 1'd1; + litedramcore_dfi_p2_we_n <= 1'd1; + litedramcore_dfi_p2_wrdata_en <= 1'd0; + litedramcore_dfi_p2_rddata_en <= 1'd0; + litedramcore_dfi_p3_address <= 15'd0; + litedramcore_dfi_p3_bank <= 3'd0; + litedramcore_dfi_p3_cas_n <= 1'd1; + litedramcore_dfi_p3_cs_n <= 1'd1; + litedramcore_dfi_p3_ras_n <= 1'd1; + litedramcore_dfi_p3_we_n <= 1'd1; + litedramcore_dfi_p3_wrdata_en <= 1'd0; + litedramcore_dfi_p3_rddata_en <= 1'd0; + litedramcore_timer_count1 <= 10'd781; + litedramcore_postponer_req_o <= 1'd0; + litedramcore_postponer_count <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + litedramcore_sequencer_counter <= 6'd0; + litedramcore_sequencer_count <= 1'd0; + litedramcore_zqcs_timer_count1 <= 27'd99999999; + litedramcore_zqcs_executer_done <= 1'd0; + litedramcore_zqcs_executer_counter <= 5'd0; + litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine0_row <= 15'd0; + litedramcore_bankmachine0_row_opened <= 1'd0; + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + litedramcore_bankmachine0_twtpcon_count <= 3'd0; + litedramcore_bankmachine0_trccon_ready <= 1'd1; + litedramcore_bankmachine0_trccon_count <= 3'd0; + litedramcore_bankmachine0_trascon_ready <= 1'd1; + litedramcore_bankmachine0_trascon_count <= 3'd0; + litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine1_row <= 15'd0; + litedramcore_bankmachine1_row_opened <= 1'd0; + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + litedramcore_bankmachine1_twtpcon_count <= 3'd0; + litedramcore_bankmachine1_trccon_ready <= 1'd1; + litedramcore_bankmachine1_trccon_count <= 3'd0; + litedramcore_bankmachine1_trascon_ready <= 1'd1; + litedramcore_bankmachine1_trascon_count <= 3'd0; + litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine2_row <= 15'd0; + litedramcore_bankmachine2_row_opened <= 1'd0; + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + litedramcore_bankmachine2_twtpcon_count <= 3'd0; + litedramcore_bankmachine2_trccon_ready <= 1'd1; + litedramcore_bankmachine2_trccon_count <= 3'd0; + litedramcore_bankmachine2_trascon_ready <= 1'd1; + litedramcore_bankmachine2_trascon_count <= 3'd0; + litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine3_row <= 15'd0; + litedramcore_bankmachine3_row_opened <= 1'd0; + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + litedramcore_bankmachine3_twtpcon_count <= 3'd0; + litedramcore_bankmachine3_trccon_ready <= 1'd1; + litedramcore_bankmachine3_trccon_count <= 3'd0; + litedramcore_bankmachine3_trascon_ready <= 1'd1; + litedramcore_bankmachine3_trascon_count <= 3'd0; + litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine4_row <= 15'd0; + litedramcore_bankmachine4_row_opened <= 1'd0; + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + litedramcore_bankmachine4_twtpcon_count <= 3'd0; + litedramcore_bankmachine4_trccon_ready <= 1'd1; + litedramcore_bankmachine4_trccon_count <= 3'd0; + litedramcore_bankmachine4_trascon_ready <= 1'd1; + litedramcore_bankmachine4_trascon_count <= 3'd0; + litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine5_row <= 15'd0; + litedramcore_bankmachine5_row_opened <= 1'd0; + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + litedramcore_bankmachine5_twtpcon_count <= 3'd0; + litedramcore_bankmachine5_trccon_ready <= 1'd1; + litedramcore_bankmachine5_trccon_count <= 3'd0; + litedramcore_bankmachine5_trascon_ready <= 1'd1; + litedramcore_bankmachine5_trascon_count <= 3'd0; + litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine6_row <= 15'd0; + litedramcore_bankmachine6_row_opened <= 1'd0; + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + litedramcore_bankmachine6_twtpcon_count <= 3'd0; + litedramcore_bankmachine6_trccon_ready <= 1'd1; + litedramcore_bankmachine6_trccon_count <= 3'd0; + litedramcore_bankmachine6_trascon_ready <= 1'd1; + litedramcore_bankmachine6_trascon_count <= 3'd0; + litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine7_row <= 15'd0; + litedramcore_bankmachine7_row_opened <= 1'd0; + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + litedramcore_bankmachine7_twtpcon_count <= 3'd0; + litedramcore_bankmachine7_trccon_ready <= 1'd1; + litedramcore_bankmachine7_trccon_count <= 3'd0; + litedramcore_bankmachine7_trascon_ready <= 1'd1; + litedramcore_bankmachine7_trascon_count <= 3'd0; + litedramcore_choose_cmd_grant <= 3'd0; + litedramcore_choose_req_grant <= 3'd0; + litedramcore_trrdcon_ready <= 1'd1; + litedramcore_trrdcon_count <= 1'd0; + litedramcore_tfawcon_ready <= 1'd1; + litedramcore_tfawcon_window <= 5'd0; + litedramcore_tccdcon_ready <= 1'd1; + litedramcore_tccdcon_count <= 1'd0; + litedramcore_twtrcon_ready <= 1'd1; + litedramcore_twtrcon_count <= 3'd0; + litedramcore_time0 <= 5'd0; + litedramcore_time1 <= 4'd0; + init_done_storage <= 1'd0; + init_done_re <= 1'd0; + init_error_storage <= 1'd0; + init_error_re <= 1'd0; + refresher_state <= 2'd0; + bankmachine0_state <= 4'd0; + bankmachine1_state <= 4'd0; + bankmachine2_state <= 4'd0; + bankmachine3_state <= 4'd0; + bankmachine4_state <= 4'd0; + bankmachine5_state <= 4'd0; + bankmachine6_state <= 4'd0; + bankmachine7_state <= 4'd0; + multiplexer_state <= 4'd0; + new_master_wdata_ready0 <= 1'd0; + new_master_wdata_ready1 <= 1'd0; + new_master_wdata_ready2 <= 1'd0; + new_master_rdata_valid0 <= 1'd0; + new_master_rdata_valid1 <= 1'd0; + new_master_rdata_valid2 <= 1'd0; + new_master_rdata_valid3 <= 1'd0; + new_master_rdata_valid4 <= 1'd0; + new_master_rdata_valid5 <= 1'd0; + new_master_rdata_valid6 <= 1'd0; + new_master_rdata_valid7 <= 1'd0; + new_master_rdata_valid8 <= 1'd0; + end end -assign soc_litedramcore_uart_rx_fifo_wrport_dat_r = memdat_3; -assign soc_litedramcore_uart_rx_fifo_rdport_dat_r = memdat_4; - BUFG BUFG( - .I(soc_s7pll0_clkout0), - .O(soc_s7pll0_clkout_buf0) + .I(s7pll0_clkout0), + .O(s7pll0_clkout_buf0) ); BUFG BUFG_1( - .I(soc_s7pll0_clkout1), - .O(soc_s7pll0_clkout_buf1) + .I(s7pll0_clkout1), + .O(s7pll0_clkout_buf1) ); BUFG BUFG_2( - .I(soc_s7pll0_clkout2), - .O(soc_s7pll0_clkout_buf2) + .I(s7pll0_clkout2), + .O(s7pll0_clkout_buf2) ); BUFG BUFG_3( - .I(soc_s7pll1_clkout), - .O(soc_s7pll1_clkout_buf) + .I(s7pll1_clkout), + .O(s7pll1_clkout_buf) ); IDELAYCTRL IDELAYCTRL( .REFCLK(iodelay_clk), - .RST(soc_ic_reset) + .RST(ic_reset) ); OSERDESE2 #( @@ -17734,11 +14783,11 @@ OSERDESE2 #( .D8(1'd1), .OCE(1'd1), .RST(sys_rst), - .OQ(soc_a7ddrphy_sd_clk_se_nodelay) + .OQ(a7ddrphy_sd_clk_se_nodelay) ); OBUFDS OBUFDS( - .I(soc_a7ddrphy_sd_clk_se_nodelay), + .I(a7ddrphy_sd_clk_se_nodelay), .O(ddram_clk_p), .OB(ddram_clk_n) ); @@ -17752,14 +14801,14 @@ OSERDESE2 #( ) OSERDESE2_1 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[0]), - .D2(soc_a7ddrphy_dfi_p0_address[0]), - .D3(soc_a7ddrphy_dfi_p1_address[0]), - .D4(soc_a7ddrphy_dfi_p1_address[0]), - .D5(soc_a7ddrphy_dfi_p2_address[0]), - .D6(soc_a7ddrphy_dfi_p2_address[0]), - .D7(soc_a7ddrphy_dfi_p3_address[0]), - .D8(soc_a7ddrphy_dfi_p3_address[0]), + .D1(a7ddrphy_dfi_p0_address[0]), + .D2(a7ddrphy_dfi_p0_address[0]), + .D3(a7ddrphy_dfi_p1_address[0]), + .D4(a7ddrphy_dfi_p1_address[0]), + .D5(a7ddrphy_dfi_p2_address[0]), + .D6(a7ddrphy_dfi_p2_address[0]), + .D7(a7ddrphy_dfi_p3_address[0]), + .D8(a7ddrphy_dfi_p3_address[0]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[0]) @@ -17774,14 +14823,14 @@ OSERDESE2 #( ) OSERDESE2_2 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[1]), - .D2(soc_a7ddrphy_dfi_p0_address[1]), - .D3(soc_a7ddrphy_dfi_p1_address[1]), - .D4(soc_a7ddrphy_dfi_p1_address[1]), - .D5(soc_a7ddrphy_dfi_p2_address[1]), - .D6(soc_a7ddrphy_dfi_p2_address[1]), - .D7(soc_a7ddrphy_dfi_p3_address[1]), - .D8(soc_a7ddrphy_dfi_p3_address[1]), + .D1(a7ddrphy_dfi_p0_address[1]), + .D2(a7ddrphy_dfi_p0_address[1]), + .D3(a7ddrphy_dfi_p1_address[1]), + .D4(a7ddrphy_dfi_p1_address[1]), + .D5(a7ddrphy_dfi_p2_address[1]), + .D6(a7ddrphy_dfi_p2_address[1]), + .D7(a7ddrphy_dfi_p3_address[1]), + .D8(a7ddrphy_dfi_p3_address[1]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[1]) @@ -17796,14 +14845,14 @@ OSERDESE2 #( ) OSERDESE2_3 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[2]), - .D2(soc_a7ddrphy_dfi_p0_address[2]), - .D3(soc_a7ddrphy_dfi_p1_address[2]), - .D4(soc_a7ddrphy_dfi_p1_address[2]), - .D5(soc_a7ddrphy_dfi_p2_address[2]), - .D6(soc_a7ddrphy_dfi_p2_address[2]), - .D7(soc_a7ddrphy_dfi_p3_address[2]), - .D8(soc_a7ddrphy_dfi_p3_address[2]), + .D1(a7ddrphy_dfi_p0_address[2]), + .D2(a7ddrphy_dfi_p0_address[2]), + .D3(a7ddrphy_dfi_p1_address[2]), + .D4(a7ddrphy_dfi_p1_address[2]), + .D5(a7ddrphy_dfi_p2_address[2]), + .D6(a7ddrphy_dfi_p2_address[2]), + .D7(a7ddrphy_dfi_p3_address[2]), + .D8(a7ddrphy_dfi_p3_address[2]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[2]) @@ -17818,14 +14867,14 @@ OSERDESE2 #( ) OSERDESE2_4 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[3]), - .D2(soc_a7ddrphy_dfi_p0_address[3]), - .D3(soc_a7ddrphy_dfi_p1_address[3]), - .D4(soc_a7ddrphy_dfi_p1_address[3]), - .D5(soc_a7ddrphy_dfi_p2_address[3]), - .D6(soc_a7ddrphy_dfi_p2_address[3]), - .D7(soc_a7ddrphy_dfi_p3_address[3]), - .D8(soc_a7ddrphy_dfi_p3_address[3]), + .D1(a7ddrphy_dfi_p0_address[3]), + .D2(a7ddrphy_dfi_p0_address[3]), + .D3(a7ddrphy_dfi_p1_address[3]), + .D4(a7ddrphy_dfi_p1_address[3]), + .D5(a7ddrphy_dfi_p2_address[3]), + .D6(a7ddrphy_dfi_p2_address[3]), + .D7(a7ddrphy_dfi_p3_address[3]), + .D8(a7ddrphy_dfi_p3_address[3]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[3]) @@ -17840,14 +14889,14 @@ OSERDESE2 #( ) OSERDESE2_5 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[4]), - .D2(soc_a7ddrphy_dfi_p0_address[4]), - .D3(soc_a7ddrphy_dfi_p1_address[4]), - .D4(soc_a7ddrphy_dfi_p1_address[4]), - .D5(soc_a7ddrphy_dfi_p2_address[4]), - .D6(soc_a7ddrphy_dfi_p2_address[4]), - .D7(soc_a7ddrphy_dfi_p3_address[4]), - .D8(soc_a7ddrphy_dfi_p3_address[4]), + .D1(a7ddrphy_dfi_p0_address[4]), + .D2(a7ddrphy_dfi_p0_address[4]), + .D3(a7ddrphy_dfi_p1_address[4]), + .D4(a7ddrphy_dfi_p1_address[4]), + .D5(a7ddrphy_dfi_p2_address[4]), + .D6(a7ddrphy_dfi_p2_address[4]), + .D7(a7ddrphy_dfi_p3_address[4]), + .D8(a7ddrphy_dfi_p3_address[4]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[4]) @@ -17862,14 +14911,14 @@ OSERDESE2 #( ) OSERDESE2_6 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[5]), - .D2(soc_a7ddrphy_dfi_p0_address[5]), - .D3(soc_a7ddrphy_dfi_p1_address[5]), - .D4(soc_a7ddrphy_dfi_p1_address[5]), - .D5(soc_a7ddrphy_dfi_p2_address[5]), - .D6(soc_a7ddrphy_dfi_p2_address[5]), - .D7(soc_a7ddrphy_dfi_p3_address[5]), - .D8(soc_a7ddrphy_dfi_p3_address[5]), + .D1(a7ddrphy_dfi_p0_address[5]), + .D2(a7ddrphy_dfi_p0_address[5]), + .D3(a7ddrphy_dfi_p1_address[5]), + .D4(a7ddrphy_dfi_p1_address[5]), + .D5(a7ddrphy_dfi_p2_address[5]), + .D6(a7ddrphy_dfi_p2_address[5]), + .D7(a7ddrphy_dfi_p3_address[5]), + .D8(a7ddrphy_dfi_p3_address[5]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[5]) @@ -17884,14 +14933,14 @@ OSERDESE2 #( ) OSERDESE2_7 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[6]), - .D2(soc_a7ddrphy_dfi_p0_address[6]), - .D3(soc_a7ddrphy_dfi_p1_address[6]), - .D4(soc_a7ddrphy_dfi_p1_address[6]), - .D5(soc_a7ddrphy_dfi_p2_address[6]), - .D6(soc_a7ddrphy_dfi_p2_address[6]), - .D7(soc_a7ddrphy_dfi_p3_address[6]), - .D8(soc_a7ddrphy_dfi_p3_address[6]), + .D1(a7ddrphy_dfi_p0_address[6]), + .D2(a7ddrphy_dfi_p0_address[6]), + .D3(a7ddrphy_dfi_p1_address[6]), + .D4(a7ddrphy_dfi_p1_address[6]), + .D5(a7ddrphy_dfi_p2_address[6]), + .D6(a7ddrphy_dfi_p2_address[6]), + .D7(a7ddrphy_dfi_p3_address[6]), + .D8(a7ddrphy_dfi_p3_address[6]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[6]) @@ -17906,14 +14955,14 @@ OSERDESE2 #( ) OSERDESE2_8 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[7]), - .D2(soc_a7ddrphy_dfi_p0_address[7]), - .D3(soc_a7ddrphy_dfi_p1_address[7]), - .D4(soc_a7ddrphy_dfi_p1_address[7]), - .D5(soc_a7ddrphy_dfi_p2_address[7]), - .D6(soc_a7ddrphy_dfi_p2_address[7]), - .D7(soc_a7ddrphy_dfi_p3_address[7]), - .D8(soc_a7ddrphy_dfi_p3_address[7]), + .D1(a7ddrphy_dfi_p0_address[7]), + .D2(a7ddrphy_dfi_p0_address[7]), + .D3(a7ddrphy_dfi_p1_address[7]), + .D4(a7ddrphy_dfi_p1_address[7]), + .D5(a7ddrphy_dfi_p2_address[7]), + .D6(a7ddrphy_dfi_p2_address[7]), + .D7(a7ddrphy_dfi_p3_address[7]), + .D8(a7ddrphy_dfi_p3_address[7]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[7]) @@ -17928,14 +14977,14 @@ OSERDESE2 #( ) OSERDESE2_9 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[8]), - .D2(soc_a7ddrphy_dfi_p0_address[8]), - .D3(soc_a7ddrphy_dfi_p1_address[8]), - .D4(soc_a7ddrphy_dfi_p1_address[8]), - .D5(soc_a7ddrphy_dfi_p2_address[8]), - .D6(soc_a7ddrphy_dfi_p2_address[8]), - .D7(soc_a7ddrphy_dfi_p3_address[8]), - .D8(soc_a7ddrphy_dfi_p3_address[8]), + .D1(a7ddrphy_dfi_p0_address[8]), + .D2(a7ddrphy_dfi_p0_address[8]), + .D3(a7ddrphy_dfi_p1_address[8]), + .D4(a7ddrphy_dfi_p1_address[8]), + .D5(a7ddrphy_dfi_p2_address[8]), + .D6(a7ddrphy_dfi_p2_address[8]), + .D7(a7ddrphy_dfi_p3_address[8]), + .D8(a7ddrphy_dfi_p3_address[8]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[8]) @@ -17950,14 +14999,14 @@ OSERDESE2 #( ) OSERDESE2_10 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[9]), - .D2(soc_a7ddrphy_dfi_p0_address[9]), - .D3(soc_a7ddrphy_dfi_p1_address[9]), - .D4(soc_a7ddrphy_dfi_p1_address[9]), - .D5(soc_a7ddrphy_dfi_p2_address[9]), - .D6(soc_a7ddrphy_dfi_p2_address[9]), - .D7(soc_a7ddrphy_dfi_p3_address[9]), - .D8(soc_a7ddrphy_dfi_p3_address[9]), + .D1(a7ddrphy_dfi_p0_address[9]), + .D2(a7ddrphy_dfi_p0_address[9]), + .D3(a7ddrphy_dfi_p1_address[9]), + .D4(a7ddrphy_dfi_p1_address[9]), + .D5(a7ddrphy_dfi_p2_address[9]), + .D6(a7ddrphy_dfi_p2_address[9]), + .D7(a7ddrphy_dfi_p3_address[9]), + .D8(a7ddrphy_dfi_p3_address[9]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[9]) @@ -17972,14 +15021,14 @@ OSERDESE2 #( ) OSERDESE2_11 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[10]), - .D2(soc_a7ddrphy_dfi_p0_address[10]), - .D3(soc_a7ddrphy_dfi_p1_address[10]), - .D4(soc_a7ddrphy_dfi_p1_address[10]), - .D5(soc_a7ddrphy_dfi_p2_address[10]), - .D6(soc_a7ddrphy_dfi_p2_address[10]), - .D7(soc_a7ddrphy_dfi_p3_address[10]), - .D8(soc_a7ddrphy_dfi_p3_address[10]), + .D1(a7ddrphy_dfi_p0_address[10]), + .D2(a7ddrphy_dfi_p0_address[10]), + .D3(a7ddrphy_dfi_p1_address[10]), + .D4(a7ddrphy_dfi_p1_address[10]), + .D5(a7ddrphy_dfi_p2_address[10]), + .D6(a7ddrphy_dfi_p2_address[10]), + .D7(a7ddrphy_dfi_p3_address[10]), + .D8(a7ddrphy_dfi_p3_address[10]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[10]) @@ -17994,14 +15043,14 @@ OSERDESE2 #( ) OSERDESE2_12 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[11]), - .D2(soc_a7ddrphy_dfi_p0_address[11]), - .D3(soc_a7ddrphy_dfi_p1_address[11]), - .D4(soc_a7ddrphy_dfi_p1_address[11]), - .D5(soc_a7ddrphy_dfi_p2_address[11]), - .D6(soc_a7ddrphy_dfi_p2_address[11]), - .D7(soc_a7ddrphy_dfi_p3_address[11]), - .D8(soc_a7ddrphy_dfi_p3_address[11]), + .D1(a7ddrphy_dfi_p0_address[11]), + .D2(a7ddrphy_dfi_p0_address[11]), + .D3(a7ddrphy_dfi_p1_address[11]), + .D4(a7ddrphy_dfi_p1_address[11]), + .D5(a7ddrphy_dfi_p2_address[11]), + .D6(a7ddrphy_dfi_p2_address[11]), + .D7(a7ddrphy_dfi_p3_address[11]), + .D8(a7ddrphy_dfi_p3_address[11]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[11]) @@ -18016,14 +15065,14 @@ OSERDESE2 #( ) OSERDESE2_13 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[12]), - .D2(soc_a7ddrphy_dfi_p0_address[12]), - .D3(soc_a7ddrphy_dfi_p1_address[12]), - .D4(soc_a7ddrphy_dfi_p1_address[12]), - .D5(soc_a7ddrphy_dfi_p2_address[12]), - .D6(soc_a7ddrphy_dfi_p2_address[12]), - .D7(soc_a7ddrphy_dfi_p3_address[12]), - .D8(soc_a7ddrphy_dfi_p3_address[12]), + .D1(a7ddrphy_dfi_p0_address[12]), + .D2(a7ddrphy_dfi_p0_address[12]), + .D3(a7ddrphy_dfi_p1_address[12]), + .D4(a7ddrphy_dfi_p1_address[12]), + .D5(a7ddrphy_dfi_p2_address[12]), + .D6(a7ddrphy_dfi_p2_address[12]), + .D7(a7ddrphy_dfi_p3_address[12]), + .D8(a7ddrphy_dfi_p3_address[12]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[12]) @@ -18038,14 +15087,14 @@ OSERDESE2 #( ) OSERDESE2_14 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[13]), - .D2(soc_a7ddrphy_dfi_p0_address[13]), - .D3(soc_a7ddrphy_dfi_p1_address[13]), - .D4(soc_a7ddrphy_dfi_p1_address[13]), - .D5(soc_a7ddrphy_dfi_p2_address[13]), - .D6(soc_a7ddrphy_dfi_p2_address[13]), - .D7(soc_a7ddrphy_dfi_p3_address[13]), - .D8(soc_a7ddrphy_dfi_p3_address[13]), + .D1(a7ddrphy_dfi_p0_address[13]), + .D2(a7ddrphy_dfi_p0_address[13]), + .D3(a7ddrphy_dfi_p1_address[13]), + .D4(a7ddrphy_dfi_p1_address[13]), + .D5(a7ddrphy_dfi_p2_address[13]), + .D6(a7ddrphy_dfi_p2_address[13]), + .D7(a7ddrphy_dfi_p3_address[13]), + .D8(a7ddrphy_dfi_p3_address[13]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[13]) @@ -18060,14 +15109,14 @@ OSERDESE2 #( ) OSERDESE2_15 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_address[14]), - .D2(soc_a7ddrphy_dfi_p0_address[14]), - .D3(soc_a7ddrphy_dfi_p1_address[14]), - .D4(soc_a7ddrphy_dfi_p1_address[14]), - .D5(soc_a7ddrphy_dfi_p2_address[14]), - .D6(soc_a7ddrphy_dfi_p2_address[14]), - .D7(soc_a7ddrphy_dfi_p3_address[14]), - .D8(soc_a7ddrphy_dfi_p3_address[14]), + .D1(a7ddrphy_dfi_p0_address[14]), + .D2(a7ddrphy_dfi_p0_address[14]), + .D3(a7ddrphy_dfi_p1_address[14]), + .D4(a7ddrphy_dfi_p1_address[14]), + .D5(a7ddrphy_dfi_p2_address[14]), + .D6(a7ddrphy_dfi_p2_address[14]), + .D7(a7ddrphy_dfi_p3_address[14]), + .D8(a7ddrphy_dfi_p3_address[14]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_a[14]) @@ -18082,14 +15131,14 @@ OSERDESE2 #( ) OSERDESE2_16 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_bank[0]), - .D2(soc_a7ddrphy_dfi_p0_bank[0]), - .D3(soc_a7ddrphy_dfi_p1_bank[0]), - .D4(soc_a7ddrphy_dfi_p1_bank[0]), - .D5(soc_a7ddrphy_dfi_p2_bank[0]), - .D6(soc_a7ddrphy_dfi_p2_bank[0]), - .D7(soc_a7ddrphy_dfi_p3_bank[0]), - .D8(soc_a7ddrphy_dfi_p3_bank[0]), + .D1(a7ddrphy_dfi_p0_bank[0]), + .D2(a7ddrphy_dfi_p0_bank[0]), + .D3(a7ddrphy_dfi_p1_bank[0]), + .D4(a7ddrphy_dfi_p1_bank[0]), + .D5(a7ddrphy_dfi_p2_bank[0]), + .D6(a7ddrphy_dfi_p2_bank[0]), + .D7(a7ddrphy_dfi_p3_bank[0]), + .D8(a7ddrphy_dfi_p3_bank[0]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_ba[0]) @@ -18104,14 +15153,14 @@ OSERDESE2 #( ) OSERDESE2_17 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_bank[1]), - .D2(soc_a7ddrphy_dfi_p0_bank[1]), - .D3(soc_a7ddrphy_dfi_p1_bank[1]), - .D4(soc_a7ddrphy_dfi_p1_bank[1]), - .D5(soc_a7ddrphy_dfi_p2_bank[1]), - .D6(soc_a7ddrphy_dfi_p2_bank[1]), - .D7(soc_a7ddrphy_dfi_p3_bank[1]), - .D8(soc_a7ddrphy_dfi_p3_bank[1]), + .D1(a7ddrphy_dfi_p0_bank[1]), + .D2(a7ddrphy_dfi_p0_bank[1]), + .D3(a7ddrphy_dfi_p1_bank[1]), + .D4(a7ddrphy_dfi_p1_bank[1]), + .D5(a7ddrphy_dfi_p2_bank[1]), + .D6(a7ddrphy_dfi_p2_bank[1]), + .D7(a7ddrphy_dfi_p3_bank[1]), + .D8(a7ddrphy_dfi_p3_bank[1]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_ba[1]) @@ -18126,14 +15175,14 @@ OSERDESE2 #( ) OSERDESE2_18 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_bank[2]), - .D2(soc_a7ddrphy_dfi_p0_bank[2]), - .D3(soc_a7ddrphy_dfi_p1_bank[2]), - .D4(soc_a7ddrphy_dfi_p1_bank[2]), - .D5(soc_a7ddrphy_dfi_p2_bank[2]), - .D6(soc_a7ddrphy_dfi_p2_bank[2]), - .D7(soc_a7ddrphy_dfi_p3_bank[2]), - .D8(soc_a7ddrphy_dfi_p3_bank[2]), + .D1(a7ddrphy_dfi_p0_bank[2]), + .D2(a7ddrphy_dfi_p0_bank[2]), + .D3(a7ddrphy_dfi_p1_bank[2]), + .D4(a7ddrphy_dfi_p1_bank[2]), + .D5(a7ddrphy_dfi_p2_bank[2]), + .D6(a7ddrphy_dfi_p2_bank[2]), + .D7(a7ddrphy_dfi_p3_bank[2]), + .D8(a7ddrphy_dfi_p3_bank[2]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_ba[2]) @@ -18148,14 +15197,14 @@ OSERDESE2 #( ) OSERDESE2_19 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_ras_n), - .D2(soc_a7ddrphy_dfi_p0_ras_n), - .D3(soc_a7ddrphy_dfi_p1_ras_n), - .D4(soc_a7ddrphy_dfi_p1_ras_n), - .D5(soc_a7ddrphy_dfi_p2_ras_n), - .D6(soc_a7ddrphy_dfi_p2_ras_n), - .D7(soc_a7ddrphy_dfi_p3_ras_n), - .D8(soc_a7ddrphy_dfi_p3_ras_n), + .D1(a7ddrphy_dfi_p0_ras_n), + .D2(a7ddrphy_dfi_p0_ras_n), + .D3(a7ddrphy_dfi_p1_ras_n), + .D4(a7ddrphy_dfi_p1_ras_n), + .D5(a7ddrphy_dfi_p2_ras_n), + .D6(a7ddrphy_dfi_p2_ras_n), + .D7(a7ddrphy_dfi_p3_ras_n), + .D8(a7ddrphy_dfi_p3_ras_n), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_ras_n) @@ -18170,14 +15219,14 @@ OSERDESE2 #( ) OSERDESE2_20 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_cas_n), - .D2(soc_a7ddrphy_dfi_p0_cas_n), - .D3(soc_a7ddrphy_dfi_p1_cas_n), - .D4(soc_a7ddrphy_dfi_p1_cas_n), - .D5(soc_a7ddrphy_dfi_p2_cas_n), - .D6(soc_a7ddrphy_dfi_p2_cas_n), - .D7(soc_a7ddrphy_dfi_p3_cas_n), - .D8(soc_a7ddrphy_dfi_p3_cas_n), + .D1(a7ddrphy_dfi_p0_cas_n), + .D2(a7ddrphy_dfi_p0_cas_n), + .D3(a7ddrphy_dfi_p1_cas_n), + .D4(a7ddrphy_dfi_p1_cas_n), + .D5(a7ddrphy_dfi_p2_cas_n), + .D6(a7ddrphy_dfi_p2_cas_n), + .D7(a7ddrphy_dfi_p3_cas_n), + .D8(a7ddrphy_dfi_p3_cas_n), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_cas_n) @@ -18192,14 +15241,14 @@ OSERDESE2 #( ) OSERDESE2_21 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_we_n), - .D2(soc_a7ddrphy_dfi_p0_we_n), - .D3(soc_a7ddrphy_dfi_p1_we_n), - .D4(soc_a7ddrphy_dfi_p1_we_n), - .D5(soc_a7ddrphy_dfi_p2_we_n), - .D6(soc_a7ddrphy_dfi_p2_we_n), - .D7(soc_a7ddrphy_dfi_p3_we_n), - .D8(soc_a7ddrphy_dfi_p3_we_n), + .D1(a7ddrphy_dfi_p0_we_n), + .D2(a7ddrphy_dfi_p0_we_n), + .D3(a7ddrphy_dfi_p1_we_n), + .D4(a7ddrphy_dfi_p1_we_n), + .D5(a7ddrphy_dfi_p2_we_n), + .D6(a7ddrphy_dfi_p2_we_n), + .D7(a7ddrphy_dfi_p3_we_n), + .D8(a7ddrphy_dfi_p3_we_n), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_we_n) @@ -18214,14 +15263,14 @@ OSERDESE2 #( ) OSERDESE2_22 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_cke), - .D2(soc_a7ddrphy_dfi_p0_cke), - .D3(soc_a7ddrphy_dfi_p1_cke), - .D4(soc_a7ddrphy_dfi_p1_cke), - .D5(soc_a7ddrphy_dfi_p2_cke), - .D6(soc_a7ddrphy_dfi_p2_cke), - .D7(soc_a7ddrphy_dfi_p3_cke), - .D8(soc_a7ddrphy_dfi_p3_cke), + .D1(a7ddrphy_dfi_p0_cke), + .D2(a7ddrphy_dfi_p0_cke), + .D3(a7ddrphy_dfi_p1_cke), + .D4(a7ddrphy_dfi_p1_cke), + .D5(a7ddrphy_dfi_p2_cke), + .D6(a7ddrphy_dfi_p2_cke), + .D7(a7ddrphy_dfi_p3_cke), + .D8(a7ddrphy_dfi_p3_cke), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_cke) @@ -18236,14 +15285,14 @@ OSERDESE2 #( ) OSERDESE2_23 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_odt), - .D2(soc_a7ddrphy_dfi_p0_odt), - .D3(soc_a7ddrphy_dfi_p1_odt), - .D4(soc_a7ddrphy_dfi_p1_odt), - .D5(soc_a7ddrphy_dfi_p2_odt), - .D6(soc_a7ddrphy_dfi_p2_odt), - .D7(soc_a7ddrphy_dfi_p3_odt), - .D8(soc_a7ddrphy_dfi_p3_odt), + .D1(a7ddrphy_dfi_p0_odt), + .D2(a7ddrphy_dfi_p0_odt), + .D3(a7ddrphy_dfi_p1_odt), + .D4(a7ddrphy_dfi_p1_odt), + .D5(a7ddrphy_dfi_p2_odt), + .D6(a7ddrphy_dfi_p2_odt), + .D7(a7ddrphy_dfi_p3_odt), + .D8(a7ddrphy_dfi_p3_odt), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_odt) @@ -18258,14 +15307,14 @@ OSERDESE2 #( ) OSERDESE2_24 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_reset_n), - .D2(soc_a7ddrphy_dfi_p0_reset_n), - .D3(soc_a7ddrphy_dfi_p1_reset_n), - .D4(soc_a7ddrphy_dfi_p1_reset_n), - .D5(soc_a7ddrphy_dfi_p2_reset_n), - .D6(soc_a7ddrphy_dfi_p2_reset_n), - .D7(soc_a7ddrphy_dfi_p3_reset_n), - .D8(soc_a7ddrphy_dfi_p3_reset_n), + .D1(a7ddrphy_dfi_p0_reset_n), + .D2(a7ddrphy_dfi_p0_reset_n), + .D3(a7ddrphy_dfi_p1_reset_n), + .D4(a7ddrphy_dfi_p1_reset_n), + .D5(a7ddrphy_dfi_p2_reset_n), + .D6(a7ddrphy_dfi_p2_reset_n), + .D7(a7ddrphy_dfi_p3_reset_n), + .D8(a7ddrphy_dfi_p3_reset_n), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_reset_n) @@ -18280,14 +15329,14 @@ OSERDESE2 #( ) OSERDESE2_25 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_cs_n), - .D2(soc_a7ddrphy_dfi_p0_cs_n), - .D3(soc_a7ddrphy_dfi_p1_cs_n), - .D4(soc_a7ddrphy_dfi_p1_cs_n), - .D5(soc_a7ddrphy_dfi_p2_cs_n), - .D6(soc_a7ddrphy_dfi_p2_cs_n), - .D7(soc_a7ddrphy_dfi_p3_cs_n), - .D8(soc_a7ddrphy_dfi_p3_cs_n), + .D1(a7ddrphy_dfi_p0_cs_n), + .D2(a7ddrphy_dfi_p0_cs_n), + .D3(a7ddrphy_dfi_p1_cs_n), + .D4(a7ddrphy_dfi_p1_cs_n), + .D5(a7ddrphy_dfi_p2_cs_n), + .D6(a7ddrphy_dfi_p2_cs_n), + .D7(a7ddrphy_dfi_p3_cs_n), + .D8(a7ddrphy_dfi_p3_cs_n), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_cs_n) @@ -18302,14 +15351,14 @@ OSERDESE2 #( ) OSERDESE2_26 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[0]), - .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[2]), - .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[0]), - .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[2]), - .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[0]), - .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[2]), - .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[0]), - .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[2]), + .D1(a7ddrphy_dfi_p0_wrdata_mask[0]), + .D2(a7ddrphy_dfi_p0_wrdata_mask[2]), + .D3(a7ddrphy_dfi_p1_wrdata_mask[0]), + .D4(a7ddrphy_dfi_p1_wrdata_mask[2]), + .D5(a7ddrphy_dfi_p2_wrdata_mask[0]), + .D6(a7ddrphy_dfi_p2_wrdata_mask[2]), + .D7(a7ddrphy_dfi_p3_wrdata_mask[0]), + .D8(a7ddrphy_dfi_p3_wrdata_mask[2]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_dm[0]) @@ -18324,14 +15373,14 @@ OSERDESE2 #( ) OSERDESE2_27 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[1]), - .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[3]), - .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[1]), - .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[3]), - .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[1]), - .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[3]), - .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[1]), - .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[3]), + .D1(a7ddrphy_dfi_p0_wrdata_mask[1]), + .D2(a7ddrphy_dfi_p0_wrdata_mask[3]), + .D3(a7ddrphy_dfi_p1_wrdata_mask[1]), + .D4(a7ddrphy_dfi_p1_wrdata_mask[3]), + .D5(a7ddrphy_dfi_p2_wrdata_mask[1]), + .D6(a7ddrphy_dfi_p2_wrdata_mask[3]), + .D7(a7ddrphy_dfi_p3_wrdata_mask[1]), + .D8(a7ddrphy_dfi_p3_wrdata_mask[3]), .OCE(1'd1), .RST(sys_rst), .OQ(ddram_dm[1]) @@ -18346,21 +15395,21 @@ OSERDESE2 #( ) OSERDESE2_28 ( .CLK(sys4x_dqs_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dqspattern_o1[0]), - .D2(soc_a7ddrphy_dqspattern_o1[1]), - .D3(soc_a7ddrphy_dqspattern_o1[2]), - .D4(soc_a7ddrphy_dqspattern_o1[3]), - .D5(soc_a7ddrphy_dqspattern_o1[4]), - .D6(soc_a7ddrphy_dqspattern_o1[5]), - .D7(soc_a7ddrphy_dqspattern_o1[6]), - .D8(soc_a7ddrphy_dqspattern_o1[7]), + .D1(a7ddrphy_dqspattern_o1[0]), + .D2(a7ddrphy_dqspattern_o1[1]), + .D3(a7ddrphy_dqspattern_o1[2]), + .D4(a7ddrphy_dqspattern_o1[3]), + .D5(a7ddrphy_dqspattern_o1[4]), + .D6(a7ddrphy_dqspattern_o1[5]), + .D7(a7ddrphy_dqspattern_o1[6]), + .D8(a7ddrphy_dqspattern_o1[7]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dqs_oe_delayed)), + .T1((~a7ddrphy_dqs_oe_delayed)), .TCE(1'd1), - .OFB(soc_a7ddrphy0), - .OQ(soc_a7ddrphy_dqs_o_no_delay0), - .TQ(soc_a7ddrphy_dqs_t0) + .OFB(a7ddrphy0), + .OQ(a7ddrphy_dqs_o_no_delay0), + .TQ(a7ddrphy_dqs_t0) ); IDELAYE2 #( @@ -18373,16 +15422,16 @@ IDELAYE2 #( .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2 ( - .IDATAIN(soc_a7ddrphy_dqs_i[0]), - .DATAOUT(soc_a7ddrphy_dqs_i_delayed[0]) + .IDATAIN(a7ddrphy_dqs_i[0]), + .DATAOUT(a7ddrphy_dqs_i_delayed[0]) ); IOBUFDS IOBUFDS( - .I(soc_a7ddrphy_dqs_o_no_delay0), - .T(soc_a7ddrphy_dqs_t0), + .I(a7ddrphy_dqs_o_no_delay0), + .T(a7ddrphy_dqs_t0), .IO(ddram_dqs_p[0]), .IOB(ddram_dqs_n[0]), - .O(soc_a7ddrphy_dqs_i[0]) + .O(a7ddrphy_dqs_i[0]) ); OSERDESE2 #( @@ -18394,21 +15443,21 @@ OSERDESE2 #( ) OSERDESE2_29 ( .CLK(sys4x_dqs_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dqspattern_o1[0]), - .D2(soc_a7ddrphy_dqspattern_o1[1]), - .D3(soc_a7ddrphy_dqspattern_o1[2]), - .D4(soc_a7ddrphy_dqspattern_o1[3]), - .D5(soc_a7ddrphy_dqspattern_o1[4]), - .D6(soc_a7ddrphy_dqspattern_o1[5]), - .D7(soc_a7ddrphy_dqspattern_o1[6]), - .D8(soc_a7ddrphy_dqspattern_o1[7]), + .D1(a7ddrphy_dqspattern_o1[0]), + .D2(a7ddrphy_dqspattern_o1[1]), + .D3(a7ddrphy_dqspattern_o1[2]), + .D4(a7ddrphy_dqspattern_o1[3]), + .D5(a7ddrphy_dqspattern_o1[4]), + .D6(a7ddrphy_dqspattern_o1[5]), + .D7(a7ddrphy_dqspattern_o1[6]), + .D8(a7ddrphy_dqspattern_o1[7]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dqs_oe_delayed)), + .T1((~a7ddrphy_dqs_oe_delayed)), .TCE(1'd1), - .OFB(soc_a7ddrphy1), - .OQ(soc_a7ddrphy_dqs_o_no_delay1), - .TQ(soc_a7ddrphy_dqs_t1) + .OFB(a7ddrphy1), + .OQ(a7ddrphy_dqs_o_no_delay1), + .TQ(a7ddrphy_dqs_t1) ); IDELAYE2 #( @@ -18421,16 +15470,16 @@ IDELAYE2 #( .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_1 ( - .IDATAIN(soc_a7ddrphy_dqs_i[1]), - .DATAOUT(soc_a7ddrphy_dqs_i_delayed[1]) + .IDATAIN(a7ddrphy_dqs_i[1]), + .DATAOUT(a7ddrphy_dqs_i_delayed[1]) ); IOBUFDS IOBUFDS_1( - .I(soc_a7ddrphy_dqs_o_no_delay1), - .T(soc_a7ddrphy_dqs_t1), + .I(a7ddrphy_dqs_o_no_delay1), + .T(a7ddrphy_dqs_t1), .IO(ddram_dqs_p[1]), .IOB(ddram_dqs_n[1]), - .O(soc_a7ddrphy_dqs_i[1]) + .O(a7ddrphy_dqs_i[1]) ); OSERDESE2 #( @@ -18442,20 +15491,20 @@ OSERDESE2 #( ) OSERDESE2_30 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[0]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[16]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[0]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[16]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[0]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[16]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[0]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[16]), + .D1(a7ddrphy_dfi_p0_wrdata[0]), + .D2(a7ddrphy_dfi_p0_wrdata[16]), + .D3(a7ddrphy_dfi_p1_wrdata[0]), + .D4(a7ddrphy_dfi_p1_wrdata[16]), + .D5(a7ddrphy_dfi_p2_wrdata[0]), + .D6(a7ddrphy_dfi_p2_wrdata[16]), + .D7(a7ddrphy_dfi_p3_wrdata[0]), + .D8(a7ddrphy_dfi_p3_wrdata[16]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay0), - .TQ(soc_a7ddrphy_dq_t0) + .OQ(a7ddrphy_dq_o_nodelay0), + .TQ(a7ddrphy_dq_t0) ); ISERDESE2 #( @@ -18471,16 +15520,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed0), + .DDLY(a7ddrphy_dq_i_delayed0), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data0[7]), - .Q2(soc_a7ddrphy_dq_i_data0[6]), - .Q3(soc_a7ddrphy_dq_i_data0[5]), - .Q4(soc_a7ddrphy_dq_i_data0[4]), - .Q5(soc_a7ddrphy_dq_i_data0[3]), - .Q6(soc_a7ddrphy_dq_i_data0[2]), - .Q7(soc_a7ddrphy_dq_i_data0[1]), - .Q8(soc_a7ddrphy_dq_i_data0[0]) + .Q1(a7ddrphy_dq_i_data0[7]), + .Q2(a7ddrphy_dq_i_data0[6]), + .Q3(a7ddrphy_dq_i_data0[5]), + .Q4(a7ddrphy_dq_i_data0[4]), + .Q5(a7ddrphy_dq_i_data0[3]), + .Q6(a7ddrphy_dq_i_data0[2]), + .Q7(a7ddrphy_dq_i_data0[1]), + .Q8(a7ddrphy_dq_i_data0[0]) ); IDELAYE2 #( @@ -18494,19 +15543,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_2 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay0), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay0), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed0) + .DATAOUT(a7ddrphy_dq_i_delayed0) ); IOBUF IOBUF( - .I(soc_a7ddrphy_dq_o_nodelay0), - .T(soc_a7ddrphy_dq_t0), + .I(a7ddrphy_dq_o_nodelay0), + .T(a7ddrphy_dq_t0), .IO(ddram_dq[0]), - .O(soc_a7ddrphy_dq_i_nodelay0) + .O(a7ddrphy_dq_i_nodelay0) ); OSERDESE2 #( @@ -18518,20 +15567,20 @@ OSERDESE2 #( ) OSERDESE2_31 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[1]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[17]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[1]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[17]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[1]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[17]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[1]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[17]), + .D1(a7ddrphy_dfi_p0_wrdata[1]), + .D2(a7ddrphy_dfi_p0_wrdata[17]), + .D3(a7ddrphy_dfi_p1_wrdata[1]), + .D4(a7ddrphy_dfi_p1_wrdata[17]), + .D5(a7ddrphy_dfi_p2_wrdata[1]), + .D6(a7ddrphy_dfi_p2_wrdata[17]), + .D7(a7ddrphy_dfi_p3_wrdata[1]), + .D8(a7ddrphy_dfi_p3_wrdata[17]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay1), - .TQ(soc_a7ddrphy_dq_t1) + .OQ(a7ddrphy_dq_o_nodelay1), + .TQ(a7ddrphy_dq_t1) ); ISERDESE2 #( @@ -18547,16 +15596,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed1), + .DDLY(a7ddrphy_dq_i_delayed1), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data1[7]), - .Q2(soc_a7ddrphy_dq_i_data1[6]), - .Q3(soc_a7ddrphy_dq_i_data1[5]), - .Q4(soc_a7ddrphy_dq_i_data1[4]), - .Q5(soc_a7ddrphy_dq_i_data1[3]), - .Q6(soc_a7ddrphy_dq_i_data1[2]), - .Q7(soc_a7ddrphy_dq_i_data1[1]), - .Q8(soc_a7ddrphy_dq_i_data1[0]) + .Q1(a7ddrphy_dq_i_data1[7]), + .Q2(a7ddrphy_dq_i_data1[6]), + .Q3(a7ddrphy_dq_i_data1[5]), + .Q4(a7ddrphy_dq_i_data1[4]), + .Q5(a7ddrphy_dq_i_data1[3]), + .Q6(a7ddrphy_dq_i_data1[2]), + .Q7(a7ddrphy_dq_i_data1[1]), + .Q8(a7ddrphy_dq_i_data1[0]) ); IDELAYE2 #( @@ -18570,19 +15619,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_3 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay1), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay1), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed1) + .DATAOUT(a7ddrphy_dq_i_delayed1) ); IOBUF IOBUF_1( - .I(soc_a7ddrphy_dq_o_nodelay1), - .T(soc_a7ddrphy_dq_t1), + .I(a7ddrphy_dq_o_nodelay1), + .T(a7ddrphy_dq_t1), .IO(ddram_dq[1]), - .O(soc_a7ddrphy_dq_i_nodelay1) + .O(a7ddrphy_dq_i_nodelay1) ); OSERDESE2 #( @@ -18594,20 +15643,20 @@ OSERDESE2 #( ) OSERDESE2_32 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[2]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[18]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[2]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[18]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[2]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[18]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[2]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[18]), + .D1(a7ddrphy_dfi_p0_wrdata[2]), + .D2(a7ddrphy_dfi_p0_wrdata[18]), + .D3(a7ddrphy_dfi_p1_wrdata[2]), + .D4(a7ddrphy_dfi_p1_wrdata[18]), + .D5(a7ddrphy_dfi_p2_wrdata[2]), + .D6(a7ddrphy_dfi_p2_wrdata[18]), + .D7(a7ddrphy_dfi_p3_wrdata[2]), + .D8(a7ddrphy_dfi_p3_wrdata[18]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay2), - .TQ(soc_a7ddrphy_dq_t2) + .OQ(a7ddrphy_dq_o_nodelay2), + .TQ(a7ddrphy_dq_t2) ); ISERDESE2 #( @@ -18623,16 +15672,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed2), + .DDLY(a7ddrphy_dq_i_delayed2), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data2[7]), - .Q2(soc_a7ddrphy_dq_i_data2[6]), - .Q3(soc_a7ddrphy_dq_i_data2[5]), - .Q4(soc_a7ddrphy_dq_i_data2[4]), - .Q5(soc_a7ddrphy_dq_i_data2[3]), - .Q6(soc_a7ddrphy_dq_i_data2[2]), - .Q7(soc_a7ddrphy_dq_i_data2[1]), - .Q8(soc_a7ddrphy_dq_i_data2[0]) + .Q1(a7ddrphy_dq_i_data2[7]), + .Q2(a7ddrphy_dq_i_data2[6]), + .Q3(a7ddrphy_dq_i_data2[5]), + .Q4(a7ddrphy_dq_i_data2[4]), + .Q5(a7ddrphy_dq_i_data2[3]), + .Q6(a7ddrphy_dq_i_data2[2]), + .Q7(a7ddrphy_dq_i_data2[1]), + .Q8(a7ddrphy_dq_i_data2[0]) ); IDELAYE2 #( @@ -18646,19 +15695,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_4 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay2), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay2), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed2) + .DATAOUT(a7ddrphy_dq_i_delayed2) ); IOBUF IOBUF_2( - .I(soc_a7ddrphy_dq_o_nodelay2), - .T(soc_a7ddrphy_dq_t2), + .I(a7ddrphy_dq_o_nodelay2), + .T(a7ddrphy_dq_t2), .IO(ddram_dq[2]), - .O(soc_a7ddrphy_dq_i_nodelay2) + .O(a7ddrphy_dq_i_nodelay2) ); OSERDESE2 #( @@ -18670,20 +15719,20 @@ OSERDESE2 #( ) OSERDESE2_33 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[3]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[19]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[3]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[19]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[3]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[19]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[3]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[19]), + .D1(a7ddrphy_dfi_p0_wrdata[3]), + .D2(a7ddrphy_dfi_p0_wrdata[19]), + .D3(a7ddrphy_dfi_p1_wrdata[3]), + .D4(a7ddrphy_dfi_p1_wrdata[19]), + .D5(a7ddrphy_dfi_p2_wrdata[3]), + .D6(a7ddrphy_dfi_p2_wrdata[19]), + .D7(a7ddrphy_dfi_p3_wrdata[3]), + .D8(a7ddrphy_dfi_p3_wrdata[19]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay3), - .TQ(soc_a7ddrphy_dq_t3) + .OQ(a7ddrphy_dq_o_nodelay3), + .TQ(a7ddrphy_dq_t3) ); ISERDESE2 #( @@ -18699,16 +15748,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed3), + .DDLY(a7ddrphy_dq_i_delayed3), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data3[7]), - .Q2(soc_a7ddrphy_dq_i_data3[6]), - .Q3(soc_a7ddrphy_dq_i_data3[5]), - .Q4(soc_a7ddrphy_dq_i_data3[4]), - .Q5(soc_a7ddrphy_dq_i_data3[3]), - .Q6(soc_a7ddrphy_dq_i_data3[2]), - .Q7(soc_a7ddrphy_dq_i_data3[1]), - .Q8(soc_a7ddrphy_dq_i_data3[0]) + .Q1(a7ddrphy_dq_i_data3[7]), + .Q2(a7ddrphy_dq_i_data3[6]), + .Q3(a7ddrphy_dq_i_data3[5]), + .Q4(a7ddrphy_dq_i_data3[4]), + .Q5(a7ddrphy_dq_i_data3[3]), + .Q6(a7ddrphy_dq_i_data3[2]), + .Q7(a7ddrphy_dq_i_data3[1]), + .Q8(a7ddrphy_dq_i_data3[0]) ); IDELAYE2 #( @@ -18722,19 +15771,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_5 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay3), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay3), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed3) + .DATAOUT(a7ddrphy_dq_i_delayed3) ); IOBUF IOBUF_3( - .I(soc_a7ddrphy_dq_o_nodelay3), - .T(soc_a7ddrphy_dq_t3), + .I(a7ddrphy_dq_o_nodelay3), + .T(a7ddrphy_dq_t3), .IO(ddram_dq[3]), - .O(soc_a7ddrphy_dq_i_nodelay3) + .O(a7ddrphy_dq_i_nodelay3) ); OSERDESE2 #( @@ -18746,20 +15795,20 @@ OSERDESE2 #( ) OSERDESE2_34 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[4]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[20]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[4]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[20]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[4]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[20]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[4]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[20]), + .D1(a7ddrphy_dfi_p0_wrdata[4]), + .D2(a7ddrphy_dfi_p0_wrdata[20]), + .D3(a7ddrphy_dfi_p1_wrdata[4]), + .D4(a7ddrphy_dfi_p1_wrdata[20]), + .D5(a7ddrphy_dfi_p2_wrdata[4]), + .D6(a7ddrphy_dfi_p2_wrdata[20]), + .D7(a7ddrphy_dfi_p3_wrdata[4]), + .D8(a7ddrphy_dfi_p3_wrdata[20]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay4), - .TQ(soc_a7ddrphy_dq_t4) + .OQ(a7ddrphy_dq_o_nodelay4), + .TQ(a7ddrphy_dq_t4) ); ISERDESE2 #( @@ -18775,16 +15824,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed4), + .DDLY(a7ddrphy_dq_i_delayed4), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data4[7]), - .Q2(soc_a7ddrphy_dq_i_data4[6]), - .Q3(soc_a7ddrphy_dq_i_data4[5]), - .Q4(soc_a7ddrphy_dq_i_data4[4]), - .Q5(soc_a7ddrphy_dq_i_data4[3]), - .Q6(soc_a7ddrphy_dq_i_data4[2]), - .Q7(soc_a7ddrphy_dq_i_data4[1]), - .Q8(soc_a7ddrphy_dq_i_data4[0]) + .Q1(a7ddrphy_dq_i_data4[7]), + .Q2(a7ddrphy_dq_i_data4[6]), + .Q3(a7ddrphy_dq_i_data4[5]), + .Q4(a7ddrphy_dq_i_data4[4]), + .Q5(a7ddrphy_dq_i_data4[3]), + .Q6(a7ddrphy_dq_i_data4[2]), + .Q7(a7ddrphy_dq_i_data4[1]), + .Q8(a7ddrphy_dq_i_data4[0]) ); IDELAYE2 #( @@ -18798,19 +15847,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_6 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay4), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay4), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed4) + .DATAOUT(a7ddrphy_dq_i_delayed4) ); IOBUF IOBUF_4( - .I(soc_a7ddrphy_dq_o_nodelay4), - .T(soc_a7ddrphy_dq_t4), + .I(a7ddrphy_dq_o_nodelay4), + .T(a7ddrphy_dq_t4), .IO(ddram_dq[4]), - .O(soc_a7ddrphy_dq_i_nodelay4) + .O(a7ddrphy_dq_i_nodelay4) ); OSERDESE2 #( @@ -18822,20 +15871,20 @@ OSERDESE2 #( ) OSERDESE2_35 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[5]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[21]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[5]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[21]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[5]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[21]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[5]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[21]), + .D1(a7ddrphy_dfi_p0_wrdata[5]), + .D2(a7ddrphy_dfi_p0_wrdata[21]), + .D3(a7ddrphy_dfi_p1_wrdata[5]), + .D4(a7ddrphy_dfi_p1_wrdata[21]), + .D5(a7ddrphy_dfi_p2_wrdata[5]), + .D6(a7ddrphy_dfi_p2_wrdata[21]), + .D7(a7ddrphy_dfi_p3_wrdata[5]), + .D8(a7ddrphy_dfi_p3_wrdata[21]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay5), - .TQ(soc_a7ddrphy_dq_t5) + .OQ(a7ddrphy_dq_o_nodelay5), + .TQ(a7ddrphy_dq_t5) ); ISERDESE2 #( @@ -18851,16 +15900,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed5), + .DDLY(a7ddrphy_dq_i_delayed5), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data5[7]), - .Q2(soc_a7ddrphy_dq_i_data5[6]), - .Q3(soc_a7ddrphy_dq_i_data5[5]), - .Q4(soc_a7ddrphy_dq_i_data5[4]), - .Q5(soc_a7ddrphy_dq_i_data5[3]), - .Q6(soc_a7ddrphy_dq_i_data5[2]), - .Q7(soc_a7ddrphy_dq_i_data5[1]), - .Q8(soc_a7ddrphy_dq_i_data5[0]) + .Q1(a7ddrphy_dq_i_data5[7]), + .Q2(a7ddrphy_dq_i_data5[6]), + .Q3(a7ddrphy_dq_i_data5[5]), + .Q4(a7ddrphy_dq_i_data5[4]), + .Q5(a7ddrphy_dq_i_data5[3]), + .Q6(a7ddrphy_dq_i_data5[2]), + .Q7(a7ddrphy_dq_i_data5[1]), + .Q8(a7ddrphy_dq_i_data5[0]) ); IDELAYE2 #( @@ -18874,19 +15923,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_7 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay5), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay5), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed5) + .DATAOUT(a7ddrphy_dq_i_delayed5) ); IOBUF IOBUF_5( - .I(soc_a7ddrphy_dq_o_nodelay5), - .T(soc_a7ddrphy_dq_t5), + .I(a7ddrphy_dq_o_nodelay5), + .T(a7ddrphy_dq_t5), .IO(ddram_dq[5]), - .O(soc_a7ddrphy_dq_i_nodelay5) + .O(a7ddrphy_dq_i_nodelay5) ); OSERDESE2 #( @@ -18898,20 +15947,20 @@ OSERDESE2 #( ) OSERDESE2_36 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[6]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[22]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[6]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[22]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[6]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[22]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[6]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[22]), + .D1(a7ddrphy_dfi_p0_wrdata[6]), + .D2(a7ddrphy_dfi_p0_wrdata[22]), + .D3(a7ddrphy_dfi_p1_wrdata[6]), + .D4(a7ddrphy_dfi_p1_wrdata[22]), + .D5(a7ddrphy_dfi_p2_wrdata[6]), + .D6(a7ddrphy_dfi_p2_wrdata[22]), + .D7(a7ddrphy_dfi_p3_wrdata[6]), + .D8(a7ddrphy_dfi_p3_wrdata[22]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay6), - .TQ(soc_a7ddrphy_dq_t6) + .OQ(a7ddrphy_dq_o_nodelay6), + .TQ(a7ddrphy_dq_t6) ); ISERDESE2 #( @@ -18927,16 +15976,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed6), + .DDLY(a7ddrphy_dq_i_delayed6), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data6[7]), - .Q2(soc_a7ddrphy_dq_i_data6[6]), - .Q3(soc_a7ddrphy_dq_i_data6[5]), - .Q4(soc_a7ddrphy_dq_i_data6[4]), - .Q5(soc_a7ddrphy_dq_i_data6[3]), - .Q6(soc_a7ddrphy_dq_i_data6[2]), - .Q7(soc_a7ddrphy_dq_i_data6[1]), - .Q8(soc_a7ddrphy_dq_i_data6[0]) + .Q1(a7ddrphy_dq_i_data6[7]), + .Q2(a7ddrphy_dq_i_data6[6]), + .Q3(a7ddrphy_dq_i_data6[5]), + .Q4(a7ddrphy_dq_i_data6[4]), + .Q5(a7ddrphy_dq_i_data6[3]), + .Q6(a7ddrphy_dq_i_data6[2]), + .Q7(a7ddrphy_dq_i_data6[1]), + .Q8(a7ddrphy_dq_i_data6[0]) ); IDELAYE2 #( @@ -18950,19 +15999,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_8 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay6), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay6), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed6) + .DATAOUT(a7ddrphy_dq_i_delayed6) ); IOBUF IOBUF_6( - .I(soc_a7ddrphy_dq_o_nodelay6), - .T(soc_a7ddrphy_dq_t6), + .I(a7ddrphy_dq_o_nodelay6), + .T(a7ddrphy_dq_t6), .IO(ddram_dq[6]), - .O(soc_a7ddrphy_dq_i_nodelay6) + .O(a7ddrphy_dq_i_nodelay6) ); OSERDESE2 #( @@ -18974,20 +16023,20 @@ OSERDESE2 #( ) OSERDESE2_37 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[7]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[23]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[7]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[23]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[7]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[23]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[7]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[23]), + .D1(a7ddrphy_dfi_p0_wrdata[7]), + .D2(a7ddrphy_dfi_p0_wrdata[23]), + .D3(a7ddrphy_dfi_p1_wrdata[7]), + .D4(a7ddrphy_dfi_p1_wrdata[23]), + .D5(a7ddrphy_dfi_p2_wrdata[7]), + .D6(a7ddrphy_dfi_p2_wrdata[23]), + .D7(a7ddrphy_dfi_p3_wrdata[7]), + .D8(a7ddrphy_dfi_p3_wrdata[23]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay7), - .TQ(soc_a7ddrphy_dq_t7) + .OQ(a7ddrphy_dq_o_nodelay7), + .TQ(a7ddrphy_dq_t7) ); ISERDESE2 #( @@ -19003,16 +16052,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed7), + .DDLY(a7ddrphy_dq_i_delayed7), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data7[7]), - .Q2(soc_a7ddrphy_dq_i_data7[6]), - .Q3(soc_a7ddrphy_dq_i_data7[5]), - .Q4(soc_a7ddrphy_dq_i_data7[4]), - .Q5(soc_a7ddrphy_dq_i_data7[3]), - .Q6(soc_a7ddrphy_dq_i_data7[2]), - .Q7(soc_a7ddrphy_dq_i_data7[1]), - .Q8(soc_a7ddrphy_dq_i_data7[0]) + .Q1(a7ddrphy_dq_i_data7[7]), + .Q2(a7ddrphy_dq_i_data7[6]), + .Q3(a7ddrphy_dq_i_data7[5]), + .Q4(a7ddrphy_dq_i_data7[4]), + .Q5(a7ddrphy_dq_i_data7[3]), + .Q6(a7ddrphy_dq_i_data7[2]), + .Q7(a7ddrphy_dq_i_data7[1]), + .Q8(a7ddrphy_dq_i_data7[0]) ); IDELAYE2 #( @@ -19026,19 +16075,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_9 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay7), + .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay7), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed7) + .DATAOUT(a7ddrphy_dq_i_delayed7) ); IOBUF IOBUF_7( - .I(soc_a7ddrphy_dq_o_nodelay7), - .T(soc_a7ddrphy_dq_t7), + .I(a7ddrphy_dq_o_nodelay7), + .T(a7ddrphy_dq_t7), .IO(ddram_dq[7]), - .O(soc_a7ddrphy_dq_i_nodelay7) + .O(a7ddrphy_dq_i_nodelay7) ); OSERDESE2 #( @@ -19050,20 +16099,20 @@ OSERDESE2 #( ) OSERDESE2_38 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[8]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[24]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[8]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[24]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[8]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[24]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[8]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[24]), + .D1(a7ddrphy_dfi_p0_wrdata[8]), + .D2(a7ddrphy_dfi_p0_wrdata[24]), + .D3(a7ddrphy_dfi_p1_wrdata[8]), + .D4(a7ddrphy_dfi_p1_wrdata[24]), + .D5(a7ddrphy_dfi_p2_wrdata[8]), + .D6(a7ddrphy_dfi_p2_wrdata[24]), + .D7(a7ddrphy_dfi_p3_wrdata[8]), + .D8(a7ddrphy_dfi_p3_wrdata[24]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay8), - .TQ(soc_a7ddrphy_dq_t8) + .OQ(a7ddrphy_dq_o_nodelay8), + .TQ(a7ddrphy_dq_t8) ); ISERDESE2 #( @@ -19079,16 +16128,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed8), + .DDLY(a7ddrphy_dq_i_delayed8), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data8[7]), - .Q2(soc_a7ddrphy_dq_i_data8[6]), - .Q3(soc_a7ddrphy_dq_i_data8[5]), - .Q4(soc_a7ddrphy_dq_i_data8[4]), - .Q5(soc_a7ddrphy_dq_i_data8[3]), - .Q6(soc_a7ddrphy_dq_i_data8[2]), - .Q7(soc_a7ddrphy_dq_i_data8[1]), - .Q8(soc_a7ddrphy_dq_i_data8[0]) + .Q1(a7ddrphy_dq_i_data8[7]), + .Q2(a7ddrphy_dq_i_data8[6]), + .Q3(a7ddrphy_dq_i_data8[5]), + .Q4(a7ddrphy_dq_i_data8[4]), + .Q5(a7ddrphy_dq_i_data8[3]), + .Q6(a7ddrphy_dq_i_data8[2]), + .Q7(a7ddrphy_dq_i_data8[1]), + .Q8(a7ddrphy_dq_i_data8[0]) ); IDELAYE2 #( @@ -19102,19 +16151,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_10 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay8), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay8), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed8) + .DATAOUT(a7ddrphy_dq_i_delayed8) ); IOBUF IOBUF_8( - .I(soc_a7ddrphy_dq_o_nodelay8), - .T(soc_a7ddrphy_dq_t8), + .I(a7ddrphy_dq_o_nodelay8), + .T(a7ddrphy_dq_t8), .IO(ddram_dq[8]), - .O(soc_a7ddrphy_dq_i_nodelay8) + .O(a7ddrphy_dq_i_nodelay8) ); OSERDESE2 #( @@ -19126,20 +16175,20 @@ OSERDESE2 #( ) OSERDESE2_39 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[9]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[25]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[9]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[25]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[9]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[25]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[9]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[25]), + .D1(a7ddrphy_dfi_p0_wrdata[9]), + .D2(a7ddrphy_dfi_p0_wrdata[25]), + .D3(a7ddrphy_dfi_p1_wrdata[9]), + .D4(a7ddrphy_dfi_p1_wrdata[25]), + .D5(a7ddrphy_dfi_p2_wrdata[9]), + .D6(a7ddrphy_dfi_p2_wrdata[25]), + .D7(a7ddrphy_dfi_p3_wrdata[9]), + .D8(a7ddrphy_dfi_p3_wrdata[25]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay9), - .TQ(soc_a7ddrphy_dq_t9) + .OQ(a7ddrphy_dq_o_nodelay9), + .TQ(a7ddrphy_dq_t9) ); ISERDESE2 #( @@ -19155,16 +16204,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed9), + .DDLY(a7ddrphy_dq_i_delayed9), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data9[7]), - .Q2(soc_a7ddrphy_dq_i_data9[6]), - .Q3(soc_a7ddrphy_dq_i_data9[5]), - .Q4(soc_a7ddrphy_dq_i_data9[4]), - .Q5(soc_a7ddrphy_dq_i_data9[3]), - .Q6(soc_a7ddrphy_dq_i_data9[2]), - .Q7(soc_a7ddrphy_dq_i_data9[1]), - .Q8(soc_a7ddrphy_dq_i_data9[0]) + .Q1(a7ddrphy_dq_i_data9[7]), + .Q2(a7ddrphy_dq_i_data9[6]), + .Q3(a7ddrphy_dq_i_data9[5]), + .Q4(a7ddrphy_dq_i_data9[4]), + .Q5(a7ddrphy_dq_i_data9[3]), + .Q6(a7ddrphy_dq_i_data9[2]), + .Q7(a7ddrphy_dq_i_data9[1]), + .Q8(a7ddrphy_dq_i_data9[0]) ); IDELAYE2 #( @@ -19178,19 +16227,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_11 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay9), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay9), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed9) + .DATAOUT(a7ddrphy_dq_i_delayed9) ); IOBUF IOBUF_9( - .I(soc_a7ddrphy_dq_o_nodelay9), - .T(soc_a7ddrphy_dq_t9), + .I(a7ddrphy_dq_o_nodelay9), + .T(a7ddrphy_dq_t9), .IO(ddram_dq[9]), - .O(soc_a7ddrphy_dq_i_nodelay9) + .O(a7ddrphy_dq_i_nodelay9) ); OSERDESE2 #( @@ -19202,20 +16251,20 @@ OSERDESE2 #( ) OSERDESE2_40 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[10]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[26]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[10]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[26]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[10]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[26]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[10]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[26]), + .D1(a7ddrphy_dfi_p0_wrdata[10]), + .D2(a7ddrphy_dfi_p0_wrdata[26]), + .D3(a7ddrphy_dfi_p1_wrdata[10]), + .D4(a7ddrphy_dfi_p1_wrdata[26]), + .D5(a7ddrphy_dfi_p2_wrdata[10]), + .D6(a7ddrphy_dfi_p2_wrdata[26]), + .D7(a7ddrphy_dfi_p3_wrdata[10]), + .D8(a7ddrphy_dfi_p3_wrdata[26]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay10), - .TQ(soc_a7ddrphy_dq_t10) + .OQ(a7ddrphy_dq_o_nodelay10), + .TQ(a7ddrphy_dq_t10) ); ISERDESE2 #( @@ -19231,16 +16280,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed10), + .DDLY(a7ddrphy_dq_i_delayed10), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data10[7]), - .Q2(soc_a7ddrphy_dq_i_data10[6]), - .Q3(soc_a7ddrphy_dq_i_data10[5]), - .Q4(soc_a7ddrphy_dq_i_data10[4]), - .Q5(soc_a7ddrphy_dq_i_data10[3]), - .Q6(soc_a7ddrphy_dq_i_data10[2]), - .Q7(soc_a7ddrphy_dq_i_data10[1]), - .Q8(soc_a7ddrphy_dq_i_data10[0]) + .Q1(a7ddrphy_dq_i_data10[7]), + .Q2(a7ddrphy_dq_i_data10[6]), + .Q3(a7ddrphy_dq_i_data10[5]), + .Q4(a7ddrphy_dq_i_data10[4]), + .Q5(a7ddrphy_dq_i_data10[3]), + .Q6(a7ddrphy_dq_i_data10[2]), + .Q7(a7ddrphy_dq_i_data10[1]), + .Q8(a7ddrphy_dq_i_data10[0]) ); IDELAYE2 #( @@ -19254,19 +16303,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_12 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay10), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay10), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed10) + .DATAOUT(a7ddrphy_dq_i_delayed10) ); IOBUF IOBUF_10( - .I(soc_a7ddrphy_dq_o_nodelay10), - .T(soc_a7ddrphy_dq_t10), + .I(a7ddrphy_dq_o_nodelay10), + .T(a7ddrphy_dq_t10), .IO(ddram_dq[10]), - .O(soc_a7ddrphy_dq_i_nodelay10) + .O(a7ddrphy_dq_i_nodelay10) ); OSERDESE2 #( @@ -19278,20 +16327,20 @@ OSERDESE2 #( ) OSERDESE2_41 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[11]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[27]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[11]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[27]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[11]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[27]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[11]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[27]), + .D1(a7ddrphy_dfi_p0_wrdata[11]), + .D2(a7ddrphy_dfi_p0_wrdata[27]), + .D3(a7ddrphy_dfi_p1_wrdata[11]), + .D4(a7ddrphy_dfi_p1_wrdata[27]), + .D5(a7ddrphy_dfi_p2_wrdata[11]), + .D6(a7ddrphy_dfi_p2_wrdata[27]), + .D7(a7ddrphy_dfi_p3_wrdata[11]), + .D8(a7ddrphy_dfi_p3_wrdata[27]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay11), - .TQ(soc_a7ddrphy_dq_t11) + .OQ(a7ddrphy_dq_o_nodelay11), + .TQ(a7ddrphy_dq_t11) ); ISERDESE2 #( @@ -19307,16 +16356,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed11), + .DDLY(a7ddrphy_dq_i_delayed11), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data11[7]), - .Q2(soc_a7ddrphy_dq_i_data11[6]), - .Q3(soc_a7ddrphy_dq_i_data11[5]), - .Q4(soc_a7ddrphy_dq_i_data11[4]), - .Q5(soc_a7ddrphy_dq_i_data11[3]), - .Q6(soc_a7ddrphy_dq_i_data11[2]), - .Q7(soc_a7ddrphy_dq_i_data11[1]), - .Q8(soc_a7ddrphy_dq_i_data11[0]) + .Q1(a7ddrphy_dq_i_data11[7]), + .Q2(a7ddrphy_dq_i_data11[6]), + .Q3(a7ddrphy_dq_i_data11[5]), + .Q4(a7ddrphy_dq_i_data11[4]), + .Q5(a7ddrphy_dq_i_data11[3]), + .Q6(a7ddrphy_dq_i_data11[2]), + .Q7(a7ddrphy_dq_i_data11[1]), + .Q8(a7ddrphy_dq_i_data11[0]) ); IDELAYE2 #( @@ -19330,19 +16379,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_13 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay11), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay11), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed11) + .DATAOUT(a7ddrphy_dq_i_delayed11) ); IOBUF IOBUF_11( - .I(soc_a7ddrphy_dq_o_nodelay11), - .T(soc_a7ddrphy_dq_t11), + .I(a7ddrphy_dq_o_nodelay11), + .T(a7ddrphy_dq_t11), .IO(ddram_dq[11]), - .O(soc_a7ddrphy_dq_i_nodelay11) + .O(a7ddrphy_dq_i_nodelay11) ); OSERDESE2 #( @@ -19354,20 +16403,20 @@ OSERDESE2 #( ) OSERDESE2_42 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[12]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[28]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[12]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[28]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[12]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[28]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[12]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[28]), + .D1(a7ddrphy_dfi_p0_wrdata[12]), + .D2(a7ddrphy_dfi_p0_wrdata[28]), + .D3(a7ddrphy_dfi_p1_wrdata[12]), + .D4(a7ddrphy_dfi_p1_wrdata[28]), + .D5(a7ddrphy_dfi_p2_wrdata[12]), + .D6(a7ddrphy_dfi_p2_wrdata[28]), + .D7(a7ddrphy_dfi_p3_wrdata[12]), + .D8(a7ddrphy_dfi_p3_wrdata[28]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay12), - .TQ(soc_a7ddrphy_dq_t12) + .OQ(a7ddrphy_dq_o_nodelay12), + .TQ(a7ddrphy_dq_t12) ); ISERDESE2 #( @@ -19383,16 +16432,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed12), + .DDLY(a7ddrphy_dq_i_delayed12), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data12[7]), - .Q2(soc_a7ddrphy_dq_i_data12[6]), - .Q3(soc_a7ddrphy_dq_i_data12[5]), - .Q4(soc_a7ddrphy_dq_i_data12[4]), - .Q5(soc_a7ddrphy_dq_i_data12[3]), - .Q6(soc_a7ddrphy_dq_i_data12[2]), - .Q7(soc_a7ddrphy_dq_i_data12[1]), - .Q8(soc_a7ddrphy_dq_i_data12[0]) + .Q1(a7ddrphy_dq_i_data12[7]), + .Q2(a7ddrphy_dq_i_data12[6]), + .Q3(a7ddrphy_dq_i_data12[5]), + .Q4(a7ddrphy_dq_i_data12[4]), + .Q5(a7ddrphy_dq_i_data12[3]), + .Q6(a7ddrphy_dq_i_data12[2]), + .Q7(a7ddrphy_dq_i_data12[1]), + .Q8(a7ddrphy_dq_i_data12[0]) ); IDELAYE2 #( @@ -19406,19 +16455,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_14 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay12), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay12), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed12) + .DATAOUT(a7ddrphy_dq_i_delayed12) ); IOBUF IOBUF_12( - .I(soc_a7ddrphy_dq_o_nodelay12), - .T(soc_a7ddrphy_dq_t12), + .I(a7ddrphy_dq_o_nodelay12), + .T(a7ddrphy_dq_t12), .IO(ddram_dq[12]), - .O(soc_a7ddrphy_dq_i_nodelay12) + .O(a7ddrphy_dq_i_nodelay12) ); OSERDESE2 #( @@ -19430,20 +16479,20 @@ OSERDESE2 #( ) OSERDESE2_43 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[13]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[29]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[13]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[29]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[13]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[29]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[13]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[29]), + .D1(a7ddrphy_dfi_p0_wrdata[13]), + .D2(a7ddrphy_dfi_p0_wrdata[29]), + .D3(a7ddrphy_dfi_p1_wrdata[13]), + .D4(a7ddrphy_dfi_p1_wrdata[29]), + .D5(a7ddrphy_dfi_p2_wrdata[13]), + .D6(a7ddrphy_dfi_p2_wrdata[29]), + .D7(a7ddrphy_dfi_p3_wrdata[13]), + .D8(a7ddrphy_dfi_p3_wrdata[29]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay13), - .TQ(soc_a7ddrphy_dq_t13) + .OQ(a7ddrphy_dq_o_nodelay13), + .TQ(a7ddrphy_dq_t13) ); ISERDESE2 #( @@ -19459,16 +16508,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed13), + .DDLY(a7ddrphy_dq_i_delayed13), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data13[7]), - .Q2(soc_a7ddrphy_dq_i_data13[6]), - .Q3(soc_a7ddrphy_dq_i_data13[5]), - .Q4(soc_a7ddrphy_dq_i_data13[4]), - .Q5(soc_a7ddrphy_dq_i_data13[3]), - .Q6(soc_a7ddrphy_dq_i_data13[2]), - .Q7(soc_a7ddrphy_dq_i_data13[1]), - .Q8(soc_a7ddrphy_dq_i_data13[0]) + .Q1(a7ddrphy_dq_i_data13[7]), + .Q2(a7ddrphy_dq_i_data13[6]), + .Q3(a7ddrphy_dq_i_data13[5]), + .Q4(a7ddrphy_dq_i_data13[4]), + .Q5(a7ddrphy_dq_i_data13[3]), + .Q6(a7ddrphy_dq_i_data13[2]), + .Q7(a7ddrphy_dq_i_data13[1]), + .Q8(a7ddrphy_dq_i_data13[0]) ); IDELAYE2 #( @@ -19482,19 +16531,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_15 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay13), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay13), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed13) + .DATAOUT(a7ddrphy_dq_i_delayed13) ); IOBUF IOBUF_13( - .I(soc_a7ddrphy_dq_o_nodelay13), - .T(soc_a7ddrphy_dq_t13), + .I(a7ddrphy_dq_o_nodelay13), + .T(a7ddrphy_dq_t13), .IO(ddram_dq[13]), - .O(soc_a7ddrphy_dq_i_nodelay13) + .O(a7ddrphy_dq_i_nodelay13) ); OSERDESE2 #( @@ -19506,20 +16555,20 @@ OSERDESE2 #( ) OSERDESE2_44 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[14]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[30]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[14]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[30]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[14]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[30]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[14]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[30]), + .D1(a7ddrphy_dfi_p0_wrdata[14]), + .D2(a7ddrphy_dfi_p0_wrdata[30]), + .D3(a7ddrphy_dfi_p1_wrdata[14]), + .D4(a7ddrphy_dfi_p1_wrdata[30]), + .D5(a7ddrphy_dfi_p2_wrdata[14]), + .D6(a7ddrphy_dfi_p2_wrdata[30]), + .D7(a7ddrphy_dfi_p3_wrdata[14]), + .D8(a7ddrphy_dfi_p3_wrdata[30]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay14), - .TQ(soc_a7ddrphy_dq_t14) + .OQ(a7ddrphy_dq_o_nodelay14), + .TQ(a7ddrphy_dq_t14) ); ISERDESE2 #( @@ -19535,16 +16584,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed14), + .DDLY(a7ddrphy_dq_i_delayed14), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data14[7]), - .Q2(soc_a7ddrphy_dq_i_data14[6]), - .Q3(soc_a7ddrphy_dq_i_data14[5]), - .Q4(soc_a7ddrphy_dq_i_data14[4]), - .Q5(soc_a7ddrphy_dq_i_data14[3]), - .Q6(soc_a7ddrphy_dq_i_data14[2]), - .Q7(soc_a7ddrphy_dq_i_data14[1]), - .Q8(soc_a7ddrphy_dq_i_data14[0]) + .Q1(a7ddrphy_dq_i_data14[7]), + .Q2(a7ddrphy_dq_i_data14[6]), + .Q3(a7ddrphy_dq_i_data14[5]), + .Q4(a7ddrphy_dq_i_data14[4]), + .Q5(a7ddrphy_dq_i_data14[3]), + .Q6(a7ddrphy_dq_i_data14[2]), + .Q7(a7ddrphy_dq_i_data14[1]), + .Q8(a7ddrphy_dq_i_data14[0]) ); IDELAYE2 #( @@ -19558,19 +16607,19 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_16 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay14), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay14), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed14) + .DATAOUT(a7ddrphy_dq_i_delayed14) ); IOBUF IOBUF_14( - .I(soc_a7ddrphy_dq_o_nodelay14), - .T(soc_a7ddrphy_dq_t14), + .I(a7ddrphy_dq_o_nodelay14), + .T(a7ddrphy_dq_t14), .IO(ddram_dq[14]), - .O(soc_a7ddrphy_dq_i_nodelay14) + .O(a7ddrphy_dq_i_nodelay14) ); OSERDESE2 #( @@ -19582,20 +16631,20 @@ OSERDESE2 #( ) OSERDESE2_45 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), - .D1(soc_a7ddrphy_dfi_p0_wrdata[15]), - .D2(soc_a7ddrphy_dfi_p0_wrdata[31]), - .D3(soc_a7ddrphy_dfi_p1_wrdata[15]), - .D4(soc_a7ddrphy_dfi_p1_wrdata[31]), - .D5(soc_a7ddrphy_dfi_p2_wrdata[15]), - .D6(soc_a7ddrphy_dfi_p2_wrdata[31]), - .D7(soc_a7ddrphy_dfi_p3_wrdata[15]), - .D8(soc_a7ddrphy_dfi_p3_wrdata[31]), + .D1(a7ddrphy_dfi_p0_wrdata[15]), + .D2(a7ddrphy_dfi_p0_wrdata[31]), + .D3(a7ddrphy_dfi_p1_wrdata[15]), + .D4(a7ddrphy_dfi_p1_wrdata[31]), + .D5(a7ddrphy_dfi_p2_wrdata[15]), + .D6(a7ddrphy_dfi_p2_wrdata[31]), + .D7(a7ddrphy_dfi_p3_wrdata[15]), + .D8(a7ddrphy_dfi_p3_wrdata[31]), .OCE(1'd1), .RST(sys_rst), - .T1((~soc_a7ddrphy_dq_oe_delayed)), + .T1((~a7ddrphy_dq_oe_delayed)), .TCE(1'd1), - .OQ(soc_a7ddrphy_dq_o_nodelay15), - .TQ(soc_a7ddrphy_dq_t15) + .OQ(a7ddrphy_dq_o_nodelay15), + .TQ(a7ddrphy_dq_t15) ); ISERDESE2 #( @@ -19611,16 +16660,16 @@ ISERDESE2 #( .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), - .DDLY(soc_a7ddrphy_dq_i_delayed15), + .DDLY(a7ddrphy_dq_i_delayed15), .RST(sys_rst), - .Q1(soc_a7ddrphy_dq_i_data15[7]), - .Q2(soc_a7ddrphy_dq_i_data15[6]), - .Q3(soc_a7ddrphy_dq_i_data15[5]), - .Q4(soc_a7ddrphy_dq_i_data15[4]), - .Q5(soc_a7ddrphy_dq_i_data15[3]), - .Q6(soc_a7ddrphy_dq_i_data15[2]), - .Q7(soc_a7ddrphy_dq_i_data15[1]), - .Q8(soc_a7ddrphy_dq_i_data15[0]) + .Q1(a7ddrphy_dq_i_data15[7]), + .Q2(a7ddrphy_dq_i_data15[6]), + .Q3(a7ddrphy_dq_i_data15[5]), + .Q4(a7ddrphy_dq_i_data15[4]), + .Q5(a7ddrphy_dq_i_data15[3]), + .Q6(a7ddrphy_dq_i_data15[2]), + .Q7(a7ddrphy_dq_i_data15[1]), + .Q8(a7ddrphy_dq_i_data15[0]) ); IDELAYE2 #( @@ -19634,163 +16683,132 @@ IDELAYE2 #( .SIGNAL_PATTERN("DATA") ) IDELAYE2_17 ( .C(sys_clk), - .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)), - .IDATAIN(soc_a7ddrphy_dq_i_nodelay15), + .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(a7ddrphy_dq_i_nodelay15), .INC(1'd1), - .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)), + .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)), .LDPIPEEN(1'd0), - .DATAOUT(soc_a7ddrphy_dq_i_delayed15) + .DATAOUT(a7ddrphy_dq_i_delayed15) ); IOBUF IOBUF_15( - .I(soc_a7ddrphy_dq_o_nodelay15), - .T(soc_a7ddrphy_dq_t15), + .I(a7ddrphy_dq_o_nodelay15), + .T(a7ddrphy_dq_t15), .IO(ddram_dq[15]), - .O(soc_a7ddrphy_dq_i_nodelay15) + .O(a7ddrphy_dq_i_nodelay15) ); -reg [24:0] storage_2[0:15]; -reg [24:0] memdat_5; +reg [24:0] storage[0:15]; +reg [24:0] memdat; always @(posedge sys_clk) begin - if (soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we) - storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; - memdat_5 <= storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) + storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; + memdat <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat_5; -assign soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; -reg [24:0] storage_3[0:15]; -reg [24:0] memdat_6; +reg [24:0] storage_1[0:15]; +reg [24:0] memdat_1; always @(posedge sys_clk) begin - if (soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we) - storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; - memdat_6 <= storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) + storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; + memdat_1 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_6; -assign soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; -reg [24:0] storage_4[0:15]; -reg [24:0] memdat_7; +reg [24:0] storage_2[0:15]; +reg [24:0] memdat_2; always @(posedge sys_clk) begin - if (soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we) - storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; - memdat_7 <= storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) + storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; + memdat_2 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_7; -assign soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; -reg [24:0] storage_5[0:15]; -reg [24:0] memdat_8; +reg [24:0] storage_3[0:15]; +reg [24:0] memdat_3; always @(posedge sys_clk) begin - if (soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we) - storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; - memdat_8 <= storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) + storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; + memdat_3 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_8; -assign soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; -reg [24:0] storage_6[0:15]; -reg [24:0] memdat_9; +reg [24:0] storage_4[0:15]; +reg [24:0] memdat_4; always @(posedge sys_clk) begin - if (soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we) - storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; - memdat_9 <= storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) + storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; + memdat_4 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_9; -assign soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; -reg [24:0] storage_7[0:15]; -reg [24:0] memdat_10; +reg [24:0] storage_5[0:15]; +reg [24:0] memdat_5; always @(posedge sys_clk) begin - if (soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we) - storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; - memdat_10 <= storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) + storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; + memdat_5 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_10; -assign soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; -reg [24:0] storage_8[0:15]; -reg [24:0] memdat_11; +reg [24:0] storage_6[0:15]; +reg [24:0] memdat_6; always @(posedge sys_clk) begin - if (soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we) - storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; - memdat_11 <= storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) + storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; + memdat_6 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_11; -assign soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; -reg [24:0] storage_9[0:15]; -reg [24:0] memdat_12; +reg [24:0] storage_7[0:15]; +reg [24:0] memdat_7; always @(posedge sys_clk) begin - if (soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we) - storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; - memdat_12 <= storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) + storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; + memdat_7 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_12; -assign soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr]; - -VexRiscv VexRiscv( - .clk(sys_clk), - .dBusWishbone_ACK(soc_litedramcore_cpu_dbus_ack), - .dBusWishbone_DAT_MISO(soc_litedramcore_cpu_dbus_dat_r), - .dBusWishbone_ERR(soc_litedramcore_cpu_dbus_err), - .externalInterruptArray(soc_litedramcore_cpu_interrupt), - .externalResetVector(soc_litedramcore_vexriscv), - .iBusWishbone_ACK(soc_litedramcore_cpu_ibus_ack), - .iBusWishbone_DAT_MISO(soc_litedramcore_cpu_ibus_dat_r), - .iBusWishbone_ERR(soc_litedramcore_cpu_ibus_err), - .reset((sys_rst | soc_litedramcore_cpu_reset)), - .softwareInterrupt(1'd0), - .timerInterrupt(1'd0), - .dBusWishbone_ADR(soc_litedramcore_cpu_dbus_adr), - .dBusWishbone_BTE(soc_litedramcore_cpu_dbus_bte), - .dBusWishbone_CTI(soc_litedramcore_cpu_dbus_cti), - .dBusWishbone_CYC(soc_litedramcore_cpu_dbus_cyc), - .dBusWishbone_DAT_MOSI(soc_litedramcore_cpu_dbus_dat_w), - .dBusWishbone_SEL(soc_litedramcore_cpu_dbus_sel), - .dBusWishbone_STB(soc_litedramcore_cpu_dbus_stb), - .dBusWishbone_WE(soc_litedramcore_cpu_dbus_we), - .iBusWishbone_ADR(soc_litedramcore_cpu_ibus_adr), - .iBusWishbone_BTE(soc_litedramcore_cpu_ibus_bte), - .iBusWishbone_CTI(soc_litedramcore_cpu_ibus_cti), - .iBusWishbone_CYC(soc_litedramcore_cpu_ibus_cyc), - .iBusWishbone_DAT_MOSI(soc_litedramcore_cpu_ibus_dat_w), - .iBusWishbone_SEL(soc_litedramcore_cpu_ibus_sel), - .iBusWishbone_STB(soc_litedramcore_cpu_ibus_stb), - .iBusWishbone_WE(soc_litedramcore_cpu_ibus_we) -); +assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; PLLE2_ADV #( .CLKFBOUT_MULT(5'd16), @@ -19805,14 +16823,14 @@ PLLE2_ADV #( .REF_JITTER1(0.01), .STARTUP_WAIT("FALSE") ) PLLE2_ADV ( - .CLKFBIN(vns_pll_fb0), - .CLKIN1(soc_s7pll0_clkin), - .RST(soc_sys_pll_reset), - .CLKFBOUT(vns_pll_fb0), - .CLKOUT0(soc_s7pll0_clkout0), - .CLKOUT1(soc_s7pll0_clkout1), - .CLKOUT2(soc_s7pll0_clkout2), - .LOCKED(soc_sys_pll_locked) + .CLKFBIN(pll_fb0), + .CLKIN1(s7pll0_clkin), + .RST(sys_pll_reset), + .CLKFBOUT(pll_fb0), + .CLKOUT0(s7pll0_clkout0), + .CLKOUT1(s7pll0_clkout1), + .CLKOUT2(s7pll0_clkout2), + .LOCKED(sys_pll_locked) ); PLLE2_ADV #( @@ -19824,12 +16842,12 @@ PLLE2_ADV #( .REF_JITTER1(0.01), .STARTUP_WAIT("FALSE") ) PLLE2_ADV_1 ( - .CLKFBIN(vns_pll_fb1), - .CLKIN1(soc_s7pll1_clkin), - .RST(soc_iodelay_pll_reset), - .CLKFBOUT(vns_pll_fb1), - .CLKOUT0(soc_s7pll1_clkout), - .LOCKED(soc_iodelay_pll_locked) + .CLKFBIN(pll_fb1), + .CLKIN1(s7pll1_clkin), + .RST(iodelay_pll_reset), + .CLKFBOUT(pll_fb1), + .CLKOUT0(s7pll1_clkout), + .LOCKED(iodelay_pll_locked) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( @@ -19838,8 +16856,8 @@ PLLE2_ADV #( .C(sys_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl0), - .Q(vns_xilinxasyncresetsynchronizerimpl0_rst_meta) + .PRE(xilinxasyncresetsynchronizerimpl0), + .Q(xilinxasyncresetsynchronizerimpl0_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -19847,8 +16865,8 @@ PLLE2_ADV #( ) FDPE_1 ( .C(sys_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl0_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl0), + .D(xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl0), .Q(sys_rst) ); @@ -19858,8 +16876,8 @@ PLLE2_ADV #( .C(sys4x_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl1), - .Q(vns_xilinxasyncresetsynchronizerimpl1_rst_meta) + .PRE(xilinxasyncresetsynchronizerimpl1), + .Q(xilinxasyncresetsynchronizerimpl1_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -19867,9 +16885,9 @@ PLLE2_ADV #( ) FDPE_3 ( .C(sys4x_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl1_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl1), - .Q(vns_xilinxasyncresetsynchronizerimpl1_expr) + .D(xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl1), + .Q(xilinxasyncresetsynchronizerimpl1_expr) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( @@ -19878,8 +16896,8 @@ PLLE2_ADV #( .C(sys4x_dqs_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl2), - .Q(vns_xilinxasyncresetsynchronizerimpl2_rst_meta) + .PRE(xilinxasyncresetsynchronizerimpl2), + .Q(xilinxasyncresetsynchronizerimpl2_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -19887,9 +16905,9 @@ PLLE2_ADV #( ) FDPE_5 ( .C(sys4x_dqs_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl2_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl2), - .Q(vns_xilinxasyncresetsynchronizerimpl2_expr) + .D(xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl2), + .Q(xilinxasyncresetsynchronizerimpl2_expr) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( @@ -19898,8 +16916,8 @@ PLLE2_ADV #( .C(iodelay_clk), .CE(1'd1), .D(1'd0), - .PRE(vns_xilinxasyncresetsynchronizerimpl3), - .Q(vns_xilinxasyncresetsynchronizerimpl3_rst_meta) + .PRE(xilinxasyncresetsynchronizerimpl3), + .Q(xilinxasyncresetsynchronizerimpl3_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( @@ -19907,8 +16925,8 @@ PLLE2_ADV #( ) FDPE_7 ( .C(iodelay_clk), .CE(1'd1), - .D(vns_xilinxasyncresetsynchronizerimpl3_rst_meta), - .PRE(vns_xilinxasyncresetsynchronizerimpl3), + .D(xilinxasyncresetsynchronizerimpl3_rst_meta), + .PRE(xilinxasyncresetsynchronizerimpl3), .Q(iodelay_rst) ); diff --git a/soc.vhdl b/soc.vhdl index db52db3..a8ae3c9 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -17,6 +17,7 @@ use work.wishbone_types.all; -- 0xc0000000: SYSCON -- 0xc0002000: UART0 -- 0xc0004000: XICS ICP +-- 0xc0100000: DRAM CSRs -- 0xf0000000: Block RAM (aliased & repeated) -- 0xffff0000: DRAM init code (if any) From e3013f5754ccd78a5da499f0800deea661c5e27c Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Sat, 9 May 2020 11:20:59 +1000 Subject: [PATCH 16/16] litedram: Use 32-bit CSR bus Signed-off-by: Benjamin Herrenschmidt --- litedram/gen-src/generate.py | 2 +- litedram/gen-src/wrapper-mw-init.vhdl | 14 +- litedram/generated/arty/litedram-wrapper.vhdl | 14 +- litedram/generated/arty/litedram_core.init | 1524 ++++++++------- litedram/generated/arty/litedram_core.v | 722 ++----- .../nexys-video/litedram-wrapper.vhdl | 14 +- .../generated/nexys-video/litedram_core.init | 1422 +++++++------- .../generated/nexys-video/litedram_core.v | 1688 +++++++---------- 8 files changed, 2331 insertions(+), 3069 deletions(-) diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py index 8c6b70a..4c24cae 100755 --- a/litedram/gen-src/generate.py +++ b/litedram/gen-src/generate.py @@ -115,7 +115,7 @@ def generate_one(t, mw_init): else: raise ValueError("Unsupported SDRAM PHY: {}".format(core_config["sdram_phy"])) - soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000) + soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000, csr_data_width=32) # Build into build_dir builder = Builder(soc, output_dir=build_dir, compile_gateware=False) diff --git a/litedram/gen-src/wrapper-mw-init.vhdl b/litedram/gen-src/wrapper-mw-init.vhdl index 475e088..46ae4b1 100644 --- a/litedram/gen-src/wrapper-mw-init.vhdl +++ b/litedram/gen-src/wrapper-mw-init.vhdl @@ -82,8 +82,8 @@ architecture behaviour of litedram_wrapper is user_rst : out std_ulogic; csr_port0_adr : in std_ulogic_vector(13 downto 0); csr_port0_we : in std_ulogic; - csr_port0_dat_w : in std_ulogic_vector(7 downto 0); - csr_port0_dat_r : out std_ulogic_vector(7 downto 0); + csr_port0_dat_w : in std_ulogic_vector(31 downto 0); + csr_port0_dat_r : out std_ulogic_vector(31 downto 0); user_port_native_0_cmd_valid : in std_ulogic; user_port_native_0_cmd_ready : out std_ulogic; user_port_native_0_cmd_we : in std_ulogic; @@ -116,8 +116,8 @@ architecture behaviour of litedram_wrapper is signal csr_port0_adr : std_ulogic_vector(13 downto 0); signal csr_port0_we : std_ulogic; - signal csr_port0_dat_w : std_ulogic_vector(7 downto 0); - signal csr_port0_dat_r : std_ulogic_vector(7 downto 0); + signal csr_port0_dat_w : std_ulogic_vector(31 downto 0); + signal csr_port0_dat_r : std_ulogic_vector(31 downto 0); signal csr_port_read_comb : std_ulogic_vector(63 downto 0); signal csr_valid : std_ulogic; signal csr_write_valid : std_ulogic; @@ -205,8 +205,8 @@ begin -- DRAM CSR interface signals. We only support access to the bottom byte csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; csr_write_valid <= wb_in.we and wb_in.sel(0); - csr_port0_adr <= wb_in.adr(13 downto 0) when wb_is_csr = '1' else (others => '0'); - csr_port0_dat_w <= wb_in.dat(7 downto 0); + csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0'); + csr_port0_dat_w <= wb_in.dat(31 downto 0); csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; -- Wishbone out signals @@ -215,7 +215,7 @@ begin user_port0_wdata_ready when state = MWRITE else user_port0_rdata_valid when state = MREAD else '0'; - csr_port_read_comb <= x"00000000000000" & csr_port0_dat_r; + csr_port_read_comb <= x"00000000" & csr_port0_dat_r; wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else wb_init_out.dat when wb_is_init = '1' else user_port0_rdata_data(127 downto 64) when ad3 = '1' else diff --git a/litedram/generated/arty/litedram-wrapper.vhdl b/litedram/generated/arty/litedram-wrapper.vhdl index 475e088..46ae4b1 100644 --- a/litedram/generated/arty/litedram-wrapper.vhdl +++ b/litedram/generated/arty/litedram-wrapper.vhdl @@ -82,8 +82,8 @@ architecture behaviour of litedram_wrapper is user_rst : out std_ulogic; csr_port0_adr : in std_ulogic_vector(13 downto 0); csr_port0_we : in std_ulogic; - csr_port0_dat_w : in std_ulogic_vector(7 downto 0); - csr_port0_dat_r : out std_ulogic_vector(7 downto 0); + csr_port0_dat_w : in std_ulogic_vector(31 downto 0); + csr_port0_dat_r : out std_ulogic_vector(31 downto 0); user_port_native_0_cmd_valid : in std_ulogic; user_port_native_0_cmd_ready : out std_ulogic; user_port_native_0_cmd_we : in std_ulogic; @@ -116,8 +116,8 @@ architecture behaviour of litedram_wrapper is signal csr_port0_adr : std_ulogic_vector(13 downto 0); signal csr_port0_we : std_ulogic; - signal csr_port0_dat_w : std_ulogic_vector(7 downto 0); - signal csr_port0_dat_r : std_ulogic_vector(7 downto 0); + signal csr_port0_dat_w : std_ulogic_vector(31 downto 0); + signal csr_port0_dat_r : std_ulogic_vector(31 downto 0); signal csr_port_read_comb : std_ulogic_vector(63 downto 0); signal csr_valid : std_ulogic; signal csr_write_valid : std_ulogic; @@ -205,8 +205,8 @@ begin -- DRAM CSR interface signals. We only support access to the bottom byte csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; csr_write_valid <= wb_in.we and wb_in.sel(0); - csr_port0_adr <= wb_in.adr(13 downto 0) when wb_is_csr = '1' else (others => '0'); - csr_port0_dat_w <= wb_in.dat(7 downto 0); + csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0'); + csr_port0_dat_w <= wb_in.dat(31 downto 0); csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; -- Wishbone out signals @@ -215,7 +215,7 @@ begin user_port0_wdata_ready when state = MWRITE else user_port0_rdata_valid when state = MREAD else '0'; - csr_port_read_comb <= x"00000000000000" & csr_port0_dat_r; + csr_port_read_comb <= x"00000000" & csr_port0_dat_r; wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else wb_init_out.dat when wb_is_init = '1' else user_port0_rdata_data(127 downto 64) when ad3 = '1' else diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init index 1031ca2..4f7ad0f 100644 --- a/litedram/generated/arty/litedram_core.init +++ b/litedram/generated/arty/litedram_core.init @@ -510,37 +510,37 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -38429f003c4c0001 +38429e003c4c0001 600000003d20c000 7929002061292000 -3d40c000f9228038 +3d40c000f92280a8 614a201839200035 7c0004ac794a0020 4e8000207d2057aa 0000000000000000 3c4c000100000000 -6000000038429ebc -39290010e9228038 +6000000038429dbc +39290010e92280a8 7d204eaa7c0004ac 4082ffe871290008 -e922803860000000 +e92280a860000000 7c604faa7c0004ac 000000004e800020 0000000000000000 -38429e783c4c0001 +38429d783c4c0001 fbc1fff07c0802a6 7fc32214fbe1fff8 f80100107c7f1b78 7fbff040f821ffd1 38210030409e000c -893f000048001b40 +893f000048001ab4 409e000c2f89000a 4bffff813860000d 3bff0001887f0000 4bffffd04bffff75 0100000000000000 3c4c000100000280 -7c0802a638429e14 +7c0802a638429d14 fbe1fff8fbc1fff0 f821fe91f8010010 f88101983bc10020 @@ -549,62 +549,62 @@ f88101983bc10020 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+7ce8305041820010 +419d00207faa3840 +7f65db78e8810060 +7c9e20507fa3eb78 +4bfff9cd7c84f850 +38e000204bfffdd4 +e8e1006098e60000 +f8e1006038e70001 +2b87006c4bffffb4 +409efdb03b200008 +4bfffda87cd83378 +3b2000022b870068 +7cd83378409efd9c +4bfffd903b200001 +4bfffd883b200008 +3b0100413a600020 +993e00004bfffc60 +e92100607d455378 +f921006039290001 +000000004bfffb24 +0000128001000000 +f9e1ff78f9c1ff70 +fa21ff88fa01ff80 +fa61ff98fa41ff90 +faa1ffa8fa81ffa0 +fae1ffb8fac1ffb0 +fb21ffc8fb01ffc0 +fb61ffd8fb41ffd0 +fba1ffe8fb81ffe0 +fbe1fff8fbc1fff0 +4e800020f8010010 +e9e1ff78e9c1ff70 +ea21ff88ea01ff80 +ea61ff98ea41ff90 +eaa1ffa8ea81ffa0 +eae1ffb8eac1ffb0 +eb21ffc8eb01ffc0 +eb61ffd8eb41ffd0 +e8010010eb81ffe0 +7c0803a6eba1ffe8 +ebe1fff8ebc1fff0 +ebc1fff04e800020 +ebe1fff8e8010010 +4e8000207c0803a6 6d6f636c65570a0a 63694d206f742065 2120747461776f72 @@ -1473,10 +1455,10 @@ e8010010ebc1fff0 000000000000002d 30252d2b64323025 0000000000006432 -00000000c0100850 -00000000c01008b8 -00000000c0100920 -00000000c0100988 +00000000c0100830 +00000000c0100860 +00000000c0100890 +00000000c01008c0 6f6e204d41524453 207265646e752077 6572617764726168 diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v index 727e21a..18cb7f1 100644 --- a/litedram/generated/arty/litedram_core.v +++ b/litedram/generated/arty/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 10:54:03 +// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 11:57:11 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, @@ -24,8 +24,8 @@ module litedram_core( output wire init_error, input wire [13:0] csr_port0_adr, input wire csr_port0_we, - input wire [7:0] csr_port0_dat_w, - output wire [7:0] csr_port0_dat_r, + input wire [31:0] csr_port0_dat_w, + output wire [31:0] csr_port0_dat_r, output wire user_clk, output wire user_rst, input wire user_port_native_0_cmd_valid, @@ -1485,8 +1485,8 @@ reg init_error_storage = 1'd0; reg init_error_re = 1'd0; wire [13:0] csr_port_adr; wire csr_port_we; -wire [7:0] csr_port_dat_w; -wire [7:0] csr_port_dat_r; +wire [31:0] csr_port_dat_w; +wire [31:0] csr_port_dat_r; wire user_port_cmd_valid; wire user_port_cmd_ready; wire user_port_cmd_payload_we; @@ -1566,8 +1566,8 @@ reg new_master_rdata_valid7 = 1'd0; reg new_master_rdata_valid8 = 1'd0; wire [13:0] interface0_bank_bus_adr; wire interface0_bank_bus_we; -wire [7:0] interface0_bank_bus_dat_w; -reg [7:0] interface0_bank_bus_dat_r = 8'd0; +wire [31:0] interface0_bank_bus_dat_w; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; wire csrbank0_init_done0_re; wire csrbank0_init_done0_r; wire csrbank0_init_done0_we; @@ -1579,8 +1579,8 @@ wire csrbank0_init_error0_w; reg csrbank0_sel = 1'd0; wire [13:0] interface1_bank_bus_adr; wire interface1_bank_bus_we; -wire [7:0] interface1_bank_bus_dat_w; -reg [7:0] interface1_bank_bus_dat_r = 8'd0; +wire [31:0] interface1_bank_bus_dat_w; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; wire csrbank1_half_sys8x_taps0_re; wire [4:0] csrbank1_half_sys8x_taps0_r; wire csrbank1_half_sys8x_taps0_we; @@ -1596,8 +1596,8 @@ wire [1:0] csrbank1_dly_sel0_w; reg csrbank1_sel = 1'd0; wire [13:0] interface2_bank_bus_adr; wire interface2_bank_bus_we; -wire [7:0] interface2_bank_bus_dat_w; -reg [7:0] interface2_bank_bus_dat_r = 8'd0; +wire [31:0] interface2_bank_bus_dat_w; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; wire csrbank2_dfii_control0_re; wire [3:0] csrbank2_dfii_control0_r; wire csrbank2_dfii_control0_we; @@ -1606,199 +1606,87 @@ wire csrbank2_dfii_pi0_command0_re; wire [5:0] csrbank2_dfii_pi0_command0_r; wire csrbank2_dfii_pi0_command0_we; wire [5:0] csrbank2_dfii_pi0_command0_w; -wire csrbank2_dfii_pi0_address1_re; -wire [5:0] csrbank2_dfii_pi0_address1_r; -wire csrbank2_dfii_pi0_address1_we; -wire [5:0] csrbank2_dfii_pi0_address1_w; wire csrbank2_dfii_pi0_address0_re; -wire [7:0] csrbank2_dfii_pi0_address0_r; +wire [13:0] csrbank2_dfii_pi0_address0_r; wire csrbank2_dfii_pi0_address0_we; -wire [7:0] csrbank2_dfii_pi0_address0_w; +wire [13:0] csrbank2_dfii_pi0_address0_w; wire csrbank2_dfii_pi0_baddress0_re; wire [2:0] csrbank2_dfii_pi0_baddress0_r; wire csrbank2_dfii_pi0_baddress0_we; wire [2:0] csrbank2_dfii_pi0_baddress0_w; -wire csrbank2_dfii_pi0_wrdata3_re; -wire [7:0] csrbank2_dfii_pi0_wrdata3_r; -wire csrbank2_dfii_pi0_wrdata3_we; -wire [7:0] csrbank2_dfii_pi0_wrdata3_w; -wire csrbank2_dfii_pi0_wrdata2_re; -wire [7:0] csrbank2_dfii_pi0_wrdata2_r; -wire csrbank2_dfii_pi0_wrdata2_we; -wire [7:0] csrbank2_dfii_pi0_wrdata2_w; -wire csrbank2_dfii_pi0_wrdata1_re; -wire [7:0] csrbank2_dfii_pi0_wrdata1_r; -wire csrbank2_dfii_pi0_wrdata1_we; -wire [7:0] csrbank2_dfii_pi0_wrdata1_w; wire csrbank2_dfii_pi0_wrdata0_re; -wire [7:0] csrbank2_dfii_pi0_wrdata0_r; +wire [31:0] csrbank2_dfii_pi0_wrdata0_r; wire csrbank2_dfii_pi0_wrdata0_we; -wire [7:0] csrbank2_dfii_pi0_wrdata0_w; -wire csrbank2_dfii_pi0_rddata3_re; -wire [7:0] csrbank2_dfii_pi0_rddata3_r; -wire csrbank2_dfii_pi0_rddata3_we; -wire [7:0] csrbank2_dfii_pi0_rddata3_w; -wire csrbank2_dfii_pi0_rddata2_re; -wire [7:0] csrbank2_dfii_pi0_rddata2_r; -wire csrbank2_dfii_pi0_rddata2_we; -wire [7:0] csrbank2_dfii_pi0_rddata2_w; -wire csrbank2_dfii_pi0_rddata1_re; -wire [7:0] csrbank2_dfii_pi0_rddata1_r; -wire csrbank2_dfii_pi0_rddata1_we; -wire [7:0] csrbank2_dfii_pi0_rddata1_w; -wire csrbank2_dfii_pi0_rddata0_re; -wire [7:0] csrbank2_dfii_pi0_rddata0_r; -wire csrbank2_dfii_pi0_rddata0_we; -wire [7:0] csrbank2_dfii_pi0_rddata0_w; +wire [31:0] csrbank2_dfii_pi0_wrdata0_w; +wire csrbank2_dfii_pi0_rddata_re; +wire [31:0] csrbank2_dfii_pi0_rddata_r; +wire csrbank2_dfii_pi0_rddata_we; +wire [31:0] csrbank2_dfii_pi0_rddata_w; wire csrbank2_dfii_pi1_command0_re; wire [5:0] csrbank2_dfii_pi1_command0_r; wire csrbank2_dfii_pi1_command0_we; wire [5:0] csrbank2_dfii_pi1_command0_w; -wire csrbank2_dfii_pi1_address1_re; -wire [5:0] csrbank2_dfii_pi1_address1_r; -wire csrbank2_dfii_pi1_address1_we; -wire [5:0] csrbank2_dfii_pi1_address1_w; wire csrbank2_dfii_pi1_address0_re; -wire [7:0] csrbank2_dfii_pi1_address0_r; +wire [13:0] csrbank2_dfii_pi1_address0_r; wire csrbank2_dfii_pi1_address0_we; -wire [7:0] csrbank2_dfii_pi1_address0_w; +wire [13:0] csrbank2_dfii_pi1_address0_w; wire csrbank2_dfii_pi1_baddress0_re; wire [2:0] csrbank2_dfii_pi1_baddress0_r; wire csrbank2_dfii_pi1_baddress0_we; wire [2:0] csrbank2_dfii_pi1_baddress0_w; -wire csrbank2_dfii_pi1_wrdata3_re; -wire [7:0] csrbank2_dfii_pi1_wrdata3_r; -wire csrbank2_dfii_pi1_wrdata3_we; -wire [7:0] csrbank2_dfii_pi1_wrdata3_w; -wire csrbank2_dfii_pi1_wrdata2_re; -wire [7:0] csrbank2_dfii_pi1_wrdata2_r; -wire csrbank2_dfii_pi1_wrdata2_we; -wire [7:0] csrbank2_dfii_pi1_wrdata2_w; -wire csrbank2_dfii_pi1_wrdata1_re; -wire [7:0] csrbank2_dfii_pi1_wrdata1_r; -wire csrbank2_dfii_pi1_wrdata1_we; -wire [7:0] csrbank2_dfii_pi1_wrdata1_w; wire csrbank2_dfii_pi1_wrdata0_re; -wire [7:0] csrbank2_dfii_pi1_wrdata0_r; +wire [31:0] csrbank2_dfii_pi1_wrdata0_r; wire csrbank2_dfii_pi1_wrdata0_we; -wire [7:0] csrbank2_dfii_pi1_wrdata0_w; -wire csrbank2_dfii_pi1_rddata3_re; -wire [7:0] csrbank2_dfii_pi1_rddata3_r; -wire csrbank2_dfii_pi1_rddata3_we; -wire [7:0] csrbank2_dfii_pi1_rddata3_w; -wire csrbank2_dfii_pi1_rddata2_re; -wire [7:0] csrbank2_dfii_pi1_rddata2_r; -wire csrbank2_dfii_pi1_rddata2_we; -wire [7:0] csrbank2_dfii_pi1_rddata2_w; -wire csrbank2_dfii_pi1_rddata1_re; -wire [7:0] csrbank2_dfii_pi1_rddata1_r; -wire csrbank2_dfii_pi1_rddata1_we; -wire [7:0] csrbank2_dfii_pi1_rddata1_w; -wire csrbank2_dfii_pi1_rddata0_re; -wire [7:0] csrbank2_dfii_pi1_rddata0_r; -wire csrbank2_dfii_pi1_rddata0_we; -wire [7:0] csrbank2_dfii_pi1_rddata0_w; +wire [31:0] csrbank2_dfii_pi1_wrdata0_w; +wire csrbank2_dfii_pi1_rddata_re; +wire [31:0] csrbank2_dfii_pi1_rddata_r; +wire csrbank2_dfii_pi1_rddata_we; +wire [31:0] csrbank2_dfii_pi1_rddata_w; wire csrbank2_dfii_pi2_command0_re; wire [5:0] csrbank2_dfii_pi2_command0_r; wire csrbank2_dfii_pi2_command0_we; wire [5:0] csrbank2_dfii_pi2_command0_w; -wire csrbank2_dfii_pi2_address1_re; -wire [5:0] csrbank2_dfii_pi2_address1_r; -wire csrbank2_dfii_pi2_address1_we; -wire [5:0] csrbank2_dfii_pi2_address1_w; wire csrbank2_dfii_pi2_address0_re; -wire [7:0] csrbank2_dfii_pi2_address0_r; +wire [13:0] csrbank2_dfii_pi2_address0_r; wire csrbank2_dfii_pi2_address0_we; -wire [7:0] csrbank2_dfii_pi2_address0_w; +wire [13:0] csrbank2_dfii_pi2_address0_w; wire csrbank2_dfii_pi2_baddress0_re; wire [2:0] csrbank2_dfii_pi2_baddress0_r; wire csrbank2_dfii_pi2_baddress0_we; wire [2:0] csrbank2_dfii_pi2_baddress0_w; -wire csrbank2_dfii_pi2_wrdata3_re; -wire [7:0] csrbank2_dfii_pi2_wrdata3_r; -wire csrbank2_dfii_pi2_wrdata3_we; -wire [7:0] csrbank2_dfii_pi2_wrdata3_w; -wire csrbank2_dfii_pi2_wrdata2_re; -wire [7:0] csrbank2_dfii_pi2_wrdata2_r; -wire csrbank2_dfii_pi2_wrdata2_we; -wire [7:0] csrbank2_dfii_pi2_wrdata2_w; -wire csrbank2_dfii_pi2_wrdata1_re; -wire [7:0] csrbank2_dfii_pi2_wrdata1_r; -wire csrbank2_dfii_pi2_wrdata1_we; -wire [7:0] csrbank2_dfii_pi2_wrdata1_w; wire csrbank2_dfii_pi2_wrdata0_re; -wire [7:0] csrbank2_dfii_pi2_wrdata0_r; +wire [31:0] csrbank2_dfii_pi2_wrdata0_r; wire csrbank2_dfii_pi2_wrdata0_we; -wire [7:0] csrbank2_dfii_pi2_wrdata0_w; -wire csrbank2_dfii_pi2_rddata3_re; -wire [7:0] csrbank2_dfii_pi2_rddata3_r; -wire csrbank2_dfii_pi2_rddata3_we; -wire [7:0] csrbank2_dfii_pi2_rddata3_w; -wire csrbank2_dfii_pi2_rddata2_re; -wire [7:0] csrbank2_dfii_pi2_rddata2_r; -wire csrbank2_dfii_pi2_rddata2_we; -wire [7:0] csrbank2_dfii_pi2_rddata2_w; -wire csrbank2_dfii_pi2_rddata1_re; -wire [7:0] csrbank2_dfii_pi2_rddata1_r; -wire csrbank2_dfii_pi2_rddata1_we; -wire [7:0] csrbank2_dfii_pi2_rddata1_w; -wire csrbank2_dfii_pi2_rddata0_re; -wire [7:0] csrbank2_dfii_pi2_rddata0_r; -wire csrbank2_dfii_pi2_rddata0_we; -wire [7:0] csrbank2_dfii_pi2_rddata0_w; +wire [31:0] csrbank2_dfii_pi2_wrdata0_w; +wire csrbank2_dfii_pi2_rddata_re; +wire [31:0] csrbank2_dfii_pi2_rddata_r; +wire csrbank2_dfii_pi2_rddata_we; +wire [31:0] csrbank2_dfii_pi2_rddata_w; wire csrbank2_dfii_pi3_command0_re; wire [5:0] csrbank2_dfii_pi3_command0_r; wire csrbank2_dfii_pi3_command0_we; wire [5:0] csrbank2_dfii_pi3_command0_w; -wire csrbank2_dfii_pi3_address1_re; -wire [5:0] csrbank2_dfii_pi3_address1_r; -wire csrbank2_dfii_pi3_address1_we; -wire [5:0] csrbank2_dfii_pi3_address1_w; wire csrbank2_dfii_pi3_address0_re; -wire [7:0] csrbank2_dfii_pi3_address0_r; +wire [13:0] csrbank2_dfii_pi3_address0_r; wire csrbank2_dfii_pi3_address0_we; -wire [7:0] csrbank2_dfii_pi3_address0_w; +wire [13:0] csrbank2_dfii_pi3_address0_w; wire csrbank2_dfii_pi3_baddress0_re; wire [2:0] csrbank2_dfii_pi3_baddress0_r; wire csrbank2_dfii_pi3_baddress0_we; wire [2:0] csrbank2_dfii_pi3_baddress0_w; -wire csrbank2_dfii_pi3_wrdata3_re; -wire [7:0] csrbank2_dfii_pi3_wrdata3_r; -wire csrbank2_dfii_pi3_wrdata3_we; -wire [7:0] csrbank2_dfii_pi3_wrdata3_w; -wire csrbank2_dfii_pi3_wrdata2_re; -wire [7:0] csrbank2_dfii_pi3_wrdata2_r; -wire csrbank2_dfii_pi3_wrdata2_we; -wire [7:0] csrbank2_dfii_pi3_wrdata2_w; -wire csrbank2_dfii_pi3_wrdata1_re; -wire [7:0] csrbank2_dfii_pi3_wrdata1_r; -wire csrbank2_dfii_pi3_wrdata1_we; -wire [7:0] csrbank2_dfii_pi3_wrdata1_w; wire csrbank2_dfii_pi3_wrdata0_re; -wire [7:0] csrbank2_dfii_pi3_wrdata0_r; +wire [31:0] csrbank2_dfii_pi3_wrdata0_r; wire csrbank2_dfii_pi3_wrdata0_we; -wire [7:0] csrbank2_dfii_pi3_wrdata0_w; -wire csrbank2_dfii_pi3_rddata3_re; -wire [7:0] csrbank2_dfii_pi3_rddata3_r; -wire csrbank2_dfii_pi3_rddata3_we; -wire [7:0] csrbank2_dfii_pi3_rddata3_w; -wire csrbank2_dfii_pi3_rddata2_re; -wire [7:0] csrbank2_dfii_pi3_rddata2_r; -wire csrbank2_dfii_pi3_rddata2_we; -wire [7:0] csrbank2_dfii_pi3_rddata2_w; -wire csrbank2_dfii_pi3_rddata1_re; -wire [7:0] csrbank2_dfii_pi3_rddata1_r; -wire csrbank2_dfii_pi3_rddata1_we; -wire [7:0] csrbank2_dfii_pi3_rddata1_w; -wire csrbank2_dfii_pi3_rddata0_re; -wire [7:0] csrbank2_dfii_pi3_rddata0_r; -wire csrbank2_dfii_pi3_rddata0_we; -wire [7:0] csrbank2_dfii_pi3_rddata0_w; +wire [31:0] csrbank2_dfii_pi3_wrdata0_w; +wire csrbank2_dfii_pi3_rddata_re; +wire [31:0] csrbank2_dfii_pi3_rddata_r; +wire csrbank2_dfii_pi3_rddata_we; +wire [31:0] csrbank2_dfii_pi3_rddata_w; reg csrbank2_sel = 1'd0; wire [13:0] adr; wire we; -wire [7:0] dat_w; -wire [7:0] dat_r; +wire [31:0] dat_w; +wire [31:0] dat_r; reg rhs_array_muxed0 = 1'd0; reg [13:0] rhs_array_muxed1 = 14'd0; reg [2:0] rhs_array_muxed2 = 3'd0; @@ -10730,7 +10618,7 @@ reg dummy_d_282; // synthesis translate_on always @(*) begin csrbank0_sel <= 1'd0; - csrbank0_sel <= (interface0_bank_bus_adr[13:11] == 2'd2); + csrbank0_sel <= (interface0_bank_bus_adr[13:9] == 2'd2); if (interface0_bank_bus_adr[0]) begin csrbank0_sel <= 1'd0; end @@ -10739,11 +10627,11 @@ always @(*) begin // synthesis translate_on end assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd0)); -assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd0)); +assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd0)); +assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd0)); assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd1)); -assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd1)); +assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd1)); +assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd1)); assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; @@ -10752,7 +10640,7 @@ reg dummy_d_283; // synthesis translate_on always @(*) begin csrbank1_sel <= 1'd0; - csrbank1_sel <= (interface1_bank_bus_adr[13:11] == 1'd0); + csrbank1_sel <= (interface1_bank_bus_adr[13:9] == 1'd0); if (interface1_bank_bus_adr[0]) begin csrbank1_sel <= 1'd0; end @@ -10761,35 +10649,35 @@ always @(*) begin // synthesis translate_on end assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; -assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd0)); -assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd0)); +assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd0)); +assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd0)); assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; -assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd1)); -assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd1)); +assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd1)); +assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd1)); assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd2)); -assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd2)); +assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd2)); +assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd2)); assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd3)); -assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd3)); +assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd3)); +assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd3)); assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd4)); -assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd4)); +assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd4)); +assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd4)); assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; -assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd5)); -assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd5)); +assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd5)); +assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd5)); assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd6)); -assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd6)); assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd7)); -assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd7)); assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd8)); -assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd8)); assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd9)); -assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd9)); assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0]; assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; @@ -10799,7 +10687,7 @@ reg dummy_d_284; // synthesis translate_on always @(*) begin csrbank2_sel <= 1'd0; - csrbank2_sel <= (interface2_bank_bus_adr[13:11] == 1'd1); + csrbank2_sel <= (interface2_bank_bus_adr[13:9] == 1'd1); if (interface2_bank_bus_adr[0]) begin csrbank2_sel <= 1'd0; end @@ -10808,217 +10696,105 @@ always @(*) begin // synthesis translate_on end assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; -assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd0)); -assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd0)); +assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd0)); +assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd0)); assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd1)); -assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd1)); +assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd1)); +assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd1)); assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd2)); -assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd2)); -assign csrbank2_dfii_pi0_address1_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi0_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd3)); -assign csrbank2_dfii_pi0_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd3)); -assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd4)); -assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd4)); +assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd2)); +assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd2)); +assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[13:0]; +assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd3)); +assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd3)); assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd5)); -assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd5)); -assign csrbank2_dfii_pi0_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd6)); -assign csrbank2_dfii_pi0_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd6)); -assign csrbank2_dfii_pi0_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd7)); -assign csrbank2_dfii_pi0_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd7)); -assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd8)); -assign csrbank2_dfii_pi0_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd8)); -assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd9)); -assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd9)); -assign csrbank2_dfii_pi0_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd10)); -assign csrbank2_dfii_pi0_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd10)); -assign csrbank2_dfii_pi0_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd11)); -assign csrbank2_dfii_pi0_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd11)); -assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd12)); -assign csrbank2_dfii_pi0_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd12)); -assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd13)); -assign csrbank2_dfii_pi0_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd13)); +assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd4)); +assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd4)); +assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd5)); +assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd5)); +assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd6)); +assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd6)); assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd14)); -assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd14)); +assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd7)); +assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd7)); assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd15)); -assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd15)); -assign csrbank2_dfii_pi1_address1_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi1_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd16)); -assign csrbank2_dfii_pi1_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd16)); -assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd17)); -assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd17)); +assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd8)); +assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd8)); +assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[13:0]; +assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd9)); +assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd9)); assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd18)); -assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd18)); -assign csrbank2_dfii_pi1_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd19)); -assign csrbank2_dfii_pi1_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd19)); -assign csrbank2_dfii_pi1_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd20)); -assign csrbank2_dfii_pi1_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd20)); -assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd21)); -assign csrbank2_dfii_pi1_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd21)); -assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd22)); -assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd22)); -assign csrbank2_dfii_pi1_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd23)); -assign csrbank2_dfii_pi1_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd23)); -assign csrbank2_dfii_pi1_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd24)); -assign csrbank2_dfii_pi1_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd24)); -assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd25)); -assign csrbank2_dfii_pi1_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd25)); -assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd26)); -assign csrbank2_dfii_pi1_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd26)); +assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd10)); +assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd10)); +assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd11)); +assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd11)); +assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd12)); +assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd12)); assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd27)); -assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd27)); +assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd13)); +assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd13)); assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd28)); -assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd28)); -assign csrbank2_dfii_pi2_address1_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi2_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd29)); -assign csrbank2_dfii_pi2_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd29)); -assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd30)); -assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd30)); +assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd14)); +assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd14)); +assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[13:0]; +assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd15)); +assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd15)); assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd31)); -assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd31)); -assign csrbank2_dfii_pi2_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd32)); -assign csrbank2_dfii_pi2_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd32)); -assign csrbank2_dfii_pi2_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd33)); -assign csrbank2_dfii_pi2_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd33)); -assign csrbank2_dfii_pi2_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd34)); -assign csrbank2_dfii_pi2_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd34)); -assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd35)); -assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd35)); -assign csrbank2_dfii_pi2_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd36)); -assign csrbank2_dfii_pi2_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd36)); -assign csrbank2_dfii_pi2_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd37)); -assign csrbank2_dfii_pi2_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd37)); -assign csrbank2_dfii_pi2_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd38)); -assign csrbank2_dfii_pi2_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd38)); -assign csrbank2_dfii_pi2_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd39)); -assign csrbank2_dfii_pi2_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd39)); +assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd16)); +assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd16)); +assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd17)); +assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd17)); +assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd18)); +assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd18)); assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd40)); -assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd40)); +assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd19)); +assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd19)); assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd41)); -assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd41)); -assign csrbank2_dfii_pi3_address1_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi3_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd42)); -assign csrbank2_dfii_pi3_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd42)); -assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd43)); -assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd43)); +assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd20)); +assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd20)); +assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[13:0]; +assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd21)); +assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd21)); assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd44)); -assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd44)); -assign csrbank2_dfii_pi3_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd45)); -assign csrbank2_dfii_pi3_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd45)); -assign csrbank2_dfii_pi3_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd46)); -assign csrbank2_dfii_pi3_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd46)); -assign csrbank2_dfii_pi3_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd47)); -assign csrbank2_dfii_pi3_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd47)); -assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd48)); -assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd48)); -assign csrbank2_dfii_pi3_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd49)); -assign csrbank2_dfii_pi3_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd49)); -assign csrbank2_dfii_pi3_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd50)); -assign csrbank2_dfii_pi3_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd50)); -assign csrbank2_dfii_pi3_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd51)); -assign csrbank2_dfii_pi3_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd51)); -assign csrbank2_dfii_pi3_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd52)); -assign csrbank2_dfii_pi3_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd52)); +assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd22)); +assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd22)); +assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd23)); +assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd23)); +assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd24)); +assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd24)); assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; -assign csrbank2_dfii_pi0_address1_w = litedramcore_phaseinjector0_address_storage[13:8]; -assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[7:0]; +assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0]; assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; -assign csrbank2_dfii_pi0_wrdata3_w = litedramcore_phaseinjector0_wrdata_storage[31:24]; -assign csrbank2_dfii_pi0_wrdata2_w = litedramcore_phaseinjector0_wrdata_storage[23:16]; -assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[15:8]; -assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[7:0]; -assign csrbank2_dfii_pi0_rddata3_w = litedramcore_phaseinjector0_status[31:24]; -assign csrbank2_dfii_pi0_rddata2_w = litedramcore_phaseinjector0_status[23:16]; -assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_status[15:8]; -assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_status[7:0]; -assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata0_we; +assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0]; +assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata_we; assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0]; -assign csrbank2_dfii_pi1_address1_w = litedramcore_phaseinjector1_address_storage[13:8]; -assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[7:0]; +assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0]; assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; -assign csrbank2_dfii_pi1_wrdata3_w = litedramcore_phaseinjector1_wrdata_storage[31:24]; -assign csrbank2_dfii_pi1_wrdata2_w = litedramcore_phaseinjector1_wrdata_storage[23:16]; -assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[15:8]; -assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[7:0]; -assign csrbank2_dfii_pi1_rddata3_w = litedramcore_phaseinjector1_status[31:24]; -assign csrbank2_dfii_pi1_rddata2_w = litedramcore_phaseinjector1_status[23:16]; -assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_status[15:8]; -assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_status[7:0]; -assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata0_we; +assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0]; +assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata_we; assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0]; -assign csrbank2_dfii_pi2_address1_w = litedramcore_phaseinjector2_address_storage[13:8]; -assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[7:0]; +assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0]; assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0]; -assign csrbank2_dfii_pi2_wrdata3_w = litedramcore_phaseinjector2_wrdata_storage[31:24]; -assign csrbank2_dfii_pi2_wrdata2_w = litedramcore_phaseinjector2_wrdata_storage[23:16]; -assign csrbank2_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[15:8]; -assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[7:0]; -assign csrbank2_dfii_pi2_rddata3_w = litedramcore_phaseinjector2_status[31:24]; -assign csrbank2_dfii_pi2_rddata2_w = litedramcore_phaseinjector2_status[23:16]; -assign csrbank2_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_status[15:8]; -assign csrbank2_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_status[7:0]; -assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata0_we; +assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0]; +assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0]; +assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata_we; assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0]; -assign csrbank2_dfii_pi3_address1_w = litedramcore_phaseinjector3_address_storage[13:8]; -assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[7:0]; +assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0]; assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0]; -assign csrbank2_dfii_pi3_wrdata3_w = litedramcore_phaseinjector3_wrdata_storage[31:24]; -assign csrbank2_dfii_pi3_wrdata2_w = litedramcore_phaseinjector3_wrdata_storage[23:16]; -assign csrbank2_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[15:8]; -assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[7:0]; -assign csrbank2_dfii_pi3_rddata3_w = litedramcore_phaseinjector3_status[31:24]; -assign csrbank2_dfii_pi3_rddata2_w = litedramcore_phaseinjector3_status[23:16]; -assign csrbank2_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_status[15:8]; -assign csrbank2_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_status[7:0]; -assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata0_we; +assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0]; +assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0]; +assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata_we; assign adr = csr_port_adr; assign we = csr_port_we; assign dat_w = csr_port_dat_w; @@ -14159,7 +13935,7 @@ always @(posedge sys_clk) begin new_master_rdata_valid8 <= new_master_rdata_valid7; interface0_bank_bus_dat_r <= 1'd0; if (csrbank0_sel) begin - case (interface0_bank_bus_adr[3]) + case (interface0_bank_bus_adr[1]) 1'd0: begin interface0_bank_bus_dat_r <= csrbank0_init_done0_w; end @@ -14178,7 +13954,7 @@ always @(posedge sys_clk) begin init_error_re <= csrbank0_init_error0_re; interface1_bank_bus_dat_r <= 1'd0; if (csrbank1_sel) begin - case (interface1_bank_bus_adr[6:3]) + case (interface1_bank_bus_adr[4:1]) 1'd0: begin interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; end @@ -14225,7 +14001,7 @@ always @(posedge sys_clk) begin a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; interface2_bank_bus_dat_r <= 1'd0; if (csrbank2_sel) begin - case (interface2_bank_bus_adr[8:3]) + case (interface2_bank_bus_adr[5:1]) 1'd0: begin interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; end @@ -14236,154 +14012,70 @@ always @(posedge sys_clk) begin interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; end 3'd4: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; end 3'd5: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; end 3'd6: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w; end 3'd7: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; end 4'd8: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w; + interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; end 4'd9: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; end 4'd10: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; end 4'd11: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; end 4'd12: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w; end 4'd13: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; end 4'd14: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; + interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; end 4'd15: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; end 5'd16: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; end 5'd17: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; end 5'd18: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w; end 5'd19: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata3_w; - end - 5'd20: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata2_w; - end - 5'd21: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w; - end - 5'd22: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; - end - 5'd23: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata3_w; - end - 5'd24: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata2_w; - end - 5'd25: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w; - end - 5'd26: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w; - end - 5'd27: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; - end - 5'd28: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; - end - 5'd29: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address1_w; - end - 5'd30: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; - end - 5'd31: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; - end - 6'd32: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata3_w; - end - 6'd33: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata2_w; - end - 6'd34: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata1_w; - end - 6'd35: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; - end - 6'd36: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata3_w; - end - 6'd37: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata2_w; - end - 6'd38: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata1_w; - end - 6'd39: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata0_w; - end - 6'd40: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; end - 6'd41: begin + 5'd20: begin interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; end - 6'd42: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address1_w; - end - 6'd43: begin + 5'd21: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; end - 6'd44: begin + 5'd22: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; end - 6'd45: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata3_w; - end - 6'd46: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata2_w; - end - 6'd47: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata1_w; - end - 6'd48: begin + 5'd23: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; end - 6'd49: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata3_w; - end - 6'd50: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata2_w; - end - 6'd51: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata1_w; - end - 6'd52: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata0_w; + 5'd24: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w; end endcase end @@ -14395,112 +14087,64 @@ always @(posedge sys_clk) begin litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; end litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; - if (csrbank2_dfii_pi0_address1_re) begin - litedramcore_phaseinjector0_address_storage[13:8] <= csrbank2_dfii_pi0_address1_r; - end if (csrbank2_dfii_pi0_address0_re) begin - litedramcore_phaseinjector0_address_storage[7:0] <= csrbank2_dfii_pi0_address0_r; + litedramcore_phaseinjector0_address_storage[13:0] <= csrbank2_dfii_pi0_address0_r; end litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; if (csrbank2_dfii_pi0_baddress0_re) begin litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; end litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; - if (csrbank2_dfii_pi0_wrdata3_re) begin - litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank2_dfii_pi0_wrdata3_r; - end - if (csrbank2_dfii_pi0_wrdata2_re) begin - litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank2_dfii_pi0_wrdata2_r; - end - if (csrbank2_dfii_pi0_wrdata1_re) begin - litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank2_dfii_pi0_wrdata1_r; - end if (csrbank2_dfii_pi0_wrdata0_re) begin - litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank2_dfii_pi0_wrdata0_r; + litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; end litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; if (csrbank2_dfii_pi1_command0_re) begin litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; end litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; - if (csrbank2_dfii_pi1_address1_re) begin - litedramcore_phaseinjector1_address_storage[13:8] <= csrbank2_dfii_pi1_address1_r; - end if (csrbank2_dfii_pi1_address0_re) begin - litedramcore_phaseinjector1_address_storage[7:0] <= csrbank2_dfii_pi1_address0_r; + litedramcore_phaseinjector1_address_storage[13:0] <= csrbank2_dfii_pi1_address0_r; end litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; if (csrbank2_dfii_pi1_baddress0_re) begin litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; end litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; - if (csrbank2_dfii_pi1_wrdata3_re) begin - litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank2_dfii_pi1_wrdata3_r; - end - if (csrbank2_dfii_pi1_wrdata2_re) begin - litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank2_dfii_pi1_wrdata2_r; - end - if (csrbank2_dfii_pi1_wrdata1_re) begin - litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank2_dfii_pi1_wrdata1_r; - end if (csrbank2_dfii_pi1_wrdata0_re) begin - litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank2_dfii_pi1_wrdata0_r; + litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; end litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; if (csrbank2_dfii_pi2_command0_re) begin litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; end litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; - if (csrbank2_dfii_pi2_address1_re) begin - litedramcore_phaseinjector2_address_storage[13:8] <= csrbank2_dfii_pi2_address1_r; - end if (csrbank2_dfii_pi2_address0_re) begin - litedramcore_phaseinjector2_address_storage[7:0] <= csrbank2_dfii_pi2_address0_r; + litedramcore_phaseinjector2_address_storage[13:0] <= csrbank2_dfii_pi2_address0_r; end litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; if (csrbank2_dfii_pi2_baddress0_re) begin litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; end litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; - if (csrbank2_dfii_pi2_wrdata3_re) begin - litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank2_dfii_pi2_wrdata3_r; - end - if (csrbank2_dfii_pi2_wrdata2_re) begin - litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank2_dfii_pi2_wrdata2_r; - end - if (csrbank2_dfii_pi2_wrdata1_re) begin - litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank2_dfii_pi2_wrdata1_r; - end if (csrbank2_dfii_pi2_wrdata0_re) begin - litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank2_dfii_pi2_wrdata0_r; + litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; end litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; if (csrbank2_dfii_pi3_command0_re) begin litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; end litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; - if (csrbank2_dfii_pi3_address1_re) begin - litedramcore_phaseinjector3_address_storage[13:8] <= csrbank2_dfii_pi3_address1_r; - end if (csrbank2_dfii_pi3_address0_re) begin - litedramcore_phaseinjector3_address_storage[7:0] <= csrbank2_dfii_pi3_address0_r; + litedramcore_phaseinjector3_address_storage[13:0] <= csrbank2_dfii_pi3_address0_r; end litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; if (csrbank2_dfii_pi3_baddress0_re) begin litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; end litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; - if (csrbank2_dfii_pi3_wrdata3_re) begin - litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank2_dfii_pi3_wrdata3_r; - end - if (csrbank2_dfii_pi3_wrdata2_re) begin - litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank2_dfii_pi3_wrdata2_r; - end - if (csrbank2_dfii_pi3_wrdata1_re) begin - litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank2_dfii_pi3_wrdata1_r; - end if (csrbank2_dfii_pi3_wrdata0_re) begin - litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank2_dfii_pi3_wrdata0_r; + litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; end litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; if (sys_rst) begin diff --git a/litedram/generated/nexys-video/litedram-wrapper.vhdl b/litedram/generated/nexys-video/litedram-wrapper.vhdl index 475e088..46ae4b1 100644 --- a/litedram/generated/nexys-video/litedram-wrapper.vhdl +++ b/litedram/generated/nexys-video/litedram-wrapper.vhdl @@ -82,8 +82,8 @@ architecture behaviour of litedram_wrapper is user_rst : out std_ulogic; csr_port0_adr : in std_ulogic_vector(13 downto 0); csr_port0_we : in std_ulogic; - csr_port0_dat_w : in std_ulogic_vector(7 downto 0); - csr_port0_dat_r : out std_ulogic_vector(7 downto 0); + csr_port0_dat_w : in std_ulogic_vector(31 downto 0); + csr_port0_dat_r : out std_ulogic_vector(31 downto 0); user_port_native_0_cmd_valid : in std_ulogic; user_port_native_0_cmd_ready : out std_ulogic; user_port_native_0_cmd_we : in std_ulogic; @@ -116,8 +116,8 @@ architecture behaviour of litedram_wrapper is signal csr_port0_adr : std_ulogic_vector(13 downto 0); signal csr_port0_we : std_ulogic; - signal csr_port0_dat_w : std_ulogic_vector(7 downto 0); - signal csr_port0_dat_r : std_ulogic_vector(7 downto 0); + signal csr_port0_dat_w : std_ulogic_vector(31 downto 0); + signal csr_port0_dat_r : std_ulogic_vector(31 downto 0); signal csr_port_read_comb : std_ulogic_vector(63 downto 0); signal csr_valid : std_ulogic; signal csr_write_valid : std_ulogic; @@ -205,8 +205,8 @@ begin -- DRAM CSR interface signals. We only support access to the bottom byte csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; csr_write_valid <= wb_in.we and wb_in.sel(0); - csr_port0_adr <= wb_in.adr(13 downto 0) when wb_is_csr = '1' else (others => '0'); - csr_port0_dat_w <= wb_in.dat(7 downto 0); + csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0'); + csr_port0_dat_w <= wb_in.dat(31 downto 0); csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; -- Wishbone out signals @@ -215,7 +215,7 @@ begin user_port0_wdata_ready when state = MWRITE else user_port0_rdata_valid when state = MREAD else '0'; - csr_port_read_comb <= x"00000000000000" & csr_port0_dat_r; + csr_port_read_comb <= x"00000000" & csr_port0_dat_r; wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else wb_init_out.dat when wb_is_init = '1' else user_port0_rdata_data(127 downto 64) when ad3 = '1' else diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init index d07879f..7708f27 100644 --- a/litedram/generated/nexys-video/litedram_core.init +++ b/litedram/generated/nexys-video/litedram_core.init @@ -513,17 +513,17 @@ a64b5a7d14004a39 38429d003c4c0001 600000003d20c000 7929002061292000 -3d40c000f9228040 +3d40c000f9228000 614a201839200035 7c0004ac794a0020 4e8000207d2057aa 0000000000000000 3c4c000100000000 6000000038429cbc -39290010e9228040 +39290010e9228000 7d204eaa7c0004ac 4082ffe871290008 -e922804060000000 +e922800060000000 7c604faa7c0004ac 000000004e800020 0000000000000000 @@ -533,7 +533,7 @@ fbc1fff07c0802a6 f80100107c7f1b78 7fbff040f821ffd1 38210030409e000c -893f00004800194c +893f000048001908 409e000c2f89000a 4bffff813860000d 3bff0001887f0000 @@ -549,11 +549,11 @@ f88101983bc10020 f8e101b038c10198 f90101b87fc3f378 f94101c8f92101c0 -60000000480012ed +60000000480012a9 7c641b787c7f1b78 4bffff457fc3f378 7fe3fb7838210170 -00000000480018ac +0000000048001868 0000028001000000 38429b983c4c0001 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+0000000000000830 +0000000000000860 +0000000000000890 +00000000000008c0 6f6e204d41524453 207265646e752077 6572617764726168 diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v index dd74efd..854f4c6 100644 --- a/litedram/generated/nexys-video/litedram_core.v +++ b/litedram/generated/nexys-video/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 10:54:05 +// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 11:57:13 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, @@ -24,8 +24,8 @@ module litedram_core( output wire init_error, input wire [13:0] csr_port0_adr, input wire csr_port0_we, - input wire [7:0] csr_port0_dat_w, - output wire [7:0] csr_port0_dat_r, + input wire [31:0] csr_port0_dat_w, + output wire [31:0] csr_port0_dat_r, output wire user_clk, output wire user_rst, input wire user_port_native_0_cmd_valid, @@ -1485,8 +1485,8 @@ reg init_error_storage = 1'd0; reg init_error_re = 1'd0; wire [13:0] csr_port_adr; wire csr_port_we; -wire [7:0] csr_port_dat_w; -wire [7:0] csr_port_dat_r; +wire [31:0] csr_port_dat_w; +wire [31:0] csr_port_dat_r; wire user_port_cmd_valid; wire user_port_cmd_ready; wire user_port_cmd_payload_we; @@ -1566,8 +1566,8 @@ reg new_master_rdata_valid7 = 1'd0; reg new_master_rdata_valid8 = 1'd0; wire [13:0] interface0_bank_bus_adr; wire interface0_bank_bus_we; -wire [7:0] interface0_bank_bus_dat_w; -reg [7:0] interface0_bank_bus_dat_r = 8'd0; +wire [31:0] interface0_bank_bus_dat_w; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; wire csrbank0_init_done0_re; wire csrbank0_init_done0_r; wire csrbank0_init_done0_we; @@ -1579,8 +1579,8 @@ wire csrbank0_init_error0_w; reg csrbank0_sel = 1'd0; wire [13:0] interface1_bank_bus_adr; wire interface1_bank_bus_we; -wire [7:0] interface1_bank_bus_dat_w; -reg [7:0] interface1_bank_bus_dat_r = 8'd0; +wire [31:0] interface1_bank_bus_dat_w; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; wire csrbank1_half_sys8x_taps0_re; wire [4:0] csrbank1_half_sys8x_taps0_r; wire csrbank1_half_sys8x_taps0_we; @@ -1596,8 +1596,8 @@ wire [1:0] csrbank1_dly_sel0_w; reg csrbank1_sel = 1'd0; wire [13:0] interface2_bank_bus_adr; wire interface2_bank_bus_we; -wire [7:0] interface2_bank_bus_dat_w; -reg [7:0] interface2_bank_bus_dat_r = 8'd0; +wire [31:0] interface2_bank_bus_dat_w; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; wire csrbank2_dfii_control0_re; wire [3:0] csrbank2_dfii_control0_r; wire csrbank2_dfii_control0_we; @@ -1606,199 +1606,87 @@ wire csrbank2_dfii_pi0_command0_re; wire [5:0] csrbank2_dfii_pi0_command0_r; wire csrbank2_dfii_pi0_command0_we; wire [5:0] csrbank2_dfii_pi0_command0_w; -wire csrbank2_dfii_pi0_address1_re; -wire [6:0] csrbank2_dfii_pi0_address1_r; -wire csrbank2_dfii_pi0_address1_we; -wire [6:0] csrbank2_dfii_pi0_address1_w; wire csrbank2_dfii_pi0_address0_re; -wire [7:0] csrbank2_dfii_pi0_address0_r; +wire [14:0] csrbank2_dfii_pi0_address0_r; wire csrbank2_dfii_pi0_address0_we; -wire [7:0] csrbank2_dfii_pi0_address0_w; +wire [14:0] csrbank2_dfii_pi0_address0_w; wire csrbank2_dfii_pi0_baddress0_re; wire [2:0] csrbank2_dfii_pi0_baddress0_r; wire csrbank2_dfii_pi0_baddress0_we; wire [2:0] csrbank2_dfii_pi0_baddress0_w; -wire csrbank2_dfii_pi0_wrdata3_re; -wire [7:0] csrbank2_dfii_pi0_wrdata3_r; -wire csrbank2_dfii_pi0_wrdata3_we; -wire [7:0] csrbank2_dfii_pi0_wrdata3_w; -wire csrbank2_dfii_pi0_wrdata2_re; -wire [7:0] csrbank2_dfii_pi0_wrdata2_r; -wire csrbank2_dfii_pi0_wrdata2_we; -wire [7:0] csrbank2_dfii_pi0_wrdata2_w; -wire csrbank2_dfii_pi0_wrdata1_re; -wire [7:0] csrbank2_dfii_pi0_wrdata1_r; -wire csrbank2_dfii_pi0_wrdata1_we; -wire [7:0] csrbank2_dfii_pi0_wrdata1_w; wire csrbank2_dfii_pi0_wrdata0_re; -wire [7:0] csrbank2_dfii_pi0_wrdata0_r; +wire [31:0] csrbank2_dfii_pi0_wrdata0_r; wire csrbank2_dfii_pi0_wrdata0_we; -wire [7:0] csrbank2_dfii_pi0_wrdata0_w; -wire csrbank2_dfii_pi0_rddata3_re; -wire [7:0] csrbank2_dfii_pi0_rddata3_r; -wire csrbank2_dfii_pi0_rddata3_we; -wire [7:0] csrbank2_dfii_pi0_rddata3_w; -wire csrbank2_dfii_pi0_rddata2_re; -wire [7:0] csrbank2_dfii_pi0_rddata2_r; -wire csrbank2_dfii_pi0_rddata2_we; -wire [7:0] csrbank2_dfii_pi0_rddata2_w; -wire csrbank2_dfii_pi0_rddata1_re; -wire [7:0] csrbank2_dfii_pi0_rddata1_r; -wire csrbank2_dfii_pi0_rddata1_we; -wire [7:0] csrbank2_dfii_pi0_rddata1_w; -wire csrbank2_dfii_pi0_rddata0_re; -wire [7:0] csrbank2_dfii_pi0_rddata0_r; -wire csrbank2_dfii_pi0_rddata0_we; -wire [7:0] csrbank2_dfii_pi0_rddata0_w; +wire [31:0] csrbank2_dfii_pi0_wrdata0_w; +wire csrbank2_dfii_pi0_rddata_re; +wire [31:0] csrbank2_dfii_pi0_rddata_r; +wire csrbank2_dfii_pi0_rddata_we; +wire [31:0] csrbank2_dfii_pi0_rddata_w; wire csrbank2_dfii_pi1_command0_re; wire [5:0] csrbank2_dfii_pi1_command0_r; wire csrbank2_dfii_pi1_command0_we; wire [5:0] csrbank2_dfii_pi1_command0_w; -wire csrbank2_dfii_pi1_address1_re; -wire [6:0] csrbank2_dfii_pi1_address1_r; -wire csrbank2_dfii_pi1_address1_we; -wire [6:0] csrbank2_dfii_pi1_address1_w; wire csrbank2_dfii_pi1_address0_re; -wire [7:0] csrbank2_dfii_pi1_address0_r; +wire [14:0] csrbank2_dfii_pi1_address0_r; wire csrbank2_dfii_pi1_address0_we; -wire [7:0] csrbank2_dfii_pi1_address0_w; +wire [14:0] csrbank2_dfii_pi1_address0_w; wire csrbank2_dfii_pi1_baddress0_re; wire [2:0] csrbank2_dfii_pi1_baddress0_r; wire csrbank2_dfii_pi1_baddress0_we; wire [2:0] csrbank2_dfii_pi1_baddress0_w; -wire csrbank2_dfii_pi1_wrdata3_re; -wire [7:0] csrbank2_dfii_pi1_wrdata3_r; -wire csrbank2_dfii_pi1_wrdata3_we; -wire [7:0] csrbank2_dfii_pi1_wrdata3_w; -wire csrbank2_dfii_pi1_wrdata2_re; -wire [7:0] csrbank2_dfii_pi1_wrdata2_r; -wire csrbank2_dfii_pi1_wrdata2_we; -wire [7:0] csrbank2_dfii_pi1_wrdata2_w; -wire csrbank2_dfii_pi1_wrdata1_re; -wire [7:0] csrbank2_dfii_pi1_wrdata1_r; -wire csrbank2_dfii_pi1_wrdata1_we; -wire [7:0] csrbank2_dfii_pi1_wrdata1_w; wire csrbank2_dfii_pi1_wrdata0_re; -wire [7:0] csrbank2_dfii_pi1_wrdata0_r; +wire [31:0] csrbank2_dfii_pi1_wrdata0_r; wire csrbank2_dfii_pi1_wrdata0_we; -wire [7:0] csrbank2_dfii_pi1_wrdata0_w; -wire csrbank2_dfii_pi1_rddata3_re; -wire [7:0] csrbank2_dfii_pi1_rddata3_r; -wire csrbank2_dfii_pi1_rddata3_we; -wire [7:0] csrbank2_dfii_pi1_rddata3_w; -wire csrbank2_dfii_pi1_rddata2_re; -wire [7:0] csrbank2_dfii_pi1_rddata2_r; -wire csrbank2_dfii_pi1_rddata2_we; -wire [7:0] csrbank2_dfii_pi1_rddata2_w; -wire csrbank2_dfii_pi1_rddata1_re; -wire [7:0] csrbank2_dfii_pi1_rddata1_r; -wire csrbank2_dfii_pi1_rddata1_we; -wire [7:0] csrbank2_dfii_pi1_rddata1_w; -wire csrbank2_dfii_pi1_rddata0_re; -wire [7:0] csrbank2_dfii_pi1_rddata0_r; -wire csrbank2_dfii_pi1_rddata0_we; -wire [7:0] csrbank2_dfii_pi1_rddata0_w; +wire [31:0] csrbank2_dfii_pi1_wrdata0_w; +wire csrbank2_dfii_pi1_rddata_re; +wire [31:0] csrbank2_dfii_pi1_rddata_r; +wire csrbank2_dfii_pi1_rddata_we; +wire [31:0] csrbank2_dfii_pi1_rddata_w; wire csrbank2_dfii_pi2_command0_re; wire [5:0] csrbank2_dfii_pi2_command0_r; wire csrbank2_dfii_pi2_command0_we; wire [5:0] csrbank2_dfii_pi2_command0_w; -wire csrbank2_dfii_pi2_address1_re; -wire [6:0] csrbank2_dfii_pi2_address1_r; -wire csrbank2_dfii_pi2_address1_we; -wire [6:0] csrbank2_dfii_pi2_address1_w; wire csrbank2_dfii_pi2_address0_re; -wire [7:0] csrbank2_dfii_pi2_address0_r; +wire [14:0] csrbank2_dfii_pi2_address0_r; wire csrbank2_dfii_pi2_address0_we; -wire [7:0] csrbank2_dfii_pi2_address0_w; +wire [14:0] csrbank2_dfii_pi2_address0_w; wire csrbank2_dfii_pi2_baddress0_re; wire [2:0] csrbank2_dfii_pi2_baddress0_r; wire csrbank2_dfii_pi2_baddress0_we; wire [2:0] csrbank2_dfii_pi2_baddress0_w; -wire csrbank2_dfii_pi2_wrdata3_re; -wire [7:0] csrbank2_dfii_pi2_wrdata3_r; -wire csrbank2_dfii_pi2_wrdata3_we; -wire [7:0] csrbank2_dfii_pi2_wrdata3_w; -wire csrbank2_dfii_pi2_wrdata2_re; -wire [7:0] csrbank2_dfii_pi2_wrdata2_r; -wire csrbank2_dfii_pi2_wrdata2_we; -wire [7:0] csrbank2_dfii_pi2_wrdata2_w; -wire csrbank2_dfii_pi2_wrdata1_re; -wire [7:0] csrbank2_dfii_pi2_wrdata1_r; -wire csrbank2_dfii_pi2_wrdata1_we; -wire [7:0] csrbank2_dfii_pi2_wrdata1_w; wire csrbank2_dfii_pi2_wrdata0_re; -wire [7:0] csrbank2_dfii_pi2_wrdata0_r; +wire [31:0] csrbank2_dfii_pi2_wrdata0_r; wire csrbank2_dfii_pi2_wrdata0_we; -wire [7:0] csrbank2_dfii_pi2_wrdata0_w; -wire csrbank2_dfii_pi2_rddata3_re; -wire [7:0] csrbank2_dfii_pi2_rddata3_r; -wire csrbank2_dfii_pi2_rddata3_we; -wire [7:0] csrbank2_dfii_pi2_rddata3_w; -wire csrbank2_dfii_pi2_rddata2_re; -wire [7:0] csrbank2_dfii_pi2_rddata2_r; -wire csrbank2_dfii_pi2_rddata2_we; -wire [7:0] csrbank2_dfii_pi2_rddata2_w; -wire csrbank2_dfii_pi2_rddata1_re; -wire [7:0] csrbank2_dfii_pi2_rddata1_r; -wire csrbank2_dfii_pi2_rddata1_we; -wire [7:0] csrbank2_dfii_pi2_rddata1_w; -wire csrbank2_dfii_pi2_rddata0_re; -wire [7:0] csrbank2_dfii_pi2_rddata0_r; -wire csrbank2_dfii_pi2_rddata0_we; -wire [7:0] csrbank2_dfii_pi2_rddata0_w; +wire [31:0] csrbank2_dfii_pi2_wrdata0_w; +wire csrbank2_dfii_pi2_rddata_re; +wire [31:0] csrbank2_dfii_pi2_rddata_r; +wire csrbank2_dfii_pi2_rddata_we; +wire [31:0] csrbank2_dfii_pi2_rddata_w; wire csrbank2_dfii_pi3_command0_re; wire [5:0] csrbank2_dfii_pi3_command0_r; wire csrbank2_dfii_pi3_command0_we; wire [5:0] csrbank2_dfii_pi3_command0_w; -wire csrbank2_dfii_pi3_address1_re; -wire [6:0] csrbank2_dfii_pi3_address1_r; -wire csrbank2_dfii_pi3_address1_we; -wire [6:0] csrbank2_dfii_pi3_address1_w; wire csrbank2_dfii_pi3_address0_re; -wire [7:0] csrbank2_dfii_pi3_address0_r; +wire [14:0] csrbank2_dfii_pi3_address0_r; wire csrbank2_dfii_pi3_address0_we; -wire [7:0] csrbank2_dfii_pi3_address0_w; +wire [14:0] csrbank2_dfii_pi3_address0_w; wire csrbank2_dfii_pi3_baddress0_re; wire [2:0] csrbank2_dfii_pi3_baddress0_r; wire csrbank2_dfii_pi3_baddress0_we; wire [2:0] csrbank2_dfii_pi3_baddress0_w; -wire csrbank2_dfii_pi3_wrdata3_re; -wire [7:0] csrbank2_dfii_pi3_wrdata3_r; -wire csrbank2_dfii_pi3_wrdata3_we; -wire [7:0] csrbank2_dfii_pi3_wrdata3_w; -wire csrbank2_dfii_pi3_wrdata2_re; -wire [7:0] csrbank2_dfii_pi3_wrdata2_r; -wire csrbank2_dfii_pi3_wrdata2_we; -wire [7:0] csrbank2_dfii_pi3_wrdata2_w; -wire csrbank2_dfii_pi3_wrdata1_re; -wire [7:0] csrbank2_dfii_pi3_wrdata1_r; -wire csrbank2_dfii_pi3_wrdata1_we; -wire [7:0] csrbank2_dfii_pi3_wrdata1_w; wire csrbank2_dfii_pi3_wrdata0_re; -wire [7:0] csrbank2_dfii_pi3_wrdata0_r; +wire [31:0] csrbank2_dfii_pi3_wrdata0_r; wire csrbank2_dfii_pi3_wrdata0_we; -wire [7:0] csrbank2_dfii_pi3_wrdata0_w; -wire csrbank2_dfii_pi3_rddata3_re; -wire [7:0] csrbank2_dfii_pi3_rddata3_r; -wire csrbank2_dfii_pi3_rddata3_we; -wire [7:0] csrbank2_dfii_pi3_rddata3_w; -wire csrbank2_dfii_pi3_rddata2_re; -wire [7:0] csrbank2_dfii_pi3_rddata2_r; -wire csrbank2_dfii_pi3_rddata2_we; -wire [7:0] csrbank2_dfii_pi3_rddata2_w; -wire csrbank2_dfii_pi3_rddata1_re; -wire [7:0] csrbank2_dfii_pi3_rddata1_r; -wire csrbank2_dfii_pi3_rddata1_we; -wire [7:0] csrbank2_dfii_pi3_rddata1_w; -wire csrbank2_dfii_pi3_rddata0_re; -wire [7:0] csrbank2_dfii_pi3_rddata0_r; -wire csrbank2_dfii_pi3_rddata0_we; -wire [7:0] csrbank2_dfii_pi3_rddata0_w; +wire [31:0] csrbank2_dfii_pi3_wrdata0_w; +wire csrbank2_dfii_pi3_rddata_re; +wire [31:0] csrbank2_dfii_pi3_rddata_r; +wire csrbank2_dfii_pi3_rddata_we; +wire [31:0] csrbank2_dfii_pi3_rddata_w; reg csrbank2_sel = 1'd0; wire [13:0] adr; wire we; -wire [7:0] dat_w; -wire [7:0] dat_r; +wire [31:0] dat_w; +wire [31:0] dat_r; reg rhs_array_muxed0 = 1'd0; reg [14:0] rhs_array_muxed1 = 15'd0; reg [2:0] rhs_array_muxed2 = 3'd0; @@ -2848,11 +2736,11 @@ assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; reg dummy_d_22; // synthesis translate_on always @(*) begin - litedramcore_master_p2_ras_n <= 1'd1; + litedramcore_master_p1_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; + litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; end else begin - litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n; + litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n; end // synthesis translate_off dummy_d_22 = dummy_s; @@ -2863,9 +2751,9 @@ end reg dummy_d_23; // synthesis translate_on always @(*) begin - litedramcore_slave_p2_rddata <= 32'd0; + litedramcore_slave_p1_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; + litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; end else begin end // synthesis translate_off @@ -2877,11 +2765,11 @@ end reg dummy_d_24; // synthesis translate_on always @(*) begin - litedramcore_master_p2_we_n <= 1'd1; + litedramcore_master_p1_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; + litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; end else begin - litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; + litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n; end // synthesis translate_off dummy_d_24 = dummy_s; @@ -2892,9 +2780,9 @@ end reg dummy_d_25; // synthesis translate_on always @(*) begin - litedramcore_slave_p2_rddata_valid <= 1'd0; + litedramcore_slave_p1_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end else begin end // synthesis translate_off @@ -2906,11 +2794,11 @@ end reg dummy_d_26; // synthesis translate_on always @(*) begin - litedramcore_master_p2_cke <= 1'd0; + litedramcore_master_p1_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; + litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; end else begin - litedramcore_master_p2_cke <= litedramcore_inti_p2_cke; + litedramcore_master_p1_cke <= litedramcore_inti_p1_cke; end // synthesis translate_off dummy_d_26 = dummy_s; @@ -2921,11 +2809,11 @@ end reg dummy_d_27; // synthesis translate_on always @(*) begin - litedramcore_master_p2_odt <= 1'd0; + litedramcore_master_p1_odt <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; + litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; end else begin - litedramcore_master_p2_odt <= litedramcore_inti_p2_odt; + litedramcore_master_p1_odt <= litedramcore_inti_p1_odt; end // synthesis translate_off dummy_d_27 = dummy_s; @@ -2936,11 +2824,11 @@ end reg dummy_d_28; // synthesis translate_on always @(*) begin - litedramcore_master_p2_reset_n <= 1'd0; + litedramcore_master_p1_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; + litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; end else begin - litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n; + litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; end // synthesis translate_off dummy_d_28 = dummy_s; @@ -2951,11 +2839,11 @@ end reg dummy_d_29; // synthesis translate_on always @(*) begin - litedramcore_master_p2_act_n <= 1'd1; + litedramcore_master_p1_act_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; + litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; end else begin - litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n; + litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n; end // synthesis translate_off dummy_d_29 = dummy_s; @@ -2966,11 +2854,11 @@ end reg dummy_d_30; // synthesis translate_on always @(*) begin - litedramcore_master_p2_wrdata <= 32'd0; + litedramcore_master_p1_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; + litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; end else begin - litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata; + litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata; end // synthesis translate_off dummy_d_30 = dummy_s; @@ -2981,10 +2869,10 @@ end reg dummy_d_31; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_rddata <= 32'd0; + litedramcore_inti_p2_rddata <= 32'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata; + litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; end // synthesis translate_off dummy_d_31 = dummy_s; @@ -2995,11 +2883,11 @@ end reg dummy_d_32; // synthesis translate_on always @(*) begin - litedramcore_master_p2_wrdata_en <= 1'd0; + litedramcore_master_p1_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; + litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en; + litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; end // synthesis translate_off dummy_d_32 = dummy_s; @@ -3010,10 +2898,10 @@ end reg dummy_d_33; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_rddata_valid <= 1'd0; + litedramcore_inti_p2_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end // synthesis translate_off dummy_d_33 = dummy_s; @@ -3024,11 +2912,11 @@ end reg dummy_d_34; // synthesis translate_on always @(*) begin - litedramcore_master_p2_wrdata_mask <= 4'd0; + litedramcore_master_p1_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; + litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask; + litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; end // synthesis translate_off dummy_d_34 = dummy_s; @@ -3039,11 +2927,11 @@ end reg dummy_d_35; // synthesis translate_on always @(*) begin - litedramcore_master_p2_rddata_en <= 1'd0; + litedramcore_master_p1_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; + litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; end else begin - litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en; + litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; end // synthesis translate_off dummy_d_35 = dummy_s; @@ -3054,11 +2942,11 @@ end reg dummy_d_36; // synthesis translate_on always @(*) begin - litedramcore_master_p3_address <= 15'd0; + litedramcore_master_p2_address <= 15'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_address <= litedramcore_slave_p3_address; + litedramcore_master_p2_address <= litedramcore_slave_p2_address; end else begin - litedramcore_master_p3_address <= litedramcore_inti_p3_address; + litedramcore_master_p2_address <= litedramcore_inti_p2_address; end // synthesis translate_off dummy_d_36 = dummy_s; @@ -3069,11 +2957,11 @@ end reg dummy_d_37; // synthesis translate_on always @(*) begin - litedramcore_master_p3_bank <= 3'd0; + litedramcore_master_p2_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; + litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; end else begin - litedramcore_master_p3_bank <= litedramcore_inti_p3_bank; + litedramcore_master_p2_bank <= litedramcore_inti_p2_bank; end // synthesis translate_off dummy_d_37 = dummy_s; @@ -3084,11 +2972,11 @@ end reg dummy_d_38; // synthesis translate_on always @(*) begin - litedramcore_master_p3_cas_n <= 1'd1; + litedramcore_master_p2_cas_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; + litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; end else begin - litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n; + litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n; end // synthesis translate_off dummy_d_38 = dummy_s; @@ -3099,11 +2987,11 @@ end reg dummy_d_39; // synthesis translate_on always @(*) begin - litedramcore_master_p3_cs_n <= 1'd1; + litedramcore_master_p2_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; + litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; end else begin - litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n; + litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n; end // synthesis translate_off dummy_d_39 = dummy_s; @@ -3114,11 +3002,11 @@ end reg dummy_d_40; // synthesis translate_on always @(*) begin - litedramcore_master_p3_ras_n <= 1'd1; + litedramcore_master_p2_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; + litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; end else begin - litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n; + litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n; end // synthesis translate_off dummy_d_40 = dummy_s; @@ -3129,9 +3017,9 @@ end reg dummy_d_41; // synthesis translate_on always @(*) begin - litedramcore_slave_p3_rddata <= 32'd0; + litedramcore_slave_p2_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; + litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; end else begin end // synthesis translate_off @@ -3143,11 +3031,11 @@ end reg dummy_d_42; // synthesis translate_on always @(*) begin - litedramcore_master_p3_we_n <= 1'd1; + litedramcore_master_p2_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; + litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; end else begin - litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n; + litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; end // synthesis translate_off dummy_d_42 = dummy_s; @@ -3158,9 +3046,9 @@ end reg dummy_d_43; // synthesis translate_on always @(*) begin - litedramcore_slave_p3_rddata_valid <= 1'd0; + litedramcore_slave_p2_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end else begin end // synthesis translate_off @@ -3172,11 +3060,11 @@ end reg dummy_d_44; // synthesis translate_on always @(*) begin - litedramcore_master_p3_cke <= 1'd0; + litedramcore_master_p2_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; + litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; end else begin - litedramcore_master_p3_cke <= litedramcore_inti_p3_cke; + litedramcore_master_p2_cke <= litedramcore_inti_p2_cke; end // synthesis translate_off dummy_d_44 = dummy_s; @@ -3187,11 +3075,11 @@ end reg dummy_d_45; // synthesis translate_on always @(*) begin - litedramcore_master_p3_odt <= 1'd0; + litedramcore_master_p2_odt <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; + litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; end else begin - litedramcore_master_p3_odt <= litedramcore_inti_p3_odt; + litedramcore_master_p2_odt <= litedramcore_inti_p2_odt; end // synthesis translate_off dummy_d_45 = dummy_s; @@ -3202,11 +3090,11 @@ end reg dummy_d_46; // synthesis translate_on always @(*) begin - litedramcore_master_p3_reset_n <= 1'd0; + litedramcore_master_p2_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; + litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; end else begin - litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n; + litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n; end // synthesis translate_off dummy_d_46 = dummy_s; @@ -3217,11 +3105,11 @@ end reg dummy_d_47; // synthesis translate_on always @(*) begin - litedramcore_master_p3_act_n <= 1'd1; + litedramcore_master_p2_act_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; + litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; end else begin - litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n; + litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n; end // synthesis translate_off dummy_d_47 = dummy_s; @@ -3232,11 +3120,11 @@ end reg dummy_d_48; // synthesis translate_on always @(*) begin - litedramcore_master_p3_wrdata <= 32'd0; + litedramcore_master_p2_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; + litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; end else begin - litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata; + litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata; end // synthesis translate_off dummy_d_48 = dummy_s; @@ -3247,10 +3135,10 @@ end reg dummy_d_49; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_rddata <= 32'd0; + litedramcore_inti_p3_rddata <= 32'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata; + litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata; end // synthesis translate_off dummy_d_49 = dummy_s; @@ -3261,11 +3149,11 @@ end reg dummy_d_50; // synthesis translate_on always @(*) begin - litedramcore_master_p3_wrdata_en <= 1'd0; + litedramcore_master_p2_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; + litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en; + litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en; end // synthesis translate_off dummy_d_50 = dummy_s; @@ -3276,10 +3164,10 @@ end reg dummy_d_51; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_rddata_valid <= 1'd0; + litedramcore_inti_p3_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end // synthesis translate_off dummy_d_51 = dummy_s; @@ -3290,11 +3178,11 @@ end reg dummy_d_52; // synthesis translate_on always @(*) begin - litedramcore_master_p3_wrdata_mask <= 4'd0; + litedramcore_master_p2_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; + litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask; + litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask; end // synthesis translate_off dummy_d_52 = dummy_s; @@ -3305,11 +3193,11 @@ end reg dummy_d_53; // synthesis translate_on always @(*) begin - litedramcore_master_p3_rddata_en <= 1'd0; + litedramcore_master_p2_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; + litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; end else begin - litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en; + litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en; end // synthesis translate_off dummy_d_53 = dummy_s; @@ -3320,11 +3208,11 @@ end reg dummy_d_54; // synthesis translate_on always @(*) begin - litedramcore_master_p0_address <= 15'd0; + litedramcore_master_p3_address <= 15'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_address <= litedramcore_slave_p0_address; + litedramcore_master_p3_address <= litedramcore_slave_p3_address; end else begin - litedramcore_master_p0_address <= litedramcore_inti_p0_address; + litedramcore_master_p3_address <= litedramcore_inti_p3_address; end // synthesis translate_off dummy_d_54 = dummy_s; @@ -3335,11 +3223,11 @@ end reg dummy_d_55; // synthesis translate_on always @(*) begin - litedramcore_master_p0_bank <= 3'd0; + litedramcore_master_p3_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; + litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; end else begin - litedramcore_master_p0_bank <= litedramcore_inti_p0_bank; + litedramcore_master_p3_bank <= litedramcore_inti_p3_bank; end // synthesis translate_off dummy_d_55 = dummy_s; @@ -3350,11 +3238,11 @@ end reg dummy_d_56; // synthesis translate_on always @(*) begin - litedramcore_master_p0_cas_n <= 1'd1; + litedramcore_master_p3_cas_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; + litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; end else begin - litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n; + litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n; end // synthesis translate_off dummy_d_56 = dummy_s; @@ -3365,11 +3253,11 @@ end reg dummy_d_57; // synthesis translate_on always @(*) begin - litedramcore_master_p0_cs_n <= 1'd1; + litedramcore_master_p3_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; end else begin - litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n; + litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n; end // synthesis translate_off dummy_d_57 = dummy_s; @@ -3380,11 +3268,11 @@ end reg dummy_d_58; // synthesis translate_on always @(*) begin - litedramcore_master_p0_ras_n <= 1'd1; + litedramcore_master_p3_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; end else begin - litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n; + litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n; end // synthesis translate_off dummy_d_58 = dummy_s; @@ -3395,9 +3283,9 @@ end reg dummy_d_59; // synthesis translate_on always @(*) begin - litedramcore_slave_p0_rddata <= 32'd0; + litedramcore_slave_p3_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; + litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; end else begin end // synthesis translate_off @@ -3409,11 +3297,11 @@ end reg dummy_d_60; // synthesis translate_on always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; + litedramcore_master_p3_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; end else begin - litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; + litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n; end // synthesis translate_off dummy_d_60 = dummy_s; @@ -3424,9 +3312,9 @@ end reg dummy_d_61; // synthesis translate_on always @(*) begin - litedramcore_slave_p0_rddata_valid <= 1'd0; + litedramcore_slave_p3_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end else begin end // synthesis translate_off @@ -3438,11 +3326,11 @@ end reg dummy_d_62; // synthesis translate_on always @(*) begin - litedramcore_master_p0_cke <= 1'd0; + litedramcore_master_p3_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; + litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; end else begin - litedramcore_master_p0_cke <= litedramcore_inti_p0_cke; + litedramcore_master_p3_cke <= litedramcore_inti_p3_cke; end // synthesis translate_off dummy_d_62 = dummy_s; @@ -3453,11 +3341,11 @@ end reg dummy_d_63; // synthesis translate_on always @(*) begin - litedramcore_master_p0_odt <= 1'd0; + litedramcore_master_p3_odt <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; + litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; end else begin - litedramcore_master_p0_odt <= litedramcore_inti_p0_odt; + litedramcore_master_p3_odt <= litedramcore_inti_p3_odt; end // synthesis translate_off dummy_d_63 = dummy_s; @@ -3468,11 +3356,11 @@ end reg dummy_d_64; // synthesis translate_on always @(*) begin - litedramcore_master_p0_reset_n <= 1'd0; + litedramcore_master_p3_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; + litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; end else begin - litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n; + litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n; end // synthesis translate_off dummy_d_64 = dummy_s; @@ -3483,11 +3371,11 @@ end reg dummy_d_65; // synthesis translate_on always @(*) begin - litedramcore_master_p0_act_n <= 1'd1; + litedramcore_master_p3_act_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; + litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; end else begin - litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n; + litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n; end // synthesis translate_off dummy_d_65 = dummy_s; @@ -3498,11 +3386,11 @@ end reg dummy_d_66; // synthesis translate_on always @(*) begin - litedramcore_master_p0_wrdata <= 32'd0; + litedramcore_master_p3_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; + litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; end else begin - litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata; + litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata; end // synthesis translate_off dummy_d_66 = dummy_s; @@ -3513,10 +3401,10 @@ end reg dummy_d_67; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_rddata <= 32'd0; + litedramcore_inti_p0_rddata <= 32'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata; + litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata; end // synthesis translate_off dummy_d_67 = dummy_s; @@ -3527,11 +3415,11 @@ end reg dummy_d_68; // synthesis translate_on always @(*) begin - litedramcore_master_p0_wrdata_en <= 1'd0; + litedramcore_master_p3_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; + litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en; + litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en; end // synthesis translate_off dummy_d_68 = dummy_s; @@ -3542,10 +3430,10 @@ end reg dummy_d_69; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_rddata_valid <= 1'd0; + litedramcore_inti_p0_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end // synthesis translate_off dummy_d_69 = dummy_s; @@ -3556,11 +3444,11 @@ end reg dummy_d_70; // synthesis translate_on always @(*) begin - litedramcore_master_p0_wrdata_mask <= 4'd0; + litedramcore_master_p3_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; + litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask; + litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask; end // synthesis translate_off dummy_d_70 = dummy_s; @@ -3571,11 +3459,11 @@ end reg dummy_d_71; // synthesis translate_on always @(*) begin - litedramcore_master_p0_rddata_en <= 1'd0; + litedramcore_master_p3_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; + litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; end else begin - litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en; + litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en; end // synthesis translate_off dummy_d_71 = dummy_s; @@ -3586,11 +3474,11 @@ end reg dummy_d_72; // synthesis translate_on always @(*) begin - litedramcore_master_p1_address <= 15'd0; + litedramcore_master_p0_address <= 15'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_address <= litedramcore_slave_p1_address; + litedramcore_master_p0_address <= litedramcore_slave_p0_address; end else begin - litedramcore_master_p1_address <= litedramcore_inti_p1_address; + litedramcore_master_p0_address <= litedramcore_inti_p0_address; end // synthesis translate_off dummy_d_72 = dummy_s; @@ -3601,11 +3489,11 @@ end reg dummy_d_73; // synthesis translate_on always @(*) begin - litedramcore_master_p1_bank <= 3'd0; + litedramcore_master_p0_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; + litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; end else begin - litedramcore_master_p1_bank <= litedramcore_inti_p1_bank; + litedramcore_master_p0_bank <= litedramcore_inti_p0_bank; end // synthesis translate_off dummy_d_73 = dummy_s; @@ -3616,11 +3504,11 @@ end reg dummy_d_74; // synthesis translate_on always @(*) begin - litedramcore_master_p1_cas_n <= 1'd1; + litedramcore_master_p0_cas_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; + litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; end else begin - litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n; + litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n; end // synthesis translate_off dummy_d_74 = dummy_s; @@ -3631,11 +3519,11 @@ end reg dummy_d_75; // synthesis translate_on always @(*) begin - litedramcore_master_p1_cs_n <= 1'd1; + litedramcore_master_p0_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; + litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; end else begin - litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n; + litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n; end // synthesis translate_off dummy_d_75 = dummy_s; @@ -3646,11 +3534,11 @@ end reg dummy_d_76; // synthesis translate_on always @(*) begin - litedramcore_master_p1_ras_n <= 1'd1; + litedramcore_master_p0_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; + litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; end else begin - litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n; + litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n; end // synthesis translate_off dummy_d_76 = dummy_s; @@ -3661,9 +3549,9 @@ end reg dummy_d_77; // synthesis translate_on always @(*) begin - litedramcore_slave_p1_rddata <= 32'd0; + litedramcore_slave_p0_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; + litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; end else begin end // synthesis translate_off @@ -3675,11 +3563,11 @@ end reg dummy_d_78; // synthesis translate_on always @(*) begin - litedramcore_master_p1_we_n <= 1'd1; + litedramcore_master_p0_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; + litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; end else begin - litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n; + litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; end // synthesis translate_off dummy_d_78 = dummy_s; @@ -3690,9 +3578,9 @@ end reg dummy_d_79; // synthesis translate_on always @(*) begin - litedramcore_slave_p1_rddata_valid <= 1'd0; + litedramcore_slave_p0_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end else begin end // synthesis translate_off @@ -3704,11 +3592,11 @@ end reg dummy_d_80; // synthesis translate_on always @(*) begin - litedramcore_master_p1_cke <= 1'd0; + litedramcore_master_p0_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; + litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; end else begin - litedramcore_master_p1_cke <= litedramcore_inti_p1_cke; + litedramcore_master_p0_cke <= litedramcore_inti_p0_cke; end // synthesis translate_off dummy_d_80 = dummy_s; @@ -3719,11 +3607,11 @@ end reg dummy_d_81; // synthesis translate_on always @(*) begin - litedramcore_master_p1_odt <= 1'd0; + litedramcore_master_p0_odt <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; + litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; end else begin - litedramcore_master_p1_odt <= litedramcore_inti_p1_odt; + litedramcore_master_p0_odt <= litedramcore_inti_p0_odt; end // synthesis translate_off dummy_d_81 = dummy_s; @@ -3734,11 +3622,11 @@ end reg dummy_d_82; // synthesis translate_on always @(*) begin - litedramcore_master_p1_reset_n <= 1'd0; + litedramcore_master_p0_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; end else begin - litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; + litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n; end // synthesis translate_off dummy_d_82 = dummy_s; @@ -3749,11 +3637,11 @@ end reg dummy_d_83; // synthesis translate_on always @(*) begin - litedramcore_master_p1_act_n <= 1'd1; + litedramcore_master_p0_act_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; end else begin - litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n; + litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n; end // synthesis translate_off dummy_d_83 = dummy_s; @@ -3764,11 +3652,11 @@ end reg dummy_d_84; // synthesis translate_on always @(*) begin - litedramcore_master_p1_wrdata <= 32'd0; + litedramcore_master_p0_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; end else begin - litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata; + litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata; end // synthesis translate_off dummy_d_84 = dummy_s; @@ -3779,10 +3667,10 @@ end reg dummy_d_85; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_rddata <= 32'd0; + litedramcore_inti_p1_rddata <= 32'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; + litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata; end // synthesis translate_off dummy_d_85 = dummy_s; @@ -3793,11 +3681,11 @@ end reg dummy_d_86; // synthesis translate_on always @(*) begin - litedramcore_master_p1_wrdata_en <= 1'd0; + litedramcore_master_p0_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; + litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en; end // synthesis translate_off dummy_d_86 = dummy_s; @@ -3808,10 +3696,10 @@ end reg dummy_d_87; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_rddata_valid <= 1'd0; + litedramcore_inti_p1_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end // synthesis translate_off dummy_d_87 = dummy_s; @@ -3822,11 +3710,11 @@ end reg dummy_d_88; // synthesis translate_on always @(*) begin - litedramcore_master_p1_wrdata_mask <= 4'd0; + litedramcore_master_p0_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; + litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask; end // synthesis translate_off dummy_d_88 = dummy_s; @@ -3837,11 +3725,11 @@ end reg dummy_d_89; // synthesis translate_on always @(*) begin - litedramcore_master_p1_rddata_en <= 1'd0; + litedramcore_master_p0_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; + litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; end else begin - litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; + litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en; end // synthesis translate_off dummy_d_89 = dummy_s; @@ -3852,11 +3740,11 @@ end reg dummy_d_90; // synthesis translate_on always @(*) begin - litedramcore_master_p2_address <= 15'd0; + litedramcore_master_p1_address <= 15'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_address <= litedramcore_slave_p2_address; + litedramcore_master_p1_address <= litedramcore_slave_p1_address; end else begin - litedramcore_master_p2_address <= litedramcore_inti_p2_address; + litedramcore_master_p1_address <= litedramcore_inti_p1_address; end // synthesis translate_off dummy_d_90 = dummy_s; @@ -3867,11 +3755,11 @@ end reg dummy_d_91; // synthesis translate_on always @(*) begin - litedramcore_master_p2_bank <= 3'd0; + litedramcore_master_p1_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; + litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; end else begin - litedramcore_master_p2_bank <= litedramcore_inti_p2_bank; + litedramcore_master_p1_bank <= litedramcore_inti_p1_bank; end // synthesis translate_off dummy_d_91 = dummy_s; @@ -3882,11 +3770,11 @@ end reg dummy_d_92; // synthesis translate_on always @(*) begin - litedramcore_master_p2_cas_n <= 1'd1; + litedramcore_master_p1_cas_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; + litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; end else begin - litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n; + litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n; end // synthesis translate_off dummy_d_92 = dummy_s; @@ -3897,11 +3785,11 @@ end reg dummy_d_93; // synthesis translate_on always @(*) begin - litedramcore_master_p2_cs_n <= 1'd1; + litedramcore_master_p1_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; + litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; end else begin - litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n; + litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n; end // synthesis translate_off dummy_d_93 = dummy_s; @@ -4695,6 +4583,39 @@ end // synthesis translate_off reg dummy_d_122; // synthesis translate_on +always @(*) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_122 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_123; +// synthesis translate_on always @(*) begin litedramcore_bankmachine0_refresh_gnt <= 1'd0; case (bankmachine0_state) @@ -4721,12 +4642,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_122 = dummy_s; + dummy_d_123 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_123; +reg dummy_d_124; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_valid <= 1'd0; @@ -4769,12 +4690,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_123 = dummy_s; + dummy_d_124 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_124; +reg dummy_d_125; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_row_open <= 1'd0; @@ -4802,12 +4723,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_124 = dummy_s; + dummy_d_125 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_125; +reg dummy_d_126; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_row_close <= 1'd0; @@ -4835,12 +4756,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_125 = dummy_s; + dummy_d_126 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_126; +reg dummy_d_127; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; @@ -4876,39 +4797,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_126 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_127; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase // synthesis translate_off dummy_d_127 = dummy_s; // synthesis translate_on @@ -5329,16 +5217,13 @@ end reg dummy_d_138; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine1_req_rdata_valid <= 1'd0; case (bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -5351,6 +5236,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -5362,7 +5262,7 @@ end reg dummy_d_139; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + litedramcore_bankmachine1_refresh_gnt <= 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5371,6 +5271,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -5381,21 +5284,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -5407,19 +5295,22 @@ end reg dummy_d_140; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd0; + litedramcore_bankmachine1_cmd_valid <= 1'd0; case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd1; + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; end end + 3'd4: begin + end 3'd5: begin end 3'd6: begin @@ -5429,6 +5320,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -5440,18 +5343,15 @@ end reg dummy_d_141; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_valid <= 1'd0; + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -5465,18 +5365,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -6133,7 +6021,7 @@ end reg dummy_d_158; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine2_row_open <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6141,7 +6029,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine2_row_open <= 1'd1; end end 3'd4: begin @@ -6166,18 +6054,18 @@ end reg dummy_d_159; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; + litedramcore_bankmachine2_row_close <= 1'd0; case (bankmachine2_state) 1'd1: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; - end end 3'd4: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6199,18 +6087,15 @@ end reg dummy_d_160; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; + litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; case (bankmachine2_state) 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6221,6 +6106,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -6232,13 +6129,16 @@ end reg dummy_d_161; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -6251,18 +6151,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -6684,6 +6572,39 @@ end // synthesis translate_off reg dummy_d_172; // synthesis translate_on +always @(*) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_172 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_173; +// synthesis translate_on always @(*) begin litedramcore_bankmachine3_req_rdata_valid <= 1'd0; case (bankmachine3_state) @@ -6722,12 +6643,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_172 = dummy_s; + dummy_d_173 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_173; +reg dummy_d_174; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_refresh_gnt <= 1'd0; @@ -6755,12 +6676,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_173 = dummy_s; + dummy_d_174 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_174; +reg dummy_d_175; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_valid <= 1'd0; @@ -6803,12 +6724,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_174 = dummy_s; + dummy_d_175 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_175; +reg dummy_d_176; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_row_open <= 1'd0; @@ -6836,12 +6757,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_175 = dummy_s; + dummy_d_176 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_176; +reg dummy_d_177; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_row_close <= 1'd0; @@ -6868,39 +6789,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_176 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_177; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase // synthesis translate_off dummy_d_177 = dummy_s; // synthesis translate_on @@ -7441,18 +7329,15 @@ end reg dummy_d_191; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_valid <= 1'd0; + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -7466,18 +7351,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -7489,15 +7362,18 @@ end reg dummy_d_192; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine4_cmd_valid <= 1'd0; case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 3'd4: begin @@ -7511,6 +7387,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -8086,18 +7974,18 @@ end reg dummy_d_207; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine5_refresh_gnt <= 1'd0; case (bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8119,18 +8007,21 @@ end reg dummy_d_208; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd0; + litedramcore_bankmachine5_cmd_valid <= 1'd0; case (bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -8141,6 +8032,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -8152,44 +8055,29 @@ end reg dummy_d_209; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_valid <= 1'd0; + litedramcore_bankmachine5_row_open <= 1'd0; case (bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + litedramcore_bankmachine5_row_open <= 1'd1; end end 3'd4: begin end 3'd5: begin end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end endcase // synthesis translate_off dummy_d_209 = dummy_s; @@ -8200,7 +8088,7 @@ end reg dummy_d_210; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_row_open <= 1'd0; + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -8208,7 +8096,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open <= 1'd1; + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -8844,39 +8732,6 @@ end // synthesis translate_off reg dummy_d_226; // synthesis translate_on -always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_226 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_227; -// synthesis translate_on always @(*) begin litedramcore_bankmachine6_row_open <= 1'd0; case (bankmachine6_state) @@ -8903,12 +8758,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_227 = dummy_s; + dummy_d_226 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_228; +reg dummy_d_227; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_row_close <= 1'd0; @@ -8936,12 +8791,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_228 = dummy_s; + dummy_d_227 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_229; +reg dummy_d_228; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; @@ -8978,12 +8833,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_229 = dummy_s; + dummy_d_228 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_230; +reg dummy_d_229; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; @@ -9014,12 +8869,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_230 = dummy_s; + dummy_d_229 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_231; +reg dummy_d_230; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_we <= 1'd0; @@ -9061,6 +8916,39 @@ always @(*) begin end end endcase +// synthesis translate_off + dummy_d_230 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_231; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_231 = dummy_s; // synthesis translate_on @@ -9441,6 +9329,39 @@ end // synthesis translate_off reg dummy_d_241; // synthesis translate_on +always @(*) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_241 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_242; +// synthesis translate_on always @(*) begin litedramcore_bankmachine7_refresh_gnt <= 1'd0; case (bankmachine7_state) @@ -9467,12 +9388,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_241 = dummy_s; + dummy_d_242 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_242; +reg dummy_d_243; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_valid <= 1'd0; @@ -9515,12 +9436,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_242 = dummy_s; + dummy_d_243 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_243; +reg dummy_d_244; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_row_open <= 1'd0; @@ -9548,12 +9469,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_243 = dummy_s; + dummy_d_244 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_244; +reg dummy_d_245; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_row_close <= 1'd0; @@ -9581,12 +9502,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_244 = dummy_s; + dummy_d_245 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_245; +reg dummy_d_246; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; @@ -9622,39 +9543,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_245 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_246; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase // synthesis translate_off dummy_d_246 = dummy_s; // synthesis translate_on @@ -10730,7 +10618,7 @@ reg dummy_d_282; // synthesis translate_on always @(*) begin csrbank0_sel <= 1'd0; - csrbank0_sel <= (interface0_bank_bus_adr[13:11] == 2'd2); + csrbank0_sel <= (interface0_bank_bus_adr[13:9] == 2'd2); if (interface0_bank_bus_adr[0]) begin csrbank0_sel <= 1'd0; end @@ -10739,11 +10627,11 @@ always @(*) begin // synthesis translate_on end assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd0)); -assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd0)); +assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd0)); +assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd0)); assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd1)); -assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd1)); +assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd1)); +assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd1)); assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; @@ -10752,7 +10640,7 @@ reg dummy_d_283; // synthesis translate_on always @(*) begin csrbank1_sel <= 1'd0; - csrbank1_sel <= (interface1_bank_bus_adr[13:11] == 1'd0); + csrbank1_sel <= (interface1_bank_bus_adr[13:9] == 1'd0); if (interface1_bank_bus_adr[0]) begin csrbank1_sel <= 1'd0; end @@ -10761,35 +10649,35 @@ always @(*) begin // synthesis translate_on end assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; -assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd0)); -assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd0)); +assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd0)); +assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd0)); assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; -assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd1)); -assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd1)); +assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd1)); +assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd1)); assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd2)); -assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd2)); +assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd2)); +assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd2)); assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd3)); -assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd3)); +assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd3)); +assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd3)); assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd4)); -assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd4)); +assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd4)); +assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd4)); assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; -assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd5)); -assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd5)); +assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd5)); +assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd5)); assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd6)); -assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd6)); assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd7)); -assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd7)); assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd8)); -assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd8)); assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd9)); -assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd9)); assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0]; assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; @@ -10799,7 +10687,7 @@ reg dummy_d_284; // synthesis translate_on always @(*) begin csrbank2_sel <= 1'd0; - csrbank2_sel <= (interface2_bank_bus_adr[13:11] == 1'd1); + csrbank2_sel <= (interface2_bank_bus_adr[13:9] == 1'd1); if (interface2_bank_bus_adr[0]) begin csrbank2_sel <= 1'd0; end @@ -10808,217 +10696,105 @@ always @(*) begin // synthesis translate_on end assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; -assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd0)); -assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd0)); +assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd0)); +assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd0)); assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd1)); -assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd1)); +assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd1)); +assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd1)); assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd2)); -assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd2)); -assign csrbank2_dfii_pi0_address1_r = interface2_bank_bus_dat_w[6:0]; -assign csrbank2_dfii_pi0_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd3)); -assign csrbank2_dfii_pi0_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd3)); -assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd4)); -assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd4)); +assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd2)); +assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd2)); +assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0]; +assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd3)); +assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd3)); assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd5)); -assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd5)); -assign csrbank2_dfii_pi0_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd6)); -assign csrbank2_dfii_pi0_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd6)); -assign csrbank2_dfii_pi0_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd7)); -assign csrbank2_dfii_pi0_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd7)); -assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd8)); -assign csrbank2_dfii_pi0_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd8)); -assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd9)); -assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd9)); -assign csrbank2_dfii_pi0_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd10)); -assign csrbank2_dfii_pi0_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd10)); -assign csrbank2_dfii_pi0_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd11)); -assign csrbank2_dfii_pi0_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd11)); -assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd12)); -assign csrbank2_dfii_pi0_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd12)); -assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd13)); -assign csrbank2_dfii_pi0_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd13)); +assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd4)); +assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd4)); +assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd5)); +assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd5)); +assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd6)); +assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd6)); assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd14)); -assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd14)); +assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd7)); +assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd7)); assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd15)); -assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd15)); -assign csrbank2_dfii_pi1_address1_r = interface2_bank_bus_dat_w[6:0]; -assign csrbank2_dfii_pi1_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd16)); -assign csrbank2_dfii_pi1_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd16)); -assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd17)); -assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd17)); +assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd8)); +assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd8)); +assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0]; +assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd9)); +assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd9)); assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd18)); -assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd18)); -assign csrbank2_dfii_pi1_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd19)); -assign csrbank2_dfii_pi1_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd19)); -assign csrbank2_dfii_pi1_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd20)); -assign csrbank2_dfii_pi1_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd20)); -assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd21)); -assign csrbank2_dfii_pi1_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd21)); -assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd22)); -assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd22)); -assign csrbank2_dfii_pi1_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd23)); -assign csrbank2_dfii_pi1_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd23)); -assign csrbank2_dfii_pi1_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd24)); -assign csrbank2_dfii_pi1_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd24)); -assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd25)); -assign csrbank2_dfii_pi1_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd25)); -assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd26)); -assign csrbank2_dfii_pi1_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd26)); +assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd10)); +assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd10)); +assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd11)); +assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd11)); +assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd12)); +assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd12)); assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd27)); -assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd27)); +assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd13)); +assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd13)); assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd28)); -assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd28)); -assign csrbank2_dfii_pi2_address1_r = interface2_bank_bus_dat_w[6:0]; -assign csrbank2_dfii_pi2_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd29)); -assign csrbank2_dfii_pi2_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd29)); -assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd30)); -assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd30)); +assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd14)); +assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd14)); +assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[14:0]; +assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd15)); +assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd15)); assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd31)); -assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd31)); -assign csrbank2_dfii_pi2_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd32)); -assign csrbank2_dfii_pi2_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd32)); -assign csrbank2_dfii_pi2_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd33)); -assign csrbank2_dfii_pi2_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd33)); -assign csrbank2_dfii_pi2_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd34)); -assign csrbank2_dfii_pi2_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd34)); -assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd35)); -assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd35)); -assign csrbank2_dfii_pi2_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd36)); -assign csrbank2_dfii_pi2_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd36)); -assign csrbank2_dfii_pi2_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd37)); -assign csrbank2_dfii_pi2_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd37)); -assign csrbank2_dfii_pi2_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd38)); -assign csrbank2_dfii_pi2_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd38)); -assign csrbank2_dfii_pi2_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd39)); -assign csrbank2_dfii_pi2_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd39)); +assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd16)); +assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd16)); +assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd17)); +assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd17)); +assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd18)); +assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd18)); assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd40)); -assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd40)); +assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd19)); +assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd19)); assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd41)); -assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd41)); -assign csrbank2_dfii_pi3_address1_r = interface2_bank_bus_dat_w[6:0]; -assign csrbank2_dfii_pi3_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd42)); -assign csrbank2_dfii_pi3_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd42)); -assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd43)); -assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd43)); +assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd20)); +assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd20)); +assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[14:0]; +assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd21)); +assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd21)); assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd44)); -assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd44)); -assign csrbank2_dfii_pi3_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd45)); -assign csrbank2_dfii_pi3_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd45)); -assign csrbank2_dfii_pi3_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd46)); -assign csrbank2_dfii_pi3_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd46)); -assign csrbank2_dfii_pi3_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd47)); -assign csrbank2_dfii_pi3_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd47)); -assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd48)); -assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd48)); -assign csrbank2_dfii_pi3_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd49)); -assign csrbank2_dfii_pi3_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd49)); -assign csrbank2_dfii_pi3_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd50)); -assign csrbank2_dfii_pi3_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd50)); -assign csrbank2_dfii_pi3_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd51)); -assign csrbank2_dfii_pi3_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd51)); -assign csrbank2_dfii_pi3_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd52)); -assign csrbank2_dfii_pi3_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd52)); +assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd22)); +assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd22)); +assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd23)); +assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd23)); +assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd24)); +assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd24)); assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; -assign csrbank2_dfii_pi0_address1_w = litedramcore_phaseinjector0_address_storage[14:8]; -assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[7:0]; +assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0]; assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; -assign csrbank2_dfii_pi0_wrdata3_w = litedramcore_phaseinjector0_wrdata_storage[31:24]; -assign csrbank2_dfii_pi0_wrdata2_w = litedramcore_phaseinjector0_wrdata_storage[23:16]; -assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[15:8]; -assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[7:0]; -assign csrbank2_dfii_pi0_rddata3_w = litedramcore_phaseinjector0_status[31:24]; -assign csrbank2_dfii_pi0_rddata2_w = litedramcore_phaseinjector0_status[23:16]; -assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_status[15:8]; -assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_status[7:0]; -assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata0_we; +assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0]; +assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata_we; assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0]; -assign csrbank2_dfii_pi1_address1_w = litedramcore_phaseinjector1_address_storage[14:8]; -assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[7:0]; +assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0]; assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; -assign csrbank2_dfii_pi1_wrdata3_w = litedramcore_phaseinjector1_wrdata_storage[31:24]; -assign csrbank2_dfii_pi1_wrdata2_w = litedramcore_phaseinjector1_wrdata_storage[23:16]; -assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[15:8]; -assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[7:0]; -assign csrbank2_dfii_pi1_rddata3_w = litedramcore_phaseinjector1_status[31:24]; -assign csrbank2_dfii_pi1_rddata2_w = litedramcore_phaseinjector1_status[23:16]; -assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_status[15:8]; -assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_status[7:0]; -assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata0_we; +assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0]; +assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata_we; assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0]; -assign csrbank2_dfii_pi2_address1_w = litedramcore_phaseinjector2_address_storage[14:8]; -assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[7:0]; +assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[14:0]; assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0]; -assign csrbank2_dfii_pi2_wrdata3_w = litedramcore_phaseinjector2_wrdata_storage[31:24]; -assign csrbank2_dfii_pi2_wrdata2_w = litedramcore_phaseinjector2_wrdata_storage[23:16]; -assign csrbank2_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[15:8]; -assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[7:0]; -assign csrbank2_dfii_pi2_rddata3_w = litedramcore_phaseinjector2_status[31:24]; -assign csrbank2_dfii_pi2_rddata2_w = litedramcore_phaseinjector2_status[23:16]; -assign csrbank2_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_status[15:8]; -assign csrbank2_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_status[7:0]; -assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata0_we; +assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0]; +assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0]; +assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata_we; assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0]; -assign csrbank2_dfii_pi3_address1_w = litedramcore_phaseinjector3_address_storage[14:8]; -assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[7:0]; +assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[14:0]; assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0]; -assign csrbank2_dfii_pi3_wrdata3_w = litedramcore_phaseinjector3_wrdata_storage[31:24]; -assign csrbank2_dfii_pi3_wrdata2_w = litedramcore_phaseinjector3_wrdata_storage[23:16]; -assign csrbank2_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[15:8]; -assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[7:0]; -assign csrbank2_dfii_pi3_rddata3_w = litedramcore_phaseinjector3_status[31:24]; -assign csrbank2_dfii_pi3_rddata2_w = litedramcore_phaseinjector3_status[23:16]; -assign csrbank2_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_status[15:8]; -assign csrbank2_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_status[7:0]; -assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata0_we; +assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0]; +assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0]; +assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata_we; assign adr = csr_port_adr; assign we = csr_port_we; assign dat_w = csr_port_dat_w; @@ -14159,7 +13935,7 @@ always @(posedge sys_clk) begin new_master_rdata_valid8 <= new_master_rdata_valid7; interface0_bank_bus_dat_r <= 1'd0; if (csrbank0_sel) begin - case (interface0_bank_bus_adr[3]) + case (interface0_bank_bus_adr[1]) 1'd0: begin interface0_bank_bus_dat_r <= csrbank0_init_done0_w; end @@ -14178,7 +13954,7 @@ always @(posedge sys_clk) begin init_error_re <= csrbank0_init_error0_re; interface1_bank_bus_dat_r <= 1'd0; if (csrbank1_sel) begin - case (interface1_bank_bus_adr[6:3]) + case (interface1_bank_bus_adr[4:1]) 1'd0: begin interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; end @@ -14225,7 +14001,7 @@ always @(posedge sys_clk) begin a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; interface2_bank_bus_dat_r <= 1'd0; if (csrbank2_sel) begin - case (interface2_bank_bus_adr[8:3]) + case (interface2_bank_bus_adr[5:1]) 1'd0: begin interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; end @@ -14236,154 +14012,70 @@ always @(posedge sys_clk) begin interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; end 3'd4: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; end 3'd5: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; end 3'd6: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w; end 3'd7: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; end 4'd8: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w; + interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; end 4'd9: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; end 4'd10: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; end 4'd11: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; end 4'd12: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w; end 4'd13: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; end 4'd14: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; + interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; end 4'd15: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; end 5'd16: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; end 5'd17: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; end 5'd18: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w; end 5'd19: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata3_w; - end - 5'd20: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata2_w; - end - 5'd21: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w; - end - 5'd22: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; - end - 5'd23: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata3_w; - end - 5'd24: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata2_w; - end - 5'd25: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w; - end - 5'd26: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w; - end - 5'd27: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; - end - 5'd28: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; - end - 5'd29: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address1_w; - end - 5'd30: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; - end - 5'd31: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; - end - 6'd32: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata3_w; - end - 6'd33: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata2_w; - end - 6'd34: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata1_w; - end - 6'd35: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; - end - 6'd36: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata3_w; - end - 6'd37: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata2_w; - end - 6'd38: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata1_w; - end - 6'd39: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata0_w; - end - 6'd40: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; end - 6'd41: begin + 5'd20: begin interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; end - 6'd42: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address1_w; - end - 6'd43: begin + 5'd21: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; end - 6'd44: begin + 5'd22: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; end - 6'd45: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata3_w; - end - 6'd46: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata2_w; - end - 6'd47: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata1_w; - end - 6'd48: begin + 5'd23: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; end - 6'd49: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata3_w; - end - 6'd50: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata2_w; - end - 6'd51: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata1_w; - end - 6'd52: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata0_w; + 5'd24: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w; end endcase end @@ -14395,112 +14087,64 @@ always @(posedge sys_clk) begin litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; end litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; - if (csrbank2_dfii_pi0_address1_re) begin - litedramcore_phaseinjector0_address_storage[14:8] <= csrbank2_dfii_pi0_address1_r; - end if (csrbank2_dfii_pi0_address0_re) begin - litedramcore_phaseinjector0_address_storage[7:0] <= csrbank2_dfii_pi0_address0_r; + litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r; end litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; if (csrbank2_dfii_pi0_baddress0_re) begin litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; end litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; - if (csrbank2_dfii_pi0_wrdata3_re) begin - litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank2_dfii_pi0_wrdata3_r; - end - if (csrbank2_dfii_pi0_wrdata2_re) begin - litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank2_dfii_pi0_wrdata2_r; - end - if (csrbank2_dfii_pi0_wrdata1_re) begin - litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank2_dfii_pi0_wrdata1_r; - end if (csrbank2_dfii_pi0_wrdata0_re) begin - litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank2_dfii_pi0_wrdata0_r; + litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; end litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; if (csrbank2_dfii_pi1_command0_re) begin litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; end litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; - if (csrbank2_dfii_pi1_address1_re) begin - litedramcore_phaseinjector1_address_storage[14:8] <= csrbank2_dfii_pi1_address1_r; - end if (csrbank2_dfii_pi1_address0_re) begin - litedramcore_phaseinjector1_address_storage[7:0] <= csrbank2_dfii_pi1_address0_r; + litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r; end litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; if (csrbank2_dfii_pi1_baddress0_re) begin litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; end litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; - if (csrbank2_dfii_pi1_wrdata3_re) begin - litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank2_dfii_pi1_wrdata3_r; - end - if (csrbank2_dfii_pi1_wrdata2_re) begin - litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank2_dfii_pi1_wrdata2_r; - end - if (csrbank2_dfii_pi1_wrdata1_re) begin - litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank2_dfii_pi1_wrdata1_r; - end if (csrbank2_dfii_pi1_wrdata0_re) begin - litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank2_dfii_pi1_wrdata0_r; + litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; end litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; if (csrbank2_dfii_pi2_command0_re) begin litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; end litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; - if (csrbank2_dfii_pi2_address1_re) begin - litedramcore_phaseinjector2_address_storage[14:8] <= csrbank2_dfii_pi2_address1_r; - end if (csrbank2_dfii_pi2_address0_re) begin - litedramcore_phaseinjector2_address_storage[7:0] <= csrbank2_dfii_pi2_address0_r; + litedramcore_phaseinjector2_address_storage[14:0] <= csrbank2_dfii_pi2_address0_r; end litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; if (csrbank2_dfii_pi2_baddress0_re) begin litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; end litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; - if (csrbank2_dfii_pi2_wrdata3_re) begin - litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank2_dfii_pi2_wrdata3_r; - end - if (csrbank2_dfii_pi2_wrdata2_re) begin - litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank2_dfii_pi2_wrdata2_r; - end - if (csrbank2_dfii_pi2_wrdata1_re) begin - litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank2_dfii_pi2_wrdata1_r; - end if (csrbank2_dfii_pi2_wrdata0_re) begin - litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank2_dfii_pi2_wrdata0_r; + litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; end litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; if (csrbank2_dfii_pi3_command0_re) begin litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; end litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; - if (csrbank2_dfii_pi3_address1_re) begin - litedramcore_phaseinjector3_address_storage[14:8] <= csrbank2_dfii_pi3_address1_r; - end if (csrbank2_dfii_pi3_address0_re) begin - litedramcore_phaseinjector3_address_storage[7:0] <= csrbank2_dfii_pi3_address0_r; + litedramcore_phaseinjector3_address_storage[14:0] <= csrbank2_dfii_pi3_address0_r; end litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; if (csrbank2_dfii_pi3_baddress0_re) begin litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; end litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; - if (csrbank2_dfii_pi3_wrdata3_re) begin - litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank2_dfii_pi3_wrdata3_r; - end - if (csrbank2_dfii_pi3_wrdata2_re) begin - litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank2_dfii_pi3_wrdata2_r; - end - if (csrbank2_dfii_pi3_wrdata1_re) begin - litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank2_dfii_pi3_wrdata1_r; - end if (csrbank2_dfii_pi3_wrdata0_re) begin - litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank2_dfii_pi3_wrdata0_r; + litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; end litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; if (sys_rst) begin