diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl
index 15e082b..9dc476f 100644
--- a/fpga/top-arty.vhdl
+++ b/fpga/top-arty.vhdl
@@ -24,7 +24,7 @@ entity toplevel is
         LOG_LENGTH         : natural := 512;
         USE_LITEETH        : boolean  := false;
         UART_IS_16550      : boolean  := false;
-        HAS_UART1          : boolean  := false
+        HAS_UART1          : boolean  := true
         );
     port(
         ext_clk   : in  std_ulogic;
diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl
index 3f27af7..2300456 100644
--- a/fpga/top-generic.vhdl
+++ b/fpga/top-generic.vhdl
@@ -12,7 +12,7 @@ entity toplevel is
 	CLK_INPUT     : positive := 100000000;
 	CLK_FREQUENCY : positive := 100000000;
 	DISABLE_FLATTEN_CORE : boolean := false;
-        UART_IS_16550 : boolean  := false
+        UART_IS_16550 : boolean  := true
 	);
     port(
 	ext_clk   : in  std_ulogic;
diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl
index 5fc3bab..ac760a1 100644
--- a/fpga/top-nexys-video.vhdl
+++ b/fpga/top-nexys-video.vhdl
@@ -20,7 +20,7 @@ entity toplevel is
         SPI_FLASH_OFFSET   : integer := 10485760;
         SPI_FLASH_DEF_CKDV : natural := 1;
         SPI_FLASH_DEF_QUAD : boolean := true;
-        UART_IS_16550      : boolean  := false;
+        UART_IS_16550      : boolean := true;
 	);
     port(
 	ext_clk   : in  std_ulogic;
diff --git a/microwatt.core b/microwatt.core
index 5fb81f5..046020d 100644
--- a/microwatt.core
+++ b/microwatt.core
@@ -315,7 +315,7 @@ parameters:
     datatype    : bool
     description : Use 16550-compatible UART from OpenCores
     paramtype   : generic
-    default     : false
+    default     : true
 
   has_uart1:
     datatype    : bool
diff --git a/soc.vhdl b/soc.vhdl
index 6ff52d6..0a70026 100644
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -63,7 +63,7 @@ entity soc is
         SPI_FLASH_DEF_QUAD : boolean := false;
         LOG_LENGTH         : natural := 512;
         HAS_LITEETH        : boolean := false;
-	UART0_IS_16550     : boolean := false;
+	UART0_IS_16550     : boolean := true;
 	HAS_UART1          : boolean := false
 	);
     port(