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@ -505,30 +505,11 @@ begin
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-- Next insn adder used in a couple of places
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next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
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-- rotator control signals
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if ( (e_in.insn_type = OP_SHR) ) then
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right_shift <= '1';
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else
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right_shift <= '0';
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end if;
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if ( e_in.insn_type = OP_RLC ) then
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rot_clear_left <= '1';
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else
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rot_clear_left <= '0';
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end if;
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if ( (e_in.insn_type = OP_RLC) or (e_in.insn_type = OP_RLCR) ) then
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rot_clear_right <= '1';
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else
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rot_clear_right <= '0';
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end if;
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if ( e_in.insn_type = OP_EXTSWSLI ) then
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rot_sign_ext <= '1';
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else
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rot_sign_ext <= '0';
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end if;
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-- rotator control signals
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right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
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rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
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rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
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rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
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ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
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ctrl_tmp.irq_state <= WRITE_SRR0;
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@ -864,7 +845,7 @@ begin
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report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
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"=" & to_hstring(a_in);
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result_en := '1';
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if (is_fast_spr(e_in.read_reg1) = '1') then
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if is_fast_spr(e_in.read_reg1) then
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result := a_in;
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if decode_spr_num(e_in.insn) = SPR_XER then
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-- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
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@ -953,7 +934,7 @@ begin
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when OP_MTSPR =>
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report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
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"=" & to_hstring(c_in);
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if ( is_fast_spr(e_in.write_reg) = '1' ) then
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if is_fast_spr(e_in.write_reg) then
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result := c_in;
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result_en := '1';
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if decode_spr_num(e_in.insn) = SPR_XER then
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