From eaf6883e5720b185d369debf3ef1321ddc5b9b51 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Mon, 1 Jun 2020 23:58:47 +1000 Subject: [PATCH] litedram: Update to latest LiteX/LiteDRAM version Signed-off-by: Benjamin Herrenschmidt --- litedram/gen-src/arty.yml | 1 + litedram/gen-src/generate.py | 5 +- litedram/gen-src/nexys-video.yml | 1 + litedram/generated/arty/litedram-initmem.vhdl | 64 +- litedram/generated/arty/litedram_core.init | 673 +- litedram/generated/arty/litedram_core.v | 2475 +++-- .../generated/nexys-video/litedram_core.init | 673 +- .../generated/nexys-video/litedram_core.v | 2149 +++-- litedram/generated/sim/litedram-initmem.vhdl | 3 +- litedram/generated/sim/litedram_core.init | 1112 ++- litedram/generated/sim/litedram_core.v | 7988 ++++------------- 11 files changed, 5254 insertions(+), 9890 deletions(-) diff --git a/litedram/gen-src/arty.yml b/litedram/gen-src/arty.yml index a4c982b..40211f0 100644 --- a/litedram/gen-src/arty.yml +++ b/litedram/gen-src/arty.yml @@ -38,4 +38,5 @@ # CSR Port ----------------------------------------------------------------- "csr_base" : 0xc0100000, # For cpu=None only + csr_data_width : 32, } diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py index 1c8069c..7dcfc4e 100755 --- a/litedram/gen-src/generate.py +++ b/litedram/gen-src/generate.py @@ -38,7 +38,7 @@ def build_init_code(build_dir, is_sim): sw_inc_dir = os.path.join(sw_dir, "include") gen_inc_dir = os.path.join(sw_inc_dir, "generated") src_dir = os.path.join(gen_src_dir, "sdram_init") - lxbios_src_dir = os.path.join(soc_directory, "software", "bios") + lxbios_src_dir = os.path.join(soc_directory, "software", "liblitedram") lxbios_inc_dir = os.path.join(soc_directory, "software", "include") print(" sw dir:", sw_dir) print("gen_inc_dir:", gen_inc_dir) @@ -109,6 +109,7 @@ def generate_one(t, mw_init): # Override values for mw_init if mw_init: core_config["cpu"] = None + core_config["cpu_variant"] = "standard" core_config["csr_alignment"] = 64 # Generate core @@ -121,7 +122,7 @@ def generate_one(t, mw_init): else: raise ValueError("Unsupported SDRAM PHY: {}".format(core_config["sdram_phy"])) - soc = LiteDRAMCore(platform, core_config, is_sim = is_sim, integrated_rom_size=0x6000, csr_data_width=32) + soc = LiteDRAMCore(platform, core_config, is_sim = is_sim, integrated_rom_size=0x6000) # Build into build_dir builder = Builder(soc, output_dir=build_dir, compile_gateware=False) diff --git a/litedram/gen-src/nexys-video.yml b/litedram/gen-src/nexys-video.yml index 23c1ce4..f9f8f09 100644 --- a/litedram/gen-src/nexys-video.yml +++ b/litedram/gen-src/nexys-video.yml @@ -38,4 +38,5 @@ # CSR Port ----------------------------------------------------------------- "csr_base" : 0xc0100000, # For cpu=None only + csr_data_width : 32, } diff --git a/litedram/generated/arty/litedram-initmem.vhdl b/litedram/generated/arty/litedram-initmem.vhdl index 717e4b6..13bd0ce 100644 --- a/litedram/generated/arty/litedram-initmem.vhdl +++ b/litedram/generated/arty/litedram-initmem.vhdl @@ -14,8 +14,8 @@ entity dram_init_mem is ); port ( clk : in std_ulogic; - wb_in : in wb_io_master_out; - wb_out : out wb_io_slave_out + wb_in : in wb_io_master_out; + wb_out : out wb_io_slave_out ); end entity dram_init_mem; @@ -47,27 +47,27 @@ architecture rtl of dram_init_mem is end procedure; impure function init_load_ram(name : string) return ram_t is - file ram_file : text open read_mode is name; - variable temp_word : std_logic_vector(63 downto 0); - variable temp_ram : ram_t := (others => (others => '0')); - variable ram_line : line; + file ram_file : text open read_mode is name; + variable temp_word : std_logic_vector(63 downto 0); + variable temp_ram : ram_t := (others => (others => '0')); + variable ram_line : line; begin report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) & " rounded to:" & integer'image(RND_PAYLOAD_SIZE); report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) & " bytes using " & integer'image(INIT_RAM_ABITS) & " address bits"; - for i in 0 to (INIT_RAM_SIZE/8)-1 loop - exit when endfile(ram_file); - readline(ram_file, ram_line); - hread(ram_line, temp_word); - temp_ram(i*2) := temp_word(31 downto 0); - temp_ram(i*2+1) := temp_word(63 downto 32); - end loop; + for i in 0 to (INIT_RAM_SIZE/8)-1 loop + exit when endfile(ram_file); + readline(ram_file, ram_line); + hread(ram_line, temp_word); + temp_ram(i*2) := temp_word(31 downto 0); + temp_ram(i*2+1) := temp_word(63 downto 32); + end loop; if RND_PAYLOAD_SIZE /= 0 then init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE); end if; - return temp_ram; + return temp_ram; end function; impure function init_zero return ram_t is @@ -95,27 +95,27 @@ architecture rtl of dram_init_mem is begin init_ram_0: process(clk) - variable adr : integer; + variable adr : integer; begin - if rising_edge(clk) then - oack <= '0'; - if (wb_in.cyc and wb_in.stb) = '1' then - adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2)))); - if wb_in.we = '0' then - obuf <= init_ram(adr); - else - for i in 0 to 3 loop - if wb_in.sel(i) = '1' then - init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= - wb_in.dat(((i + 1) * 8) - 1 downto i * 8); - end if; - end loop; - end if; - oack <= '1'; - end if; + if rising_edge(clk) then + oack <= '0'; + if (wb_in.cyc and wb_in.stb) = '1' then + adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2)))); + if wb_in.we = '0' then + obuf <= init_ram(adr); + else + for i in 0 to 3 loop + if wb_in.sel(i) = '1' then + init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= + wb_in.dat(((i + 1) * 8) - 1 downto i * 8); + end if; + end loop; + end if; + oack <= '1'; + end if; wb_out.ack <= oack; wb_out.dat <= obuf; - end if; + end if; end process; wb_out.stall <= '0'; diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init index 2325bba..d20e710 100644 --- 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-4bfffa194bfff0d5 -4bfff6b54bfff661 +386000c84bfff111 +4bfffa194bfff145 +4bfff7254bfff6d1 4082001c2c230000 7f80df2a7c0004ac 7f80d72a7c0004ac @@ -1100,27 +1086,27 @@ f821ff7148000c8d 4bffffec38600001 0100000000000000 3c4c000100000680 -3d20c00038428f94 +3d20c00038428f04 6129200060000000 -f922801079290020 +f922800879290020 612900203d20c000 7c0004ac79290020 3d40001c7d204eea 7d295392614a2000 -394a0018e9428010 +394a0018e9428008 7c0004ac3929ffff 4e8000207d2057ea 0000000000000000 3c4c000100000000 -6000000038428f34 -39290010e9228010 +6000000038428ea4 +39290010e9228008 7d204eea7c0004ac 4082ffe871290008 -e94280105469063e +e94280085469063e 7d2057ea7c0004ac 000000004e800020 0000000000000000 -38428ef03c4c0001 +38428e603c4c0001 fbc1fff07c0802a6 3bc3fffffbe1fff8 f821ffd1f8010010 @@ -1194,7 +1180,7 @@ f924000039290002 7c6307b43863ffe0 000000004e800020 0000000000000000 -38428ca03c4c0001 +38428c103c4c0001 3d2037367c0802a6 612935347d908026 65293332792907c6 @@ -1228,7 +1214,7 @@ fbfd00007fe9fa14 4bfffff07d29f392 0300000000000000 3c4c000100000580 -7c0802a638428b94 +7c0802a638428b04 f821ffb1480006e9 7c7f1b78eb630000 7cbd2b787c9c2378 @@ -1244,7 +1230,7 @@ f821ffb1480006e9 4bffffb8f93f0000 0100000000000000 3c4c000100000580 -7c0802a638428b14 +7c0802a638428a84 f821ffa148000661 7c9b23787c7d1b78 388000007ca32b78 @@ -1275,7 +1261,7 @@ e95d00009b270000 f95d0000394a0001 000000004bffffa8 0000078001000000 -38428a183c4c0001 +384289883c4c0001 480005397c0802a6 7c741b79f821fed1 38600000f8610060 @@ -1284,7 +1270,7 @@ f95d0000394a0001 3ac4ffff3e42ffff f92100703b410020 3ae0000060000000 -3a527fc039228008 +3a527fb839228000 f92100783ba10060 ebc1006089250000 419e00102fa90000 @@ -1497,9 +1483,9 @@ e8010010ebc1fff0 203a4b4c43202020 7a484d20646c6c25 000000000000000a -6131333764343635 +3163616539333236 0000000000000000 -0033306536316430 +0039326232623162 4d4152446574694c 6620746c69756220 6567694d206d6f72 @@ -1516,35 +1502,16 @@ e8010010ebc1fff0 20676e69746f6f42 415244206d6f7266 0000000a2e2e2e4d -20747365746d656d -000a2e2e2e737562 -7830203a7375625b -7830203a5d783025 -2073762078383025 -000a783830257830 -257830207375625b -257830203a5d7830 -3020737620783830 -00000a7838302578 20747365746d654d 6c69616620737562 252f6425203a6465 73726f7272652064 000000000000000a -20747365746d656d -0a2e2e2e61746164 -0000000000000000 -783020617461645b -7830203a5d783025 -2073762078383025 -000a783830257830 -20747365746d656d -0a2e2e2e72646461 -0000000000000000 -783020726464615b -7830203a5d783025 -2073762078383025 -000a783830257830 +20747365746d654d +6961662061746164 +2f6425203a64656c +726f727265206425 +0000000000000a73 20747365746d654d 6961662072646461 2f6425203a64656c @@ -1563,10 +1530,10 @@ e8010010ebc1fff0 000000000000002d 30252d2b64323025 0000000000006432 +00000000c0100818 00000000c0100830 +00000000c0100848 00000000c0100860 -00000000c0100890 -00000000c01008c0 6f6e204d41524453 207265646e752077 6572617764726168 diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v index 780ce87..a43ca24 100644 --- a/litedram/generated/arty/litedram_core.v +++ b/litedram/generated/arty/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-31 17:48:50 +// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-02 11:27:36 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, @@ -1607,7 +1607,7 @@ wire csrbank0_init_error0_re; wire csrbank0_init_error0_r; wire csrbank0_init_error0_we; wire csrbank0_init_error0_w; -reg csrbank0_sel = 1'd0; +wire csrbank0_sel; wire [13:0] interface1_bank_bus_adr; wire interface1_bank_bus_we; wire [31:0] interface1_bank_bus_dat_w; @@ -1624,7 +1624,7 @@ wire csrbank1_dly_sel0_re; wire [1:0] csrbank1_dly_sel0_r; wire csrbank1_dly_sel0_we; wire [1:0] csrbank1_dly_sel0_w; -reg csrbank1_sel = 1'd0; +wire csrbank1_sel; wire [13:0] interface2_bank_bus_adr; wire interface2_bank_bus_we; wire [31:0] interface2_bank_bus_dat_w; @@ -1713,7 +1713,7 @@ wire csrbank2_dfii_pi3_rddata_re; wire [31:0] csrbank2_dfii_pi3_rddata_r; wire csrbank2_dfii_pi3_rddata_we; wire [31:0] csrbank2_dfii_pi3_rddata_w; -reg csrbank2_sel = 1'd0; +wire csrbank2_sel; wire [13:0] adr; wire we; wire [31:0] dat_w; @@ -1899,7 +1899,7 @@ always @(*) begin end default: begin if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we <= litedramcore_wishbone_we; + litedramcore_we <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); end end endcase @@ -3235,6 +3235,35 @@ assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; // synthesis translate_off reg dummy_d_26; // synthesis translate_on +always @(*) begin + litedramcore_master_p2_we_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; + end else begin + litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; + end +// synthesis translate_off + dummy_d_26 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_27; +// synthesis translate_on +always @(*) begin + litedramcore_slave_p2_rddata_valid <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + end else begin + end +// synthesis translate_off + dummy_d_27 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_28; +// synthesis translate_on always @(*) begin litedramcore_master_p2_cke <= 1'd0; if (litedramcore_storage[0]) begin @@ -3243,12 +3272,12 @@ always @(*) begin litedramcore_master_p2_cke <= litedramcore_inti_p2_cke; end // synthesis translate_off - dummy_d_26 = dummy_s; + dummy_d_28 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_27; +reg dummy_d_29; // synthesis translate_on always @(*) begin litedramcore_master_p2_odt <= 1'd0; @@ -3258,12 +3287,12 @@ always @(*) begin litedramcore_master_p2_odt <= litedramcore_inti_p2_odt; end // synthesis translate_off - dummy_d_27 = dummy_s; + dummy_d_29 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_28; +reg dummy_d_30; // synthesis translate_on always @(*) begin litedramcore_master_p2_reset_n <= 1'd0; @@ -3273,12 +3302,12 @@ always @(*) begin litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n; end // synthesis translate_off - dummy_d_28 = dummy_s; + dummy_d_30 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_29; +reg dummy_d_31; // synthesis translate_on always @(*) begin litedramcore_master_p2_act_n <= 1'd1; @@ -3288,12 +3317,12 @@ always @(*) begin litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n; end // synthesis translate_off - dummy_d_29 = dummy_s; + dummy_d_31 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_30; +reg dummy_d_32; // synthesis translate_on always @(*) begin litedramcore_master_p2_wrdata <= 32'd0; @@ -3303,12 +3332,12 @@ always @(*) begin litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata; end // synthesis translate_off - dummy_d_30 = dummy_s; + dummy_d_32 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_31; +reg dummy_d_33; // synthesis translate_on always @(*) begin litedramcore_inti_p3_rddata <= 32'd0; @@ -3317,12 +3346,12 @@ always @(*) begin litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata; end // synthesis translate_off - dummy_d_31 = dummy_s; + dummy_d_33 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_32; +reg dummy_d_34; // synthesis translate_on always @(*) begin litedramcore_master_p2_wrdata_en <= 1'd0; @@ -3332,12 +3361,12 @@ always @(*) begin litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en; end // synthesis translate_off - dummy_d_32 = dummy_s; + dummy_d_34 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_33; +reg dummy_d_35; // synthesis translate_on always @(*) begin litedramcore_inti_p3_rddata_valid <= 1'd0; @@ -3346,12 +3375,12 @@ always @(*) begin litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end // synthesis translate_off - dummy_d_33 = dummy_s; + dummy_d_35 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_34; +reg dummy_d_36; // synthesis translate_on always @(*) begin litedramcore_master_p2_wrdata_mask <= 4'd0; @@ -3361,12 +3390,12 @@ always @(*) begin litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask; end // synthesis translate_off - dummy_d_34 = dummy_s; + dummy_d_36 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_35; +reg dummy_d_37; // synthesis translate_on always @(*) begin litedramcore_master_p2_rddata_en <= 1'd0; @@ -3376,12 +3405,12 @@ always @(*) begin litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en; end // synthesis translate_off - dummy_d_35 = dummy_s; + dummy_d_37 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_36; +reg dummy_d_38; // synthesis translate_on always @(*) begin litedramcore_master_p3_address <= 14'd0; @@ -3391,12 +3420,12 @@ always @(*) begin litedramcore_master_p3_address <= litedramcore_inti_p3_address; end // synthesis translate_off - dummy_d_36 = dummy_s; + dummy_d_38 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_37; +reg dummy_d_39; // synthesis translate_on always @(*) begin litedramcore_master_p3_bank <= 3'd0; @@ -3406,12 +3435,12 @@ always @(*) begin litedramcore_master_p3_bank <= litedramcore_inti_p3_bank; end // synthesis translate_off - dummy_d_37 = dummy_s; + dummy_d_39 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_38; +reg dummy_d_40; // synthesis translate_on always @(*) begin litedramcore_master_p3_cas_n <= 1'd1; @@ -3421,12 +3450,12 @@ always @(*) begin litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n; end // synthesis translate_off - dummy_d_38 = dummy_s; + dummy_d_40 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_39; +reg dummy_d_41; // synthesis translate_on always @(*) begin litedramcore_master_p3_cs_n <= 1'd1; @@ -3436,12 +3465,12 @@ always @(*) begin litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n; end // synthesis translate_off - dummy_d_39 = dummy_s; + dummy_d_41 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_40; +reg dummy_d_42; // synthesis translate_on always @(*) begin litedramcore_master_p3_ras_n <= 1'd1; @@ -3451,12 +3480,12 @@ always @(*) begin litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n; end // synthesis translate_off - dummy_d_40 = dummy_s; + dummy_d_42 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_41; +reg dummy_d_43; // synthesis translate_on always @(*) begin litedramcore_slave_p3_rddata <= 32'd0; @@ -3465,12 +3494,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_41 = dummy_s; + dummy_d_43 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_42; +reg dummy_d_44; // synthesis translate_on always @(*) begin litedramcore_master_p3_we_n <= 1'd1; @@ -3480,12 +3509,12 @@ always @(*) begin litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n; end // synthesis translate_off - dummy_d_42 = dummy_s; + dummy_d_44 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_43; +reg dummy_d_45; // synthesis translate_on always @(*) begin litedramcore_slave_p3_rddata_valid <= 1'd0; @@ -3494,12 +3523,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_43 = dummy_s; + dummy_d_45 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_44; +reg dummy_d_46; // synthesis translate_on always @(*) begin litedramcore_master_p3_cke <= 1'd0; @@ -3509,12 +3538,12 @@ always @(*) begin litedramcore_master_p3_cke <= litedramcore_inti_p3_cke; end // synthesis translate_off - dummy_d_44 = dummy_s; + dummy_d_46 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_45; +reg dummy_d_47; // synthesis translate_on always @(*) begin litedramcore_master_p3_odt <= 1'd0; @@ -3524,12 +3553,12 @@ always @(*) begin litedramcore_master_p3_odt <= litedramcore_inti_p3_odt; end // synthesis translate_off - dummy_d_45 = dummy_s; + dummy_d_47 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_46; +reg dummy_d_48; // synthesis translate_on always @(*) begin litedramcore_master_p3_reset_n <= 1'd0; @@ -3539,12 +3568,12 @@ always @(*) begin litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n; end // synthesis translate_off - dummy_d_46 = dummy_s; + dummy_d_48 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_47; +reg dummy_d_49; // synthesis translate_on always @(*) begin litedramcore_master_p3_act_n <= 1'd1; @@ -3554,12 +3583,12 @@ always @(*) begin litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n; end // synthesis translate_off - dummy_d_47 = dummy_s; + dummy_d_49 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_48; +reg dummy_d_50; // synthesis translate_on always @(*) begin litedramcore_master_p3_wrdata <= 32'd0; @@ -3569,12 +3598,12 @@ always @(*) begin litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata; end // synthesis translate_off - dummy_d_48 = dummy_s; + dummy_d_50 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_49; +reg dummy_d_51; // synthesis translate_on always @(*) begin litedramcore_inti_p0_rddata <= 32'd0; @@ -3583,12 +3612,12 @@ always @(*) begin litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata; end // synthesis translate_off - dummy_d_49 = dummy_s; + dummy_d_51 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_50; +reg dummy_d_52; // synthesis translate_on always @(*) begin litedramcore_master_p3_wrdata_en <= 1'd0; @@ -3598,12 +3627,12 @@ always @(*) begin litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en; end // synthesis translate_off - dummy_d_50 = dummy_s; + dummy_d_52 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_51; +reg dummy_d_53; // synthesis translate_on always @(*) begin litedramcore_inti_p0_rddata_valid <= 1'd0; @@ -3612,12 +3641,12 @@ always @(*) begin litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end // synthesis translate_off - dummy_d_51 = dummy_s; + dummy_d_53 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_52; +reg dummy_d_54; // synthesis translate_on always @(*) begin litedramcore_master_p3_wrdata_mask <= 4'd0; @@ -3627,12 +3656,12 @@ always @(*) begin litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask; end // synthesis translate_off - dummy_d_52 = dummy_s; + dummy_d_54 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_53; +reg dummy_d_55; // synthesis translate_on always @(*) begin litedramcore_master_p3_rddata_en <= 1'd0; @@ -3642,12 +3671,12 @@ always @(*) begin litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en; end // synthesis translate_off - dummy_d_53 = dummy_s; + dummy_d_55 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_54; +reg dummy_d_56; // synthesis translate_on always @(*) begin litedramcore_master_p0_address <= 14'd0; @@ -3657,12 +3686,12 @@ always @(*) begin litedramcore_master_p0_address <= litedramcore_inti_p0_address; end // synthesis translate_off - dummy_d_54 = dummy_s; + dummy_d_56 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_55; +reg dummy_d_57; // synthesis translate_on always @(*) begin litedramcore_master_p0_bank <= 3'd0; @@ -3672,12 +3701,12 @@ always @(*) begin litedramcore_master_p0_bank <= litedramcore_inti_p0_bank; end // synthesis translate_off - dummy_d_55 = dummy_s; + dummy_d_57 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_56; +reg dummy_d_58; // synthesis translate_on always @(*) begin litedramcore_master_p0_cas_n <= 1'd1; @@ -3687,12 +3716,12 @@ always @(*) begin litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n; end // synthesis translate_off - dummy_d_56 = dummy_s; + dummy_d_58 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_57; +reg dummy_d_59; // synthesis translate_on always @(*) begin litedramcore_master_p0_cs_n <= 1'd1; @@ -3702,12 +3731,12 @@ always @(*) begin litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n; end // synthesis translate_off - dummy_d_57 = dummy_s; + dummy_d_59 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_58; +reg dummy_d_60; // synthesis translate_on always @(*) begin litedramcore_slave_p0_rddata <= 32'd0; @@ -3716,12 +3745,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_58 = dummy_s; + dummy_d_60 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_59; +reg dummy_d_61; // synthesis translate_on always @(*) begin litedramcore_master_p0_ras_n <= 1'd1; @@ -3731,41 +3760,41 @@ always @(*) begin litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n; end // synthesis translate_off - dummy_d_59 = dummy_s; + dummy_d_61 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_60; +reg dummy_d_62; // synthesis translate_on always @(*) begin - litedramcore_slave_p0_rddata_valid <= 1'd0; + litedramcore_master_p0_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; end else begin + litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; end // synthesis translate_off - dummy_d_60 = dummy_s; + dummy_d_62 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_61; +reg dummy_d_63; // synthesis translate_on always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; + litedramcore_slave_p0_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end else begin - litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; end // synthesis translate_off - dummy_d_61 = dummy_s; + dummy_d_63 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_62; +reg dummy_d_64; // synthesis translate_on always @(*) begin litedramcore_master_p0_cke <= 1'd0; @@ -3775,12 +3804,12 @@ always @(*) begin litedramcore_master_p0_cke <= litedramcore_inti_p0_cke; end // synthesis translate_off - dummy_d_62 = dummy_s; + dummy_d_64 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_63; +reg dummy_d_65; // synthesis translate_on always @(*) begin litedramcore_master_p0_odt <= 1'd0; @@ -3790,12 +3819,12 @@ always @(*) begin litedramcore_master_p0_odt <= litedramcore_inti_p0_odt; end // synthesis translate_off - dummy_d_63 = dummy_s; + dummy_d_65 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_64; +reg dummy_d_66; // synthesis translate_on always @(*) begin litedramcore_master_p0_reset_n <= 1'd0; @@ -3805,12 +3834,12 @@ always @(*) begin litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n; end // synthesis translate_off - dummy_d_64 = dummy_s; + dummy_d_66 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_65; +reg dummy_d_67; // synthesis translate_on always @(*) begin litedramcore_master_p0_act_n <= 1'd1; @@ -3820,12 +3849,12 @@ always @(*) begin litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n; end // synthesis translate_off - dummy_d_65 = dummy_s; + dummy_d_67 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_66; +reg dummy_d_68; // synthesis translate_on always @(*) begin litedramcore_master_p0_wrdata <= 32'd0; @@ -3835,12 +3864,12 @@ always @(*) begin litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata; end // synthesis translate_off - dummy_d_66 = dummy_s; + dummy_d_68 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_67; +reg dummy_d_69; // synthesis translate_on always @(*) begin litedramcore_inti_p1_rddata <= 32'd0; @@ -3849,12 +3878,12 @@ always @(*) begin litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata; end // synthesis translate_off - dummy_d_67 = dummy_s; + dummy_d_69 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_68; +reg dummy_d_70; // synthesis translate_on always @(*) begin litedramcore_master_p0_wrdata_en <= 1'd0; @@ -3864,12 +3893,12 @@ always @(*) begin litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en; end // synthesis translate_off - dummy_d_68 = dummy_s; + dummy_d_70 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_69; +reg dummy_d_71; // synthesis translate_on always @(*) begin litedramcore_inti_p1_rddata_valid <= 1'd0; @@ -3878,12 +3907,12 @@ always @(*) begin litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end // synthesis translate_off - dummy_d_69 = dummy_s; + dummy_d_71 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_70; +reg dummy_d_72; // synthesis translate_on always @(*) begin litedramcore_master_p0_wrdata_mask <= 4'd0; @@ -3893,12 +3922,12 @@ always @(*) begin litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask; end // synthesis translate_off - dummy_d_70 = dummy_s; + dummy_d_72 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_71; +reg dummy_d_73; // synthesis translate_on always @(*) begin litedramcore_master_p0_rddata_en <= 1'd0; @@ -3908,12 +3937,12 @@ always @(*) begin litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en; end // synthesis translate_off - dummy_d_71 = dummy_s; + dummy_d_73 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_72; +reg dummy_d_74; // synthesis translate_on always @(*) begin litedramcore_master_p1_address <= 14'd0; @@ -3923,12 +3952,12 @@ always @(*) begin litedramcore_master_p1_address <= litedramcore_inti_p1_address; end // synthesis translate_off - dummy_d_72 = dummy_s; + dummy_d_74 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_73; +reg dummy_d_75; // synthesis translate_on always @(*) begin litedramcore_master_p1_bank <= 3'd0; @@ -3938,12 +3967,12 @@ always @(*) begin litedramcore_master_p1_bank <= litedramcore_inti_p1_bank; end // synthesis translate_off - dummy_d_73 = dummy_s; + dummy_d_75 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_74; +reg dummy_d_76; // synthesis translate_on always @(*) begin litedramcore_master_p1_cas_n <= 1'd1; @@ -3953,26 +3982,12 @@ always @(*) begin litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n; end // synthesis translate_off - dummy_d_74 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_75; -// synthesis translate_on -always @(*) begin - litedramcore_slave_p2_rddata <= 32'd0; - if (litedramcore_storage[0]) begin - litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; - end else begin - end -// synthesis translate_off - dummy_d_75 = dummy_s; + dummy_d_76 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_76; +reg dummy_d_77; // synthesis translate_on always @(*) begin litedramcore_master_p1_cs_n <= 1'd1; @@ -3982,12 +3997,12 @@ always @(*) begin litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n; end // synthesis translate_off - dummy_d_76 = dummy_s; + dummy_d_77 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_77; +reg dummy_d_78; // synthesis translate_on always @(*) begin litedramcore_master_p1_ras_n <= 1'd1; @@ -3997,12 +4012,12 @@ always @(*) begin litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n; end // synthesis translate_off - dummy_d_77 = dummy_s; + dummy_d_78 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_78; +reg dummy_d_79; // synthesis translate_on always @(*) begin litedramcore_slave_p1_rddata <= 32'd0; @@ -4011,12 +4026,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_78 = dummy_s; + dummy_d_79 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_79; +reg dummy_d_80; // synthesis translate_on always @(*) begin litedramcore_master_p1_we_n <= 1'd1; @@ -4026,12 +4041,12 @@ always @(*) begin litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n; end // synthesis translate_off - dummy_d_79 = dummy_s; + dummy_d_80 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_80; +reg dummy_d_81; // synthesis translate_on always @(*) begin litedramcore_slave_p1_rddata_valid <= 1'd0; @@ -4040,12 +4055,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_80 = dummy_s; + dummy_d_81 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_81; +reg dummy_d_82; // synthesis translate_on always @(*) begin litedramcore_master_p1_cke <= 1'd0; @@ -4055,12 +4070,12 @@ always @(*) begin litedramcore_master_p1_cke <= litedramcore_inti_p1_cke; end // synthesis translate_off - dummy_d_81 = dummy_s; + dummy_d_82 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_82; +reg dummy_d_83; // synthesis translate_on always @(*) begin litedramcore_master_p1_odt <= 1'd0; @@ -4070,41 +4085,41 @@ always @(*) begin litedramcore_master_p1_odt <= litedramcore_inti_p1_odt; end // synthesis translate_off - dummy_d_82 = dummy_s; + dummy_d_83 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_83; +reg dummy_d_84; // synthesis translate_on always @(*) begin - litedramcore_slave_p2_rddata_valid <= 1'd0; + litedramcore_master_p1_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; end else begin + litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; end // synthesis translate_off - dummy_d_83 = dummy_s; + dummy_d_84 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_84; +reg dummy_d_85; // synthesis translate_on always @(*) begin - litedramcore_master_p1_reset_n <= 1'd0; + litedramcore_slave_p2_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; end else begin - litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; end // synthesis translate_off - dummy_d_84 = dummy_s; + dummy_d_85 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_85; +reg dummy_d_86; // synthesis translate_on always @(*) begin litedramcore_master_p1_act_n <= 1'd1; @@ -4114,12 +4129,12 @@ always @(*) begin litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n; end // synthesis translate_off - dummy_d_85 = dummy_s; + dummy_d_86 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_86; +reg dummy_d_87; // synthesis translate_on always @(*) begin litedramcore_master_p1_wrdata <= 32'd0; @@ -4129,12 +4144,12 @@ always @(*) begin litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata; end // synthesis translate_off - dummy_d_86 = dummy_s; + dummy_d_87 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_87; +reg dummy_d_88; // synthesis translate_on always @(*) begin litedramcore_inti_p2_rddata <= 32'd0; @@ -4143,12 +4158,12 @@ always @(*) begin litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; end // synthesis translate_off - dummy_d_87 = dummy_s; + dummy_d_88 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_88; +reg dummy_d_89; // synthesis translate_on always @(*) begin litedramcore_master_p1_wrdata_en <= 1'd0; @@ -4158,12 +4173,12 @@ always @(*) begin litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; end // synthesis translate_off - dummy_d_88 = dummy_s; + dummy_d_89 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_89; +reg dummy_d_90; // synthesis translate_on always @(*) begin litedramcore_inti_p2_rddata_valid <= 1'd0; @@ -4172,12 +4187,12 @@ always @(*) begin litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end // synthesis translate_off - dummy_d_89 = dummy_s; + dummy_d_90 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_90; +reg dummy_d_91; // synthesis translate_on always @(*) begin litedramcore_master_p1_wrdata_mask <= 4'd0; @@ -4187,12 +4202,12 @@ always @(*) begin litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; end // synthesis translate_off - dummy_d_90 = dummy_s; + dummy_d_91 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_91; +reg dummy_d_92; // synthesis translate_on always @(*) begin litedramcore_master_p1_rddata_en <= 1'd0; @@ -4202,12 +4217,12 @@ always @(*) begin litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; end // synthesis translate_off - dummy_d_91 = dummy_s; + dummy_d_92 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_92; +reg dummy_d_93; // synthesis translate_on always @(*) begin litedramcore_master_p2_address <= 14'd0; @@ -4217,12 +4232,12 @@ always @(*) begin litedramcore_master_p2_address <= litedramcore_inti_p2_address; end // synthesis translate_off - dummy_d_92 = dummy_s; + dummy_d_93 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_93; +reg dummy_d_94; // synthesis translate_on always @(*) begin litedramcore_master_p2_bank <= 3'd0; @@ -4232,12 +4247,12 @@ always @(*) begin litedramcore_master_p2_bank <= litedramcore_inti_p2_bank; end // synthesis translate_off - dummy_d_93 = dummy_s; + dummy_d_94 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_94; +reg dummy_d_95; // synthesis translate_on always @(*) begin litedramcore_master_p2_cas_n <= 1'd1; @@ -4247,12 +4262,12 @@ always @(*) begin litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n; end // synthesis translate_off - dummy_d_94 = dummy_s; + dummy_d_95 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_95; +reg dummy_d_96; // synthesis translate_on always @(*) begin litedramcore_master_p2_cs_n <= 1'd1; @@ -4262,12 +4277,12 @@ always @(*) begin litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n; end // synthesis translate_off - dummy_d_95 = dummy_s; + dummy_d_96 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_96; +reg dummy_d_97; // synthesis translate_on always @(*) begin litedramcore_master_p2_ras_n <= 1'd1; @@ -4276,21 +4291,6 @@ always @(*) begin end else begin litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n; end -// synthesis translate_off - dummy_d_96 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_97; -// synthesis translate_on -always @(*) begin - litedramcore_master_p2_we_n <= 1'd1; - if (litedramcore_storage[0]) begin - litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; - end else begin - litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; - end // synthesis translate_off dummy_d_97 = dummy_s; // synthesis translate_on @@ -4312,11 +4312,11 @@ assign litedramcore_inti_p3_reset_n = litedramcore_storage[3]; reg dummy_d_98; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_cas_n <= 1'd1; + litedramcore_inti_p0_we_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]); + litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]); end else begin - litedramcore_inti_p0_cas_n <= 1'd1; + litedramcore_inti_p0_we_n <= 1'd1; end // synthesis translate_off dummy_d_98 = dummy_s; @@ -4327,11 +4327,11 @@ end reg dummy_d_99; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_cs_n <= 1'd1; + litedramcore_inti_p0_cas_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}}; + litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]); end else begin - litedramcore_inti_p0_cs_n <= {1{1'd1}}; + litedramcore_inti_p0_cas_n <= 1'd1; end // synthesis translate_off dummy_d_99 = dummy_s; @@ -4342,11 +4342,11 @@ end reg dummy_d_100; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_ras_n <= 1'd1; + litedramcore_inti_p0_cs_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]); + litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}}; end else begin - litedramcore_inti_p0_ras_n <= 1'd1; + litedramcore_inti_p0_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_100 = dummy_s; @@ -4357,11 +4357,11 @@ end reg dummy_d_101; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_we_n <= 1'd1; + litedramcore_inti_p0_ras_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]); + litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]); end else begin - litedramcore_inti_p0_we_n <= 1'd1; + litedramcore_inti_p0_ras_n <= 1'd1; end // synthesis translate_off dummy_d_101 = dummy_s; @@ -4378,11 +4378,11 @@ assign litedramcore_inti_p0_wrdata_mask = 1'd0; reg dummy_d_102; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_cas_n <= 1'd1; + litedramcore_inti_p1_we_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]); + litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]); end else begin - litedramcore_inti_p1_cas_n <= 1'd1; + litedramcore_inti_p1_we_n <= 1'd1; end // synthesis translate_off dummy_d_102 = dummy_s; @@ -4393,11 +4393,11 @@ end reg dummy_d_103; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_cs_n <= 1'd1; + litedramcore_inti_p1_cas_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}}; + litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]); end else begin - litedramcore_inti_p1_cs_n <= {1{1'd1}}; + litedramcore_inti_p1_cas_n <= 1'd1; end // synthesis translate_off dummy_d_103 = dummy_s; @@ -4408,11 +4408,11 @@ end reg dummy_d_104; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_ras_n <= 1'd1; + litedramcore_inti_p1_cs_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]); + litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}}; end else begin - litedramcore_inti_p1_ras_n <= 1'd1; + litedramcore_inti_p1_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_104 = dummy_s; @@ -4423,11 +4423,11 @@ end reg dummy_d_105; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_we_n <= 1'd1; + litedramcore_inti_p1_ras_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]); + litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]); end else begin - litedramcore_inti_p1_we_n <= 1'd1; + litedramcore_inti_p1_ras_n <= 1'd1; end // synthesis translate_off dummy_d_105 = dummy_s; @@ -4444,11 +4444,11 @@ assign litedramcore_inti_p1_wrdata_mask = 1'd0; reg dummy_d_106; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_cas_n <= 1'd1; + litedramcore_inti_p2_we_n <= 1'd1; if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_cas_n <= (~litedramcore_phaseinjector2_command_storage[2]); + litedramcore_inti_p2_we_n <= (~litedramcore_phaseinjector2_command_storage[1]); end else begin - litedramcore_inti_p2_cas_n <= 1'd1; + litedramcore_inti_p2_we_n <= 1'd1; end // synthesis translate_off dummy_d_106 = dummy_s; @@ -4459,11 +4459,11 @@ end reg dummy_d_107; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_cs_n <= 1'd1; + litedramcore_inti_p2_cas_n <= 1'd1; if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}}; + litedramcore_inti_p2_cas_n <= (~litedramcore_phaseinjector2_command_storage[2]); end else begin - litedramcore_inti_p2_cs_n <= {1{1'd1}}; + litedramcore_inti_p2_cas_n <= 1'd1; end // synthesis translate_off dummy_d_107 = dummy_s; @@ -4474,11 +4474,11 @@ end reg dummy_d_108; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_ras_n <= 1'd1; + litedramcore_inti_p2_cs_n <= 1'd1; if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_ras_n <= (~litedramcore_phaseinjector2_command_storage[3]); + litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}}; end else begin - litedramcore_inti_p2_ras_n <= 1'd1; + litedramcore_inti_p2_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_108 = dummy_s; @@ -4489,11 +4489,11 @@ end reg dummy_d_109; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_we_n <= 1'd1; + litedramcore_inti_p2_ras_n <= 1'd1; if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_we_n <= (~litedramcore_phaseinjector2_command_storage[1]); + litedramcore_inti_p2_ras_n <= (~litedramcore_phaseinjector2_command_storage[3]); end else begin - litedramcore_inti_p2_we_n <= 1'd1; + litedramcore_inti_p2_ras_n <= 1'd1; end // synthesis translate_off dummy_d_109 = dummy_s; @@ -4510,11 +4510,11 @@ assign litedramcore_inti_p2_wrdata_mask = 1'd0; reg dummy_d_110; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_cas_n <= 1'd1; + litedramcore_inti_p3_we_n <= 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_cas_n <= (~litedramcore_phaseinjector3_command_storage[2]); + litedramcore_inti_p3_we_n <= (~litedramcore_phaseinjector3_command_storage[1]); end else begin - litedramcore_inti_p3_cas_n <= 1'd1; + litedramcore_inti_p3_we_n <= 1'd1; end // synthesis translate_off dummy_d_110 = dummy_s; @@ -4525,11 +4525,11 @@ end reg dummy_d_111; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_cs_n <= 1'd1; + litedramcore_inti_p3_cas_n <= 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}}; + litedramcore_inti_p3_cas_n <= (~litedramcore_phaseinjector3_command_storage[2]); end else begin - litedramcore_inti_p3_cs_n <= {1{1'd1}}; + litedramcore_inti_p3_cas_n <= 1'd1; end // synthesis translate_off dummy_d_111 = dummy_s; @@ -4540,11 +4540,11 @@ end reg dummy_d_112; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_ras_n <= 1'd1; + litedramcore_inti_p3_cs_n <= 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_ras_n <= (~litedramcore_phaseinjector3_command_storage[3]); + litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}}; end else begin - litedramcore_inti_p3_ras_n <= 1'd1; + litedramcore_inti_p3_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_112 = dummy_s; @@ -4555,11 +4555,11 @@ end reg dummy_d_113; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_we_n <= 1'd1; + litedramcore_inti_p3_ras_n <= 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_we_n <= (~litedramcore_phaseinjector3_command_storage[1]); + litedramcore_inti_p3_ras_n <= (~litedramcore_phaseinjector3_command_storage[3]); end else begin - litedramcore_inti_p3_we_n <= 1'd1; + litedramcore_inti_p3_ras_n <= 1'd1; end // synthesis translate_off dummy_d_113 = dummy_s; @@ -4918,38 +4918,83 @@ always @(*) begin bankmachine0_next_state <= 4'd8; end 4'd8: begin - bankmachine0_next_state <= 1'd0; + bankmachine0_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + bankmachine0_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin + bankmachine0_next_state <= 2'd2; + end + end else begin + bankmachine0_next_state <= 1'd1; + end + end else begin + bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_122 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_123; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin end default: begin if (litedramcore_bankmachine0_refresh_req) begin - bankmachine0_next_state <= 3'd4; end else begin if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin - if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin - bankmachine0_next_state <= 2'd2; + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin end end else begin - bankmachine0_next_state <= 1'd1; end end else begin - bankmachine0_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_122 = dummy_s; + dummy_d_123 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_123; +reg dummy_d_124; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + litedramcore_bankmachine0_req_wdata_ready <= 1'd0; case (bankmachine0_state) 1'd1: begin end @@ -4974,8 +5019,8 @@ always @(*) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; end else begin - litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; end end else begin end @@ -4986,24 +5031,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_123 = dummy_s; + dummy_d_124 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_124; +reg dummy_d_125; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine0_req_rdata_valid <= 1'd0; case (bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -5016,15 +5058,30 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_124 = dummy_s; + dummy_d_125 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_125; +reg dummy_d_126; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_refresh_gnt <= 1'd0; @@ -5052,12 +5109,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_125 = dummy_s; + dummy_d_126 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_126; +reg dummy_d_127; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_valid <= 1'd0; @@ -5099,39 +5156,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_126 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_127; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine0_row_open <= 1'd0; - case (bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase // synthesis translate_off dummy_d_127 = dummy_s; // synthesis translate_on @@ -5141,18 +5165,18 @@ end reg dummy_d_128; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_row_close <= 1'd0; + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; case (bankmachine0_state) 1'd1: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -5174,13 +5198,16 @@ end reg dummy_d_129; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine0_row_open <= 1'd0; case (bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_open <= 1'd1; + end end 3'd4: begin end @@ -5193,18 +5220,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -5216,21 +5231,18 @@ end reg dummy_d_130; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine0_row_close <= 1'd0; case (bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end + litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end end 3'd4: begin + litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -5252,12 +5264,9 @@ end reg dummy_d_131; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; case (bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -5279,10 +5288,7 @@ always @(*) begin if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end else begin - end + litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -5300,22 +5306,21 @@ end reg dummy_d_132; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; case (bankmachine0_state) 1'd1: begin if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5337,9 +5342,12 @@ end reg dummy_d_133; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine0_cmd_payload_we <= 1'd0; case (bankmachine0_state) 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -5362,8 +5370,8 @@ always @(*) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; end else begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; end end else begin end @@ -5382,15 +5390,22 @@ end reg dummy_d_134; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; case (bankmachine0_state) 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5401,21 +5416,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -5427,7 +5427,7 @@ end reg dummy_d_135; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; case (bankmachine0_state) 1'd1: begin end @@ -5452,8 +5452,8 @@ always @(*) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; end else begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; end end else begin end @@ -5627,7 +5627,7 @@ end reg dummy_d_140; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5652,8 +5652,8 @@ always @(*) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; end else begin - litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; end end else begin end @@ -5672,7 +5672,7 @@ end reg dummy_d_141; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd0; + litedramcore_bankmachine1_req_wdata_ready <= 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5681,9 +5681,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -5694,6 +5691,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -5705,19 +5717,13 @@ end reg dummy_d_142; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_valid <= 1'd0; + litedramcore_bankmachine1_req_rdata_valid <= 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -5735,7 +5741,10 @@ always @(*) begin if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; + end end else begin end end else begin @@ -5753,15 +5762,51 @@ end reg dummy_d_143; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_143 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_144; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine1_cmd_valid <= 1'd0; case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine1_cmd_valid <= 1'd1; end end 3'd4: begin @@ -5775,15 +5820,27 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_143 = dummy_s; + dummy_d_144 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_144; +reg dummy_d_145; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_row_open <= 1'd0; @@ -5811,12 +5868,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_144 = dummy_s; + dummy_d_145 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_145; +reg dummy_d_146; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_row_close <= 1'd0; @@ -5844,12 +5901,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_145 = dummy_s; + dummy_d_146 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_146; +reg dummy_d_147; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; @@ -5886,12 +5943,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_146 = dummy_s; + dummy_d_147 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_147; +reg dummy_d_148; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; @@ -5921,54 +5978,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_147 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_148; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd0; - case (bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase // synthesis translate_off dummy_d_148 = dummy_s; // synthesis translate_on @@ -5978,22 +5987,18 @@ end reg dummy_d_149; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6015,9 +6020,12 @@ end reg dummy_d_150; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine1_cmd_payload_we <= 1'd0; case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -6040,8 +6048,8 @@ always @(*) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end else begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6060,15 +6068,22 @@ end reg dummy_d_151; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6079,21 +6094,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -6105,7 +6105,7 @@ end reg dummy_d_152; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -6130,8 +6130,8 @@ always @(*) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; end else begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6305,7 +6305,7 @@ end reg dummy_d_157; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6330,8 +6330,8 @@ always @(*) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; end else begin - litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; end end else begin end @@ -6350,7 +6350,7 @@ end reg dummy_d_158; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd0; + litedramcore_bankmachine2_req_wdata_ready <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6359,9 +6359,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine2_twtpcon_ready) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -6372,6 +6369,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -6383,18 +6395,15 @@ end reg dummy_d_159; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_valid <= 1'd0; + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -6408,18 +6417,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -6431,16 +6428,13 @@ end reg dummy_d_160; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; + litedramcore_bankmachine2_req_rdata_valid <= 1'd0; case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; - end end 3'd4: begin end @@ -6453,6 +6447,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -6464,18 +6473,18 @@ end reg dummy_d_161; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; + litedramcore_bankmachine2_refresh_gnt <= 1'd0; case (bankmachine2_state) 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; + if (litedramcore_bankmachine2_twtpcon_ready) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6497,13 +6506,19 @@ end reg dummy_d_162; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine2_cmd_valid <= 1'd0; case (bankmachine2_state) 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -6521,7 +6536,7 @@ always @(*) begin if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + litedramcore_bankmachine2_cmd_valid <= 1'd1; end else begin end end else begin @@ -6539,7 +6554,7 @@ end reg dummy_d_163; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine2_row_open <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6547,7 +6562,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine2_row_open <= 1'd1; end end 3'd4: begin @@ -6572,21 +6587,18 @@ end reg dummy_d_164; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine2_row_close <= 1'd0; case (bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end end 3'd4: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6608,12 +6620,9 @@ end reg dummy_d_165; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; case (bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -6635,10 +6644,7 @@ always @(*) begin if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end else begin - end + litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -6656,22 +6662,21 @@ end reg dummy_d_166; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; case (bankmachine2_state) 1'd1: begin if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6693,9 +6698,12 @@ end reg dummy_d_167; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine2_cmd_payload_we <= 1'd0; case (bankmachine2_state) 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -6718,8 +6726,8 @@ always @(*) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end else begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6738,15 +6746,22 @@ end reg dummy_d_168; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; case (bankmachine2_state) 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6757,21 +6772,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -6783,7 +6783,7 @@ end reg dummy_d_169; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6808,8 +6808,8 @@ always @(*) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; end else begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6983,7 +6983,7 @@ end reg dummy_d_174; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; case (bankmachine3_state) 1'd1: begin end @@ -7008,8 +7008,8 @@ always @(*) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; end else begin - litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -7028,7 +7028,7 @@ end reg dummy_d_175; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd0; + litedramcore_bankmachine3_req_wdata_ready <= 1'd0; case (bankmachine3_state) 1'd1: begin end @@ -7037,9 +7037,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine3_twtpcon_ready) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7050,6 +7047,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -7061,19 +7073,13 @@ end reg dummy_d_176; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_valid <= 1'd0; + litedramcore_bankmachine3_req_rdata_valid <= 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -7091,7 +7097,10 @@ always @(*) begin if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; + end end else begin end end else begin @@ -7109,18 +7118,18 @@ end reg dummy_d_177; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_row_open <= 1'd0; + litedramcore_bankmachine3_refresh_gnt <= 1'd0; case (bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_open <= 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine3_twtpcon_ready) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7142,18 +7151,21 @@ end reg dummy_d_178; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_row_close <= 1'd0; + litedramcore_bankmachine3_cmd_valid <= 1'd0; case (bankmachine3_state) 1'd1: begin - litedramcore_bankmachine3_row_close <= 1'd1; + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end end 2'd2: begin - litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -7164,6 +7176,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -7175,13 +7199,16 @@ end reg dummy_d_179; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; case (bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -7194,18 +7221,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -7217,18 +7232,15 @@ end reg dummy_d_180; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine3_row_open <= 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + litedramcore_bankmachine3_row_open <= 1'd1; end end 3'd4: begin @@ -7253,18 +7265,18 @@ end reg dummy_d_181; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + litedramcore_bankmachine3_row_close <= 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end + litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -7275,21 +7287,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -7301,22 +7298,15 @@ end reg dummy_d_182; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7327,6 +7317,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -7338,13 +7340,19 @@ end reg dummy_d_183; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -7357,21 +7365,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -7383,16 +7376,16 @@ end reg dummy_d_184; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine3_cmd_payload_we <= 1'd0; case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -7405,6 +7398,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -7416,15 +7424,22 @@ end reg dummy_d_185; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7435,21 +7450,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -7461,7 +7461,7 @@ end reg dummy_d_186; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; case (bankmachine3_state) 1'd1: begin end @@ -7486,8 +7486,8 @@ always @(*) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; end else begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; end end else begin end @@ -7661,7 +7661,7 @@ end reg dummy_d_191; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; case (bankmachine4_state) 1'd1: begin end @@ -7686,8 +7686,8 @@ always @(*) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; end else begin - litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; end end else begin end @@ -7706,16 +7706,13 @@ end reg dummy_d_192; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine4_req_wdata_ready <= 1'd0; case (bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -7728,6 +7725,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -7739,19 +7751,13 @@ end reg dummy_d_193; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_valid <= 1'd0; + litedramcore_bankmachine4_req_rdata_valid <= 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -7769,7 +7775,10 @@ always @(*) begin if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; + end end else begin end end else begin @@ -7820,15 +7829,18 @@ end reg dummy_d_195; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_row_open <= 1'd0; + litedramcore_bankmachine4_cmd_valid <= 1'd0; case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_open <= 1'd1; + litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 3'd4: begin @@ -7842,6 +7854,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -7853,18 +7877,18 @@ end reg dummy_d_196; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_row_close <= 1'd0; + litedramcore_bankmachine4_row_open <= 1'd0; case (bankmachine4_state) 1'd1: begin - litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_open <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -7886,15 +7910,18 @@ end reg dummy_d_197; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine4_row_close <= 1'd0; case (bankmachine4_state) 1'd1: begin + litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -7905,18 +7932,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -7928,18 +7943,15 @@ end reg dummy_d_198; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -7964,12 +7976,9 @@ end reg dummy_d_199; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -7991,10 +8000,7 @@ always @(*) begin if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end else begin - end + litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -8012,22 +8018,21 @@ end reg dummy_d_200; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; case (bankmachine4_state) 1'd1: begin if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8049,9 +8054,12 @@ end reg dummy_d_201; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine4_cmd_payload_we <= 1'd0; case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -8074,8 +8082,8 @@ always @(*) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end else begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8094,15 +8102,22 @@ end reg dummy_d_202; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8113,21 +8128,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -8139,7 +8139,7 @@ end reg dummy_d_203; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; case (bankmachine4_state) 1'd1: begin end @@ -8164,8 +8164,8 @@ always @(*) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; end else begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8339,7 +8339,7 @@ end reg dummy_d_208; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -8364,8 +8364,8 @@ always @(*) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; end else begin - litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; end end else begin end @@ -8384,7 +8384,7 @@ end reg dummy_d_209; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd0; + litedramcore_bankmachine5_req_wdata_ready <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -8393,9 +8393,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -8406,6 +8403,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -8417,19 +8429,13 @@ end reg dummy_d_210; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_valid <= 1'd0; + litedramcore_bankmachine5_req_rdata_valid <= 1'd0; case (bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -8447,7 +8453,10 @@ always @(*) begin if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; + end end else begin end end else begin @@ -8465,18 +8474,18 @@ end reg dummy_d_211; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine5_refresh_gnt <= 1'd0; case (bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8498,15 +8507,18 @@ end reg dummy_d_212; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_row_open <= 1'd0; + litedramcore_bankmachine5_cmd_valid <= 1'd0; case (bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open <= 1'd1; + litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 3'd4: begin @@ -8520,6 +8532,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -8530,6 +8554,39 @@ end // synthesis translate_off reg dummy_d_213; // synthesis translate_on +always @(*) begin + litedramcore_bankmachine5_row_open <= 1'd0; + case (bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_213 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_214; +// synthesis translate_on always @(*) begin litedramcore_bankmachine5_row_close <= 1'd0; case (bankmachine5_state) @@ -8556,12 +8613,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_213 = dummy_s; + dummy_d_214 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_214; +reg dummy_d_215; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; @@ -8598,12 +8655,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_214 = dummy_s; + dummy_d_215 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_215; +reg dummy_d_216; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; @@ -8634,12 +8691,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_215 = dummy_s; + dummy_d_216 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_216; +reg dummy_d_217; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_we <= 1'd0; @@ -8682,12 +8739,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_216 = dummy_s; + dummy_d_217 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_217; +reg dummy_d_218; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; @@ -8718,51 +8775,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_217 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_218; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; - case (bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase // synthesis translate_off dummy_d_218 = dummy_s; // synthesis translate_on @@ -8772,13 +8784,16 @@ end reg dummy_d_219; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; case (bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -8791,21 +8806,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -8817,7 +8817,7 @@ end reg dummy_d_220; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -8842,8 +8842,8 @@ always @(*) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; end else begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9017,7 +9017,7 @@ end reg dummy_d_225; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -9042,8 +9042,8 @@ always @(*) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; end else begin - litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; end end else begin end @@ -9062,7 +9062,7 @@ end reg dummy_d_226; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd0; + litedramcore_bankmachine6_req_wdata_ready <= 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -9071,9 +9071,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine6_twtpcon_ready) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9084,6 +9081,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -9095,19 +9107,13 @@ end reg dummy_d_227; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_valid <= 1'd0; + litedramcore_bankmachine6_req_rdata_valid <= 1'd0; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -9125,7 +9131,10 @@ always @(*) begin if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; + end end else begin end end else begin @@ -9143,7 +9152,7 @@ end reg dummy_d_228; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_row_open <= 1'd0; + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -9151,7 +9160,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open <= 1'd1; + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -9176,18 +9185,18 @@ end reg dummy_d_229; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_row_close <= 1'd0; + litedramcore_bankmachine6_refresh_gnt <= 1'd0; case (bankmachine6_state) 1'd1: begin - litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine6_row_close <= 1'd1; + if (litedramcore_bankmachine6_twtpcon_ready) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9209,13 +9218,19 @@ end reg dummy_d_230; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine6_cmd_valid <= 1'd0; case (bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -9233,7 +9248,7 @@ always @(*) begin if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + litedramcore_bankmachine6_cmd_valid <= 1'd1; end else begin end end else begin @@ -9251,18 +9266,15 @@ end reg dummy_d_231; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine6_row_open <= 1'd0; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + litedramcore_bankmachine6_row_open <= 1'd1; end end 3'd4: begin @@ -9287,18 +9299,18 @@ end reg dummy_d_232; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + litedramcore_bankmachine6_row_close <= 1'd0; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end + litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -9309,21 +9321,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -9335,22 +9332,15 @@ end reg dummy_d_233; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9361,6 +9351,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -9372,15 +9374,18 @@ end reg dummy_d_234; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; case (bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -9405,9 +9410,12 @@ end reg dummy_d_235; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine6_cmd_payload_we <= 1'd0; case (bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -9430,8 +9438,8 @@ always @(*) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end else begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9450,15 +9458,22 @@ end reg dummy_d_236; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; case (bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9469,21 +9484,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -9495,7 +9495,7 @@ end reg dummy_d_237; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -9520,8 +9520,8 @@ always @(*) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; end else begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9695,16 +9695,13 @@ end reg dummy_d_242; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; case (bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -9717,6 +9714,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -9728,7 +9740,7 @@ end reg dummy_d_243; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + litedramcore_bankmachine7_req_wdata_ready <= 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -9753,8 +9765,8 @@ always @(*) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; end else begin - litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -9773,7 +9785,7 @@ end reg dummy_d_244; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd0; + litedramcore_bankmachine7_req_rdata_valid <= 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -9782,9 +9794,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine7_twtpcon_ready) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9795,6 +9804,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -9806,21 +9830,18 @@ end reg dummy_d_245; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_valid <= 1'd0; + litedramcore_bankmachine7_refresh_gnt <= 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine7_twtpcon_ready) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9831,18 +9852,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -9854,15 +9863,18 @@ end reg dummy_d_246; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_row_open <= 1'd0; + litedramcore_bankmachine7_cmd_valid <= 1'd0; case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_open <= 1'd1; + litedramcore_bankmachine7_cmd_valid <= 1'd1; end end 3'd4: begin @@ -9876,6 +9888,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -9887,18 +9911,18 @@ end reg dummy_d_247; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_row_close <= 1'd0; + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; case (bankmachine7_state) 1'd1: begin - litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9920,13 +9944,16 @@ end reg dummy_d_248; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine7_row_open <= 1'd0; case (bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_open <= 1'd1; + end end 3'd4: begin end @@ -9939,18 +9966,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -9962,21 +9977,18 @@ end reg dummy_d_249; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine7_row_close <= 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end + litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end end 3'd4: begin + litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9998,12 +10010,9 @@ end reg dummy_d_250; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -10025,10 +10034,7 @@ always @(*) begin if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end else begin - end + litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -10046,22 +10052,21 @@ end reg dummy_d_251; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; case (bankmachine7_state) 1'd1: begin if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -10083,9 +10088,12 @@ end reg dummy_d_252; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine7_cmd_payload_we <= 1'd0; case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -10108,8 +10116,8 @@ always @(*) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end else begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -10128,15 +10136,22 @@ end reg dummy_d_253; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -10147,21 +10162,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -10173,7 +10173,7 @@ end reg dummy_d_254; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -10198,8 +10198,8 @@ always @(*) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; end else begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -10581,10 +10581,10 @@ end reg dummy_d_272; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel3 <= 2'd0; + litedramcore_steerer_sel2 <= 2'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel3 <= 2'd2; + litedramcore_steerer_sel2 <= 1'd1; end 2'd2: begin end @@ -10605,7 +10605,7 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel3 <= 1'd0; + litedramcore_steerer_sel2 <= 2'd2; end endcase // synthesis translate_off @@ -10617,9 +10617,13 @@ end reg dummy_d_273; // synthesis translate_on always @(*) begin - litedramcore_en0 <= 1'd0; + litedramcore_choose_cmd_want_activates <= 1'd0; case (multiplexer_state) 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end end 2'd2: begin end @@ -10640,7 +10644,10 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_en0 <= 1'd1; + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end end endcase // synthesis translate_off @@ -10652,12 +10659,12 @@ end reg dummy_d_274; // synthesis translate_on always @(*) begin - litedramcore_cmd_ready <= 1'd0; + litedramcore_steerer_sel3 <= 2'd0; case (multiplexer_state) 1'd1: begin + litedramcore_steerer_sel3 <= 2'd2; end 2'd2: begin - litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -10676,6 +10683,7 @@ always @(*) begin 4'd10: begin end default: begin + litedramcore_steerer_sel3 <= 1'd0; end endcase // synthesis translate_off @@ -10687,13 +10695,9 @@ end reg dummy_d_275; // synthesis translate_on always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; + litedramcore_en0 <= 1'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end end 2'd2: begin end @@ -10714,10 +10718,7 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end + litedramcore_en0 <= 1'd1; end endcase // synthesis translate_off @@ -10729,11 +10730,12 @@ end reg dummy_d_276; // synthesis translate_on always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; + litedramcore_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin end 2'd2: begin + litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -10752,7 +10754,6 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_choose_req_want_reads <= 1'd1; end endcase // synthesis translate_off @@ -10764,10 +10765,13 @@ end reg dummy_d_277; // synthesis translate_on always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; + litedramcore_choose_cmd_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end end 2'd2: begin end @@ -10788,6 +10792,10 @@ always @(*) begin 4'd10: begin end default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end end endcase // synthesis translate_off @@ -10799,14 +10807,9 @@ end reg dummy_d_278; // synthesis translate_on always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; + litedramcore_choose_req_want_reads <= 1'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end end 2'd2: begin end @@ -10827,11 +10830,7 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end + litedramcore_choose_req_want_reads <= 1'd1; end endcase // synthesis translate_off @@ -10843,10 +10842,10 @@ end reg dummy_d_279; // synthesis translate_on always @(*) begin - litedramcore_en1 <= 1'd0; + litedramcore_choose_req_want_writes <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_en1 <= 1'd1; + litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -10878,13 +10877,16 @@ end reg dummy_d_280; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel0 <= 2'd0; + litedramcore_choose_req_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel0 <= 1'd0; + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end 2'd2: begin - litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -10903,7 +10905,11 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel0 <= 1'd0; + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end endcase // synthesis translate_off @@ -10915,10 +10921,10 @@ end reg dummy_d_281; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel1 <= 2'd0; + litedramcore_en1 <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel1 <= 1'd0; + litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -10939,7 +10945,6 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel1 <= 1'd1; end endcase // synthesis translate_off @@ -10951,12 +10956,13 @@ end reg dummy_d_282; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel2 <= 2'd0; + litedramcore_steerer_sel0 <= 2'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel2 <= 1'd1; + litedramcore_steerer_sel0 <= 1'd0; end 2'd2: begin + litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -10975,7 +10981,7 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel2 <= 2'd2; + litedramcore_steerer_sel0 <= 1'd0; end endcase // synthesis translate_off @@ -10987,13 +10993,10 @@ end reg dummy_d_283; // synthesis translate_on always @(*) begin - litedramcore_choose_cmd_want_activates <= 1'd0; + litedramcore_steerer_sel1 <= 2'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end + litedramcore_steerer_sel1 <= 1'd0; end 2'd2: begin end @@ -11014,10 +11017,7 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end + litedramcore_steerer_sel1 <= 1'd1; end endcase // synthesis translate_off @@ -11072,13 +11072,13 @@ assign user_port_rdata_valid = new_master_rdata_valid8; reg dummy_d_284; // synthesis translate_on always @(*) begin - litedramcore_interface_wdata_we <= 16'd0; + litedramcore_interface_wdata <= 128'd0; case ({new_master_wdata_ready2}) 1'd1: begin - litedramcore_interface_wdata_we <= user_port_wdata_payload_we; + litedramcore_interface_wdata <= user_port_wdata_payload_data; end default: begin - litedramcore_interface_wdata_we <= 1'd0; + litedramcore_interface_wdata <= 1'd0; end endcase // synthesis translate_off @@ -11090,13 +11090,13 @@ end reg dummy_d_285; // synthesis translate_on always @(*) begin - litedramcore_interface_wdata <= 128'd0; + litedramcore_interface_wdata_we <= 16'd0; case ({new_master_wdata_ready2}) 1'd1: begin - litedramcore_interface_wdata <= user_port_wdata_payload_data; + litedramcore_interface_wdata_we <= user_port_wdata_payload_we; end default: begin - litedramcore_interface_wdata <= 1'd0; + litedramcore_interface_wdata_we <= 1'd0; end endcase // synthesis translate_off @@ -11123,164 +11123,125 @@ assign litedramcore_wishbone_we = wb_bus_we; assign litedramcore_wishbone_cti = wb_bus_cti; assign litedramcore_wishbone_bte = wb_bus_bte; assign wb_bus_err = litedramcore_wishbone_err; - -// synthesis translate_off -reg dummy_d_286; -// synthesis translate_on -always @(*) begin - csrbank0_sel <= 1'd0; - csrbank0_sel <= (interface0_bank_bus_adr[13:9] == 2'd2); - if (interface0_bank_bus_adr[0]) begin - csrbank0_sel <= 1'd0; - end -// synthesis translate_off - dummy_d_286 = dummy_s; -// synthesis translate_on -end +assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 2'd2); assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd0)); -assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd0)); +assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd0)); +assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd0)); assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd1)); -assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd1)); +assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd1)); +assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd1)); assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; - -// synthesis translate_off -reg dummy_d_287; -// synthesis translate_on -always @(*) begin - csrbank1_sel <= 1'd0; - csrbank1_sel <= (interface1_bank_bus_adr[13:9] == 1'd0); - if (interface1_bank_bus_adr[0]) begin - csrbank1_sel <= 1'd0; - end -// synthesis translate_off - dummy_d_287 = dummy_s; -// synthesis translate_on -end +assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd0); assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; -assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd0)); -assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd0)); +assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 1'd0)); +assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 1'd0)); assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; -assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd1)); -assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd1)); +assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 1'd1)); +assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 1'd1)); assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd2)); -assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd2)); +assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 2'd2)); +assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 2'd2)); assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd3)); -assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd3)); +assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 2'd3)); +assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 2'd3)); assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd4)); -assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd4)); +assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd4)); +assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd4)); assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; -assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd5)); -assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd5)); +assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd5)); +assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd5)); assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd6)); -assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd6)); assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd7)); -assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd7)); assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd8)); -assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 4'd8)); assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd9)); -assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 4'd9)); assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0]; assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; - -// synthesis translate_off -reg dummy_d_288; -// synthesis translate_on -always @(*) begin - csrbank2_sel <= 1'd0; - csrbank2_sel <= (interface2_bank_bus_adr[13:9] == 1'd1); - if (interface2_bank_bus_adr[0]) begin - csrbank2_sel <= 1'd0; - end -// synthesis translate_off - dummy_d_288 = dummy_s; -// synthesis translate_on -end +assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 1'd1); assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; -assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd0)); -assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd0)); +assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 1'd0)); +assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 1'd0)); assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd1)); -assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd1)); +assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 1'd1)); +assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 1'd1)); assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd2)); -assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd2)); +assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 2'd2)); +assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 2'd2)); assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[13:0]; -assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd3)); -assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd3)); +assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 2'd3)); +assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 2'd3)); assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd4)); -assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd4)); +assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd4)); +assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd4)); assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd5)); -assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd5)); +assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd5)); +assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd5)); assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd6)); -assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd6)); +assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd6)); +assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd6)); assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd7)); -assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd7)); +assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd7)); +assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd7)); assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd8)); -assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd8)); +assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd8)); +assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd8)); assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[13:0]; -assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd9)); -assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd9)); +assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd9)); +assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd9)); assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd10)); -assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd10)); +assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd10)); +assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd10)); assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd11)); -assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd11)); +assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd11)); +assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd11)); assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd12)); -assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd12)); +assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd12)); +assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd12)); assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd13)); -assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd13)); +assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd13)); +assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd13)); assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd14)); -assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd14)); +assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd14)); +assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd14)); assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[13:0]; -assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd15)); -assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd15)); +assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd15)); +assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd15)); assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd16)); -assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd16)); +assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd16)); +assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd16)); assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd17)); -assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd17)); +assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd17)); +assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd17)); assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd18)); -assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd18)); +assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd18)); +assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd18)); assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd19)); -assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd19)); +assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd19)); +assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd19)); assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd20)); -assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd20)); +assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd20)); +assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd20)); assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[13:0]; -assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd21)); -assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd21)); +assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd21)); +assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd21)); assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd22)); -assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd22)); +assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd22)); +assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd22)); assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd23)); -assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd23)); +assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd23)); +assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd23)); assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd24)); -assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd24)); +assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd24)); +assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd24)); assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0]; @@ -11322,7 +11283,7 @@ assign interface2_bank_bus_dat_w = dat_w; assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); // synthesis translate_off -reg dummy_d_289; +reg dummy_d_286; // synthesis translate_on always @(*) begin rhs_array_muxed0 <= 1'd0; @@ -11353,12 +11314,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_289 = dummy_s; + dummy_d_286 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_290; +reg dummy_d_287; // synthesis translate_on always @(*) begin rhs_array_muxed1 <= 14'd0; @@ -11389,12 +11350,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_290 = dummy_s; + dummy_d_287 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_291; +reg dummy_d_288; // synthesis translate_on always @(*) begin rhs_array_muxed2 <= 3'd0; @@ -11425,12 +11386,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_291 = dummy_s; + dummy_d_288 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_292; +reg dummy_d_289; // synthesis translate_on always @(*) begin rhs_array_muxed3 <= 1'd0; @@ -11461,12 +11422,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_292 = dummy_s; + dummy_d_289 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_293; +reg dummy_d_290; // synthesis translate_on always @(*) begin rhs_array_muxed4 <= 1'd0; @@ -11497,12 +11458,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_293 = dummy_s; + dummy_d_290 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_294; +reg dummy_d_291; // synthesis translate_on always @(*) begin rhs_array_muxed5 <= 1'd0; @@ -11533,12 +11494,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_294 = dummy_s; + dummy_d_291 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_295; +reg dummy_d_292; // synthesis translate_on always @(*) begin t_array_muxed0 <= 1'd0; @@ -11569,12 +11530,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_295 = dummy_s; + dummy_d_292 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_296; +reg dummy_d_293; // synthesis translate_on always @(*) begin t_array_muxed1 <= 1'd0; @@ -11605,12 +11566,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_296 = dummy_s; + dummy_d_293 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_297; +reg dummy_d_294; // synthesis translate_on always @(*) begin t_array_muxed2 <= 1'd0; @@ -11641,12 +11602,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_297 = dummy_s; + dummy_d_294 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_298; +reg dummy_d_295; // synthesis translate_on always @(*) begin rhs_array_muxed6 <= 1'd0; @@ -11677,12 +11638,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_298 = dummy_s; + dummy_d_295 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_299; +reg dummy_d_296; // synthesis translate_on always @(*) begin rhs_array_muxed7 <= 14'd0; @@ -11713,12 +11674,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_299 = dummy_s; + dummy_d_296 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_300; +reg dummy_d_297; // synthesis translate_on always @(*) begin rhs_array_muxed8 <= 3'd0; @@ -11749,12 +11710,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_300 = dummy_s; + dummy_d_297 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_301; +reg dummy_d_298; // synthesis translate_on always @(*) begin rhs_array_muxed9 <= 1'd0; @@ -11785,12 +11746,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_301 = dummy_s; + dummy_d_298 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_302; +reg dummy_d_299; // synthesis translate_on always @(*) begin rhs_array_muxed10 <= 1'd0; @@ -11821,12 +11782,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_302 = dummy_s; + dummy_d_299 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_303; +reg dummy_d_300; // synthesis translate_on always @(*) begin rhs_array_muxed11 <= 1'd0; @@ -11857,12 +11818,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_303 = dummy_s; + dummy_d_300 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_304; +reg dummy_d_301; // synthesis translate_on always @(*) begin t_array_muxed3 <= 1'd0; @@ -11893,12 +11854,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_304 = dummy_s; + dummy_d_301 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_305; +reg dummy_d_302; // synthesis translate_on always @(*) begin t_array_muxed4 <= 1'd0; @@ -11929,12 +11890,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_305 = dummy_s; + dummy_d_302 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_306; +reg dummy_d_303; // synthesis translate_on always @(*) begin t_array_muxed5 <= 1'd0; @@ -11965,12 +11926,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_306 = dummy_s; + dummy_d_303 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_307; +reg dummy_d_304; // synthesis translate_on always @(*) begin rhs_array_muxed12 <= 21'd0; @@ -11980,12 +11941,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_307 = dummy_s; + dummy_d_304 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_308; +reg dummy_d_305; // synthesis translate_on always @(*) begin rhs_array_muxed13 <= 1'd0; @@ -11995,12 +11956,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_308 = dummy_s; + dummy_d_305 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_309; +reg dummy_d_306; // synthesis translate_on always @(*) begin rhs_array_muxed14 <= 1'd0; @@ -12010,12 +11971,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_309 = dummy_s; + dummy_d_306 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_310; +reg dummy_d_307; // synthesis translate_on always @(*) begin rhs_array_muxed15 <= 21'd0; @@ -12025,12 +11986,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_310 = dummy_s; + dummy_d_307 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_311; +reg dummy_d_308; // synthesis translate_on always @(*) begin rhs_array_muxed16 <= 1'd0; @@ -12040,12 +12001,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_311 = dummy_s; + dummy_d_308 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_312; +reg dummy_d_309; // synthesis translate_on always @(*) begin rhs_array_muxed17 <= 1'd0; @@ -12055,12 +12016,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_312 = dummy_s; + dummy_d_309 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_313; +reg dummy_d_310; // synthesis translate_on always @(*) begin rhs_array_muxed18 <= 21'd0; @@ -12070,12 +12031,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_313 = dummy_s; + dummy_d_310 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_314; +reg dummy_d_311; // synthesis translate_on always @(*) begin rhs_array_muxed19 <= 1'd0; @@ -12085,12 +12046,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_314 = dummy_s; + dummy_d_311 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_315; +reg dummy_d_312; // synthesis translate_on always @(*) begin rhs_array_muxed20 <= 1'd0; @@ -12100,12 +12061,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_315 = dummy_s; + dummy_d_312 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_316; +reg dummy_d_313; // synthesis translate_on always @(*) begin rhs_array_muxed21 <= 21'd0; @@ -12115,12 +12076,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_316 = dummy_s; + dummy_d_313 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_317; +reg dummy_d_314; // synthesis translate_on always @(*) begin rhs_array_muxed22 <= 1'd0; @@ -12130,12 +12091,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_317 = dummy_s; + dummy_d_314 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_318; +reg dummy_d_315; // synthesis translate_on always @(*) begin rhs_array_muxed23 <= 1'd0; @@ -12145,12 +12106,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_318 = dummy_s; + dummy_d_315 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_319; +reg dummy_d_316; // synthesis translate_on always @(*) begin rhs_array_muxed24 <= 21'd0; @@ -12160,12 +12121,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_319 = dummy_s; + dummy_d_316 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_320; +reg dummy_d_317; // synthesis translate_on always @(*) begin rhs_array_muxed25 <= 1'd0; @@ -12175,12 +12136,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_320 = dummy_s; + dummy_d_317 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_321; +reg dummy_d_318; // synthesis translate_on always @(*) begin rhs_array_muxed26 <= 1'd0; @@ -12190,12 +12151,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_321 = dummy_s; + dummy_d_318 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_322; +reg dummy_d_319; // synthesis translate_on always @(*) begin rhs_array_muxed27 <= 21'd0; @@ -12205,12 +12166,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_322 = dummy_s; + dummy_d_319 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_323; +reg dummy_d_320; // synthesis translate_on always @(*) begin rhs_array_muxed28 <= 1'd0; @@ -12220,12 +12181,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_323 = dummy_s; + dummy_d_320 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_324; +reg dummy_d_321; // synthesis translate_on always @(*) begin rhs_array_muxed29 <= 1'd0; @@ -12235,12 +12196,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_324 = dummy_s; + dummy_d_321 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_325; +reg dummy_d_322; // synthesis translate_on always @(*) begin rhs_array_muxed30 <= 21'd0; @@ -12250,12 +12211,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_325 = dummy_s; + dummy_d_322 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_326; +reg dummy_d_323; // synthesis translate_on always @(*) begin rhs_array_muxed31 <= 1'd0; @@ -12265,12 +12226,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_326 = dummy_s; + dummy_d_323 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_327; +reg dummy_d_324; // synthesis translate_on always @(*) begin rhs_array_muxed32 <= 1'd0; @@ -12280,12 +12241,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_327 = dummy_s; + dummy_d_324 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_328; +reg dummy_d_325; // synthesis translate_on always @(*) begin rhs_array_muxed33 <= 21'd0; @@ -12295,12 +12256,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_328 = dummy_s; + dummy_d_325 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_329; +reg dummy_d_326; // synthesis translate_on always @(*) begin rhs_array_muxed34 <= 1'd0; @@ -12310,12 +12271,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_329 = dummy_s; + dummy_d_326 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_330; +reg dummy_d_327; // synthesis translate_on always @(*) begin rhs_array_muxed35 <= 1'd0; @@ -12325,12 +12286,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_330 = dummy_s; + dummy_d_327 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_331; +reg dummy_d_328; // synthesis translate_on always @(*) begin array_muxed0 <= 3'd0; @@ -12349,12 +12310,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_331 = dummy_s; + dummy_d_328 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_332; +reg dummy_d_329; // synthesis translate_on always @(*) begin array_muxed1 <= 14'd0; @@ -12373,12 +12334,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_332 = dummy_s; + dummy_d_329 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_333; +reg dummy_d_330; // synthesis translate_on always @(*) begin array_muxed2 <= 1'd0; @@ -12397,12 +12358,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_333 = dummy_s; + dummy_d_330 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_334; +reg dummy_d_331; // synthesis translate_on always @(*) begin array_muxed3 <= 1'd0; @@ -12421,12 +12382,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_334 = dummy_s; + dummy_d_331 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_335; +reg dummy_d_332; // synthesis translate_on always @(*) begin array_muxed4 <= 1'd0; @@ -12445,12 +12406,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_335 = dummy_s; + dummy_d_332 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_336; +reg dummy_d_333; // synthesis translate_on always @(*) begin array_muxed5 <= 1'd0; @@ -12469,12 +12430,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_336 = dummy_s; + dummy_d_333 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_337; +reg dummy_d_334; // synthesis translate_on always @(*) begin array_muxed6 <= 1'd0; @@ -12493,12 +12454,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_337 = dummy_s; + dummy_d_334 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_338; +reg dummy_d_335; // synthesis translate_on always @(*) begin array_muxed7 <= 3'd0; @@ -12517,12 +12478,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_338 = dummy_s; + dummy_d_335 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_339; +reg dummy_d_336; // synthesis translate_on always @(*) begin array_muxed8 <= 14'd0; @@ -12541,12 +12502,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_339 = dummy_s; + dummy_d_336 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_340; +reg dummy_d_337; // synthesis translate_on always @(*) begin array_muxed9 <= 1'd0; @@ -12565,12 +12526,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_340 = dummy_s; + dummy_d_337 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_341; +reg dummy_d_338; // synthesis translate_on always @(*) begin array_muxed10 <= 1'd0; @@ -12589,12 +12550,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_341 = dummy_s; + dummy_d_338 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_342; +reg dummy_d_339; // synthesis translate_on always @(*) begin array_muxed11 <= 1'd0; @@ -12613,12 +12574,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_342 = dummy_s; + dummy_d_339 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_343; +reg dummy_d_340; // synthesis translate_on always @(*) begin array_muxed12 <= 1'd0; @@ -12637,12 +12598,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_343 = dummy_s; + dummy_d_340 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_344; +reg dummy_d_341; // synthesis translate_on always @(*) begin array_muxed13 <= 1'd0; @@ -12661,12 +12622,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_344 = dummy_s; + dummy_d_341 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_345; +reg dummy_d_342; // synthesis translate_on always @(*) begin array_muxed14 <= 3'd0; @@ -12685,12 +12646,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_345 = dummy_s; + dummy_d_342 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_346; +reg dummy_d_343; // synthesis translate_on always @(*) begin array_muxed15 <= 14'd0; @@ -12709,12 +12670,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_346 = dummy_s; + dummy_d_343 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_347; +reg dummy_d_344; // synthesis translate_on always @(*) begin array_muxed16 <= 1'd0; @@ -12733,12 +12694,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_347 = dummy_s; + dummy_d_344 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_348; +reg dummy_d_345; // synthesis translate_on always @(*) begin array_muxed17 <= 1'd0; @@ -12757,12 +12718,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_348 = dummy_s; + dummy_d_345 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_349; +reg dummy_d_346; // synthesis translate_on always @(*) begin array_muxed18 <= 1'd0; @@ -12781,12 +12742,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_349 = dummy_s; + dummy_d_346 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_350; +reg dummy_d_347; // synthesis translate_on always @(*) begin array_muxed19 <= 1'd0; @@ -12805,12 +12766,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_350 = dummy_s; + dummy_d_347 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_351; +reg dummy_d_348; // synthesis translate_on always @(*) begin array_muxed20 <= 1'd0; @@ -12829,12 +12790,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_351 = dummy_s; + dummy_d_348 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_352; +reg dummy_d_349; // synthesis translate_on always @(*) begin array_muxed21 <= 3'd0; @@ -12853,12 +12814,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_352 = dummy_s; + dummy_d_349 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_353; +reg dummy_d_350; // synthesis translate_on always @(*) begin array_muxed22 <= 14'd0; @@ -12877,12 +12838,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_353 = dummy_s; + dummy_d_350 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_354; +reg dummy_d_351; // synthesis translate_on always @(*) begin array_muxed23 <= 1'd0; @@ -12901,12 +12862,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_354 = dummy_s; + dummy_d_351 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_355; +reg dummy_d_352; // synthesis translate_on always @(*) begin array_muxed24 <= 1'd0; @@ -12925,12 +12886,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_355 = dummy_s; + dummy_d_352 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_356; +reg dummy_d_353; // synthesis translate_on always @(*) begin array_muxed25 <= 1'd0; @@ -12949,12 +12910,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_356 = dummy_s; + dummy_d_353 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_357; +reg dummy_d_354; // synthesis translate_on always @(*) begin array_muxed26 <= 1'd0; @@ -12973,12 +12934,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_357 = dummy_s; + dummy_d_354 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_358; +reg dummy_d_355; // synthesis translate_on always @(*) begin array_muxed27 <= 1'd0; @@ -12997,7 +12958,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_358 = dummy_s; + dummy_d_355 = dummy_s; // synthesis translate_on end assign xilinxasyncresetsynchronizerimpl0 = ((~sys_pll_locked) | sys_pll_reset); @@ -14447,7 +14408,7 @@ always @(posedge sys_clk) begin new_master_rdata_valid8 <= new_master_rdata_valid7; interface0_bank_bus_dat_r <= 1'd0; if (csrbank0_sel) begin - case (interface0_bank_bus_adr[1]) + case (interface0_bank_bus_adr[0]) 1'd0: begin interface0_bank_bus_dat_r <= csrbank0_init_done0_w; end @@ -14466,7 +14427,7 @@ always @(posedge sys_clk) begin init_error_re <= csrbank0_init_error0_re; interface1_bank_bus_dat_r <= 1'd0; if (csrbank1_sel) begin - case (interface1_bank_bus_adr[4:1]) + case (interface1_bank_bus_adr[3:0]) 1'd0: begin interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; end @@ -14513,7 +14474,7 @@ always @(posedge sys_clk) begin a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; interface2_bank_bus_dat_r <= 1'd0; if (csrbank2_sel) begin - case (interface2_bank_bus_adr[5:1]) + case (interface2_bank_bus_adr[4:0]) 1'd0: begin interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; end diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init index 2325bba..d20e710 100644 --- a/litedram/generated/nexys-video/litedram_core.init +++ b/litedram/generated/nexys-video/litedram_core.init @@ -510,7 +510,7 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -3842a2003c4c0001 +3842a1003c4c0001 fbc1fff07c0802a6 f8010010fbe1fff8 3be10020f821fe91 @@ -519,11 +519,11 @@ f8c101a838800140 38c101987c651b78 7fe3fb78f8e101b0 f92101c0f90101b8 -480017a5f94101c8 +48001735f94101c8 7c7e1b7860000000 -480012bd7fe3fb78 +4800124d7fe3fb78 3821017060000000 -48001d647fc3f378 +48001cf47fc3f378 0100000000000000 4e80002000000280 0000000000000000 @@ -531,76 +531,76 @@ f92101c0f90101b8 4e8000204c00012c 0000000000000000 3c4c000100000000 -7c0802a63842a15c +7c0802a63842a05c 7d800026fbe1fff8 91810008f8010010 -480011b1f821ff91 +48001141f821ff91 3c62ffff60000000 -4bffff3538637be8 +4bffff3538637c78 548400023880ffff 7c8026ea7c0004ac 3fe0c0003c62ffff -63ff000838637c08 +63ff000838637c98 3c62ffff4bffff11 -38637c287bff0020 +38637cb87bff0020 7c0004ac4bffff01 73e900017fe0feea 3c62ffff41820010 -4bfffee538637c40 +4bfffee538637cd0 4d80000073e90002 3c62ffff41820010 -4bfffecd38637c48 +4bfffecd38637cd8 4e00000073e90004 3c62ffff41820010 -4bfffeb538637c50 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f821ff7148000c8d 4bffffec38600001 0100000000000000 3c4c000100000680 -3d20c00038428f94 +3d20c00038428f04 6129200060000000 -f922801079290020 +f922800879290020 612900203d20c000 7c0004ac79290020 3d40001c7d204eea 7d295392614a2000 -394a0018e9428010 +394a0018e9428008 7c0004ac3929ffff 4e8000207d2057ea 0000000000000000 3c4c000100000000 -6000000038428f34 -39290010e9228010 +6000000038428ea4 +39290010e9228008 7d204eea7c0004ac 4082ffe871290008 -e94280105469063e +e94280085469063e 7d2057ea7c0004ac 000000004e800020 0000000000000000 -38428ef03c4c0001 +38428e603c4c0001 fbc1fff07c0802a6 3bc3fffffbe1fff8 f821ffd1f8010010 @@ -1194,7 +1180,7 @@ f924000039290002 7c6307b43863ffe0 000000004e800020 0000000000000000 -38428ca03c4c0001 +38428c103c4c0001 3d2037367c0802a6 612935347d908026 65293332792907c6 @@ -1228,7 +1214,7 @@ fbfd00007fe9fa14 4bfffff07d29f392 0300000000000000 3c4c000100000580 -7c0802a638428b94 +7c0802a638428b04 f821ffb1480006e9 7c7f1b78eb630000 7cbd2b787c9c2378 @@ -1244,7 +1230,7 @@ f821ffb1480006e9 4bffffb8f93f0000 0100000000000000 3c4c000100000580 -7c0802a638428b14 +7c0802a638428a84 f821ffa148000661 7c9b23787c7d1b78 388000007ca32b78 @@ -1275,7 +1261,7 @@ e95d00009b270000 f95d0000394a0001 000000004bffffa8 0000078001000000 -38428a183c4c0001 +384289883c4c0001 480005397c0802a6 7c741b79f821fed1 38600000f8610060 @@ -1284,7 +1270,7 @@ f95d0000394a0001 3ac4ffff3e42ffff f92100703b410020 3ae0000060000000 -3a527fc039228008 +3a527fb839228000 f92100783ba10060 ebc1006089250000 419e00102fa90000 @@ -1497,9 +1483,9 @@ e8010010ebc1fff0 203a4b4c43202020 7a484d20646c6c25 000000000000000a -6131333764343635 +3163616539333236 0000000000000000 -0033306536316430 +0039326232623162 4d4152446574694c 6620746c69756220 6567694d206d6f72 @@ -1516,35 +1502,16 @@ e8010010ebc1fff0 20676e69746f6f42 415244206d6f7266 0000000a2e2e2e4d -20747365746d656d -000a2e2e2e737562 -7830203a7375625b -7830203a5d783025 -2073762078383025 -000a783830257830 -257830207375625b -257830203a5d7830 -3020737620783830 -00000a7838302578 20747365746d654d 6c69616620737562 252f6425203a6465 73726f7272652064 000000000000000a -20747365746d656d -0a2e2e2e61746164 -0000000000000000 -783020617461645b -7830203a5d783025 -2073762078383025 -000a783830257830 -20747365746d656d -0a2e2e2e72646461 -0000000000000000 -783020726464615b -7830203a5d783025 -2073762078383025 -000a783830257830 +20747365746d654d +6961662061746164 +2f6425203a64656c +726f727265206425 +0000000000000a73 20747365746d654d 6961662072646461 2f6425203a64656c @@ -1563,10 +1530,10 @@ e8010010ebc1fff0 000000000000002d 30252d2b64323025 0000000000006432 +00000000c0100818 00000000c0100830 +00000000c0100848 00000000c0100860 -00000000c0100890 -00000000c01008c0 6f6e204d41524453 207265646e752077 6572617764726168 diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v index 687067e..c1ff475 100644 --- a/litedram/generated/nexys-video/litedram_core.v +++ b/litedram/generated/nexys-video/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-31 17:48:52 +// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-02 11:27:37 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, @@ -1607,7 +1607,7 @@ wire csrbank0_init_error0_re; wire csrbank0_init_error0_r; wire csrbank0_init_error0_we; wire csrbank0_init_error0_w; -reg csrbank0_sel = 1'd0; +wire csrbank0_sel; wire [13:0] interface1_bank_bus_adr; wire interface1_bank_bus_we; wire [31:0] interface1_bank_bus_dat_w; @@ -1624,7 +1624,7 @@ wire csrbank1_dly_sel0_re; wire [1:0] csrbank1_dly_sel0_r; wire csrbank1_dly_sel0_we; wire [1:0] csrbank1_dly_sel0_w; -reg csrbank1_sel = 1'd0; +wire csrbank1_sel; wire [13:0] interface2_bank_bus_adr; wire interface2_bank_bus_we; wire [31:0] interface2_bank_bus_dat_w; @@ -1713,7 +1713,7 @@ wire csrbank2_dfii_pi3_rddata_re; wire [31:0] csrbank2_dfii_pi3_rddata_r; wire csrbank2_dfii_pi3_rddata_we; wire [31:0] csrbank2_dfii_pi3_rddata_w; -reg csrbank2_sel = 1'd0; +wire csrbank2_sel; wire [13:0] adr; wire we; wire [31:0] dat_w; @@ -1857,13 +1857,13 @@ end reg dummy_d_1; // synthesis translate_on always @(*) begin - litedramcore_adr <= 14'd0; + litedramcore_we <= 1'd0; case (state) 1'd1: begin end default: begin if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr <= litedramcore_wishbone_adr; + litedramcore_we <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); end end endcase @@ -1876,14 +1876,12 @@ end reg dummy_d_2; // synthesis translate_on always @(*) begin - litedramcore_we <= 1'd0; + litedramcore_wishbone_ack <= 1'd0; case (state) 1'd1: begin + litedramcore_wishbone_ack <= 1'd1; end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we <= litedramcore_wishbone_we; - end end endcase // synthesis translate_off @@ -1895,12 +1893,14 @@ end reg dummy_d_3; // synthesis translate_on always @(*) begin - litedramcore_wishbone_ack <= 1'd0; + litedramcore_adr <= 14'd0; case (state) 1'd1: begin - litedramcore_wishbone_ack <= 1'd1; end default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr <= litedramcore_wishbone_adr; + end end endcase // synthesis translate_off @@ -3235,65 +3235,6 @@ assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; // synthesis translate_off reg dummy_d_26; // synthesis translate_on -always @(*) begin - litedramcore_master_p1_wrdata_en <= 1'd0; - if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; - end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; - end -// synthesis translate_off - dummy_d_26 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_27; -// synthesis translate_on -always @(*) begin - litedramcore_inti_p2_rddata_valid <= 1'd0; - if (litedramcore_storage[0]) begin - end else begin - litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; - end -// synthesis translate_off - dummy_d_27 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_28; -// synthesis translate_on -always @(*) begin - litedramcore_master_p1_wrdata_mask <= 4'd0; - if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; - end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; - end -// synthesis translate_off - dummy_d_28 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_29; -// synthesis translate_on -always @(*) begin - litedramcore_master_p1_rddata_en <= 1'd0; - if (litedramcore_storage[0]) begin - litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; - end else begin - litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; - end -// synthesis translate_off - dummy_d_29 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_30; -// synthesis translate_on always @(*) begin litedramcore_master_p2_address <= 15'd0; if (litedramcore_storage[0]) begin @@ -3302,12 +3243,12 @@ always @(*) begin litedramcore_master_p2_address <= litedramcore_inti_p2_address; end // synthesis translate_off - dummy_d_30 = dummy_s; + dummy_d_26 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_31; +reg dummy_d_27; // synthesis translate_on always @(*) begin litedramcore_master_p2_bank <= 3'd0; @@ -3317,12 +3258,12 @@ always @(*) begin litedramcore_master_p2_bank <= litedramcore_inti_p2_bank; end // synthesis translate_off - dummy_d_31 = dummy_s; + dummy_d_27 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_32; +reg dummy_d_28; // synthesis translate_on always @(*) begin litedramcore_master_p2_cas_n <= 1'd1; @@ -3332,12 +3273,12 @@ always @(*) begin litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n; end // synthesis translate_off - dummy_d_32 = dummy_s; + dummy_d_28 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_33; +reg dummy_d_29; // synthesis translate_on always @(*) begin litedramcore_master_p2_cs_n <= 1'd1; @@ -3347,12 +3288,12 @@ always @(*) begin litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n; end // synthesis translate_off - dummy_d_33 = dummy_s; + dummy_d_29 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_34; +reg dummy_d_30; // synthesis translate_on always @(*) begin litedramcore_master_p2_ras_n <= 1'd1; @@ -3362,12 +3303,12 @@ always @(*) begin litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n; end // synthesis translate_off - dummy_d_34 = dummy_s; + dummy_d_30 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_35; +reg dummy_d_31; // synthesis translate_on always @(*) begin litedramcore_slave_p2_rddata <= 32'd0; @@ -3376,12 +3317,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_35 = dummy_s; + dummy_d_31 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_36; +reg dummy_d_32; // synthesis translate_on always @(*) begin litedramcore_master_p2_we_n <= 1'd1; @@ -3391,12 +3332,12 @@ always @(*) begin litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; end // synthesis translate_off - dummy_d_36 = dummy_s; + dummy_d_32 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_37; +reg dummy_d_33; // synthesis translate_on always @(*) begin litedramcore_slave_p2_rddata_valid <= 1'd0; @@ -3405,12 +3346,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_37 = dummy_s; + dummy_d_33 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_38; +reg dummy_d_34; // synthesis translate_on always @(*) begin litedramcore_master_p2_cke <= 1'd0; @@ -3420,26 +3361,12 @@ always @(*) begin litedramcore_master_p2_cke <= litedramcore_inti_p2_cke; end // synthesis translate_off - dummy_d_38 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_39; -// synthesis translate_on -always @(*) begin - litedramcore_inti_p2_rddata <= 32'd0; - if (litedramcore_storage[0]) begin - end else begin - litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; - end -// synthesis translate_off - dummy_d_39 = dummy_s; + dummy_d_34 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_40; +reg dummy_d_35; // synthesis translate_on always @(*) begin litedramcore_master_p2_odt <= 1'd0; @@ -3449,12 +3376,12 @@ always @(*) begin litedramcore_master_p2_odt <= litedramcore_inti_p2_odt; end // synthesis translate_off - dummy_d_40 = dummy_s; + dummy_d_35 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_41; +reg dummy_d_36; // synthesis translate_on always @(*) begin litedramcore_master_p2_reset_n <= 1'd0; @@ -3464,12 +3391,12 @@ always @(*) begin litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n; end // synthesis translate_off - dummy_d_41 = dummy_s; + dummy_d_36 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_42; +reg dummy_d_37; // synthesis translate_on always @(*) begin litedramcore_master_p2_act_n <= 1'd1; @@ -3479,12 +3406,12 @@ always @(*) begin litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n; end // synthesis translate_off - dummy_d_42 = dummy_s; + dummy_d_37 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_43; +reg dummy_d_38; // synthesis translate_on always @(*) begin litedramcore_master_p2_wrdata <= 32'd0; @@ -3494,12 +3421,12 @@ always @(*) begin litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata; end // synthesis translate_off - dummy_d_43 = dummy_s; + dummy_d_38 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_44; +reg dummy_d_39; // synthesis translate_on always @(*) begin litedramcore_inti_p3_rddata <= 32'd0; @@ -3508,12 +3435,12 @@ always @(*) begin litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata; end // synthesis translate_off - dummy_d_44 = dummy_s; + dummy_d_39 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_45; +reg dummy_d_40; // synthesis translate_on always @(*) begin litedramcore_master_p2_wrdata_en <= 1'd0; @@ -3523,12 +3450,12 @@ always @(*) begin litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en; end // synthesis translate_off - dummy_d_45 = dummy_s; + dummy_d_40 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_46; +reg dummy_d_41; // synthesis translate_on always @(*) begin litedramcore_inti_p3_rddata_valid <= 1'd0; @@ -3537,12 +3464,12 @@ always @(*) begin litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end // synthesis translate_off - dummy_d_46 = dummy_s; + dummy_d_41 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_47; +reg dummy_d_42; // synthesis translate_on always @(*) begin litedramcore_master_p2_wrdata_mask <= 4'd0; @@ -3552,12 +3479,12 @@ always @(*) begin litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask; end // synthesis translate_off - dummy_d_47 = dummy_s; + dummy_d_42 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_48; +reg dummy_d_43; // synthesis translate_on always @(*) begin litedramcore_master_p2_rddata_en <= 1'd0; @@ -3567,12 +3494,12 @@ always @(*) begin litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en; end // synthesis translate_off - dummy_d_48 = dummy_s; + dummy_d_43 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_49; +reg dummy_d_44; // synthesis translate_on always @(*) begin litedramcore_master_p3_address <= 15'd0; @@ -3582,12 +3509,12 @@ always @(*) begin litedramcore_master_p3_address <= litedramcore_inti_p3_address; end // synthesis translate_off - dummy_d_49 = dummy_s; + dummy_d_44 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_50; +reg dummy_d_45; // synthesis translate_on always @(*) begin litedramcore_master_p3_bank <= 3'd0; @@ -3597,12 +3524,12 @@ always @(*) begin litedramcore_master_p3_bank <= litedramcore_inti_p3_bank; end // synthesis translate_off - dummy_d_50 = dummy_s; + dummy_d_45 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_51; +reg dummy_d_46; // synthesis translate_on always @(*) begin litedramcore_master_p3_cas_n <= 1'd1; @@ -3612,12 +3539,12 @@ always @(*) begin litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n; end // synthesis translate_off - dummy_d_51 = dummy_s; + dummy_d_46 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_52; +reg dummy_d_47; // synthesis translate_on always @(*) begin litedramcore_master_p3_cs_n <= 1'd1; @@ -3627,12 +3554,12 @@ always @(*) begin litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n; end // synthesis translate_off - dummy_d_52 = dummy_s; + dummy_d_47 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_53; +reg dummy_d_48; // synthesis translate_on always @(*) begin litedramcore_master_p3_ras_n <= 1'd1; @@ -3642,12 +3569,12 @@ always @(*) begin litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n; end // synthesis translate_off - dummy_d_53 = dummy_s; + dummy_d_48 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_54; +reg dummy_d_49; // synthesis translate_on always @(*) begin litedramcore_slave_p3_rddata <= 32'd0; @@ -3656,12 +3583,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_54 = dummy_s; + dummy_d_49 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_55; +reg dummy_d_50; // synthesis translate_on always @(*) begin litedramcore_master_p3_we_n <= 1'd1; @@ -3671,12 +3598,12 @@ always @(*) begin litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n; end // synthesis translate_off - dummy_d_55 = dummy_s; + dummy_d_50 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_56; +reg dummy_d_51; // synthesis translate_on always @(*) begin litedramcore_slave_p3_rddata_valid <= 1'd0; @@ -3685,12 +3612,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_56 = dummy_s; + dummy_d_51 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_57; +reg dummy_d_52; // synthesis translate_on always @(*) begin litedramcore_master_p3_cke <= 1'd0; @@ -3700,12 +3627,12 @@ always @(*) begin litedramcore_master_p3_cke <= litedramcore_inti_p3_cke; end // synthesis translate_off - dummy_d_57 = dummy_s; + dummy_d_52 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_58; +reg dummy_d_53; // synthesis translate_on always @(*) begin litedramcore_master_p3_odt <= 1'd0; @@ -3715,12 +3642,12 @@ always @(*) begin litedramcore_master_p3_odt <= litedramcore_inti_p3_odt; end // synthesis translate_off - dummy_d_58 = dummy_s; + dummy_d_53 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_59; +reg dummy_d_54; // synthesis translate_on always @(*) begin litedramcore_master_p3_reset_n <= 1'd0; @@ -3730,12 +3657,12 @@ always @(*) begin litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n; end // synthesis translate_off - dummy_d_59 = dummy_s; + dummy_d_54 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_60; +reg dummy_d_55; // synthesis translate_on always @(*) begin litedramcore_master_p3_act_n <= 1'd1; @@ -3745,12 +3672,12 @@ always @(*) begin litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n; end // synthesis translate_off - dummy_d_60 = dummy_s; + dummy_d_55 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_61; +reg dummy_d_56; // synthesis translate_on always @(*) begin litedramcore_master_p3_wrdata <= 32'd0; @@ -3760,12 +3687,12 @@ always @(*) begin litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata; end // synthesis translate_off - dummy_d_61 = dummy_s; + dummy_d_56 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_62; +reg dummy_d_57; // synthesis translate_on always @(*) begin litedramcore_inti_p0_rddata <= 32'd0; @@ -3774,12 +3701,12 @@ always @(*) begin litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata; end // synthesis translate_off - dummy_d_62 = dummy_s; + dummy_d_57 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_63; +reg dummy_d_58; // synthesis translate_on always @(*) begin litedramcore_master_p3_wrdata_en <= 1'd0; @@ -3789,12 +3716,12 @@ always @(*) begin litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en; end // synthesis translate_off - dummy_d_63 = dummy_s; + dummy_d_58 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_64; +reg dummy_d_59; // synthesis translate_on always @(*) begin litedramcore_inti_p0_rddata_valid <= 1'd0; @@ -3803,12 +3730,12 @@ always @(*) begin litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end // synthesis translate_off - dummy_d_64 = dummy_s; + dummy_d_59 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_65; +reg dummy_d_60; // synthesis translate_on always @(*) begin litedramcore_master_p3_wrdata_mask <= 4'd0; @@ -3818,12 +3745,12 @@ always @(*) begin litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask; end // synthesis translate_off - dummy_d_65 = dummy_s; + dummy_d_60 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_66; +reg dummy_d_61; // synthesis translate_on always @(*) begin litedramcore_master_p3_rddata_en <= 1'd0; @@ -3833,12 +3760,12 @@ always @(*) begin litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en; end // synthesis translate_off - dummy_d_66 = dummy_s; + dummy_d_61 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_67; +reg dummy_d_62; // synthesis translate_on always @(*) begin litedramcore_master_p0_address <= 15'd0; @@ -3848,12 +3775,12 @@ always @(*) begin litedramcore_master_p0_address <= litedramcore_inti_p0_address; end // synthesis translate_off - dummy_d_67 = dummy_s; + dummy_d_62 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_68; +reg dummy_d_63; // synthesis translate_on always @(*) begin litedramcore_master_p0_bank <= 3'd0; @@ -3863,12 +3790,12 @@ always @(*) begin litedramcore_master_p0_bank <= litedramcore_inti_p0_bank; end // synthesis translate_off - dummy_d_68 = dummy_s; + dummy_d_63 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_69; +reg dummy_d_64; // synthesis translate_on always @(*) begin litedramcore_master_p0_cas_n <= 1'd1; @@ -3878,12 +3805,12 @@ always @(*) begin litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n; end // synthesis translate_off - dummy_d_69 = dummy_s; + dummy_d_64 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_70; +reg dummy_d_65; // synthesis translate_on always @(*) begin litedramcore_master_p0_cs_n <= 1'd1; @@ -3893,12 +3820,12 @@ always @(*) begin litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n; end // synthesis translate_off - dummy_d_70 = dummy_s; + dummy_d_65 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_71; +reg dummy_d_66; // synthesis translate_on always @(*) begin litedramcore_master_p0_ras_n <= 1'd1; @@ -3908,12 +3835,12 @@ always @(*) begin litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n; end // synthesis translate_off - dummy_d_71 = dummy_s; + dummy_d_66 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_72; +reg dummy_d_67; // synthesis translate_on always @(*) begin litedramcore_slave_p0_rddata <= 32'd0; @@ -3922,12 +3849,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_72 = dummy_s; + dummy_d_67 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_73; +reg dummy_d_68; // synthesis translate_on always @(*) begin litedramcore_master_p0_we_n <= 1'd1; @@ -3937,12 +3864,12 @@ always @(*) begin litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; end // synthesis translate_off - dummy_d_73 = dummy_s; + dummy_d_68 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_74; +reg dummy_d_69; // synthesis translate_on always @(*) begin litedramcore_slave_p0_rddata_valid <= 1'd0; @@ -3951,12 +3878,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_74 = dummy_s; + dummy_d_69 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_75; +reg dummy_d_70; // synthesis translate_on always @(*) begin litedramcore_master_p0_cke <= 1'd0; @@ -3966,12 +3893,12 @@ always @(*) begin litedramcore_master_p0_cke <= litedramcore_inti_p0_cke; end // synthesis translate_off - dummy_d_75 = dummy_s; + dummy_d_70 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_76; +reg dummy_d_71; // synthesis translate_on always @(*) begin litedramcore_master_p0_odt <= 1'd0; @@ -3981,12 +3908,12 @@ always @(*) begin litedramcore_master_p0_odt <= litedramcore_inti_p0_odt; end // synthesis translate_off - dummy_d_76 = dummy_s; + dummy_d_71 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_77; +reg dummy_d_72; // synthesis translate_on always @(*) begin litedramcore_master_p0_reset_n <= 1'd0; @@ -3996,12 +3923,12 @@ always @(*) begin litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n; end // synthesis translate_off - dummy_d_77 = dummy_s; + dummy_d_72 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_78; +reg dummy_d_73; // synthesis translate_on always @(*) begin litedramcore_master_p0_act_n <= 1'd1; @@ -4011,12 +3938,12 @@ always @(*) begin litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n; end // synthesis translate_off - dummy_d_78 = dummy_s; + dummy_d_73 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_79; +reg dummy_d_74; // synthesis translate_on always @(*) begin litedramcore_master_p0_wrdata <= 32'd0; @@ -4026,12 +3953,12 @@ always @(*) begin litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata; end // synthesis translate_off - dummy_d_79 = dummy_s; + dummy_d_74 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_80; +reg dummy_d_75; // synthesis translate_on always @(*) begin litedramcore_inti_p1_rddata <= 32'd0; @@ -4040,12 +3967,12 @@ always @(*) begin litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata; end // synthesis translate_off - dummy_d_80 = dummy_s; + dummy_d_75 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_81; +reg dummy_d_76; // synthesis translate_on always @(*) begin litedramcore_master_p0_wrdata_en <= 1'd0; @@ -4055,12 +3982,12 @@ always @(*) begin litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en; end // synthesis translate_off - dummy_d_81 = dummy_s; + dummy_d_76 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_82; +reg dummy_d_77; // synthesis translate_on always @(*) begin litedramcore_inti_p1_rddata_valid <= 1'd0; @@ -4069,12 +3996,12 @@ always @(*) begin litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end // synthesis translate_off - dummy_d_82 = dummy_s; + dummy_d_77 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_83; +reg dummy_d_78; // synthesis translate_on always @(*) begin litedramcore_master_p0_wrdata_mask <= 4'd0; @@ -4084,12 +4011,12 @@ always @(*) begin litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask; end // synthesis translate_off - dummy_d_83 = dummy_s; + dummy_d_78 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_84; +reg dummy_d_79; // synthesis translate_on always @(*) begin litedramcore_master_p0_rddata_en <= 1'd0; @@ -4099,12 +4026,12 @@ always @(*) begin litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en; end // synthesis translate_off - dummy_d_84 = dummy_s; + dummy_d_79 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_85; +reg dummy_d_80; // synthesis translate_on always @(*) begin litedramcore_master_p1_address <= 15'd0; @@ -4114,12 +4041,12 @@ always @(*) begin litedramcore_master_p1_address <= litedramcore_inti_p1_address; end // synthesis translate_off - dummy_d_85 = dummy_s; + dummy_d_80 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_86; +reg dummy_d_81; // synthesis translate_on always @(*) begin litedramcore_master_p1_bank <= 3'd0; @@ -4129,12 +4056,12 @@ always @(*) begin litedramcore_master_p1_bank <= litedramcore_inti_p1_bank; end // synthesis translate_off - dummy_d_86 = dummy_s; + dummy_d_81 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_87; +reg dummy_d_82; // synthesis translate_on always @(*) begin litedramcore_master_p1_cas_n <= 1'd1; @@ -4144,12 +4071,12 @@ always @(*) begin litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n; end // synthesis translate_off - dummy_d_87 = dummy_s; + dummy_d_82 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_88; +reg dummy_d_83; // synthesis translate_on always @(*) begin litedramcore_master_p1_cs_n <= 1'd1; @@ -4159,12 +4086,12 @@ always @(*) begin litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n; end // synthesis translate_off - dummy_d_88 = dummy_s; + dummy_d_83 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_89; +reg dummy_d_84; // synthesis translate_on always @(*) begin litedramcore_master_p1_ras_n <= 1'd1; @@ -4174,12 +4101,12 @@ always @(*) begin litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n; end // synthesis translate_off - dummy_d_89 = dummy_s; + dummy_d_84 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_90; +reg dummy_d_85; // synthesis translate_on always @(*) begin litedramcore_slave_p1_rddata <= 32'd0; @@ -4188,12 +4115,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_90 = dummy_s; + dummy_d_85 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_91; +reg dummy_d_86; // synthesis translate_on always @(*) begin litedramcore_master_p1_we_n <= 1'd1; @@ -4203,12 +4130,12 @@ always @(*) begin litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n; end // synthesis translate_off - dummy_d_91 = dummy_s; + dummy_d_86 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_92; +reg dummy_d_87; // synthesis translate_on always @(*) begin litedramcore_slave_p1_rddata_valid <= 1'd0; @@ -4217,12 +4144,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_92 = dummy_s; + dummy_d_87 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_93; +reg dummy_d_88; // synthesis translate_on always @(*) begin litedramcore_master_p1_cke <= 1'd0; @@ -4232,12 +4159,26 @@ always @(*) begin litedramcore_master_p1_cke <= litedramcore_inti_p1_cke; end // synthesis translate_off - dummy_d_93 = dummy_s; + dummy_d_88 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_94; +reg dummy_d_89; +// synthesis translate_on +always @(*) begin + litedramcore_inti_p2_rddata <= 32'd0; + if (litedramcore_storage[0]) begin + end else begin + litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; + end +// synthesis translate_off + dummy_d_89 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_90; // synthesis translate_on always @(*) begin litedramcore_master_p1_odt <= 1'd0; @@ -4247,12 +4188,12 @@ always @(*) begin litedramcore_master_p1_odt <= litedramcore_inti_p1_odt; end // synthesis translate_off - dummy_d_94 = dummy_s; + dummy_d_90 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_95; +reg dummy_d_91; // synthesis translate_on always @(*) begin litedramcore_master_p1_reset_n <= 1'd0; @@ -4262,12 +4203,12 @@ always @(*) begin litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; end // synthesis translate_off - dummy_d_95 = dummy_s; + dummy_d_91 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_96; +reg dummy_d_92; // synthesis translate_on always @(*) begin litedramcore_master_p1_act_n <= 1'd1; @@ -4277,12 +4218,12 @@ always @(*) begin litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n; end // synthesis translate_off - dummy_d_96 = dummy_s; + dummy_d_92 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_97; +reg dummy_d_93; // synthesis translate_on always @(*) begin litedramcore_master_p1_wrdata <= 32'd0; @@ -4291,6 +4232,65 @@ always @(*) begin end else begin litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata; end +// synthesis translate_off + dummy_d_93 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_94; +// synthesis translate_on +always @(*) begin + litedramcore_master_p1_wrdata_en <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + end else begin + litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; + end +// synthesis translate_off + dummy_d_94 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_95; +// synthesis translate_on +always @(*) begin + litedramcore_inti_p2_rddata_valid <= 1'd0; + if (litedramcore_storage[0]) begin + end else begin + litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + end +// synthesis translate_off + dummy_d_95 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_96; +// synthesis translate_on +always @(*) begin + litedramcore_master_p1_wrdata_mask <= 4'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + end else begin + litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; + end +// synthesis translate_off + dummy_d_96 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_97; +// synthesis translate_on +always @(*) begin + litedramcore_master_p1_rddata_en <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; + end else begin + litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; + end // synthesis translate_off dummy_d_97 = dummy_s; // synthesis translate_on @@ -4312,11 +4312,11 @@ assign litedramcore_inti_p3_reset_n = litedramcore_storage[3]; reg dummy_d_98; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_cs_n <= 1'd1; + litedramcore_inti_p0_cas_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}}; + litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]); end else begin - litedramcore_inti_p0_cs_n <= {1{1'd1}}; + litedramcore_inti_p0_cas_n <= 1'd1; end // synthesis translate_off dummy_d_98 = dummy_s; @@ -4327,11 +4327,11 @@ end reg dummy_d_99; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_ras_n <= 1'd1; + litedramcore_inti_p0_cs_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]); + litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}}; end else begin - litedramcore_inti_p0_ras_n <= 1'd1; + litedramcore_inti_p0_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_99 = dummy_s; @@ -4342,11 +4342,11 @@ end reg dummy_d_100; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_we_n <= 1'd1; + litedramcore_inti_p0_ras_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]); + litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]); end else begin - litedramcore_inti_p0_we_n <= 1'd1; + litedramcore_inti_p0_ras_n <= 1'd1; end // synthesis translate_off dummy_d_100 = dummy_s; @@ -4357,11 +4357,11 @@ end reg dummy_d_101; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_cas_n <= 1'd1; + litedramcore_inti_p0_we_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]); + litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]); end else begin - litedramcore_inti_p0_cas_n <= 1'd1; + litedramcore_inti_p0_we_n <= 1'd1; end // synthesis translate_off dummy_d_101 = dummy_s; @@ -4378,11 +4378,11 @@ assign litedramcore_inti_p0_wrdata_mask = 1'd0; reg dummy_d_102; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_cs_n <= 1'd1; + litedramcore_inti_p1_cas_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}}; + litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]); end else begin - litedramcore_inti_p1_cs_n <= {1{1'd1}}; + litedramcore_inti_p1_cas_n <= 1'd1; end // synthesis translate_off dummy_d_102 = dummy_s; @@ -4393,11 +4393,11 @@ end reg dummy_d_103; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_ras_n <= 1'd1; + litedramcore_inti_p1_cs_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]); + litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}}; end else begin - litedramcore_inti_p1_ras_n <= 1'd1; + litedramcore_inti_p1_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_103 = dummy_s; @@ -4408,11 +4408,11 @@ end reg dummy_d_104; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_we_n <= 1'd1; + litedramcore_inti_p1_ras_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]); + litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]); end else begin - litedramcore_inti_p1_we_n <= 1'd1; + litedramcore_inti_p1_ras_n <= 1'd1; end // synthesis translate_off dummy_d_104 = dummy_s; @@ -4423,11 +4423,11 @@ end reg dummy_d_105; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_cas_n <= 1'd1; + litedramcore_inti_p1_we_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]); + litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]); end else begin - litedramcore_inti_p1_cas_n <= 1'd1; + litedramcore_inti_p1_we_n <= 1'd1; end // synthesis translate_off dummy_d_105 = dummy_s; @@ -4444,11 +4444,11 @@ assign litedramcore_inti_p1_wrdata_mask = 1'd0; reg dummy_d_106; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_cs_n <= 1'd1; + litedramcore_inti_p2_cas_n <= 1'd1; if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}}; + litedramcore_inti_p2_cas_n <= (~litedramcore_phaseinjector2_command_storage[2]); end else begin - litedramcore_inti_p2_cs_n <= {1{1'd1}}; + litedramcore_inti_p2_cas_n <= 1'd1; end // synthesis translate_off dummy_d_106 = dummy_s; @@ -4459,11 +4459,11 @@ end reg dummy_d_107; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_ras_n <= 1'd1; + litedramcore_inti_p2_cs_n <= 1'd1; if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_ras_n <= (~litedramcore_phaseinjector2_command_storage[3]); + litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}}; end else begin - litedramcore_inti_p2_ras_n <= 1'd1; + litedramcore_inti_p2_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_107 = dummy_s; @@ -4474,11 +4474,11 @@ end reg dummy_d_108; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_we_n <= 1'd1; + litedramcore_inti_p2_ras_n <= 1'd1; if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_we_n <= (~litedramcore_phaseinjector2_command_storage[1]); + litedramcore_inti_p2_ras_n <= (~litedramcore_phaseinjector2_command_storage[3]); end else begin - litedramcore_inti_p2_we_n <= 1'd1; + litedramcore_inti_p2_ras_n <= 1'd1; end // synthesis translate_off dummy_d_108 = dummy_s; @@ -4489,11 +4489,11 @@ end reg dummy_d_109; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_cas_n <= 1'd1; + litedramcore_inti_p2_we_n <= 1'd1; if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_cas_n <= (~litedramcore_phaseinjector2_command_storage[2]); + litedramcore_inti_p2_we_n <= (~litedramcore_phaseinjector2_command_storage[1]); end else begin - litedramcore_inti_p2_cas_n <= 1'd1; + litedramcore_inti_p2_we_n <= 1'd1; end // synthesis translate_off dummy_d_109 = dummy_s; @@ -4510,11 +4510,11 @@ assign litedramcore_inti_p2_wrdata_mask = 1'd0; reg dummy_d_110; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_cs_n <= 1'd1; + litedramcore_inti_p3_cas_n <= 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}}; + litedramcore_inti_p3_cas_n <= (~litedramcore_phaseinjector3_command_storage[2]); end else begin - litedramcore_inti_p3_cs_n <= {1{1'd1}}; + litedramcore_inti_p3_cas_n <= 1'd1; end // synthesis translate_off dummy_d_110 = dummy_s; @@ -4525,11 +4525,11 @@ end reg dummy_d_111; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_ras_n <= 1'd1; + litedramcore_inti_p3_cs_n <= 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_ras_n <= (~litedramcore_phaseinjector3_command_storage[3]); + litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}}; end else begin - litedramcore_inti_p3_ras_n <= 1'd1; + litedramcore_inti_p3_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_111 = dummy_s; @@ -4540,11 +4540,11 @@ end reg dummy_d_112; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_we_n <= 1'd1; + litedramcore_inti_p3_ras_n <= 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_we_n <= (~litedramcore_phaseinjector3_command_storage[1]); + litedramcore_inti_p3_ras_n <= (~litedramcore_phaseinjector3_command_storage[3]); end else begin - litedramcore_inti_p3_we_n <= 1'd1; + litedramcore_inti_p3_ras_n <= 1'd1; end // synthesis translate_off dummy_d_112 = dummy_s; @@ -4555,11 +4555,11 @@ end reg dummy_d_113; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_cas_n <= 1'd1; + litedramcore_inti_p3_we_n <= 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_cas_n <= (~litedramcore_phaseinjector3_command_storage[2]); + litedramcore_inti_p3_we_n <= (~litedramcore_phaseinjector3_command_storage[1]); end else begin - litedramcore_inti_p3_cas_n <= 1'd1; + litedramcore_inti_p3_we_n <= 1'd1; end // synthesis translate_off dummy_d_113 = dummy_s; @@ -4948,39 +4948,6 @@ end // synthesis translate_off reg dummy_d_123; // synthesis translate_on -always @(*) begin - litedramcore_bankmachine0_row_open <= 1'd0; - case (bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_123 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_124; -// synthesis translate_on always @(*) begin litedramcore_bankmachine0_row_close <= 1'd0; case (bankmachine0_state) @@ -5007,12 +4974,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_124 = dummy_s; + dummy_d_123 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_125; +reg dummy_d_124; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; @@ -5049,12 +5016,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_125 = dummy_s; + dummy_d_124 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_126; +reg dummy_d_125; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; @@ -5085,12 +5052,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_126 = dummy_s; + dummy_d_125 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_127; +reg dummy_d_126; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_we <= 1'd0; @@ -5133,12 +5100,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_127 = dummy_s; + dummy_d_126 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_128; +reg dummy_d_127; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; @@ -5166,12 +5133,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_128 = dummy_s; + dummy_d_127 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_129; +reg dummy_d_128; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; @@ -5203,12 +5170,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_129 = dummy_s; + dummy_d_128 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_130; +reg dummy_d_129; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; @@ -5248,12 +5215,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_130 = dummy_s; + dummy_d_129 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_131; +reg dummy_d_130; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; @@ -5293,12 +5260,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_131 = dummy_s; + dummy_d_130 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_132; +reg dummy_d_131; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_req_wdata_ready <= 1'd0; @@ -5338,12 +5305,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_132 = dummy_s; + dummy_d_131 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_133; +reg dummy_d_132; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_req_rdata_valid <= 1'd0; @@ -5383,12 +5350,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_133 = dummy_s; + dummy_d_132 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_134; +reg dummy_d_133; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_refresh_gnt <= 1'd0; @@ -5416,12 +5383,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_134 = dummy_s; + dummy_d_133 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_135; +reg dummy_d_134; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_valid <= 1'd0; @@ -5463,6 +5430,39 @@ always @(*) begin end end endcase +// synthesis translate_off + dummy_d_134 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_135; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine0_row_open <= 1'd0; + case (bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_135 = dummy_s; // synthesis translate_on @@ -5587,77 +5587,44 @@ always @(*) begin end end 3'd5: begin - bankmachine1_next_state <= 3'd6; - end - 3'd6: begin - bankmachine1_next_state <= 2'd3; - end - 3'd7: begin - bankmachine1_next_state <= 4'd8; - end - 4'd8: begin - bankmachine1_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - bankmachine1_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin - bankmachine1_next_state <= 2'd2; - end - end else begin - bankmachine1_next_state <= 1'd1; - end - end else begin - bankmachine1_next_state <= 2'd3; - end - end - end - end - endcase -// synthesis translate_off - dummy_d_139 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_140; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine1_row_open <= 1'd0; - case (bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin + bankmachine1_next_state <= 3'd6; end 3'd6: begin + bankmachine1_next_state <= 2'd3; end 3'd7: begin + bankmachine1_next_state <= 4'd8; end 4'd8: begin + bankmachine1_next_state <= 1'd0; end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + bankmachine1_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin + bankmachine1_next_state <= 2'd2; + end + end else begin + bankmachine1_next_state <= 1'd1; + end + end else begin + bankmachine1_next_state <= 2'd3; + end + end + end end endcase // synthesis translate_off - dummy_d_140 = dummy_s; + dummy_d_139 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_141; +reg dummy_d_140; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_row_close <= 1'd0; @@ -5685,12 +5652,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_141 = dummy_s; + dummy_d_140 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_142; +reg dummy_d_141; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; @@ -5727,12 +5694,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_142 = dummy_s; + dummy_d_141 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_143; +reg dummy_d_142; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; @@ -5763,12 +5730,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_143 = dummy_s; + dummy_d_142 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_144; +reg dummy_d_143; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_we <= 1'd0; @@ -5811,12 +5778,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_144 = dummy_s; + dummy_d_143 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_145; +reg dummy_d_144; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; @@ -5844,12 +5811,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_145 = dummy_s; + dummy_d_144 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_146; +reg dummy_d_145; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; @@ -5881,12 +5848,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_146 = dummy_s; + dummy_d_145 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_147; +reg dummy_d_146; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; @@ -5926,12 +5893,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_147 = dummy_s; + dummy_d_146 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_148; +reg dummy_d_147; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; @@ -5971,12 +5938,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_148 = dummy_s; + dummy_d_147 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_149; +reg dummy_d_148; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_req_wdata_ready <= 1'd0; @@ -6016,12 +5983,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_149 = dummy_s; + dummy_d_148 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_150; +reg dummy_d_149; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_req_rdata_valid <= 1'd0; @@ -6061,12 +6028,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_150 = dummy_s; + dummy_d_149 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_151; +reg dummy_d_150; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_refresh_gnt <= 1'd0; @@ -6094,12 +6061,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_151 = dummy_s; + dummy_d_150 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_152; +reg dummy_d_151; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_valid <= 1'd0; @@ -6141,6 +6108,39 @@ always @(*) begin end end endcase +// synthesis translate_off + dummy_d_151 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_152; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine1_row_open <= 1'd0; + case (bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_152 = dummy_s; // synthesis translate_on @@ -6304,39 +6304,6 @@ end // synthesis translate_off reg dummy_d_157; // synthesis translate_on -always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; - case (bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_157 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_158; -// synthesis translate_on always @(*) begin litedramcore_bankmachine2_row_close <= 1'd0; case (bankmachine2_state) @@ -6363,12 +6330,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_158 = dummy_s; + dummy_d_157 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_159; +reg dummy_d_158; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; @@ -6405,12 +6372,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_159 = dummy_s; + dummy_d_158 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_160; +reg dummy_d_159; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; @@ -6441,12 +6408,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_160 = dummy_s; + dummy_d_159 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_161; +reg dummy_d_160; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_we <= 1'd0; @@ -6489,12 +6456,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_161 = dummy_s; + dummy_d_160 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_162; +reg dummy_d_161; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; @@ -6522,12 +6489,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_162 = dummy_s; + dummy_d_161 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_163; +reg dummy_d_162; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; @@ -6559,12 +6526,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_163 = dummy_s; + dummy_d_162 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_164; +reg dummy_d_163; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; @@ -6604,12 +6571,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_164 = dummy_s; + dummy_d_163 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_165; +reg dummy_d_164; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; @@ -6649,12 +6616,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_165 = dummy_s; + dummy_d_164 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_166; +reg dummy_d_165; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_req_wdata_ready <= 1'd0; @@ -6694,12 +6661,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_166 = dummy_s; + dummy_d_165 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_167; +reg dummy_d_166; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_req_rdata_valid <= 1'd0; @@ -6739,12 +6706,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_167 = dummy_s; + dummy_d_166 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_168; +reg dummy_d_167; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_refresh_gnt <= 1'd0; @@ -6772,12 +6739,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_168 = dummy_s; + dummy_d_167 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_169; +reg dummy_d_168; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_valid <= 1'd0; @@ -6819,6 +6786,39 @@ always @(*) begin end end endcase +// synthesis translate_off + dummy_d_168 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_169; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine2_row_open <= 1'd0; + case (bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_169 = dummy_s; // synthesis translate_on @@ -6961,59 +6961,26 @@ always @(*) begin if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin - if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin - bankmachine3_next_state <= 2'd2; - end - end else begin - bankmachine3_next_state <= 1'd1; - end - end else begin - bankmachine3_next_state <= 2'd3; - end - end - end - end - endcase -// synthesis translate_off - dummy_d_173 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_174; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine3_row_open <= 1'd0; - case (bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin + if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin + bankmachine3_next_state <= 2'd2; + end + end else begin + bankmachine3_next_state <= 1'd1; + end + end else begin + bankmachine3_next_state <= 2'd3; + end + end + end end endcase // synthesis translate_off - dummy_d_174 = dummy_s; + dummy_d_173 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_175; +reg dummy_d_174; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_row_close <= 1'd0; @@ -7041,12 +7008,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_175 = dummy_s; + dummy_d_174 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_176; +reg dummy_d_175; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; @@ -7083,12 +7050,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_176 = dummy_s; + dummy_d_175 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_177; +reg dummy_d_176; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; @@ -7119,12 +7086,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_177 = dummy_s; + dummy_d_176 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_178; +reg dummy_d_177; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_we <= 1'd0; @@ -7167,12 +7134,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_178 = dummy_s; + dummy_d_177 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_179; +reg dummy_d_178; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; @@ -7200,12 +7167,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_179 = dummy_s; + dummy_d_178 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_180; +reg dummy_d_179; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; @@ -7237,12 +7204,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_180 = dummy_s; + dummy_d_179 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_181; +reg dummy_d_180; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; @@ -7282,12 +7249,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_181 = dummy_s; + dummy_d_180 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_182; +reg dummy_d_181; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; @@ -7327,12 +7294,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_182 = dummy_s; + dummy_d_181 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_183; +reg dummy_d_182; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_req_wdata_ready <= 1'd0; @@ -7372,12 +7339,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_183 = dummy_s; + dummy_d_182 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_184; +reg dummy_d_183; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_req_rdata_valid <= 1'd0; @@ -7417,12 +7384,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_184 = dummy_s; + dummy_d_183 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_185; +reg dummy_d_184; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_refresh_gnt <= 1'd0; @@ -7450,12 +7417,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_185 = dummy_s; + dummy_d_184 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_186; +reg dummy_d_185; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_valid <= 1'd0; @@ -7497,6 +7464,39 @@ always @(*) begin end end endcase +// synthesis translate_off + dummy_d_185 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_186; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine3_row_open <= 1'd0; + case (bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_186 = dummy_s; // synthesis translate_on @@ -7660,39 +7660,6 @@ end // synthesis translate_off reg dummy_d_191; // synthesis translate_on -always @(*) begin - litedramcore_bankmachine4_row_open <= 1'd0; - case (bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_191 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_192; -// synthesis translate_on always @(*) begin litedramcore_bankmachine4_row_close <= 1'd0; case (bankmachine4_state) @@ -7719,12 +7686,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_192 = dummy_s; + dummy_d_191 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_193; +reg dummy_d_192; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; @@ -7761,12 +7728,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_193 = dummy_s; + dummy_d_192 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_194; +reg dummy_d_193; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; @@ -7797,12 +7764,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_194 = dummy_s; + dummy_d_193 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_195; +reg dummy_d_194; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_we <= 1'd0; @@ -7845,12 +7812,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_195 = dummy_s; + dummy_d_194 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_196; +reg dummy_d_195; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; @@ -7878,12 +7845,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_196 = dummy_s; + dummy_d_195 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_197; +reg dummy_d_196; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; @@ -7915,12 +7882,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_197 = dummy_s; + dummy_d_196 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_198; +reg dummy_d_197; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; @@ -7960,12 +7927,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_198 = dummy_s; + dummy_d_197 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_199; +reg dummy_d_198; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; @@ -8005,12 +7972,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_199 = dummy_s; + dummy_d_198 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_200; +reg dummy_d_199; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_req_wdata_ready <= 1'd0; @@ -8050,12 +8017,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_200 = dummy_s; + dummy_d_199 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_201; +reg dummy_d_200; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_req_rdata_valid <= 1'd0; @@ -8095,12 +8062,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_201 = dummy_s; + dummy_d_200 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_202; +reg dummy_d_201; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_refresh_gnt <= 1'd0; @@ -8128,12 +8095,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_202 = dummy_s; + dummy_d_201 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_203; +reg dummy_d_202; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_valid <= 1'd0; @@ -8175,6 +8142,39 @@ always @(*) begin end end endcase +// synthesis translate_off + dummy_d_202 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_203; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine4_row_open <= 1'd0; + case (bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_203 = dummy_s; // synthesis translate_on @@ -8299,77 +8299,44 @@ always @(*) begin end end 3'd5: begin - bankmachine5_next_state <= 3'd6; - end - 3'd6: begin - bankmachine5_next_state <= 2'd3; - end - 3'd7: begin - bankmachine5_next_state <= 4'd8; - end - 4'd8: begin - bankmachine5_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - bankmachine5_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin - bankmachine5_next_state <= 2'd2; - end - end else begin - bankmachine5_next_state <= 1'd1; - end - end else begin - bankmachine5_next_state <= 2'd3; - end - end - end - end - endcase -// synthesis translate_off - dummy_d_207 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_208; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine5_row_open <= 1'd0; - case (bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin + bankmachine5_next_state <= 3'd6; end 3'd6: begin + bankmachine5_next_state <= 2'd3; end 3'd7: begin + bankmachine5_next_state <= 4'd8; end 4'd8: begin + bankmachine5_next_state <= 1'd0; end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + bankmachine5_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin + bankmachine5_next_state <= 2'd2; + end + end else begin + bankmachine5_next_state <= 1'd1; + end + end else begin + bankmachine5_next_state <= 2'd3; + end + end + end end endcase // synthesis translate_off - dummy_d_208 = dummy_s; + dummy_d_207 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_209; +reg dummy_d_208; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_row_close <= 1'd0; @@ -8397,12 +8364,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_209 = dummy_s; + dummy_d_208 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_210; +reg dummy_d_209; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; @@ -8439,12 +8406,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_210 = dummy_s; + dummy_d_209 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_211; +reg dummy_d_210; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; @@ -8475,12 +8442,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_211 = dummy_s; + dummy_d_210 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_212; +reg dummy_d_211; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_we <= 1'd0; @@ -8523,12 +8490,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_212 = dummy_s; + dummy_d_211 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_213; +reg dummy_d_212; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; @@ -8556,12 +8523,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_213 = dummy_s; + dummy_d_212 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_214; +reg dummy_d_213; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; @@ -8593,12 +8560,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_214 = dummy_s; + dummy_d_213 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_215; +reg dummy_d_214; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; @@ -8638,12 +8605,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_215 = dummy_s; + dummy_d_214 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_216; +reg dummy_d_215; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; @@ -8683,12 +8650,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_216 = dummy_s; + dummy_d_215 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_217; +reg dummy_d_216; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_req_wdata_ready <= 1'd0; @@ -8728,12 +8695,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_217 = dummy_s; + dummy_d_216 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_218; +reg dummy_d_217; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_req_rdata_valid <= 1'd0; @@ -8773,12 +8740,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_218 = dummy_s; + dummy_d_217 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_219; +reg dummy_d_218; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_refresh_gnt <= 1'd0; @@ -8806,12 +8773,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_219 = dummy_s; + dummy_d_218 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_220; +reg dummy_d_219; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_valid <= 1'd0; @@ -8853,6 +8820,39 @@ always @(*) begin end end endcase +// synthesis translate_off + dummy_d_219 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_220; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine5_row_open <= 1'd0; + case (bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_220 = dummy_s; // synthesis translate_on @@ -9016,39 +9016,6 @@ end // synthesis translate_off reg dummy_d_225; // synthesis translate_on -always @(*) begin - litedramcore_bankmachine6_row_open <= 1'd0; - case (bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_225 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_226; -// synthesis translate_on always @(*) begin litedramcore_bankmachine6_row_close <= 1'd0; case (bankmachine6_state) @@ -9075,12 +9042,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_226 = dummy_s; + dummy_d_225 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_227; +reg dummy_d_226; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; @@ -9117,12 +9084,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_227 = dummy_s; + dummy_d_226 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_228; +reg dummy_d_227; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; @@ -9153,12 +9120,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_228 = dummy_s; + dummy_d_227 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_229; +reg dummy_d_228; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_we <= 1'd0; @@ -9201,12 +9168,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_229 = dummy_s; + dummy_d_228 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_230; +reg dummy_d_229; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; @@ -9234,12 +9201,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_230 = dummy_s; + dummy_d_229 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_231; +reg dummy_d_230; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; @@ -9271,12 +9238,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_231 = dummy_s; + dummy_d_230 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_232; +reg dummy_d_231; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; @@ -9316,12 +9283,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_232 = dummy_s; + dummy_d_231 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_233; +reg dummy_d_232; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; @@ -9361,12 +9328,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_233 = dummy_s; + dummy_d_232 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_234; +reg dummy_d_233; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_req_wdata_ready <= 1'd0; @@ -9406,12 +9373,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_234 = dummy_s; + dummy_d_233 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_235; +reg dummy_d_234; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_req_rdata_valid <= 1'd0; @@ -9451,12 +9418,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_235 = dummy_s; + dummy_d_234 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_236; +reg dummy_d_235; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_refresh_gnt <= 1'd0; @@ -9484,12 +9451,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_236 = dummy_s; + dummy_d_235 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_237; +reg dummy_d_236; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_valid <= 1'd0; @@ -9531,6 +9498,39 @@ always @(*) begin end end endcase +// synthesis translate_off + dummy_d_236 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_237; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine6_row_open <= 1'd0; + case (bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_237 = dummy_s; // synthesis translate_on @@ -9673,59 +9673,26 @@ always @(*) begin if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin - if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin - bankmachine7_next_state <= 2'd2; - end - end else begin - bankmachine7_next_state <= 1'd1; - end - end else begin - bankmachine7_next_state <= 2'd3; - end - end - end - end - endcase -// synthesis translate_off - dummy_d_241 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_242; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine7_row_open <= 1'd0; - case (bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin + if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin + bankmachine7_next_state <= 2'd2; + end + end else begin + bankmachine7_next_state <= 1'd1; + end + end else begin + bankmachine7_next_state <= 2'd3; + end + end + end end endcase // synthesis translate_off - dummy_d_242 = dummy_s; + dummy_d_241 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_243; +reg dummy_d_242; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_row_close <= 1'd0; @@ -9753,12 +9720,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_243 = dummy_s; + dummy_d_242 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_244; +reg dummy_d_243; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; @@ -9795,12 +9762,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_244 = dummy_s; + dummy_d_243 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_245; +reg dummy_d_244; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; @@ -9831,12 +9798,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_245 = dummy_s; + dummy_d_244 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_246; +reg dummy_d_245; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_we <= 1'd0; @@ -9879,12 +9846,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_246 = dummy_s; + dummy_d_245 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_247; +reg dummy_d_246; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; @@ -9912,12 +9879,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_247 = dummy_s; + dummy_d_246 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_248; +reg dummy_d_247; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; @@ -9949,12 +9916,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_248 = dummy_s; + dummy_d_247 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_249; +reg dummy_d_248; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; @@ -9994,12 +9961,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_249 = dummy_s; + dummy_d_248 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_250; +reg dummy_d_249; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; @@ -10039,12 +10006,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_250 = dummy_s; + dummy_d_249 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_251; +reg dummy_d_250; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_req_wdata_ready <= 1'd0; @@ -10084,12 +10051,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_251 = dummy_s; + dummy_d_250 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_252; +reg dummy_d_251; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_req_rdata_valid <= 1'd0; @@ -10129,12 +10096,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_252 = dummy_s; + dummy_d_251 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_253; +reg dummy_d_252; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_refresh_gnt <= 1'd0; @@ -10162,12 +10129,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_253 = dummy_s; + dummy_d_252 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_254; +reg dummy_d_253; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_valid <= 1'd0; @@ -10209,6 +10176,39 @@ always @(*) begin end end endcase +// synthesis translate_off + dummy_d_253 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_254; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine7_row_open <= 1'd0; + case (bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_254 = dummy_s; // synthesis translate_on @@ -10581,16 +10581,13 @@ end reg dummy_d_272; // synthesis translate_on always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; + litedramcore_steerer_sel0 <= 2'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end + litedramcore_steerer_sel0 <= 1'd0; end 2'd2: begin + litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -10609,11 +10606,7 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end + litedramcore_steerer_sel0 <= 1'd0; end endcase // synthesis translate_off @@ -10625,10 +10618,10 @@ end reg dummy_d_273; // synthesis translate_on always @(*) begin - litedramcore_en1 <= 1'd0; + litedramcore_steerer_sel1 <= 2'd0; case (multiplexer_state) 1'd1: begin - litedramcore_en1 <= 1'd1; + litedramcore_steerer_sel1 <= 1'd0; end 2'd2: begin end @@ -10649,6 +10642,7 @@ always @(*) begin 4'd10: begin end default: begin + litedramcore_steerer_sel1 <= 1'd1; end endcase // synthesis translate_off @@ -10660,13 +10654,12 @@ end reg dummy_d_274; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel0 <= 2'd0; + litedramcore_steerer_sel2 <= 2'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel0 <= 1'd0; + litedramcore_steerer_sel2 <= 1'd1; end 2'd2: begin - litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -10685,7 +10678,7 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel0 <= 1'd0; + litedramcore_steerer_sel2 <= 2'd2; end endcase // synthesis translate_off @@ -10697,10 +10690,13 @@ end reg dummy_d_275; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel1 <= 2'd0; + litedramcore_choose_cmd_want_activates <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel1 <= 1'd0; + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end end 2'd2: begin end @@ -10721,7 +10717,10 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel1 <= 1'd1; + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end end endcase // synthesis translate_off @@ -10733,10 +10732,10 @@ end reg dummy_d_276; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel2 <= 2'd0; + litedramcore_steerer_sel3 <= 2'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel2 <= 1'd1; + litedramcore_steerer_sel3 <= 2'd2; end 2'd2: begin end @@ -10757,7 +10756,7 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel2 <= 2'd2; + litedramcore_steerer_sel3 <= 1'd0; end endcase // synthesis translate_off @@ -10769,13 +10768,9 @@ end reg dummy_d_277; // synthesis translate_on always @(*) begin - litedramcore_choose_cmd_want_activates <= 1'd0; + litedramcore_en0 <= 1'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end end 2'd2: begin end @@ -10796,10 +10791,7 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end + litedramcore_en0 <= 1'd1; end endcase // synthesis translate_off @@ -10811,12 +10803,12 @@ end reg dummy_d_278; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel3 <= 2'd0; + litedramcore_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel3 <= 2'd2; end 2'd2: begin + litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -10835,7 +10827,6 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel3 <= 1'd0; end endcase // synthesis translate_off @@ -10847,9 +10838,13 @@ end reg dummy_d_279; // synthesis translate_on always @(*) begin - litedramcore_en0 <= 1'd0; + litedramcore_choose_cmd_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end end 2'd2: begin end @@ -10870,7 +10865,10 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_en0 <= 1'd1; + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end end endcase // synthesis translate_off @@ -10882,12 +10880,11 @@ end reg dummy_d_280; // synthesis translate_on always @(*) begin - litedramcore_cmd_ready <= 1'd0; + litedramcore_choose_req_want_reads <= 1'd0; case (multiplexer_state) 1'd1: begin end 2'd2: begin - litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -10906,6 +10903,7 @@ always @(*) begin 4'd10: begin end default: begin + litedramcore_choose_req_want_reads <= 1'd1; end endcase // synthesis translate_off @@ -10917,13 +10915,10 @@ end reg dummy_d_281; // synthesis translate_on always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; + litedramcore_choose_req_want_writes <= 1'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end + litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -10944,10 +10939,6 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end end endcase // synthesis translate_off @@ -10959,9 +10950,10 @@ end reg dummy_d_282; // synthesis translate_on always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; + litedramcore_en1 <= 1'd0; case (multiplexer_state) 1'd1: begin + litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -10982,7 +10974,6 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_choose_req_want_reads <= 1'd1; end endcase // synthesis translate_off @@ -10994,10 +10985,14 @@ end reg dummy_d_283; // synthesis translate_on always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; + litedramcore_choose_req_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end 2'd2: begin end @@ -11018,6 +11013,11 @@ always @(*) begin 4'd10: begin end default: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end endcase // synthesis translate_off @@ -11072,13 +11072,13 @@ assign user_port_rdata_valid = new_master_rdata_valid8; reg dummy_d_284; // synthesis translate_on always @(*) begin - litedramcore_interface_wdata <= 128'd0; + litedramcore_interface_wdata_we <= 16'd0; case ({new_master_wdata_ready2}) 1'd1: begin - litedramcore_interface_wdata <= user_port_wdata_payload_data; + litedramcore_interface_wdata_we <= user_port_wdata_payload_we; end default: begin - litedramcore_interface_wdata <= 1'd0; + litedramcore_interface_wdata_we <= 1'd0; end endcase // synthesis translate_off @@ -11090,13 +11090,13 @@ end reg dummy_d_285; // synthesis translate_on always @(*) begin - litedramcore_interface_wdata_we <= 16'd0; + litedramcore_interface_wdata <= 128'd0; case ({new_master_wdata_ready2}) 1'd1: begin - litedramcore_interface_wdata_we <= user_port_wdata_payload_we; + litedramcore_interface_wdata <= user_port_wdata_payload_data; end default: begin - litedramcore_interface_wdata_we <= 1'd0; + litedramcore_interface_wdata <= 1'd0; end endcase // synthesis translate_off @@ -11123,164 +11123,125 @@ assign litedramcore_wishbone_we = wb_bus_we; assign litedramcore_wishbone_cti = wb_bus_cti; assign litedramcore_wishbone_bte = wb_bus_bte; assign wb_bus_err = litedramcore_wishbone_err; - -// synthesis translate_off -reg dummy_d_286; -// synthesis translate_on -always @(*) begin - csrbank0_sel <= 1'd0; - csrbank0_sel <= (interface0_bank_bus_adr[13:9] == 2'd2); - if (interface0_bank_bus_adr[0]) begin - csrbank0_sel <= 1'd0; - end -// synthesis translate_off - dummy_d_286 = dummy_s; -// synthesis translate_on -end +assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 2'd2); assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd0)); -assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd0)); +assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd0)); +assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd0)); assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd1)); -assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd1)); +assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd1)); +assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd1)); assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; - -// synthesis translate_off -reg dummy_d_287; -// synthesis translate_on -always @(*) begin - csrbank1_sel <= 1'd0; - csrbank1_sel <= (interface1_bank_bus_adr[13:9] == 1'd0); - if (interface1_bank_bus_adr[0]) begin - csrbank1_sel <= 1'd0; - end -// synthesis translate_off - dummy_d_287 = dummy_s; -// synthesis translate_on -end +assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd0); assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; -assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd0)); -assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd0)); +assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 1'd0)); +assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 1'd0)); assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; -assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd1)); -assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd1)); +assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 1'd1)); +assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 1'd1)); assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd2)); -assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd2)); +assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 2'd2)); +assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 2'd2)); assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd3)); -assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd3)); +assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 2'd3)); +assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 2'd3)); assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd4)); -assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd4)); +assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd4)); +assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd4)); assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; -assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd5)); -assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd5)); +assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd5)); +assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd5)); assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd6)); -assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd6)); assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd7)); -assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd7)); assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd8)); -assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 4'd8)); assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd9)); -assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 4'd9)); assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0]; assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; - -// synthesis translate_off -reg dummy_d_288; -// synthesis translate_on -always @(*) begin - csrbank2_sel <= 1'd0; - csrbank2_sel <= (interface2_bank_bus_adr[13:9] == 1'd1); - if (interface2_bank_bus_adr[0]) begin - csrbank2_sel <= 1'd0; - end -// synthesis translate_off - dummy_d_288 = dummy_s; -// synthesis translate_on -end +assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 1'd1); assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; -assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd0)); -assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd0)); +assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 1'd0)); +assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 1'd0)); assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd1)); -assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd1)); +assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 1'd1)); +assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 1'd1)); assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd2)); -assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd2)); +assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 2'd2)); +assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 2'd2)); assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0]; -assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd3)); -assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd3)); +assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 2'd3)); +assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 2'd3)); assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd4)); -assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd4)); +assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd4)); +assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd4)); assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd5)); -assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd5)); +assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd5)); +assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd5)); assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd6)); -assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd6)); +assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd6)); +assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd6)); assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd7)); -assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd7)); +assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd7)); +assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd7)); assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd8)); -assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd8)); +assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd8)); +assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd8)); assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0]; -assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd9)); -assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd9)); +assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd9)); +assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd9)); assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd10)); -assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd10)); +assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd10)); +assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd10)); assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd11)); -assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd11)); +assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd11)); +assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd11)); assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd12)); -assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd12)); +assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd12)); +assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd12)); assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd13)); -assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd13)); +assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd13)); +assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd13)); assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd14)); -assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd14)); +assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd14)); +assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd14)); assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[14:0]; -assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd15)); -assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd15)); +assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd15)); +assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd15)); assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd16)); -assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd16)); +assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd16)); +assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd16)); assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd17)); -assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd17)); +assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd17)); +assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd17)); assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd18)); -assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd18)); +assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd18)); +assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd18)); assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd19)); -assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd19)); +assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd19)); +assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd19)); assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd20)); -assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd20)); +assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd20)); +assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd20)); assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[14:0]; -assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd21)); -assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd21)); +assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd21)); +assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd21)); assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd22)); -assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd22)); +assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd22)); +assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd22)); assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd23)); -assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd23)); +assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd23)); +assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd23)); assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd24)); -assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd24)); +assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd24)); +assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd24)); assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0]; @@ -11322,7 +11283,7 @@ assign interface2_bank_bus_dat_w = dat_w; assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); // synthesis translate_off -reg dummy_d_289; +reg dummy_d_286; // synthesis translate_on always @(*) begin rhs_array_muxed0 <= 1'd0; @@ -11353,12 +11314,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_289 = dummy_s; + dummy_d_286 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_290; +reg dummy_d_287; // synthesis translate_on always @(*) begin rhs_array_muxed1 <= 15'd0; @@ -11389,12 +11350,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_290 = dummy_s; + dummy_d_287 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_291; +reg dummy_d_288; // synthesis translate_on always @(*) begin rhs_array_muxed2 <= 3'd0; @@ -11425,12 +11386,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_291 = dummy_s; + dummy_d_288 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_292; +reg dummy_d_289; // synthesis translate_on always @(*) begin rhs_array_muxed3 <= 1'd0; @@ -11461,12 +11422,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_292 = dummy_s; + dummy_d_289 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_293; +reg dummy_d_290; // synthesis translate_on always @(*) begin rhs_array_muxed4 <= 1'd0; @@ -11497,12 +11458,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_293 = dummy_s; + dummy_d_290 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_294; +reg dummy_d_291; // synthesis translate_on always @(*) begin rhs_array_muxed5 <= 1'd0; @@ -11533,12 +11494,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_294 = dummy_s; + dummy_d_291 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_295; +reg dummy_d_292; // synthesis translate_on always @(*) begin t_array_muxed0 <= 1'd0; @@ -11569,12 +11530,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_295 = dummy_s; + dummy_d_292 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_296; +reg dummy_d_293; // synthesis translate_on always @(*) begin t_array_muxed1 <= 1'd0; @@ -11605,12 +11566,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_296 = dummy_s; + dummy_d_293 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_297; +reg dummy_d_294; // synthesis translate_on always @(*) begin t_array_muxed2 <= 1'd0; @@ -11641,12 +11602,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_297 = dummy_s; + dummy_d_294 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_298; +reg dummy_d_295; // synthesis translate_on always @(*) begin rhs_array_muxed6 <= 1'd0; @@ -11677,12 +11638,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_298 = dummy_s; + dummy_d_295 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_299; +reg dummy_d_296; // synthesis translate_on always @(*) begin rhs_array_muxed7 <= 15'd0; @@ -11713,12 +11674,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_299 = dummy_s; + dummy_d_296 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_300; +reg dummy_d_297; // synthesis translate_on always @(*) begin rhs_array_muxed8 <= 3'd0; @@ -11749,12 +11710,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_300 = dummy_s; + dummy_d_297 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_301; +reg dummy_d_298; // synthesis translate_on always @(*) begin rhs_array_muxed9 <= 1'd0; @@ -11785,12 +11746,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_301 = dummy_s; + dummy_d_298 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_302; +reg dummy_d_299; // synthesis translate_on always @(*) begin rhs_array_muxed10 <= 1'd0; @@ -11821,12 +11782,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_302 = dummy_s; + dummy_d_299 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_303; +reg dummy_d_300; // synthesis translate_on always @(*) begin rhs_array_muxed11 <= 1'd0; @@ -11857,12 +11818,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_303 = dummy_s; + dummy_d_300 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_304; +reg dummy_d_301; // synthesis translate_on always @(*) begin t_array_muxed3 <= 1'd0; @@ -11893,12 +11854,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_304 = dummy_s; + dummy_d_301 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_305; +reg dummy_d_302; // synthesis translate_on always @(*) begin t_array_muxed4 <= 1'd0; @@ -11929,12 +11890,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_305 = dummy_s; + dummy_d_302 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_306; +reg dummy_d_303; // synthesis translate_on always @(*) begin t_array_muxed5 <= 1'd0; @@ -11965,12 +11926,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_306 = dummy_s; + dummy_d_303 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_307; +reg dummy_d_304; // synthesis translate_on always @(*) begin rhs_array_muxed12 <= 22'd0; @@ -11980,12 +11941,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_307 = dummy_s; + dummy_d_304 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_308; +reg dummy_d_305; // synthesis translate_on always @(*) begin rhs_array_muxed13 <= 1'd0; @@ -11995,12 +11956,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_308 = dummy_s; + dummy_d_305 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_309; +reg dummy_d_306; // synthesis translate_on always @(*) begin rhs_array_muxed14 <= 1'd0; @@ -12010,12 +11971,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_309 = dummy_s; + dummy_d_306 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_310; +reg dummy_d_307; // synthesis translate_on always @(*) begin rhs_array_muxed15 <= 22'd0; @@ -12025,12 +11986,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_310 = dummy_s; + dummy_d_307 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_311; +reg dummy_d_308; // synthesis translate_on always @(*) begin rhs_array_muxed16 <= 1'd0; @@ -12040,12 +12001,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_311 = dummy_s; + dummy_d_308 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_312; +reg dummy_d_309; // synthesis translate_on always @(*) begin rhs_array_muxed17 <= 1'd0; @@ -12055,12 +12016,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_312 = dummy_s; + dummy_d_309 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_313; +reg dummy_d_310; // synthesis translate_on always @(*) begin rhs_array_muxed18 <= 22'd0; @@ -12070,12 +12031,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_313 = dummy_s; + dummy_d_310 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_314; +reg dummy_d_311; // synthesis translate_on always @(*) begin rhs_array_muxed19 <= 1'd0; @@ -12085,12 +12046,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_314 = dummy_s; + dummy_d_311 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_315; +reg dummy_d_312; // synthesis translate_on always @(*) begin rhs_array_muxed20 <= 1'd0; @@ -12100,12 +12061,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_315 = dummy_s; + dummy_d_312 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_316; +reg dummy_d_313; // synthesis translate_on always @(*) begin rhs_array_muxed21 <= 22'd0; @@ -12115,12 +12076,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_316 = dummy_s; + dummy_d_313 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_317; +reg dummy_d_314; // synthesis translate_on always @(*) begin rhs_array_muxed22 <= 1'd0; @@ -12130,12 +12091,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_317 = dummy_s; + dummy_d_314 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_318; +reg dummy_d_315; // synthesis translate_on always @(*) begin rhs_array_muxed23 <= 1'd0; @@ -12145,12 +12106,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_318 = dummy_s; + dummy_d_315 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_319; +reg dummy_d_316; // synthesis translate_on always @(*) begin rhs_array_muxed24 <= 22'd0; @@ -12160,12 +12121,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_319 = dummy_s; + dummy_d_316 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_320; +reg dummy_d_317; // synthesis translate_on always @(*) begin rhs_array_muxed25 <= 1'd0; @@ -12175,12 +12136,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_320 = dummy_s; + dummy_d_317 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_321; +reg dummy_d_318; // synthesis translate_on always @(*) begin rhs_array_muxed26 <= 1'd0; @@ -12190,12 +12151,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_321 = dummy_s; + dummy_d_318 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_322; +reg dummy_d_319; // synthesis translate_on always @(*) begin rhs_array_muxed27 <= 22'd0; @@ -12205,12 +12166,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_322 = dummy_s; + dummy_d_319 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_323; +reg dummy_d_320; // synthesis translate_on always @(*) begin rhs_array_muxed28 <= 1'd0; @@ -12220,12 +12181,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_323 = dummy_s; + dummy_d_320 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_324; +reg dummy_d_321; // synthesis translate_on always @(*) begin rhs_array_muxed29 <= 1'd0; @@ -12235,12 +12196,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_324 = dummy_s; + dummy_d_321 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_325; +reg dummy_d_322; // synthesis translate_on always @(*) begin rhs_array_muxed30 <= 22'd0; @@ -12250,12 +12211,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_325 = dummy_s; + dummy_d_322 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_326; +reg dummy_d_323; // synthesis translate_on always @(*) begin rhs_array_muxed31 <= 1'd0; @@ -12265,12 +12226,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_326 = dummy_s; + dummy_d_323 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_327; +reg dummy_d_324; // synthesis translate_on always @(*) begin rhs_array_muxed32 <= 1'd0; @@ -12280,12 +12241,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_327 = dummy_s; + dummy_d_324 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_328; +reg dummy_d_325; // synthesis translate_on always @(*) begin rhs_array_muxed33 <= 22'd0; @@ -12295,12 +12256,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_328 = dummy_s; + dummy_d_325 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_329; +reg dummy_d_326; // synthesis translate_on always @(*) begin rhs_array_muxed34 <= 1'd0; @@ -12310,12 +12271,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_329 = dummy_s; + dummy_d_326 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_330; +reg dummy_d_327; // synthesis translate_on always @(*) begin rhs_array_muxed35 <= 1'd0; @@ -12325,12 +12286,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_330 = dummy_s; + dummy_d_327 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_331; +reg dummy_d_328; // synthesis translate_on always @(*) begin array_muxed0 <= 3'd0; @@ -12349,12 +12310,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_331 = dummy_s; + dummy_d_328 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_332; +reg dummy_d_329; // synthesis translate_on always @(*) begin array_muxed1 <= 15'd0; @@ -12373,12 +12334,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_332 = dummy_s; + dummy_d_329 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_333; +reg dummy_d_330; // synthesis translate_on always @(*) begin array_muxed2 <= 1'd0; @@ -12397,12 +12358,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_333 = dummy_s; + dummy_d_330 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_334; +reg dummy_d_331; // synthesis translate_on always @(*) begin array_muxed3 <= 1'd0; @@ -12421,12 +12382,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_334 = dummy_s; + dummy_d_331 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_335; +reg dummy_d_332; // synthesis translate_on always @(*) begin array_muxed4 <= 1'd0; @@ -12445,12 +12406,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_335 = dummy_s; + dummy_d_332 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_336; +reg dummy_d_333; // synthesis translate_on always @(*) begin array_muxed5 <= 1'd0; @@ -12469,12 +12430,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_336 = dummy_s; + dummy_d_333 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_337; +reg dummy_d_334; // synthesis translate_on always @(*) begin array_muxed6 <= 1'd0; @@ -12493,12 +12454,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_337 = dummy_s; + dummy_d_334 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_338; +reg dummy_d_335; // synthesis translate_on always @(*) begin array_muxed7 <= 3'd0; @@ -12517,12 +12478,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_338 = dummy_s; + dummy_d_335 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_339; +reg dummy_d_336; // synthesis translate_on always @(*) begin array_muxed8 <= 15'd0; @@ -12541,12 +12502,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_339 = dummy_s; + dummy_d_336 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_340; +reg dummy_d_337; // synthesis translate_on always @(*) begin array_muxed9 <= 1'd0; @@ -12565,12 +12526,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_340 = dummy_s; + dummy_d_337 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_341; +reg dummy_d_338; // synthesis translate_on always @(*) begin array_muxed10 <= 1'd0; @@ -12589,12 +12550,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_341 = dummy_s; + dummy_d_338 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_342; +reg dummy_d_339; // synthesis translate_on always @(*) begin array_muxed11 <= 1'd0; @@ -12613,12 +12574,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_342 = dummy_s; + dummy_d_339 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_343; +reg dummy_d_340; // synthesis translate_on always @(*) begin array_muxed12 <= 1'd0; @@ -12637,12 +12598,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_343 = dummy_s; + dummy_d_340 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_344; +reg dummy_d_341; // synthesis translate_on always @(*) begin array_muxed13 <= 1'd0; @@ -12661,12 +12622,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_344 = dummy_s; + dummy_d_341 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_345; +reg dummy_d_342; // synthesis translate_on always @(*) begin array_muxed14 <= 3'd0; @@ -12685,12 +12646,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_345 = dummy_s; + dummy_d_342 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_346; +reg dummy_d_343; // synthesis translate_on always @(*) begin array_muxed15 <= 15'd0; @@ -12709,12 +12670,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_346 = dummy_s; + dummy_d_343 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_347; +reg dummy_d_344; // synthesis translate_on always @(*) begin array_muxed16 <= 1'd0; @@ -12733,12 +12694,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_347 = dummy_s; + dummy_d_344 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_348; +reg dummy_d_345; // synthesis translate_on always @(*) begin array_muxed17 <= 1'd0; @@ -12757,12 +12718,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_348 = dummy_s; + dummy_d_345 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_349; +reg dummy_d_346; // synthesis translate_on always @(*) begin array_muxed18 <= 1'd0; @@ -12781,12 +12742,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_349 = dummy_s; + dummy_d_346 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_350; +reg dummy_d_347; // synthesis translate_on always @(*) begin array_muxed19 <= 1'd0; @@ -12805,12 +12766,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_350 = dummy_s; + dummy_d_347 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_351; +reg dummy_d_348; // synthesis translate_on always @(*) begin array_muxed20 <= 1'd0; @@ -12829,12 +12790,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_351 = dummy_s; + dummy_d_348 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_352; +reg dummy_d_349; // synthesis translate_on always @(*) begin array_muxed21 <= 3'd0; @@ -12853,12 +12814,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_352 = dummy_s; + dummy_d_349 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_353; +reg dummy_d_350; // synthesis translate_on always @(*) begin array_muxed22 <= 15'd0; @@ -12877,12 +12838,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_353 = dummy_s; + dummy_d_350 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_354; +reg dummy_d_351; // synthesis translate_on always @(*) begin array_muxed23 <= 1'd0; @@ -12901,12 +12862,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_354 = dummy_s; + dummy_d_351 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_355; +reg dummy_d_352; // synthesis translate_on always @(*) begin array_muxed24 <= 1'd0; @@ -12925,12 +12886,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_355 = dummy_s; + dummy_d_352 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_356; +reg dummy_d_353; // synthesis translate_on always @(*) begin array_muxed25 <= 1'd0; @@ -12949,12 +12910,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_356 = dummy_s; + dummy_d_353 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_357; +reg dummy_d_354; // synthesis translate_on always @(*) begin array_muxed26 <= 1'd0; @@ -12973,12 +12934,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_357 = dummy_s; + dummy_d_354 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_358; +reg dummy_d_355; // synthesis translate_on always @(*) begin array_muxed27 <= 1'd0; @@ -12997,7 +12958,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_358 = dummy_s; + dummy_d_355 = dummy_s; // synthesis translate_on end assign xilinxasyncresetsynchronizerimpl0 = ((~sys_pll_locked) | sys_pll_reset); @@ -14447,7 +14408,7 @@ always @(posedge sys_clk) begin new_master_rdata_valid8 <= new_master_rdata_valid7; interface0_bank_bus_dat_r <= 1'd0; if (csrbank0_sel) begin - case (interface0_bank_bus_adr[1]) + case (interface0_bank_bus_adr[0]) 1'd0: begin interface0_bank_bus_dat_r <= csrbank0_init_done0_w; end @@ -14466,7 +14427,7 @@ always @(posedge sys_clk) begin init_error_re <= csrbank0_init_error0_re; interface1_bank_bus_dat_r <= 1'd0; if (csrbank1_sel) begin - case (interface1_bank_bus_adr[4:1]) + case (interface1_bank_bus_adr[3:0]) 1'd0: begin interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; end @@ -14513,7 +14474,7 @@ always @(posedge sys_clk) begin a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; interface2_bank_bus_dat_r <= 1'd0; if (csrbank2_sel) begin - case (interface2_bank_bus_adr[5:1]) + case (interface2_bank_bus_adr[4:0]) 1'd0: begin interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; end diff --git a/litedram/generated/sim/litedram-initmem.vhdl b/litedram/generated/sim/litedram-initmem.vhdl index e9a379c..7abaf48 100644 --- a/litedram/generated/sim/litedram-initmem.vhdl +++ b/litedram/generated/sim/litedram-initmem.vhdl @@ -48,7 +48,6 @@ architecture rtl of dram_init_mem is impure function init_load_ram(name : string) return ram_t is file ram_file : text open read_mode is name; - file payload_file : text open read_mode is EXTRA_PAYLOAD_FILE; variable temp_word : std_logic_vector(63 downto 0); variable temp_ram : ram_t := (others => (others => '0')); variable ram_line : line; @@ -66,7 +65,7 @@ architecture rtl of dram_init_mem is temp_ram(i*2+1) := temp_word(63 downto 32); end loop; if RND_PAYLOAD_SIZE /= 0 then - procedure init_load_payload(ram: inout ram_t; filename: string) is + init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE); end if; return temp_ram; end function; diff --git a/litedram/generated/sim/litedram_core.init b/litedram/generated/sim/litedram_core.init index bb13c9d..5dd2a84 100644 --- a/litedram/generated/sim/litedram_core.init +++ b/litedram/generated/sim/litedram_core.init @@ -510,7 +510,7 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -384297003c4c0001 +384296003c4c0001 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+eb81ffe0eb61ffd8 +eba1ffe8e8010010 +ebc1fff07c0803a6 +4e800020ebe1fff8 +e8010010ebc1fff0 +7c0803a6ebe1fff8 +000000004e800020 6d6f636c65570a0a 63694d206f742065 2120747461776f72 @@ -1180,9 +1160,9 @@ ebe1fff8e8010010 203a4b4c43202020 7a484d20646c6c25 000000000000000a -6131333764343635 +3163616539333236 0000000000000000 -0033306536316430 +0039326232623162 4d4152446574694c 6620746c69756220 6567694d206d6f72 @@ -1199,35 +1179,16 @@ ebe1fff8e8010010 20676e69746f6f42 415244206d6f7266 0000000a2e2e2e4d -20747365746d656d -000a2e2e2e737562 -7830203a7375625b -7830203a5d783025 -2073762078383025 -000a783830257830 -257830207375625b -257830203a5d7830 -3020737620783830 -00000a7838302578 20747365746d654d 6c69616620737562 252f6425203a6465 73726f7272652064 000000000000000a -20747365746d656d -0a2e2e2e61746164 -0000000000000000 -783020617461645b -7830203a5d783025 -2073762078383025 -000a783830257830 -20747365746d656d -0a2e2e2e72646461 -0000000000000000 -783020726464615b -7830203a5d783025 -2073762078383025 -000a783830257830 +20747365746d654d +6961662061746164 +2f6425203a64656c +726f727265206425 +0000000000000a73 20747365746d654d 6961662072646461 2f6425203a64656c @@ -1249,11 +1210,6 @@ ebe1fff8e8010010 696c616974696e49 52445320676e697a 00000a2e2e2e4d41 -6f6e204d41524453 -207265646e752077 -6572617774666f73 -6c6f72746e6f6320 -000000000000000a 0000000000000000 00000000000000ff 000000000000ffff diff --git a/litedram/generated/sim/litedram_core.v b/litedram/generated/sim/litedram_core.v index e44b526..f3f21e3 100644 --- a/litedram/generated/sim/litedram_core.v +++ b/litedram/generated/sim/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-31 17:48:54 +// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-02 11:27:39 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, @@ -33,8 +33,8 @@ module litedram_core( reg [13:0] litedramcore_adr = 14'd0; reg litedramcore_we = 1'd0; -wire [31:0] litedramcore_dat_w; -wire [31:0] litedramcore_dat_r; +wire [7:0] litedramcore_dat_w; +wire [7:0] litedramcore_dat_r; wire [29:0] litedramcore_wishbone_adr; wire [31:0] litedramcore_wishbone_dat_w; wire [31:0] litedramcore_wishbone_dat_r; @@ -130,310 +130,6 @@ reg ddrphy_dfiphasemodel3_activate = 1'd0; reg ddrphy_dfiphasemodel3_precharge = 1'd0; reg ddrphy_dfiphasemodel3_write = 1'd0; reg ddrphy_dfiphasemodel3_read = 1'd0; -reg [63:0] ddrphy_dfitimingschecker_cnt = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker0 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker1 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker2 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker3 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker4 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker5 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker6 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker7 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker8 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker9 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker10 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker11 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker12 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker13 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker14 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker15 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker16 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker17 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker18 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker19 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker20 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker21 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker22 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker23 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker24 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker25 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker26 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker27 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker28 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker29 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker30 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker31 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker32 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker33 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker34 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker35 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker36 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker37 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker38 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker39 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker40 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker41 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker42 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker43 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker44 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker45 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker46 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker47 = 64'd0; -reg [3:0] ddrphy_dfitimingschecker_last_cmd0 = 4'd0; -reg [3:0] ddrphy_dfitimingschecker_last_cmd1 = 4'd0; -reg [3:0] ddrphy_dfitimingschecker_last_cmd2 = 4'd0; -reg [3:0] ddrphy_dfitimingschecker_last_cmd3 = 4'd0; -reg [3:0] ddrphy_dfitimingschecker_last_cmd4 = 4'd0; -reg [3:0] ddrphy_dfitimingschecker_last_cmd5 = 4'd0; -reg [3:0] ddrphy_dfitimingschecker_last_cmd6 = 4'd0; -reg [3:0] ddrphy_dfitimingschecker_last_cmd7 = 4'd0; -reg [63:0] ddrphy_dfitimingschecker0 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker1 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker2 = 64'd0; -reg [63:0] ddrphy_dfitimingschecker3 = 64'd0; -reg [1:0] ddrphy_dfitimingschecker_act_curr = 2'd0; -reg [3:0] ddrphy_dfitimingschecker_ref_issued = 4'd0; -wire [63:0] ddrphy_dfitimingschecker_ps0; -wire [3:0] ddrphy_dfitimingschecker_state0; -wire ddrphy_dfitimingschecker_all_banks0; -wire ddrphy_dfitimingschecker_cmd_recv0; -wire ddrphy_dfitimingschecker_cmd_recv1; -wire ddrphy_dfitimingschecker_cmd_recv2; -wire [1:0] ddrphy_dfitimingschecker_act_next0; -wire ddrphy_dfitimingschecker_cmd_recv3; -wire ddrphy_dfitimingschecker_cmd_recv4; -wire ddrphy_dfitimingschecker_cmd_recv5; -wire ddrphy_dfitimingschecker_cmd_recv6; -wire ddrphy_dfitimingschecker_cmd_recv7; -wire ddrphy_dfitimingschecker_cmd_recv8; -wire [1:0] ddrphy_dfitimingschecker_act_next1; -wire ddrphy_dfitimingschecker_cmd_recv9; -wire ddrphy_dfitimingschecker_cmd_recv10; -wire ddrphy_dfitimingschecker_cmd_recv11; -wire ddrphy_dfitimingschecker_cmd_recv12; -wire ddrphy_dfitimingschecker_cmd_recv13; -wire ddrphy_dfitimingschecker_cmd_recv14; -wire [1:0] ddrphy_dfitimingschecker_act_next2; -wire ddrphy_dfitimingschecker_cmd_recv15; -wire ddrphy_dfitimingschecker_cmd_recv16; -wire ddrphy_dfitimingschecker_cmd_recv17; -wire ddrphy_dfitimingschecker_cmd_recv18; -wire ddrphy_dfitimingschecker_cmd_recv19; -wire ddrphy_dfitimingschecker_cmd_recv20; -wire [1:0] ddrphy_dfitimingschecker_act_next3; -wire ddrphy_dfitimingschecker_cmd_recv21; -wire ddrphy_dfitimingschecker_cmd_recv22; -wire ddrphy_dfitimingschecker_cmd_recv23; -wire ddrphy_dfitimingschecker_cmd_recv24; -wire ddrphy_dfitimingschecker_cmd_recv25; -wire ddrphy_dfitimingschecker_cmd_recv26; -wire [1:0] ddrphy_dfitimingschecker_act_next4; -wire ddrphy_dfitimingschecker_cmd_recv27; -wire ddrphy_dfitimingschecker_cmd_recv28; -wire ddrphy_dfitimingschecker_cmd_recv29; -wire ddrphy_dfitimingschecker_cmd_recv30; -wire ddrphy_dfitimingschecker_cmd_recv31; -wire ddrphy_dfitimingschecker_cmd_recv32; -wire [1:0] ddrphy_dfitimingschecker_act_next5; -wire ddrphy_dfitimingschecker_cmd_recv33; -wire ddrphy_dfitimingschecker_cmd_recv34; -wire ddrphy_dfitimingschecker_cmd_recv35; -wire ddrphy_dfitimingschecker_cmd_recv36; -wire ddrphy_dfitimingschecker_cmd_recv37; -wire ddrphy_dfitimingschecker_cmd_recv38; -wire [1:0] ddrphy_dfitimingschecker_act_next6; -wire ddrphy_dfitimingschecker_cmd_recv39; -wire ddrphy_dfitimingschecker_cmd_recv40; -wire ddrphy_dfitimingschecker_cmd_recv41; -wire ddrphy_dfitimingschecker_cmd_recv42; -wire ddrphy_dfitimingschecker_cmd_recv43; -wire ddrphy_dfitimingschecker_cmd_recv44; -wire [1:0] ddrphy_dfitimingschecker_act_next7; -wire ddrphy_dfitimingschecker_cmd_recv45; -wire ddrphy_dfitimingschecker_cmd_recv46; -wire ddrphy_dfitimingschecker_cmd_recv47; -wire [63:0] ddrphy_dfitimingschecker_ps1; -wire [3:0] ddrphy_dfitimingschecker_state1; -wire ddrphy_dfitimingschecker_all_banks1; -wire ddrphy_dfitimingschecker_cmd_recv48; -wire ddrphy_dfitimingschecker_cmd_recv49; -wire ddrphy_dfitimingschecker_cmd_recv50; -wire [1:0] ddrphy_dfitimingschecker_act_next8; -wire ddrphy_dfitimingschecker_cmd_recv51; -wire ddrphy_dfitimingschecker_cmd_recv52; -wire ddrphy_dfitimingschecker_cmd_recv53; -wire ddrphy_dfitimingschecker_cmd_recv54; -wire ddrphy_dfitimingschecker_cmd_recv55; -wire ddrphy_dfitimingschecker_cmd_recv56; -wire [1:0] ddrphy_dfitimingschecker_act_next9; -wire ddrphy_dfitimingschecker_cmd_recv57; -wire ddrphy_dfitimingschecker_cmd_recv58; -wire ddrphy_dfitimingschecker_cmd_recv59; -wire ddrphy_dfitimingschecker_cmd_recv60; -wire ddrphy_dfitimingschecker_cmd_recv61; -wire ddrphy_dfitimingschecker_cmd_recv62; -wire [1:0] ddrphy_dfitimingschecker_act_next10; -wire ddrphy_dfitimingschecker_cmd_recv63; -wire ddrphy_dfitimingschecker_cmd_recv64; -wire ddrphy_dfitimingschecker_cmd_recv65; -wire ddrphy_dfitimingschecker_cmd_recv66; -wire ddrphy_dfitimingschecker_cmd_recv67; -wire ddrphy_dfitimingschecker_cmd_recv68; -wire [1:0] ddrphy_dfitimingschecker_act_next11; -wire ddrphy_dfitimingschecker_cmd_recv69; -wire ddrphy_dfitimingschecker_cmd_recv70; -wire ddrphy_dfitimingschecker_cmd_recv71; -wire ddrphy_dfitimingschecker_cmd_recv72; -wire ddrphy_dfitimingschecker_cmd_recv73; -wire ddrphy_dfitimingschecker_cmd_recv74; -wire [1:0] ddrphy_dfitimingschecker_act_next12; -wire ddrphy_dfitimingschecker_cmd_recv75; -wire ddrphy_dfitimingschecker_cmd_recv76; -wire ddrphy_dfitimingschecker_cmd_recv77; -wire ddrphy_dfitimingschecker_cmd_recv78; -wire ddrphy_dfitimingschecker_cmd_recv79; -wire ddrphy_dfitimingschecker_cmd_recv80; -wire [1:0] ddrphy_dfitimingschecker_act_next13; -wire ddrphy_dfitimingschecker_cmd_recv81; -wire ddrphy_dfitimingschecker_cmd_recv82; -wire ddrphy_dfitimingschecker_cmd_recv83; -wire ddrphy_dfitimingschecker_cmd_recv84; -wire ddrphy_dfitimingschecker_cmd_recv85; -wire ddrphy_dfitimingschecker_cmd_recv86; -wire [1:0] ddrphy_dfitimingschecker_act_next14; -wire ddrphy_dfitimingschecker_cmd_recv87; -wire ddrphy_dfitimingschecker_cmd_recv88; -wire ddrphy_dfitimingschecker_cmd_recv89; -wire ddrphy_dfitimingschecker_cmd_recv90; -wire ddrphy_dfitimingschecker_cmd_recv91; -wire ddrphy_dfitimingschecker_cmd_recv92; -wire [1:0] ddrphy_dfitimingschecker_act_next15; -wire ddrphy_dfitimingschecker_cmd_recv93; -wire ddrphy_dfitimingschecker_cmd_recv94; -wire ddrphy_dfitimingschecker_cmd_recv95; -wire [63:0] ddrphy_dfitimingschecker_ps2; -wire [3:0] ddrphy_dfitimingschecker_state2; -wire ddrphy_dfitimingschecker_all_banks2; -wire ddrphy_dfitimingschecker_cmd_recv96; -wire ddrphy_dfitimingschecker_cmd_recv97; -wire ddrphy_dfitimingschecker_cmd_recv98; -wire [1:0] ddrphy_dfitimingschecker_act_next16; -wire ddrphy_dfitimingschecker_cmd_recv99; -wire ddrphy_dfitimingschecker_cmd_recv100; -wire ddrphy_dfitimingschecker_cmd_recv101; -wire ddrphy_dfitimingschecker_cmd_recv102; -wire ddrphy_dfitimingschecker_cmd_recv103; -wire ddrphy_dfitimingschecker_cmd_recv104; -wire [1:0] ddrphy_dfitimingschecker_act_next17; -wire ddrphy_dfitimingschecker_cmd_recv105; -wire ddrphy_dfitimingschecker_cmd_recv106; -wire ddrphy_dfitimingschecker_cmd_recv107; -wire ddrphy_dfitimingschecker_cmd_recv108; -wire ddrphy_dfitimingschecker_cmd_recv109; -wire ddrphy_dfitimingschecker_cmd_recv110; -wire [1:0] ddrphy_dfitimingschecker_act_next18; -wire ddrphy_dfitimingschecker_cmd_recv111; -wire ddrphy_dfitimingschecker_cmd_recv112; -wire ddrphy_dfitimingschecker_cmd_recv113; -wire ddrphy_dfitimingschecker_cmd_recv114; -wire ddrphy_dfitimingschecker_cmd_recv115; -wire ddrphy_dfitimingschecker_cmd_recv116; -wire [1:0] ddrphy_dfitimingschecker_act_next19; -wire ddrphy_dfitimingschecker_cmd_recv117; -wire ddrphy_dfitimingschecker_cmd_recv118; -wire ddrphy_dfitimingschecker_cmd_recv119; -wire ddrphy_dfitimingschecker_cmd_recv120; -wire ddrphy_dfitimingschecker_cmd_recv121; -wire ddrphy_dfitimingschecker_cmd_recv122; -wire [1:0] ddrphy_dfitimingschecker_act_next20; -wire ddrphy_dfitimingschecker_cmd_recv123; -wire ddrphy_dfitimingschecker_cmd_recv124; -wire ddrphy_dfitimingschecker_cmd_recv125; -wire ddrphy_dfitimingschecker_cmd_recv126; -wire ddrphy_dfitimingschecker_cmd_recv127; -wire ddrphy_dfitimingschecker_cmd_recv128; -wire [1:0] ddrphy_dfitimingschecker_act_next21; -wire ddrphy_dfitimingschecker_cmd_recv129; -wire ddrphy_dfitimingschecker_cmd_recv130; -wire ddrphy_dfitimingschecker_cmd_recv131; -wire ddrphy_dfitimingschecker_cmd_recv132; -wire ddrphy_dfitimingschecker_cmd_recv133; -wire ddrphy_dfitimingschecker_cmd_recv134; -wire [1:0] ddrphy_dfitimingschecker_act_next22; -wire ddrphy_dfitimingschecker_cmd_recv135; -wire ddrphy_dfitimingschecker_cmd_recv136; -wire ddrphy_dfitimingschecker_cmd_recv137; -wire ddrphy_dfitimingschecker_cmd_recv138; -wire ddrphy_dfitimingschecker_cmd_recv139; -wire ddrphy_dfitimingschecker_cmd_recv140; -wire [1:0] ddrphy_dfitimingschecker_act_next23; -wire ddrphy_dfitimingschecker_cmd_recv141; -wire ddrphy_dfitimingschecker_cmd_recv142; -wire ddrphy_dfitimingschecker_cmd_recv143; -wire [63:0] ddrphy_dfitimingschecker_ps3; -wire [3:0] ddrphy_dfitimingschecker_state3; -wire ddrphy_dfitimingschecker_all_banks3; -wire ddrphy_dfitimingschecker_cmd_recv144; -wire ddrphy_dfitimingschecker_cmd_recv145; -wire ddrphy_dfitimingschecker_cmd_recv146; -wire [1:0] ddrphy_dfitimingschecker_act_next24; -wire ddrphy_dfitimingschecker_cmd_recv147; -wire ddrphy_dfitimingschecker_cmd_recv148; -wire ddrphy_dfitimingschecker_cmd_recv149; -wire ddrphy_dfitimingschecker_cmd_recv150; -wire ddrphy_dfitimingschecker_cmd_recv151; -wire ddrphy_dfitimingschecker_cmd_recv152; -wire [1:0] ddrphy_dfitimingschecker_act_next25; -wire ddrphy_dfitimingschecker_cmd_recv153; -wire ddrphy_dfitimingschecker_cmd_recv154; -wire ddrphy_dfitimingschecker_cmd_recv155; -wire ddrphy_dfitimingschecker_cmd_recv156; -wire ddrphy_dfitimingschecker_cmd_recv157; -wire ddrphy_dfitimingschecker_cmd_recv158; -wire [1:0] ddrphy_dfitimingschecker_act_next26; -wire ddrphy_dfitimingschecker_cmd_recv159; -wire ddrphy_dfitimingschecker_cmd_recv160; -wire ddrphy_dfitimingschecker_cmd_recv161; -wire ddrphy_dfitimingschecker_cmd_recv162; -wire ddrphy_dfitimingschecker_cmd_recv163; -wire ddrphy_dfitimingschecker_cmd_recv164; -wire [1:0] ddrphy_dfitimingschecker_act_next27; -wire ddrphy_dfitimingschecker_cmd_recv165; -wire ddrphy_dfitimingschecker_cmd_recv166; -wire ddrphy_dfitimingschecker_cmd_recv167; -wire ddrphy_dfitimingschecker_cmd_recv168; -wire ddrphy_dfitimingschecker_cmd_recv169; -wire ddrphy_dfitimingschecker_cmd_recv170; -wire [1:0] ddrphy_dfitimingschecker_act_next28; -wire ddrphy_dfitimingschecker_cmd_recv171; -wire ddrphy_dfitimingschecker_cmd_recv172; -wire ddrphy_dfitimingschecker_cmd_recv173; -wire ddrphy_dfitimingschecker_cmd_recv174; -wire ddrphy_dfitimingschecker_cmd_recv175; -wire ddrphy_dfitimingschecker_cmd_recv176; -wire [1:0] ddrphy_dfitimingschecker_act_next29; -wire ddrphy_dfitimingschecker_cmd_recv177; -wire ddrphy_dfitimingschecker_cmd_recv178; -wire ddrphy_dfitimingschecker_cmd_recv179; -wire ddrphy_dfitimingschecker_cmd_recv180; -wire ddrphy_dfitimingschecker_cmd_recv181; -wire ddrphy_dfitimingschecker_cmd_recv182; -wire [1:0] ddrphy_dfitimingschecker_act_next30; -wire ddrphy_dfitimingschecker_cmd_recv183; -wire ddrphy_dfitimingschecker_cmd_recv184; -wire ddrphy_dfitimingschecker_cmd_recv185; -wire ddrphy_dfitimingschecker_cmd_recv186; -wire ddrphy_dfitimingschecker_cmd_recv187; -wire ddrphy_dfitimingschecker_cmd_recv188; -wire [1:0] ddrphy_dfitimingschecker_act_next31; -wire ddrphy_dfitimingschecker_cmd_recv189; -wire ddrphy_dfitimingschecker_cmd_recv190; -wire ddrphy_dfitimingschecker_cmd_recv191; -reg [63:0] ddrphy_dfitimingschecker_ref_ps = 64'd0; -reg [63:0] ddrphy_dfitimingschecker_ref_ps_mod = 64'd0; -reg signed [63:0] ddrphy_dfitimingschecker_ref_ps_diff = 64'd0; -wire signed [63:0] ddrphy_dfitimingschecker_curr_diff; -reg ddrphy_dfitimingschecker_ref_done = 1'd0; reg ddrphy_bankmodel0_activate = 1'd0; reg [13:0] ddrphy_bankmodel0_activate_row = 14'd0; reg ddrphy_bankmodel0_precharge = 1'd0; @@ -1942,8 +1638,8 @@ reg new_master_rdata_valid8 = 1'd0; reg new_master_rdata_valid9 = 1'd0; wire [13:0] interface0_bank_bus_adr; wire interface0_bank_bus_we; -wire [31:0] interface0_bank_bus_dat_w; -reg [31:0] interface0_bank_bus_dat_r = 32'd0; +wire [7:0] interface0_bank_bus_dat_w; +reg [7:0] interface0_bank_bus_dat_r = 8'd0; wire csrbank0_init_done0_re; wire csrbank0_init_done0_r; wire csrbank0_init_done0_we; @@ -1952,11 +1648,11 @@ wire csrbank0_init_error0_re; wire csrbank0_init_error0_r; wire csrbank0_init_error0_we; wire csrbank0_init_error0_w; -reg csrbank0_sel = 1'd0; +wire csrbank0_sel; wire [13:0] interface1_bank_bus_adr; wire interface1_bank_bus_we; -wire [31:0] interface1_bank_bus_dat_w; -reg [31:0] interface1_bank_bus_dat_r = 32'd0; +wire [7:0] interface1_bank_bus_dat_w; +reg [7:0] interface1_bank_bus_dat_r = 8'd0; wire csrbank1_dfii_control0_re; wire [3:0] csrbank1_dfii_control0_r; wire csrbank1_dfii_control0_we; @@ -1965,87 +1661,199 @@ wire csrbank1_dfii_pi0_command0_re; wire [5:0] csrbank1_dfii_pi0_command0_r; wire csrbank1_dfii_pi0_command0_we; wire [5:0] csrbank1_dfii_pi0_command0_w; +wire csrbank1_dfii_pi0_address1_re; +wire [5:0] csrbank1_dfii_pi0_address1_r; +wire csrbank1_dfii_pi0_address1_we; +wire [5:0] csrbank1_dfii_pi0_address1_w; wire csrbank1_dfii_pi0_address0_re; -wire [13:0] csrbank1_dfii_pi0_address0_r; +wire [7:0] csrbank1_dfii_pi0_address0_r; wire csrbank1_dfii_pi0_address0_we; -wire [13:0] csrbank1_dfii_pi0_address0_w; +wire [7:0] csrbank1_dfii_pi0_address0_w; wire csrbank1_dfii_pi0_baddress0_re; wire [2:0] csrbank1_dfii_pi0_baddress0_r; wire csrbank1_dfii_pi0_baddress0_we; wire [2:0] csrbank1_dfii_pi0_baddress0_w; +wire csrbank1_dfii_pi0_wrdata3_re; +wire [7:0] csrbank1_dfii_pi0_wrdata3_r; +wire csrbank1_dfii_pi0_wrdata3_we; +wire [7:0] csrbank1_dfii_pi0_wrdata3_w; +wire csrbank1_dfii_pi0_wrdata2_re; +wire [7:0] csrbank1_dfii_pi0_wrdata2_r; +wire csrbank1_dfii_pi0_wrdata2_we; +wire [7:0] csrbank1_dfii_pi0_wrdata2_w; +wire csrbank1_dfii_pi0_wrdata1_re; +wire [7:0] csrbank1_dfii_pi0_wrdata1_r; +wire csrbank1_dfii_pi0_wrdata1_we; +wire [7:0] csrbank1_dfii_pi0_wrdata1_w; wire csrbank1_dfii_pi0_wrdata0_re; -wire [31:0] csrbank1_dfii_pi0_wrdata0_r; +wire [7:0] csrbank1_dfii_pi0_wrdata0_r; wire csrbank1_dfii_pi0_wrdata0_we; -wire [31:0] csrbank1_dfii_pi0_wrdata0_w; -wire csrbank1_dfii_pi0_rddata_re; -wire [31:0] csrbank1_dfii_pi0_rddata_r; -wire csrbank1_dfii_pi0_rddata_we; -wire [31:0] csrbank1_dfii_pi0_rddata_w; +wire [7:0] csrbank1_dfii_pi0_wrdata0_w; +wire csrbank1_dfii_pi0_rddata3_re; +wire [7:0] csrbank1_dfii_pi0_rddata3_r; +wire csrbank1_dfii_pi0_rddata3_we; +wire [7:0] csrbank1_dfii_pi0_rddata3_w; +wire csrbank1_dfii_pi0_rddata2_re; +wire [7:0] csrbank1_dfii_pi0_rddata2_r; +wire csrbank1_dfii_pi0_rddata2_we; +wire [7:0] csrbank1_dfii_pi0_rddata2_w; +wire csrbank1_dfii_pi0_rddata1_re; +wire [7:0] csrbank1_dfii_pi0_rddata1_r; +wire csrbank1_dfii_pi0_rddata1_we; +wire [7:0] csrbank1_dfii_pi0_rddata1_w; +wire csrbank1_dfii_pi0_rddata0_re; +wire [7:0] csrbank1_dfii_pi0_rddata0_r; +wire csrbank1_dfii_pi0_rddata0_we; +wire [7:0] csrbank1_dfii_pi0_rddata0_w; wire csrbank1_dfii_pi1_command0_re; wire [5:0] csrbank1_dfii_pi1_command0_r; wire csrbank1_dfii_pi1_command0_we; wire [5:0] csrbank1_dfii_pi1_command0_w; +wire csrbank1_dfii_pi1_address1_re; +wire [5:0] csrbank1_dfii_pi1_address1_r; +wire csrbank1_dfii_pi1_address1_we; +wire [5:0] csrbank1_dfii_pi1_address1_w; wire csrbank1_dfii_pi1_address0_re; -wire [13:0] csrbank1_dfii_pi1_address0_r; +wire [7:0] csrbank1_dfii_pi1_address0_r; wire csrbank1_dfii_pi1_address0_we; -wire [13:0] csrbank1_dfii_pi1_address0_w; +wire [7:0] csrbank1_dfii_pi1_address0_w; wire csrbank1_dfii_pi1_baddress0_re; wire [2:0] csrbank1_dfii_pi1_baddress0_r; wire csrbank1_dfii_pi1_baddress0_we; wire [2:0] csrbank1_dfii_pi1_baddress0_w; +wire csrbank1_dfii_pi1_wrdata3_re; +wire [7:0] csrbank1_dfii_pi1_wrdata3_r; +wire csrbank1_dfii_pi1_wrdata3_we; +wire [7:0] csrbank1_dfii_pi1_wrdata3_w; +wire csrbank1_dfii_pi1_wrdata2_re; +wire [7:0] csrbank1_dfii_pi1_wrdata2_r; +wire csrbank1_dfii_pi1_wrdata2_we; +wire [7:0] csrbank1_dfii_pi1_wrdata2_w; +wire csrbank1_dfii_pi1_wrdata1_re; +wire [7:0] csrbank1_dfii_pi1_wrdata1_r; +wire csrbank1_dfii_pi1_wrdata1_we; +wire [7:0] csrbank1_dfii_pi1_wrdata1_w; wire csrbank1_dfii_pi1_wrdata0_re; -wire [31:0] csrbank1_dfii_pi1_wrdata0_r; +wire [7:0] csrbank1_dfii_pi1_wrdata0_r; wire csrbank1_dfii_pi1_wrdata0_we; -wire [31:0] csrbank1_dfii_pi1_wrdata0_w; -wire csrbank1_dfii_pi1_rddata_re; -wire [31:0] csrbank1_dfii_pi1_rddata_r; -wire csrbank1_dfii_pi1_rddata_we; -wire [31:0] csrbank1_dfii_pi1_rddata_w; +wire [7:0] csrbank1_dfii_pi1_wrdata0_w; +wire csrbank1_dfii_pi1_rddata3_re; +wire [7:0] csrbank1_dfii_pi1_rddata3_r; +wire csrbank1_dfii_pi1_rddata3_we; +wire [7:0] csrbank1_dfii_pi1_rddata3_w; +wire csrbank1_dfii_pi1_rddata2_re; +wire [7:0] csrbank1_dfii_pi1_rddata2_r; +wire csrbank1_dfii_pi1_rddata2_we; +wire [7:0] csrbank1_dfii_pi1_rddata2_w; +wire csrbank1_dfii_pi1_rddata1_re; +wire [7:0] csrbank1_dfii_pi1_rddata1_r; +wire csrbank1_dfii_pi1_rddata1_we; +wire [7:0] csrbank1_dfii_pi1_rddata1_w; +wire csrbank1_dfii_pi1_rddata0_re; +wire [7:0] csrbank1_dfii_pi1_rddata0_r; +wire csrbank1_dfii_pi1_rddata0_we; +wire [7:0] csrbank1_dfii_pi1_rddata0_w; wire csrbank1_dfii_pi2_command0_re; wire [5:0] csrbank1_dfii_pi2_command0_r; wire csrbank1_dfii_pi2_command0_we; wire [5:0] csrbank1_dfii_pi2_command0_w; +wire csrbank1_dfii_pi2_address1_re; +wire [5:0] csrbank1_dfii_pi2_address1_r; +wire csrbank1_dfii_pi2_address1_we; +wire [5:0] csrbank1_dfii_pi2_address1_w; wire csrbank1_dfii_pi2_address0_re; -wire [13:0] csrbank1_dfii_pi2_address0_r; +wire [7:0] csrbank1_dfii_pi2_address0_r; wire csrbank1_dfii_pi2_address0_we; -wire [13:0] csrbank1_dfii_pi2_address0_w; +wire [7:0] csrbank1_dfii_pi2_address0_w; wire csrbank1_dfii_pi2_baddress0_re; wire [2:0] csrbank1_dfii_pi2_baddress0_r; wire csrbank1_dfii_pi2_baddress0_we; wire [2:0] csrbank1_dfii_pi2_baddress0_w; +wire csrbank1_dfii_pi2_wrdata3_re; +wire [7:0] csrbank1_dfii_pi2_wrdata3_r; +wire csrbank1_dfii_pi2_wrdata3_we; +wire [7:0] csrbank1_dfii_pi2_wrdata3_w; +wire csrbank1_dfii_pi2_wrdata2_re; +wire [7:0] csrbank1_dfii_pi2_wrdata2_r; +wire csrbank1_dfii_pi2_wrdata2_we; +wire [7:0] csrbank1_dfii_pi2_wrdata2_w; +wire csrbank1_dfii_pi2_wrdata1_re; +wire [7:0] csrbank1_dfii_pi2_wrdata1_r; +wire csrbank1_dfii_pi2_wrdata1_we; +wire [7:0] csrbank1_dfii_pi2_wrdata1_w; wire csrbank1_dfii_pi2_wrdata0_re; -wire [31:0] csrbank1_dfii_pi2_wrdata0_r; +wire [7:0] csrbank1_dfii_pi2_wrdata0_r; wire csrbank1_dfii_pi2_wrdata0_we; -wire [31:0] csrbank1_dfii_pi2_wrdata0_w; -wire csrbank1_dfii_pi2_rddata_re; -wire [31:0] csrbank1_dfii_pi2_rddata_r; -wire csrbank1_dfii_pi2_rddata_we; -wire [31:0] csrbank1_dfii_pi2_rddata_w; +wire [7:0] csrbank1_dfii_pi2_wrdata0_w; +wire csrbank1_dfii_pi2_rddata3_re; +wire [7:0] csrbank1_dfii_pi2_rddata3_r; +wire csrbank1_dfii_pi2_rddata3_we; +wire [7:0] csrbank1_dfii_pi2_rddata3_w; +wire csrbank1_dfii_pi2_rddata2_re; +wire [7:0] csrbank1_dfii_pi2_rddata2_r; +wire csrbank1_dfii_pi2_rddata2_we; +wire [7:0] csrbank1_dfii_pi2_rddata2_w; +wire csrbank1_dfii_pi2_rddata1_re; +wire [7:0] csrbank1_dfii_pi2_rddata1_r; +wire csrbank1_dfii_pi2_rddata1_we; +wire [7:0] csrbank1_dfii_pi2_rddata1_w; +wire csrbank1_dfii_pi2_rddata0_re; +wire [7:0] csrbank1_dfii_pi2_rddata0_r; +wire csrbank1_dfii_pi2_rddata0_we; +wire [7:0] csrbank1_dfii_pi2_rddata0_w; wire csrbank1_dfii_pi3_command0_re; wire [5:0] csrbank1_dfii_pi3_command0_r; wire csrbank1_dfii_pi3_command0_we; wire [5:0] csrbank1_dfii_pi3_command0_w; +wire csrbank1_dfii_pi3_address1_re; +wire [5:0] csrbank1_dfii_pi3_address1_r; +wire csrbank1_dfii_pi3_address1_we; +wire [5:0] csrbank1_dfii_pi3_address1_w; wire csrbank1_dfii_pi3_address0_re; -wire [13:0] csrbank1_dfii_pi3_address0_r; +wire [7:0] csrbank1_dfii_pi3_address0_r; wire csrbank1_dfii_pi3_address0_we; -wire [13:0] csrbank1_dfii_pi3_address0_w; +wire [7:0] csrbank1_dfii_pi3_address0_w; wire csrbank1_dfii_pi3_baddress0_re; wire [2:0] csrbank1_dfii_pi3_baddress0_r; wire csrbank1_dfii_pi3_baddress0_we; wire [2:0] csrbank1_dfii_pi3_baddress0_w; +wire csrbank1_dfii_pi3_wrdata3_re; +wire [7:0] csrbank1_dfii_pi3_wrdata3_r; +wire csrbank1_dfii_pi3_wrdata3_we; +wire [7:0] csrbank1_dfii_pi3_wrdata3_w; +wire csrbank1_dfii_pi3_wrdata2_re; +wire [7:0] csrbank1_dfii_pi3_wrdata2_r; +wire csrbank1_dfii_pi3_wrdata2_we; +wire [7:0] csrbank1_dfii_pi3_wrdata2_w; +wire csrbank1_dfii_pi3_wrdata1_re; +wire [7:0] csrbank1_dfii_pi3_wrdata1_r; +wire csrbank1_dfii_pi3_wrdata1_we; +wire [7:0] csrbank1_dfii_pi3_wrdata1_w; wire csrbank1_dfii_pi3_wrdata0_re; -wire [31:0] csrbank1_dfii_pi3_wrdata0_r; +wire [7:0] csrbank1_dfii_pi3_wrdata0_r; wire csrbank1_dfii_pi3_wrdata0_we; -wire [31:0] csrbank1_dfii_pi3_wrdata0_w; -wire csrbank1_dfii_pi3_rddata_re; -wire [31:0] csrbank1_dfii_pi3_rddata_r; -wire csrbank1_dfii_pi3_rddata_we; -wire [31:0] csrbank1_dfii_pi3_rddata_w; -reg csrbank1_sel = 1'd0; +wire [7:0] csrbank1_dfii_pi3_wrdata0_w; +wire csrbank1_dfii_pi3_rddata3_re; +wire [7:0] csrbank1_dfii_pi3_rddata3_r; +wire csrbank1_dfii_pi3_rddata3_we; +wire [7:0] csrbank1_dfii_pi3_rddata3_w; +wire csrbank1_dfii_pi3_rddata2_re; +wire [7:0] csrbank1_dfii_pi3_rddata2_r; +wire csrbank1_dfii_pi3_rddata2_we; +wire [7:0] csrbank1_dfii_pi3_rddata2_w; +wire csrbank1_dfii_pi3_rddata1_re; +wire [7:0] csrbank1_dfii_pi3_rddata1_r; +wire csrbank1_dfii_pi3_rddata1_we; +wire [7:0] csrbank1_dfii_pi3_rddata1_w; +wire csrbank1_dfii_pi3_rddata0_re; +wire [7:0] csrbank1_dfii_pi3_rddata0_r; +wire csrbank1_dfii_pi3_rddata0_we; +wire [7:0] csrbank1_dfii_pi3_rddata0_w; +wire csrbank1_sel; wire [13:0] adr; wire we; -wire [31:0] dat_w; -wire [31:0] dat_r; +wire [7:0] dat_w; +wire [7:0] dat_r; wire [24:0] slice_proxy0; wire [24:0] slice_proxy1; wire [24:0] slice_proxy2; @@ -2062,172 +1870,76 @@ wire [24:0] slice_proxy12; wire [24:0] slice_proxy13; wire [24:0] slice_proxy14; wire [24:0] slice_proxy15; -reg comb_rhs_array_muxed0 = 1'd0; -reg [13:0] comb_rhs_array_muxed1 = 14'd0; -reg [2:0] comb_rhs_array_muxed2 = 3'd0; -reg comb_rhs_array_muxed3 = 1'd0; -reg comb_rhs_array_muxed4 = 1'd0; -reg comb_rhs_array_muxed5 = 1'd0; -reg comb_t_array_muxed0 = 1'd0; -reg comb_t_array_muxed1 = 1'd0; -reg comb_t_array_muxed2 = 1'd0; -reg comb_rhs_array_muxed6 = 1'd0; -reg [13:0] comb_rhs_array_muxed7 = 14'd0; -reg [2:0] comb_rhs_array_muxed8 = 3'd0; -reg comb_rhs_array_muxed9 = 1'd0; -reg comb_rhs_array_muxed10 = 1'd0; -reg comb_rhs_array_muxed11 = 1'd0; -reg comb_t_array_muxed3 = 1'd0; -reg comb_t_array_muxed4 = 1'd0; -reg comb_t_array_muxed5 = 1'd0; -reg [20:0] comb_rhs_array_muxed12 = 21'd0; -reg comb_rhs_array_muxed13 = 1'd0; -reg comb_rhs_array_muxed14 = 1'd0; -reg [20:0] comb_rhs_array_muxed15 = 21'd0; -reg comb_rhs_array_muxed16 = 1'd0; -reg comb_rhs_array_muxed17 = 1'd0; -reg [20:0] comb_rhs_array_muxed18 = 21'd0; -reg comb_rhs_array_muxed19 = 1'd0; -reg comb_rhs_array_muxed20 = 1'd0; -reg [20:0] comb_rhs_array_muxed21 = 21'd0; -reg comb_rhs_array_muxed22 = 1'd0; -reg comb_rhs_array_muxed23 = 1'd0; -reg [20:0] comb_rhs_array_muxed24 = 21'd0; -reg comb_rhs_array_muxed25 = 1'd0; -reg comb_rhs_array_muxed26 = 1'd0; -reg [20:0] comb_rhs_array_muxed27 = 21'd0; -reg comb_rhs_array_muxed28 = 1'd0; -reg comb_rhs_array_muxed29 = 1'd0; -reg [20:0] comb_rhs_array_muxed30 = 21'd0; -reg comb_rhs_array_muxed31 = 1'd0; -reg comb_rhs_array_muxed32 = 1'd0; -reg [20:0] comb_rhs_array_muxed33 = 21'd0; -reg comb_rhs_array_muxed34 = 1'd0; -reg comb_rhs_array_muxed35 = 1'd0; -reg [63:0] sync_basiclowerer_array_muxed0 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed1 = 64'd0; -reg [63:0] sync_t_array_muxed0 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed2 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed3 = 64'd0; -reg [63:0] sync_t_array_muxed1 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed4 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed5 = 64'd0; -reg [63:0] sync_t_array_muxed2 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed6 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed7 = 64'd0; -reg [63:0] sync_t_array_muxed3 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed8 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed9 = 64'd0; -reg [63:0] sync_t_array_muxed4 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed10 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed11 = 64'd0; -reg [63:0] sync_t_array_muxed5 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed12 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed13 = 64'd0; -reg [63:0] sync_t_array_muxed6 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed14 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed15 = 64'd0; -reg [63:0] sync_t_array_muxed7 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed16 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed17 = 64'd0; -reg [63:0] sync_t_array_muxed8 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed18 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed19 = 64'd0; -reg [63:0] sync_t_array_muxed9 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed20 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed21 = 64'd0; -reg [63:0] sync_t_array_muxed10 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed22 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed23 = 64'd0; -reg [63:0] sync_t_array_muxed11 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed24 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed25 = 64'd0; -reg [63:0] sync_t_array_muxed12 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed26 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed27 = 64'd0; -reg [63:0] sync_t_array_muxed13 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed28 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed29 = 64'd0; -reg [63:0] sync_t_array_muxed14 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed30 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed31 = 64'd0; -reg [63:0] sync_t_array_muxed15 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed32 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed33 = 64'd0; -reg [63:0] sync_t_array_muxed16 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed34 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed35 = 64'd0; -reg [63:0] sync_t_array_muxed17 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed36 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed37 = 64'd0; -reg [63:0] sync_t_array_muxed18 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed38 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed39 = 64'd0; -reg [63:0] sync_t_array_muxed19 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed40 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed41 = 64'd0; -reg [63:0] sync_t_array_muxed20 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed42 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed43 = 64'd0; -reg [63:0] sync_t_array_muxed21 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed44 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed45 = 64'd0; -reg [63:0] sync_t_array_muxed22 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed46 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed47 = 64'd0; -reg [63:0] sync_t_array_muxed23 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed48 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed49 = 64'd0; -reg [63:0] sync_t_array_muxed24 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed50 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed51 = 64'd0; -reg [63:0] sync_t_array_muxed25 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed52 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed53 = 64'd0; -reg [63:0] sync_t_array_muxed26 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed54 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed55 = 64'd0; -reg [63:0] sync_t_array_muxed27 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed56 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed57 = 64'd0; -reg [63:0] sync_t_array_muxed28 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed58 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed59 = 64'd0; -reg [63:0] sync_t_array_muxed29 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed60 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed61 = 64'd0; -reg [63:0] sync_t_array_muxed30 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed62 = 64'd0; -reg [63:0] sync_basiclowerer_array_muxed63 = 64'd0; -reg [63:0] sync_t_array_muxed31 = 64'd0; -reg [2:0] sync_rhs_array_muxed0 = 3'd0; -reg [13:0] sync_rhs_array_muxed1 = 14'd0; -reg sync_rhs_array_muxed2 = 1'd0; -reg sync_rhs_array_muxed3 = 1'd0; -reg sync_rhs_array_muxed4 = 1'd0; -reg sync_rhs_array_muxed5 = 1'd0; -reg sync_rhs_array_muxed6 = 1'd0; -reg [2:0] sync_rhs_array_muxed7 = 3'd0; -reg [13:0] sync_rhs_array_muxed8 = 14'd0; -reg sync_rhs_array_muxed9 = 1'd0; -reg sync_rhs_array_muxed10 = 1'd0; -reg sync_rhs_array_muxed11 = 1'd0; -reg sync_rhs_array_muxed12 = 1'd0; -reg sync_rhs_array_muxed13 = 1'd0; -reg [2:0] sync_rhs_array_muxed14 = 3'd0; -reg [13:0] sync_rhs_array_muxed15 = 14'd0; -reg sync_rhs_array_muxed16 = 1'd0; -reg sync_rhs_array_muxed17 = 1'd0; -reg sync_rhs_array_muxed18 = 1'd0; -reg sync_rhs_array_muxed19 = 1'd0; -reg sync_rhs_array_muxed20 = 1'd0; -reg [2:0] sync_rhs_array_muxed21 = 3'd0; -reg [13:0] sync_rhs_array_muxed22 = 14'd0; -reg sync_rhs_array_muxed23 = 1'd0; -reg sync_rhs_array_muxed24 = 1'd0; -reg sync_rhs_array_muxed25 = 1'd0; -reg sync_rhs_array_muxed26 = 1'd0; -reg sync_rhs_array_muxed27 = 1'd0; +reg rhs_array_muxed0 = 1'd0; +reg [13:0] rhs_array_muxed1 = 14'd0; +reg [2:0] rhs_array_muxed2 = 3'd0; +reg rhs_array_muxed3 = 1'd0; +reg rhs_array_muxed4 = 1'd0; +reg rhs_array_muxed5 = 1'd0; +reg t_array_muxed0 = 1'd0; +reg t_array_muxed1 = 1'd0; +reg t_array_muxed2 = 1'd0; +reg rhs_array_muxed6 = 1'd0; +reg [13:0] rhs_array_muxed7 = 14'd0; +reg [2:0] rhs_array_muxed8 = 3'd0; +reg rhs_array_muxed9 = 1'd0; +reg rhs_array_muxed10 = 1'd0; +reg rhs_array_muxed11 = 1'd0; +reg t_array_muxed3 = 1'd0; +reg t_array_muxed4 = 1'd0; +reg t_array_muxed5 = 1'd0; +reg [20:0] rhs_array_muxed12 = 21'd0; +reg rhs_array_muxed13 = 1'd0; +reg rhs_array_muxed14 = 1'd0; +reg [20:0] rhs_array_muxed15 = 21'd0; +reg rhs_array_muxed16 = 1'd0; +reg rhs_array_muxed17 = 1'd0; +reg [20:0] rhs_array_muxed18 = 21'd0; +reg rhs_array_muxed19 = 1'd0; +reg rhs_array_muxed20 = 1'd0; +reg [20:0] rhs_array_muxed21 = 21'd0; +reg rhs_array_muxed22 = 1'd0; +reg rhs_array_muxed23 = 1'd0; +reg [20:0] rhs_array_muxed24 = 21'd0; +reg rhs_array_muxed25 = 1'd0; +reg rhs_array_muxed26 = 1'd0; +reg [20:0] rhs_array_muxed27 = 21'd0; +reg rhs_array_muxed28 = 1'd0; +reg rhs_array_muxed29 = 1'd0; +reg [20:0] rhs_array_muxed30 = 21'd0; +reg rhs_array_muxed31 = 1'd0; +reg rhs_array_muxed32 = 1'd0; +reg [20:0] rhs_array_muxed33 = 21'd0; +reg rhs_array_muxed34 = 1'd0; +reg rhs_array_muxed35 = 1'd0; +reg [2:0] array_muxed0 = 3'd0; +reg [13:0] array_muxed1 = 14'd0; +reg array_muxed2 = 1'd0; +reg array_muxed3 = 1'd0; +reg array_muxed4 = 1'd0; +reg array_muxed5 = 1'd0; +reg array_muxed6 = 1'd0; +reg [2:0] array_muxed7 = 3'd0; +reg [13:0] array_muxed8 = 14'd0; +reg array_muxed9 = 1'd0; +reg array_muxed10 = 1'd0; +reg array_muxed11 = 1'd0; +reg array_muxed12 = 1'd0; +reg array_muxed13 = 1'd0; +reg [2:0] array_muxed14 = 3'd0; +reg [13:0] array_muxed15 = 14'd0; +reg array_muxed16 = 1'd0; +reg array_muxed17 = 1'd0; +reg array_muxed18 = 1'd0; +reg array_muxed19 = 1'd0; +reg array_muxed20 = 1'd0; +reg [2:0] array_muxed21 = 3'd0; +reg [13:0] array_muxed22 = 14'd0; +reg array_muxed23 = 1'd0; +reg array_muxed24 = 1'd0; +reg array_muxed25 = 1'd0; +reg array_muxed26 = 1'd0; +reg array_muxed27 = 1'd0; assign init_done = init_done_storage; assign init_error = init_error_storage; @@ -2272,36 +1984,36 @@ always @(*) begin endcase end always @(*) begin - litedramcore_adr = 14'd0; + litedramcore_we = 1'd0; case (state) 1'd1: begin end default: begin if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr = litedramcore_wishbone_adr; + litedramcore_we = (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); end end endcase end always @(*) begin - litedramcore_we = 1'd0; + litedramcore_wishbone_ack = 1'd0; case (state) 1'd1: begin + litedramcore_wishbone_ack = 1'd1; end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we = litedramcore_wishbone_we; - end end endcase end always @(*) begin - litedramcore_wishbone_ack = 1'd0; + litedramcore_adr = 14'd0; case (state) 1'd1: begin - litedramcore_wishbone_ack = 1'd1; end default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr = litedramcore_wishbone_adr; + end end endcase end @@ -2381,36 +2093,36 @@ always @(*) begin ddrphy_writes0[3] = ddrphy_dfiphasemodel3_write; end always @(*) begin - ddrphy_bank_write0 = 1'd0; + ddrphy_bank_write_col0 = 10'd0; case (ddrphy_writes0) 1'd1: begin - ddrphy_bank_write0 = (ddrphy_dfi_p0_bank == 1'd0); + ddrphy_bank_write_col0 = ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bank_write0 = (ddrphy_dfi_p1_bank == 1'd0); + ddrphy_bank_write_col0 = ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bank_write0 = (ddrphy_dfi_p2_bank == 1'd0); + ddrphy_bank_write_col0 = ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bank_write0 = (ddrphy_dfi_p3_bank == 1'd0); + ddrphy_bank_write_col0 = ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_bank_write_col0 = 10'd0; + ddrphy_bank_write0 = 1'd0; case (ddrphy_writes0) 1'd1: begin - ddrphy_bank_write_col0 = ddrphy_dfi_p0_address; + ddrphy_bank_write0 = (ddrphy_dfi_p0_bank == 1'd0); end 2'd2: begin - ddrphy_bank_write_col0 = ddrphy_dfi_p1_address; + ddrphy_bank_write0 = (ddrphy_dfi_p1_bank == 1'd0); end 3'd4: begin - ddrphy_bank_write_col0 = ddrphy_dfi_p2_address; + ddrphy_bank_write0 = (ddrphy_dfi_p2_bank == 1'd0); end 4'd8: begin - ddrphy_bank_write_col0 = ddrphy_dfi_p3_address; + ddrphy_bank_write0 = (ddrphy_dfi_p3_bank == 1'd0); end endcase end @@ -2426,36 +2138,36 @@ always @(*) begin ddrphy_reads0[3] = ddrphy_dfiphasemodel3_read; end always @(*) begin - ddrphy_bankmodel0_read_col = 10'd0; + ddrphy_bankmodel0_read = 1'd0; case (ddrphy_reads0) 1'd1: begin - ddrphy_bankmodel0_read_col = ddrphy_dfi_p0_address; + ddrphy_bankmodel0_read = (ddrphy_dfi_p0_bank == 1'd0); end 2'd2: begin - ddrphy_bankmodel0_read_col = ddrphy_dfi_p1_address; + ddrphy_bankmodel0_read = (ddrphy_dfi_p1_bank == 1'd0); end 3'd4: begin - ddrphy_bankmodel0_read_col = ddrphy_dfi_p2_address; + ddrphy_bankmodel0_read = (ddrphy_dfi_p2_bank == 1'd0); end 4'd8: begin - ddrphy_bankmodel0_read_col = ddrphy_dfi_p3_address; + ddrphy_bankmodel0_read = (ddrphy_dfi_p3_bank == 1'd0); end endcase end always @(*) begin - ddrphy_bankmodel0_read = 1'd0; + ddrphy_bankmodel0_read_col = 10'd0; case (ddrphy_reads0) 1'd1: begin - ddrphy_bankmodel0_read = (ddrphy_dfi_p0_bank == 1'd0); + ddrphy_bankmodel0_read_col = ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel0_read = (ddrphy_dfi_p1_bank == 1'd0); + ddrphy_bankmodel0_read_col = ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel0_read = (ddrphy_dfi_p2_bank == 1'd0); + ddrphy_bankmodel0_read_col = ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel0_read = (ddrphy_dfi_p3_bank == 1'd0); + ddrphy_bankmodel0_read_col = ddrphy_dfi_p3_address; end endcase end @@ -2618,36 +2330,36 @@ always @(*) begin ddrphy_activates2[3] = ddrphy_dfiphasemodel3_activate; end always @(*) begin - ddrphy_bankmodel2_activate_row = 14'd0; + ddrphy_bankmodel2_activate = 1'd0; case (ddrphy_activates2) 1'd1: begin - ddrphy_bankmodel2_activate_row = ddrphy_dfi_p0_address; + ddrphy_bankmodel2_activate = (ddrphy_dfi_p0_bank == 2'd2); end 2'd2: begin - ddrphy_bankmodel2_activate_row = ddrphy_dfi_p1_address; + ddrphy_bankmodel2_activate = (ddrphy_dfi_p1_bank == 2'd2); end 3'd4: begin - ddrphy_bankmodel2_activate_row = ddrphy_dfi_p2_address; + ddrphy_bankmodel2_activate = (ddrphy_dfi_p2_bank == 2'd2); end 4'd8: begin - ddrphy_bankmodel2_activate_row = ddrphy_dfi_p3_address; + ddrphy_bankmodel2_activate = (ddrphy_dfi_p3_bank == 2'd2); end endcase end always @(*) begin - ddrphy_bankmodel2_activate = 1'd0; + ddrphy_bankmodel2_activate_row = 14'd0; case (ddrphy_activates2) 1'd1: begin - ddrphy_bankmodel2_activate = (ddrphy_dfi_p0_bank == 2'd2); + ddrphy_bankmodel2_activate_row = ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel2_activate = (ddrphy_dfi_p1_bank == 2'd2); + ddrphy_bankmodel2_activate_row = ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel2_activate = (ddrphy_dfi_p2_bank == 2'd2); + ddrphy_bankmodel2_activate_row = ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel2_activate = (ddrphy_dfi_p3_bank == 2'd2); + ddrphy_bankmodel2_activate_row = ddrphy_dfi_p3_address; end endcase end @@ -2728,36 +2440,36 @@ always @(*) begin ddrphy_reads2[3] = ddrphy_dfiphasemodel3_read; end always @(*) begin - ddrphy_bankmodel2_read = 1'd0; + ddrphy_bankmodel2_read_col = 10'd0; case (ddrphy_reads2) 1'd1: begin - ddrphy_bankmodel2_read = (ddrphy_dfi_p0_bank == 2'd2); + ddrphy_bankmodel2_read_col = ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel2_read = (ddrphy_dfi_p1_bank == 2'd2); + ddrphy_bankmodel2_read_col = ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel2_read = (ddrphy_dfi_p2_bank == 2'd2); + ddrphy_bankmodel2_read_col = ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel2_read = (ddrphy_dfi_p3_bank == 2'd2); + ddrphy_bankmodel2_read_col = ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_bankmodel2_read_col = 10'd0; + ddrphy_bankmodel2_read = 1'd0; case (ddrphy_reads2) 1'd1: begin - ddrphy_bankmodel2_read_col = ddrphy_dfi_p0_address; + ddrphy_bankmodel2_read = (ddrphy_dfi_p0_bank == 2'd2); end 2'd2: begin - ddrphy_bankmodel2_read_col = ddrphy_dfi_p1_address; + ddrphy_bankmodel2_read = (ddrphy_dfi_p1_bank == 2'd2); end 3'd4: begin - ddrphy_bankmodel2_read_col = ddrphy_dfi_p2_address; + ddrphy_bankmodel2_read = (ddrphy_dfi_p2_bank == 2'd2); end 4'd8: begin - ddrphy_bankmodel2_read_col = ddrphy_dfi_p3_address; + ddrphy_bankmodel2_read = (ddrphy_dfi_p3_bank == 2'd2); end endcase end @@ -2834,36 +2546,36 @@ always @(*) begin ddrphy_writes3[3] = ddrphy_dfiphasemodel3_write; end always @(*) begin - ddrphy_bank_write_col3 = 10'd0; + ddrphy_bank_write3 = 1'd0; case (ddrphy_writes3) 1'd1: begin - ddrphy_bank_write_col3 = ddrphy_dfi_p0_address; + ddrphy_bank_write3 = (ddrphy_dfi_p0_bank == 2'd3); end 2'd2: begin - ddrphy_bank_write_col3 = ddrphy_dfi_p1_address; + ddrphy_bank_write3 = (ddrphy_dfi_p1_bank == 2'd3); end 3'd4: begin - ddrphy_bank_write_col3 = ddrphy_dfi_p2_address; + ddrphy_bank_write3 = (ddrphy_dfi_p2_bank == 2'd3); end 4'd8: begin - ddrphy_bank_write_col3 = ddrphy_dfi_p3_address; + ddrphy_bank_write3 = (ddrphy_dfi_p3_bank == 2'd3); end endcase end always @(*) begin - ddrphy_bank_write3 = 1'd0; + ddrphy_bank_write_col3 = 10'd0; case (ddrphy_writes3) 1'd1: begin - ddrphy_bank_write3 = (ddrphy_dfi_p0_bank == 2'd3); + ddrphy_bank_write_col3 = ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bank_write3 = (ddrphy_dfi_p1_bank == 2'd3); + ddrphy_bank_write_col3 = ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bank_write3 = (ddrphy_dfi_p2_bank == 2'd3); + ddrphy_bank_write_col3 = ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bank_write3 = (ddrphy_dfi_p3_bank == 2'd3); + ddrphy_bank_write_col3 = ddrphy_dfi_p3_address; end endcase end @@ -2920,36 +2632,36 @@ always @(*) begin ddrphy_activates4[3] = ddrphy_dfiphasemodel3_activate; end always @(*) begin - ddrphy_bankmodel4_activate = 1'd0; + ddrphy_bankmodel4_activate_row = 14'd0; case (ddrphy_activates4) 1'd1: begin - ddrphy_bankmodel4_activate = (ddrphy_dfi_p0_bank == 3'd4); + ddrphy_bankmodel4_activate_row = ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bankmodel4_activate = (ddrphy_dfi_p1_bank == 3'd4); + ddrphy_bankmodel4_activate_row = ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bankmodel4_activate = (ddrphy_dfi_p2_bank == 3'd4); + ddrphy_bankmodel4_activate_row = ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bankmodel4_activate = (ddrphy_dfi_p3_bank == 3'd4); + ddrphy_bankmodel4_activate_row = ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_bankmodel4_activate_row = 14'd0; + ddrphy_bankmodel4_activate = 1'd0; case (ddrphy_activates4) 1'd1: begin - ddrphy_bankmodel4_activate_row = ddrphy_dfi_p0_address; + ddrphy_bankmodel4_activate = (ddrphy_dfi_p0_bank == 3'd4); end 2'd2: begin - ddrphy_bankmodel4_activate_row = ddrphy_dfi_p1_address; + ddrphy_bankmodel4_activate = (ddrphy_dfi_p1_bank == 3'd4); end 3'd4: begin - ddrphy_bankmodel4_activate_row = ddrphy_dfi_p2_address; + ddrphy_bankmodel4_activate = (ddrphy_dfi_p2_bank == 3'd4); end 4'd8: begin - ddrphy_bankmodel4_activate_row = ddrphy_dfi_p3_address; + ddrphy_bankmodel4_activate = (ddrphy_dfi_p3_bank == 3'd4); end endcase end @@ -2985,36 +2697,36 @@ always @(*) begin ddrphy_writes4[3] = ddrphy_dfiphasemodel3_write; end always @(*) begin - ddrphy_bank_write4 = 1'd0; + ddrphy_bank_write_col4 = 10'd0; case (ddrphy_writes4) 1'd1: begin - ddrphy_bank_write4 = (ddrphy_dfi_p0_bank == 3'd4); + ddrphy_bank_write_col4 = ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bank_write4 = (ddrphy_dfi_p1_bank == 3'd4); + ddrphy_bank_write_col4 = ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bank_write4 = (ddrphy_dfi_p2_bank == 3'd4); + ddrphy_bank_write_col4 = ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bank_write4 = (ddrphy_dfi_p3_bank == 3'd4); + ddrphy_bank_write_col4 = ddrphy_dfi_p3_address; end endcase end always @(*) begin - ddrphy_bank_write_col4 = 10'd0; + ddrphy_bank_write4 = 1'd0; case (ddrphy_writes4) 1'd1: begin - ddrphy_bank_write_col4 = ddrphy_dfi_p0_address; + ddrphy_bank_write4 = (ddrphy_dfi_p0_bank == 3'd4); end 2'd2: begin - ddrphy_bank_write_col4 = ddrphy_dfi_p1_address; + ddrphy_bank_write4 = (ddrphy_dfi_p1_bank == 3'd4); end 3'd4: begin - ddrphy_bank_write_col4 = ddrphy_dfi_p2_address; + ddrphy_bank_write4 = (ddrphy_dfi_p2_bank == 3'd4); end 4'd8: begin - ddrphy_bank_write_col4 = ddrphy_dfi_p3_address; + ddrphy_bank_write4 = (ddrphy_dfi_p3_bank == 3'd4); end endcase end @@ -3438,36 +3150,36 @@ always @(*) begin ddrphy_writes7[3] = ddrphy_dfiphasemodel3_write; end always @(*) begin - ddrphy_bank_write_col7 = 10'd0; + ddrphy_bank_write7 = 1'd0; case (ddrphy_writes7) 1'd1: begin - ddrphy_bank_write_col7 = ddrphy_dfi_p0_address; + ddrphy_bank_write7 = (ddrphy_dfi_p0_bank == 3'd7); end 2'd2: begin - ddrphy_bank_write_col7 = ddrphy_dfi_p1_address; + ddrphy_bank_write7 = (ddrphy_dfi_p1_bank == 3'd7); end 3'd4: begin - ddrphy_bank_write_col7 = ddrphy_dfi_p2_address; + ddrphy_bank_write7 = (ddrphy_dfi_p2_bank == 3'd7); end 4'd8: begin - ddrphy_bank_write_col7 = ddrphy_dfi_p3_address; + ddrphy_bank_write7 = (ddrphy_dfi_p3_bank == 3'd7); end endcase end always @(*) begin - ddrphy_bank_write7 = 1'd0; + ddrphy_bank_write_col7 = 10'd0; case (ddrphy_writes7) 1'd1: begin - ddrphy_bank_write7 = (ddrphy_dfi_p0_bank == 3'd7); + ddrphy_bank_write_col7 = ddrphy_dfi_p0_address; end 2'd2: begin - ddrphy_bank_write7 = (ddrphy_dfi_p1_bank == 3'd7); + ddrphy_bank_write_col7 = ddrphy_dfi_p1_address; end 3'd4: begin - ddrphy_bank_write7 = (ddrphy_dfi_p2_bank == 3'd7); + ddrphy_bank_write_col7 = ddrphy_dfi_p2_address; end 4'd8: begin - ddrphy_bank_write7 = (ddrphy_dfi_p3_bank == 3'd7); + ddrphy_bank_write_col7 = ddrphy_dfi_p3_address; end endcase end @@ -3622,250 +3334,6 @@ always @(*) begin ddrphy_dfiphasemodel3_read = ddrphy_dfi_p3_we_n; end end -assign ddrphy_dfitimingschecker_ps0 = ((ddrphy_dfitimingschecker_cnt + 1'd0) * 12'd2500); -assign ddrphy_dfitimingschecker_state0 = {ddrphy_dfi_p0_cs_n, ddrphy_dfi_p0_ras_n, ddrphy_dfi_p0_cas_n, ddrphy_dfi_p0_we_n}; -assign ddrphy_dfitimingschecker_all_banks0 = ((ddrphy_dfitimingschecker_state0 == 1'd1) | ((ddrphy_dfitimingschecker_state0 == 2'd2) & ddrphy_dfi_p0_address[10])); -always @(*) begin - ddrphy_dfitimingschecker_ref_issued = 4'd0; - ddrphy_dfitimingschecker_ref_issued[0] = (ddrphy_dfitimingschecker_state0 == 1'd1); - ddrphy_dfitimingschecker_ref_issued[1] = (ddrphy_dfitimingschecker_state1 == 1'd1); - ddrphy_dfitimingschecker_ref_issued[2] = (ddrphy_dfitimingschecker_state2 == 1'd1); - ddrphy_dfitimingschecker_ref_issued[3] = (ddrphy_dfitimingschecker_state3 == 1'd1); -end -assign ddrphy_dfitimingschecker_cmd_recv0 = (((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv1 = (((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv2 = (((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next0 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv3 = (((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv4 = (((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv5 = (((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv6 = (((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv7 = (((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv8 = (((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next1 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv9 = (((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv10 = (((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv11 = (((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv12 = (((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv13 = (((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv14 = (((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next2 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv15 = (((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv16 = (((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv17 = (((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv18 = (((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv19 = (((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv20 = (((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next3 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv21 = (((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv22 = (((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv23 = (((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv24 = (((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv25 = (((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv26 = (((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next4 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv27 = (((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv28 = (((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv29 = (((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv30 = (((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv31 = (((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv32 = (((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next5 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv33 = (((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv34 = (((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv35 = (((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv36 = (((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv37 = (((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv38 = (((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next6 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv39 = (((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv40 = (((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv41 = (((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv42 = (((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv43 = (((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv44 = (((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next7 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv45 = (((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv46 = (((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv47 = (((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6)); -assign ddrphy_dfitimingschecker_ps1 = ((ddrphy_dfitimingschecker_cnt + 1'd1) * 12'd2500); -assign ddrphy_dfitimingschecker_state1 = {ddrphy_dfi_p1_cs_n, ddrphy_dfi_p1_ras_n, ddrphy_dfi_p1_cas_n, ddrphy_dfi_p1_we_n}; -assign ddrphy_dfitimingschecker_all_banks1 = ((ddrphy_dfitimingschecker_state1 == 1'd1) | ((ddrphy_dfitimingschecker_state1 == 2'd2) & ddrphy_dfi_p1_address[10])); -assign ddrphy_dfitimingschecker_cmd_recv48 = (((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv49 = (((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv50 = (((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next8 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv51 = (((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv52 = (((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv53 = (((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv54 = (((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv55 = (((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv56 = (((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next9 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv57 = (((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv58 = (((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv59 = (((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv60 = (((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv61 = (((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv62 = (((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next10 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv63 = (((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv64 = (((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv65 = (((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv66 = (((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv67 = (((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv68 = (((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next11 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv69 = (((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv70 = (((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv71 = (((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv72 = (((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv73 = (((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv74 = (((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next12 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv75 = (((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv76 = (((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv77 = (((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv78 = (((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv79 = (((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv80 = (((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next13 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv81 = (((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv82 = (((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv83 = (((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv84 = (((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv85 = (((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv86 = (((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next14 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv87 = (((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv88 = (((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv89 = (((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv90 = (((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv91 = (((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv92 = (((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next15 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv93 = (((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv94 = (((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv95 = (((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6)); -assign ddrphy_dfitimingschecker_ps2 = ((ddrphy_dfitimingschecker_cnt + 2'd2) * 12'd2500); -assign ddrphy_dfitimingschecker_state2 = {ddrphy_dfi_p2_cs_n, ddrphy_dfi_p2_ras_n, ddrphy_dfi_p2_cas_n, ddrphy_dfi_p2_we_n}; -assign ddrphy_dfitimingschecker_all_banks2 = ((ddrphy_dfitimingschecker_state2 == 1'd1) | ((ddrphy_dfitimingschecker_state2 == 2'd2) & ddrphy_dfi_p2_address[10])); -assign ddrphy_dfitimingschecker_cmd_recv96 = (((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv97 = (((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv98 = (((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next16 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv99 = (((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv100 = (((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv101 = (((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv102 = (((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv103 = (((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv104 = (((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next17 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv105 = (((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv106 = (((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv107 = (((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv108 = (((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv109 = (((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv110 = (((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next18 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv111 = (((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv112 = (((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv113 = (((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv114 = (((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv115 = (((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv116 = (((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next19 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv117 = (((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv118 = (((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv119 = (((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv120 = (((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv121 = (((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv122 = (((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next20 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv123 = (((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv124 = (((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv125 = (((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv126 = (((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv127 = (((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv128 = (((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next21 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv129 = (((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv130 = (((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv131 = (((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv132 = (((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv133 = (((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv134 = (((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next22 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv135 = (((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv136 = (((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv137 = (((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv138 = (((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv139 = (((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv140 = (((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next23 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv141 = (((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv142 = (((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv143 = (((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6)); -assign ddrphy_dfitimingschecker_ps3 = ((ddrphy_dfitimingschecker_cnt + 2'd3) * 12'd2500); -assign ddrphy_dfitimingschecker_state3 = {ddrphy_dfi_p3_cs_n, ddrphy_dfi_p3_ras_n, ddrphy_dfi_p3_cas_n, ddrphy_dfi_p3_we_n}; -assign ddrphy_dfitimingschecker_all_banks3 = ((ddrphy_dfitimingschecker_state3 == 1'd1) | ((ddrphy_dfitimingschecker_state3 == 2'd2) & ddrphy_dfi_p3_address[10])); -assign ddrphy_dfitimingschecker_cmd_recv144 = (((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv145 = (((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv146 = (((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next24 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv147 = (((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv148 = (((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv149 = (((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv150 = (((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv151 = (((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv152 = (((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next25 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv153 = (((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv154 = (((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv155 = (((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv156 = (((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv157 = (((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv158 = (((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next26 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv159 = (((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv160 = (((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv161 = (((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv162 = (((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv163 = (((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv164 = (((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next27 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv165 = (((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv166 = (((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv167 = (((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv168 = (((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv169 = (((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv170 = (((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next28 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv171 = (((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv172 = (((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv173 = (((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv174 = (((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv175 = (((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv176 = (((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next29 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv177 = (((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv178 = (((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv179 = (((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv180 = (((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv181 = (((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv182 = (((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next30 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv183 = (((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv184 = (((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv185 = (((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6)); -assign ddrphy_dfitimingschecker_cmd_recv186 = (((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2)); -assign ddrphy_dfitimingschecker_cmd_recv187 = (((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1)); -assign ddrphy_dfitimingschecker_cmd_recv188 = (((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3)); -assign ddrphy_dfitimingschecker_act_next31 = (ddrphy_dfitimingschecker_act_curr + 1'd1); -assign ddrphy_dfitimingschecker_cmd_recv189 = (((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5)); -assign ddrphy_dfitimingschecker_cmd_recv190 = (((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4)); -assign ddrphy_dfitimingschecker_cmd_recv191 = (((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6)); -assign ddrphy_dfitimingschecker_curr_diff = (ddrphy_dfitimingschecker_ps3 - (ddrphy_dfitimingschecker_ref_ps + 23'd7812500)); assign ddrphy_bankmodel0_wraddr = slice_proxy0[24:3]; assign ddrphy_bankmodel0_rdaddr = slice_proxy1[24:3]; always @(*) begin @@ -4315,119 +3783,267 @@ assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en; assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata; assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; always @(*) begin - litedramcore_master_p2_ras_n = 1'd1; + litedramcore_master_p1_cs_n = 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_ras_n = litedramcore_slave_p2_ras_n; + litedramcore_master_p1_cs_n = litedramcore_slave_p1_cs_n; end else begin - litedramcore_master_p2_ras_n = litedramcore_inti_p2_ras_n; + litedramcore_master_p1_cs_n = litedramcore_inti_p1_cs_n; end end always @(*) begin - litedramcore_slave_p2_rddata = 32'd0; + litedramcore_master_p1_ras_n = 1'd1; if (litedramcore_storage[0]) begin - litedramcore_slave_p2_rddata = litedramcore_master_p2_rddata; + litedramcore_master_p1_ras_n = litedramcore_slave_p1_ras_n; end else begin + litedramcore_master_p1_ras_n = litedramcore_inti_p1_ras_n; end end always @(*) begin - litedramcore_master_p2_we_n = 1'd1; + litedramcore_slave_p1_rddata = 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_we_n = litedramcore_slave_p2_we_n; + litedramcore_slave_p1_rddata = litedramcore_master_p1_rddata; end else begin - litedramcore_master_p2_we_n = litedramcore_inti_p2_we_n; end end always @(*) begin - litedramcore_slave_p2_rddata_valid = 1'd0; + litedramcore_master_p1_we_n = 1'd1; if (litedramcore_storage[0]) begin - litedramcore_slave_p2_rddata_valid = litedramcore_master_p2_rddata_valid; + litedramcore_master_p1_we_n = litedramcore_slave_p1_we_n; end else begin + litedramcore_master_p1_we_n = litedramcore_inti_p1_we_n; end end always @(*) begin - litedramcore_master_p2_cke = 1'd0; + litedramcore_slave_p1_rddata_valid = 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cke = litedramcore_slave_p2_cke; + litedramcore_slave_p1_rddata_valid = litedramcore_master_p1_rddata_valid; end else begin - litedramcore_master_p2_cke = litedramcore_inti_p2_cke; end end always @(*) begin - litedramcore_master_p2_odt = 1'd0; + litedramcore_master_p1_cke = 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_odt = litedramcore_slave_p2_odt; + litedramcore_master_p1_cke = litedramcore_slave_p1_cke; end else begin - litedramcore_master_p2_odt = litedramcore_inti_p2_odt; + litedramcore_master_p1_cke = litedramcore_inti_p1_cke; end end always @(*) begin - litedramcore_master_p2_reset_n = 1'd0; + litedramcore_master_p1_odt = 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_reset_n = litedramcore_slave_p2_reset_n; + litedramcore_master_p1_odt = litedramcore_slave_p1_odt; end else begin - litedramcore_master_p2_reset_n = litedramcore_inti_p2_reset_n; + litedramcore_master_p1_odt = litedramcore_inti_p1_odt; end end always @(*) begin - litedramcore_master_p2_act_n = 1'd1; + litedramcore_master_p1_reset_n = 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_act_n = litedramcore_slave_p2_act_n; + litedramcore_master_p1_reset_n = litedramcore_slave_p1_reset_n; end else begin - litedramcore_master_p2_act_n = litedramcore_inti_p2_act_n; + litedramcore_master_p1_reset_n = litedramcore_inti_p1_reset_n; end end always @(*) begin - litedramcore_master_p2_wrdata = 32'd0; + litedramcore_master_p1_act_n = 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata = litedramcore_slave_p2_wrdata; + litedramcore_master_p1_act_n = litedramcore_slave_p1_act_n; end else begin - litedramcore_master_p2_wrdata = litedramcore_inti_p2_wrdata; + litedramcore_master_p1_act_n = litedramcore_inti_p1_act_n; end end always @(*) begin - litedramcore_inti_p3_rddata = 32'd0; + litedramcore_master_p1_wrdata = 32'd0; if (litedramcore_storage[0]) begin + litedramcore_master_p1_wrdata = litedramcore_slave_p1_wrdata; end else begin - litedramcore_inti_p3_rddata = litedramcore_master_p3_rddata; + litedramcore_master_p1_wrdata = litedramcore_inti_p1_wrdata; end end always @(*) begin - litedramcore_master_p2_wrdata_en = 1'd0; + litedramcore_inti_p2_rddata = 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata_en = litedramcore_slave_p2_wrdata_en; end else begin - litedramcore_master_p2_wrdata_en = litedramcore_inti_p2_wrdata_en; + litedramcore_inti_p2_rddata = litedramcore_master_p2_rddata; end end always @(*) begin - litedramcore_inti_p3_rddata_valid = 1'd0; + litedramcore_master_p1_wrdata_en = 1'd0; if (litedramcore_storage[0]) begin + litedramcore_master_p1_wrdata_en = litedramcore_slave_p1_wrdata_en; end else begin - litedramcore_inti_p3_rddata_valid = litedramcore_master_p3_rddata_valid; + litedramcore_master_p1_wrdata_en = litedramcore_inti_p1_wrdata_en; end end always @(*) begin - litedramcore_master_p2_wrdata_mask = 4'd0; + litedramcore_inti_p2_rddata_valid = 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata_mask = litedramcore_slave_p2_wrdata_mask; end else begin - litedramcore_master_p2_wrdata_mask = litedramcore_inti_p2_wrdata_mask; + litedramcore_inti_p2_rddata_valid = litedramcore_master_p2_rddata_valid; end end always @(*) begin - litedramcore_master_p2_rddata_en = 1'd0; + litedramcore_master_p1_wrdata_mask = 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_rddata_en = litedramcore_slave_p2_rddata_en; + litedramcore_master_p1_wrdata_mask = litedramcore_slave_p1_wrdata_mask; end else begin - litedramcore_master_p2_rddata_en = litedramcore_inti_p2_rddata_en; + litedramcore_master_p1_wrdata_mask = litedramcore_inti_p1_wrdata_mask; end end always @(*) begin - litedramcore_master_p3_address = 14'd0; + litedramcore_master_p1_rddata_en = 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_address = litedramcore_slave_p3_address; + litedramcore_master_p1_rddata_en = litedramcore_slave_p1_rddata_en; end else begin - litedramcore_master_p3_address = litedramcore_inti_p3_address; + litedramcore_master_p1_rddata_en = litedramcore_inti_p1_rddata_en; + end +end +always @(*) begin + litedramcore_master_p2_address = 14'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_address = litedramcore_slave_p2_address; + end else begin + litedramcore_master_p2_address = litedramcore_inti_p2_address; + end +end +always @(*) begin + litedramcore_master_p2_bank = 3'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_bank = litedramcore_slave_p2_bank; + end else begin + litedramcore_master_p2_bank = litedramcore_inti_p2_bank; + end +end +always @(*) begin + litedramcore_master_p2_cas_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_cas_n = litedramcore_slave_p2_cas_n; + end else begin + litedramcore_master_p2_cas_n = litedramcore_inti_p2_cas_n; + end +end +always @(*) begin + litedramcore_master_p2_cs_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_cs_n = litedramcore_slave_p2_cs_n; + end else begin + litedramcore_master_p2_cs_n = litedramcore_inti_p2_cs_n; + end +end +always @(*) begin + litedramcore_master_p2_ras_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_ras_n = litedramcore_slave_p2_ras_n; + end else begin + litedramcore_master_p2_ras_n = litedramcore_inti_p2_ras_n; + end +end +always @(*) begin + litedramcore_slave_p2_rddata = 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p2_rddata = litedramcore_master_p2_rddata; + end else begin + end +end +always @(*) begin + litedramcore_master_p2_we_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_we_n = litedramcore_slave_p2_we_n; + end else begin + litedramcore_master_p2_we_n = litedramcore_inti_p2_we_n; + end +end +always @(*) begin + litedramcore_slave_p2_rddata_valid = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p2_rddata_valid = litedramcore_master_p2_rddata_valid; + end else begin + end +end +always @(*) begin + litedramcore_master_p2_cke = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_cke = litedramcore_slave_p2_cke; + end else begin + litedramcore_master_p2_cke = litedramcore_inti_p2_cke; + end +end +always @(*) begin + litedramcore_master_p2_odt = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_odt = litedramcore_slave_p2_odt; + end else begin + litedramcore_master_p2_odt = litedramcore_inti_p2_odt; + end +end +always @(*) begin + litedramcore_master_p2_reset_n = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_reset_n = litedramcore_slave_p2_reset_n; + end else begin + litedramcore_master_p2_reset_n = litedramcore_inti_p2_reset_n; + end +end +always @(*) begin + litedramcore_master_p2_act_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_act_n = litedramcore_slave_p2_act_n; + end else begin + litedramcore_master_p2_act_n = litedramcore_inti_p2_act_n; + end +end +always @(*) begin + litedramcore_master_p2_wrdata = 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_wrdata = litedramcore_slave_p2_wrdata; + end else begin + litedramcore_master_p2_wrdata = litedramcore_inti_p2_wrdata; + end +end +always @(*) begin + litedramcore_inti_p3_rddata = 32'd0; + if (litedramcore_storage[0]) begin + end else begin + litedramcore_inti_p3_rddata = litedramcore_master_p3_rddata; + end +end +always @(*) begin + litedramcore_master_p2_wrdata_en = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_wrdata_en = litedramcore_slave_p2_wrdata_en; + end else begin + litedramcore_master_p2_wrdata_en = litedramcore_inti_p2_wrdata_en; + end +end +always @(*) begin + litedramcore_inti_p3_rddata_valid = 1'd0; + if (litedramcore_storage[0]) begin + end else begin + litedramcore_inti_p3_rddata_valid = litedramcore_master_p3_rddata_valid; + end +end +always @(*) begin + litedramcore_master_p2_wrdata_mask = 4'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_wrdata_mask = litedramcore_slave_p2_wrdata_mask; + end else begin + litedramcore_master_p2_wrdata_mask = litedramcore_inti_p2_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p2_rddata_en = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_rddata_en = litedramcore_slave_p2_rddata_en; + end else begin + litedramcore_master_p2_rddata_en = litedramcore_inti_p2_rddata_en; + end +end +always @(*) begin + litedramcore_master_p3_address = 14'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_address = litedramcore_slave_p3_address; + end else begin + litedramcore_master_p3_address = litedramcore_inti_p3_address; end end always @(*) begin @@ -4726,254 +4342,114 @@ always @(*) begin litedramcore_master_p1_cas_n = litedramcore_inti_p1_cas_n; end end +assign litedramcore_inti_p0_cke = litedramcore_storage[1]; +assign litedramcore_inti_p1_cke = litedramcore_storage[1]; +assign litedramcore_inti_p2_cke = litedramcore_storage[1]; +assign litedramcore_inti_p3_cke = litedramcore_storage[1]; +assign litedramcore_inti_p0_odt = litedramcore_storage[2]; +assign litedramcore_inti_p1_odt = litedramcore_storage[2]; +assign litedramcore_inti_p2_odt = litedramcore_storage[2]; +assign litedramcore_inti_p3_odt = litedramcore_storage[2]; +assign litedramcore_inti_p0_reset_n = litedramcore_storage[3]; +assign litedramcore_inti_p1_reset_n = litedramcore_storage[3]; +assign litedramcore_inti_p2_reset_n = litedramcore_storage[3]; +assign litedramcore_inti_p3_reset_n = litedramcore_storage[3]; always @(*) begin - litedramcore_master_p1_cs_n = 1'd1; - if (litedramcore_storage[0]) begin - litedramcore_master_p1_cs_n = litedramcore_slave_p1_cs_n; + litedramcore_inti_p0_cs_n = 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_cs_n = {1{(~litedramcore_phaseinjector0_command_storage[0])}}; end else begin - litedramcore_master_p1_cs_n = litedramcore_inti_p1_cs_n; + litedramcore_inti_p0_cs_n = {1{1'd1}}; end end always @(*) begin - litedramcore_master_p1_ras_n = 1'd1; - if (litedramcore_storage[0]) begin - litedramcore_master_p1_ras_n = litedramcore_slave_p1_ras_n; + litedramcore_inti_p0_ras_n = 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_ras_n = (~litedramcore_phaseinjector0_command_storage[3]); end else begin - litedramcore_master_p1_ras_n = litedramcore_inti_p1_ras_n; + litedramcore_inti_p0_ras_n = 1'd1; end end always @(*) begin - litedramcore_slave_p1_rddata = 32'd0; - if (litedramcore_storage[0]) begin - litedramcore_slave_p1_rddata = litedramcore_master_p1_rddata; + litedramcore_inti_p0_we_n = 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_we_n = (~litedramcore_phaseinjector0_command_storage[1]); end else begin + litedramcore_inti_p0_we_n = 1'd1; end end always @(*) begin - litedramcore_master_p1_we_n = 1'd1; - if (litedramcore_storage[0]) begin - litedramcore_master_p1_we_n = litedramcore_slave_p1_we_n; + litedramcore_inti_p0_cas_n = 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_cas_n = (~litedramcore_phaseinjector0_command_storage[2]); end else begin - litedramcore_master_p1_we_n = litedramcore_inti_p1_we_n; + litedramcore_inti_p0_cas_n = 1'd1; end end +assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage; +assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage; +assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]); +assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]); +assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; +assign litedramcore_inti_p0_wrdata_mask = 1'd0; always @(*) begin - litedramcore_slave_p1_rddata_valid = 1'd0; - if (litedramcore_storage[0]) begin - litedramcore_slave_p1_rddata_valid = litedramcore_master_p1_rddata_valid; + litedramcore_inti_p1_cs_n = 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_cs_n = {1{(~litedramcore_phaseinjector1_command_storage[0])}}; end else begin + litedramcore_inti_p1_cs_n = {1{1'd1}}; end end always @(*) begin - litedramcore_master_p1_cke = 1'd0; - if (litedramcore_storage[0]) begin - litedramcore_master_p1_cke = litedramcore_slave_p1_cke; + litedramcore_inti_p1_ras_n = 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_ras_n = (~litedramcore_phaseinjector1_command_storage[3]); end else begin - litedramcore_master_p1_cke = litedramcore_inti_p1_cke; + litedramcore_inti_p1_ras_n = 1'd1; end end always @(*) begin - litedramcore_master_p1_odt = 1'd0; - if (litedramcore_storage[0]) begin - litedramcore_master_p1_odt = litedramcore_slave_p1_odt; + litedramcore_inti_p1_we_n = 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_we_n = (~litedramcore_phaseinjector1_command_storage[1]); end else begin - litedramcore_master_p1_odt = litedramcore_inti_p1_odt; + litedramcore_inti_p1_we_n = 1'd1; end end always @(*) begin - litedramcore_master_p1_reset_n = 1'd0; - if (litedramcore_storage[0]) begin - litedramcore_master_p1_reset_n = litedramcore_slave_p1_reset_n; + litedramcore_inti_p1_cas_n = 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_cas_n = (~litedramcore_phaseinjector1_command_storage[2]); end else begin - litedramcore_master_p1_reset_n = litedramcore_inti_p1_reset_n; + litedramcore_inti_p1_cas_n = 1'd1; end end +assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage; +assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage; +assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]); +assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]); +assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; +assign litedramcore_inti_p1_wrdata_mask = 1'd0; always @(*) begin - litedramcore_master_p1_act_n = 1'd1; - if (litedramcore_storage[0]) begin - litedramcore_master_p1_act_n = litedramcore_slave_p1_act_n; + litedramcore_inti_p2_cs_n = 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_inti_p2_cs_n = {1{(~litedramcore_phaseinjector2_command_storage[0])}}; end else begin - litedramcore_master_p1_act_n = litedramcore_inti_p1_act_n; + litedramcore_inti_p2_cs_n = {1{1'd1}}; end end always @(*) begin - litedramcore_master_p1_wrdata = 32'd0; - if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata = litedramcore_slave_p1_wrdata; + litedramcore_inti_p2_ras_n = 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_inti_p2_ras_n = (~litedramcore_phaseinjector2_command_storage[3]); end else begin - litedramcore_master_p1_wrdata = litedramcore_inti_p1_wrdata; + litedramcore_inti_p2_ras_n = 1'd1; end end always @(*) begin - litedramcore_inti_p2_rddata = 32'd0; - if (litedramcore_storage[0]) begin - end else begin - litedramcore_inti_p2_rddata = litedramcore_master_p2_rddata; - end -end -always @(*) begin - litedramcore_master_p1_wrdata_en = 1'd0; - if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata_en = litedramcore_slave_p1_wrdata_en; - end else begin - litedramcore_master_p1_wrdata_en = litedramcore_inti_p1_wrdata_en; - end -end -always @(*) begin - litedramcore_inti_p2_rddata_valid = 1'd0; - if (litedramcore_storage[0]) begin - end else begin - litedramcore_inti_p2_rddata_valid = litedramcore_master_p2_rddata_valid; - end -end -always @(*) begin - litedramcore_master_p1_wrdata_mask = 4'd0; - if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata_mask = litedramcore_slave_p1_wrdata_mask; - end else begin - litedramcore_master_p1_wrdata_mask = litedramcore_inti_p1_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p1_rddata_en = 1'd0; - if (litedramcore_storage[0]) begin - litedramcore_master_p1_rddata_en = litedramcore_slave_p1_rddata_en; - end else begin - litedramcore_master_p1_rddata_en = litedramcore_inti_p1_rddata_en; - end -end -always @(*) begin - litedramcore_master_p2_address = 14'd0; - if (litedramcore_storage[0]) begin - litedramcore_master_p2_address = litedramcore_slave_p2_address; - end else begin - litedramcore_master_p2_address = litedramcore_inti_p2_address; - end -end -always @(*) begin - litedramcore_master_p2_bank = 3'd0; - if (litedramcore_storage[0]) begin - litedramcore_master_p2_bank = litedramcore_slave_p2_bank; - end else begin - litedramcore_master_p2_bank = litedramcore_inti_p2_bank; - end -end -always @(*) begin - litedramcore_master_p2_cas_n = 1'd1; - if (litedramcore_storage[0]) begin - litedramcore_master_p2_cas_n = litedramcore_slave_p2_cas_n; - end else begin - litedramcore_master_p2_cas_n = litedramcore_inti_p2_cas_n; - end -end -always @(*) begin - litedramcore_master_p2_cs_n = 1'd1; - if (litedramcore_storage[0]) begin - litedramcore_master_p2_cs_n = litedramcore_slave_p2_cs_n; - end else begin - litedramcore_master_p2_cs_n = litedramcore_inti_p2_cs_n; - end -end -assign litedramcore_inti_p0_cke = litedramcore_storage[1]; -assign litedramcore_inti_p1_cke = litedramcore_storage[1]; -assign litedramcore_inti_p2_cke = litedramcore_storage[1]; -assign litedramcore_inti_p3_cke = litedramcore_storage[1]; -assign litedramcore_inti_p0_odt = litedramcore_storage[2]; -assign litedramcore_inti_p1_odt = litedramcore_storage[2]; -assign litedramcore_inti_p2_odt = litedramcore_storage[2]; -assign litedramcore_inti_p3_odt = litedramcore_storage[2]; -assign litedramcore_inti_p0_reset_n = litedramcore_storage[3]; -assign litedramcore_inti_p1_reset_n = litedramcore_storage[3]; -assign litedramcore_inti_p2_reset_n = litedramcore_storage[3]; -assign litedramcore_inti_p3_reset_n = litedramcore_storage[3]; -always @(*) begin - litedramcore_inti_p0_ras_n = 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_ras_n = (~litedramcore_phaseinjector0_command_storage[3]); - end else begin - litedramcore_inti_p0_ras_n = 1'd1; - end -end -always @(*) begin - litedramcore_inti_p0_we_n = 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_we_n = (~litedramcore_phaseinjector0_command_storage[1]); - end else begin - litedramcore_inti_p0_we_n = 1'd1; - end -end -always @(*) begin - litedramcore_inti_p0_cas_n = 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_cas_n = (~litedramcore_phaseinjector0_command_storage[2]); - end else begin - litedramcore_inti_p0_cas_n = 1'd1; - end -end -always @(*) begin - litedramcore_inti_p0_cs_n = 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_cs_n = {1{(~litedramcore_phaseinjector0_command_storage[0])}}; - end else begin - litedramcore_inti_p0_cs_n = {1{1'd1}}; - end -end -assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage; -assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage; -assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]); -assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]); -assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; -assign litedramcore_inti_p0_wrdata_mask = 1'd0; -always @(*) begin - litedramcore_inti_p1_ras_n = 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_ras_n = (~litedramcore_phaseinjector1_command_storage[3]); - end else begin - litedramcore_inti_p1_ras_n = 1'd1; - end -end -always @(*) begin - litedramcore_inti_p1_we_n = 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_we_n = (~litedramcore_phaseinjector1_command_storage[1]); - end else begin - litedramcore_inti_p1_we_n = 1'd1; - end -end -always @(*) begin - litedramcore_inti_p1_cas_n = 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_cas_n = (~litedramcore_phaseinjector1_command_storage[2]); - end else begin - litedramcore_inti_p1_cas_n = 1'd1; - end -end -always @(*) begin - litedramcore_inti_p1_cs_n = 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_cs_n = {1{(~litedramcore_phaseinjector1_command_storage[0])}}; - end else begin - litedramcore_inti_p1_cs_n = {1{1'd1}}; - end -end -assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage; -assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage; -assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]); -assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]); -assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; -assign litedramcore_inti_p1_wrdata_mask = 1'd0; -always @(*) begin - litedramcore_inti_p2_ras_n = 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_ras_n = (~litedramcore_phaseinjector2_command_storage[3]); - end else begin - litedramcore_inti_p2_ras_n = 1'd1; - end -end -always @(*) begin - litedramcore_inti_p2_we_n = 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_we_n = (~litedramcore_phaseinjector2_command_storage[1]); + litedramcore_inti_p2_we_n = 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_inti_p2_we_n = (~litedramcore_phaseinjector2_command_storage[1]); end else begin litedramcore_inti_p2_we_n = 1'd1; end @@ -4986,20 +4462,20 @@ always @(*) begin litedramcore_inti_p2_cas_n = 1'd1; end end -always @(*) begin - litedramcore_inti_p2_cs_n = 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_cs_n = {1{(~litedramcore_phaseinjector2_command_storage[0])}}; - end else begin - litedramcore_inti_p2_cs_n = {1{1'd1}}; - end -end assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage; assign litedramcore_inti_p2_bank = litedramcore_phaseinjector2_baddress_storage; assign litedramcore_inti_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[4]); assign litedramcore_inti_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[5]); assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; assign litedramcore_inti_p2_wrdata_mask = 1'd0; +always @(*) begin + litedramcore_inti_p3_cs_n = 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_inti_p3_cs_n = {1{(~litedramcore_phaseinjector3_command_storage[0])}}; + end else begin + litedramcore_inti_p3_cs_n = {1{1'd1}}; + end +end always @(*) begin litedramcore_inti_p3_ras_n = 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin @@ -5024,14 +4500,6 @@ always @(*) begin litedramcore_inti_p3_cas_n = 1'd1; end end -always @(*) begin - litedramcore_inti_p3_cs_n = 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_cs_n = {1{(~litedramcore_phaseinjector3_command_storage[0])}}; - end else begin - litedramcore_inti_p3_cs_n = {1{1'd1}}; - end -end assign litedramcore_inti_p3_address = litedramcore_phaseinjector3_address_storage; assign litedramcore_inti_p3_bank = litedramcore_phaseinjector3_baddress_storage; assign litedramcore_inti_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[4]); @@ -5526,6 +4994,32 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; + case (bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_col_n_addr_sel = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin litedramcore_bankmachine0_cmd_valid = 1'd0; case (bankmachine0_state) @@ -5619,32 +5113,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; - case (bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel = 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin litedramcore_bankmachine0_cmd_payload_cas = 1'd0; case (bankmachine0_state) @@ -5984,33 +5452,7 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; - case (bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel = 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_req_wdata_ready = 1'd0; + litedramcore_bankmachine1_req_wdata_ready = 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -6178,6 +5620,32 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; + case (bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_col_n_addr_sel = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin litedramcore_bankmachine1_row_close = 1'd0; case (bankmachine1_state) @@ -6685,32 +6153,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; - case (bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel = 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin litedramcore_bankmachine2_row_open = 1'd0; case (bankmachine2_state) @@ -6868,6 +6310,32 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; + case (bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_col_n_addr_sel = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; case (bankmachine2_state) @@ -7177,6 +6645,32 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; + case (bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_col_n_addr_sel = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin litedramcore_bankmachine3_refresh_gnt = 1'd0; case (bankmachine3_state) @@ -7296,32 +6790,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; - case (bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel = 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin litedramcore_bankmachine3_cmd_payload_cas = 1'd0; case (bankmachine3_state) @@ -7763,15 +7231,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; + litedramcore_bankmachine4_cmd_valid = 1'd0; case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_valid = 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel = 1'd1; + litedramcore_bankmachine4_cmd_valid = 1'd1; end end 3'd4: begin @@ -7785,22 +7256,31 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_valid = 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine4_cmd_valid = 1'd0; + litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid = 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid = 1'd1; + litedramcore_bankmachine4_row_col_n_addr_sel = 1'd1; end end 3'd4: begin @@ -7814,18 +7294,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid = 1'd1; - end else begin - end - end else begin - end - end - end end endcase end @@ -8296,18 +7764,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; + litedramcore_bankmachine5_refresh_gnt = 1'd0; case (bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel = 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt = 1'd1; + end end 3'd5: begin end @@ -8322,18 +7790,21 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine5_refresh_gnt = 1'd0; + litedramcore_bankmachine5_cmd_valid = 1'd0; case (bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid = 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_valid = 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt = 1'd1; - end end 3'd5: begin end @@ -8344,22 +7815,31 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_valid = 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - litedramcore_bankmachine5_cmd_valid = 1'd0; + litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; case (bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid = 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid = 1'd1; + litedramcore_bankmachine5_row_col_n_addr_sel = 1'd1; end end 3'd4: begin @@ -8373,18 +7853,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid = 1'd1; - end else begin - end - end else begin - end - end - end end endcase end @@ -8741,13 +8209,16 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; + litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; case (bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_col_n_addr_sel = 1'd1; + end end 3'd4: begin end @@ -8760,26 +8231,11 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_is_write = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine6_req_wdata_ready = 1'd0; + litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -8804,7 +8260,45 @@ always @(*) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_req_wdata_ready = litedramcore_bankmachine6_cmd_ready; + litedramcore_bankmachine6_cmd_payload_is_write = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_req_wdata_ready = 1'd0; + case (bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_req_wdata_ready = litedramcore_bankmachine6_cmd_ready; end else begin end end else begin @@ -8921,32 +8415,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; - case (bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel = 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin litedramcore_bankmachine6_row_open = 1'd0; case (bankmachine6_state) @@ -9414,18 +8882,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_refresh_gnt = 1'd0; + litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; case (bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_col_n_addr_sel = 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine7_twtpcon_ready) begin - litedramcore_bankmachine7_refresh_gnt = 1'd1; - end end 3'd5: begin end @@ -9440,21 +8908,18 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine7_cmd_valid = 1'd0; + litedramcore_bankmachine7_refresh_gnt = 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_valid = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_valid = 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine7_twtpcon_ready) begin + litedramcore_bankmachine7_refresh_gnt = 1'd1; + end end 3'd5: begin end @@ -9465,31 +8930,22 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_valid = 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; + litedramcore_bankmachine7_cmd_valid = 1'd0; case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_valid = 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel = 1'd1; + litedramcore_bankmachine7_cmd_valid = 1'd1; end end 3'd4: begin @@ -9503,6 +8959,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_valid = 1'd1; + end else begin + end + end else begin + end + end + end end endcase end @@ -9733,28 +9201,28 @@ always @(*) begin litedramcore_choose_cmd_valids[7] = (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); end assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; -assign litedramcore_choose_cmd_cmd_valid = comb_rhs_array_muxed0; -assign litedramcore_choose_cmd_cmd_payload_a = comb_rhs_array_muxed1; -assign litedramcore_choose_cmd_cmd_payload_ba = comb_rhs_array_muxed2; -assign litedramcore_choose_cmd_cmd_payload_is_read = comb_rhs_array_muxed3; -assign litedramcore_choose_cmd_cmd_payload_is_write = comb_rhs_array_muxed4; -assign litedramcore_choose_cmd_cmd_payload_is_cmd = comb_rhs_array_muxed5; +assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; +assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1; +assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2; +assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; +assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; +assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; always @(*) begin litedramcore_choose_cmd_cmd_payload_cas = 1'd0; if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_cas = comb_t_array_muxed0; + litedramcore_choose_cmd_cmd_payload_cas = t_array_muxed0; end end always @(*) begin litedramcore_choose_cmd_cmd_payload_ras = 1'd0; if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_ras = comb_t_array_muxed1; + litedramcore_choose_cmd_cmd_payload_ras = t_array_muxed1; end end always @(*) begin litedramcore_choose_cmd_cmd_payload_we = 1'd0; if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_we = comb_t_array_muxed2; + litedramcore_choose_cmd_cmd_payload_we = t_array_muxed2; end end always @(*) begin @@ -9842,28 +9310,28 @@ always @(*) begin litedramcore_choose_req_valids[7] = (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); end assign litedramcore_choose_req_request = litedramcore_choose_req_valids; -assign litedramcore_choose_req_cmd_valid = comb_rhs_array_muxed6; -assign litedramcore_choose_req_cmd_payload_a = comb_rhs_array_muxed7; -assign litedramcore_choose_req_cmd_payload_ba = comb_rhs_array_muxed8; -assign litedramcore_choose_req_cmd_payload_is_read = comb_rhs_array_muxed9; -assign litedramcore_choose_req_cmd_payload_is_write = comb_rhs_array_muxed10; -assign litedramcore_choose_req_cmd_payload_is_cmd = comb_rhs_array_muxed11; +assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6; +assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7; +assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8; +assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; +assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; +assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; always @(*) begin litedramcore_choose_req_cmd_payload_cas = 1'd0; if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_cas = comb_t_array_muxed3; + litedramcore_choose_req_cmd_payload_cas = t_array_muxed3; end end always @(*) begin litedramcore_choose_req_cmd_payload_ras = 1'd0; if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_ras = comb_t_array_muxed4; + litedramcore_choose_req_cmd_payload_ras = t_array_muxed4; end end always @(*) begin litedramcore_choose_req_cmd_payload_we = 1'd0; if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_we = comb_t_array_muxed5; + litedramcore_choose_req_cmd_payload_we = t_array_muxed5; end end assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); @@ -10330,44 +9798,44 @@ always @(*) begin end assign roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; assign roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); -assign litedramcore_interface_bank0_addr = comb_rhs_array_muxed12; -assign litedramcore_interface_bank0_we = comb_rhs_array_muxed13; -assign litedramcore_interface_bank0_valid = comb_rhs_array_muxed14; +assign litedramcore_interface_bank0_addr = rhs_array_muxed12; +assign litedramcore_interface_bank0_we = rhs_array_muxed13; +assign litedramcore_interface_bank0_valid = rhs_array_muxed14; assign roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; assign roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock)); -assign litedramcore_interface_bank1_addr = comb_rhs_array_muxed15; -assign litedramcore_interface_bank1_we = comb_rhs_array_muxed16; -assign litedramcore_interface_bank1_valid = comb_rhs_array_muxed17; +assign litedramcore_interface_bank1_addr = rhs_array_muxed15; +assign litedramcore_interface_bank1_we = rhs_array_muxed16; +assign litedramcore_interface_bank1_valid = rhs_array_muxed17; assign roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; assign roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock)); -assign litedramcore_interface_bank2_addr = comb_rhs_array_muxed18; -assign litedramcore_interface_bank2_we = comb_rhs_array_muxed19; -assign litedramcore_interface_bank2_valid = comb_rhs_array_muxed20; +assign litedramcore_interface_bank2_addr = rhs_array_muxed18; +assign litedramcore_interface_bank2_we = rhs_array_muxed19; +assign litedramcore_interface_bank2_valid = rhs_array_muxed20; assign roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; assign roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock)); -assign litedramcore_interface_bank3_addr = comb_rhs_array_muxed21; -assign litedramcore_interface_bank3_we = comb_rhs_array_muxed22; -assign litedramcore_interface_bank3_valid = comb_rhs_array_muxed23; +assign litedramcore_interface_bank3_addr = rhs_array_muxed21; +assign litedramcore_interface_bank3_we = rhs_array_muxed22; +assign litedramcore_interface_bank3_valid = rhs_array_muxed23; assign roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; assign roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock)); -assign litedramcore_interface_bank4_addr = comb_rhs_array_muxed24; -assign litedramcore_interface_bank4_we = comb_rhs_array_muxed25; -assign litedramcore_interface_bank4_valid = comb_rhs_array_muxed26; +assign litedramcore_interface_bank4_addr = rhs_array_muxed24; +assign litedramcore_interface_bank4_we = rhs_array_muxed25; +assign litedramcore_interface_bank4_valid = rhs_array_muxed26; assign roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; assign roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock)); -assign litedramcore_interface_bank5_addr = comb_rhs_array_muxed27; -assign litedramcore_interface_bank5_we = comb_rhs_array_muxed28; -assign litedramcore_interface_bank5_valid = comb_rhs_array_muxed29; +assign litedramcore_interface_bank5_addr = rhs_array_muxed27; +assign litedramcore_interface_bank5_we = rhs_array_muxed28; +assign litedramcore_interface_bank5_valid = rhs_array_muxed29; assign roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; assign roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock)); -assign litedramcore_interface_bank6_addr = comb_rhs_array_muxed30; -assign litedramcore_interface_bank6_we = comb_rhs_array_muxed31; -assign litedramcore_interface_bank6_valid = comb_rhs_array_muxed32; +assign litedramcore_interface_bank6_addr = rhs_array_muxed30; +assign litedramcore_interface_bank6_we = rhs_array_muxed31; +assign litedramcore_interface_bank6_valid = rhs_array_muxed32; assign roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)}; assign roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock)); -assign litedramcore_interface_bank7_addr = comb_rhs_array_muxed33; -assign litedramcore_interface_bank7_we = comb_rhs_array_muxed34; -assign litedramcore_interface_bank7_valid = comb_rhs_array_muxed35; +assign litedramcore_interface_bank7_addr = rhs_array_muxed33; +assign litedramcore_interface_bank7_we = rhs_array_muxed34; +assign litedramcore_interface_bank7_valid = rhs_array_muxed35; assign user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready)); assign user_port_wdata_ready = new_master_wdata_ready2; assign user_port_rdata_valid = new_master_rdata_valid9; @@ -10413,128 +9881,228 @@ assign litedramcore_wishbone_we = wb_bus_we; assign litedramcore_wishbone_cti = wb_bus_cti; assign litedramcore_wishbone_bte = wb_bus_bte; assign wb_bus_err = litedramcore_wishbone_err; -always @(*) begin - csrbank0_sel = 1'd0; - csrbank0_sel = (interface0_bank_bus_adr[13:9] == 2'd2); - if (interface0_bank_bus_adr[0]) begin - csrbank0_sel = 1'd0; - end -end +assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 2'd2); assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd0)); -assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd0)); +assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd0)); +assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd0)); assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd1)); -assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd1)); +assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd1)); +assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd1)); assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; -always @(*) begin - csrbank1_sel = 1'd0; - csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); - if (interface1_bank_bus_adr[0]) begin - csrbank1_sel = 1'd0; - end -end +assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0]; -assign csrbank1_dfii_control0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 1'd0)); -assign csrbank1_dfii_control0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 1'd0)); +assign csrbank1_dfii_control0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 1'd0)); +assign csrbank1_dfii_control0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 1'd0)); assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0]; -assign csrbank1_dfii_pi0_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 1'd1)); -assign csrbank1_dfii_pi0_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 1'd1)); +assign csrbank1_dfii_pi0_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 1'd1)); +assign csrbank1_dfii_pi0_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 1'd1)); assign litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector0_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 2'd2)); -assign litedramcore_phaseinjector0_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 2'd2)); -assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[13:0]; -assign csrbank1_dfii_pi0_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 2'd3)); -assign csrbank1_dfii_pi0_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 2'd3)); +assign litedramcore_phaseinjector0_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 2'd2)); +assign litedramcore_phaseinjector0_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 2'd2)); +assign csrbank1_dfii_pi0_address1_r = interface1_bank_bus_dat_w[5:0]; +assign csrbank1_dfii_pi0_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 2'd3)); +assign csrbank1_dfii_pi0_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 2'd3)); +assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi0_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd4)); +assign csrbank1_dfii_pi0_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd4)); assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0]; -assign csrbank1_dfii_pi0_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 3'd4)); -assign csrbank1_dfii_pi0_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 3'd4)); -assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[31:0]; -assign csrbank1_dfii_pi0_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 3'd5)); -assign csrbank1_dfii_pi0_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 3'd5)); -assign csrbank1_dfii_pi0_rddata_r = interface1_bank_bus_dat_w[31:0]; -assign csrbank1_dfii_pi0_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 3'd6)); -assign csrbank1_dfii_pi0_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 3'd6)); +assign csrbank1_dfii_pi0_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd5)); +assign csrbank1_dfii_pi0_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd5)); +assign csrbank1_dfii_pi0_wrdata3_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi0_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd6)); +assign csrbank1_dfii_pi0_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd6)); +assign csrbank1_dfii_pi0_wrdata2_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi0_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd7)); +assign csrbank1_dfii_pi0_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd7)); +assign csrbank1_dfii_pi0_wrdata1_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi0_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd8)); +assign csrbank1_dfii_pi0_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd8)); +assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi0_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd9)); +assign csrbank1_dfii_pi0_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd9)); +assign csrbank1_dfii_pi0_rddata3_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi0_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd10)); +assign csrbank1_dfii_pi0_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd10)); +assign csrbank1_dfii_pi0_rddata2_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi0_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd11)); +assign csrbank1_dfii_pi0_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd11)); +assign csrbank1_dfii_pi0_rddata1_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi0_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd12)); +assign csrbank1_dfii_pi0_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd12)); +assign csrbank1_dfii_pi0_rddata0_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi0_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd13)); +assign csrbank1_dfii_pi0_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd13)); assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0]; -assign csrbank1_dfii_pi1_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 3'd7)); -assign csrbank1_dfii_pi1_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 3'd7)); +assign csrbank1_dfii_pi1_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd14)); +assign csrbank1_dfii_pi1_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd14)); assign litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector1_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd8)); -assign litedramcore_phaseinjector1_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd8)); -assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[13:0]; -assign csrbank1_dfii_pi1_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd9)); -assign csrbank1_dfii_pi1_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd9)); +assign litedramcore_phaseinjector1_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd15)); +assign litedramcore_phaseinjector1_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd15)); +assign csrbank1_dfii_pi1_address1_r = interface1_bank_bus_dat_w[5:0]; +assign csrbank1_dfii_pi1_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd16)); +assign csrbank1_dfii_pi1_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd16)); +assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi1_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd17)); +assign csrbank1_dfii_pi1_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd17)); assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0]; -assign csrbank1_dfii_pi1_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd10)); -assign csrbank1_dfii_pi1_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd10)); -assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[31:0]; -assign csrbank1_dfii_pi1_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd11)); -assign csrbank1_dfii_pi1_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd11)); -assign csrbank1_dfii_pi1_rddata_r = interface1_bank_bus_dat_w[31:0]; -assign csrbank1_dfii_pi1_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd12)); -assign csrbank1_dfii_pi1_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd12)); +assign csrbank1_dfii_pi1_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd18)); +assign csrbank1_dfii_pi1_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd18)); +assign csrbank1_dfii_pi1_wrdata3_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi1_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd19)); +assign csrbank1_dfii_pi1_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd19)); +assign csrbank1_dfii_pi1_wrdata2_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi1_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd20)); +assign csrbank1_dfii_pi1_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd20)); +assign csrbank1_dfii_pi1_wrdata1_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi1_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd21)); +assign csrbank1_dfii_pi1_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd21)); +assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi1_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd22)); +assign csrbank1_dfii_pi1_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd22)); +assign csrbank1_dfii_pi1_rddata3_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi1_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd23)); +assign csrbank1_dfii_pi1_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd23)); +assign csrbank1_dfii_pi1_rddata2_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi1_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd24)); +assign csrbank1_dfii_pi1_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd24)); +assign csrbank1_dfii_pi1_rddata1_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi1_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd25)); +assign csrbank1_dfii_pi1_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd25)); +assign csrbank1_dfii_pi1_rddata0_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi1_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd26)); +assign csrbank1_dfii_pi1_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd26)); assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0]; -assign csrbank1_dfii_pi2_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd13)); -assign csrbank1_dfii_pi2_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd13)); +assign csrbank1_dfii_pi2_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd27)); +assign csrbank1_dfii_pi2_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd27)); assign litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector2_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd14)); -assign litedramcore_phaseinjector2_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd14)); -assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[13:0]; -assign csrbank1_dfii_pi2_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd15)); -assign csrbank1_dfii_pi2_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd15)); +assign litedramcore_phaseinjector2_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd28)); +assign litedramcore_phaseinjector2_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd28)); +assign csrbank1_dfii_pi2_address1_r = interface1_bank_bus_dat_w[5:0]; +assign csrbank1_dfii_pi2_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd29)); +assign csrbank1_dfii_pi2_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd29)); +assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi2_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd30)); +assign csrbank1_dfii_pi2_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd30)); assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0]; -assign csrbank1_dfii_pi2_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd16)); -assign csrbank1_dfii_pi2_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd16)); -assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[31:0]; -assign csrbank1_dfii_pi2_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd17)); -assign csrbank1_dfii_pi2_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd17)); -assign csrbank1_dfii_pi2_rddata_r = interface1_bank_bus_dat_w[31:0]; -assign csrbank1_dfii_pi2_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd18)); -assign csrbank1_dfii_pi2_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd18)); +assign csrbank1_dfii_pi2_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd31)); +assign csrbank1_dfii_pi2_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd31)); +assign csrbank1_dfii_pi2_wrdata3_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi2_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd32)); +assign csrbank1_dfii_pi2_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd32)); +assign csrbank1_dfii_pi2_wrdata2_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi2_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd33)); +assign csrbank1_dfii_pi2_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd33)); +assign csrbank1_dfii_pi2_wrdata1_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi2_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd34)); +assign csrbank1_dfii_pi2_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd34)); +assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi2_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd35)); +assign csrbank1_dfii_pi2_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd35)); +assign csrbank1_dfii_pi2_rddata3_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi2_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd36)); +assign csrbank1_dfii_pi2_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd36)); +assign csrbank1_dfii_pi2_rddata2_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi2_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd37)); +assign csrbank1_dfii_pi2_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd37)); +assign csrbank1_dfii_pi2_rddata1_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi2_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd38)); +assign csrbank1_dfii_pi2_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd38)); +assign csrbank1_dfii_pi2_rddata0_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi2_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd39)); +assign csrbank1_dfii_pi2_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd39)); assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0]; -assign csrbank1_dfii_pi3_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd19)); -assign csrbank1_dfii_pi3_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd19)); +assign csrbank1_dfii_pi3_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd40)); +assign csrbank1_dfii_pi3_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd40)); assign litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector3_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd20)); -assign litedramcore_phaseinjector3_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd20)); -assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[13:0]; -assign csrbank1_dfii_pi3_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd21)); -assign csrbank1_dfii_pi3_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd21)); +assign litedramcore_phaseinjector3_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd41)); +assign litedramcore_phaseinjector3_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd41)); +assign csrbank1_dfii_pi3_address1_r = interface1_bank_bus_dat_w[5:0]; +assign csrbank1_dfii_pi3_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd42)); +assign csrbank1_dfii_pi3_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd42)); +assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi3_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd43)); +assign csrbank1_dfii_pi3_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd43)); assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0]; -assign csrbank1_dfii_pi3_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd22)); -assign csrbank1_dfii_pi3_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd22)); -assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[31:0]; -assign csrbank1_dfii_pi3_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd23)); -assign csrbank1_dfii_pi3_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd23)); -assign csrbank1_dfii_pi3_rddata_r = interface1_bank_bus_dat_w[31:0]; -assign csrbank1_dfii_pi3_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd24)); -assign csrbank1_dfii_pi3_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd24)); +assign csrbank1_dfii_pi3_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd44)); +assign csrbank1_dfii_pi3_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd44)); +assign csrbank1_dfii_pi3_wrdata3_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi3_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd45)); +assign csrbank1_dfii_pi3_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd45)); +assign csrbank1_dfii_pi3_wrdata2_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi3_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd46)); +assign csrbank1_dfii_pi3_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd46)); +assign csrbank1_dfii_pi3_wrdata1_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi3_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd47)); +assign csrbank1_dfii_pi3_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd47)); +assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi3_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd48)); +assign csrbank1_dfii_pi3_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd48)); +assign csrbank1_dfii_pi3_rddata3_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi3_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd49)); +assign csrbank1_dfii_pi3_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd49)); +assign csrbank1_dfii_pi3_rddata2_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi3_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd50)); +assign csrbank1_dfii_pi3_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd50)); +assign csrbank1_dfii_pi3_rddata1_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi3_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd51)); +assign csrbank1_dfii_pi3_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd51)); +assign csrbank1_dfii_pi3_rddata0_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi3_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd52)); +assign csrbank1_dfii_pi3_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd52)); assign csrbank1_dfii_control0_w = litedramcore_storage[3:0]; assign csrbank1_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; -assign csrbank1_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0]; +assign csrbank1_dfii_pi0_address1_w = litedramcore_phaseinjector0_address_storage[13:8]; +assign csrbank1_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[7:0]; assign csrbank1_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; -assign csrbank1_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0]; -assign csrbank1_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0]; -assign litedramcore_phaseinjector0_we = csrbank1_dfii_pi0_rddata_we; +assign csrbank1_dfii_pi0_wrdata3_w = litedramcore_phaseinjector0_wrdata_storage[31:24]; +assign csrbank1_dfii_pi0_wrdata2_w = litedramcore_phaseinjector0_wrdata_storage[23:16]; +assign csrbank1_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[15:8]; +assign csrbank1_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[7:0]; +assign csrbank1_dfii_pi0_rddata3_w = litedramcore_phaseinjector0_status[31:24]; +assign csrbank1_dfii_pi0_rddata2_w = litedramcore_phaseinjector0_status[23:16]; +assign csrbank1_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_status[15:8]; +assign csrbank1_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_status[7:0]; +assign litedramcore_phaseinjector0_we = csrbank1_dfii_pi0_rddata0_we; assign csrbank1_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0]; -assign csrbank1_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0]; +assign csrbank1_dfii_pi1_address1_w = litedramcore_phaseinjector1_address_storage[13:8]; +assign csrbank1_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[7:0]; assign csrbank1_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; -assign csrbank1_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0]; -assign csrbank1_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0]; -assign litedramcore_phaseinjector1_we = csrbank1_dfii_pi1_rddata_we; +assign csrbank1_dfii_pi1_wrdata3_w = litedramcore_phaseinjector1_wrdata_storage[31:24]; +assign csrbank1_dfii_pi1_wrdata2_w = litedramcore_phaseinjector1_wrdata_storage[23:16]; +assign csrbank1_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[15:8]; +assign csrbank1_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[7:0]; +assign csrbank1_dfii_pi1_rddata3_w = litedramcore_phaseinjector1_status[31:24]; +assign csrbank1_dfii_pi1_rddata2_w = litedramcore_phaseinjector1_status[23:16]; +assign csrbank1_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_status[15:8]; +assign csrbank1_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_status[7:0]; +assign litedramcore_phaseinjector1_we = csrbank1_dfii_pi1_rddata0_we; assign csrbank1_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0]; -assign csrbank1_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0]; +assign csrbank1_dfii_pi2_address1_w = litedramcore_phaseinjector2_address_storage[13:8]; +assign csrbank1_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[7:0]; assign csrbank1_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0]; -assign csrbank1_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0]; -assign csrbank1_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0]; -assign litedramcore_phaseinjector2_we = csrbank1_dfii_pi2_rddata_we; +assign csrbank1_dfii_pi2_wrdata3_w = litedramcore_phaseinjector2_wrdata_storage[31:24]; +assign csrbank1_dfii_pi2_wrdata2_w = litedramcore_phaseinjector2_wrdata_storage[23:16]; +assign csrbank1_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[15:8]; +assign csrbank1_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[7:0]; +assign csrbank1_dfii_pi2_rddata3_w = litedramcore_phaseinjector2_status[31:24]; +assign csrbank1_dfii_pi2_rddata2_w = litedramcore_phaseinjector2_status[23:16]; +assign csrbank1_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_status[15:8]; +assign csrbank1_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_status[7:0]; +assign litedramcore_phaseinjector2_we = csrbank1_dfii_pi2_rddata0_we; assign csrbank1_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0]; -assign csrbank1_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0]; +assign csrbank1_dfii_pi3_address1_w = litedramcore_phaseinjector3_address_storage[13:8]; +assign csrbank1_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[7:0]; assign csrbank1_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0]; -assign csrbank1_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0]; -assign csrbank1_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0]; -assign litedramcore_phaseinjector3_we = csrbank1_dfii_pi3_rddata_we; +assign csrbank1_dfii_pi3_wrdata3_w = litedramcore_phaseinjector3_wrdata_storage[31:24]; +assign csrbank1_dfii_pi3_wrdata2_w = litedramcore_phaseinjector3_wrdata_storage[23:16]; +assign csrbank1_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[15:8]; +assign csrbank1_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[7:0]; +assign csrbank1_dfii_pi3_rddata3_w = litedramcore_phaseinjector3_status[31:24]; +assign csrbank1_dfii_pi3_rddata2_w = litedramcore_phaseinjector3_status[23:16]; +assign csrbank1_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_status[15:8]; +assign csrbank1_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_status[7:0]; +assign litedramcore_phaseinjector3_we = csrbank1_dfii_pi3_rddata0_we; assign adr = litedramcore_adr; assign we = litedramcore_we; assign dat_w = litedramcore_dat_w; @@ -10563,5336 +10131,1252 @@ assign slice_proxy13 = ((ddrphy_bankmodel6_row * 11'd1024) | ddrphy_bankmodel6_r assign slice_proxy14 = ((ddrphy_bankmodel7_row * 11'd1024) | ddrphy_bankmodel7_write_col); assign slice_proxy15 = ((ddrphy_bankmodel7_row * 11'd1024) | ddrphy_bankmodel7_read_col); always @(*) begin - comb_rhs_array_muxed0 = 1'd0; + rhs_array_muxed0 = 1'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin - comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[0]; + rhs_array_muxed0 = litedramcore_choose_cmd_valids[0]; end 1'd1: begin - comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[1]; + rhs_array_muxed0 = litedramcore_choose_cmd_valids[1]; end 2'd2: begin - comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[2]; + rhs_array_muxed0 = litedramcore_choose_cmd_valids[2]; end 2'd3: begin - comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[3]; + rhs_array_muxed0 = litedramcore_choose_cmd_valids[3]; end 3'd4: begin - comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[4]; + rhs_array_muxed0 = litedramcore_choose_cmd_valids[4]; end 3'd5: begin - comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[5]; + rhs_array_muxed0 = litedramcore_choose_cmd_valids[5]; end 3'd6: begin - comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[6]; + rhs_array_muxed0 = litedramcore_choose_cmd_valids[6]; end default: begin - comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[7]; + rhs_array_muxed0 = litedramcore_choose_cmd_valids[7]; end endcase end always @(*) begin - comb_rhs_array_muxed1 = 14'd0; + rhs_array_muxed1 = 14'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin - comb_rhs_array_muxed1 = litedramcore_bankmachine0_cmd_payload_a; + rhs_array_muxed1 = litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - comb_rhs_array_muxed1 = litedramcore_bankmachine1_cmd_payload_a; + rhs_array_muxed1 = litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - comb_rhs_array_muxed1 = litedramcore_bankmachine2_cmd_payload_a; + rhs_array_muxed1 = litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - comb_rhs_array_muxed1 = litedramcore_bankmachine3_cmd_payload_a; + rhs_array_muxed1 = litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - comb_rhs_array_muxed1 = litedramcore_bankmachine4_cmd_payload_a; + rhs_array_muxed1 = litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - comb_rhs_array_muxed1 = litedramcore_bankmachine5_cmd_payload_a; + rhs_array_muxed1 = litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - comb_rhs_array_muxed1 = litedramcore_bankmachine6_cmd_payload_a; + rhs_array_muxed1 = litedramcore_bankmachine6_cmd_payload_a; end default: begin - comb_rhs_array_muxed1 = litedramcore_bankmachine7_cmd_payload_a; + rhs_array_muxed1 = litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin - comb_rhs_array_muxed2 = 3'd0; + rhs_array_muxed2 = 3'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin - comb_rhs_array_muxed2 = litedramcore_bankmachine0_cmd_payload_ba; + rhs_array_muxed2 = litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - comb_rhs_array_muxed2 = litedramcore_bankmachine1_cmd_payload_ba; + rhs_array_muxed2 = litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - comb_rhs_array_muxed2 = litedramcore_bankmachine2_cmd_payload_ba; + rhs_array_muxed2 = litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - comb_rhs_array_muxed2 = litedramcore_bankmachine3_cmd_payload_ba; + rhs_array_muxed2 = litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - comb_rhs_array_muxed2 = litedramcore_bankmachine4_cmd_payload_ba; + rhs_array_muxed2 = litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - comb_rhs_array_muxed2 = litedramcore_bankmachine5_cmd_payload_ba; + rhs_array_muxed2 = litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - comb_rhs_array_muxed2 = litedramcore_bankmachine6_cmd_payload_ba; + rhs_array_muxed2 = litedramcore_bankmachine6_cmd_payload_ba; end default: begin - comb_rhs_array_muxed2 = litedramcore_bankmachine7_cmd_payload_ba; + rhs_array_muxed2 = litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin - comb_rhs_array_muxed3 = 1'd0; + rhs_array_muxed3 = 1'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin - comb_rhs_array_muxed3 = litedramcore_bankmachine0_cmd_payload_is_read; + rhs_array_muxed3 = litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - comb_rhs_array_muxed3 = litedramcore_bankmachine1_cmd_payload_is_read; + rhs_array_muxed3 = litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - comb_rhs_array_muxed3 = litedramcore_bankmachine2_cmd_payload_is_read; + rhs_array_muxed3 = litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - comb_rhs_array_muxed3 = litedramcore_bankmachine3_cmd_payload_is_read; + rhs_array_muxed3 = litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - comb_rhs_array_muxed3 = litedramcore_bankmachine4_cmd_payload_is_read; + rhs_array_muxed3 = litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - comb_rhs_array_muxed3 = litedramcore_bankmachine5_cmd_payload_is_read; + rhs_array_muxed3 = litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - comb_rhs_array_muxed3 = litedramcore_bankmachine6_cmd_payload_is_read; + rhs_array_muxed3 = litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - comb_rhs_array_muxed3 = litedramcore_bankmachine7_cmd_payload_is_read; + rhs_array_muxed3 = litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin - comb_rhs_array_muxed4 = 1'd0; + rhs_array_muxed4 = 1'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin - comb_rhs_array_muxed4 = litedramcore_bankmachine0_cmd_payload_is_write; + rhs_array_muxed4 = litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - comb_rhs_array_muxed4 = litedramcore_bankmachine1_cmd_payload_is_write; + rhs_array_muxed4 = litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - comb_rhs_array_muxed4 = litedramcore_bankmachine2_cmd_payload_is_write; + rhs_array_muxed4 = litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - comb_rhs_array_muxed4 = litedramcore_bankmachine3_cmd_payload_is_write; + rhs_array_muxed4 = litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - comb_rhs_array_muxed4 = litedramcore_bankmachine4_cmd_payload_is_write; + rhs_array_muxed4 = litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - comb_rhs_array_muxed4 = litedramcore_bankmachine5_cmd_payload_is_write; + rhs_array_muxed4 = litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - comb_rhs_array_muxed4 = litedramcore_bankmachine6_cmd_payload_is_write; + rhs_array_muxed4 = litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - comb_rhs_array_muxed4 = litedramcore_bankmachine7_cmd_payload_is_write; + rhs_array_muxed4 = litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin - comb_rhs_array_muxed5 = 1'd0; + rhs_array_muxed5 = 1'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin - comb_rhs_array_muxed5 = litedramcore_bankmachine0_cmd_payload_is_cmd; + rhs_array_muxed5 = litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - comb_rhs_array_muxed5 = litedramcore_bankmachine1_cmd_payload_is_cmd; + rhs_array_muxed5 = litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - comb_rhs_array_muxed5 = litedramcore_bankmachine2_cmd_payload_is_cmd; + rhs_array_muxed5 = litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - comb_rhs_array_muxed5 = litedramcore_bankmachine3_cmd_payload_is_cmd; + rhs_array_muxed5 = litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - comb_rhs_array_muxed5 = litedramcore_bankmachine4_cmd_payload_is_cmd; + rhs_array_muxed5 = litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - comb_rhs_array_muxed5 = litedramcore_bankmachine5_cmd_payload_is_cmd; + rhs_array_muxed5 = litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - comb_rhs_array_muxed5 = litedramcore_bankmachine6_cmd_payload_is_cmd; + rhs_array_muxed5 = litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - comb_rhs_array_muxed5 = litedramcore_bankmachine7_cmd_payload_is_cmd; + rhs_array_muxed5 = litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin - comb_t_array_muxed0 = 1'd0; + t_array_muxed0 = 1'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin - comb_t_array_muxed0 = litedramcore_bankmachine0_cmd_payload_cas; + t_array_muxed0 = litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - comb_t_array_muxed0 = litedramcore_bankmachine1_cmd_payload_cas; + t_array_muxed0 = litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - comb_t_array_muxed0 = litedramcore_bankmachine2_cmd_payload_cas; + t_array_muxed0 = litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - comb_t_array_muxed0 = litedramcore_bankmachine3_cmd_payload_cas; + t_array_muxed0 = litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - comb_t_array_muxed0 = litedramcore_bankmachine4_cmd_payload_cas; + t_array_muxed0 = litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - comb_t_array_muxed0 = litedramcore_bankmachine5_cmd_payload_cas; + t_array_muxed0 = litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - comb_t_array_muxed0 = litedramcore_bankmachine6_cmd_payload_cas; + t_array_muxed0 = litedramcore_bankmachine6_cmd_payload_cas; end default: begin - comb_t_array_muxed0 = litedramcore_bankmachine7_cmd_payload_cas; + t_array_muxed0 = litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin - comb_t_array_muxed1 = 1'd0; + t_array_muxed1 = 1'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin - comb_t_array_muxed1 = litedramcore_bankmachine0_cmd_payload_ras; + t_array_muxed1 = litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - comb_t_array_muxed1 = litedramcore_bankmachine1_cmd_payload_ras; + t_array_muxed1 = litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - comb_t_array_muxed1 = litedramcore_bankmachine2_cmd_payload_ras; + t_array_muxed1 = litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - comb_t_array_muxed1 = litedramcore_bankmachine3_cmd_payload_ras; + t_array_muxed1 = litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - comb_t_array_muxed1 = litedramcore_bankmachine4_cmd_payload_ras; + t_array_muxed1 = litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - comb_t_array_muxed1 = litedramcore_bankmachine5_cmd_payload_ras; + t_array_muxed1 = litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - comb_t_array_muxed1 = litedramcore_bankmachine6_cmd_payload_ras; + t_array_muxed1 = litedramcore_bankmachine6_cmd_payload_ras; end default: begin - comb_t_array_muxed1 = litedramcore_bankmachine7_cmd_payload_ras; + t_array_muxed1 = litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin - comb_t_array_muxed2 = 1'd0; + t_array_muxed2 = 1'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin - comb_t_array_muxed2 = litedramcore_bankmachine0_cmd_payload_we; + t_array_muxed2 = litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - comb_t_array_muxed2 = litedramcore_bankmachine1_cmd_payload_we; + t_array_muxed2 = litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - comb_t_array_muxed2 = litedramcore_bankmachine2_cmd_payload_we; + t_array_muxed2 = litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - comb_t_array_muxed2 = litedramcore_bankmachine3_cmd_payload_we; + t_array_muxed2 = litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - comb_t_array_muxed2 = litedramcore_bankmachine4_cmd_payload_we; + t_array_muxed2 = litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - comb_t_array_muxed2 = litedramcore_bankmachine5_cmd_payload_we; + t_array_muxed2 = litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - comb_t_array_muxed2 = litedramcore_bankmachine6_cmd_payload_we; + t_array_muxed2 = litedramcore_bankmachine6_cmd_payload_we; end default: begin - comb_t_array_muxed2 = litedramcore_bankmachine7_cmd_payload_we; + t_array_muxed2 = litedramcore_bankmachine7_cmd_payload_we; end endcase end always @(*) begin - comb_rhs_array_muxed6 = 1'd0; + rhs_array_muxed6 = 1'd0; case (litedramcore_choose_req_grant) 1'd0: begin - comb_rhs_array_muxed6 = litedramcore_choose_req_valids[0]; + rhs_array_muxed6 = litedramcore_choose_req_valids[0]; end 1'd1: begin - comb_rhs_array_muxed6 = litedramcore_choose_req_valids[1]; + rhs_array_muxed6 = litedramcore_choose_req_valids[1]; end 2'd2: begin - comb_rhs_array_muxed6 = litedramcore_choose_req_valids[2]; + rhs_array_muxed6 = litedramcore_choose_req_valids[2]; end 2'd3: begin - comb_rhs_array_muxed6 = litedramcore_choose_req_valids[3]; + rhs_array_muxed6 = litedramcore_choose_req_valids[3]; end 3'd4: begin - comb_rhs_array_muxed6 = litedramcore_choose_req_valids[4]; + rhs_array_muxed6 = litedramcore_choose_req_valids[4]; end 3'd5: begin - comb_rhs_array_muxed6 = litedramcore_choose_req_valids[5]; + rhs_array_muxed6 = litedramcore_choose_req_valids[5]; end 3'd6: begin - comb_rhs_array_muxed6 = litedramcore_choose_req_valids[6]; + rhs_array_muxed6 = litedramcore_choose_req_valids[6]; end default: begin - comb_rhs_array_muxed6 = litedramcore_choose_req_valids[7]; + rhs_array_muxed6 = litedramcore_choose_req_valids[7]; end endcase end always @(*) begin - comb_rhs_array_muxed7 = 14'd0; + rhs_array_muxed7 = 14'd0; case (litedramcore_choose_req_grant) 1'd0: begin - comb_rhs_array_muxed7 = litedramcore_bankmachine0_cmd_payload_a; + rhs_array_muxed7 = litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - comb_rhs_array_muxed7 = litedramcore_bankmachine1_cmd_payload_a; + rhs_array_muxed7 = litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - comb_rhs_array_muxed7 = litedramcore_bankmachine2_cmd_payload_a; + rhs_array_muxed7 = litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - comb_rhs_array_muxed7 = litedramcore_bankmachine3_cmd_payload_a; + rhs_array_muxed7 = litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - comb_rhs_array_muxed7 = litedramcore_bankmachine4_cmd_payload_a; + rhs_array_muxed7 = litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - comb_rhs_array_muxed7 = litedramcore_bankmachine5_cmd_payload_a; + rhs_array_muxed7 = litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - comb_rhs_array_muxed7 = litedramcore_bankmachine6_cmd_payload_a; + rhs_array_muxed7 = litedramcore_bankmachine6_cmd_payload_a; end default: begin - comb_rhs_array_muxed7 = litedramcore_bankmachine7_cmd_payload_a; + rhs_array_muxed7 = litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin - comb_rhs_array_muxed8 = 3'd0; + rhs_array_muxed8 = 3'd0; case (litedramcore_choose_req_grant) 1'd0: begin - comb_rhs_array_muxed8 = litedramcore_bankmachine0_cmd_payload_ba; + rhs_array_muxed8 = litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - comb_rhs_array_muxed8 = litedramcore_bankmachine1_cmd_payload_ba; + rhs_array_muxed8 = litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - comb_rhs_array_muxed8 = litedramcore_bankmachine2_cmd_payload_ba; + rhs_array_muxed8 = litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - comb_rhs_array_muxed8 = litedramcore_bankmachine3_cmd_payload_ba; + rhs_array_muxed8 = litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - comb_rhs_array_muxed8 = litedramcore_bankmachine4_cmd_payload_ba; + rhs_array_muxed8 = litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - comb_rhs_array_muxed8 = litedramcore_bankmachine5_cmd_payload_ba; + rhs_array_muxed8 = litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - comb_rhs_array_muxed8 = litedramcore_bankmachine6_cmd_payload_ba; + rhs_array_muxed8 = litedramcore_bankmachine6_cmd_payload_ba; end default: begin - comb_rhs_array_muxed8 = litedramcore_bankmachine7_cmd_payload_ba; + rhs_array_muxed8 = litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin - comb_rhs_array_muxed9 = 1'd0; + rhs_array_muxed9 = 1'd0; case (litedramcore_choose_req_grant) 1'd0: begin - comb_rhs_array_muxed9 = litedramcore_bankmachine0_cmd_payload_is_read; + rhs_array_muxed9 = litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - comb_rhs_array_muxed9 = litedramcore_bankmachine1_cmd_payload_is_read; + rhs_array_muxed9 = litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - comb_rhs_array_muxed9 = litedramcore_bankmachine2_cmd_payload_is_read; + rhs_array_muxed9 = litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - comb_rhs_array_muxed9 = litedramcore_bankmachine3_cmd_payload_is_read; + rhs_array_muxed9 = litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - comb_rhs_array_muxed9 = litedramcore_bankmachine4_cmd_payload_is_read; + rhs_array_muxed9 = litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - comb_rhs_array_muxed9 = litedramcore_bankmachine5_cmd_payload_is_read; + rhs_array_muxed9 = litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - comb_rhs_array_muxed9 = litedramcore_bankmachine6_cmd_payload_is_read; + rhs_array_muxed9 = litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - comb_rhs_array_muxed9 = litedramcore_bankmachine7_cmd_payload_is_read; + rhs_array_muxed9 = litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin - comb_rhs_array_muxed10 = 1'd0; + rhs_array_muxed10 = 1'd0; case (litedramcore_choose_req_grant) 1'd0: begin - comb_rhs_array_muxed10 = litedramcore_bankmachine0_cmd_payload_is_write; + rhs_array_muxed10 = litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - comb_rhs_array_muxed10 = litedramcore_bankmachine1_cmd_payload_is_write; + rhs_array_muxed10 = litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - comb_rhs_array_muxed10 = litedramcore_bankmachine2_cmd_payload_is_write; + rhs_array_muxed10 = litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - comb_rhs_array_muxed10 = litedramcore_bankmachine3_cmd_payload_is_write; + rhs_array_muxed10 = litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - comb_rhs_array_muxed10 = litedramcore_bankmachine4_cmd_payload_is_write; + rhs_array_muxed10 = litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - comb_rhs_array_muxed10 = litedramcore_bankmachine5_cmd_payload_is_write; + rhs_array_muxed10 = litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - comb_rhs_array_muxed10 = litedramcore_bankmachine6_cmd_payload_is_write; + rhs_array_muxed10 = litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - comb_rhs_array_muxed10 = litedramcore_bankmachine7_cmd_payload_is_write; + rhs_array_muxed10 = litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin - comb_rhs_array_muxed11 = 1'd0; + rhs_array_muxed11 = 1'd0; case (litedramcore_choose_req_grant) 1'd0: begin - comb_rhs_array_muxed11 = litedramcore_bankmachine0_cmd_payload_is_cmd; + rhs_array_muxed11 = litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - comb_rhs_array_muxed11 = litedramcore_bankmachine1_cmd_payload_is_cmd; + rhs_array_muxed11 = litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - comb_rhs_array_muxed11 = litedramcore_bankmachine2_cmd_payload_is_cmd; + rhs_array_muxed11 = litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - comb_rhs_array_muxed11 = litedramcore_bankmachine3_cmd_payload_is_cmd; + rhs_array_muxed11 = litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - comb_rhs_array_muxed11 = litedramcore_bankmachine4_cmd_payload_is_cmd; + rhs_array_muxed11 = litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - comb_rhs_array_muxed11 = litedramcore_bankmachine5_cmd_payload_is_cmd; + rhs_array_muxed11 = litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - comb_rhs_array_muxed11 = litedramcore_bankmachine6_cmd_payload_is_cmd; + rhs_array_muxed11 = litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - comb_rhs_array_muxed11 = litedramcore_bankmachine7_cmd_payload_is_cmd; + rhs_array_muxed11 = litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin - comb_t_array_muxed3 = 1'd0; + t_array_muxed3 = 1'd0; case (litedramcore_choose_req_grant) 1'd0: begin - comb_t_array_muxed3 = litedramcore_bankmachine0_cmd_payload_cas; + t_array_muxed3 = litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - comb_t_array_muxed3 = litedramcore_bankmachine1_cmd_payload_cas; + t_array_muxed3 = litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - comb_t_array_muxed3 = litedramcore_bankmachine2_cmd_payload_cas; + t_array_muxed3 = litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - comb_t_array_muxed3 = litedramcore_bankmachine3_cmd_payload_cas; + t_array_muxed3 = litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - comb_t_array_muxed3 = litedramcore_bankmachine4_cmd_payload_cas; + t_array_muxed3 = litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - comb_t_array_muxed3 = litedramcore_bankmachine5_cmd_payload_cas; + t_array_muxed3 = litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - comb_t_array_muxed3 = litedramcore_bankmachine6_cmd_payload_cas; + t_array_muxed3 = litedramcore_bankmachine6_cmd_payload_cas; end default: begin - comb_t_array_muxed3 = litedramcore_bankmachine7_cmd_payload_cas; + t_array_muxed3 = litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin - comb_t_array_muxed4 = 1'd0; + t_array_muxed4 = 1'd0; case (litedramcore_choose_req_grant) 1'd0: begin - comb_t_array_muxed4 = litedramcore_bankmachine0_cmd_payload_ras; + t_array_muxed4 = litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - comb_t_array_muxed4 = litedramcore_bankmachine1_cmd_payload_ras; + t_array_muxed4 = litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - comb_t_array_muxed4 = litedramcore_bankmachine2_cmd_payload_ras; + t_array_muxed4 = litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - comb_t_array_muxed4 = litedramcore_bankmachine3_cmd_payload_ras; + t_array_muxed4 = litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - comb_t_array_muxed4 = litedramcore_bankmachine4_cmd_payload_ras; + t_array_muxed4 = litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - comb_t_array_muxed4 = litedramcore_bankmachine5_cmd_payload_ras; + t_array_muxed4 = litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - comb_t_array_muxed4 = litedramcore_bankmachine6_cmd_payload_ras; + t_array_muxed4 = litedramcore_bankmachine6_cmd_payload_ras; end default: begin - comb_t_array_muxed4 = litedramcore_bankmachine7_cmd_payload_ras; + t_array_muxed4 = litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin - comb_t_array_muxed5 = 1'd0; + t_array_muxed5 = 1'd0; case (litedramcore_choose_req_grant) 1'd0: begin - comb_t_array_muxed5 = litedramcore_bankmachine0_cmd_payload_we; + t_array_muxed5 = litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - comb_t_array_muxed5 = litedramcore_bankmachine1_cmd_payload_we; + t_array_muxed5 = litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - comb_t_array_muxed5 = litedramcore_bankmachine2_cmd_payload_we; + t_array_muxed5 = litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - comb_t_array_muxed5 = litedramcore_bankmachine3_cmd_payload_we; + t_array_muxed5 = litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - comb_t_array_muxed5 = litedramcore_bankmachine4_cmd_payload_we; + t_array_muxed5 = litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - comb_t_array_muxed5 = litedramcore_bankmachine5_cmd_payload_we; + t_array_muxed5 = litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - comb_t_array_muxed5 = litedramcore_bankmachine6_cmd_payload_we; + t_array_muxed5 = litedramcore_bankmachine6_cmd_payload_we; end default: begin - comb_t_array_muxed5 = litedramcore_bankmachine7_cmd_payload_we; + t_array_muxed5 = litedramcore_bankmachine7_cmd_payload_we; end endcase end always @(*) begin - comb_rhs_array_muxed12 = 21'd0; + rhs_array_muxed12 = 21'd0; case (roundrobin0_grant) default: begin - comb_rhs_array_muxed12 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed12 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - comb_rhs_array_muxed13 = 1'd0; + rhs_array_muxed13 = 1'd0; case (roundrobin0_grant) default: begin - comb_rhs_array_muxed13 = user_port_cmd_payload_we; + rhs_array_muxed13 = user_port_cmd_payload_we; end endcase end always @(*) begin - comb_rhs_array_muxed14 = 1'd0; + rhs_array_muxed14 = 1'd0; case (roundrobin0_grant) default: begin - comb_rhs_array_muxed14 = (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + rhs_array_muxed14 = (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin - comb_rhs_array_muxed15 = 21'd0; + rhs_array_muxed15 = 21'd0; case (roundrobin1_grant) default: begin - comb_rhs_array_muxed15 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed15 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - comb_rhs_array_muxed16 = 1'd0; + rhs_array_muxed16 = 1'd0; case (roundrobin1_grant) default: begin - comb_rhs_array_muxed16 = user_port_cmd_payload_we; + rhs_array_muxed16 = user_port_cmd_payload_we; end endcase end always @(*) begin - comb_rhs_array_muxed17 = 1'd0; + rhs_array_muxed17 = 1'd0; case (roundrobin1_grant) default: begin - comb_rhs_array_muxed17 = (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + rhs_array_muxed17 = (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin - comb_rhs_array_muxed18 = 21'd0; + rhs_array_muxed18 = 21'd0; case (roundrobin2_grant) default: begin - comb_rhs_array_muxed18 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed18 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - comb_rhs_array_muxed19 = 1'd0; + rhs_array_muxed19 = 1'd0; case (roundrobin2_grant) default: begin - comb_rhs_array_muxed19 = user_port_cmd_payload_we; + rhs_array_muxed19 = user_port_cmd_payload_we; end endcase end always @(*) begin - comb_rhs_array_muxed20 = 1'd0; + rhs_array_muxed20 = 1'd0; case (roundrobin2_grant) default: begin - comb_rhs_array_muxed20 = (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + rhs_array_muxed20 = (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin - comb_rhs_array_muxed21 = 21'd0; + rhs_array_muxed21 = 21'd0; case (roundrobin3_grant) default: begin - comb_rhs_array_muxed21 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed21 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - comb_rhs_array_muxed22 = 1'd0; + rhs_array_muxed22 = 1'd0; case (roundrobin3_grant) default: begin - comb_rhs_array_muxed22 = user_port_cmd_payload_we; + rhs_array_muxed22 = user_port_cmd_payload_we; end endcase end always @(*) begin - comb_rhs_array_muxed23 = 1'd0; + rhs_array_muxed23 = 1'd0; case (roundrobin3_grant) default: begin - comb_rhs_array_muxed23 = (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + rhs_array_muxed23 = (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin - comb_rhs_array_muxed24 = 21'd0; + rhs_array_muxed24 = 21'd0; case (roundrobin4_grant) default: begin - comb_rhs_array_muxed24 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed24 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - comb_rhs_array_muxed25 = 1'd0; + rhs_array_muxed25 = 1'd0; case (roundrobin4_grant) default: begin - comb_rhs_array_muxed25 = user_port_cmd_payload_we; + rhs_array_muxed25 = user_port_cmd_payload_we; end endcase end always @(*) begin - comb_rhs_array_muxed26 = 1'd0; + rhs_array_muxed26 = 1'd0; case (roundrobin4_grant) default: begin - comb_rhs_array_muxed26 = (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + rhs_array_muxed26 = (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin - comb_rhs_array_muxed27 = 21'd0; + rhs_array_muxed27 = 21'd0; case (roundrobin5_grant) default: begin - comb_rhs_array_muxed27 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed27 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - comb_rhs_array_muxed28 = 1'd0; + rhs_array_muxed28 = 1'd0; case (roundrobin5_grant) default: begin - comb_rhs_array_muxed28 = user_port_cmd_payload_we; + rhs_array_muxed28 = user_port_cmd_payload_we; end endcase end always @(*) begin - comb_rhs_array_muxed29 = 1'd0; + rhs_array_muxed29 = 1'd0; case (roundrobin5_grant) default: begin - comb_rhs_array_muxed29 = (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + rhs_array_muxed29 = (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin - comb_rhs_array_muxed30 = 21'd0; + rhs_array_muxed30 = 21'd0; case (roundrobin6_grant) default: begin - comb_rhs_array_muxed30 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed30 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - comb_rhs_array_muxed31 = 1'd0; + rhs_array_muxed31 = 1'd0; case (roundrobin6_grant) default: begin - comb_rhs_array_muxed31 = user_port_cmd_payload_we; + rhs_array_muxed31 = user_port_cmd_payload_we; end endcase end always @(*) begin - comb_rhs_array_muxed32 = 1'd0; + rhs_array_muxed32 = 1'd0; case (roundrobin6_grant) default: begin - comb_rhs_array_muxed32 = (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + rhs_array_muxed32 = (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin - comb_rhs_array_muxed33 = 21'd0; + rhs_array_muxed33 = 21'd0; case (roundrobin7_grant) default: begin - comb_rhs_array_muxed33 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed33 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - comb_rhs_array_muxed34 = 1'd0; + rhs_array_muxed34 = 1'd0; case (roundrobin7_grant) default: begin - comb_rhs_array_muxed34 = user_port_cmd_payload_we; + rhs_array_muxed34 = user_port_cmd_payload_we; end endcase end always @(*) begin - comb_rhs_array_muxed35 = 1'd0; + rhs_array_muxed35 = 1'd0; case (roundrobin7_grant) default: begin - comb_rhs_array_muxed35 = (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed0 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed0 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed0 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed0 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed0 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed1 = 64'd0; - case (ddrphy_dfitimingschecker_act_next0) - 1'd0: begin - sync_basiclowerer_array_muxed1 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed1 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed1 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed1 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed2 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed2 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed2 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed2 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed2 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed3 = 64'd0; - case (ddrphy_dfitimingschecker_act_next1) - 1'd0: begin - sync_basiclowerer_array_muxed3 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed3 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed3 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed3 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed4 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed4 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed4 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed4 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed4 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed5 = 64'd0; - case (ddrphy_dfitimingschecker_act_next2) - 1'd0: begin - sync_basiclowerer_array_muxed5 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed5 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed5 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed5 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed6 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed6 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed6 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed6 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed6 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed7 = 64'd0; - case (ddrphy_dfitimingschecker_act_next3) - 1'd0: begin - sync_basiclowerer_array_muxed7 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed7 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed7 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed7 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed8 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed8 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed8 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed8 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed8 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed9 = 64'd0; - case (ddrphy_dfitimingschecker_act_next4) - 1'd0: begin - sync_basiclowerer_array_muxed9 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed9 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed9 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed9 = ddrphy_dfitimingschecker3; + rhs_array_muxed35 = (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin - sync_basiclowerer_array_muxed10 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) + array_muxed0 = 3'd0; + case (litedramcore_steerer_sel0) 1'd0: begin - sync_basiclowerer_array_muxed10 = ddrphy_dfitimingschecker0; + array_muxed0 = litedramcore_nop_ba[2:0]; end 1'd1: begin - sync_basiclowerer_array_muxed10 = ddrphy_dfitimingschecker1; + array_muxed0 = litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - sync_basiclowerer_array_muxed10 = ddrphy_dfitimingschecker2; + array_muxed0 = litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - sync_basiclowerer_array_muxed10 = ddrphy_dfitimingschecker3; + array_muxed0 = litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - sync_basiclowerer_array_muxed11 = 64'd0; - case (ddrphy_dfitimingschecker_act_next5) + array_muxed1 = 14'd0; + case (litedramcore_steerer_sel0) 1'd0: begin - sync_basiclowerer_array_muxed11 = ddrphy_dfitimingschecker0; + array_muxed1 = litedramcore_nop_a; end 1'd1: begin - sync_basiclowerer_array_muxed11 = ddrphy_dfitimingschecker1; + array_muxed1 = litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - sync_basiclowerer_array_muxed11 = ddrphy_dfitimingschecker2; + array_muxed1 = litedramcore_choose_req_cmd_payload_a; end default: begin - sync_basiclowerer_array_muxed11 = ddrphy_dfitimingschecker3; + array_muxed1 = litedramcore_cmd_payload_a; end endcase end always @(*) begin - sync_basiclowerer_array_muxed12 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) + array_muxed2 = 1'd0; + case (litedramcore_steerer_sel0) 1'd0: begin - sync_basiclowerer_array_muxed12 = ddrphy_dfitimingschecker0; + array_muxed2 = 1'd0; end 1'd1: begin - sync_basiclowerer_array_muxed12 = ddrphy_dfitimingschecker1; + array_muxed2 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - sync_basiclowerer_array_muxed12 = ddrphy_dfitimingschecker2; + array_muxed2 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); end default: begin - sync_basiclowerer_array_muxed12 = ddrphy_dfitimingschecker3; + array_muxed2 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); end endcase end always @(*) begin - sync_basiclowerer_array_muxed13 = 64'd0; - case (ddrphy_dfitimingschecker_act_next6) + array_muxed3 = 1'd0; + case (litedramcore_steerer_sel0) 1'd0: begin - sync_basiclowerer_array_muxed13 = ddrphy_dfitimingschecker0; + array_muxed3 = 1'd0; end 1'd1: begin - sync_basiclowerer_array_muxed13 = ddrphy_dfitimingschecker1; + array_muxed3 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - sync_basiclowerer_array_muxed13 = ddrphy_dfitimingschecker2; + array_muxed3 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); end default: begin - sync_basiclowerer_array_muxed13 = ddrphy_dfitimingschecker3; + array_muxed3 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); end endcase end always @(*) begin - sync_basiclowerer_array_muxed14 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) + array_muxed4 = 1'd0; + case (litedramcore_steerer_sel0) 1'd0: begin - sync_basiclowerer_array_muxed14 = ddrphy_dfitimingschecker0; + array_muxed4 = 1'd0; end 1'd1: begin - sync_basiclowerer_array_muxed14 = ddrphy_dfitimingschecker1; + array_muxed4 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - sync_basiclowerer_array_muxed14 = ddrphy_dfitimingschecker2; + array_muxed4 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); end default: begin - sync_basiclowerer_array_muxed14 = ddrphy_dfitimingschecker3; + array_muxed4 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); end endcase end always @(*) begin - sync_basiclowerer_array_muxed15 = 64'd0; - case (ddrphy_dfitimingschecker_act_next7) + array_muxed5 = 1'd0; + case (litedramcore_steerer_sel0) 1'd0: begin - sync_basiclowerer_array_muxed15 = ddrphy_dfitimingschecker0; + array_muxed5 = 1'd0; end 1'd1: begin - sync_basiclowerer_array_muxed15 = ddrphy_dfitimingschecker1; + array_muxed5 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - sync_basiclowerer_array_muxed15 = ddrphy_dfitimingschecker2; + array_muxed5 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); end default: begin - sync_basiclowerer_array_muxed15 = ddrphy_dfitimingschecker3; + array_muxed5 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - sync_basiclowerer_array_muxed16 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) + array_muxed6 = 1'd0; + case (litedramcore_steerer_sel0) 1'd0: begin - sync_basiclowerer_array_muxed16 = ddrphy_dfitimingschecker0; + array_muxed6 = 1'd0; end 1'd1: begin - sync_basiclowerer_array_muxed16 = ddrphy_dfitimingschecker1; + array_muxed6 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - sync_basiclowerer_array_muxed16 = ddrphy_dfitimingschecker2; + array_muxed6 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); end default: begin - sync_basiclowerer_array_muxed16 = ddrphy_dfitimingschecker3; + array_muxed6 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - sync_basiclowerer_array_muxed17 = 64'd0; - case (ddrphy_dfitimingschecker_act_next8) + array_muxed7 = 3'd0; + case (litedramcore_steerer_sel1) 1'd0: begin - sync_basiclowerer_array_muxed17 = ddrphy_dfitimingschecker0; + array_muxed7 = litedramcore_nop_ba[2:0]; end 1'd1: begin - sync_basiclowerer_array_muxed17 = ddrphy_dfitimingschecker1; + array_muxed7 = litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - sync_basiclowerer_array_muxed17 = ddrphy_dfitimingschecker2; + array_muxed7 = litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - sync_basiclowerer_array_muxed17 = ddrphy_dfitimingschecker3; + array_muxed7 = litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - sync_basiclowerer_array_muxed18 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) + array_muxed8 = 14'd0; + case (litedramcore_steerer_sel1) 1'd0: begin - sync_basiclowerer_array_muxed18 = ddrphy_dfitimingschecker0; + array_muxed8 = litedramcore_nop_a; end 1'd1: begin - sync_basiclowerer_array_muxed18 = ddrphy_dfitimingschecker1; + array_muxed8 = litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - sync_basiclowerer_array_muxed18 = ddrphy_dfitimingschecker2; + array_muxed8 = litedramcore_choose_req_cmd_payload_a; end default: begin - sync_basiclowerer_array_muxed18 = ddrphy_dfitimingschecker3; + array_muxed8 = litedramcore_cmd_payload_a; end endcase end always @(*) begin - sync_basiclowerer_array_muxed19 = 64'd0; - case (ddrphy_dfitimingschecker_act_next9) + array_muxed9 = 1'd0; + case (litedramcore_steerer_sel1) 1'd0: begin - sync_basiclowerer_array_muxed19 = ddrphy_dfitimingschecker0; + array_muxed9 = 1'd0; end 1'd1: begin - sync_basiclowerer_array_muxed19 = ddrphy_dfitimingschecker1; + array_muxed9 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - sync_basiclowerer_array_muxed19 = ddrphy_dfitimingschecker2; + array_muxed9 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); end default: begin - sync_basiclowerer_array_muxed19 = ddrphy_dfitimingschecker3; + array_muxed9 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); end endcase end always @(*) begin - sync_basiclowerer_array_muxed20 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) + array_muxed10 = 1'd0; + case (litedramcore_steerer_sel1) 1'd0: begin - sync_basiclowerer_array_muxed20 = ddrphy_dfitimingschecker0; + array_muxed10 = 1'd0; end 1'd1: begin - sync_basiclowerer_array_muxed20 = ddrphy_dfitimingschecker1; + array_muxed10 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - sync_basiclowerer_array_muxed20 = ddrphy_dfitimingschecker2; + array_muxed10 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); end default: begin - sync_basiclowerer_array_muxed20 = ddrphy_dfitimingschecker3; + array_muxed10 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); end endcase end always @(*) begin - sync_basiclowerer_array_muxed21 = 64'd0; - case (ddrphy_dfitimingschecker_act_next10) + array_muxed11 = 1'd0; + case (litedramcore_steerer_sel1) 1'd0: begin - sync_basiclowerer_array_muxed21 = ddrphy_dfitimingschecker0; + array_muxed11 = 1'd0; end 1'd1: begin - sync_basiclowerer_array_muxed21 = ddrphy_dfitimingschecker1; + array_muxed11 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - sync_basiclowerer_array_muxed21 = ddrphy_dfitimingschecker2; + array_muxed11 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); end default: begin - sync_basiclowerer_array_muxed21 = ddrphy_dfitimingschecker3; + array_muxed11 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); end endcase end always @(*) begin - sync_basiclowerer_array_muxed22 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) + array_muxed12 = 1'd0; + case (litedramcore_steerer_sel1) 1'd0: begin - sync_basiclowerer_array_muxed22 = ddrphy_dfitimingschecker0; + array_muxed12 = 1'd0; end 1'd1: begin - sync_basiclowerer_array_muxed22 = ddrphy_dfitimingschecker1; + array_muxed12 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - sync_basiclowerer_array_muxed22 = ddrphy_dfitimingschecker2; + array_muxed12 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); end default: begin - sync_basiclowerer_array_muxed22 = ddrphy_dfitimingschecker3; + array_muxed12 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - sync_basiclowerer_array_muxed23 = 64'd0; - case (ddrphy_dfitimingschecker_act_next11) + array_muxed13 = 1'd0; + case (litedramcore_steerer_sel1) 1'd0: begin - sync_basiclowerer_array_muxed23 = ddrphy_dfitimingschecker0; + array_muxed13 = 1'd0; end 1'd1: begin - sync_basiclowerer_array_muxed23 = ddrphy_dfitimingschecker1; + array_muxed13 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - sync_basiclowerer_array_muxed23 = ddrphy_dfitimingschecker2; + array_muxed13 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); end default: begin - sync_basiclowerer_array_muxed23 = ddrphy_dfitimingschecker3; + array_muxed13 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - sync_basiclowerer_array_muxed24 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) + array_muxed14 = 3'd0; + case (litedramcore_steerer_sel2) 1'd0: begin - sync_basiclowerer_array_muxed24 = ddrphy_dfitimingschecker0; + array_muxed14 = litedramcore_nop_ba[2:0]; end 1'd1: begin - sync_basiclowerer_array_muxed24 = ddrphy_dfitimingschecker1; + array_muxed14 = litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - sync_basiclowerer_array_muxed24 = ddrphy_dfitimingschecker2; + array_muxed14 = litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - sync_basiclowerer_array_muxed24 = ddrphy_dfitimingschecker3; + array_muxed14 = litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - sync_basiclowerer_array_muxed25 = 64'd0; - case (ddrphy_dfitimingschecker_act_next12) + array_muxed15 = 14'd0; + case (litedramcore_steerer_sel2) 1'd0: begin - sync_basiclowerer_array_muxed25 = ddrphy_dfitimingschecker0; + array_muxed15 = litedramcore_nop_a; end 1'd1: begin - sync_basiclowerer_array_muxed25 = ddrphy_dfitimingschecker1; + array_muxed15 = litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - sync_basiclowerer_array_muxed25 = ddrphy_dfitimingschecker2; + array_muxed15 = litedramcore_choose_req_cmd_payload_a; end default: begin - sync_basiclowerer_array_muxed25 = ddrphy_dfitimingschecker3; + array_muxed15 = litedramcore_cmd_payload_a; end endcase end always @(*) begin - sync_basiclowerer_array_muxed26 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) + array_muxed16 = 1'd0; + case (litedramcore_steerer_sel2) 1'd0: begin - sync_basiclowerer_array_muxed26 = ddrphy_dfitimingschecker0; + array_muxed16 = 1'd0; end 1'd1: begin - sync_basiclowerer_array_muxed26 = ddrphy_dfitimingschecker1; + array_muxed16 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - sync_basiclowerer_array_muxed26 = ddrphy_dfitimingschecker2; + array_muxed16 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); end default: begin - sync_basiclowerer_array_muxed26 = ddrphy_dfitimingschecker3; + array_muxed16 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); end endcase end always @(*) begin - sync_basiclowerer_array_muxed27 = 64'd0; - case (ddrphy_dfitimingschecker_act_next13) + array_muxed17 = 1'd0; + case (litedramcore_steerer_sel2) 1'd0: begin - sync_basiclowerer_array_muxed27 = ddrphy_dfitimingschecker0; + array_muxed17 = 1'd0; end 1'd1: begin - sync_basiclowerer_array_muxed27 = ddrphy_dfitimingschecker1; + array_muxed17 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - sync_basiclowerer_array_muxed27 = ddrphy_dfitimingschecker2; + array_muxed17 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); end default: begin - sync_basiclowerer_array_muxed27 = ddrphy_dfitimingschecker3; + array_muxed17 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); end endcase end always @(*) begin - sync_basiclowerer_array_muxed28 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed28 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed28 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed28 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed28 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed29 = 64'd0; - case (ddrphy_dfitimingschecker_act_next14) - 1'd0: begin - sync_basiclowerer_array_muxed29 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed29 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed29 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed29 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed30 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed30 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed30 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed30 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed30 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed31 = 64'd0; - case (ddrphy_dfitimingschecker_act_next15) - 1'd0: begin - sync_basiclowerer_array_muxed31 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed31 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed31 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed31 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed32 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed32 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed32 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed32 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed32 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed33 = 64'd0; - case (ddrphy_dfitimingschecker_act_next16) - 1'd0: begin - sync_basiclowerer_array_muxed33 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed33 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed33 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed33 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed34 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed34 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed34 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed34 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed34 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed35 = 64'd0; - case (ddrphy_dfitimingschecker_act_next17) - 1'd0: begin - sync_basiclowerer_array_muxed35 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed35 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed35 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed35 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed36 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed36 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed36 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed36 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed36 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed37 = 64'd0; - case (ddrphy_dfitimingschecker_act_next18) - 1'd0: begin - sync_basiclowerer_array_muxed37 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed37 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed37 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed37 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed38 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed38 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed38 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed38 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed38 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed39 = 64'd0; - case (ddrphy_dfitimingschecker_act_next19) - 1'd0: begin - sync_basiclowerer_array_muxed39 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed39 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed39 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed39 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed40 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed40 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed40 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed40 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed40 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed41 = 64'd0; - case (ddrphy_dfitimingschecker_act_next20) - 1'd0: begin - sync_basiclowerer_array_muxed41 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed41 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed41 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed41 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed42 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed42 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed42 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed42 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed42 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed43 = 64'd0; - case (ddrphy_dfitimingschecker_act_next21) - 1'd0: begin - sync_basiclowerer_array_muxed43 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed43 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed43 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed43 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed44 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed44 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed44 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed44 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed44 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed45 = 64'd0; - case (ddrphy_dfitimingschecker_act_next22) - 1'd0: begin - sync_basiclowerer_array_muxed45 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed45 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed45 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed45 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed46 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed46 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed46 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed46 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed46 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed47 = 64'd0; - case (ddrphy_dfitimingschecker_act_next23) - 1'd0: begin - sync_basiclowerer_array_muxed47 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed47 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed47 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed47 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed48 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed48 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed48 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed48 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed48 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed49 = 64'd0; - case (ddrphy_dfitimingschecker_act_next24) - 1'd0: begin - sync_basiclowerer_array_muxed49 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed49 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed49 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed49 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed50 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed50 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed50 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed50 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed50 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed51 = 64'd0; - case (ddrphy_dfitimingschecker_act_next25) - 1'd0: begin - sync_basiclowerer_array_muxed51 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed51 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed51 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed51 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed52 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed52 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed52 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed52 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed52 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed53 = 64'd0; - case (ddrphy_dfitimingschecker_act_next26) - 1'd0: begin - sync_basiclowerer_array_muxed53 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed53 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed53 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed53 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed54 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed54 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed54 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed54 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed54 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed55 = 64'd0; - case (ddrphy_dfitimingschecker_act_next27) - 1'd0: begin - sync_basiclowerer_array_muxed55 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed55 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed55 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed55 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed56 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed56 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed56 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed56 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed56 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed57 = 64'd0; - case (ddrphy_dfitimingschecker_act_next28) - 1'd0: begin - sync_basiclowerer_array_muxed57 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed57 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed57 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed57 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed58 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed58 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed58 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed58 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed58 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed59 = 64'd0; - case (ddrphy_dfitimingschecker_act_next29) - 1'd0: begin - sync_basiclowerer_array_muxed59 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed59 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed59 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed59 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed60 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed60 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed60 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed60 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed60 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed61 = 64'd0; - case (ddrphy_dfitimingschecker_act_next30) - 1'd0: begin - sync_basiclowerer_array_muxed61 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed61 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed61 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed61 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed62 = 64'd0; - case (ddrphy_dfitimingschecker_act_curr) - 1'd0: begin - sync_basiclowerer_array_muxed62 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed62 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed62 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed62 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_basiclowerer_array_muxed63 = 64'd0; - case (ddrphy_dfitimingschecker_act_next31) - 1'd0: begin - sync_basiclowerer_array_muxed63 = ddrphy_dfitimingschecker0; - end - 1'd1: begin - sync_basiclowerer_array_muxed63 = ddrphy_dfitimingschecker1; - end - 2'd2: begin - sync_basiclowerer_array_muxed63 = ddrphy_dfitimingschecker2; - end - default: begin - sync_basiclowerer_array_muxed63 = ddrphy_dfitimingschecker3; - end - endcase -end -always @(*) begin - sync_rhs_array_muxed0 = 3'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - sync_rhs_array_muxed0 = litedramcore_nop_ba[2:0]; - end - 1'd1: begin - sync_rhs_array_muxed0 = litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - sync_rhs_array_muxed0 = litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - sync_rhs_array_muxed0 = litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - sync_rhs_array_muxed1 = 14'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - sync_rhs_array_muxed1 = litedramcore_nop_a; - end - 1'd1: begin - sync_rhs_array_muxed1 = litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - sync_rhs_array_muxed1 = litedramcore_choose_req_cmd_payload_a; - end - default: begin - sync_rhs_array_muxed1 = litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - sync_rhs_array_muxed2 = 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - sync_rhs_array_muxed2 = 1'd0; - end - 1'd1: begin - sync_rhs_array_muxed2 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - sync_rhs_array_muxed2 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - sync_rhs_array_muxed2 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - sync_rhs_array_muxed3 = 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - sync_rhs_array_muxed3 = 1'd0; - end - 1'd1: begin - sync_rhs_array_muxed3 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - sync_rhs_array_muxed3 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - sync_rhs_array_muxed3 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - sync_rhs_array_muxed4 = 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - sync_rhs_array_muxed4 = 1'd0; - end - 1'd1: begin - sync_rhs_array_muxed4 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - sync_rhs_array_muxed4 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - sync_rhs_array_muxed4 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - sync_rhs_array_muxed5 = 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - sync_rhs_array_muxed5 = 1'd0; - end - 1'd1: begin - sync_rhs_array_muxed5 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - sync_rhs_array_muxed5 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - sync_rhs_array_muxed5 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - sync_rhs_array_muxed6 = 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - sync_rhs_array_muxed6 = 1'd0; - end - 1'd1: begin - sync_rhs_array_muxed6 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - sync_rhs_array_muxed6 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - sync_rhs_array_muxed6 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - sync_rhs_array_muxed7 = 3'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - sync_rhs_array_muxed7 = litedramcore_nop_ba[2:0]; - end - 1'd1: begin - sync_rhs_array_muxed7 = litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - sync_rhs_array_muxed7 = litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - sync_rhs_array_muxed7 = litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - sync_rhs_array_muxed8 = 14'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - sync_rhs_array_muxed8 = litedramcore_nop_a; - end - 1'd1: begin - sync_rhs_array_muxed8 = litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - sync_rhs_array_muxed8 = litedramcore_choose_req_cmd_payload_a; - end - default: begin - sync_rhs_array_muxed8 = litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - sync_rhs_array_muxed9 = 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - sync_rhs_array_muxed9 = 1'd0; - end - 1'd1: begin - sync_rhs_array_muxed9 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - sync_rhs_array_muxed9 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - sync_rhs_array_muxed9 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - sync_rhs_array_muxed10 = 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - sync_rhs_array_muxed10 = 1'd0; - end - 1'd1: begin - sync_rhs_array_muxed10 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - sync_rhs_array_muxed10 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - sync_rhs_array_muxed10 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - sync_rhs_array_muxed11 = 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - sync_rhs_array_muxed11 = 1'd0; - end - 1'd1: begin - sync_rhs_array_muxed11 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - sync_rhs_array_muxed11 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - sync_rhs_array_muxed11 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - sync_rhs_array_muxed12 = 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - sync_rhs_array_muxed12 = 1'd0; - end - 1'd1: begin - sync_rhs_array_muxed12 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - sync_rhs_array_muxed12 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - sync_rhs_array_muxed12 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - sync_rhs_array_muxed13 = 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - sync_rhs_array_muxed13 = 1'd0; - end - 1'd1: begin - sync_rhs_array_muxed13 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - sync_rhs_array_muxed13 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - sync_rhs_array_muxed13 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - sync_rhs_array_muxed14 = 3'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - sync_rhs_array_muxed14 = litedramcore_nop_ba[2:0]; - end - 1'd1: begin - sync_rhs_array_muxed14 = litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - sync_rhs_array_muxed14 = litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - sync_rhs_array_muxed14 = litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - sync_rhs_array_muxed15 = 14'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - sync_rhs_array_muxed15 = litedramcore_nop_a; - end - 1'd1: begin - sync_rhs_array_muxed15 = litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - sync_rhs_array_muxed15 = litedramcore_choose_req_cmd_payload_a; - end - default: begin - sync_rhs_array_muxed15 = litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - sync_rhs_array_muxed16 = 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - sync_rhs_array_muxed16 = 1'd0; - end - 1'd1: begin - sync_rhs_array_muxed16 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - sync_rhs_array_muxed16 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - sync_rhs_array_muxed16 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - sync_rhs_array_muxed17 = 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - sync_rhs_array_muxed17 = 1'd0; - end - 1'd1: begin - sync_rhs_array_muxed17 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - sync_rhs_array_muxed17 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - sync_rhs_array_muxed17 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - sync_rhs_array_muxed18 = 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - sync_rhs_array_muxed18 = 1'd0; - end - 1'd1: begin - sync_rhs_array_muxed18 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - sync_rhs_array_muxed18 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - sync_rhs_array_muxed18 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - sync_rhs_array_muxed19 = 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - sync_rhs_array_muxed19 = 1'd0; - end - 1'd1: begin - sync_rhs_array_muxed19 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - sync_rhs_array_muxed19 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - sync_rhs_array_muxed19 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - sync_rhs_array_muxed20 = 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - sync_rhs_array_muxed20 = 1'd0; - end - 1'd1: begin - sync_rhs_array_muxed20 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - sync_rhs_array_muxed20 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - sync_rhs_array_muxed20 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - sync_rhs_array_muxed21 = 3'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - sync_rhs_array_muxed21 = litedramcore_nop_ba[2:0]; - end - 1'd1: begin - sync_rhs_array_muxed21 = litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - sync_rhs_array_muxed21 = litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - sync_rhs_array_muxed21 = litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - sync_rhs_array_muxed22 = 14'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - sync_rhs_array_muxed22 = litedramcore_nop_a; - end - 1'd1: begin - sync_rhs_array_muxed22 = litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - sync_rhs_array_muxed22 = litedramcore_choose_req_cmd_payload_a; - end - default: begin - sync_rhs_array_muxed22 = litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - sync_rhs_array_muxed23 = 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - sync_rhs_array_muxed23 = 1'd0; - end - 1'd1: begin - sync_rhs_array_muxed23 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - sync_rhs_array_muxed23 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - sync_rhs_array_muxed23 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - sync_rhs_array_muxed24 = 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - sync_rhs_array_muxed24 = 1'd0; - end - 1'd1: begin - sync_rhs_array_muxed24 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - sync_rhs_array_muxed24 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - sync_rhs_array_muxed24 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - sync_rhs_array_muxed25 = 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - sync_rhs_array_muxed25 = 1'd0; - end - 1'd1: begin - sync_rhs_array_muxed25 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - sync_rhs_array_muxed25 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - sync_rhs_array_muxed25 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - sync_rhs_array_muxed26 = 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - sync_rhs_array_muxed26 = 1'd0; - end - 1'd1: begin - sync_rhs_array_muxed26 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - sync_rhs_array_muxed26 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - sync_rhs_array_muxed26 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - sync_rhs_array_muxed27 = 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - sync_rhs_array_muxed27 = 1'd0; - end - 1'd1: begin - sync_rhs_array_muxed27 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - sync_rhs_array_muxed27 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - sync_rhs_array_muxed27 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase -end - -always @(posedge por_clk) begin - int_rst <= 1'd0; -end - -always @(posedge sys_clk) begin - state <= next_state; - ddrphy_new_bank_write0 <= ddrphy_bank_write0; - ddrphy_new_bank_write_col0 <= ddrphy_bank_write_col0; - ddrphy_new_bank_write1 <= ddrphy_new_bank_write0; - ddrphy_new_bank_write_col1 <= ddrphy_new_bank_write_col0; - ddrphy_new_bank_write2 <= ddrphy_bank_write1; - ddrphy_new_bank_write_col2 <= ddrphy_bank_write_col1; - ddrphy_new_bank_write3 <= ddrphy_new_bank_write2; - ddrphy_new_bank_write_col3 <= ddrphy_new_bank_write_col2; - ddrphy_new_bank_write4 <= ddrphy_bank_write2; - ddrphy_new_bank_write_col4 <= ddrphy_bank_write_col2; - ddrphy_new_bank_write5 <= ddrphy_new_bank_write4; - ddrphy_new_bank_write_col5 <= ddrphy_new_bank_write_col4; - ddrphy_new_bank_write6 <= ddrphy_bank_write3; - ddrphy_new_bank_write_col6 <= ddrphy_bank_write_col3; - ddrphy_new_bank_write7 <= ddrphy_new_bank_write6; - ddrphy_new_bank_write_col7 <= ddrphy_new_bank_write_col6; - ddrphy_new_bank_write8 <= ddrphy_bank_write4; - ddrphy_new_bank_write_col8 <= ddrphy_bank_write_col4; - ddrphy_new_bank_write9 <= ddrphy_new_bank_write8; - ddrphy_new_bank_write_col9 <= ddrphy_new_bank_write_col8; - ddrphy_new_bank_write10 <= ddrphy_bank_write5; - ddrphy_new_bank_write_col10 <= ddrphy_bank_write_col5; - ddrphy_new_bank_write11 <= ddrphy_new_bank_write10; - ddrphy_new_bank_write_col11 <= ddrphy_new_bank_write_col10; - ddrphy_new_bank_write12 <= ddrphy_bank_write6; - ddrphy_new_bank_write_col12 <= ddrphy_bank_write_col6; - ddrphy_new_bank_write13 <= ddrphy_new_bank_write12; - ddrphy_new_bank_write_col13 <= ddrphy_new_bank_write_col12; - ddrphy_new_bank_write14 <= ddrphy_bank_write7; - ddrphy_new_bank_write_col14 <= ddrphy_bank_write_col7; - ddrphy_new_bank_write15 <= ddrphy_new_bank_write14; - ddrphy_new_bank_write_col15 <= ddrphy_new_bank_write_col14; - ddrphy_new_banks_read0 <= ddrphy_banks_read; - ddrphy_new_banks_read_data0 <= ddrphy_banks_read_data; - ddrphy_new_banks_read1 <= ddrphy_new_banks_read0; - ddrphy_new_banks_read_data1 <= ddrphy_new_banks_read_data0; - ddrphy_new_banks_read2 <= ddrphy_new_banks_read1; - ddrphy_new_banks_read_data2 <= ddrphy_new_banks_read_data1; - ddrphy_new_banks_read3 <= ddrphy_new_banks_read2; - ddrphy_new_banks_read_data3 <= ddrphy_new_banks_read_data2; - ddrphy_new_banks_read4 <= ddrphy_new_banks_read3; - ddrphy_new_banks_read_data4 <= ddrphy_new_banks_read_data3; - ddrphy_new_banks_read5 <= ddrphy_new_banks_read4; - ddrphy_new_banks_read_data5 <= ddrphy_new_banks_read_data4; - ddrphy_new_banks_read6 <= ddrphy_new_banks_read5; - ddrphy_new_banks_read_data6 <= ddrphy_new_banks_read_data5; - ddrphy_new_banks_read7 <= ddrphy_new_banks_read6; - ddrphy_new_banks_read_data7 <= ddrphy_new_banks_read_data6; - ddrphy_new_banks_read8 <= ddrphy_new_banks_read7; - ddrphy_new_banks_read_data8 <= ddrphy_new_banks_read_data7; - ddrphy_dfitimingschecker_cnt <= (ddrphy_dfitimingschecker_cnt + 3'd4); - if (((ddrphy_dfitimingschecker_cmd_recv0 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv0 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv0 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv0) begin - ddrphy_dfitimingschecker_dfitimingschecker0 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv1 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv1) begin - ddrphy_dfitimingschecker_dfitimingschecker1 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv2 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv2 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv2 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv2 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker5 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv2) begin - ddrphy_dfitimingschecker_dfitimingschecker2 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state0; - end - if ((ddrphy_dfitimingschecker_cmd_recv2 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed0 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0); - end - if ((ddrphy_dfitimingschecker_cmd_recv2 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed1 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv2) begin - sync_t_array_muxed0 = ddrphy_dfitimingschecker_ps0; - case (ddrphy_dfitimingschecker_act_next0) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed0; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed0; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed0; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed0; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next0; - end - if (((ddrphy_dfitimingschecker_cmd_recv3 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv3 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv3 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv3 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv3) begin - ddrphy_dfitimingschecker_dfitimingschecker3 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv4 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv4 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv4 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv4) begin - ddrphy_dfitimingschecker_dfitimingschecker4 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state0; - end - if (ddrphy_dfitimingschecker_cmd_recv5) begin - ddrphy_dfitimingschecker_dfitimingschecker5 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv6 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv6 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv6 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv6) begin - ddrphy_dfitimingschecker_dfitimingschecker6 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv7 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv7) begin - ddrphy_dfitimingschecker_dfitimingschecker7 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv8 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv8 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv8 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv8 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker11 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv8) begin - ddrphy_dfitimingschecker_dfitimingschecker8 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state0; - end - if ((ddrphy_dfitimingschecker_cmd_recv8 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed2 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1); - end - if ((ddrphy_dfitimingschecker_cmd_recv8 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed3 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv8) begin - sync_t_array_muxed1 = ddrphy_dfitimingschecker_ps0; - case (ddrphy_dfitimingschecker_act_next1) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed1; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed1; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed1; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed1; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next1; - end - if (((ddrphy_dfitimingschecker_cmd_recv9 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv9 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv9 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv9 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv9) begin - ddrphy_dfitimingschecker_dfitimingschecker9 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv10 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv10 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv10 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv10) begin - ddrphy_dfitimingschecker_dfitimingschecker10 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state0; - end - if (ddrphy_dfitimingschecker_cmd_recv11) begin - ddrphy_dfitimingschecker_dfitimingschecker11 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv12 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv12 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv12 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv12) begin - ddrphy_dfitimingschecker_dfitimingschecker12 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv13 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv13) begin - ddrphy_dfitimingschecker_dfitimingschecker13 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv14 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv14 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv14 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv14 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker17 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv14) begin - ddrphy_dfitimingschecker_dfitimingschecker14 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state0; - end - if ((ddrphy_dfitimingschecker_cmd_recv14 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed4 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2); - end - if ((ddrphy_dfitimingschecker_cmd_recv14 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed5 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv14) begin - sync_t_array_muxed2 = ddrphy_dfitimingschecker_ps0; - case (ddrphy_dfitimingschecker_act_next2) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed2; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed2; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed2; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed2; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next2; - end - if (((ddrphy_dfitimingschecker_cmd_recv15 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv15 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv15 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv15 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv15) begin - ddrphy_dfitimingschecker_dfitimingschecker15 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv16 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv16 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv16 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv16) begin - ddrphy_dfitimingschecker_dfitimingschecker16 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state0; - end - if (ddrphy_dfitimingschecker_cmd_recv17) begin - ddrphy_dfitimingschecker_dfitimingschecker17 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv18 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv18 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv18 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv18) begin - ddrphy_dfitimingschecker_dfitimingschecker18 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv19 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv19) begin - ddrphy_dfitimingschecker_dfitimingschecker19 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv20 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv20 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv20 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv20 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker23 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv20) begin - ddrphy_dfitimingschecker_dfitimingschecker20 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state0; - end - if ((ddrphy_dfitimingschecker_cmd_recv20 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed6 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3); - end - if ((ddrphy_dfitimingschecker_cmd_recv20 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed7 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv20) begin - sync_t_array_muxed3 = ddrphy_dfitimingschecker_ps0; - case (ddrphy_dfitimingschecker_act_next3) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed3; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed3; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed3; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed3; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next3; - end - if (((ddrphy_dfitimingschecker_cmd_recv21 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv21 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv21 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv21 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv21) begin - ddrphy_dfitimingschecker_dfitimingschecker21 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv22 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv22 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv22 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv22) begin - ddrphy_dfitimingschecker_dfitimingschecker22 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state0; - end - if (ddrphy_dfitimingschecker_cmd_recv23) begin - ddrphy_dfitimingschecker_dfitimingschecker23 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv24 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv24 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv24 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv24) begin - ddrphy_dfitimingschecker_dfitimingschecker24 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv25 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv25) begin - ddrphy_dfitimingschecker_dfitimingschecker25 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv26 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv26 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv26 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv26 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker29 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv26) begin - ddrphy_dfitimingschecker_dfitimingschecker26 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state0; - end - if ((ddrphy_dfitimingschecker_cmd_recv26 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed8 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4); - end - if ((ddrphy_dfitimingschecker_cmd_recv26 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed9 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv26) begin - sync_t_array_muxed4 = ddrphy_dfitimingschecker_ps0; - case (ddrphy_dfitimingschecker_act_next4) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed4; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed4; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed4; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed4; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next4; - end - if (((ddrphy_dfitimingschecker_cmd_recv27 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv27 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv27 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv27 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv27) begin - ddrphy_dfitimingschecker_dfitimingschecker27 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv28 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv28 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv28 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv28) begin - ddrphy_dfitimingschecker_dfitimingschecker28 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state0; - end - if (ddrphy_dfitimingschecker_cmd_recv29) begin - ddrphy_dfitimingschecker_dfitimingschecker29 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv30 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv30 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv30 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv30) begin - ddrphy_dfitimingschecker_dfitimingschecker30 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv31 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv31) begin - ddrphy_dfitimingschecker_dfitimingschecker31 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv32 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv32 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv32 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv32 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker35 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv32) begin - ddrphy_dfitimingschecker_dfitimingschecker32 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state0; - end - if ((ddrphy_dfitimingschecker_cmd_recv32 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed10 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5); - end - if ((ddrphy_dfitimingschecker_cmd_recv32 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed11 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv32) begin - sync_t_array_muxed5 = ddrphy_dfitimingschecker_ps0; - case (ddrphy_dfitimingschecker_act_next5) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed5; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed5; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed5; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed5; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next5; - end - if (((ddrphy_dfitimingschecker_cmd_recv33 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv33 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv33 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv33 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv33) begin - ddrphy_dfitimingschecker_dfitimingschecker33 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv34 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv34 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv34 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv34) begin - ddrphy_dfitimingschecker_dfitimingschecker34 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state0; - end - if (ddrphy_dfitimingschecker_cmd_recv35) begin - ddrphy_dfitimingschecker_dfitimingschecker35 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv36 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv36 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv36 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv36) begin - ddrphy_dfitimingschecker_dfitimingschecker36 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv37 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv37) begin - ddrphy_dfitimingschecker_dfitimingschecker37 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv38 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv38 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv38 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv38 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker41 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv38) begin - ddrphy_dfitimingschecker_dfitimingschecker38 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state0; - end - if ((ddrphy_dfitimingschecker_cmd_recv38 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed12 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6); - end - if ((ddrphy_dfitimingschecker_cmd_recv38 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed13 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv38) begin - sync_t_array_muxed6 = ddrphy_dfitimingschecker_ps0; - case (ddrphy_dfitimingschecker_act_next6) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed6; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed6; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed6; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed6; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next6; - end - if (((ddrphy_dfitimingschecker_cmd_recv39 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv39 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv39 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv39 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv39) begin - ddrphy_dfitimingschecker_dfitimingschecker39 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv40 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv40 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv40 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv40) begin - ddrphy_dfitimingschecker_dfitimingschecker40 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state0; - end - if (ddrphy_dfitimingschecker_cmd_recv41) begin - ddrphy_dfitimingschecker_dfitimingschecker41 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv42 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv42 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv42 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv42) begin - ddrphy_dfitimingschecker_dfitimingschecker42 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv43 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv43) begin - ddrphy_dfitimingschecker_dfitimingschecker43 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv44 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv44 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv44 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv44 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker47 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv44) begin - ddrphy_dfitimingschecker_dfitimingschecker44 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state0; - end - if ((ddrphy_dfitimingschecker_cmd_recv44 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed14 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7); - end - if ((ddrphy_dfitimingschecker_cmd_recv44 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed15 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv44) begin - sync_t_array_muxed7 = ddrphy_dfitimingschecker_ps0; - case (ddrphy_dfitimingschecker_act_next7) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed7; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed7; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed7; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed7; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next7; - end - if (((ddrphy_dfitimingschecker_cmd_recv45 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv45 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv45 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv45 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv45) begin - ddrphy_dfitimingschecker_dfitimingschecker45 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv46 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv46 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv46 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv46) begin - ddrphy_dfitimingschecker_dfitimingschecker46 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state0; - end - if (ddrphy_dfitimingschecker_cmd_recv47) begin - ddrphy_dfitimingschecker_dfitimingschecker47 <= ddrphy_dfitimingschecker_ps0; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state0; - end - if (((ddrphy_dfitimingschecker_cmd_recv48 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv48 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv48 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv48) begin - ddrphy_dfitimingschecker_dfitimingschecker0 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv49 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv49) begin - ddrphy_dfitimingschecker_dfitimingschecker1 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv50 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv50 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv50 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv50 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker5 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv50) begin - ddrphy_dfitimingschecker_dfitimingschecker2 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state1; - end - if ((ddrphy_dfitimingschecker_cmd_recv50 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed16 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0); - end - if ((ddrphy_dfitimingschecker_cmd_recv50 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed17 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv50) begin - sync_t_array_muxed8 = ddrphy_dfitimingschecker_ps1; - case (ddrphy_dfitimingschecker_act_next8) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed8; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed8; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed8; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed8; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next8; - end - if (((ddrphy_dfitimingschecker_cmd_recv51 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv51 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv51 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv51 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv51) begin - ddrphy_dfitimingschecker_dfitimingschecker3 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv52 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv52 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv52 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv52) begin - ddrphy_dfitimingschecker_dfitimingschecker4 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state1; - end - if (ddrphy_dfitimingschecker_cmd_recv53) begin - ddrphy_dfitimingschecker_dfitimingschecker5 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv54 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv54 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv54 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv54) begin - ddrphy_dfitimingschecker_dfitimingschecker6 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv55 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv55) begin - ddrphy_dfitimingschecker_dfitimingschecker7 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv56 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv56 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv56 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv56 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker11 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv56) begin - ddrphy_dfitimingschecker_dfitimingschecker8 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state1; - end - if ((ddrphy_dfitimingschecker_cmd_recv56 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed18 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1); - end - if ((ddrphy_dfitimingschecker_cmd_recv56 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed19 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv56) begin - sync_t_array_muxed9 = ddrphy_dfitimingschecker_ps1; - case (ddrphy_dfitimingschecker_act_next9) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed9; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed9; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed9; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed9; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next9; - end - if (((ddrphy_dfitimingschecker_cmd_recv57 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv57 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv57 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv57 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv57) begin - ddrphy_dfitimingschecker_dfitimingschecker9 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv58 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv58 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv58 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv58) begin - ddrphy_dfitimingschecker_dfitimingschecker10 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state1; - end - if (ddrphy_dfitimingschecker_cmd_recv59) begin - ddrphy_dfitimingschecker_dfitimingschecker11 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv60 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv60 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv60 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv60) begin - ddrphy_dfitimingschecker_dfitimingschecker12 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv61 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv61) begin - ddrphy_dfitimingschecker_dfitimingschecker13 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv62 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv62 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv62 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv62 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker17 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv62) begin - ddrphy_dfitimingschecker_dfitimingschecker14 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state1; - end - if ((ddrphy_dfitimingschecker_cmd_recv62 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed20 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2); - end - if ((ddrphy_dfitimingschecker_cmd_recv62 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed21 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv62) begin - sync_t_array_muxed10 = ddrphy_dfitimingschecker_ps1; - case (ddrphy_dfitimingschecker_act_next10) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed10; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed10; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed10; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed10; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next10; - end - if (((ddrphy_dfitimingschecker_cmd_recv63 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv63 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv63 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv63 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv63) begin - ddrphy_dfitimingschecker_dfitimingschecker15 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv64 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv64 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv64 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv64) begin - ddrphy_dfitimingschecker_dfitimingschecker16 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state1; - end - if (ddrphy_dfitimingschecker_cmd_recv65) begin - ddrphy_dfitimingschecker_dfitimingschecker17 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv66 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv66 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv66 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv66) begin - ddrphy_dfitimingschecker_dfitimingschecker18 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv67 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv67) begin - ddrphy_dfitimingschecker_dfitimingschecker19 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv68 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv68 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv68 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv68 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker23 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv68) begin - ddrphy_dfitimingschecker_dfitimingschecker20 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state1; - end - if ((ddrphy_dfitimingschecker_cmd_recv68 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed22 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3); - end - if ((ddrphy_dfitimingschecker_cmd_recv68 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed23 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv68) begin - sync_t_array_muxed11 = ddrphy_dfitimingschecker_ps1; - case (ddrphy_dfitimingschecker_act_next11) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed11; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed11; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed11; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed11; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next11; - end - if (((ddrphy_dfitimingschecker_cmd_recv69 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv69 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv69 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv69 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv69) begin - ddrphy_dfitimingschecker_dfitimingschecker21 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv70 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv70 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv70 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv70) begin - ddrphy_dfitimingschecker_dfitimingschecker22 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state1; - end - if (ddrphy_dfitimingschecker_cmd_recv71) begin - ddrphy_dfitimingschecker_dfitimingschecker23 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv72 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv72 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv72 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv72) begin - ddrphy_dfitimingschecker_dfitimingschecker24 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv73 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv73) begin - ddrphy_dfitimingschecker_dfitimingschecker25 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv74 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv74 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv74 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv74 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker29 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv74) begin - ddrphy_dfitimingschecker_dfitimingschecker26 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state1; - end - if ((ddrphy_dfitimingschecker_cmd_recv74 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed24 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4); - end - if ((ddrphy_dfitimingschecker_cmd_recv74 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed25 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv74) begin - sync_t_array_muxed12 = ddrphy_dfitimingschecker_ps1; - case (ddrphy_dfitimingschecker_act_next12) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed12; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed12; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed12; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed12; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next12; - end - if (((ddrphy_dfitimingschecker_cmd_recv75 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv75 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv75 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv75 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv75) begin - ddrphy_dfitimingschecker_dfitimingschecker27 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv76 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv76 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv76 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv76) begin - ddrphy_dfitimingschecker_dfitimingschecker28 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state1; - end - if (ddrphy_dfitimingschecker_cmd_recv77) begin - ddrphy_dfitimingschecker_dfitimingschecker29 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv78 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv78 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv78 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv78) begin - ddrphy_dfitimingschecker_dfitimingschecker30 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv79 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv79) begin - ddrphy_dfitimingschecker_dfitimingschecker31 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv80 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv80 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv80 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv80 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker35 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv80) begin - ddrphy_dfitimingschecker_dfitimingschecker32 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state1; - end - if ((ddrphy_dfitimingschecker_cmd_recv80 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed26 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5); - end - if ((ddrphy_dfitimingschecker_cmd_recv80 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed27 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv80) begin - sync_t_array_muxed13 = ddrphy_dfitimingschecker_ps1; - case (ddrphy_dfitimingschecker_act_next13) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed13; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed13; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed13; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed13; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next13; - end - if (((ddrphy_dfitimingschecker_cmd_recv81 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv81 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv81 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv81 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv81) begin - ddrphy_dfitimingschecker_dfitimingschecker33 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv82 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv82 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv82 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv82) begin - ddrphy_dfitimingschecker_dfitimingschecker34 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state1; - end - if (ddrphy_dfitimingschecker_cmd_recv83) begin - ddrphy_dfitimingschecker_dfitimingschecker35 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv84 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv84 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv84 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv84) begin - ddrphy_dfitimingschecker_dfitimingschecker36 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv85 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv85) begin - ddrphy_dfitimingschecker_dfitimingschecker37 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv86 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv86 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv86 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv86 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker41 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv86) begin - ddrphy_dfitimingschecker_dfitimingschecker38 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state1; - end - if ((ddrphy_dfitimingschecker_cmd_recv86 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed28 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6); - end - if ((ddrphy_dfitimingschecker_cmd_recv86 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed29 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv86) begin - sync_t_array_muxed14 = ddrphy_dfitimingschecker_ps1; - case (ddrphy_dfitimingschecker_act_next14) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed14; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed14; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed14; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed14; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next14; - end - if (((ddrphy_dfitimingschecker_cmd_recv87 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv87 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv87 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv87 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv87) begin - ddrphy_dfitimingschecker_dfitimingschecker39 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv88 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv88 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv88 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv88) begin - ddrphy_dfitimingschecker_dfitimingschecker40 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state1; - end - if (ddrphy_dfitimingschecker_cmd_recv89) begin - ddrphy_dfitimingschecker_dfitimingschecker41 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv90 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv90 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv90 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv90) begin - ddrphy_dfitimingschecker_dfitimingschecker42 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv91 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv91) begin - ddrphy_dfitimingschecker_dfitimingschecker43 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv92 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv92 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv92 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv92 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker47 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv92) begin - ddrphy_dfitimingschecker_dfitimingschecker44 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state1; - end - if ((ddrphy_dfitimingschecker_cmd_recv92 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed30 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7); - end - if ((ddrphy_dfitimingschecker_cmd_recv92 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed31 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv92) begin - sync_t_array_muxed15 = ddrphy_dfitimingschecker_ps1; - case (ddrphy_dfitimingschecker_act_next15) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed15; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed15; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed15; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed15; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next15; - end - if (((ddrphy_dfitimingschecker_cmd_recv93 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv93 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv93 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv93 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv93) begin - ddrphy_dfitimingschecker_dfitimingschecker45 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv94 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv94 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv94 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv94) begin - ddrphy_dfitimingschecker_dfitimingschecker46 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state1; - end - if (ddrphy_dfitimingschecker_cmd_recv95) begin - ddrphy_dfitimingschecker_dfitimingschecker47 <= ddrphy_dfitimingschecker_ps1; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state1; - end - if (((ddrphy_dfitimingschecker_cmd_recv96 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv96 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv96 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv96) begin - ddrphy_dfitimingschecker_dfitimingschecker0 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv97 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv97) begin - ddrphy_dfitimingschecker_dfitimingschecker1 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv98 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv98 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv98 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv98 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker5 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv98) begin - ddrphy_dfitimingschecker_dfitimingschecker2 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state2; - end - if ((ddrphy_dfitimingschecker_cmd_recv98 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed32 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0); - end - if ((ddrphy_dfitimingschecker_cmd_recv98 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed33 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv98) begin - sync_t_array_muxed16 = ddrphy_dfitimingschecker_ps2; - case (ddrphy_dfitimingschecker_act_next16) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed16; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed16; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed16; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed16; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next16; - end - if (((ddrphy_dfitimingschecker_cmd_recv99 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv99 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv99 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv99 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv99) begin - ddrphy_dfitimingschecker_dfitimingschecker3 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv100 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv100 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv100 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv100) begin - ddrphy_dfitimingschecker_dfitimingschecker4 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state2; - end - if (ddrphy_dfitimingschecker_cmd_recv101) begin - ddrphy_dfitimingschecker_dfitimingschecker5 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv102 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv102 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv102 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv102) begin - ddrphy_dfitimingschecker_dfitimingschecker6 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv103 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv103) begin - ddrphy_dfitimingschecker_dfitimingschecker7 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv104 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv104 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv104 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv104 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker11 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv104) begin - ddrphy_dfitimingschecker_dfitimingschecker8 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state2; - end - if ((ddrphy_dfitimingschecker_cmd_recv104 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed34 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1); - end - if ((ddrphy_dfitimingschecker_cmd_recv104 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed35 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv104) begin - sync_t_array_muxed17 = ddrphy_dfitimingschecker_ps2; - case (ddrphy_dfitimingschecker_act_next17) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed17; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed17; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed17; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed17; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next17; - end - if (((ddrphy_dfitimingschecker_cmd_recv105 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv105 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv105 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv105 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv105) begin - ddrphy_dfitimingschecker_dfitimingschecker9 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv106 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv106 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv106 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv106) begin - ddrphy_dfitimingschecker_dfitimingschecker10 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state2; - end - if (ddrphy_dfitimingschecker_cmd_recv107) begin - ddrphy_dfitimingschecker_dfitimingschecker11 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv108 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv108 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv108 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv108) begin - ddrphy_dfitimingschecker_dfitimingschecker12 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv109 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv109) begin - ddrphy_dfitimingschecker_dfitimingschecker13 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv110 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv110 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv110 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv110 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker17 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv110) begin - ddrphy_dfitimingschecker_dfitimingschecker14 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state2; - end - if ((ddrphy_dfitimingschecker_cmd_recv110 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed36 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2); - end - if ((ddrphy_dfitimingschecker_cmd_recv110 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed37 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv110) begin - sync_t_array_muxed18 = ddrphy_dfitimingschecker_ps2; - case (ddrphy_dfitimingschecker_act_next18) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed18; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed18; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed18; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed18; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next18; - end - if (((ddrphy_dfitimingschecker_cmd_recv111 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv111 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv111 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv111 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv111) begin - ddrphy_dfitimingschecker_dfitimingschecker15 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv112 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv112 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv112 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv112) begin - ddrphy_dfitimingschecker_dfitimingschecker16 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state2; - end - if (ddrphy_dfitimingschecker_cmd_recv113) begin - ddrphy_dfitimingschecker_dfitimingschecker17 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv114 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv114 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv114 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv114) begin - ddrphy_dfitimingschecker_dfitimingschecker18 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv115 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv115) begin - ddrphy_dfitimingschecker_dfitimingschecker19 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv116 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv116 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv116 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv116 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker23 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv116) begin - ddrphy_dfitimingschecker_dfitimingschecker20 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state2; - end - if ((ddrphy_dfitimingschecker_cmd_recv116 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed38 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3); - end - if ((ddrphy_dfitimingschecker_cmd_recv116 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed39 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv116) begin - sync_t_array_muxed19 = ddrphy_dfitimingschecker_ps2; - case (ddrphy_dfitimingschecker_act_next19) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed19; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed19; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed19; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed19; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next19; - end - if (((ddrphy_dfitimingschecker_cmd_recv117 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv117 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv117 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv117 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv117) begin - ddrphy_dfitimingschecker_dfitimingschecker21 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv118 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv118 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv118 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv118) begin - ddrphy_dfitimingschecker_dfitimingschecker22 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state2; - end - if (ddrphy_dfitimingschecker_cmd_recv119) begin - ddrphy_dfitimingschecker_dfitimingschecker23 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv120 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv120 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv120 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv120) begin - ddrphy_dfitimingschecker_dfitimingschecker24 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv121 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv121) begin - ddrphy_dfitimingschecker_dfitimingschecker25 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv122 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv122 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv122 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv122 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker29 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv122) begin - ddrphy_dfitimingschecker_dfitimingschecker26 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state2; - end - if ((ddrphy_dfitimingschecker_cmd_recv122 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed40 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4); - end - if ((ddrphy_dfitimingschecker_cmd_recv122 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed41 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv122) begin - sync_t_array_muxed20 = ddrphy_dfitimingschecker_ps2; - case (ddrphy_dfitimingschecker_act_next20) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed20; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed20; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed20; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed20; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next20; - end - if (((ddrphy_dfitimingschecker_cmd_recv123 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv123 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv123 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv123 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv123) begin - ddrphy_dfitimingschecker_dfitimingschecker27 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv124 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv124 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv124 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv124) begin - ddrphy_dfitimingschecker_dfitimingschecker28 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state2; - end - if (ddrphy_dfitimingschecker_cmd_recv125) begin - ddrphy_dfitimingschecker_dfitimingschecker29 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv126 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv126 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv126 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv126) begin - ddrphy_dfitimingschecker_dfitimingschecker30 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv127 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv127) begin - ddrphy_dfitimingschecker_dfitimingschecker31 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv128 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv128 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv128 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv128 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker35 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv128) begin - ddrphy_dfitimingschecker_dfitimingschecker32 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state2; - end - if ((ddrphy_dfitimingschecker_cmd_recv128 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed42 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5); - end - if ((ddrphy_dfitimingschecker_cmd_recv128 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed43 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv128) begin - sync_t_array_muxed21 = ddrphy_dfitimingschecker_ps2; - case (ddrphy_dfitimingschecker_act_next21) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed21; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed21; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed21; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed21; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next21; - end - if (((ddrphy_dfitimingschecker_cmd_recv129 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv129 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv129 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv129 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv129) begin - ddrphy_dfitimingschecker_dfitimingschecker33 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv130 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv130 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv130 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv130) begin - ddrphy_dfitimingschecker_dfitimingschecker34 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state2; - end - if (ddrphy_dfitimingschecker_cmd_recv131) begin - ddrphy_dfitimingschecker_dfitimingschecker35 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv132 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv132 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv132 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv132) begin - ddrphy_dfitimingschecker_dfitimingschecker36 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv133 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv133) begin - ddrphy_dfitimingschecker_dfitimingschecker37 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv134 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv134 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv134 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv134 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker41 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv134) begin - ddrphy_dfitimingschecker_dfitimingschecker38 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state2; - end - if ((ddrphy_dfitimingschecker_cmd_recv134 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed44 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6); - end - if ((ddrphy_dfitimingschecker_cmd_recv134 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed45 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv134) begin - sync_t_array_muxed22 = ddrphy_dfitimingschecker_ps2; - case (ddrphy_dfitimingschecker_act_next22) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed22; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed22; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed22; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed22; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next22; - end - if (((ddrphy_dfitimingschecker_cmd_recv135 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv135 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv135 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv135 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv135) begin - ddrphy_dfitimingschecker_dfitimingschecker39 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv136 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv136 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv136 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv136) begin - ddrphy_dfitimingschecker_dfitimingschecker40 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state2; - end - if (ddrphy_dfitimingschecker_cmd_recv137) begin - ddrphy_dfitimingschecker_dfitimingschecker41 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv138 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv138 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv138 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv138) begin - ddrphy_dfitimingschecker_dfitimingschecker42 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv139 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv139) begin - ddrphy_dfitimingschecker_dfitimingschecker43 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv140 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv140 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv140 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv140 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker47 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv140) begin - ddrphy_dfitimingschecker_dfitimingschecker44 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state2; - end - if ((ddrphy_dfitimingschecker_cmd_recv140 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed46 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7); - end - if ((ddrphy_dfitimingschecker_cmd_recv140 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed47 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv140) begin - sync_t_array_muxed23 = ddrphy_dfitimingschecker_ps2; - case (ddrphy_dfitimingschecker_act_next23) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed23; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed23; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed23; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed23; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next23; - end - if (((ddrphy_dfitimingschecker_cmd_recv141 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv141 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv141 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv141 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv141) begin - ddrphy_dfitimingschecker_dfitimingschecker45 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv142 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv142 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv142 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv142) begin - ddrphy_dfitimingschecker_dfitimingschecker46 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state2; - end - if (ddrphy_dfitimingschecker_cmd_recv143) begin - ddrphy_dfitimingschecker_dfitimingschecker47 <= ddrphy_dfitimingschecker_ps2; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state2; - end - if (((ddrphy_dfitimingschecker_cmd_recv144 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv144 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv144 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv144) begin - ddrphy_dfitimingschecker_dfitimingschecker0 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv145 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv145) begin - ddrphy_dfitimingschecker_dfitimingschecker1 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv146 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv146 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv146 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv146 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker5 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv146) begin - ddrphy_dfitimingschecker_dfitimingschecker2 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state3; - end - if ((ddrphy_dfitimingschecker_cmd_recv146 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed48 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0); - end - if ((ddrphy_dfitimingschecker_cmd_recv146 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed49 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv146) begin - sync_t_array_muxed24 = ddrphy_dfitimingschecker_ps3; - case (ddrphy_dfitimingschecker_act_next24) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed24; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed24; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed24; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed24; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next24; - end - if (((ddrphy_dfitimingschecker_cmd_recv147 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv147 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv147 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv147 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv147) begin - ddrphy_dfitimingschecker_dfitimingschecker3 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv148 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv148 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0); - end - if (((ddrphy_dfitimingschecker_cmd_recv148 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0); - end - if (ddrphy_dfitimingschecker_cmd_recv148) begin - ddrphy_dfitimingschecker_dfitimingschecker4 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state3; - end - if (ddrphy_dfitimingschecker_cmd_recv149) begin - ddrphy_dfitimingschecker_dfitimingschecker5 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv150 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv150 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv150 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv150) begin - ddrphy_dfitimingschecker_dfitimingschecker6 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv151 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv151) begin - ddrphy_dfitimingschecker_dfitimingschecker7 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv152 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv152 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv152 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv152 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker11 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv152) begin - ddrphy_dfitimingschecker_dfitimingschecker8 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state3; - end - if ((ddrphy_dfitimingschecker_cmd_recv152 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed50 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1); - end - if ((ddrphy_dfitimingschecker_cmd_recv152 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed51 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv152) begin - sync_t_array_muxed25 = ddrphy_dfitimingschecker_ps3; - case (ddrphy_dfitimingschecker_act_next25) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed25; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed25; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed25; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed25; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next25; - end - if (((ddrphy_dfitimingschecker_cmd_recv153 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv153 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv153 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv153 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv153) begin - ddrphy_dfitimingschecker_dfitimingschecker9 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv154 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv154 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1); - end - if (((ddrphy_dfitimingschecker_cmd_recv154 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1); - end - if (ddrphy_dfitimingschecker_cmd_recv154) begin - ddrphy_dfitimingschecker_dfitimingschecker10 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state3; - end - if (ddrphy_dfitimingschecker_cmd_recv155) begin - ddrphy_dfitimingschecker_dfitimingschecker11 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv156 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv156 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv156 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv156) begin - ddrphy_dfitimingschecker_dfitimingschecker12 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv157 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv157) begin - ddrphy_dfitimingschecker_dfitimingschecker13 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv158 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv158 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv158 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv158 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker17 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv158) begin - ddrphy_dfitimingschecker_dfitimingschecker14 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state3; - end - if ((ddrphy_dfitimingschecker_cmd_recv158 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed52 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2); - end - if ((ddrphy_dfitimingschecker_cmd_recv158 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed53 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv158) begin - sync_t_array_muxed26 = ddrphy_dfitimingschecker_ps3; - case (ddrphy_dfitimingschecker_act_next26) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed26; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed26; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed26; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed26; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next26; - end - if (((ddrphy_dfitimingschecker_cmd_recv159 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv159 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv159 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv159 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv159) begin - ddrphy_dfitimingschecker_dfitimingschecker15 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv160 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv160 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2); - end - if (((ddrphy_dfitimingschecker_cmd_recv160 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2); - end - if (ddrphy_dfitimingschecker_cmd_recv160) begin - ddrphy_dfitimingschecker_dfitimingschecker16 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state3; - end - if (ddrphy_dfitimingschecker_cmd_recv161) begin - ddrphy_dfitimingschecker_dfitimingschecker17 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv162 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv162 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv162 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv162) begin - ddrphy_dfitimingschecker_dfitimingschecker18 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv163 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv163) begin - ddrphy_dfitimingschecker_dfitimingschecker19 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv164 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv164 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv164 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv164 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker23 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv164) begin - ddrphy_dfitimingschecker_dfitimingschecker20 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state3; - end - if ((ddrphy_dfitimingschecker_cmd_recv164 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed54 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3); - end - if ((ddrphy_dfitimingschecker_cmd_recv164 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed55 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv164) begin - sync_t_array_muxed27 = ddrphy_dfitimingschecker_ps3; - case (ddrphy_dfitimingschecker_act_next27) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed27; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed27; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed27; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed27; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next27; - end - if (((ddrphy_dfitimingschecker_cmd_recv165 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv165 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv165 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv165 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv165) begin - ddrphy_dfitimingschecker_dfitimingschecker21 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv166 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv166 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3); - end - if (((ddrphy_dfitimingschecker_cmd_recv166 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3); - end - if (ddrphy_dfitimingschecker_cmd_recv166) begin - ddrphy_dfitimingschecker_dfitimingschecker22 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state3; - end - if (ddrphy_dfitimingschecker_cmd_recv167) begin - ddrphy_dfitimingschecker_dfitimingschecker23 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv168 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv168 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv168 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv168) begin - ddrphy_dfitimingschecker_dfitimingschecker24 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv169 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv169) begin - ddrphy_dfitimingschecker_dfitimingschecker25 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv170 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv170 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv170 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv170 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker29 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv170) begin - ddrphy_dfitimingschecker_dfitimingschecker26 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state3; - end - if ((ddrphy_dfitimingschecker_cmd_recv170 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed56 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4); - end - if ((ddrphy_dfitimingschecker_cmd_recv170 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed57 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv170) begin - sync_t_array_muxed28 = ddrphy_dfitimingschecker_ps3; - case (ddrphy_dfitimingschecker_act_next28) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed28; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed28; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed28; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed28; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next28; - end - if (((ddrphy_dfitimingschecker_cmd_recv171 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv171 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv171 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv171 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv171) begin - ddrphy_dfitimingschecker_dfitimingschecker27 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv172 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv172 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4); - end - if (((ddrphy_dfitimingschecker_cmd_recv172 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4); - end - if (ddrphy_dfitimingschecker_cmd_recv172) begin - ddrphy_dfitimingschecker_dfitimingschecker28 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state3; - end - if (ddrphy_dfitimingschecker_cmd_recv173) begin - ddrphy_dfitimingschecker_dfitimingschecker29 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv174 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv174 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv174 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv174) begin - ddrphy_dfitimingschecker_dfitimingschecker30 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv175 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv175) begin - ddrphy_dfitimingschecker_dfitimingschecker31 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv176 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv176 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv176 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv176 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker35 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv176) begin - ddrphy_dfitimingschecker_dfitimingschecker32 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state3; - end - if ((ddrphy_dfitimingschecker_cmd_recv176 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed58 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5); - end - if ((ddrphy_dfitimingschecker_cmd_recv176 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed59 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv176) begin - sync_t_array_muxed29 = ddrphy_dfitimingschecker_ps3; - case (ddrphy_dfitimingschecker_act_next29) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed29; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed29; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed29; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed29; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next29; - end - if (((ddrphy_dfitimingschecker_cmd_recv177 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv177 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv177 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv177 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv177) begin - ddrphy_dfitimingschecker_dfitimingschecker33 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv178 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv178 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5); - end - if (((ddrphy_dfitimingschecker_cmd_recv178 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5); - end - if (ddrphy_dfitimingschecker_cmd_recv178) begin - ddrphy_dfitimingschecker_dfitimingschecker34 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state3; - end - if (ddrphy_dfitimingschecker_cmd_recv179) begin - ddrphy_dfitimingschecker_dfitimingschecker35 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv180 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv180 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv180 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv180) begin - ddrphy_dfitimingschecker_dfitimingschecker36 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv181 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv181) begin - ddrphy_dfitimingschecker_dfitimingschecker37 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv182 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv182 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv182 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv182 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker41 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv182) begin - ddrphy_dfitimingschecker_dfitimingschecker38 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state3; - end - if ((ddrphy_dfitimingschecker_cmd_recv182 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed60 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6); - end - if ((ddrphy_dfitimingschecker_cmd_recv182 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed61 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv182) begin - sync_t_array_muxed30 = ddrphy_dfitimingschecker_ps3; - case (ddrphy_dfitimingschecker_act_next30) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed30; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed30; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed30; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed30; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next30; - end - if (((ddrphy_dfitimingschecker_cmd_recv183 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv183 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv183 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv183 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv183) begin - ddrphy_dfitimingschecker_dfitimingschecker39 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv184 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv184 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6); - end - if (((ddrphy_dfitimingschecker_cmd_recv184 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6); - end - if (ddrphy_dfitimingschecker_cmd_recv184) begin - ddrphy_dfitimingschecker_dfitimingschecker40 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state3; - end - if (ddrphy_dfitimingschecker_cmd_recv185) begin - ddrphy_dfitimingschecker_dfitimingschecker41 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv186 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin - $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv186 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd35000)))) begin - $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv186 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd21250)))) begin - $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv186) begin - ddrphy_dfitimingschecker_dfitimingschecker42 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv187 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin - $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv187) begin - ddrphy_dfitimingschecker_dfitimingschecker43 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv188 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin - $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv188 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin - $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv188 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd48750)))) begin - $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv188 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker47 + 18'd160000)))) begin - $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv188) begin - ddrphy_dfitimingschecker_dfitimingschecker44 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state3; - end - if ((ddrphy_dfitimingschecker_cmd_recv188 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed62 + 14'd10000)))) begin - $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7); - end - if ((ddrphy_dfitimingschecker_cmd_recv188 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed63 + 16'd40000)))) begin - $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv188) begin - sync_t_array_muxed31 = ddrphy_dfitimingschecker_ps3; - case (ddrphy_dfitimingschecker_act_next31) - 1'd0: begin - ddrphy_dfitimingschecker0 <= sync_t_array_muxed31; - end - 1'd1: begin - ddrphy_dfitimingschecker1 <= sync_t_array_muxed31; - end - 2'd2: begin - ddrphy_dfitimingschecker2 <= sync_t_array_muxed31; - end - default: begin - ddrphy_dfitimingschecker3 <= sync_t_array_muxed31; - end - endcase - ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next31; - end - if (((ddrphy_dfitimingschecker_cmd_recv189 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin - $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv189 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin - $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv189 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv189 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd17500)))) begin - $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv189) begin - ddrphy_dfitimingschecker_dfitimingschecker45 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state3; - end - if (((ddrphy_dfitimingschecker_cmd_recv190 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin - $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv190 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin - $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7); - end - if (((ddrphy_dfitimingschecker_cmd_recv190 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin - $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7); - end - if (ddrphy_dfitimingschecker_cmd_recv190) begin - ddrphy_dfitimingschecker_dfitimingschecker46 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state3; - end - if (ddrphy_dfitimingschecker_cmd_recv191) begin - ddrphy_dfitimingschecker_dfitimingschecker47 <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state3; - end - if ((ddrphy_dfitimingschecker_ref_ps_mod < 36'd64000000000)) begin - ddrphy_dfitimingschecker_ref_ps_mod <= (ddrphy_dfitimingschecker_ref_ps_mod + 14'd10000); - end else begin - ddrphy_dfitimingschecker_ref_ps_mod <= 1'd0; - end - if ((ddrphy_dfitimingschecker_ref_issued != 1'd0)) begin - ddrphy_dfitimingschecker_ref_ps <= ddrphy_dfitimingschecker_ps3; - ddrphy_dfitimingschecker_ref_ps_diff <= (ddrphy_dfitimingschecker_ref_ps_diff - ddrphy_dfitimingschecker_curr_diff); - end - if (($signed({1'd0, (ddrphy_dfitimingschecker_ref_ps_mod == 1'd0)}) & (ddrphy_dfitimingschecker_ref_ps_diff > $signed({1'd0, 1'd0})))) begin - $display("[%016dps] tREFI violation (64ms period): %0d", ddrphy_dfitimingschecker_ps3, ddrphy_dfitimingschecker_ref_ps_diff); - end - if ((ddrphy_dfitimingschecker_ref_issued != 1'd0)) begin - ddrphy_dfitimingschecker_ref_done <= 1'd1; - end - if ((((ddrphy_dfitimingschecker_ref_issued == 1'd0) & ddrphy_dfitimingschecker_ref_done) & (ddrphy_dfitimingschecker_ref_ps > (ddrphy_dfitimingschecker_ps3 + 27'd70312500)))) begin - $display("[%016dps] tREFI violation (too many postponed refreshes)", ddrphy_dfitimingschecker_ps3); - ddrphy_dfitimingschecker_ref_done <= 1'd0; - end + array_muxed18 = 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed18 = 1'd0; + end + 1'd1: begin + array_muxed18 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed18 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed18 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed19 = 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed19 = 1'd0; + end + 1'd1: begin + array_muxed19 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed19 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed19 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed20 = 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed20 = 1'd0; + end + 1'd1: begin + array_muxed20 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed20 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed20 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed21 = 3'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed21 = litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed21 = litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed21 = litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed21 = litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed22 = 14'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed22 = litedramcore_nop_a; + end + 1'd1: begin + array_muxed22 = litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed22 = litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed22 = litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed23 = 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed23 = 1'd0; + end + 1'd1: begin + array_muxed23 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed23 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed23 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed24 = 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed24 = 1'd0; + end + 1'd1: begin + array_muxed24 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed24 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed24 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed25 = 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed25 = 1'd0; + end + 1'd1: begin + array_muxed25 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed25 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed25 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed26 = 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed26 = 1'd0; + end + 1'd1: begin + array_muxed26 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed26 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed26 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed27 = 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed27 = 1'd0; + end + 1'd1: begin + array_muxed27 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed27 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed27 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end + +always @(posedge por_clk) begin + int_rst <= 1'd0; +end + +always @(posedge sys_clk) begin + state <= next_state; + ddrphy_new_bank_write0 <= ddrphy_bank_write0; + ddrphy_new_bank_write_col0 <= ddrphy_bank_write_col0; + ddrphy_new_bank_write1 <= ddrphy_new_bank_write0; + ddrphy_new_bank_write_col1 <= ddrphy_new_bank_write_col0; + ddrphy_new_bank_write2 <= ddrphy_bank_write1; + ddrphy_new_bank_write_col2 <= ddrphy_bank_write_col1; + ddrphy_new_bank_write3 <= ddrphy_new_bank_write2; + ddrphy_new_bank_write_col3 <= ddrphy_new_bank_write_col2; + ddrphy_new_bank_write4 <= ddrphy_bank_write2; + ddrphy_new_bank_write_col4 <= ddrphy_bank_write_col2; + ddrphy_new_bank_write5 <= ddrphy_new_bank_write4; + ddrphy_new_bank_write_col5 <= ddrphy_new_bank_write_col4; + ddrphy_new_bank_write6 <= ddrphy_bank_write3; + ddrphy_new_bank_write_col6 <= ddrphy_bank_write_col3; + ddrphy_new_bank_write7 <= ddrphy_new_bank_write6; + ddrphy_new_bank_write_col7 <= ddrphy_new_bank_write_col6; + ddrphy_new_bank_write8 <= ddrphy_bank_write4; + ddrphy_new_bank_write_col8 <= ddrphy_bank_write_col4; + ddrphy_new_bank_write9 <= ddrphy_new_bank_write8; + ddrphy_new_bank_write_col9 <= ddrphy_new_bank_write_col8; + ddrphy_new_bank_write10 <= ddrphy_bank_write5; + ddrphy_new_bank_write_col10 <= ddrphy_bank_write_col5; + ddrphy_new_bank_write11 <= ddrphy_new_bank_write10; + ddrphy_new_bank_write_col11 <= ddrphy_new_bank_write_col10; + ddrphy_new_bank_write12 <= ddrphy_bank_write6; + ddrphy_new_bank_write_col12 <= ddrphy_bank_write_col6; + ddrphy_new_bank_write13 <= ddrphy_new_bank_write12; + ddrphy_new_bank_write_col13 <= ddrphy_new_bank_write_col12; + ddrphy_new_bank_write14 <= ddrphy_bank_write7; + ddrphy_new_bank_write_col14 <= ddrphy_bank_write_col7; + ddrphy_new_bank_write15 <= ddrphy_new_bank_write14; + ddrphy_new_bank_write_col15 <= ddrphy_new_bank_write_col14; + ddrphy_new_banks_read0 <= ddrphy_banks_read; + ddrphy_new_banks_read_data0 <= ddrphy_banks_read_data; + ddrphy_new_banks_read1 <= ddrphy_new_banks_read0; + ddrphy_new_banks_read_data1 <= ddrphy_new_banks_read_data0; + ddrphy_new_banks_read2 <= ddrphy_new_banks_read1; + ddrphy_new_banks_read_data2 <= ddrphy_new_banks_read_data1; + ddrphy_new_banks_read3 <= ddrphy_new_banks_read2; + ddrphy_new_banks_read_data3 <= ddrphy_new_banks_read_data2; + ddrphy_new_banks_read4 <= ddrphy_new_banks_read3; + ddrphy_new_banks_read_data4 <= ddrphy_new_banks_read_data3; + ddrphy_new_banks_read5 <= ddrphy_new_banks_read4; + ddrphy_new_banks_read_data5 <= ddrphy_new_banks_read_data4; + ddrphy_new_banks_read6 <= ddrphy_new_banks_read5; + ddrphy_new_banks_read_data6 <= ddrphy_new_banks_read_data5; + ddrphy_new_banks_read7 <= ddrphy_new_banks_read6; + ddrphy_new_banks_read_data7 <= ddrphy_new_banks_read_data6; + ddrphy_new_banks_read8 <= ddrphy_new_banks_read7; + ddrphy_new_banks_read_data8 <= ddrphy_new_banks_read_data7; if (ddrphy_bankmodel0_precharge) begin ddrphy_bankmodel0_active <= 1'd0; end else begin @@ -17165,37 +12649,37 @@ always @(posedge sys_clk) begin endcase end litedramcore_dfi_p0_cs_n <= 1'd0; - litedramcore_dfi_p0_bank <= sync_rhs_array_muxed0; - litedramcore_dfi_p0_address <= sync_rhs_array_muxed1; - litedramcore_dfi_p0_cas_n <= (~sync_rhs_array_muxed2); - litedramcore_dfi_p0_ras_n <= (~sync_rhs_array_muxed3); - litedramcore_dfi_p0_we_n <= (~sync_rhs_array_muxed4); - litedramcore_dfi_p0_rddata_en <= sync_rhs_array_muxed5; - litedramcore_dfi_p0_wrdata_en <= sync_rhs_array_muxed6; + litedramcore_dfi_p0_bank <= array_muxed0; + litedramcore_dfi_p0_address <= array_muxed1; + litedramcore_dfi_p0_cas_n <= (~array_muxed2); + litedramcore_dfi_p0_ras_n <= (~array_muxed3); + litedramcore_dfi_p0_we_n <= (~array_muxed4); + litedramcore_dfi_p0_rddata_en <= array_muxed5; + litedramcore_dfi_p0_wrdata_en <= array_muxed6; litedramcore_dfi_p1_cs_n <= 1'd0; - litedramcore_dfi_p1_bank <= sync_rhs_array_muxed7; - litedramcore_dfi_p1_address <= sync_rhs_array_muxed8; - litedramcore_dfi_p1_cas_n <= (~sync_rhs_array_muxed9); - litedramcore_dfi_p1_ras_n <= (~sync_rhs_array_muxed10); - litedramcore_dfi_p1_we_n <= (~sync_rhs_array_muxed11); - litedramcore_dfi_p1_rddata_en <= sync_rhs_array_muxed12; - litedramcore_dfi_p1_wrdata_en <= sync_rhs_array_muxed13; + litedramcore_dfi_p1_bank <= array_muxed7; + litedramcore_dfi_p1_address <= array_muxed8; + litedramcore_dfi_p1_cas_n <= (~array_muxed9); + litedramcore_dfi_p1_ras_n <= (~array_muxed10); + litedramcore_dfi_p1_we_n <= (~array_muxed11); + litedramcore_dfi_p1_rddata_en <= array_muxed12; + litedramcore_dfi_p1_wrdata_en <= array_muxed13; litedramcore_dfi_p2_cs_n <= 1'd0; - litedramcore_dfi_p2_bank <= sync_rhs_array_muxed14; - litedramcore_dfi_p2_address <= sync_rhs_array_muxed15; - litedramcore_dfi_p2_cas_n <= (~sync_rhs_array_muxed16); - litedramcore_dfi_p2_ras_n <= (~sync_rhs_array_muxed17); - litedramcore_dfi_p2_we_n <= (~sync_rhs_array_muxed18); - litedramcore_dfi_p2_rddata_en <= sync_rhs_array_muxed19; - litedramcore_dfi_p2_wrdata_en <= sync_rhs_array_muxed20; + litedramcore_dfi_p2_bank <= array_muxed14; + litedramcore_dfi_p2_address <= array_muxed15; + litedramcore_dfi_p2_cas_n <= (~array_muxed16); + litedramcore_dfi_p2_ras_n <= (~array_muxed17); + litedramcore_dfi_p2_we_n <= (~array_muxed18); + litedramcore_dfi_p2_rddata_en <= array_muxed19; + litedramcore_dfi_p2_wrdata_en <= array_muxed20; litedramcore_dfi_p3_cs_n <= 1'd0; - litedramcore_dfi_p3_bank <= sync_rhs_array_muxed21; - litedramcore_dfi_p3_address <= sync_rhs_array_muxed22; - litedramcore_dfi_p3_cas_n <= (~sync_rhs_array_muxed23); - litedramcore_dfi_p3_ras_n <= (~sync_rhs_array_muxed24); - litedramcore_dfi_p3_we_n <= (~sync_rhs_array_muxed25); - litedramcore_dfi_p3_rddata_en <= sync_rhs_array_muxed26; - litedramcore_dfi_p3_wrdata_en <= sync_rhs_array_muxed27; + litedramcore_dfi_p3_bank <= array_muxed21; + litedramcore_dfi_p3_address <= array_muxed22; + litedramcore_dfi_p3_cas_n <= (~array_muxed23); + litedramcore_dfi_p3_ras_n <= (~array_muxed24); + litedramcore_dfi_p3_we_n <= (~array_muxed25); + litedramcore_dfi_p3_rddata_en <= array_muxed26; + litedramcore_dfi_p3_wrdata_en <= array_muxed27; if (litedramcore_trrdcon_valid) begin litedramcore_trrdcon_count <= 1'd1; if (1'd0) begin @@ -17265,7 +12749,7 @@ always @(posedge sys_clk) begin new_master_rdata_valid9 <= new_master_rdata_valid8; interface0_bank_bus_dat_r <= 1'd0; if (csrbank0_sel) begin - case (interface0_bank_bus_adr[1]) + case (interface0_bank_bus_adr[0]) 1'd0: begin interface0_bank_bus_dat_r <= csrbank0_init_done0_w; end @@ -17284,7 +12768,7 @@ always @(posedge sys_clk) begin init_error_re <= csrbank0_init_error0_re; interface1_bank_bus_dat_r <= 1'd0; if (csrbank1_sel) begin - case (interface1_bank_bus_adr[5:1]) + case (interface1_bank_bus_adr[5:0]) 1'd0: begin interface1_bank_bus_dat_r <= csrbank1_dfii_control0_w; end @@ -17295,70 +12779,154 @@ always @(posedge sys_clk) begin interface1_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address1_w; end 3'd4: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w; end 3'd5: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w; end 3'd6: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata3_w; end 3'd7: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata2_w; end 4'd8: begin - interface1_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata1_w; end 4'd9: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w; end 4'd10: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata3_w; end 4'd11: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata2_w; end 4'd12: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata1_w; end 4'd13: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata0_w; end 4'd14: begin - interface1_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w; end 4'd15: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w; + interface1_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; end 5'd16: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address1_w; end 5'd17: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w; end 5'd18: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w; end 5'd19: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata3_w; end 5'd20: begin - interface1_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata2_w; end 5'd21: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata1_w; end 5'd22: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w; end 5'd23: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata3_w; end 5'd24: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata2_w; + end + 5'd25: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata1_w; + end + 5'd26: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata0_w; + end + 5'd27: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w; + end + 5'd28: begin + interface1_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; + end + 5'd29: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address1_w; + end + 5'd30: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w; + end + 5'd31: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w; + end + 6'd32: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata3_w; + end + 6'd33: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata2_w; + end + 6'd34: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata1_w; + end + 6'd35: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w; + end + 6'd36: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata3_w; + end + 6'd37: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata2_w; + end + 6'd38: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata1_w; + end + 6'd39: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata0_w; + end + 6'd40: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w; + end + 6'd41: begin + interface1_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; + end + 6'd42: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address1_w; + end + 6'd43: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w; + end + 6'd44: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w; + end + 6'd45: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata3_w; + end + 6'd46: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata2_w; + end + 6'd47: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata1_w; + end + 6'd48: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w; + end + 6'd49: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata3_w; + end + 6'd50: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata2_w; + end + 6'd51: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata1_w; + end + 6'd52: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata0_w; end endcase end @@ -17370,133 +12938,115 @@ always @(posedge sys_clk) begin litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r; end litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re; + if (csrbank1_dfii_pi0_address1_re) begin + litedramcore_phaseinjector0_address_storage[13:8] <= csrbank1_dfii_pi0_address1_r; + end if (csrbank1_dfii_pi0_address0_re) begin - litedramcore_phaseinjector0_address_storage[13:0] <= csrbank1_dfii_pi0_address0_r; + litedramcore_phaseinjector0_address_storage[7:0] <= csrbank1_dfii_pi0_address0_r; end litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re; if (csrbank1_dfii_pi0_baddress0_re) begin litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r; end litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re; + if (csrbank1_dfii_pi0_wrdata3_re) begin + litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank1_dfii_pi0_wrdata3_r; + end + if (csrbank1_dfii_pi0_wrdata2_re) begin + litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank1_dfii_pi0_wrdata2_r; + end + if (csrbank1_dfii_pi0_wrdata1_re) begin + litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank1_dfii_pi0_wrdata1_r; + end if (csrbank1_dfii_pi0_wrdata0_re) begin - litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank1_dfii_pi0_wrdata0_r; + litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank1_dfii_pi0_wrdata0_r; end litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re; if (csrbank1_dfii_pi1_command0_re) begin litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r; end litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re; + if (csrbank1_dfii_pi1_address1_re) begin + litedramcore_phaseinjector1_address_storage[13:8] <= csrbank1_dfii_pi1_address1_r; + end if (csrbank1_dfii_pi1_address0_re) begin - litedramcore_phaseinjector1_address_storage[13:0] <= csrbank1_dfii_pi1_address0_r; + litedramcore_phaseinjector1_address_storage[7:0] <= csrbank1_dfii_pi1_address0_r; end litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re; if (csrbank1_dfii_pi1_baddress0_re) begin litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r; end litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re; + if (csrbank1_dfii_pi1_wrdata3_re) begin + litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank1_dfii_pi1_wrdata3_r; + end + if (csrbank1_dfii_pi1_wrdata2_re) begin + litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank1_dfii_pi1_wrdata2_r; + end + if (csrbank1_dfii_pi1_wrdata1_re) begin + litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank1_dfii_pi1_wrdata1_r; + end if (csrbank1_dfii_pi1_wrdata0_re) begin - litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank1_dfii_pi1_wrdata0_r; + litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank1_dfii_pi1_wrdata0_r; end litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re; if (csrbank1_dfii_pi2_command0_re) begin litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r; end litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re; + if (csrbank1_dfii_pi2_address1_re) begin + litedramcore_phaseinjector2_address_storage[13:8] <= csrbank1_dfii_pi2_address1_r; + end if (csrbank1_dfii_pi2_address0_re) begin - litedramcore_phaseinjector2_address_storage[13:0] <= csrbank1_dfii_pi2_address0_r; + litedramcore_phaseinjector2_address_storage[7:0] <= csrbank1_dfii_pi2_address0_r; end litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re; if (csrbank1_dfii_pi2_baddress0_re) begin litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r; end litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re; + if (csrbank1_dfii_pi2_wrdata3_re) begin + litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank1_dfii_pi2_wrdata3_r; + end + if (csrbank1_dfii_pi2_wrdata2_re) begin + litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank1_dfii_pi2_wrdata2_r; + end + if (csrbank1_dfii_pi2_wrdata1_re) begin + litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank1_dfii_pi2_wrdata1_r; + end if (csrbank1_dfii_pi2_wrdata0_re) begin - litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank1_dfii_pi2_wrdata0_r; + litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank1_dfii_pi2_wrdata0_r; end litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re; if (csrbank1_dfii_pi3_command0_re) begin litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r; end litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re; + if (csrbank1_dfii_pi3_address1_re) begin + litedramcore_phaseinjector3_address_storage[13:8] <= csrbank1_dfii_pi3_address1_r; + end if (csrbank1_dfii_pi3_address0_re) begin - litedramcore_phaseinjector3_address_storage[13:0] <= csrbank1_dfii_pi3_address0_r; + litedramcore_phaseinjector3_address_storage[7:0] <= csrbank1_dfii_pi3_address0_r; end litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re; if (csrbank1_dfii_pi3_baddress0_re) begin litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r; end litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re; + if (csrbank1_dfii_pi3_wrdata3_re) begin + litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank1_dfii_pi3_wrdata3_r; + end + if (csrbank1_dfii_pi3_wrdata2_re) begin + litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank1_dfii_pi3_wrdata2_r; + end + if (csrbank1_dfii_pi3_wrdata1_re) begin + litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank1_dfii_pi3_wrdata1_r; + end if (csrbank1_dfii_pi3_wrdata0_re) begin - litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank1_dfii_pi3_wrdata0_r; + litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank1_dfii_pi3_wrdata0_r; end litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re; if (sys_rst) begin - ddrphy_dfitimingschecker_cnt <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker0 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker1 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker2 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker3 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker4 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker5 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker6 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker7 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker8 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker9 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker10 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker11 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker12 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker13 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker14 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker15 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker16 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker17 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker18 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker19 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker20 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker21 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker22 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker23 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker24 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker25 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker26 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker27 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker28 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker29 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker30 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker31 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker32 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker33 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker34 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker35 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker36 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker37 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker38 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker39 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker40 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker41 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker42 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker43 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker44 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker45 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker46 <= 64'd0; - ddrphy_dfitimingschecker_dfitimingschecker47 <= 64'd0; - ddrphy_dfitimingschecker_last_cmd0 <= 4'd0; - ddrphy_dfitimingschecker_last_cmd1 <= 4'd0; - ddrphy_dfitimingschecker_last_cmd2 <= 4'd0; - ddrphy_dfitimingschecker_last_cmd3 <= 4'd0; - ddrphy_dfitimingschecker_last_cmd4 <= 4'd0; - ddrphy_dfitimingschecker_last_cmd5 <= 4'd0; - ddrphy_dfitimingschecker_last_cmd6 <= 4'd0; - ddrphy_dfitimingschecker_last_cmd7 <= 4'd0; - ddrphy_dfitimingschecker0 <= 64'd0; - ddrphy_dfitimingschecker1 <= 64'd0; - ddrphy_dfitimingschecker2 <= 64'd0; - ddrphy_dfitimingschecker3 <= 64'd0; - ddrphy_dfitimingschecker_act_curr <= 2'd0; - ddrphy_dfitimingschecker_ref_ps <= 64'd0; - ddrphy_dfitimingschecker_ref_ps_mod <= 64'd0; - ddrphy_dfitimingschecker_ref_ps_diff <= 64'd0; - ddrphy_dfitimingschecker_ref_done <= 1'd0; ddrphy_bankmodel0_active <= 1'd0; ddrphy_bankmodel0_row <= 14'd0; ddrphy_bankmodel1_active <= 1'd0;