replacing (condition) with (condition='1' --removing vhdl 2008 featuers to support vivado simulation

Signed-off-by: alaasal <alaamohsalman@gmail.com>

core_debug.vhdl

@@ -145,7 +145,7 @@ begin
 	    do_icreset <= '0';
             do_dmi_log_rd <= '0';
 
-	    if (rst) then
+	    if (rst = '1') then
 		stopping <= '0';
 		terminated <= '0';
 	    else

execute1.vhdl

@@ -864,7 +864,7 @@ begin
 		report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 		    "=" & to_hstring(a_in);
 		result_en := '1';
-		if is_fast_spr(e_in.read_reg1) then
+		if (is_fast_spr(e_in.read_reg1) = '1') then
 		    result := a_in;
 		    if decode_spr_num(e_in.insn) = SPR_XER then
 			-- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
@@ -953,7 +953,7 @@ begin
 	    when OP_MTSPR =>
 		report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 		    "=" & to_hstring(c_in);
-		if is_fast_spr(e_in.write_reg) then
+		if ( is_fast_spr(e_in.write_reg) = '1' ) then
 		    result := c_in;
 		    result_en := '1';
 		    if decode_spr_num(e_in.insn) = SPR_XER then