From e3013f5754ccd78a5da499f0800deea661c5e27c Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Sat, 9 May 2020 11:20:59 +1000 Subject: [PATCH] litedram: Use 32-bit CSR bus Signed-off-by: Benjamin Herrenschmidt --- litedram/gen-src/generate.py | 2 +- litedram/gen-src/wrapper-mw-init.vhdl | 14 +- litedram/generated/arty/litedram-wrapper.vhdl | 14 +- litedram/generated/arty/litedram_core.init | 1524 ++++++++------- litedram/generated/arty/litedram_core.v | 722 ++----- .../nexys-video/litedram-wrapper.vhdl | 14 +- .../generated/nexys-video/litedram_core.init | 1422 +++++++------- .../generated/nexys-video/litedram_core.v | 1688 +++++++---------- 8 files changed, 2331 insertions(+), 3069 deletions(-) diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py index 8c6b70a..4c24cae 100755 --- a/litedram/gen-src/generate.py +++ b/litedram/gen-src/generate.py @@ -115,7 +115,7 @@ def generate_one(t, mw_init): else: raise ValueError("Unsupported SDRAM PHY: {}".format(core_config["sdram_phy"])) - soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000) + soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000, csr_data_width=32) # Build into build_dir builder = Builder(soc, output_dir=build_dir, compile_gateware=False) diff --git a/litedram/gen-src/wrapper-mw-init.vhdl b/litedram/gen-src/wrapper-mw-init.vhdl index 475e088..46ae4b1 100644 --- a/litedram/gen-src/wrapper-mw-init.vhdl +++ b/litedram/gen-src/wrapper-mw-init.vhdl @@ -82,8 +82,8 @@ architecture behaviour of litedram_wrapper is user_rst : out std_ulogic; csr_port0_adr : in std_ulogic_vector(13 downto 0); csr_port0_we : in std_ulogic; - csr_port0_dat_w : in std_ulogic_vector(7 downto 0); - csr_port0_dat_r : out std_ulogic_vector(7 downto 0); + csr_port0_dat_w : in std_ulogic_vector(31 downto 0); + csr_port0_dat_r : out std_ulogic_vector(31 downto 0); user_port_native_0_cmd_valid : in std_ulogic; user_port_native_0_cmd_ready : out std_ulogic; user_port_native_0_cmd_we : in std_ulogic; @@ -116,8 +116,8 @@ architecture behaviour of litedram_wrapper is signal csr_port0_adr : std_ulogic_vector(13 downto 0); signal csr_port0_we : std_ulogic; - signal csr_port0_dat_w : std_ulogic_vector(7 downto 0); - signal csr_port0_dat_r : std_ulogic_vector(7 downto 0); + signal csr_port0_dat_w : std_ulogic_vector(31 downto 0); + signal csr_port0_dat_r : std_ulogic_vector(31 downto 0); signal csr_port_read_comb : std_ulogic_vector(63 downto 0); signal csr_valid : std_ulogic; signal csr_write_valid : std_ulogic; @@ -205,8 +205,8 @@ begin -- DRAM CSR interface signals. We only support access to the bottom byte csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; csr_write_valid <= wb_in.we and wb_in.sel(0); - csr_port0_adr <= wb_in.adr(13 downto 0) when wb_is_csr = '1' else (others => '0'); - csr_port0_dat_w <= wb_in.dat(7 downto 0); + csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0'); + csr_port0_dat_w <= wb_in.dat(31 downto 0); csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; -- Wishbone out signals @@ -215,7 +215,7 @@ begin user_port0_wdata_ready when state = MWRITE else user_port0_rdata_valid when state = MREAD else '0'; - csr_port_read_comb <= x"00000000000000" & csr_port0_dat_r; + csr_port_read_comb <= x"00000000" & csr_port0_dat_r; wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else wb_init_out.dat when wb_is_init = '1' else user_port0_rdata_data(127 downto 64) when ad3 = '1' else diff --git a/litedram/generated/arty/litedram-wrapper.vhdl b/litedram/generated/arty/litedram-wrapper.vhdl index 475e088..46ae4b1 100644 --- a/litedram/generated/arty/litedram-wrapper.vhdl +++ b/litedram/generated/arty/litedram-wrapper.vhdl @@ -82,8 +82,8 @@ architecture behaviour of litedram_wrapper is user_rst : out std_ulogic; csr_port0_adr : in std_ulogic_vector(13 downto 0); csr_port0_we : in std_ulogic; - csr_port0_dat_w : in std_ulogic_vector(7 downto 0); - csr_port0_dat_r : out std_ulogic_vector(7 downto 0); + csr_port0_dat_w : in std_ulogic_vector(31 downto 0); + csr_port0_dat_r : out std_ulogic_vector(31 downto 0); user_port_native_0_cmd_valid : in std_ulogic; user_port_native_0_cmd_ready : out std_ulogic; user_port_native_0_cmd_we : in std_ulogic; @@ -116,8 +116,8 @@ architecture behaviour of litedram_wrapper is signal csr_port0_adr : std_ulogic_vector(13 downto 0); signal csr_port0_we : std_ulogic; - signal csr_port0_dat_w : std_ulogic_vector(7 downto 0); - signal csr_port0_dat_r : std_ulogic_vector(7 downto 0); + signal csr_port0_dat_w : std_ulogic_vector(31 downto 0); + signal csr_port0_dat_r : std_ulogic_vector(31 downto 0); signal csr_port_read_comb : std_ulogic_vector(63 downto 0); signal csr_valid : std_ulogic; signal csr_write_valid : std_ulogic; @@ -205,8 +205,8 @@ begin -- DRAM CSR interface signals. We only support access to the bottom byte csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; csr_write_valid <= wb_in.we and wb_in.sel(0); - csr_port0_adr <= wb_in.adr(13 downto 0) when wb_is_csr = '1' else (others => '0'); - csr_port0_dat_w <= wb_in.dat(7 downto 0); + csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0'); + csr_port0_dat_w <= wb_in.dat(31 downto 0); csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; -- Wishbone out signals @@ -215,7 +215,7 @@ begin user_port0_wdata_ready when state = MWRITE else user_port0_rdata_valid when state = MREAD else '0'; - csr_port_read_comb <= x"00000000000000" & csr_port0_dat_r; + csr_port_read_comb <= x"00000000" & csr_port0_dat_r; wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else wb_init_out.dat when wb_is_init = '1' else user_port0_rdata_data(127 downto 64) when ad3 = '1' else diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init index 1031ca2..4f7ad0f 100644 --- a/litedram/generated/arty/litedram_core.init +++ b/litedram/generated/arty/litedram_core.init @@ -510,37 +510,37 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -38429f003c4c0001 +38429e003c4c0001 600000003d20c000 7929002061292000 -3d40c000f9228038 +3d40c000f92280a8 614a201839200035 7c0004ac794a0020 4e8000207d2057aa 0000000000000000 3c4c000100000000 -6000000038429ebc -39290010e9228038 +6000000038429dbc +39290010e92280a8 7d204eaa7c0004ac 4082ffe871290008 -e922803860000000 +e92280a860000000 7c604faa7c0004ac 000000004e800020 0000000000000000 -38429e783c4c0001 +38429d783c4c0001 fbc1fff07c0802a6 7fc32214fbe1fff8 f80100107c7f1b78 7fbff040f821ffd1 38210030409e000c -893f000048001b40 +893f000048001ab4 409e000c2f89000a 4bffff813860000d 3bff0001887f0000 4bffffd04bffff75 0100000000000000 3c4c000100000280 -7c0802a638429e14 +7c0802a638429d14 fbe1fff8fbc1fff0 f821fe91f8010010 f88101983bc10020 @@ -549,62 +549,62 @@ f88101983bc10020 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+7ce8305041820010 +419d00207faa3840 +7f65db78e8810060 +7c9e20507fa3eb78 +4bfff9cd7c84f850 +38e000204bfffdd4 +e8e1006098e60000 +f8e1006038e70001 +2b87006c4bffffb4 +409efdb03b200008 +4bfffda87cd83378 +3b2000022b870068 +7cd83378409efd9c +4bfffd903b200001 +4bfffd883b200008 +3b0100413a600020 +993e00004bfffc60 +e92100607d455378 +f921006039290001 +000000004bfffb24 +0000128001000000 +f9e1ff78f9c1ff70 +fa21ff88fa01ff80 +fa61ff98fa41ff90 +faa1ffa8fa81ffa0 +fae1ffb8fac1ffb0 +fb21ffc8fb01ffc0 +fb61ffd8fb41ffd0 +fba1ffe8fb81ffe0 +fbe1fff8fbc1fff0 +4e800020f8010010 +e9e1ff78e9c1ff70 +ea21ff88ea01ff80 +ea61ff98ea41ff90 +eaa1ffa8ea81ffa0 +eae1ffb8eac1ffb0 +eb21ffc8eb01ffc0 +eb61ffd8eb41ffd0 +e8010010eb81ffe0 +7c0803a6eba1ffe8 +ebe1fff8ebc1fff0 +ebc1fff04e800020 +ebe1fff8e8010010 +4e8000207c0803a6 6d6f636c65570a0a 63694d206f742065 2120747461776f72 @@ -1473,10 +1455,10 @@ e8010010ebc1fff0 000000000000002d 30252d2b64323025 0000000000006432 -00000000c0100850 -00000000c01008b8 -00000000c0100920 -00000000c0100988 +00000000c0100830 +00000000c0100860 +00000000c0100890 +00000000c01008c0 6f6e204d41524453 207265646e752077 6572617764726168 diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v index 727e21a..18cb7f1 100644 --- a/litedram/generated/arty/litedram_core.v +++ b/litedram/generated/arty/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 10:54:03 +// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 11:57:11 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, @@ -24,8 +24,8 @@ module litedram_core( output wire init_error, input wire [13:0] csr_port0_adr, input wire csr_port0_we, - input wire [7:0] csr_port0_dat_w, - output wire [7:0] csr_port0_dat_r, + input wire [31:0] csr_port0_dat_w, + output wire [31:0] csr_port0_dat_r, output wire user_clk, output wire user_rst, input wire user_port_native_0_cmd_valid, @@ -1485,8 +1485,8 @@ reg init_error_storage = 1'd0; reg init_error_re = 1'd0; wire [13:0] csr_port_adr; wire csr_port_we; -wire [7:0] csr_port_dat_w; -wire [7:0] csr_port_dat_r; +wire [31:0] csr_port_dat_w; +wire [31:0] csr_port_dat_r; wire user_port_cmd_valid; wire user_port_cmd_ready; wire user_port_cmd_payload_we; @@ -1566,8 +1566,8 @@ reg new_master_rdata_valid7 = 1'd0; reg new_master_rdata_valid8 = 1'd0; wire [13:0] interface0_bank_bus_adr; wire interface0_bank_bus_we; -wire [7:0] interface0_bank_bus_dat_w; -reg [7:0] interface0_bank_bus_dat_r = 8'd0; +wire [31:0] interface0_bank_bus_dat_w; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; wire csrbank0_init_done0_re; wire csrbank0_init_done0_r; wire csrbank0_init_done0_we; @@ -1579,8 +1579,8 @@ wire csrbank0_init_error0_w; reg csrbank0_sel = 1'd0; wire [13:0] interface1_bank_bus_adr; wire interface1_bank_bus_we; -wire [7:0] interface1_bank_bus_dat_w; -reg [7:0] interface1_bank_bus_dat_r = 8'd0; +wire [31:0] interface1_bank_bus_dat_w; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; wire csrbank1_half_sys8x_taps0_re; wire [4:0] csrbank1_half_sys8x_taps0_r; wire csrbank1_half_sys8x_taps0_we; @@ -1596,8 +1596,8 @@ wire [1:0] csrbank1_dly_sel0_w; reg csrbank1_sel = 1'd0; wire [13:0] interface2_bank_bus_adr; wire interface2_bank_bus_we; -wire [7:0] interface2_bank_bus_dat_w; -reg [7:0] interface2_bank_bus_dat_r = 8'd0; +wire [31:0] interface2_bank_bus_dat_w; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; wire csrbank2_dfii_control0_re; wire [3:0] csrbank2_dfii_control0_r; wire csrbank2_dfii_control0_we; @@ -1606,199 +1606,87 @@ wire csrbank2_dfii_pi0_command0_re; wire [5:0] csrbank2_dfii_pi0_command0_r; wire csrbank2_dfii_pi0_command0_we; wire [5:0] csrbank2_dfii_pi0_command0_w; -wire csrbank2_dfii_pi0_address1_re; -wire [5:0] csrbank2_dfii_pi0_address1_r; -wire csrbank2_dfii_pi0_address1_we; -wire [5:0] csrbank2_dfii_pi0_address1_w; wire csrbank2_dfii_pi0_address0_re; -wire [7:0] csrbank2_dfii_pi0_address0_r; +wire [13:0] csrbank2_dfii_pi0_address0_r; wire csrbank2_dfii_pi0_address0_we; -wire [7:0] csrbank2_dfii_pi0_address0_w; +wire [13:0] csrbank2_dfii_pi0_address0_w; wire csrbank2_dfii_pi0_baddress0_re; wire [2:0] csrbank2_dfii_pi0_baddress0_r; wire csrbank2_dfii_pi0_baddress0_we; wire [2:0] csrbank2_dfii_pi0_baddress0_w; -wire csrbank2_dfii_pi0_wrdata3_re; -wire [7:0] csrbank2_dfii_pi0_wrdata3_r; -wire csrbank2_dfii_pi0_wrdata3_we; -wire [7:0] csrbank2_dfii_pi0_wrdata3_w; -wire csrbank2_dfii_pi0_wrdata2_re; -wire [7:0] csrbank2_dfii_pi0_wrdata2_r; -wire csrbank2_dfii_pi0_wrdata2_we; -wire [7:0] csrbank2_dfii_pi0_wrdata2_w; -wire csrbank2_dfii_pi0_wrdata1_re; -wire [7:0] csrbank2_dfii_pi0_wrdata1_r; -wire csrbank2_dfii_pi0_wrdata1_we; -wire [7:0] csrbank2_dfii_pi0_wrdata1_w; wire csrbank2_dfii_pi0_wrdata0_re; -wire [7:0] csrbank2_dfii_pi0_wrdata0_r; +wire [31:0] csrbank2_dfii_pi0_wrdata0_r; wire csrbank2_dfii_pi0_wrdata0_we; -wire [7:0] csrbank2_dfii_pi0_wrdata0_w; -wire csrbank2_dfii_pi0_rddata3_re; -wire [7:0] csrbank2_dfii_pi0_rddata3_r; -wire csrbank2_dfii_pi0_rddata3_we; -wire [7:0] csrbank2_dfii_pi0_rddata3_w; -wire csrbank2_dfii_pi0_rddata2_re; -wire [7:0] csrbank2_dfii_pi0_rddata2_r; -wire csrbank2_dfii_pi0_rddata2_we; -wire [7:0] csrbank2_dfii_pi0_rddata2_w; -wire csrbank2_dfii_pi0_rddata1_re; -wire [7:0] csrbank2_dfii_pi0_rddata1_r; -wire csrbank2_dfii_pi0_rddata1_we; -wire [7:0] csrbank2_dfii_pi0_rddata1_w; -wire csrbank2_dfii_pi0_rddata0_re; -wire [7:0] csrbank2_dfii_pi0_rddata0_r; -wire csrbank2_dfii_pi0_rddata0_we; -wire [7:0] csrbank2_dfii_pi0_rddata0_w; +wire [31:0] csrbank2_dfii_pi0_wrdata0_w; +wire csrbank2_dfii_pi0_rddata_re; +wire [31:0] csrbank2_dfii_pi0_rddata_r; +wire csrbank2_dfii_pi0_rddata_we; +wire [31:0] csrbank2_dfii_pi0_rddata_w; wire csrbank2_dfii_pi1_command0_re; wire [5:0] csrbank2_dfii_pi1_command0_r; wire csrbank2_dfii_pi1_command0_we; wire [5:0] csrbank2_dfii_pi1_command0_w; -wire csrbank2_dfii_pi1_address1_re; -wire [5:0] csrbank2_dfii_pi1_address1_r; -wire csrbank2_dfii_pi1_address1_we; -wire [5:0] csrbank2_dfii_pi1_address1_w; wire csrbank2_dfii_pi1_address0_re; -wire [7:0] csrbank2_dfii_pi1_address0_r; +wire [13:0] csrbank2_dfii_pi1_address0_r; wire csrbank2_dfii_pi1_address0_we; -wire [7:0] csrbank2_dfii_pi1_address0_w; +wire [13:0] csrbank2_dfii_pi1_address0_w; wire csrbank2_dfii_pi1_baddress0_re; wire [2:0] csrbank2_dfii_pi1_baddress0_r; wire csrbank2_dfii_pi1_baddress0_we; wire [2:0] csrbank2_dfii_pi1_baddress0_w; -wire csrbank2_dfii_pi1_wrdata3_re; -wire [7:0] csrbank2_dfii_pi1_wrdata3_r; -wire csrbank2_dfii_pi1_wrdata3_we; -wire [7:0] csrbank2_dfii_pi1_wrdata3_w; -wire csrbank2_dfii_pi1_wrdata2_re; -wire [7:0] csrbank2_dfii_pi1_wrdata2_r; -wire csrbank2_dfii_pi1_wrdata2_we; -wire [7:0] csrbank2_dfii_pi1_wrdata2_w; -wire csrbank2_dfii_pi1_wrdata1_re; -wire [7:0] csrbank2_dfii_pi1_wrdata1_r; -wire csrbank2_dfii_pi1_wrdata1_we; -wire [7:0] csrbank2_dfii_pi1_wrdata1_w; wire csrbank2_dfii_pi1_wrdata0_re; -wire [7:0] csrbank2_dfii_pi1_wrdata0_r; +wire [31:0] csrbank2_dfii_pi1_wrdata0_r; wire csrbank2_dfii_pi1_wrdata0_we; -wire [7:0] csrbank2_dfii_pi1_wrdata0_w; -wire csrbank2_dfii_pi1_rddata3_re; -wire [7:0] csrbank2_dfii_pi1_rddata3_r; -wire csrbank2_dfii_pi1_rddata3_we; -wire [7:0] csrbank2_dfii_pi1_rddata3_w; -wire csrbank2_dfii_pi1_rddata2_re; -wire [7:0] csrbank2_dfii_pi1_rddata2_r; -wire csrbank2_dfii_pi1_rddata2_we; -wire [7:0] csrbank2_dfii_pi1_rddata2_w; -wire csrbank2_dfii_pi1_rddata1_re; -wire [7:0] csrbank2_dfii_pi1_rddata1_r; -wire csrbank2_dfii_pi1_rddata1_we; -wire [7:0] csrbank2_dfii_pi1_rddata1_w; -wire csrbank2_dfii_pi1_rddata0_re; -wire [7:0] csrbank2_dfii_pi1_rddata0_r; -wire csrbank2_dfii_pi1_rddata0_we; -wire [7:0] csrbank2_dfii_pi1_rddata0_w; +wire [31:0] csrbank2_dfii_pi1_wrdata0_w; +wire csrbank2_dfii_pi1_rddata_re; +wire [31:0] csrbank2_dfii_pi1_rddata_r; +wire csrbank2_dfii_pi1_rddata_we; +wire [31:0] csrbank2_dfii_pi1_rddata_w; wire csrbank2_dfii_pi2_command0_re; wire [5:0] csrbank2_dfii_pi2_command0_r; wire csrbank2_dfii_pi2_command0_we; wire [5:0] csrbank2_dfii_pi2_command0_w; -wire csrbank2_dfii_pi2_address1_re; -wire [5:0] csrbank2_dfii_pi2_address1_r; -wire csrbank2_dfii_pi2_address1_we; -wire [5:0] csrbank2_dfii_pi2_address1_w; wire csrbank2_dfii_pi2_address0_re; -wire [7:0] csrbank2_dfii_pi2_address0_r; +wire [13:0] csrbank2_dfii_pi2_address0_r; wire csrbank2_dfii_pi2_address0_we; -wire [7:0] csrbank2_dfii_pi2_address0_w; +wire [13:0] csrbank2_dfii_pi2_address0_w; wire csrbank2_dfii_pi2_baddress0_re; wire [2:0] csrbank2_dfii_pi2_baddress0_r; wire csrbank2_dfii_pi2_baddress0_we; wire [2:0] csrbank2_dfii_pi2_baddress0_w; -wire csrbank2_dfii_pi2_wrdata3_re; -wire [7:0] csrbank2_dfii_pi2_wrdata3_r; -wire csrbank2_dfii_pi2_wrdata3_we; -wire [7:0] csrbank2_dfii_pi2_wrdata3_w; -wire csrbank2_dfii_pi2_wrdata2_re; -wire [7:0] csrbank2_dfii_pi2_wrdata2_r; -wire csrbank2_dfii_pi2_wrdata2_we; -wire [7:0] csrbank2_dfii_pi2_wrdata2_w; -wire csrbank2_dfii_pi2_wrdata1_re; -wire [7:0] csrbank2_dfii_pi2_wrdata1_r; -wire csrbank2_dfii_pi2_wrdata1_we; -wire [7:0] csrbank2_dfii_pi2_wrdata1_w; wire csrbank2_dfii_pi2_wrdata0_re; -wire [7:0] csrbank2_dfii_pi2_wrdata0_r; +wire [31:0] csrbank2_dfii_pi2_wrdata0_r; wire csrbank2_dfii_pi2_wrdata0_we; -wire [7:0] csrbank2_dfii_pi2_wrdata0_w; -wire csrbank2_dfii_pi2_rddata3_re; -wire [7:0] csrbank2_dfii_pi2_rddata3_r; -wire csrbank2_dfii_pi2_rddata3_we; -wire [7:0] csrbank2_dfii_pi2_rddata3_w; -wire csrbank2_dfii_pi2_rddata2_re; -wire [7:0] csrbank2_dfii_pi2_rddata2_r; -wire csrbank2_dfii_pi2_rddata2_we; -wire [7:0] csrbank2_dfii_pi2_rddata2_w; -wire csrbank2_dfii_pi2_rddata1_re; -wire [7:0] csrbank2_dfii_pi2_rddata1_r; -wire csrbank2_dfii_pi2_rddata1_we; -wire [7:0] csrbank2_dfii_pi2_rddata1_w; -wire csrbank2_dfii_pi2_rddata0_re; -wire [7:0] csrbank2_dfii_pi2_rddata0_r; -wire csrbank2_dfii_pi2_rddata0_we; -wire [7:0] csrbank2_dfii_pi2_rddata0_w; +wire [31:0] csrbank2_dfii_pi2_wrdata0_w; +wire csrbank2_dfii_pi2_rddata_re; +wire [31:0] csrbank2_dfii_pi2_rddata_r; +wire csrbank2_dfii_pi2_rddata_we; +wire [31:0] csrbank2_dfii_pi2_rddata_w; wire csrbank2_dfii_pi3_command0_re; wire [5:0] csrbank2_dfii_pi3_command0_r; wire csrbank2_dfii_pi3_command0_we; wire [5:0] csrbank2_dfii_pi3_command0_w; -wire csrbank2_dfii_pi3_address1_re; -wire [5:0] csrbank2_dfii_pi3_address1_r; -wire csrbank2_dfii_pi3_address1_we; -wire [5:0] csrbank2_dfii_pi3_address1_w; wire csrbank2_dfii_pi3_address0_re; -wire [7:0] csrbank2_dfii_pi3_address0_r; +wire [13:0] csrbank2_dfii_pi3_address0_r; wire csrbank2_dfii_pi3_address0_we; -wire [7:0] csrbank2_dfii_pi3_address0_w; +wire [13:0] csrbank2_dfii_pi3_address0_w; wire csrbank2_dfii_pi3_baddress0_re; wire [2:0] csrbank2_dfii_pi3_baddress0_r; wire csrbank2_dfii_pi3_baddress0_we; wire [2:0] csrbank2_dfii_pi3_baddress0_w; -wire csrbank2_dfii_pi3_wrdata3_re; -wire [7:0] csrbank2_dfii_pi3_wrdata3_r; -wire csrbank2_dfii_pi3_wrdata3_we; -wire [7:0] csrbank2_dfii_pi3_wrdata3_w; -wire csrbank2_dfii_pi3_wrdata2_re; -wire [7:0] csrbank2_dfii_pi3_wrdata2_r; -wire csrbank2_dfii_pi3_wrdata2_we; -wire [7:0] csrbank2_dfii_pi3_wrdata2_w; -wire csrbank2_dfii_pi3_wrdata1_re; -wire [7:0] csrbank2_dfii_pi3_wrdata1_r; -wire csrbank2_dfii_pi3_wrdata1_we; -wire [7:0] csrbank2_dfii_pi3_wrdata1_w; wire csrbank2_dfii_pi3_wrdata0_re; -wire [7:0] csrbank2_dfii_pi3_wrdata0_r; +wire [31:0] csrbank2_dfii_pi3_wrdata0_r; wire csrbank2_dfii_pi3_wrdata0_we; -wire [7:0] csrbank2_dfii_pi3_wrdata0_w; -wire csrbank2_dfii_pi3_rddata3_re; -wire [7:0] csrbank2_dfii_pi3_rddata3_r; -wire csrbank2_dfii_pi3_rddata3_we; -wire [7:0] csrbank2_dfii_pi3_rddata3_w; -wire csrbank2_dfii_pi3_rddata2_re; -wire [7:0] csrbank2_dfii_pi3_rddata2_r; -wire csrbank2_dfii_pi3_rddata2_we; -wire [7:0] csrbank2_dfii_pi3_rddata2_w; -wire csrbank2_dfii_pi3_rddata1_re; -wire [7:0] csrbank2_dfii_pi3_rddata1_r; -wire csrbank2_dfii_pi3_rddata1_we; -wire [7:0] csrbank2_dfii_pi3_rddata1_w; -wire csrbank2_dfii_pi3_rddata0_re; -wire [7:0] csrbank2_dfii_pi3_rddata0_r; -wire csrbank2_dfii_pi3_rddata0_we; -wire [7:0] csrbank2_dfii_pi3_rddata0_w; +wire [31:0] csrbank2_dfii_pi3_wrdata0_w; +wire csrbank2_dfii_pi3_rddata_re; +wire [31:0] csrbank2_dfii_pi3_rddata_r; +wire csrbank2_dfii_pi3_rddata_we; +wire [31:0] csrbank2_dfii_pi3_rddata_w; reg csrbank2_sel = 1'd0; wire [13:0] adr; wire we; -wire [7:0] dat_w; -wire [7:0] dat_r; +wire [31:0] dat_w; +wire [31:0] dat_r; reg rhs_array_muxed0 = 1'd0; reg [13:0] rhs_array_muxed1 = 14'd0; reg [2:0] rhs_array_muxed2 = 3'd0; @@ -10730,7 +10618,7 @@ reg dummy_d_282; // synthesis translate_on always @(*) begin csrbank0_sel <= 1'd0; - csrbank0_sel <= (interface0_bank_bus_adr[13:11] == 2'd2); + csrbank0_sel <= (interface0_bank_bus_adr[13:9] == 2'd2); if (interface0_bank_bus_adr[0]) begin csrbank0_sel <= 1'd0; end @@ -10739,11 +10627,11 @@ always @(*) begin // synthesis translate_on end assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd0)); -assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd0)); +assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd0)); +assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd0)); assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd1)); -assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd1)); +assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd1)); +assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd1)); assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; @@ -10752,7 +10640,7 @@ reg dummy_d_283; // synthesis translate_on always @(*) begin csrbank1_sel <= 1'd0; - csrbank1_sel <= (interface1_bank_bus_adr[13:11] == 1'd0); + csrbank1_sel <= (interface1_bank_bus_adr[13:9] == 1'd0); if (interface1_bank_bus_adr[0]) begin csrbank1_sel <= 1'd0; end @@ -10761,35 +10649,35 @@ always @(*) begin // synthesis translate_on end assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; -assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd0)); -assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd0)); +assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd0)); +assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd0)); assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; -assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd1)); -assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd1)); +assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd1)); +assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd1)); assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd2)); -assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd2)); +assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd2)); +assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd2)); assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd3)); -assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd3)); +assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd3)); +assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd3)); assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd4)); -assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd4)); +assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd4)); +assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd4)); assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; -assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd5)); -assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd5)); +assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd5)); +assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd5)); assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd6)); -assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd6)); assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd7)); -assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd7)); assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd8)); -assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd8)); assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd9)); -assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd9)); assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0]; assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; @@ -10799,7 +10687,7 @@ reg dummy_d_284; // synthesis translate_on always @(*) begin csrbank2_sel <= 1'd0; - csrbank2_sel <= (interface2_bank_bus_adr[13:11] == 1'd1); + csrbank2_sel <= (interface2_bank_bus_adr[13:9] == 1'd1); if (interface2_bank_bus_adr[0]) begin csrbank2_sel <= 1'd0; end @@ -10808,217 +10696,105 @@ always @(*) begin // synthesis translate_on end assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; -assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd0)); -assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd0)); +assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd0)); +assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd0)); assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd1)); -assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd1)); +assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd1)); +assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd1)); assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd2)); -assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd2)); -assign csrbank2_dfii_pi0_address1_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi0_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd3)); -assign csrbank2_dfii_pi0_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd3)); -assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd4)); -assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd4)); +assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd2)); +assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd2)); +assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[13:0]; +assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd3)); +assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd3)); assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd5)); -assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd5)); -assign csrbank2_dfii_pi0_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd6)); -assign csrbank2_dfii_pi0_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd6)); -assign csrbank2_dfii_pi0_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd7)); -assign csrbank2_dfii_pi0_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd7)); -assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd8)); -assign csrbank2_dfii_pi0_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd8)); -assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd9)); -assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd9)); -assign csrbank2_dfii_pi0_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd10)); -assign csrbank2_dfii_pi0_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd10)); -assign csrbank2_dfii_pi0_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd11)); -assign csrbank2_dfii_pi0_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd11)); -assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd12)); -assign csrbank2_dfii_pi0_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd12)); -assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd13)); -assign csrbank2_dfii_pi0_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd13)); +assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd4)); +assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd4)); +assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd5)); +assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd5)); +assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd6)); +assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd6)); assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd14)); -assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd14)); +assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd7)); +assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd7)); assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd15)); -assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd15)); -assign csrbank2_dfii_pi1_address1_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi1_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd16)); -assign csrbank2_dfii_pi1_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd16)); -assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd17)); -assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd17)); +assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd8)); +assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd8)); +assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[13:0]; +assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd9)); +assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd9)); assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd18)); -assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd18)); -assign csrbank2_dfii_pi1_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd19)); -assign csrbank2_dfii_pi1_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd19)); -assign csrbank2_dfii_pi1_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd20)); -assign csrbank2_dfii_pi1_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd20)); -assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd21)); -assign csrbank2_dfii_pi1_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd21)); -assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd22)); -assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd22)); -assign csrbank2_dfii_pi1_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd23)); -assign csrbank2_dfii_pi1_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd23)); -assign csrbank2_dfii_pi1_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd24)); -assign csrbank2_dfii_pi1_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd24)); -assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd25)); -assign csrbank2_dfii_pi1_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd25)); -assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd26)); -assign csrbank2_dfii_pi1_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd26)); +assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd10)); +assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd10)); +assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd11)); +assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd11)); +assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd12)); +assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd12)); assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd27)); -assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd27)); +assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd13)); +assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd13)); assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd28)); -assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd28)); -assign csrbank2_dfii_pi2_address1_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi2_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd29)); -assign csrbank2_dfii_pi2_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd29)); -assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd30)); -assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd30)); +assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd14)); +assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd14)); +assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[13:0]; +assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd15)); +assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd15)); assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd31)); -assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd31)); -assign csrbank2_dfii_pi2_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd32)); -assign csrbank2_dfii_pi2_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd32)); -assign csrbank2_dfii_pi2_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd33)); -assign csrbank2_dfii_pi2_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd33)); -assign csrbank2_dfii_pi2_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd34)); -assign csrbank2_dfii_pi2_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd34)); -assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd35)); -assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd35)); -assign csrbank2_dfii_pi2_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd36)); -assign csrbank2_dfii_pi2_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd36)); -assign csrbank2_dfii_pi2_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd37)); -assign csrbank2_dfii_pi2_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd37)); -assign csrbank2_dfii_pi2_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd38)); -assign csrbank2_dfii_pi2_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd38)); -assign csrbank2_dfii_pi2_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd39)); -assign csrbank2_dfii_pi2_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd39)); +assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd16)); +assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd16)); +assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd17)); +assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd17)); +assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd18)); +assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd18)); assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd40)); -assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd40)); +assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd19)); +assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd19)); assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd41)); -assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd41)); -assign csrbank2_dfii_pi3_address1_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi3_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd42)); -assign csrbank2_dfii_pi3_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd42)); -assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd43)); -assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd43)); +assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd20)); +assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd20)); +assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[13:0]; +assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd21)); +assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd21)); assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd44)); -assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd44)); -assign csrbank2_dfii_pi3_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd45)); -assign csrbank2_dfii_pi3_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd45)); -assign csrbank2_dfii_pi3_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd46)); -assign csrbank2_dfii_pi3_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd46)); -assign csrbank2_dfii_pi3_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd47)); -assign csrbank2_dfii_pi3_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd47)); -assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd48)); -assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd48)); -assign csrbank2_dfii_pi3_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd49)); -assign csrbank2_dfii_pi3_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd49)); -assign csrbank2_dfii_pi3_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd50)); -assign csrbank2_dfii_pi3_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd50)); -assign csrbank2_dfii_pi3_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd51)); -assign csrbank2_dfii_pi3_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd51)); -assign csrbank2_dfii_pi3_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd52)); -assign csrbank2_dfii_pi3_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd52)); +assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd22)); +assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd22)); +assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd23)); +assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd23)); +assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd24)); +assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd24)); assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; -assign csrbank2_dfii_pi0_address1_w = litedramcore_phaseinjector0_address_storage[13:8]; -assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[7:0]; +assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0]; assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; -assign csrbank2_dfii_pi0_wrdata3_w = litedramcore_phaseinjector0_wrdata_storage[31:24]; -assign csrbank2_dfii_pi0_wrdata2_w = litedramcore_phaseinjector0_wrdata_storage[23:16]; -assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[15:8]; -assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[7:0]; -assign csrbank2_dfii_pi0_rddata3_w = litedramcore_phaseinjector0_status[31:24]; -assign csrbank2_dfii_pi0_rddata2_w = litedramcore_phaseinjector0_status[23:16]; -assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_status[15:8]; -assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_status[7:0]; -assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata0_we; +assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0]; +assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata_we; assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0]; -assign csrbank2_dfii_pi1_address1_w = litedramcore_phaseinjector1_address_storage[13:8]; -assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[7:0]; +assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0]; assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; -assign csrbank2_dfii_pi1_wrdata3_w = litedramcore_phaseinjector1_wrdata_storage[31:24]; -assign csrbank2_dfii_pi1_wrdata2_w = litedramcore_phaseinjector1_wrdata_storage[23:16]; -assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[15:8]; -assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[7:0]; -assign csrbank2_dfii_pi1_rddata3_w = litedramcore_phaseinjector1_status[31:24]; -assign csrbank2_dfii_pi1_rddata2_w = litedramcore_phaseinjector1_status[23:16]; -assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_status[15:8]; -assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_status[7:0]; -assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata0_we; +assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0]; +assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata_we; assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0]; -assign csrbank2_dfii_pi2_address1_w = litedramcore_phaseinjector2_address_storage[13:8]; -assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[7:0]; +assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0]; assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0]; -assign csrbank2_dfii_pi2_wrdata3_w = litedramcore_phaseinjector2_wrdata_storage[31:24]; -assign csrbank2_dfii_pi2_wrdata2_w = litedramcore_phaseinjector2_wrdata_storage[23:16]; -assign csrbank2_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[15:8]; -assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[7:0]; -assign csrbank2_dfii_pi2_rddata3_w = litedramcore_phaseinjector2_status[31:24]; -assign csrbank2_dfii_pi2_rddata2_w = litedramcore_phaseinjector2_status[23:16]; -assign csrbank2_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_status[15:8]; -assign csrbank2_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_status[7:0]; -assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata0_we; +assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0]; +assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0]; +assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata_we; assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0]; -assign csrbank2_dfii_pi3_address1_w = litedramcore_phaseinjector3_address_storage[13:8]; -assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[7:0]; +assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0]; assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0]; -assign csrbank2_dfii_pi3_wrdata3_w = litedramcore_phaseinjector3_wrdata_storage[31:24]; -assign csrbank2_dfii_pi3_wrdata2_w = litedramcore_phaseinjector3_wrdata_storage[23:16]; -assign csrbank2_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[15:8]; -assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[7:0]; -assign csrbank2_dfii_pi3_rddata3_w = litedramcore_phaseinjector3_status[31:24]; -assign csrbank2_dfii_pi3_rddata2_w = litedramcore_phaseinjector3_status[23:16]; -assign csrbank2_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_status[15:8]; -assign csrbank2_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_status[7:0]; -assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata0_we; +assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0]; +assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0]; +assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata_we; assign adr = csr_port_adr; assign we = csr_port_we; assign dat_w = csr_port_dat_w; @@ -14159,7 +13935,7 @@ always @(posedge sys_clk) begin new_master_rdata_valid8 <= new_master_rdata_valid7; interface0_bank_bus_dat_r <= 1'd0; if (csrbank0_sel) begin - case (interface0_bank_bus_adr[3]) + case (interface0_bank_bus_adr[1]) 1'd0: begin interface0_bank_bus_dat_r <= csrbank0_init_done0_w; end @@ -14178,7 +13954,7 @@ always @(posedge sys_clk) begin init_error_re <= csrbank0_init_error0_re; interface1_bank_bus_dat_r <= 1'd0; if (csrbank1_sel) begin - case (interface1_bank_bus_adr[6:3]) + case (interface1_bank_bus_adr[4:1]) 1'd0: begin interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; end @@ -14225,7 +14001,7 @@ always @(posedge sys_clk) begin a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; interface2_bank_bus_dat_r <= 1'd0; if (csrbank2_sel) begin - case (interface2_bank_bus_adr[8:3]) + case (interface2_bank_bus_adr[5:1]) 1'd0: begin interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; end @@ -14236,154 +14012,70 @@ always @(posedge sys_clk) begin interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; end 3'd4: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; end 3'd5: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; end 3'd6: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w; end 3'd7: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; end 4'd8: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w; + interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; end 4'd9: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; end 4'd10: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; end 4'd11: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; end 4'd12: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w; end 4'd13: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; end 4'd14: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; + interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; end 4'd15: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; end 5'd16: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; end 5'd17: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; end 5'd18: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w; end 5'd19: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata3_w; - end - 5'd20: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata2_w; - end - 5'd21: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w; - end - 5'd22: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; - end - 5'd23: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata3_w; - end - 5'd24: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata2_w; - end - 5'd25: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w; - end - 5'd26: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w; - end - 5'd27: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; - end - 5'd28: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; - end - 5'd29: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address1_w; - end - 5'd30: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; - end - 5'd31: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; - end - 6'd32: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata3_w; - end - 6'd33: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata2_w; - end - 6'd34: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata1_w; - end - 6'd35: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; - end - 6'd36: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata3_w; - end - 6'd37: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata2_w; - end - 6'd38: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata1_w; - end - 6'd39: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata0_w; - end - 6'd40: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; end - 6'd41: begin + 5'd20: begin interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; end - 6'd42: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address1_w; - end - 6'd43: begin + 5'd21: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; end - 6'd44: begin + 5'd22: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; end - 6'd45: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata3_w; - end - 6'd46: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata2_w; - end - 6'd47: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata1_w; - end - 6'd48: begin + 5'd23: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; end - 6'd49: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata3_w; - end - 6'd50: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata2_w; - end - 6'd51: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata1_w; - end - 6'd52: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata0_w; + 5'd24: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w; end endcase end @@ -14395,112 +14087,64 @@ always @(posedge sys_clk) begin litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; end litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; - if (csrbank2_dfii_pi0_address1_re) begin - litedramcore_phaseinjector0_address_storage[13:8] <= csrbank2_dfii_pi0_address1_r; - end if (csrbank2_dfii_pi0_address0_re) begin - litedramcore_phaseinjector0_address_storage[7:0] <= csrbank2_dfii_pi0_address0_r; + litedramcore_phaseinjector0_address_storage[13:0] <= csrbank2_dfii_pi0_address0_r; end litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; if (csrbank2_dfii_pi0_baddress0_re) begin litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; end litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; - if (csrbank2_dfii_pi0_wrdata3_re) begin - litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank2_dfii_pi0_wrdata3_r; - end - if (csrbank2_dfii_pi0_wrdata2_re) begin - litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank2_dfii_pi0_wrdata2_r; - end - if (csrbank2_dfii_pi0_wrdata1_re) begin - litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank2_dfii_pi0_wrdata1_r; - end if (csrbank2_dfii_pi0_wrdata0_re) begin - litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank2_dfii_pi0_wrdata0_r; + litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; end litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; if (csrbank2_dfii_pi1_command0_re) begin litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; end litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; - if (csrbank2_dfii_pi1_address1_re) begin - litedramcore_phaseinjector1_address_storage[13:8] <= csrbank2_dfii_pi1_address1_r; - end if (csrbank2_dfii_pi1_address0_re) begin - litedramcore_phaseinjector1_address_storage[7:0] <= csrbank2_dfii_pi1_address0_r; + litedramcore_phaseinjector1_address_storage[13:0] <= csrbank2_dfii_pi1_address0_r; end litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; if (csrbank2_dfii_pi1_baddress0_re) begin litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; end litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; - if (csrbank2_dfii_pi1_wrdata3_re) begin - litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank2_dfii_pi1_wrdata3_r; - end - if (csrbank2_dfii_pi1_wrdata2_re) begin - litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank2_dfii_pi1_wrdata2_r; - end - if (csrbank2_dfii_pi1_wrdata1_re) begin - litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank2_dfii_pi1_wrdata1_r; - end if (csrbank2_dfii_pi1_wrdata0_re) begin - litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank2_dfii_pi1_wrdata0_r; + litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; end litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; if (csrbank2_dfii_pi2_command0_re) begin litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; end litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; - if (csrbank2_dfii_pi2_address1_re) begin - litedramcore_phaseinjector2_address_storage[13:8] <= csrbank2_dfii_pi2_address1_r; - end if (csrbank2_dfii_pi2_address0_re) begin - litedramcore_phaseinjector2_address_storage[7:0] <= csrbank2_dfii_pi2_address0_r; + litedramcore_phaseinjector2_address_storage[13:0] <= csrbank2_dfii_pi2_address0_r; end litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; if (csrbank2_dfii_pi2_baddress0_re) begin litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; end litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; - if (csrbank2_dfii_pi2_wrdata3_re) begin - litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank2_dfii_pi2_wrdata3_r; - end - if (csrbank2_dfii_pi2_wrdata2_re) begin - litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank2_dfii_pi2_wrdata2_r; - end - if (csrbank2_dfii_pi2_wrdata1_re) begin - litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank2_dfii_pi2_wrdata1_r; - end if (csrbank2_dfii_pi2_wrdata0_re) begin - litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank2_dfii_pi2_wrdata0_r; + litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; end litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; if (csrbank2_dfii_pi3_command0_re) begin litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; end litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; - if (csrbank2_dfii_pi3_address1_re) begin - litedramcore_phaseinjector3_address_storage[13:8] <= csrbank2_dfii_pi3_address1_r; - end if (csrbank2_dfii_pi3_address0_re) begin - litedramcore_phaseinjector3_address_storage[7:0] <= csrbank2_dfii_pi3_address0_r; + litedramcore_phaseinjector3_address_storage[13:0] <= csrbank2_dfii_pi3_address0_r; end litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; if (csrbank2_dfii_pi3_baddress0_re) begin litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; end litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; - if (csrbank2_dfii_pi3_wrdata3_re) begin - litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank2_dfii_pi3_wrdata3_r; - end - if (csrbank2_dfii_pi3_wrdata2_re) begin - litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank2_dfii_pi3_wrdata2_r; - end - if (csrbank2_dfii_pi3_wrdata1_re) begin - litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank2_dfii_pi3_wrdata1_r; - end if (csrbank2_dfii_pi3_wrdata0_re) begin - litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank2_dfii_pi3_wrdata0_r; + litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; end litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; if (sys_rst) begin diff --git a/litedram/generated/nexys-video/litedram-wrapper.vhdl b/litedram/generated/nexys-video/litedram-wrapper.vhdl index 475e088..46ae4b1 100644 --- a/litedram/generated/nexys-video/litedram-wrapper.vhdl +++ b/litedram/generated/nexys-video/litedram-wrapper.vhdl @@ -82,8 +82,8 @@ architecture behaviour of litedram_wrapper is user_rst : out std_ulogic; csr_port0_adr : in std_ulogic_vector(13 downto 0); csr_port0_we : in std_ulogic; - csr_port0_dat_w : in std_ulogic_vector(7 downto 0); - csr_port0_dat_r : out std_ulogic_vector(7 downto 0); + csr_port0_dat_w : in std_ulogic_vector(31 downto 0); + csr_port0_dat_r : out std_ulogic_vector(31 downto 0); user_port_native_0_cmd_valid : in std_ulogic; user_port_native_0_cmd_ready : out std_ulogic; user_port_native_0_cmd_we : in std_ulogic; @@ -116,8 +116,8 @@ architecture behaviour of litedram_wrapper is signal csr_port0_adr : std_ulogic_vector(13 downto 0); signal csr_port0_we : std_ulogic; - signal csr_port0_dat_w : std_ulogic_vector(7 downto 0); - signal csr_port0_dat_r : std_ulogic_vector(7 downto 0); + signal csr_port0_dat_w : std_ulogic_vector(31 downto 0); + signal csr_port0_dat_r : std_ulogic_vector(31 downto 0); signal csr_port_read_comb : std_ulogic_vector(63 downto 0); signal csr_valid : std_ulogic; signal csr_write_valid : std_ulogic; @@ -205,8 +205,8 @@ begin -- DRAM CSR interface signals. We only support access to the bottom byte csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; csr_write_valid <= wb_in.we and wb_in.sel(0); - csr_port0_adr <= wb_in.adr(13 downto 0) when wb_is_csr = '1' else (others => '0'); - csr_port0_dat_w <= wb_in.dat(7 downto 0); + csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0'); + csr_port0_dat_w <= wb_in.dat(31 downto 0); csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; -- Wishbone out signals @@ -215,7 +215,7 @@ begin user_port0_wdata_ready when state = MWRITE else user_port0_rdata_valid when state = MREAD else '0'; - csr_port_read_comb <= x"00000000000000" & csr_port0_dat_r; + csr_port_read_comb <= x"00000000" & csr_port0_dat_r; wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else wb_init_out.dat when wb_is_init = '1' else user_port0_rdata_data(127 downto 64) when ad3 = '1' else diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init index d07879f..7708f27 100644 --- a/litedram/generated/nexys-video/litedram_core.init +++ b/litedram/generated/nexys-video/litedram_core.init @@ -513,17 +513,17 @@ a64b5a7d14004a39 38429d003c4c0001 600000003d20c000 7929002061292000 -3d40c000f9228040 +3d40c000f9228000 614a201839200035 7c0004ac794a0020 4e8000207d2057aa 0000000000000000 3c4c000100000000 6000000038429cbc -39290010e9228040 +39290010e9228000 7d204eaa7c0004ac 4082ffe871290008 -e922804060000000 +e922800060000000 7c604faa7c0004ac 000000004e800020 0000000000000000 @@ -533,7 +533,7 @@ fbc1fff07c0802a6 f80100107c7f1b78 7fbff040f821ffd1 38210030409e000c -893f00004800194c +893f000048001908 409e000c2f89000a 4bffff813860000d 3bff0001887f0000 @@ -549,11 +549,11 @@ f88101983bc10020 f8e101b038c10198 f90101b87fc3f378 f94101c8f92101c0 -60000000480012ed +60000000480012a9 7c641b787c7f1b78 4bffff457fc3f378 7fe3fb7838210170 -00000000480018ac +0000000048001868 0000028001000000 38429b983c4c0001 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+0000000000000830 +0000000000000860 +0000000000000890 +00000000000008c0 6f6e204d41524453 207265646e752077 6572617764726168 diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v index dd74efd..854f4c6 100644 --- a/litedram/generated/nexys-video/litedram_core.v +++ b/litedram/generated/nexys-video/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 10:54:05 +// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 11:57:13 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, @@ -24,8 +24,8 @@ module litedram_core( output wire init_error, input wire [13:0] csr_port0_adr, input wire csr_port0_we, - input wire [7:0] csr_port0_dat_w, - output wire [7:0] csr_port0_dat_r, + input wire [31:0] csr_port0_dat_w, + output wire [31:0] csr_port0_dat_r, output wire user_clk, output wire user_rst, input wire user_port_native_0_cmd_valid, @@ -1485,8 +1485,8 @@ reg init_error_storage = 1'd0; reg init_error_re = 1'd0; wire [13:0] csr_port_adr; wire csr_port_we; -wire [7:0] csr_port_dat_w; -wire [7:0] csr_port_dat_r; +wire [31:0] csr_port_dat_w; +wire [31:0] csr_port_dat_r; wire user_port_cmd_valid; wire user_port_cmd_ready; wire user_port_cmd_payload_we; @@ -1566,8 +1566,8 @@ reg new_master_rdata_valid7 = 1'd0; reg new_master_rdata_valid8 = 1'd0; wire [13:0] interface0_bank_bus_adr; wire interface0_bank_bus_we; -wire [7:0] interface0_bank_bus_dat_w; -reg [7:0] interface0_bank_bus_dat_r = 8'd0; +wire [31:0] interface0_bank_bus_dat_w; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; wire csrbank0_init_done0_re; wire csrbank0_init_done0_r; wire csrbank0_init_done0_we; @@ -1579,8 +1579,8 @@ wire csrbank0_init_error0_w; reg csrbank0_sel = 1'd0; wire [13:0] interface1_bank_bus_adr; wire interface1_bank_bus_we; -wire [7:0] interface1_bank_bus_dat_w; -reg [7:0] interface1_bank_bus_dat_r = 8'd0; +wire [31:0] interface1_bank_bus_dat_w; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; wire csrbank1_half_sys8x_taps0_re; wire [4:0] csrbank1_half_sys8x_taps0_r; wire csrbank1_half_sys8x_taps0_we; @@ -1596,8 +1596,8 @@ wire [1:0] csrbank1_dly_sel0_w; reg csrbank1_sel = 1'd0; wire [13:0] interface2_bank_bus_adr; wire interface2_bank_bus_we; -wire [7:0] interface2_bank_bus_dat_w; -reg [7:0] interface2_bank_bus_dat_r = 8'd0; +wire [31:0] interface2_bank_bus_dat_w; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; wire csrbank2_dfii_control0_re; wire [3:0] csrbank2_dfii_control0_r; wire csrbank2_dfii_control0_we; @@ -1606,199 +1606,87 @@ wire csrbank2_dfii_pi0_command0_re; wire [5:0] csrbank2_dfii_pi0_command0_r; wire csrbank2_dfii_pi0_command0_we; wire [5:0] csrbank2_dfii_pi0_command0_w; -wire csrbank2_dfii_pi0_address1_re; -wire [6:0] csrbank2_dfii_pi0_address1_r; -wire csrbank2_dfii_pi0_address1_we; -wire [6:0] csrbank2_dfii_pi0_address1_w; wire csrbank2_dfii_pi0_address0_re; -wire [7:0] csrbank2_dfii_pi0_address0_r; +wire [14:0] csrbank2_dfii_pi0_address0_r; wire csrbank2_dfii_pi0_address0_we; -wire [7:0] csrbank2_dfii_pi0_address0_w; +wire [14:0] csrbank2_dfii_pi0_address0_w; wire csrbank2_dfii_pi0_baddress0_re; wire [2:0] csrbank2_dfii_pi0_baddress0_r; wire csrbank2_dfii_pi0_baddress0_we; wire [2:0] csrbank2_dfii_pi0_baddress0_w; -wire csrbank2_dfii_pi0_wrdata3_re; -wire [7:0] csrbank2_dfii_pi0_wrdata3_r; -wire csrbank2_dfii_pi0_wrdata3_we; -wire [7:0] csrbank2_dfii_pi0_wrdata3_w; -wire csrbank2_dfii_pi0_wrdata2_re; -wire [7:0] csrbank2_dfii_pi0_wrdata2_r; -wire csrbank2_dfii_pi0_wrdata2_we; -wire [7:0] csrbank2_dfii_pi0_wrdata2_w; -wire csrbank2_dfii_pi0_wrdata1_re; -wire [7:0] csrbank2_dfii_pi0_wrdata1_r; -wire csrbank2_dfii_pi0_wrdata1_we; -wire [7:0] csrbank2_dfii_pi0_wrdata1_w; wire csrbank2_dfii_pi0_wrdata0_re; -wire [7:0] csrbank2_dfii_pi0_wrdata0_r; +wire [31:0] csrbank2_dfii_pi0_wrdata0_r; wire csrbank2_dfii_pi0_wrdata0_we; -wire [7:0] csrbank2_dfii_pi0_wrdata0_w; -wire csrbank2_dfii_pi0_rddata3_re; -wire [7:0] csrbank2_dfii_pi0_rddata3_r; -wire csrbank2_dfii_pi0_rddata3_we; -wire [7:0] csrbank2_dfii_pi0_rddata3_w; -wire csrbank2_dfii_pi0_rddata2_re; -wire [7:0] csrbank2_dfii_pi0_rddata2_r; -wire csrbank2_dfii_pi0_rddata2_we; -wire [7:0] csrbank2_dfii_pi0_rddata2_w; -wire csrbank2_dfii_pi0_rddata1_re; -wire [7:0] csrbank2_dfii_pi0_rddata1_r; -wire csrbank2_dfii_pi0_rddata1_we; -wire [7:0] csrbank2_dfii_pi0_rddata1_w; -wire csrbank2_dfii_pi0_rddata0_re; -wire [7:0] csrbank2_dfii_pi0_rddata0_r; -wire csrbank2_dfii_pi0_rddata0_we; -wire [7:0] csrbank2_dfii_pi0_rddata0_w; +wire [31:0] csrbank2_dfii_pi0_wrdata0_w; +wire csrbank2_dfii_pi0_rddata_re; +wire [31:0] csrbank2_dfii_pi0_rddata_r; +wire csrbank2_dfii_pi0_rddata_we; +wire [31:0] csrbank2_dfii_pi0_rddata_w; wire csrbank2_dfii_pi1_command0_re; wire [5:0] csrbank2_dfii_pi1_command0_r; wire csrbank2_dfii_pi1_command0_we; wire [5:0] csrbank2_dfii_pi1_command0_w; -wire csrbank2_dfii_pi1_address1_re; -wire [6:0] csrbank2_dfii_pi1_address1_r; -wire csrbank2_dfii_pi1_address1_we; -wire [6:0] csrbank2_dfii_pi1_address1_w; wire csrbank2_dfii_pi1_address0_re; -wire [7:0] csrbank2_dfii_pi1_address0_r; +wire [14:0] csrbank2_dfii_pi1_address0_r; wire csrbank2_dfii_pi1_address0_we; -wire [7:0] csrbank2_dfii_pi1_address0_w; +wire [14:0] csrbank2_dfii_pi1_address0_w; wire csrbank2_dfii_pi1_baddress0_re; wire [2:0] csrbank2_dfii_pi1_baddress0_r; wire csrbank2_dfii_pi1_baddress0_we; wire [2:0] csrbank2_dfii_pi1_baddress0_w; -wire csrbank2_dfii_pi1_wrdata3_re; -wire [7:0] csrbank2_dfii_pi1_wrdata3_r; -wire csrbank2_dfii_pi1_wrdata3_we; -wire [7:0] csrbank2_dfii_pi1_wrdata3_w; -wire csrbank2_dfii_pi1_wrdata2_re; -wire [7:0] csrbank2_dfii_pi1_wrdata2_r; -wire csrbank2_dfii_pi1_wrdata2_we; -wire [7:0] csrbank2_dfii_pi1_wrdata2_w; -wire csrbank2_dfii_pi1_wrdata1_re; -wire [7:0] csrbank2_dfii_pi1_wrdata1_r; -wire csrbank2_dfii_pi1_wrdata1_we; -wire [7:0] csrbank2_dfii_pi1_wrdata1_w; wire csrbank2_dfii_pi1_wrdata0_re; -wire [7:0] csrbank2_dfii_pi1_wrdata0_r; +wire [31:0] csrbank2_dfii_pi1_wrdata0_r; wire csrbank2_dfii_pi1_wrdata0_we; -wire [7:0] csrbank2_dfii_pi1_wrdata0_w; -wire csrbank2_dfii_pi1_rddata3_re; -wire [7:0] csrbank2_dfii_pi1_rddata3_r; -wire csrbank2_dfii_pi1_rddata3_we; -wire [7:0] csrbank2_dfii_pi1_rddata3_w; -wire csrbank2_dfii_pi1_rddata2_re; -wire [7:0] csrbank2_dfii_pi1_rddata2_r; -wire csrbank2_dfii_pi1_rddata2_we; -wire [7:0] csrbank2_dfii_pi1_rddata2_w; -wire csrbank2_dfii_pi1_rddata1_re; -wire [7:0] csrbank2_dfii_pi1_rddata1_r; -wire csrbank2_dfii_pi1_rddata1_we; -wire [7:0] csrbank2_dfii_pi1_rddata1_w; -wire csrbank2_dfii_pi1_rddata0_re; -wire [7:0] csrbank2_dfii_pi1_rddata0_r; -wire csrbank2_dfii_pi1_rddata0_we; -wire [7:0] csrbank2_dfii_pi1_rddata0_w; +wire [31:0] csrbank2_dfii_pi1_wrdata0_w; +wire csrbank2_dfii_pi1_rddata_re; +wire [31:0] csrbank2_dfii_pi1_rddata_r; +wire csrbank2_dfii_pi1_rddata_we; +wire [31:0] csrbank2_dfii_pi1_rddata_w; wire csrbank2_dfii_pi2_command0_re; wire [5:0] csrbank2_dfii_pi2_command0_r; wire csrbank2_dfii_pi2_command0_we; wire [5:0] csrbank2_dfii_pi2_command0_w; -wire csrbank2_dfii_pi2_address1_re; -wire [6:0] csrbank2_dfii_pi2_address1_r; -wire csrbank2_dfii_pi2_address1_we; -wire [6:0] csrbank2_dfii_pi2_address1_w; wire csrbank2_dfii_pi2_address0_re; -wire [7:0] csrbank2_dfii_pi2_address0_r; +wire [14:0] csrbank2_dfii_pi2_address0_r; wire csrbank2_dfii_pi2_address0_we; -wire [7:0] csrbank2_dfii_pi2_address0_w; +wire [14:0] csrbank2_dfii_pi2_address0_w; wire csrbank2_dfii_pi2_baddress0_re; wire [2:0] csrbank2_dfii_pi2_baddress0_r; wire csrbank2_dfii_pi2_baddress0_we; wire [2:0] csrbank2_dfii_pi2_baddress0_w; -wire csrbank2_dfii_pi2_wrdata3_re; -wire [7:0] csrbank2_dfii_pi2_wrdata3_r; -wire csrbank2_dfii_pi2_wrdata3_we; -wire [7:0] csrbank2_dfii_pi2_wrdata3_w; -wire csrbank2_dfii_pi2_wrdata2_re; -wire [7:0] csrbank2_dfii_pi2_wrdata2_r; -wire csrbank2_dfii_pi2_wrdata2_we; -wire [7:0] csrbank2_dfii_pi2_wrdata2_w; -wire csrbank2_dfii_pi2_wrdata1_re; -wire [7:0] csrbank2_dfii_pi2_wrdata1_r; -wire csrbank2_dfii_pi2_wrdata1_we; -wire [7:0] csrbank2_dfii_pi2_wrdata1_w; wire csrbank2_dfii_pi2_wrdata0_re; -wire [7:0] csrbank2_dfii_pi2_wrdata0_r; +wire [31:0] csrbank2_dfii_pi2_wrdata0_r; wire csrbank2_dfii_pi2_wrdata0_we; -wire [7:0] csrbank2_dfii_pi2_wrdata0_w; -wire csrbank2_dfii_pi2_rddata3_re; -wire [7:0] csrbank2_dfii_pi2_rddata3_r; -wire csrbank2_dfii_pi2_rddata3_we; -wire [7:0] csrbank2_dfii_pi2_rddata3_w; -wire csrbank2_dfii_pi2_rddata2_re; -wire [7:0] csrbank2_dfii_pi2_rddata2_r; -wire csrbank2_dfii_pi2_rddata2_we; -wire [7:0] csrbank2_dfii_pi2_rddata2_w; -wire csrbank2_dfii_pi2_rddata1_re; -wire [7:0] csrbank2_dfii_pi2_rddata1_r; -wire csrbank2_dfii_pi2_rddata1_we; -wire [7:0] csrbank2_dfii_pi2_rddata1_w; -wire csrbank2_dfii_pi2_rddata0_re; -wire [7:0] csrbank2_dfii_pi2_rddata0_r; -wire csrbank2_dfii_pi2_rddata0_we; -wire [7:0] csrbank2_dfii_pi2_rddata0_w; +wire [31:0] csrbank2_dfii_pi2_wrdata0_w; +wire csrbank2_dfii_pi2_rddata_re; +wire [31:0] csrbank2_dfii_pi2_rddata_r; +wire csrbank2_dfii_pi2_rddata_we; +wire [31:0] csrbank2_dfii_pi2_rddata_w; wire csrbank2_dfii_pi3_command0_re; wire [5:0] csrbank2_dfii_pi3_command0_r; wire csrbank2_dfii_pi3_command0_we; wire [5:0] csrbank2_dfii_pi3_command0_w; -wire csrbank2_dfii_pi3_address1_re; -wire [6:0] csrbank2_dfii_pi3_address1_r; -wire csrbank2_dfii_pi3_address1_we; -wire [6:0] csrbank2_dfii_pi3_address1_w; wire csrbank2_dfii_pi3_address0_re; -wire [7:0] csrbank2_dfii_pi3_address0_r; +wire [14:0] csrbank2_dfii_pi3_address0_r; wire csrbank2_dfii_pi3_address0_we; -wire [7:0] csrbank2_dfii_pi3_address0_w; +wire [14:0] csrbank2_dfii_pi3_address0_w; wire csrbank2_dfii_pi3_baddress0_re; wire [2:0] csrbank2_dfii_pi3_baddress0_r; wire csrbank2_dfii_pi3_baddress0_we; wire [2:0] csrbank2_dfii_pi3_baddress0_w; -wire csrbank2_dfii_pi3_wrdata3_re; -wire [7:0] csrbank2_dfii_pi3_wrdata3_r; -wire csrbank2_dfii_pi3_wrdata3_we; -wire [7:0] csrbank2_dfii_pi3_wrdata3_w; -wire csrbank2_dfii_pi3_wrdata2_re; -wire [7:0] csrbank2_dfii_pi3_wrdata2_r; -wire csrbank2_dfii_pi3_wrdata2_we; -wire [7:0] csrbank2_dfii_pi3_wrdata2_w; -wire csrbank2_dfii_pi3_wrdata1_re; -wire [7:0] csrbank2_dfii_pi3_wrdata1_r; -wire csrbank2_dfii_pi3_wrdata1_we; -wire [7:0] csrbank2_dfii_pi3_wrdata1_w; wire csrbank2_dfii_pi3_wrdata0_re; -wire [7:0] csrbank2_dfii_pi3_wrdata0_r; +wire [31:0] csrbank2_dfii_pi3_wrdata0_r; wire csrbank2_dfii_pi3_wrdata0_we; -wire [7:0] csrbank2_dfii_pi3_wrdata0_w; -wire csrbank2_dfii_pi3_rddata3_re; -wire [7:0] csrbank2_dfii_pi3_rddata3_r; -wire csrbank2_dfii_pi3_rddata3_we; -wire [7:0] csrbank2_dfii_pi3_rddata3_w; -wire csrbank2_dfii_pi3_rddata2_re; -wire [7:0] csrbank2_dfii_pi3_rddata2_r; -wire csrbank2_dfii_pi3_rddata2_we; -wire [7:0] csrbank2_dfii_pi3_rddata2_w; -wire csrbank2_dfii_pi3_rddata1_re; -wire [7:0] csrbank2_dfii_pi3_rddata1_r; -wire csrbank2_dfii_pi3_rddata1_we; -wire [7:0] csrbank2_dfii_pi3_rddata1_w; -wire csrbank2_dfii_pi3_rddata0_re; -wire [7:0] csrbank2_dfii_pi3_rddata0_r; -wire csrbank2_dfii_pi3_rddata0_we; -wire [7:0] csrbank2_dfii_pi3_rddata0_w; +wire [31:0] csrbank2_dfii_pi3_wrdata0_w; +wire csrbank2_dfii_pi3_rddata_re; +wire [31:0] csrbank2_dfii_pi3_rddata_r; +wire csrbank2_dfii_pi3_rddata_we; +wire [31:0] csrbank2_dfii_pi3_rddata_w; reg csrbank2_sel = 1'd0; wire [13:0] adr; wire we; -wire [7:0] dat_w; -wire [7:0] dat_r; +wire [31:0] dat_w; +wire [31:0] dat_r; reg rhs_array_muxed0 = 1'd0; reg [14:0] rhs_array_muxed1 = 15'd0; reg [2:0] rhs_array_muxed2 = 3'd0; @@ -2848,11 +2736,11 @@ assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; reg dummy_d_22; // synthesis translate_on always @(*) begin - litedramcore_master_p2_ras_n <= 1'd1; + litedramcore_master_p1_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; + litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; end else begin - litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n; + litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n; end // synthesis translate_off dummy_d_22 = dummy_s; @@ -2863,9 +2751,9 @@ end reg dummy_d_23; // synthesis translate_on always @(*) begin - litedramcore_slave_p2_rddata <= 32'd0; + litedramcore_slave_p1_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; + litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; end else begin end // synthesis translate_off @@ -2877,11 +2765,11 @@ end reg dummy_d_24; // synthesis translate_on always @(*) begin - litedramcore_master_p2_we_n <= 1'd1; + litedramcore_master_p1_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; + litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; end else begin - litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; + litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n; end // synthesis translate_off dummy_d_24 = dummy_s; @@ -2892,9 +2780,9 @@ end reg dummy_d_25; // synthesis translate_on always @(*) begin - litedramcore_slave_p2_rddata_valid <= 1'd0; + litedramcore_slave_p1_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end else begin end // synthesis translate_off @@ -2906,11 +2794,11 @@ end reg dummy_d_26; // synthesis translate_on always @(*) begin - litedramcore_master_p2_cke <= 1'd0; + litedramcore_master_p1_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; + litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; end else begin - litedramcore_master_p2_cke <= litedramcore_inti_p2_cke; + litedramcore_master_p1_cke <= litedramcore_inti_p1_cke; end // synthesis translate_off dummy_d_26 = dummy_s; @@ -2921,11 +2809,11 @@ end reg dummy_d_27; // synthesis translate_on always @(*) begin - litedramcore_master_p2_odt <= 1'd0; + litedramcore_master_p1_odt <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; + litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; end else begin - litedramcore_master_p2_odt <= litedramcore_inti_p2_odt; + litedramcore_master_p1_odt <= litedramcore_inti_p1_odt; end // synthesis translate_off dummy_d_27 = dummy_s; @@ -2936,11 +2824,11 @@ end reg dummy_d_28; // synthesis translate_on always @(*) begin - litedramcore_master_p2_reset_n <= 1'd0; + litedramcore_master_p1_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; + litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; end else begin - litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n; + litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; end // synthesis translate_off dummy_d_28 = dummy_s; @@ -2951,11 +2839,11 @@ end reg dummy_d_29; // synthesis translate_on always @(*) begin - litedramcore_master_p2_act_n <= 1'd1; + litedramcore_master_p1_act_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; + litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; end else begin - litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n; + litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n; end // synthesis translate_off dummy_d_29 = dummy_s; @@ -2966,11 +2854,11 @@ end reg dummy_d_30; // synthesis translate_on always @(*) begin - litedramcore_master_p2_wrdata <= 32'd0; + litedramcore_master_p1_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; + litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; end else begin - litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata; + litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata; end // synthesis translate_off dummy_d_30 = dummy_s; @@ -2981,10 +2869,10 @@ end reg dummy_d_31; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_rddata <= 32'd0; + litedramcore_inti_p2_rddata <= 32'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata; + litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; end // synthesis translate_off dummy_d_31 = dummy_s; @@ -2995,11 +2883,11 @@ end reg dummy_d_32; // synthesis translate_on always @(*) begin - litedramcore_master_p2_wrdata_en <= 1'd0; + litedramcore_master_p1_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; + litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en; + litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; end // synthesis translate_off dummy_d_32 = dummy_s; @@ -3010,10 +2898,10 @@ end reg dummy_d_33; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_rddata_valid <= 1'd0; + litedramcore_inti_p2_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end // synthesis translate_off dummy_d_33 = dummy_s; @@ -3024,11 +2912,11 @@ end reg dummy_d_34; // synthesis translate_on always @(*) begin - litedramcore_master_p2_wrdata_mask <= 4'd0; + litedramcore_master_p1_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; + litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask; + litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; end // synthesis translate_off dummy_d_34 = dummy_s; @@ -3039,11 +2927,11 @@ end reg dummy_d_35; // synthesis translate_on always @(*) begin - litedramcore_master_p2_rddata_en <= 1'd0; + litedramcore_master_p1_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; + litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; end else begin - litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en; + litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; end // synthesis translate_off dummy_d_35 = dummy_s; @@ -3054,11 +2942,11 @@ end reg dummy_d_36; // synthesis translate_on always @(*) begin - litedramcore_master_p3_address <= 15'd0; + litedramcore_master_p2_address <= 15'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_address <= litedramcore_slave_p3_address; + litedramcore_master_p2_address <= litedramcore_slave_p2_address; end else begin - litedramcore_master_p3_address <= litedramcore_inti_p3_address; + litedramcore_master_p2_address <= litedramcore_inti_p2_address; end // synthesis translate_off dummy_d_36 = dummy_s; @@ -3069,11 +2957,11 @@ end reg dummy_d_37; // synthesis translate_on always @(*) begin - litedramcore_master_p3_bank <= 3'd0; + litedramcore_master_p2_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; + litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; end else begin - litedramcore_master_p3_bank <= litedramcore_inti_p3_bank; + litedramcore_master_p2_bank <= litedramcore_inti_p2_bank; end // synthesis translate_off dummy_d_37 = dummy_s; @@ -3084,11 +2972,11 @@ end reg dummy_d_38; // synthesis translate_on always @(*) begin - litedramcore_master_p3_cas_n <= 1'd1; + litedramcore_master_p2_cas_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; + litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; end else begin - litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n; + litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n; end // synthesis translate_off dummy_d_38 = dummy_s; @@ -3099,11 +2987,11 @@ end reg dummy_d_39; // synthesis translate_on always @(*) begin - litedramcore_master_p3_cs_n <= 1'd1; + litedramcore_master_p2_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; + litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; end else begin - litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n; + litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n; end // synthesis translate_off dummy_d_39 = dummy_s; @@ -3114,11 +3002,11 @@ end reg dummy_d_40; // synthesis translate_on always @(*) begin - litedramcore_master_p3_ras_n <= 1'd1; + litedramcore_master_p2_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; + litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; end else begin - litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n; + litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n; end // synthesis translate_off dummy_d_40 = dummy_s; @@ -3129,9 +3017,9 @@ end reg dummy_d_41; // synthesis translate_on always @(*) begin - litedramcore_slave_p3_rddata <= 32'd0; + litedramcore_slave_p2_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; + litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; end else begin end // synthesis translate_off @@ -3143,11 +3031,11 @@ end reg dummy_d_42; // synthesis translate_on always @(*) begin - litedramcore_master_p3_we_n <= 1'd1; + litedramcore_master_p2_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; + litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; end else begin - litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n; + litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; end // synthesis translate_off dummy_d_42 = dummy_s; @@ -3158,9 +3046,9 @@ end reg dummy_d_43; // synthesis translate_on always @(*) begin - litedramcore_slave_p3_rddata_valid <= 1'd0; + litedramcore_slave_p2_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end else begin end // synthesis translate_off @@ -3172,11 +3060,11 @@ end reg dummy_d_44; // synthesis translate_on always @(*) begin - litedramcore_master_p3_cke <= 1'd0; + litedramcore_master_p2_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; + litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; end else begin - litedramcore_master_p3_cke <= litedramcore_inti_p3_cke; + litedramcore_master_p2_cke <= litedramcore_inti_p2_cke; end // synthesis translate_off dummy_d_44 = dummy_s; @@ -3187,11 +3075,11 @@ end reg dummy_d_45; // synthesis translate_on always @(*) begin - litedramcore_master_p3_odt <= 1'd0; + litedramcore_master_p2_odt <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; + litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; end else begin - litedramcore_master_p3_odt <= litedramcore_inti_p3_odt; + litedramcore_master_p2_odt <= litedramcore_inti_p2_odt; end // synthesis translate_off dummy_d_45 = dummy_s; @@ -3202,11 +3090,11 @@ end reg dummy_d_46; // synthesis translate_on always @(*) begin - litedramcore_master_p3_reset_n <= 1'd0; + litedramcore_master_p2_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; + litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; end else begin - litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n; + litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n; end // synthesis translate_off dummy_d_46 = dummy_s; @@ -3217,11 +3105,11 @@ end reg dummy_d_47; // synthesis translate_on always @(*) begin - litedramcore_master_p3_act_n <= 1'd1; + litedramcore_master_p2_act_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; + litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; end else begin - litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n; + litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n; end // synthesis translate_off dummy_d_47 = dummy_s; @@ -3232,11 +3120,11 @@ end reg dummy_d_48; // synthesis translate_on always @(*) begin - litedramcore_master_p3_wrdata <= 32'd0; + litedramcore_master_p2_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; + litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; end else begin - litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata; + litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata; end // synthesis translate_off dummy_d_48 = dummy_s; @@ -3247,10 +3135,10 @@ end reg dummy_d_49; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_rddata <= 32'd0; + litedramcore_inti_p3_rddata <= 32'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata; + litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata; end // synthesis translate_off dummy_d_49 = dummy_s; @@ -3261,11 +3149,11 @@ end reg dummy_d_50; // synthesis translate_on always @(*) begin - litedramcore_master_p3_wrdata_en <= 1'd0; + litedramcore_master_p2_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; + litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en; + litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en; end // synthesis translate_off dummy_d_50 = dummy_s; @@ -3276,10 +3164,10 @@ end reg dummy_d_51; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_rddata_valid <= 1'd0; + litedramcore_inti_p3_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end // synthesis translate_off dummy_d_51 = dummy_s; @@ -3290,11 +3178,11 @@ end reg dummy_d_52; // synthesis translate_on always @(*) begin - litedramcore_master_p3_wrdata_mask <= 4'd0; + litedramcore_master_p2_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; + litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask; + litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask; end // synthesis translate_off dummy_d_52 = dummy_s; @@ -3305,11 +3193,11 @@ end reg dummy_d_53; // synthesis translate_on always @(*) begin - litedramcore_master_p3_rddata_en <= 1'd0; + litedramcore_master_p2_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; + litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; end else begin - litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en; + litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en; end // synthesis translate_off dummy_d_53 = dummy_s; @@ -3320,11 +3208,11 @@ end reg dummy_d_54; // synthesis translate_on always @(*) begin - litedramcore_master_p0_address <= 15'd0; + litedramcore_master_p3_address <= 15'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_address <= litedramcore_slave_p0_address; + litedramcore_master_p3_address <= litedramcore_slave_p3_address; end else begin - litedramcore_master_p0_address <= litedramcore_inti_p0_address; + litedramcore_master_p3_address <= litedramcore_inti_p3_address; end // synthesis translate_off dummy_d_54 = dummy_s; @@ -3335,11 +3223,11 @@ end reg dummy_d_55; // synthesis translate_on always @(*) begin - litedramcore_master_p0_bank <= 3'd0; + litedramcore_master_p3_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; + litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; end else begin - litedramcore_master_p0_bank <= litedramcore_inti_p0_bank; + litedramcore_master_p3_bank <= litedramcore_inti_p3_bank; end // synthesis translate_off dummy_d_55 = dummy_s; @@ -3350,11 +3238,11 @@ end reg dummy_d_56; // synthesis translate_on always @(*) begin - litedramcore_master_p0_cas_n <= 1'd1; + litedramcore_master_p3_cas_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; + litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; end else begin - litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n; + litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n; end // synthesis translate_off dummy_d_56 = dummy_s; @@ -3365,11 +3253,11 @@ end reg dummy_d_57; // synthesis translate_on always @(*) begin - litedramcore_master_p0_cs_n <= 1'd1; + litedramcore_master_p3_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; end else begin - litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n; + litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n; end // synthesis translate_off dummy_d_57 = dummy_s; @@ -3380,11 +3268,11 @@ end reg dummy_d_58; // synthesis translate_on always @(*) begin - litedramcore_master_p0_ras_n <= 1'd1; + litedramcore_master_p3_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; end else begin - litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n; + litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n; end // synthesis translate_off dummy_d_58 = dummy_s; @@ -3395,9 +3283,9 @@ end reg dummy_d_59; // synthesis translate_on always @(*) begin - litedramcore_slave_p0_rddata <= 32'd0; + litedramcore_slave_p3_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; + litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; end else begin end // synthesis translate_off @@ -3409,11 +3297,11 @@ end reg dummy_d_60; // synthesis translate_on always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; + litedramcore_master_p3_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; end else begin - litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; + litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n; end // synthesis translate_off dummy_d_60 = dummy_s; @@ -3424,9 +3312,9 @@ end reg dummy_d_61; // synthesis translate_on always @(*) begin - litedramcore_slave_p0_rddata_valid <= 1'd0; + litedramcore_slave_p3_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end else begin end // synthesis translate_off @@ -3438,11 +3326,11 @@ end reg dummy_d_62; // synthesis translate_on always @(*) begin - litedramcore_master_p0_cke <= 1'd0; + litedramcore_master_p3_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; + litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; end else begin - litedramcore_master_p0_cke <= litedramcore_inti_p0_cke; + litedramcore_master_p3_cke <= litedramcore_inti_p3_cke; end // synthesis translate_off dummy_d_62 = dummy_s; @@ -3453,11 +3341,11 @@ end reg dummy_d_63; // synthesis translate_on always @(*) begin - litedramcore_master_p0_odt <= 1'd0; + litedramcore_master_p3_odt <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; + litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; end else begin - litedramcore_master_p0_odt <= litedramcore_inti_p0_odt; + litedramcore_master_p3_odt <= litedramcore_inti_p3_odt; end // synthesis translate_off dummy_d_63 = dummy_s; @@ -3468,11 +3356,11 @@ end reg dummy_d_64; // synthesis translate_on always @(*) begin - litedramcore_master_p0_reset_n <= 1'd0; + litedramcore_master_p3_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; + litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; end else begin - litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n; + litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n; end // synthesis translate_off dummy_d_64 = dummy_s; @@ -3483,11 +3371,11 @@ end reg dummy_d_65; // synthesis translate_on always @(*) begin - litedramcore_master_p0_act_n <= 1'd1; + litedramcore_master_p3_act_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; + litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; end else begin - litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n; + litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n; end // synthesis translate_off dummy_d_65 = dummy_s; @@ -3498,11 +3386,11 @@ end reg dummy_d_66; // synthesis translate_on always @(*) begin - litedramcore_master_p0_wrdata <= 32'd0; + litedramcore_master_p3_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; + litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; end else begin - litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata; + litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata; end // synthesis translate_off dummy_d_66 = dummy_s; @@ -3513,10 +3401,10 @@ end reg dummy_d_67; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_rddata <= 32'd0; + litedramcore_inti_p0_rddata <= 32'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata; + litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata; end // synthesis translate_off dummy_d_67 = dummy_s; @@ -3527,11 +3415,11 @@ end reg dummy_d_68; // synthesis translate_on always @(*) begin - litedramcore_master_p0_wrdata_en <= 1'd0; + litedramcore_master_p3_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; + litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en; + litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en; end // synthesis translate_off dummy_d_68 = dummy_s; @@ -3542,10 +3430,10 @@ end reg dummy_d_69; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_rddata_valid <= 1'd0; + litedramcore_inti_p0_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end // synthesis translate_off dummy_d_69 = dummy_s; @@ -3556,11 +3444,11 @@ end reg dummy_d_70; // synthesis translate_on always @(*) begin - litedramcore_master_p0_wrdata_mask <= 4'd0; + litedramcore_master_p3_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; + litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask; + litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask; end // synthesis translate_off dummy_d_70 = dummy_s; @@ -3571,11 +3459,11 @@ end reg dummy_d_71; // synthesis translate_on always @(*) begin - litedramcore_master_p0_rddata_en <= 1'd0; + litedramcore_master_p3_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; + litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; end else begin - litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en; + litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en; end // synthesis translate_off dummy_d_71 = dummy_s; @@ -3586,11 +3474,11 @@ end reg dummy_d_72; // synthesis translate_on always @(*) begin - litedramcore_master_p1_address <= 15'd0; + litedramcore_master_p0_address <= 15'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_address <= litedramcore_slave_p1_address; + litedramcore_master_p0_address <= litedramcore_slave_p0_address; end else begin - litedramcore_master_p1_address <= litedramcore_inti_p1_address; + litedramcore_master_p0_address <= litedramcore_inti_p0_address; end // synthesis translate_off dummy_d_72 = dummy_s; @@ -3601,11 +3489,11 @@ end reg dummy_d_73; // synthesis translate_on always @(*) begin - litedramcore_master_p1_bank <= 3'd0; + litedramcore_master_p0_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; + litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; end else begin - litedramcore_master_p1_bank <= litedramcore_inti_p1_bank; + litedramcore_master_p0_bank <= litedramcore_inti_p0_bank; end // synthesis translate_off dummy_d_73 = dummy_s; @@ -3616,11 +3504,11 @@ end reg dummy_d_74; // synthesis translate_on always @(*) begin - litedramcore_master_p1_cas_n <= 1'd1; + litedramcore_master_p0_cas_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; + litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; end else begin - litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n; + litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n; end // synthesis translate_off dummy_d_74 = dummy_s; @@ -3631,11 +3519,11 @@ end reg dummy_d_75; // synthesis translate_on always @(*) begin - litedramcore_master_p1_cs_n <= 1'd1; + litedramcore_master_p0_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; + litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; end else begin - litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n; + litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n; end // synthesis translate_off dummy_d_75 = dummy_s; @@ -3646,11 +3534,11 @@ end reg dummy_d_76; // synthesis translate_on always @(*) begin - litedramcore_master_p1_ras_n <= 1'd1; + litedramcore_master_p0_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; + litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; end else begin - litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n; + litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n; end // synthesis translate_off dummy_d_76 = dummy_s; @@ -3661,9 +3549,9 @@ end reg dummy_d_77; // synthesis translate_on always @(*) begin - litedramcore_slave_p1_rddata <= 32'd0; + litedramcore_slave_p0_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; + litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; end else begin end // synthesis translate_off @@ -3675,11 +3563,11 @@ end reg dummy_d_78; // synthesis translate_on always @(*) begin - litedramcore_master_p1_we_n <= 1'd1; + litedramcore_master_p0_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; + litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; end else begin - litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n; + litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; end // synthesis translate_off dummy_d_78 = dummy_s; @@ -3690,9 +3578,9 @@ end reg dummy_d_79; // synthesis translate_on always @(*) begin - litedramcore_slave_p1_rddata_valid <= 1'd0; + litedramcore_slave_p0_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end else begin end // synthesis translate_off @@ -3704,11 +3592,11 @@ end reg dummy_d_80; // synthesis translate_on always @(*) begin - litedramcore_master_p1_cke <= 1'd0; + litedramcore_master_p0_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; + litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; end else begin - litedramcore_master_p1_cke <= litedramcore_inti_p1_cke; + litedramcore_master_p0_cke <= litedramcore_inti_p0_cke; end // synthesis translate_off dummy_d_80 = dummy_s; @@ -3719,11 +3607,11 @@ end reg dummy_d_81; // synthesis translate_on always @(*) begin - litedramcore_master_p1_odt <= 1'd0; + litedramcore_master_p0_odt <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; + litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; end else begin - litedramcore_master_p1_odt <= litedramcore_inti_p1_odt; + litedramcore_master_p0_odt <= litedramcore_inti_p0_odt; end // synthesis translate_off dummy_d_81 = dummy_s; @@ -3734,11 +3622,11 @@ end reg dummy_d_82; // synthesis translate_on always @(*) begin - litedramcore_master_p1_reset_n <= 1'd0; + litedramcore_master_p0_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; end else begin - litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; + litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n; end // synthesis translate_off dummy_d_82 = dummy_s; @@ -3749,11 +3637,11 @@ end reg dummy_d_83; // synthesis translate_on always @(*) begin - litedramcore_master_p1_act_n <= 1'd1; + litedramcore_master_p0_act_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; end else begin - litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n; + litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n; end // synthesis translate_off dummy_d_83 = dummy_s; @@ -3764,11 +3652,11 @@ end reg dummy_d_84; // synthesis translate_on always @(*) begin - litedramcore_master_p1_wrdata <= 32'd0; + litedramcore_master_p0_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; end else begin - litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata; + litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata; end // synthesis translate_off dummy_d_84 = dummy_s; @@ -3779,10 +3667,10 @@ end reg dummy_d_85; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_rddata <= 32'd0; + litedramcore_inti_p1_rddata <= 32'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; + litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata; end // synthesis translate_off dummy_d_85 = dummy_s; @@ -3793,11 +3681,11 @@ end reg dummy_d_86; // synthesis translate_on always @(*) begin - litedramcore_master_p1_wrdata_en <= 1'd0; + litedramcore_master_p0_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; + litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en; end // synthesis translate_off dummy_d_86 = dummy_s; @@ -3808,10 +3696,10 @@ end reg dummy_d_87; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_rddata_valid <= 1'd0; + litedramcore_inti_p1_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end // synthesis translate_off dummy_d_87 = dummy_s; @@ -3822,11 +3710,11 @@ end reg dummy_d_88; // synthesis translate_on always @(*) begin - litedramcore_master_p1_wrdata_mask <= 4'd0; + litedramcore_master_p0_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; + litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask; end // synthesis translate_off dummy_d_88 = dummy_s; @@ -3837,11 +3725,11 @@ end reg dummy_d_89; // synthesis translate_on always @(*) begin - litedramcore_master_p1_rddata_en <= 1'd0; + litedramcore_master_p0_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; + litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; end else begin - litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; + litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en; end // synthesis translate_off dummy_d_89 = dummy_s; @@ -3852,11 +3740,11 @@ end reg dummy_d_90; // synthesis translate_on always @(*) begin - litedramcore_master_p2_address <= 15'd0; + litedramcore_master_p1_address <= 15'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_address <= litedramcore_slave_p2_address; + litedramcore_master_p1_address <= litedramcore_slave_p1_address; end else begin - litedramcore_master_p2_address <= litedramcore_inti_p2_address; + litedramcore_master_p1_address <= litedramcore_inti_p1_address; end // synthesis translate_off dummy_d_90 = dummy_s; @@ -3867,11 +3755,11 @@ end reg dummy_d_91; // synthesis translate_on always @(*) begin - litedramcore_master_p2_bank <= 3'd0; + litedramcore_master_p1_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; + litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; end else begin - litedramcore_master_p2_bank <= litedramcore_inti_p2_bank; + litedramcore_master_p1_bank <= litedramcore_inti_p1_bank; end // synthesis translate_off dummy_d_91 = dummy_s; @@ -3882,11 +3770,11 @@ end reg dummy_d_92; // synthesis translate_on always @(*) begin - litedramcore_master_p2_cas_n <= 1'd1; + litedramcore_master_p1_cas_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; + litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; end else begin - litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n; + litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n; end // synthesis translate_off dummy_d_92 = dummy_s; @@ -3897,11 +3785,11 @@ end reg dummy_d_93; // synthesis translate_on always @(*) begin - litedramcore_master_p2_cs_n <= 1'd1; + litedramcore_master_p1_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; + litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; end else begin - litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n; + litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n; end // synthesis translate_off dummy_d_93 = dummy_s; @@ -4695,6 +4583,39 @@ end // synthesis translate_off reg dummy_d_122; // synthesis translate_on +always @(*) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_122 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_123; +// synthesis translate_on always @(*) begin litedramcore_bankmachine0_refresh_gnt <= 1'd0; case (bankmachine0_state) @@ -4721,12 +4642,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_122 = dummy_s; + dummy_d_123 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_123; +reg dummy_d_124; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_valid <= 1'd0; @@ -4769,12 +4690,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_123 = dummy_s; + dummy_d_124 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_124; +reg dummy_d_125; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_row_open <= 1'd0; @@ -4802,12 +4723,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_124 = dummy_s; + dummy_d_125 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_125; +reg dummy_d_126; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_row_close <= 1'd0; @@ -4835,12 +4756,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_125 = dummy_s; + dummy_d_126 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_126; +reg dummy_d_127; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; @@ -4876,39 +4797,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_126 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_127; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase // synthesis translate_off dummy_d_127 = dummy_s; // synthesis translate_on @@ -5329,16 +5217,13 @@ end reg dummy_d_138; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine1_req_rdata_valid <= 1'd0; case (bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -5351,6 +5236,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -5362,7 +5262,7 @@ end reg dummy_d_139; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + litedramcore_bankmachine1_refresh_gnt <= 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5371,6 +5271,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -5381,21 +5284,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -5407,19 +5295,22 @@ end reg dummy_d_140; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd0; + litedramcore_bankmachine1_cmd_valid <= 1'd0; case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd1; + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; end end + 3'd4: begin + end 3'd5: begin end 3'd6: begin @@ -5429,6 +5320,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -5440,18 +5343,15 @@ end reg dummy_d_141; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_valid <= 1'd0; + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -5465,18 +5365,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -6133,7 +6021,7 @@ end reg dummy_d_158; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine2_row_open <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6141,7 +6029,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine2_row_open <= 1'd1; end end 3'd4: begin @@ -6166,18 +6054,18 @@ end reg dummy_d_159; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; + litedramcore_bankmachine2_row_close <= 1'd0; case (bankmachine2_state) 1'd1: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; - end end 3'd4: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6199,18 +6087,15 @@ end reg dummy_d_160; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; + litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; case (bankmachine2_state) 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6221,6 +6106,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -6232,13 +6129,16 @@ end reg dummy_d_161; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -6251,18 +6151,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -6684,6 +6572,39 @@ end // synthesis translate_off reg dummy_d_172; // synthesis translate_on +always @(*) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_172 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_173; +// synthesis translate_on always @(*) begin litedramcore_bankmachine3_req_rdata_valid <= 1'd0; case (bankmachine3_state) @@ -6722,12 +6643,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_172 = dummy_s; + dummy_d_173 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_173; +reg dummy_d_174; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_refresh_gnt <= 1'd0; @@ -6755,12 +6676,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_173 = dummy_s; + dummy_d_174 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_174; +reg dummy_d_175; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_valid <= 1'd0; @@ -6803,12 +6724,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_174 = dummy_s; + dummy_d_175 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_175; +reg dummy_d_176; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_row_open <= 1'd0; @@ -6836,12 +6757,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_175 = dummy_s; + dummy_d_176 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_176; +reg dummy_d_177; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_row_close <= 1'd0; @@ -6868,39 +6789,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_176 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_177; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase // synthesis translate_off dummy_d_177 = dummy_s; // synthesis translate_on @@ -7441,18 +7329,15 @@ end reg dummy_d_191; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_valid <= 1'd0; + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -7466,18 +7351,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -7489,15 +7362,18 @@ end reg dummy_d_192; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine4_cmd_valid <= 1'd0; case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 3'd4: begin @@ -7511,6 +7387,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -8086,18 +7974,18 @@ end reg dummy_d_207; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine5_refresh_gnt <= 1'd0; case (bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8119,18 +8007,21 @@ end reg dummy_d_208; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd0; + litedramcore_bankmachine5_cmd_valid <= 1'd0; case (bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -8141,6 +8032,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -8152,44 +8055,29 @@ end reg dummy_d_209; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_valid <= 1'd0; + litedramcore_bankmachine5_row_open <= 1'd0; case (bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + litedramcore_bankmachine5_row_open <= 1'd1; end end 3'd4: begin end 3'd5: begin end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end endcase // synthesis translate_off dummy_d_209 = dummy_s; @@ -8200,7 +8088,7 @@ end reg dummy_d_210; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_row_open <= 1'd0; + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -8208,7 +8096,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open <= 1'd1; + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -8844,39 +8732,6 @@ end // synthesis translate_off reg dummy_d_226; // synthesis translate_on -always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_226 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_227; -// synthesis translate_on always @(*) begin litedramcore_bankmachine6_row_open <= 1'd0; case (bankmachine6_state) @@ -8903,12 +8758,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_227 = dummy_s; + dummy_d_226 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_228; +reg dummy_d_227; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_row_close <= 1'd0; @@ -8936,12 +8791,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_228 = dummy_s; + dummy_d_227 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_229; +reg dummy_d_228; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; @@ -8978,12 +8833,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_229 = dummy_s; + dummy_d_228 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_230; +reg dummy_d_229; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; @@ -9014,12 +8869,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_230 = dummy_s; + dummy_d_229 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_231; +reg dummy_d_230; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_we <= 1'd0; @@ -9061,6 +8916,39 @@ always @(*) begin end end endcase +// synthesis translate_off + dummy_d_230 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_231; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_231 = dummy_s; // synthesis translate_on @@ -9441,6 +9329,39 @@ end // synthesis translate_off reg dummy_d_241; // synthesis translate_on +always @(*) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_241 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_242; +// synthesis translate_on always @(*) begin litedramcore_bankmachine7_refresh_gnt <= 1'd0; case (bankmachine7_state) @@ -9467,12 +9388,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_241 = dummy_s; + dummy_d_242 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_242; +reg dummy_d_243; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_valid <= 1'd0; @@ -9515,12 +9436,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_242 = dummy_s; + dummy_d_243 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_243; +reg dummy_d_244; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_row_open <= 1'd0; @@ -9548,12 +9469,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_243 = dummy_s; + dummy_d_244 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_244; +reg dummy_d_245; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_row_close <= 1'd0; @@ -9581,12 +9502,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_244 = dummy_s; + dummy_d_245 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_245; +reg dummy_d_246; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; @@ -9622,39 +9543,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_245 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_246; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase // synthesis translate_off dummy_d_246 = dummy_s; // synthesis translate_on @@ -10730,7 +10618,7 @@ reg dummy_d_282; // synthesis translate_on always @(*) begin csrbank0_sel <= 1'd0; - csrbank0_sel <= (interface0_bank_bus_adr[13:11] == 2'd2); + csrbank0_sel <= (interface0_bank_bus_adr[13:9] == 2'd2); if (interface0_bank_bus_adr[0]) begin csrbank0_sel <= 1'd0; end @@ -10739,11 +10627,11 @@ always @(*) begin // synthesis translate_on end assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd0)); -assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd0)); +assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd0)); +assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd0)); assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd1)); -assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd1)); +assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd1)); +assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd1)); assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; @@ -10752,7 +10640,7 @@ reg dummy_d_283; // synthesis translate_on always @(*) begin csrbank1_sel <= 1'd0; - csrbank1_sel <= (interface1_bank_bus_adr[13:11] == 1'd0); + csrbank1_sel <= (interface1_bank_bus_adr[13:9] == 1'd0); if (interface1_bank_bus_adr[0]) begin csrbank1_sel <= 1'd0; end @@ -10761,35 +10649,35 @@ always @(*) begin // synthesis translate_on end assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; -assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd0)); -assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd0)); +assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd0)); +assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd0)); assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; -assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd1)); -assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd1)); +assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd1)); +assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd1)); assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd2)); -assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd2)); +assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd2)); +assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd2)); assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd3)); -assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd3)); +assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd3)); +assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd3)); assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd4)); -assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd4)); +assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd4)); +assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd4)); assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; -assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd5)); -assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd5)); +assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd5)); +assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd5)); assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd6)); -assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd6)); assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd7)); -assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd7)); assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd8)); -assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd8)); assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd9)); -assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd9)); assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0]; assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; @@ -10799,7 +10687,7 @@ reg dummy_d_284; // synthesis translate_on always @(*) begin csrbank2_sel <= 1'd0; - csrbank2_sel <= (interface2_bank_bus_adr[13:11] == 1'd1); + csrbank2_sel <= (interface2_bank_bus_adr[13:9] == 1'd1); if (interface2_bank_bus_adr[0]) begin csrbank2_sel <= 1'd0; end @@ -10808,217 +10696,105 @@ always @(*) begin // synthesis translate_on end assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; -assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd0)); -assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd0)); +assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd0)); +assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd0)); assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd1)); -assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd1)); +assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd1)); +assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd1)); assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd2)); -assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd2)); -assign csrbank2_dfii_pi0_address1_r = interface2_bank_bus_dat_w[6:0]; -assign csrbank2_dfii_pi0_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd3)); -assign csrbank2_dfii_pi0_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd3)); -assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd4)); -assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd4)); +assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd2)); +assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd2)); +assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0]; +assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd3)); +assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd3)); assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd5)); -assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd5)); -assign csrbank2_dfii_pi0_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd6)); -assign csrbank2_dfii_pi0_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd6)); -assign csrbank2_dfii_pi0_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd7)); -assign csrbank2_dfii_pi0_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd7)); -assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd8)); -assign csrbank2_dfii_pi0_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd8)); -assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd9)); -assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd9)); -assign csrbank2_dfii_pi0_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd10)); -assign csrbank2_dfii_pi0_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd10)); -assign csrbank2_dfii_pi0_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd11)); -assign csrbank2_dfii_pi0_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd11)); -assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd12)); -assign csrbank2_dfii_pi0_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd12)); -assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd13)); -assign csrbank2_dfii_pi0_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd13)); +assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd4)); +assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd4)); +assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd5)); +assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd5)); +assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd6)); +assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd6)); assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd14)); -assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd14)); +assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd7)); +assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd7)); assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd15)); -assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd15)); -assign csrbank2_dfii_pi1_address1_r = interface2_bank_bus_dat_w[6:0]; -assign csrbank2_dfii_pi1_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd16)); -assign csrbank2_dfii_pi1_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd16)); -assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd17)); -assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd17)); +assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd8)); +assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd8)); +assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0]; +assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd9)); +assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd9)); assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd18)); -assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd18)); -assign csrbank2_dfii_pi1_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd19)); -assign csrbank2_dfii_pi1_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd19)); -assign csrbank2_dfii_pi1_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd20)); -assign csrbank2_dfii_pi1_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd20)); -assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd21)); -assign csrbank2_dfii_pi1_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd21)); -assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd22)); -assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd22)); -assign csrbank2_dfii_pi1_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd23)); -assign csrbank2_dfii_pi1_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd23)); -assign csrbank2_dfii_pi1_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd24)); -assign csrbank2_dfii_pi1_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd24)); -assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd25)); -assign csrbank2_dfii_pi1_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd25)); -assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd26)); -assign csrbank2_dfii_pi1_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd26)); +assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd10)); +assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd10)); +assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd11)); +assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd11)); +assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd12)); +assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd12)); assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd27)); -assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd27)); +assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd13)); +assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd13)); assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd28)); -assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd28)); -assign csrbank2_dfii_pi2_address1_r = interface2_bank_bus_dat_w[6:0]; -assign csrbank2_dfii_pi2_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd29)); -assign csrbank2_dfii_pi2_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd29)); -assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd30)); -assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd30)); +assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd14)); +assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd14)); +assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[14:0]; +assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd15)); +assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd15)); assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd31)); -assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd31)); -assign csrbank2_dfii_pi2_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd32)); -assign csrbank2_dfii_pi2_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd32)); -assign csrbank2_dfii_pi2_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd33)); -assign csrbank2_dfii_pi2_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd33)); -assign csrbank2_dfii_pi2_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd34)); -assign csrbank2_dfii_pi2_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd34)); -assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd35)); -assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd35)); -assign csrbank2_dfii_pi2_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd36)); -assign csrbank2_dfii_pi2_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd36)); -assign csrbank2_dfii_pi2_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd37)); -assign csrbank2_dfii_pi2_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd37)); -assign csrbank2_dfii_pi2_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd38)); -assign csrbank2_dfii_pi2_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd38)); -assign csrbank2_dfii_pi2_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd39)); -assign csrbank2_dfii_pi2_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd39)); +assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd16)); +assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd16)); +assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd17)); +assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd17)); +assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd18)); +assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd18)); assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd40)); -assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd40)); +assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd19)); +assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd19)); assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd41)); -assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd41)); -assign csrbank2_dfii_pi3_address1_r = interface2_bank_bus_dat_w[6:0]; -assign csrbank2_dfii_pi3_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd42)); -assign csrbank2_dfii_pi3_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd42)); -assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd43)); -assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd43)); +assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd20)); +assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd20)); +assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[14:0]; +assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd21)); +assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd21)); assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd44)); -assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd44)); -assign csrbank2_dfii_pi3_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd45)); -assign csrbank2_dfii_pi3_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd45)); -assign csrbank2_dfii_pi3_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd46)); -assign csrbank2_dfii_pi3_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd46)); -assign csrbank2_dfii_pi3_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd47)); -assign csrbank2_dfii_pi3_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd47)); -assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd48)); -assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd48)); -assign csrbank2_dfii_pi3_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd49)); -assign csrbank2_dfii_pi3_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd49)); -assign csrbank2_dfii_pi3_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd50)); -assign csrbank2_dfii_pi3_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd50)); -assign csrbank2_dfii_pi3_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd51)); -assign csrbank2_dfii_pi3_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd51)); -assign csrbank2_dfii_pi3_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd52)); -assign csrbank2_dfii_pi3_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd52)); +assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd22)); +assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd22)); +assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd23)); +assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd23)); +assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd24)); +assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd24)); assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; -assign csrbank2_dfii_pi0_address1_w = litedramcore_phaseinjector0_address_storage[14:8]; -assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[7:0]; +assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0]; assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; -assign csrbank2_dfii_pi0_wrdata3_w = litedramcore_phaseinjector0_wrdata_storage[31:24]; -assign csrbank2_dfii_pi0_wrdata2_w = litedramcore_phaseinjector0_wrdata_storage[23:16]; -assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[15:8]; -assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[7:0]; -assign csrbank2_dfii_pi0_rddata3_w = litedramcore_phaseinjector0_status[31:24]; -assign csrbank2_dfii_pi0_rddata2_w = litedramcore_phaseinjector0_status[23:16]; -assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_status[15:8]; -assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_status[7:0]; -assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata0_we; +assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0]; +assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata_we; assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0]; -assign csrbank2_dfii_pi1_address1_w = litedramcore_phaseinjector1_address_storage[14:8]; -assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[7:0]; +assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0]; assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; -assign csrbank2_dfii_pi1_wrdata3_w = litedramcore_phaseinjector1_wrdata_storage[31:24]; -assign csrbank2_dfii_pi1_wrdata2_w = litedramcore_phaseinjector1_wrdata_storage[23:16]; -assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[15:8]; -assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[7:0]; -assign csrbank2_dfii_pi1_rddata3_w = litedramcore_phaseinjector1_status[31:24]; -assign csrbank2_dfii_pi1_rddata2_w = litedramcore_phaseinjector1_status[23:16]; -assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_status[15:8]; -assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_status[7:0]; -assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata0_we; +assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0]; +assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata_we; assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0]; -assign csrbank2_dfii_pi2_address1_w = litedramcore_phaseinjector2_address_storage[14:8]; -assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[7:0]; +assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[14:0]; assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0]; -assign csrbank2_dfii_pi2_wrdata3_w = litedramcore_phaseinjector2_wrdata_storage[31:24]; -assign csrbank2_dfii_pi2_wrdata2_w = litedramcore_phaseinjector2_wrdata_storage[23:16]; -assign csrbank2_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[15:8]; -assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[7:0]; -assign csrbank2_dfii_pi2_rddata3_w = litedramcore_phaseinjector2_status[31:24]; -assign csrbank2_dfii_pi2_rddata2_w = litedramcore_phaseinjector2_status[23:16]; -assign csrbank2_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_status[15:8]; -assign csrbank2_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_status[7:0]; -assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata0_we; +assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0]; +assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0]; +assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata_we; assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0]; -assign csrbank2_dfii_pi3_address1_w = litedramcore_phaseinjector3_address_storage[14:8]; -assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[7:0]; +assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[14:0]; assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0]; -assign csrbank2_dfii_pi3_wrdata3_w = litedramcore_phaseinjector3_wrdata_storage[31:24]; -assign csrbank2_dfii_pi3_wrdata2_w = litedramcore_phaseinjector3_wrdata_storage[23:16]; -assign csrbank2_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[15:8]; -assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[7:0]; -assign csrbank2_dfii_pi3_rddata3_w = litedramcore_phaseinjector3_status[31:24]; -assign csrbank2_dfii_pi3_rddata2_w = litedramcore_phaseinjector3_status[23:16]; -assign csrbank2_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_status[15:8]; -assign csrbank2_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_status[7:0]; -assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata0_we; +assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0]; +assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0]; +assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata_we; assign adr = csr_port_adr; assign we = csr_port_we; assign dat_w = csr_port_dat_w; @@ -14159,7 +13935,7 @@ always @(posedge sys_clk) begin new_master_rdata_valid8 <= new_master_rdata_valid7; interface0_bank_bus_dat_r <= 1'd0; if (csrbank0_sel) begin - case (interface0_bank_bus_adr[3]) + case (interface0_bank_bus_adr[1]) 1'd0: begin interface0_bank_bus_dat_r <= csrbank0_init_done0_w; end @@ -14178,7 +13954,7 @@ always @(posedge sys_clk) begin init_error_re <= csrbank0_init_error0_re; interface1_bank_bus_dat_r <= 1'd0; if (csrbank1_sel) begin - case (interface1_bank_bus_adr[6:3]) + case (interface1_bank_bus_adr[4:1]) 1'd0: begin interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; end @@ -14225,7 +14001,7 @@ always @(posedge sys_clk) begin a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; interface2_bank_bus_dat_r <= 1'd0; if (csrbank2_sel) begin - case (interface2_bank_bus_adr[8:3]) + case (interface2_bank_bus_adr[5:1]) 1'd0: begin interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; end @@ -14236,154 +14012,70 @@ always @(posedge sys_clk) begin interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; end 3'd4: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; end 3'd5: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; end 3'd6: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w; end 3'd7: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; end 4'd8: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w; + interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; end 4'd9: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; end 4'd10: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; end 4'd11: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; end 4'd12: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w; end 4'd13: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; end 4'd14: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; + interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; end 4'd15: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; end 5'd16: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; end 5'd17: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; end 5'd18: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w; end 5'd19: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata3_w; - end - 5'd20: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata2_w; - end - 5'd21: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w; - end - 5'd22: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; - end - 5'd23: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata3_w; - end - 5'd24: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata2_w; - end - 5'd25: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w; - end - 5'd26: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w; - end - 5'd27: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; - end - 5'd28: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; - end - 5'd29: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address1_w; - end - 5'd30: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; - end - 5'd31: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; - end - 6'd32: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata3_w; - end - 6'd33: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata2_w; - end - 6'd34: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata1_w; - end - 6'd35: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; - end - 6'd36: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata3_w; - end - 6'd37: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata2_w; - end - 6'd38: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata1_w; - end - 6'd39: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata0_w; - end - 6'd40: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; end - 6'd41: begin + 5'd20: begin interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; end - 6'd42: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address1_w; - end - 6'd43: begin + 5'd21: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; end - 6'd44: begin + 5'd22: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; end - 6'd45: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata3_w; - end - 6'd46: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata2_w; - end - 6'd47: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata1_w; - end - 6'd48: begin + 5'd23: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; end - 6'd49: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata3_w; - end - 6'd50: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata2_w; - end - 6'd51: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata1_w; - end - 6'd52: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata0_w; + 5'd24: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w; end endcase end @@ -14395,112 +14087,64 @@ always @(posedge sys_clk) begin litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; end litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; - if (csrbank2_dfii_pi0_address1_re) begin - litedramcore_phaseinjector0_address_storage[14:8] <= csrbank2_dfii_pi0_address1_r; - end if (csrbank2_dfii_pi0_address0_re) begin - litedramcore_phaseinjector0_address_storage[7:0] <= csrbank2_dfii_pi0_address0_r; + litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r; end litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; if (csrbank2_dfii_pi0_baddress0_re) begin litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; end litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; - if (csrbank2_dfii_pi0_wrdata3_re) begin - litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank2_dfii_pi0_wrdata3_r; - end - if (csrbank2_dfii_pi0_wrdata2_re) begin - litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank2_dfii_pi0_wrdata2_r; - end - if (csrbank2_dfii_pi0_wrdata1_re) begin - litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank2_dfii_pi0_wrdata1_r; - end if (csrbank2_dfii_pi0_wrdata0_re) begin - litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank2_dfii_pi0_wrdata0_r; + litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; end litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; if (csrbank2_dfii_pi1_command0_re) begin litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; end litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; - if (csrbank2_dfii_pi1_address1_re) begin - litedramcore_phaseinjector1_address_storage[14:8] <= csrbank2_dfii_pi1_address1_r; - end if (csrbank2_dfii_pi1_address0_re) begin - litedramcore_phaseinjector1_address_storage[7:0] <= csrbank2_dfii_pi1_address0_r; + litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r; end litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; if (csrbank2_dfii_pi1_baddress0_re) begin litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; end litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; - if (csrbank2_dfii_pi1_wrdata3_re) begin - litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank2_dfii_pi1_wrdata3_r; - end - if (csrbank2_dfii_pi1_wrdata2_re) begin - litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank2_dfii_pi1_wrdata2_r; - end - if (csrbank2_dfii_pi1_wrdata1_re) begin - litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank2_dfii_pi1_wrdata1_r; - end if (csrbank2_dfii_pi1_wrdata0_re) begin - litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank2_dfii_pi1_wrdata0_r; + litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; end litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; if (csrbank2_dfii_pi2_command0_re) begin litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; end litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; - if (csrbank2_dfii_pi2_address1_re) begin - litedramcore_phaseinjector2_address_storage[14:8] <= csrbank2_dfii_pi2_address1_r; - end if (csrbank2_dfii_pi2_address0_re) begin - litedramcore_phaseinjector2_address_storage[7:0] <= csrbank2_dfii_pi2_address0_r; + litedramcore_phaseinjector2_address_storage[14:0] <= csrbank2_dfii_pi2_address0_r; end litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; if (csrbank2_dfii_pi2_baddress0_re) begin litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; end litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; - if (csrbank2_dfii_pi2_wrdata3_re) begin - litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank2_dfii_pi2_wrdata3_r; - end - if (csrbank2_dfii_pi2_wrdata2_re) begin - litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank2_dfii_pi2_wrdata2_r; - end - if (csrbank2_dfii_pi2_wrdata1_re) begin - litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank2_dfii_pi2_wrdata1_r; - end if (csrbank2_dfii_pi2_wrdata0_re) begin - litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank2_dfii_pi2_wrdata0_r; + litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; end litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; if (csrbank2_dfii_pi3_command0_re) begin litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; end litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; - if (csrbank2_dfii_pi3_address1_re) begin - litedramcore_phaseinjector3_address_storage[14:8] <= csrbank2_dfii_pi3_address1_r; - end if (csrbank2_dfii_pi3_address0_re) begin - litedramcore_phaseinjector3_address_storage[7:0] <= csrbank2_dfii_pi3_address0_r; + litedramcore_phaseinjector3_address_storage[14:0] <= csrbank2_dfii_pi3_address0_r; end litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; if (csrbank2_dfii_pi3_baddress0_re) begin litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; end litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; - if (csrbank2_dfii_pi3_wrdata3_re) begin - litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank2_dfii_pi3_wrdata3_r; - end - if (csrbank2_dfii_pi3_wrdata2_re) begin - litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank2_dfii_pi3_wrdata2_r; - end - if (csrbank2_dfii_pi3_wrdata1_re) begin - litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank2_dfii_pi3_wrdata1_r; - end if (csrbank2_dfii_pi3_wrdata0_re) begin - litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank2_dfii_pi3_wrdata0_r; + litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; end litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; if (sys_rst) begin