diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py index 8c6b70a..4c24cae 100755 --- a/litedram/gen-src/generate.py +++ b/litedram/gen-src/generate.py @@ -115,7 +115,7 @@ def generate_one(t, mw_init): else: raise ValueError("Unsupported SDRAM PHY: {}".format(core_config["sdram_phy"])) - soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000) + soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000, csr_data_width=32) # Build into build_dir builder = Builder(soc, output_dir=build_dir, compile_gateware=False) diff --git a/litedram/gen-src/wrapper-mw-init.vhdl b/litedram/gen-src/wrapper-mw-init.vhdl index 475e088..46ae4b1 100644 --- a/litedram/gen-src/wrapper-mw-init.vhdl +++ b/litedram/gen-src/wrapper-mw-init.vhdl @@ -82,8 +82,8 @@ architecture behaviour of litedram_wrapper is user_rst : out std_ulogic; csr_port0_adr : in std_ulogic_vector(13 downto 0); csr_port0_we : in std_ulogic; - csr_port0_dat_w : in std_ulogic_vector(7 downto 0); - csr_port0_dat_r : out std_ulogic_vector(7 downto 0); + csr_port0_dat_w : in std_ulogic_vector(31 downto 0); + csr_port0_dat_r : out std_ulogic_vector(31 downto 0); user_port_native_0_cmd_valid : in std_ulogic; user_port_native_0_cmd_ready : out std_ulogic; user_port_native_0_cmd_we : in std_ulogic; @@ -116,8 +116,8 @@ architecture behaviour of litedram_wrapper is signal csr_port0_adr : std_ulogic_vector(13 downto 0); signal csr_port0_we : std_ulogic; - signal csr_port0_dat_w : std_ulogic_vector(7 downto 0); - signal csr_port0_dat_r : std_ulogic_vector(7 downto 0); + signal csr_port0_dat_w : std_ulogic_vector(31 downto 0); + signal csr_port0_dat_r : std_ulogic_vector(31 downto 0); signal csr_port_read_comb : std_ulogic_vector(63 downto 0); signal csr_valid : std_ulogic; signal csr_write_valid : std_ulogic; @@ -205,8 +205,8 @@ begin -- DRAM CSR interface signals. We only support access to the bottom byte csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; csr_write_valid <= wb_in.we and wb_in.sel(0); - csr_port0_adr <= wb_in.adr(13 downto 0) when wb_is_csr = '1' else (others => '0'); - csr_port0_dat_w <= wb_in.dat(7 downto 0); + csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0'); + csr_port0_dat_w <= wb_in.dat(31 downto 0); csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; -- Wishbone out signals @@ -215,7 +215,7 @@ begin user_port0_wdata_ready when state = MWRITE else user_port0_rdata_valid when state = MREAD else '0'; - csr_port_read_comb <= x"00000000000000" & csr_port0_dat_r; + csr_port_read_comb <= x"00000000" & csr_port0_dat_r; wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else wb_init_out.dat when wb_is_init = '1' else user_port0_rdata_data(127 downto 64) when ad3 = '1' else diff --git a/litedram/generated/arty/litedram-wrapper.vhdl b/litedram/generated/arty/litedram-wrapper.vhdl index 475e088..46ae4b1 100644 --- a/litedram/generated/arty/litedram-wrapper.vhdl +++ b/litedram/generated/arty/litedram-wrapper.vhdl @@ -82,8 +82,8 @@ architecture behaviour of litedram_wrapper is user_rst : out std_ulogic; csr_port0_adr : in std_ulogic_vector(13 downto 0); csr_port0_we : in std_ulogic; - csr_port0_dat_w : in std_ulogic_vector(7 downto 0); - csr_port0_dat_r : out std_ulogic_vector(7 downto 0); + csr_port0_dat_w : in std_ulogic_vector(31 downto 0); + csr_port0_dat_r : out std_ulogic_vector(31 downto 0); user_port_native_0_cmd_valid : in std_ulogic; user_port_native_0_cmd_ready : out std_ulogic; user_port_native_0_cmd_we : in std_ulogic; @@ -116,8 +116,8 @@ architecture behaviour of litedram_wrapper is signal csr_port0_adr : std_ulogic_vector(13 downto 0); signal csr_port0_we : std_ulogic; - signal csr_port0_dat_w : std_ulogic_vector(7 downto 0); - signal csr_port0_dat_r : std_ulogic_vector(7 downto 0); + signal csr_port0_dat_w : std_ulogic_vector(31 downto 0); + signal csr_port0_dat_r : std_ulogic_vector(31 downto 0); signal csr_port_read_comb : std_ulogic_vector(63 downto 0); signal csr_valid : std_ulogic; signal csr_write_valid : std_ulogic; @@ -205,8 +205,8 @@ begin -- DRAM CSR interface signals. We only support access to the bottom byte csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; csr_write_valid <= wb_in.we and wb_in.sel(0); - csr_port0_adr <= wb_in.adr(13 downto 0) when wb_is_csr = '1' else (others => '0'); - csr_port0_dat_w <= wb_in.dat(7 downto 0); + csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0'); + csr_port0_dat_w <= wb_in.dat(31 downto 0); csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; -- Wishbone out signals @@ -215,7 +215,7 @@ begin user_port0_wdata_ready when state = MWRITE else user_port0_rdata_valid when state = MREAD else '0'; - csr_port_read_comb <= x"00000000000000" & csr_port0_dat_r; + csr_port_read_comb <= x"00000000" & csr_port0_dat_r; wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else wb_init_out.dat when wb_is_init = '1' else user_port0_rdata_data(127 downto 64) when ad3 = '1' else diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init index 1031ca2..4f7ad0f 100644 --- a/litedram/generated/arty/litedram_core.init +++ b/litedram/generated/arty/litedram_core.init @@ -510,37 +510,37 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -38429f003c4c0001 +38429e003c4c0001 600000003d20c000 7929002061292000 -3d40c000f9228038 +3d40c000f92280a8 614a201839200035 7c0004ac794a0020 4e8000207d2057aa 0000000000000000 3c4c000100000000 -6000000038429ebc -39290010e9228038 +6000000038429dbc +39290010e92280a8 7d204eaa7c0004ac 4082ffe871290008 -e922803860000000 +e92280a860000000 7c604faa7c0004ac 000000004e800020 0000000000000000 -38429e783c4c0001 +38429d783c4c0001 fbc1fff07c0802a6 7fc32214fbe1fff8 f80100107c7f1b78 7fbff040f821ffd1 38210030409e000c -893f000048001b40 +893f000048001ab4 409e000c2f89000a 4bffff813860000d 3bff0001887f0000 4bffffd04bffff75 0100000000000000 3c4c000100000280 -7c0802a638429e14 +7c0802a638429d14 fbe1fff8fbc1fff0 f821fe91f8010010 f88101983bc10020 @@ -549,62 +549,62 @@ f88101983bc10020 f8e101b038c10198 f90101b87fc3f378 f94101c8f92101c0 -60000000480014e1 +6000000048001455 7c641b787c7f1b78 4bffff457fc3f378 7fe3fb7838210170 -0000000048001aa0 +0000000048001a14 0000028001000000 -38429d983c4c0001 +38429c983c4c0001 fbe1fff87c0802a6 918100087d908026 f821ff91f8010010 3d2000014bfffe81 7d2903a6612986a0 -e922803860000000 +e92280a860000000 7c0004ac39290010 4200ffec7d204eaa -38637d103c62ffff +38637d803c62ffff 3880ffff4bffff3d 7c0004ac54840002 3c62ffff7c8026ea -38637d303fe0c000 +38637da03fe0c000 4bffff1963ff0008 7bff00203c62ffff -4bffff0938637d50 +4bffff0938637dc0 7fe0feea7c0004ac 4182001073e90001 -38637d683c62ffff +38637dd83c62ffff 73e900024bfffeed 418200104e000000 -38637d703c62ffff +38637de03c62ffff 3fe2ffff4bfffed5 -7fe3fb783bff7f58 +7fe3fb783bff7fc8 3c80c0004bfffec5 7884002060840010 7c8026ea7c0004ac 7884b2823c62ffff -4bfffea138637d78 +4bfffea138637de8 3c80c00041920028 7884002060840018 7c8026ea7c0004ac 788465023c62ffff -4bfffe7938637d98 +4bfffe7938637e08 612900203d20c000 7c0004ac79290020 3c80000f7d204eea 608442403c62ffff -7c89239238637db8 +7c89239238637e28 7fe3fb784bfffe4d 419200284bfffe45 3c82ffff3ca2ffff -38a57dd83c62ffff -38637df038847de8 -48000d994bfffe25 +38a57e483c62ffff +38637e6038847e58 +48000d3d4bfffe25 3c62ffff60000000 -4bfffe1138637e20 +4bfffe1138637e90 8181000838210070 -480019087d908120 +4800187c7d908120 0300000000000000 3863ffff00000180 3923000178630020 @@ -629,785 +629,767 @@ f869000039000001 39400000f90a0000 4e800020f9490000 0000000000000000 -3920000400000000 -7d2903a63884ffff -386300088d240001 -4200fff4f923fff8 +8944000100000000 +794a45e489240000 +892400027d4a4b78 +7d2a5378792983e4 +7929c1e489240003 +552ac03e7d295378 +512a463e512a421e +f923000079490020 000000004e800020 0000000000000000 -3884ffff39200004 -e92300007d2903a6 -9d24000138630008 -4e8000204200fff4 +792ac202e9230000 +9944000299240003 +79294602792a8402 +9924000099440001 +000000004e800020 0000000000000000 -3c4c000100000000 -7c0802a638429aec -f821ff0148001741 -3c62ffff7c7e1b78 -3be0000438637ef0 -600000004bfffcbd -394100603cc08020 -3920002a60c60003 -78c600207d5d5378 -38e0000039000004 -7928f8427d0903a6 -7d2900d0792907e0 -7d2842787d293038 -7d0a39ae79090020 -4200ffe038e70001 -394a00043bffffff -4082ffc47bff0021 -394000093d20c010 -3b80000161290818 -3860000f79290020 -3e80c0103ee0c010 -3d20c010fbe90000 -61290820237e0001 -7929002062f708d8 -3ea2ffff629408e0 -fbe900007f7b07b4 -7af700203d20c010 -3a60002561290828 -7a94002079290020 -3ac100703a400001 +384299c83c4c0001 +480016917c0802a6 +7c7e1b78f821ff01 +38637f603c62ffff +4bfffc993be00004 +3cc0802060000000 +60c6000339410060 +7d5d53783920002a +3900000478c60020 +7d0903a638e00000 +792907e07928f842 +7d2930387d2900d0 +790900207d284278 +38e700017d0a39ae +3bffffff4200ffe0 +7bff0021394a0004 +3d20c0104082ffc4 +6129081839400009 +792900203b800001 +3ee0c0103860000f +fbe900003e80c010 +237e00013d20c010 +62f7086861290820 +6294087079290020 +7f7b07b43ea2ffff 3d20c010fbe90000 -612908083ab57f18 -792900207f1dda14 -3d20c010f9490000 -7929002061290810 -4bfffdd9fb890000 -7fa4eb783c60c010 -7863002060630830 -3c60c0104bfffe7d -6063089838810064 +612908087af70020 +792900203a600025 +3a4000017a940020 +f94900003ac10070 +3ab57f883d20c010 +7f1dda1461290810 +fb89000079290020 +3c60c0104bfffdc5 +606308287fa4eb78 4bfffe6978630020 -388100683c60c010 -7863002060630900 +388100643c60c010 +7863002060630858 3c60c0104bfffe55 -606309683881006c +6063088838810068 4bfffe4178630020 -394000173d20c010 -7fc3f37861290950 -fbe9000079290020 -612909583d20c010 -fbe9000079290020 -612909603d20c010 -fbe9000079290020 -612909403d20c010 -f949000079290020 -612909483d20c010 -fb89000079290020 -612908e83d20c010 -fbe9000079290020 -612908f03d20c010 -fbe9000079290020 -612908f83d20c010 -fbe9000079290020 -4bfffd213be00000 -79390020213e0003 -7f3dca147d2907b4 -fa7700007e3d4a14 -3860000ffa540000 -3b4000013b800000 -7b890fa44bfffccd -7c75482a7ec4b378 -7d38e0ae4bfffda1 -7f89500089580010 -7d39e0ae409e0048 -7f89500089510010 -3b9c0004409e0038 -409effc82bbc0010 -393f00012fba0000 -409e00287d3c07b4 -419e001c2f890020 -7f9fe3787fc3f378 -4bffff884bfffcdd -4bffffc83b400000 -38bf00017f9fe378 -7cbc07b47fc3f378 -4bfffcb93e80c010 -213e00033e60c010 -629408d879370020 -7d2907b4627308e0 -7efdba147f7dda14 -3a4000257a940020 -3a2000017a730020 -fa5400007fbd4a14 -3860000ffa330000 -3b2000013b400000 -7b490fa44bfffbfd -7c75482a7ec4b378 -7d38d0ae4bfffcd1 -7f895000895b0010 -7d37d0ae409e0044 -7f895000895d0010 -3b5a0004409e0034 -409effc82bba0010 -419e00282fb90000 -2f89001f393c0001 -419d00187d3c07b4 -4bfffc117fc3f378 -3b2000004bffff8c -2f9f00204bffffcc -7fbd0e707fbfe214 -3c62ffff409e0094 -4bfff96938637f00 -7fc3f37860000000 -4bfffb913be00000 -419c00987f9fe800 -392000003d40c010 -3860000f614a0818 -f92a0000794a0020 -614a08203d40c010 -f92a0000794a0020 -614a08283d40c010 -f92a0000794a0020 -3940000b3d20c010 -7929002061290808 +3881006c3c60c010 +78630020606308b8 +3d20c0104bfffe2d +612908a839400017 +792900207fc3f378 +3d20c010fbe90000 +79290020612908b0 +3d20c010fbe90000 +7929002061290898 3d20c010f9490000 -6129081039400001 +79290020612908a0 +3d20c010fb890000 +7929002061290878 +3d20c010fbe90000 +7929002061290880 +3be00000fbe90000 +213e00034bfffd2d +7d2907b479390020 +7e3d4a147f3dca14 +fa540000fa770000 +3b8000003860000f +4bfffcd93b400001 +7ec4b3787b890fa4 +4bfffdcd7c75482a +895800107d38e0ae +409e00487f895000 +895100107d39e0ae +409e00387f895000 +2bbc00103b9c0004 +2fba0000409effc8 +7d3c07b4393f0001 +2f890020409e0028 +7fc3f378419e001c +4bfffce97f9fe378 +3b4000004bffff88 +7f9fe3784bffffc8 +7fc3f37838bf0001 +3e80c0107cbc07b4 +3e60c0104bfffcc5 +79370020213e0003 +6273087062940868 +7f7dda147d2907b4 +7a9400207efdba14 +7a7300203a400025 +7fbd4a143a200001 +fa330000fa540000 +3b4000003860000f +4bfffc093b200001 +7ec4b3787b490fa4 +4bfffcfd7c75482a +895b00107d38d0ae +409e00447f895000 +895d00107d37d0ae +409e00347f895000 +2bba00103b5a0004 +2fb90000409effc8 +393c0001419e0028 +7d3c07b42f89001f +7fc3f378419d0018 +4bffff8c4bfffc1d +4bffffcc3b200000 +7fbfe2142f9f0020 +409e00847fbd0e70 +38637f703c62ffff +600000004bfff975 +3be000007fc3f378 +7f9fe8004bfffb9d +3d40c010419c0088 +614a081839200000 +794a00203860000f +3d40c010f92a0000 +794a0020614a0820 +3d20c010f92a0000 +612908083940000b f949000079290020 -382101004bfffafd -7cbfe050480013a0 -7ca50e703c62ffff -7fa4eb787ca50194 -7ca507b438637f08 -600000004bfff8c5 -7fc3f3784bffff5c -4bfffb313bff0001 -4bffff547fff07b4 +394000013d20c010 +7929002061290810 +4bfffb19f9490000 +4800133038210100 +3c62ffff7cbfe050 +7ca501947ca50e70 +38637f787fa4eb78 +4bfff8e17ca507b4 +4bffff6c60000000 +3bff00017fc3f378 +7fff07b44bfffb4d +000000004bffff64 +00000f8001000000 +384295c03c4c0001 +3d20c0107c0802a6 +3940000e61290800 +6000000079290020 +f801001038628030 +f9490000f821ffa1 +600000004bfff885 +e801001038210060 +4e8000207c0803a6 0100000000000000 -3c4c000100000f80 -7c0802a6384296a4 +3c4c000100000080 +7c0802a63842956c 612908003d20c010 -792900203940000e -38637fc03c62ffff +7929002039400001 +38637fa83c62ffff f821ffa1f8010010 -4bfff869f9490000 +4bfff831f9490000 3821006060000000 7c0803a6e8010010 000000004e800020 0000008001000000 -384296503c4c0001 -3d20c0107c0802a6 -3940000161290800 -3c62ffff79290020 -f801001038637f38 -f9490000f821ffa1 -600000004bfff815 -e801001038210060 -4e8000207c0803a6 -0100000000000000 -3c4c000100000080 -7c0802a6384295fc -7d0903a639000080 -3d2040003d40aaaa -4800126d614aaaaa -91490000f821ff81 -4200fff839290004 -3d00aaaa39400080 -3d2040007d4903a6 -6108aaaa3be00000 -7f8a400081490000 -3bff0001419e000c -392900047fff07b4 -390000804200ffe8 -7d0903a63d405555 -614a55553d204000 +384295183c4c0001 +390000807c0802a6 +3d40aaaa7d0903a6 +614aaaaa3d204000 +f821ff81480011fd 3929000491490000 394000804200fff8 -7d4903a63d005555 -610855553d204000 -7f8a400081490000 -3bff0001419e000c -392900047fff07b4 -2fbf00004200ffe8 -3c62ffff419e001c -7fe4fb7838a00100 -4bfff72138637e38 -3d00000860000000 -7d0903a63ce08020 -3d40400060e70003 -78e7002039200001 -792907e07928f842 -394a00047d2900d0 -7d2942787d293838 -4200ffe4912afffc +7d4903a63d00aaaa +3be000003d204000 +814900006108aaaa +419e000c7f8a4000 +7fff07b43bff0001 +4200ffe839290004 +3d40555539000080 +3d2040007d0903a6 +91490000614a5555 +4200fff839290004 +3d00555539400080 +3d2040007d4903a6 +8149000061085555 +419e000c7f8a4000 +7fff07b43bff0001 +4200ffe839290004 +419e001c2fbf0000 +38a001003c62ffff +38637ea87fe4fb78 +600000004bfff73d 3ce080203d000008 60e700037d0903a6 -3ba000003d404000 -78e7002039200001 -792907e07928f842 -7d2938387d2900d0 -810a00007d294278 -419e000c7f884840 -7fbd07b43bbd0001 -4200ffd4394a0004 -419e001c2fbd0000 -3ca000083c62ffff -38637e607fa4eb78 -600000004bfff675 -3940000039202000 -3d2a10007d2903a6 -3929000279480020 -79291764394a0001 -4200ffe891090000 -3940000039202000 -3bc000007d2903a6 -792917643d2a1000 -5529043e81290008 -419e000c7f895000 -7fde07b43bde0001 -4200ffdc394a0001 -419e001c2fbe0000 -38a020003c62ffff -38637e887fc4f378 -600000004bfff5f5 -386000007fffea14 -2f9f00007ffff214 -3c62ffff409e009c -4bfff5d138637eb0 -7d3602a660000000 -792a00203d000008 -392000007d0903a6 -792700203d091000 -3929000179081764 -4200ffec90e80000 -7d2450507c9602a6 -7c844b963c806400 -7d3602a678840020 -792900203d000008 -3d4040007d0903a6 -394a0004810a0000 -7cb602a64200fff8 -3ca064007d254850 -3c62ffff7ca54b96 -78a5006038637ec0 -600000004bfff54d -3821008038600001 -0000000048001028 -0000038001000000 -384293383c4c0001 -48000f817c0802a6 -3fe0c010f821fec1 -63ff00283f80c010 -7bff0020639c0040 -7b9c00203bc00001 -3e02ffff3ba00000 -4bfffc613aa00000 -3b61007038600000 -fbdf00004bfff71d -38600001fbdc0000 -fbbf00003ae10063 -3a107f583ac10061 -392000024bfff6fd -38637f783c62ffff -fbdc0000f93f0000 -3be00000fbbf0000 -600000004bfff4a5 -fb6100803d22ffff -f921008839297f88 -39297f183d22ffff -3d22fffff9210090 -f921009839297f98 -39297fa03d22ffff -3b800001f92100a0 -3e40c0103e20c010 -3e80c0103e60c010 -623108187f9cf830 -6273082862520820 -7f9c07b462940808 -3b0000003bc00000 -7a3100203ba00000 -7a7300207a520020 -480000447a940020 -2f9d00077fbeeb78 -3d20c010419e02d0 -612900283d40c010 -79290020614a0048 -39000001794a0020 -fb8900003bbd0001 -7f58d3787fbd07b4 -faa90000f90a0000 -3b40000439410060 -7d5953783920002a -38e0000039000004 -3cc080207d0903a6 -60c600037928f842 +392000013d404000 +7928f84278e70020 7d2900d0792907e0 -7d29303878c60020 -790900207d284278 -38e700017d0a39ae -3b5affff4200ffd4 -7b5a0021394a0004 -392000094082ffb8 +7d293838394a0004 +912afffc7d294278 +3d0000084200ffe4 +7d0903a63ce08020 +3d40400060e70003 +392000013ba00000 +7928f84278e70020 +7d2900d0792907e0 +7d2942787d293838 +7f884840810a0000 +3bbd0001419e000c +394a00047fbd07b4 +2fbd00004200ffd4 +3c62ffff419e001c +7fa4eb783ca00008 +4bfff69138637ed0 +3920200060000000 +7d2903a639400000 +794800203d2a1000 +394a000139290002 +9109000079291764 +392020004200ffe8 +7d2903a639400000 +3d2a10003bc00000 +8129000879291764 +7f8950005529043e +3bde0001419e000c +394a00017fde07b4 +2fbe00004200ffdc +3c62ffff419e001c +7fc4f37838a02000 +4bfff61138637ef8 +7fffea1460000000 +7ffff21438600000 +409e009c2f9f0000 +38637f203c62ffff +600000004bfff5ed +3d0000087d3602a6 +7d0903a6792a0020 +3d09100039200000 +7908176479270020 +90e8000039290001 +7c9602a64200ffec +3c8064007d245050 +788400207c844b96 +3d0000087d3602a6 +7d0903a679290020 +810a00003d404000 +4200fff8394a0004 +7d2548507cb602a6 +7ca54b963ca06400 +38637f303c62ffff +4bfff56978a50060 +3860000160000000 +48000fb838210080 +0100000000000000 +3c4c000100000380 +7c0802a638429254 +f821fec148000f11 +3f80c0103fe0c010 +639c004063ff0028 +3bc000017bff0020 +3ba000007b9c0020 +3aa000003e02ffff +386000004bfffc61 +4bfff7393b610070 +fbdc0000fbdf0000 +3ae1006338600001 +3ac10061fbbf0000 +4bfff7193a107fc8 +3c62ffff39200002 +f93f000038637fe8 +fbbf0000fbdc0000 +4bfff4c13be00000 +3d22ffff60000000 +39297ff8fb610080 +3d22fffff9210088 +f921009039297f88 +3922800860000000 +60000000f9210098 +f92100a039228010 +3e20c0103b800001 +3e60c0103e40c010 +7f9cf8303e80c010 +6252082062310818 +6294081062730808 +3bc000007f9c07b4 +3ba000003b000000 +7a5200207a310020 +7a9400207a730020 +7fbeeb7848000044 +419e02902f9d0007 +3d40c0103d20c010 +614a004861290028 +794a002079290020 +3bbd000139000001 +7fbd07b4fb890000 +f90a00007f58d378 +39410060faa90000 +3920002a3b400004 +390000047d595378 +7d0903a638e00000 +7928f8423cc08020 +792907e060c60003 +78c600207d2900d0 +7d2842787d293038 +7d0a39ae79090020 +4200ffd438e70001 +394a00043b5affff +4082ffb87b5a0021 +39e0000139200009 fb520000fb510000 -fb53000039e00001 39c000013860000f -3d20c010f9340000 -7929002061290810 -4bfff561f9e90000 -7f24cb783c60c010 -3b20002060630830 -4bfff60178630020 -388100643c60c010 -7863002060630898 -3c60c0104bfff5ed -6063090038810068 -4bfff5d978630020 -3881006c3c60c010 -7863002060630968 -3d20c0104bfff5c5 -e861008839400017 -7fa5eb7861290950 -7fe4fb7879290020 -3d20c010fb490000 -7929002061290958 -3d20c010fb490000 -7929002061290960 -3d20c010fb490000 -7929002061290940 -3d20c010f9490000 -7929002061290948 -3d20c010f9e90000 -79290020612908e8 -3d20c010fb490000 -79290020612908f0 -3d20c010fb490000 -79290020612908f8 -3b400000fb490000 -600000004bfff265 -4bfff4917fe3fb78 -394000253d20c010 -3860000f612908d8 -39e0000179290020 -3d20c010f9490000 -79290020612908e0 -4bfff439f9c90000 -e921009039400000 -e881008079480fa4 -7c69402af94100a8 -e94100a84bfff501 -7d1650ae88fb0001 -409e00ac7f883800 -88fb00037d1750ae -409e009c7f883800 -2baa0010394a0004 -e8610098409effbc -3b39ffff7de47b78 -7f5a07b47f5a7a14 -600000004bfff1c5 -4bfff4397fe3fb78 -4082ff5c7b390021 -4bfff1a9e86100a0 -3920000b60000000 -fb320000fb310000 -fb33000039400001 -f93400003860000f -612908103d20c010 +f9f40000f9330000 +3c60c0104bfff58d +606308287f24cb78 +786300203b200020 +3c60c0104bfff62d +6063085838810064 +4bfff61978630020 +388100683c60c010 +7863002060630888 +3c60c0104bfff605 +606308b83881006c +4bfff5f178630020 +394000173d20c010 +612908a8e8610088 +792900207fa5eb78 +fb4900007fe4fb78 +612908b03d20c010 +fb49000079290020 +612908983d20c010 f949000079290020 -7fe3fb784bfff385 -7e0383784bfff495 -600000004bfff165 -419cfd3c7f98d000 -4bfffd387f1ac378 -4bffff6439e00000 -7fc5f3783c62ffff -38637fa87fe4fb78 -600000004bfff135 -3d40c0103d20c010 -614a004061290028 -794a002079290020 -7bde002039000001 -fb89000038fe0001 -f90a00007ce903a6 -3d40c010faa90000 -794a0020614a0048 -7fe3fb7842000034 -4bfff4093af7ffff -3b7bffff7e038378 -600000004bfff0d5 -3ad6ffff2f9f0001 -3be00001419e001c -fb8900004bfffc54 +612908a03d20c010 +f9e9000079290020 +612908783d20c010 +fb49000079290020 +612908803d20c010 +fb49000079290020 +4bfff2b13b400000 +7fe3fb7860000000 +3d20c0104bfff4dd +6129086839400025 +792900203860000f +f949000039e00001 +612908703d20c010 +f9c9000079290020 +394000004bfff485 +79480fa4e9210090 +f94100a8e8810080 +4bfff56d7c69402a +88fb0001e94100a8 +7f8838007d1650ae +7d1750ae409e009c +7f88380088fb0003 +394a0004409e008c +409effbc2baa0010 +7de47b78e8610098 +7f5a7a143b39ffff +4bfff2117f5a07b4 +7fe3fb7860000000 +7b3900214bfff485 +e86100a04082ff5c +600000004bfff1f5 +fb3100003920000b +3860000ffb320000 +39200001f9330000 +4bfff3e1f9340000 +4bfff5157fe3fb78 +4bfff1c17e038378 +7f98d00060000000 +7f1ac378419cfd7c +39e000004bfffd78 +600000004bffff74 +7fe4fb787fc5f378 +4bfff19138628018 +3d20c01060000000 +612900283d40c010 +79290020614a0040 +39000001794a0020 +38fe00017bde0020 +7ce903a6fb890000 faa90000f90a0000 -382101404bffffc0 -48000b5038600001 -0100000000000000 -3c4c000100001280 -7c0802a638428e9c -38637f603c62ffff -f821ff5148000afd -3ee0c0103f00c010 -3f80c0103f60c010 -3fc0c0103fa0c010 -62f7100863181000 -639c0820637b0818 -63de080063bd0828 -600000004bfff045 -7b7b00203be00000 +614a00483d40c010 +42000034794a0020 +3af7ffff7fe3fb78 +7e0383784bfff489 +4bfff1313b7bffff +2f9f000160000000 +419e001c3ad6ffff +4bfffc943be00001 +f90a0000fb890000 +4bffffc0faa90000 +3860000138210140 +0000000048000b20 +0000128001000000 +38428df83c4c0001 +3c62ffff7c0802a6 +48000ad138637fd0 +3f20c010f821ff51 +3f80c0103f00c010 +3fe0c0103fa0c010 +6318100863391000 +63bd0820639c0818 +4bfff0a963ff0800 +3bc0000060000000 7bbd00207b9c0020 -3920000c7bde0020 -7af700207b180020 -3f20c01038600000 -fbf70000fbf80000 +3920000c7bff0020 +7b1800207b390020 +fbd9000038600000 3f40c0106063c350 -fbfc0000fbfb0000 -635a081063390808 -f93e0000fbfd0000 -7b5a00207b390020 -4bfff1f13ac00003 -fbfb00003920000e -38602710fbfc0000 -f93e0000fbfd0000 -4bfff1d13bc00001 -3940020039200002 -f93b0000386000c8 -39400006f95c0000 -3920000ff93d0000 -fbda0000f9390000 -fbfc0000fbfb0000 -f9390000fadd0000 -fbfb0000fbda0000 -39400009f95c0000 -f9390000fbdd0000 -f95b0000fbda0000 -f95c000039400920 -f9390000fbfd0000 -4bfff161fbda0000 -386000c839200004 -39200400f93b0000 -fbfd0000f93c0000 -fbda0000fad90000 -4bfffa054bfff13d -4bfff7394bfff6e9 -2c230000fbd80000 -fbd7000040820010 -480009d8382100b0 -4bfffff438600001 -0100000000000000 -2c24000000000a80 -3881fff040820008 -f86400002b850024 -4d9d002038600000 -78c683e43cc00001 -e924000060c62600 -2b8a002089490000 -7cc75436419d002c -4082001470e80001 -409e00542fa50000 -4800005c38a0000a -f924000039290001 -2fa500004bffffcc -2b8a0030409e0038 -409e003c38a0000a -2f8a007889490001 -89490001409e0030 -2f8a007838a00010 -39290002409e0020 -48000014f9240000 -409e000c2f850010 -419effd82b8a0030 -4800003038600000 -54ca063e38c9ffd0 -419d00342b8a0009 -7f8928007cc90734 -38e700014c9c0020 -f8e400007c6519d2 -e8e400007c691a14 -2fa9000089270000 -4e800020409effc8 -554a063e3949ff9f -419d00102b8a0019 -7d2907343929ffa9 -3949ffbf4bffffbc +fbdc0000fbd80000 +635a08083f60c010 +f93f0000fbdd0000 +7b5a0020637b0810 +3ae000037b7b0020 +3920000e4bfff25d +fbdd0000fbdc0000 +f93f000038602710 +4bfff2413be00001 +3940000639200200 +f93c0000386000c8 +f93d000039200002 +f93a00003920000f +fbdc0000fbfb0000 +f93a0000fafd0000 +f95c0000fbfb0000 +fbfd000039400920 +fbfb0000f93a0000 +fbdd0000f95c0000 +fbfb0000f93a0000 +392004004bfff1e5 +f93c0000386000c8 +fafa0000fbdd0000 +4bfff1c9fbfb0000 +4bfff7594bfffa75 +fbf900004bfff7a9 +408200102c230000 +382100b0fbf80000 +38600001480009dc +000000004bfffff4 +0000098001000000 +408200082c240000 +2b8500243881fff0 +38600000f8640000 +3cc000014d9d0020 +60c6260078c683e4 +89490000e9240000 +419d002c2b8a0020 +70e800017cc75436 +2fa5000040820014 +38a0000a409e0054 +392900014800005c +4bffffccf9240000 +409e00382fa50000 +38a0000a2b8a0030 +89490001409e003c +409e00302f8a0078 +38a0001089490001 +409e00202f8a0078 +f924000039290002 +2f85001048000014 +2b8a0030409e000c +38600000419effd8 +38c9ffd048000030 +2b8a000954ca063e +7cc90734419d0034 +4c9c00207f892800 +7c6519d238e70001 +7c691a14f8e40000 +89270000e8e40000 +409effc82fa90000 +3949ff9f4e800020 2b8a0019554a063e -3929ffc94d9d0020 -000000004bffffe4 -0000000000000000 -7d4348ae39200000 -409e000c2f8a0000 -4e8000207d234b78 -4bffffe839290001 +3929ffa9419d0010 +4bffffbc7d290734 +554a063e3949ffbf +4d9d00202b8a0019 +4bffffe43929ffc9 +0000000000000000 +3920000000000000 +2f8a00007d4348ae +7d234b78409e000c +392900014e800020 +000000004bffffe8 +0000000000000000 +2b8900193923ff9f +3863ffe04d9d0020 +4e8000207c6307b4 0000000000000000 -3923ff9f00000000 -4d9d00202b890019 -7c6307b43863ffe0 -000000004e800020 -0000000000000000 -38428b783c4c0001 -3d2037367c0802a6 -612935347d908026 -65293332792907c6 -6129313091810008 -f821ffa1480007d9 -7cde33787c7d1b78 -f92100203be00000 -612964633d206665 -65296261792907c6 -f921002861293938 -2fa900007ca92b78 -2fbf0000409e0080 -3be00001409e0008 -386000007fbf2040 -2e270000419d0058 -7f65f3923b9fffff -7ca928507d3bf1d2 -886500207ca12a14 -4bffff4141920010 -5463063e60000000 -e93d00002fbb0000 -7c69e1ae7f65db78 -409effc83b9cffff -38600001e93d0000 -fbfd00007fe9fa14 -8181000838210060 -480007747d908120 -409e00142b9e0010 -3bff00017929e102 -4bffff687fff07b4 -4bfffff07d29f392 -0300000000000000 -3c4c000100000580 -7c0802a638428a6c -f821ffb1480006e9 -7c7f1b78eb630000 -7cbd2b787c9c2378 -7fa3eb783bc00000 -600000004bfffe79 -409d00147fa3f040 -7d3b5050e95f0000 -419c00107fa9e040 -3860000138210050 -7d3df0ae480006f0 -992a00003bde0001 -39290001e93f0000 -4bffffb8f93f0000 +3c4c000100000000 +7c0802a638428b04 +7d9080263d203736 +792907c661293534 +9181000865293332 +480007d961293130 +7c7d1b78f821ffa1 +3be000007cde3378 +3d206665f9210020 +792907c661296463 +6129393865296261 +7ca92b78f9210028 +409e00802fa90000 +409e00082fbf0000 +7fbf20403be00001 +419d005838600000 +3b9fffff2e270000 +7d3bf1d27f65f392 +7ca12a147ca92850 +4192001088650020 +600000004bffff41 +2fbb00005463063e +7f65db78e93d0000 +3b9cffff7c69e1ae +e93d0000409effc8 +7fe9fa1438600001 +38210060fbfd0000 +7d90812081810008 +2b9e001048000774 +7929e102409e0014 +7fff07b43bff0001 +7d29f3924bffff68 +000000004bfffff0 +0000058003000000 +384289f83c4c0001 +480006e97c0802a6 +eb630000f821ffb1 +7c9c23787c7f1b78 +3bc000007cbd2b78 +4bfffe797fa3eb78 +7fa3f04060000000 +e95f0000409d0014 +7fa9e0407d3b5050 +38210050419c0010 +480006f038600001 +3bde00017d3df0ae +e93f0000992a0000 +f93f000039290001 +000000004bffffb8 +0000058001000000 +384289783c4c0001 +480006617c0802a6 +7c7d1b78f821ffa1 +7ca32b787c9b2378 +38a0000a38800000 +eb5d00007cde3378 +7d1943787cfc3b78 +4bfffcb57d3f4b78 +3940000060000000 +2fbe00007c6307b4 +2faa0000409e006c +39400001409e0008 +7f8348007d3f5214 +409d00447d2a07b4 +2f8300007c6a1850 +3929000178690020 +3d408000419c0010 +409e00087f835000 +2c29000139200001 +418200143929ffff +7d5a3850e8fd0000 +419c00307faad840 +3860000038210060 +2b9c001048000604 +7bdee102409e0014 +7d4a07b4394a0001 +7fdee3924bffff7c +9b2700004bfffff0 +394a0001e95d0000 +4bffffa8f95d0000 0100000000000000 -3c4c000100000580 -7c0802a6384289ec -f821ffa148000661 -7c9b23787c7d1b78 -388000007ca32b78 -7cde337838a0000a -7cfc3b78eb5d0000 -7d3f4b787d194378 -600000004bfffcb5 -7c6307b439400000 -409e006c2fbe0000 -409e00082faa0000 -7d3f521439400001 -7d2a07b47f834800 -7c6a1850409d0044 -786900202f830000 -419c001039290001 -7f8350003d408000 -39200001409e0008 -3929ffff2c290001 -e8fd000041820014 -7faad8407d5a3850 -38210060419c0030 -4800060438600000 -409e00142b9c0010 -394a00017bdee102 -4bffff7c7d4a07b4 -4bfffff07fdee392 -e95d00009b270000 -f95d0000394a0001 -000000004bffffa8 -0000078001000000 -384288f03c4c0001 -480005397c0802a6 -7c741b79f821fed1 -38600000f8610060 -2fa4000041820068 -39210040419e0060 -3ac4ffff3e42ffff -f92100703b410020 -3ae0000060000000 -3a527fe839228030 -f92100783ba10060 -ebc1006089250000 +3c4c000100000780 +7c0802a63842887c +f821fed148000539 +f86100607c741b79 +4182006838600000 +419e00602fa40000 +6000000039210040 +3b4100203ac4ffff +60000000f9210070 +392280a03ae00000 +3ba100603a428058 +89250000f9210078 +2fa90000ebc10060 +7ff4f050419e0010 +419c00207fbfb040 +993e000039200000 +7e941850e8610060 +382101307e8307b4 +2b89002548000508 +409e048839450001 +8925000038e00000 +f8a10068e9010070 +7d2741ae7cea07b4 +8d25000139070001 +2b8900647d0807b4 +2b890069419e0058 +2b890075419e0050 +2b890078419e0048 +2b890058419e0040 +2b890070419e0038 +2b890063419e0030 +2b890073419e0028 +2b890025419e0020 +2b89004f419e0018 +2b89006f419e0010 +409eff8838e70001 +2b890025394a0002 +7d1a42147d4a07b4 +992800207d5a5214 +409e00209aea0020 +f9210060393e0001 +993e000039200025 +38a90002e9210068 +892100414bffff04 +3a2600087fffb050 +3a600030eb660000 +3929ffd23b010042 +4082039c712900fd +3b2000043aa00000 +3a0000013b800000 +7ddb00d039e0002d +2b89006c48000108 +88f8000138d80001 +419d0118419e033c +419e02402b890063 +2b89004f419d0038 +2b890058419e01e8 +3949ffd0419e0188 +2b8a0009554a063e +395c0001419d00c4 +993c00207f81e214 +480000b0795c0020 +419e03042b890068 +419e000c2b890069 +409effc82b890064 +7d41e2142b890075 +7f6adb789aea0020 +57291838419e0034 +7e0948363929ffff +418200207f694839 +e921006099e80000 +f921006039290001 +7d52482a7b291f24 +e88100607dca5038 +38e0000a7d465378 +7f45d378f9410080 +7e689b7839200000 +7c9e20507fa3eb78 +4bfffc9d7c84f850 +e9410080e8810060 +38c0000a7ea7ab78 +7d4553787c9e2050 +7fa3eb787c84f850 +3b1800014bfffaed +e901006089380000 419e00102fa90000 -7fbfb0407ff4f050 -39200000419c0020 -e8610060993e0000 -7e8307b47e941850 -4800050838210130 -394500012b890025 -38e00000409e0488 -e901007089250000 -7cea07b4f8a10068 -390700017d2741ae -7d0807b48d250001 -419e00582b890064 -419e00502b890069 -419e00482b890075 -419e00402b890078 -419e00382b890058 -419e00302b890070 -419e00282b890063 -419e00202b890073 -419e00182b890025 -419e00102b89004f -38e700012b89006f -394a0002409eff88 -7d4a07b42b890025 -7d5a52147d1a4214 -9aea002099280020 -393e0001409e0020 -39200025f9210060 -e9210068993e0000 -4bffff0438a90002 -7fffb05089210041 -eb6600003a260008 -3b0100423a600030 -712900fd3929ffd2 -3aa000004082039c -3b8000003b200004 -39e0002d3a000001 -480001087ddb00d0 -38d800012b89006c -419e033c88f80001 -2b890063419d0118 -419d0038419e0240 -419e01e82b89004f -419e01882b890058 -554a063e3949ffd0 -419d00c42b8a0009 -7f81e214395c0001 -795c0020993c0020 -2b890068480000b0 -2b890069419e0304 -2b890064419e000c -2b890075409effc8 -9aea00207d41e214 -419e00347f6adb78 -3929ffff57291838 -7f6948397e094836 -99e8000041820020 -39290001e9210060 -7b291f24f9210060 -7dca50387d52482a -7d465378e8810060 -f941008038e0000a -392000007f45d378 -7fa3eb787e689b78 -7c84f8507c9e2050 -e88100604bfffc9d -7ea7ab78e9410080 -7c9e205038c0000a -7c84f8507d455378 -4bfffaed7fa3eb78 -893800003b180001 -2fa90000e9010060 -7d5e4050419e0010 -419dfee47fbf5040 -4bfffe907e268b78 -419e016c2b890073 -2b89006f419d006c -2b890070419e00d4 -7d21e214409efef0 -7f66db7838e00010 -9ae900207c8af850 -3920000239000020 -7fa3eb787f45d378 -e88100604bfffc0d -7fa3eb78e8a10078 -7c84f8507c9e2050 -e88100604bfffb75 -38c000107ea7ab78 -7c9e20507f65db78 -2b8900784bffff5c -2b89007a419e0018 -2b890075419e01cc -3aa000014bfffeb8 +7fbf50407d5e4050 +7e268b78419dfee4 +2b8900734bfffe90 +419d006c419e016c +419e00d42b89006f +409efef02b890070 38e000107d21e214 -7e689b787c8af850 -7b291f249ae90020 -7fa3eb787f45d378 -392000007d72482a -7d665b787f6b5838 -4bfffb89f9610080 +7c8af8507f66db78 +390000209ae90020 +7f45d37839200002 +4bfffc0d7fa3eb78 +e8a10078e8810060 +7c9e20507fa3eb78 +4bfffb757c84f850 7ea7ab78e8810060 -7c9e205038c00010 -7d655b78e9610080 -7d21e2144bfffeec -7c8af85038e00008 +7f65db7838c00010 +4bffff5c7c9e2050 +419e00182b890078 +419e01cc2b89007a +4bfffeb82b890075 +7d21e2143aa00001 +7c8af85038e00010 9ae900207e689b78 7f45d3787b291f24 7d72482a7fa3eb78 7f6b583839200000 f96100807d665b78 -e88100604bfffb35 -38c000087ea7ab78 -4bffffac7c9e2050 -390000207d21e214 -38c0000138e0000a -7f45d3789ae90020 -7c8af85039200000 -4bfffaf97fa3eb78 -9b690000e9210060 -39290001e9210060 -4bfffe6cf9210060 -38a0000a7d21e214 -f9410088f9010090 -7f43d37838800000 -4bfff7a99ae90020 -f861008060000000 -4bfff8cd7f63db78 -e921008060000000 -409d00407fa91840 -e94100887c634850 -2fa30000e9010090 -7d4af85039230001 -39200001409e0008 -e8c100602c290001 -418200103929ffff -7faa38407ce83050 -e8810060419d0020 -7fa3eb787f65db78 -7c84f8507c9e2050 -4bfffdd44bfff9cd -98e6000038e00020 -38e70001e8e10060 -4bffffb4f8e10060 -3b2000082b87006c -7cd83378409efdb0 -2b8700684bfffda8 -409efd9c3b200002 -3b2000017cd83378 -3b2000084bfffd90 -3a6000204bfffd88 -4bfffc603b010041 -7d455378993e0000 -39290001e9210060 -4bfffb24f9210060 -0100000000000000 -f9c1ff7000001280 -fa01ff80f9e1ff78 -fa41ff90fa21ff88 -fa81ffa0fa61ff98 -fac1ffb0faa1ffa8 -fb01ffc0fae1ffb8 -fb41ffd0fb21ffc8 -fb81ffe0fb61ffd8 -fbc1fff0fba1ffe8 -f8010010fbe1fff8 -e9c1ff704e800020 -ea01ff80e9e1ff78 -ea41ff90ea21ff88 -ea81ffa0ea61ff98 -eac1ffb0eaa1ffa8 -eb01ffc0eae1ffb8 -eb41ffd0eb21ffc8 -eb81ffe0eb61ffd8 -eba1ffe8e8010010 -ebc1fff07c0803a6 -4e800020ebe1fff8 -e8010010ebc1fff0 -7c0803a6ebe1fff8 -000000004e800020 +e88100604bfffb89 +38c000107ea7ab78 +e96100807c9e2050 +4bfffeec7d655b78 +38e000087d21e214 +7e689b787c8af850 +7b291f249ae90020 +7fa3eb787f45d378 +392000007d72482a +7d665b787f6b5838 +4bfffb35f9610080 +7ea7ab78e8810060 +7c9e205038c00008 +7d21e2144bffffac +38e0000a39000020 +9ae9002038c00001 +392000007f45d378 +7fa3eb787c8af850 +e92100604bfffaf9 +e92100609b690000 +f921006039290001 +7d21e2144bfffe6c +f901009038a0000a +38800000f9410088 +9ae900207f43d378 +600000004bfff7a9 +7f63db78f8610080 +600000004bfff8cd +7fa91840e9210080 +7c634850409d0040 +e9010090e9410088 +392300012fa30000 +409e00087d4af850 +2c29000139200001 +3929ffffe8c10060 +7ce8305041820010 +419d00207faa3840 +7f65db78e8810060 +7c9e20507fa3eb78 +4bfff9cd7c84f850 +38e000204bfffdd4 +e8e1006098e60000 +f8e1006038e70001 +2b87006c4bffffb4 +409efdb03b200008 +4bfffda87cd83378 +3b2000022b870068 +7cd83378409efd9c +4bfffd903b200001 +4bfffd883b200008 +3b0100413a600020 +993e00004bfffc60 +e92100607d455378 +f921006039290001 +000000004bfffb24 +0000128001000000 +f9e1ff78f9c1ff70 +fa21ff88fa01ff80 +fa61ff98fa41ff90 +faa1ffa8fa81ffa0 +fae1ffb8fac1ffb0 +fb21ffc8fb01ffc0 +fb61ffd8fb41ffd0 +fba1ffe8fb81ffe0 +fbe1fff8fbc1fff0 +4e800020f8010010 +e9e1ff78e9c1ff70 +ea21ff88ea01ff80 +ea61ff98ea41ff90 +eaa1ffa8ea81ffa0 +eae1ffb8eac1ffb0 +eb21ffc8eb01ffc0 +eb61ffd8eb41ffd0 +e8010010eb81ffe0 +7c0803a6eba1ffe8 +ebe1fff8ebc1fff0 +ebc1fff04e800020 +ebe1fff8e8010010 +4e8000207c0803a6 6d6f636c65570a0a 63694d206f742065 2120747461776f72 @@ -1473,10 +1455,10 @@ e8010010ebc1fff0 000000000000002d 30252d2b64323025 0000000000006432 -00000000c0100850 -00000000c01008b8 -00000000c0100920 -00000000c0100988 +00000000c0100830 +00000000c0100860 +00000000c0100890 +00000000c01008c0 6f6e204d41524453 207265646e752077 6572617764726168 diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v index 727e21a..18cb7f1 100644 --- a/litedram/generated/arty/litedram_core.v +++ b/litedram/generated/arty/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 10:54:03 +// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 11:57:11 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, @@ -24,8 +24,8 @@ module litedram_core( output wire init_error, input wire [13:0] csr_port0_adr, input wire csr_port0_we, - input wire [7:0] csr_port0_dat_w, - output wire [7:0] csr_port0_dat_r, + input wire [31:0] csr_port0_dat_w, + output wire [31:0] csr_port0_dat_r, output wire user_clk, output wire user_rst, input wire user_port_native_0_cmd_valid, @@ -1485,8 +1485,8 @@ reg init_error_storage = 1'd0; reg init_error_re = 1'd0; wire [13:0] csr_port_adr; wire csr_port_we; -wire [7:0] csr_port_dat_w; -wire [7:0] csr_port_dat_r; +wire [31:0] csr_port_dat_w; +wire [31:0] csr_port_dat_r; wire user_port_cmd_valid; wire user_port_cmd_ready; wire user_port_cmd_payload_we; @@ -1566,8 +1566,8 @@ reg new_master_rdata_valid7 = 1'd0; reg new_master_rdata_valid8 = 1'd0; wire [13:0] interface0_bank_bus_adr; wire interface0_bank_bus_we; -wire [7:0] interface0_bank_bus_dat_w; -reg [7:0] interface0_bank_bus_dat_r = 8'd0; +wire [31:0] interface0_bank_bus_dat_w; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; wire csrbank0_init_done0_re; wire csrbank0_init_done0_r; wire csrbank0_init_done0_we; @@ -1579,8 +1579,8 @@ wire csrbank0_init_error0_w; reg csrbank0_sel = 1'd0; wire [13:0] interface1_bank_bus_adr; wire interface1_bank_bus_we; -wire [7:0] interface1_bank_bus_dat_w; -reg [7:0] interface1_bank_bus_dat_r = 8'd0; +wire [31:0] interface1_bank_bus_dat_w; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; wire csrbank1_half_sys8x_taps0_re; wire [4:0] csrbank1_half_sys8x_taps0_r; wire csrbank1_half_sys8x_taps0_we; @@ -1596,8 +1596,8 @@ wire [1:0] csrbank1_dly_sel0_w; reg csrbank1_sel = 1'd0; wire [13:0] interface2_bank_bus_adr; wire interface2_bank_bus_we; -wire [7:0] interface2_bank_bus_dat_w; -reg [7:0] interface2_bank_bus_dat_r = 8'd0; +wire [31:0] interface2_bank_bus_dat_w; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; wire csrbank2_dfii_control0_re; wire [3:0] csrbank2_dfii_control0_r; wire csrbank2_dfii_control0_we; @@ -1606,199 +1606,87 @@ wire csrbank2_dfii_pi0_command0_re; wire [5:0] csrbank2_dfii_pi0_command0_r; wire csrbank2_dfii_pi0_command0_we; wire [5:0] csrbank2_dfii_pi0_command0_w; -wire csrbank2_dfii_pi0_address1_re; -wire [5:0] csrbank2_dfii_pi0_address1_r; -wire csrbank2_dfii_pi0_address1_we; -wire [5:0] csrbank2_dfii_pi0_address1_w; wire csrbank2_dfii_pi0_address0_re; -wire [7:0] csrbank2_dfii_pi0_address0_r; +wire [13:0] csrbank2_dfii_pi0_address0_r; wire csrbank2_dfii_pi0_address0_we; -wire [7:0] csrbank2_dfii_pi0_address0_w; +wire [13:0] csrbank2_dfii_pi0_address0_w; wire csrbank2_dfii_pi0_baddress0_re; wire [2:0] csrbank2_dfii_pi0_baddress0_r; wire csrbank2_dfii_pi0_baddress0_we; wire [2:0] csrbank2_dfii_pi0_baddress0_w; -wire csrbank2_dfii_pi0_wrdata3_re; -wire [7:0] csrbank2_dfii_pi0_wrdata3_r; -wire csrbank2_dfii_pi0_wrdata3_we; -wire [7:0] csrbank2_dfii_pi0_wrdata3_w; -wire csrbank2_dfii_pi0_wrdata2_re; -wire [7:0] csrbank2_dfii_pi0_wrdata2_r; -wire csrbank2_dfii_pi0_wrdata2_we; -wire [7:0] csrbank2_dfii_pi0_wrdata2_w; -wire csrbank2_dfii_pi0_wrdata1_re; -wire [7:0] csrbank2_dfii_pi0_wrdata1_r; -wire csrbank2_dfii_pi0_wrdata1_we; -wire [7:0] csrbank2_dfii_pi0_wrdata1_w; wire csrbank2_dfii_pi0_wrdata0_re; -wire [7:0] csrbank2_dfii_pi0_wrdata0_r; +wire [31:0] csrbank2_dfii_pi0_wrdata0_r; wire csrbank2_dfii_pi0_wrdata0_we; -wire [7:0] csrbank2_dfii_pi0_wrdata0_w; -wire csrbank2_dfii_pi0_rddata3_re; -wire [7:0] csrbank2_dfii_pi0_rddata3_r; -wire csrbank2_dfii_pi0_rddata3_we; -wire [7:0] csrbank2_dfii_pi0_rddata3_w; -wire csrbank2_dfii_pi0_rddata2_re; -wire [7:0] csrbank2_dfii_pi0_rddata2_r; -wire csrbank2_dfii_pi0_rddata2_we; -wire [7:0] csrbank2_dfii_pi0_rddata2_w; -wire csrbank2_dfii_pi0_rddata1_re; -wire [7:0] csrbank2_dfii_pi0_rddata1_r; -wire csrbank2_dfii_pi0_rddata1_we; -wire [7:0] csrbank2_dfii_pi0_rddata1_w; -wire csrbank2_dfii_pi0_rddata0_re; -wire [7:0] csrbank2_dfii_pi0_rddata0_r; -wire csrbank2_dfii_pi0_rddata0_we; -wire [7:0] csrbank2_dfii_pi0_rddata0_w; +wire [31:0] csrbank2_dfii_pi0_wrdata0_w; +wire csrbank2_dfii_pi0_rddata_re; +wire [31:0] csrbank2_dfii_pi0_rddata_r; +wire csrbank2_dfii_pi0_rddata_we; +wire [31:0] csrbank2_dfii_pi0_rddata_w; wire csrbank2_dfii_pi1_command0_re; wire [5:0] csrbank2_dfii_pi1_command0_r; wire csrbank2_dfii_pi1_command0_we; wire [5:0] csrbank2_dfii_pi1_command0_w; -wire csrbank2_dfii_pi1_address1_re; -wire [5:0] csrbank2_dfii_pi1_address1_r; -wire csrbank2_dfii_pi1_address1_we; -wire [5:0] csrbank2_dfii_pi1_address1_w; wire csrbank2_dfii_pi1_address0_re; -wire [7:0] csrbank2_dfii_pi1_address0_r; +wire [13:0] csrbank2_dfii_pi1_address0_r; wire csrbank2_dfii_pi1_address0_we; -wire [7:0] csrbank2_dfii_pi1_address0_w; +wire [13:0] csrbank2_dfii_pi1_address0_w; wire csrbank2_dfii_pi1_baddress0_re; wire [2:0] csrbank2_dfii_pi1_baddress0_r; wire csrbank2_dfii_pi1_baddress0_we; wire [2:0] csrbank2_dfii_pi1_baddress0_w; -wire csrbank2_dfii_pi1_wrdata3_re; -wire [7:0] csrbank2_dfii_pi1_wrdata3_r; -wire csrbank2_dfii_pi1_wrdata3_we; -wire [7:0] csrbank2_dfii_pi1_wrdata3_w; -wire csrbank2_dfii_pi1_wrdata2_re; -wire [7:0] csrbank2_dfii_pi1_wrdata2_r; -wire csrbank2_dfii_pi1_wrdata2_we; -wire [7:0] csrbank2_dfii_pi1_wrdata2_w; -wire csrbank2_dfii_pi1_wrdata1_re; -wire [7:0] csrbank2_dfii_pi1_wrdata1_r; -wire csrbank2_dfii_pi1_wrdata1_we; -wire [7:0] csrbank2_dfii_pi1_wrdata1_w; wire csrbank2_dfii_pi1_wrdata0_re; -wire [7:0] csrbank2_dfii_pi1_wrdata0_r; +wire [31:0] csrbank2_dfii_pi1_wrdata0_r; wire csrbank2_dfii_pi1_wrdata0_we; -wire [7:0] csrbank2_dfii_pi1_wrdata0_w; -wire csrbank2_dfii_pi1_rddata3_re; -wire [7:0] csrbank2_dfii_pi1_rddata3_r; -wire csrbank2_dfii_pi1_rddata3_we; -wire [7:0] csrbank2_dfii_pi1_rddata3_w; -wire csrbank2_dfii_pi1_rddata2_re; -wire [7:0] csrbank2_dfii_pi1_rddata2_r; -wire csrbank2_dfii_pi1_rddata2_we; -wire [7:0] csrbank2_dfii_pi1_rddata2_w; -wire csrbank2_dfii_pi1_rddata1_re; -wire [7:0] csrbank2_dfii_pi1_rddata1_r; -wire csrbank2_dfii_pi1_rddata1_we; -wire [7:0] csrbank2_dfii_pi1_rddata1_w; -wire csrbank2_dfii_pi1_rddata0_re; -wire [7:0] csrbank2_dfii_pi1_rddata0_r; -wire csrbank2_dfii_pi1_rddata0_we; -wire [7:0] csrbank2_dfii_pi1_rddata0_w; +wire [31:0] csrbank2_dfii_pi1_wrdata0_w; +wire csrbank2_dfii_pi1_rddata_re; +wire [31:0] csrbank2_dfii_pi1_rddata_r; +wire csrbank2_dfii_pi1_rddata_we; +wire [31:0] csrbank2_dfii_pi1_rddata_w; wire csrbank2_dfii_pi2_command0_re; wire [5:0] csrbank2_dfii_pi2_command0_r; wire csrbank2_dfii_pi2_command0_we; wire [5:0] csrbank2_dfii_pi2_command0_w; -wire csrbank2_dfii_pi2_address1_re; -wire [5:0] csrbank2_dfii_pi2_address1_r; -wire csrbank2_dfii_pi2_address1_we; -wire [5:0] csrbank2_dfii_pi2_address1_w; wire csrbank2_dfii_pi2_address0_re; -wire [7:0] csrbank2_dfii_pi2_address0_r; +wire [13:0] csrbank2_dfii_pi2_address0_r; wire csrbank2_dfii_pi2_address0_we; -wire [7:0] csrbank2_dfii_pi2_address0_w; +wire [13:0] csrbank2_dfii_pi2_address0_w; wire csrbank2_dfii_pi2_baddress0_re; wire [2:0] csrbank2_dfii_pi2_baddress0_r; wire csrbank2_dfii_pi2_baddress0_we; wire [2:0] csrbank2_dfii_pi2_baddress0_w; -wire csrbank2_dfii_pi2_wrdata3_re; -wire [7:0] csrbank2_dfii_pi2_wrdata3_r; -wire csrbank2_dfii_pi2_wrdata3_we; -wire [7:0] csrbank2_dfii_pi2_wrdata3_w; -wire csrbank2_dfii_pi2_wrdata2_re; -wire [7:0] csrbank2_dfii_pi2_wrdata2_r; -wire csrbank2_dfii_pi2_wrdata2_we; -wire [7:0] csrbank2_dfii_pi2_wrdata2_w; -wire csrbank2_dfii_pi2_wrdata1_re; -wire [7:0] csrbank2_dfii_pi2_wrdata1_r; -wire csrbank2_dfii_pi2_wrdata1_we; -wire [7:0] csrbank2_dfii_pi2_wrdata1_w; wire csrbank2_dfii_pi2_wrdata0_re; -wire [7:0] csrbank2_dfii_pi2_wrdata0_r; +wire [31:0] csrbank2_dfii_pi2_wrdata0_r; wire csrbank2_dfii_pi2_wrdata0_we; -wire [7:0] csrbank2_dfii_pi2_wrdata0_w; -wire csrbank2_dfii_pi2_rddata3_re; -wire [7:0] csrbank2_dfii_pi2_rddata3_r; -wire csrbank2_dfii_pi2_rddata3_we; -wire [7:0] csrbank2_dfii_pi2_rddata3_w; -wire csrbank2_dfii_pi2_rddata2_re; -wire [7:0] csrbank2_dfii_pi2_rddata2_r; -wire csrbank2_dfii_pi2_rddata2_we; -wire [7:0] csrbank2_dfii_pi2_rddata2_w; -wire csrbank2_dfii_pi2_rddata1_re; -wire [7:0] csrbank2_dfii_pi2_rddata1_r; -wire csrbank2_dfii_pi2_rddata1_we; -wire [7:0] csrbank2_dfii_pi2_rddata1_w; -wire csrbank2_dfii_pi2_rddata0_re; -wire [7:0] csrbank2_dfii_pi2_rddata0_r; -wire csrbank2_dfii_pi2_rddata0_we; -wire [7:0] csrbank2_dfii_pi2_rddata0_w; +wire [31:0] csrbank2_dfii_pi2_wrdata0_w; +wire csrbank2_dfii_pi2_rddata_re; +wire [31:0] csrbank2_dfii_pi2_rddata_r; +wire csrbank2_dfii_pi2_rddata_we; +wire [31:0] csrbank2_dfii_pi2_rddata_w; wire csrbank2_dfii_pi3_command0_re; wire [5:0] csrbank2_dfii_pi3_command0_r; wire csrbank2_dfii_pi3_command0_we; wire [5:0] csrbank2_dfii_pi3_command0_w; -wire csrbank2_dfii_pi3_address1_re; -wire [5:0] csrbank2_dfii_pi3_address1_r; -wire csrbank2_dfii_pi3_address1_we; -wire [5:0] csrbank2_dfii_pi3_address1_w; wire csrbank2_dfii_pi3_address0_re; -wire [7:0] csrbank2_dfii_pi3_address0_r; +wire [13:0] csrbank2_dfii_pi3_address0_r; wire csrbank2_dfii_pi3_address0_we; -wire [7:0] csrbank2_dfii_pi3_address0_w; +wire [13:0] csrbank2_dfii_pi3_address0_w; wire csrbank2_dfii_pi3_baddress0_re; wire [2:0] csrbank2_dfii_pi3_baddress0_r; wire csrbank2_dfii_pi3_baddress0_we; wire [2:0] csrbank2_dfii_pi3_baddress0_w; -wire csrbank2_dfii_pi3_wrdata3_re; -wire [7:0] csrbank2_dfii_pi3_wrdata3_r; -wire csrbank2_dfii_pi3_wrdata3_we; -wire [7:0] csrbank2_dfii_pi3_wrdata3_w; -wire csrbank2_dfii_pi3_wrdata2_re; -wire [7:0] csrbank2_dfii_pi3_wrdata2_r; -wire csrbank2_dfii_pi3_wrdata2_we; -wire [7:0] csrbank2_dfii_pi3_wrdata2_w; -wire csrbank2_dfii_pi3_wrdata1_re; -wire [7:0] csrbank2_dfii_pi3_wrdata1_r; -wire csrbank2_dfii_pi3_wrdata1_we; -wire [7:0] csrbank2_dfii_pi3_wrdata1_w; wire csrbank2_dfii_pi3_wrdata0_re; -wire [7:0] csrbank2_dfii_pi3_wrdata0_r; +wire [31:0] csrbank2_dfii_pi3_wrdata0_r; wire csrbank2_dfii_pi3_wrdata0_we; -wire [7:0] csrbank2_dfii_pi3_wrdata0_w; -wire csrbank2_dfii_pi3_rddata3_re; -wire [7:0] csrbank2_dfii_pi3_rddata3_r; -wire csrbank2_dfii_pi3_rddata3_we; -wire [7:0] csrbank2_dfii_pi3_rddata3_w; -wire csrbank2_dfii_pi3_rddata2_re; -wire [7:0] csrbank2_dfii_pi3_rddata2_r; -wire csrbank2_dfii_pi3_rddata2_we; -wire [7:0] csrbank2_dfii_pi3_rddata2_w; -wire csrbank2_dfii_pi3_rddata1_re; -wire [7:0] csrbank2_dfii_pi3_rddata1_r; -wire csrbank2_dfii_pi3_rddata1_we; -wire [7:0] csrbank2_dfii_pi3_rddata1_w; -wire csrbank2_dfii_pi3_rddata0_re; -wire [7:0] csrbank2_dfii_pi3_rddata0_r; -wire csrbank2_dfii_pi3_rddata0_we; -wire [7:0] csrbank2_dfii_pi3_rddata0_w; +wire [31:0] csrbank2_dfii_pi3_wrdata0_w; +wire csrbank2_dfii_pi3_rddata_re; +wire [31:0] csrbank2_dfii_pi3_rddata_r; +wire csrbank2_dfii_pi3_rddata_we; +wire [31:0] csrbank2_dfii_pi3_rddata_w; reg csrbank2_sel = 1'd0; wire [13:0] adr; wire we; -wire [7:0] dat_w; -wire [7:0] dat_r; +wire [31:0] dat_w; +wire [31:0] dat_r; reg rhs_array_muxed0 = 1'd0; reg [13:0] rhs_array_muxed1 = 14'd0; reg [2:0] rhs_array_muxed2 = 3'd0; @@ -10730,7 +10618,7 @@ reg dummy_d_282; // synthesis translate_on always @(*) begin csrbank0_sel <= 1'd0; - csrbank0_sel <= (interface0_bank_bus_adr[13:11] == 2'd2); + csrbank0_sel <= (interface0_bank_bus_adr[13:9] == 2'd2); if (interface0_bank_bus_adr[0]) begin csrbank0_sel <= 1'd0; end @@ -10739,11 +10627,11 @@ always @(*) begin // synthesis translate_on end assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd0)); -assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd0)); +assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd0)); +assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd0)); assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd1)); -assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd1)); +assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd1)); +assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd1)); assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; @@ -10752,7 +10640,7 @@ reg dummy_d_283; // synthesis translate_on always @(*) begin csrbank1_sel <= 1'd0; - csrbank1_sel <= (interface1_bank_bus_adr[13:11] == 1'd0); + csrbank1_sel <= (interface1_bank_bus_adr[13:9] == 1'd0); if (interface1_bank_bus_adr[0]) begin csrbank1_sel <= 1'd0; end @@ -10761,35 +10649,35 @@ always @(*) begin // synthesis translate_on end assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; -assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd0)); -assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd0)); +assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd0)); +assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd0)); assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; -assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd1)); -assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd1)); +assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd1)); +assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd1)); assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd2)); -assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd2)); +assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd2)); +assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd2)); assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd3)); -assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd3)); +assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd3)); +assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd3)); assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd4)); -assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd4)); +assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd4)); +assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd4)); assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; -assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd5)); -assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd5)); +assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd5)); +assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd5)); assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd6)); -assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd6)); assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd7)); -assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd7)); assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd8)); -assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd8)); assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd9)); -assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd9)); assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0]; assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; @@ -10799,7 +10687,7 @@ reg dummy_d_284; // synthesis translate_on always @(*) begin csrbank2_sel <= 1'd0; - csrbank2_sel <= (interface2_bank_bus_adr[13:11] == 1'd1); + csrbank2_sel <= (interface2_bank_bus_adr[13:9] == 1'd1); if (interface2_bank_bus_adr[0]) begin csrbank2_sel <= 1'd0; end @@ -10808,217 +10696,105 @@ always @(*) begin // synthesis translate_on end assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; -assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd0)); -assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd0)); +assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd0)); +assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd0)); assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd1)); -assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd1)); +assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd1)); +assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd1)); assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd2)); -assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd2)); -assign csrbank2_dfii_pi0_address1_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi0_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd3)); -assign csrbank2_dfii_pi0_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd3)); -assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd4)); -assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd4)); +assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd2)); +assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd2)); +assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[13:0]; +assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd3)); +assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd3)); assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd5)); -assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd5)); -assign csrbank2_dfii_pi0_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd6)); -assign csrbank2_dfii_pi0_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd6)); -assign csrbank2_dfii_pi0_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd7)); -assign csrbank2_dfii_pi0_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd7)); -assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd8)); -assign csrbank2_dfii_pi0_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd8)); -assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd9)); -assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd9)); -assign csrbank2_dfii_pi0_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd10)); -assign csrbank2_dfii_pi0_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd10)); -assign csrbank2_dfii_pi0_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd11)); -assign csrbank2_dfii_pi0_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd11)); -assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd12)); -assign csrbank2_dfii_pi0_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd12)); -assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd13)); -assign csrbank2_dfii_pi0_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd13)); +assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd4)); +assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd4)); +assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd5)); +assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd5)); +assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd6)); +assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd6)); assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd14)); -assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd14)); +assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd7)); +assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd7)); assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd15)); -assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd15)); -assign csrbank2_dfii_pi1_address1_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi1_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd16)); -assign csrbank2_dfii_pi1_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd16)); -assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd17)); -assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd17)); +assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd8)); +assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd8)); +assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[13:0]; +assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd9)); +assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd9)); assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd18)); -assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd18)); -assign csrbank2_dfii_pi1_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd19)); -assign csrbank2_dfii_pi1_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd19)); -assign csrbank2_dfii_pi1_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd20)); -assign csrbank2_dfii_pi1_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd20)); -assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd21)); -assign csrbank2_dfii_pi1_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd21)); -assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd22)); -assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd22)); -assign csrbank2_dfii_pi1_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd23)); -assign csrbank2_dfii_pi1_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd23)); -assign csrbank2_dfii_pi1_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd24)); -assign csrbank2_dfii_pi1_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd24)); -assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd25)); -assign csrbank2_dfii_pi1_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd25)); -assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd26)); -assign csrbank2_dfii_pi1_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd26)); +assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd10)); +assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd10)); +assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd11)); +assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd11)); +assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd12)); +assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd12)); assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd27)); -assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd27)); +assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd13)); +assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd13)); assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd28)); -assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd28)); -assign csrbank2_dfii_pi2_address1_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi2_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd29)); -assign csrbank2_dfii_pi2_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd29)); -assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd30)); -assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd30)); +assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd14)); +assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd14)); +assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[13:0]; +assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd15)); +assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd15)); assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd31)); -assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd31)); -assign csrbank2_dfii_pi2_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd32)); -assign csrbank2_dfii_pi2_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd32)); -assign csrbank2_dfii_pi2_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd33)); -assign csrbank2_dfii_pi2_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd33)); -assign csrbank2_dfii_pi2_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd34)); -assign csrbank2_dfii_pi2_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd34)); -assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd35)); -assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd35)); -assign csrbank2_dfii_pi2_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd36)); -assign csrbank2_dfii_pi2_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd36)); -assign csrbank2_dfii_pi2_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd37)); -assign csrbank2_dfii_pi2_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd37)); -assign csrbank2_dfii_pi2_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd38)); -assign csrbank2_dfii_pi2_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd38)); -assign csrbank2_dfii_pi2_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd39)); -assign csrbank2_dfii_pi2_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd39)); +assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd16)); +assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd16)); +assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd17)); +assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd17)); +assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd18)); +assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd18)); assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd40)); -assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd40)); +assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd19)); +assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd19)); assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd41)); -assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd41)); -assign csrbank2_dfii_pi3_address1_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi3_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd42)); -assign csrbank2_dfii_pi3_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd42)); -assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd43)); -assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd43)); +assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd20)); +assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd20)); +assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[13:0]; +assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd21)); +assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd21)); assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd44)); -assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd44)); -assign csrbank2_dfii_pi3_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd45)); -assign csrbank2_dfii_pi3_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd45)); -assign csrbank2_dfii_pi3_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd46)); -assign csrbank2_dfii_pi3_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd46)); -assign csrbank2_dfii_pi3_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd47)); -assign csrbank2_dfii_pi3_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd47)); -assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd48)); -assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd48)); -assign csrbank2_dfii_pi3_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd49)); -assign csrbank2_dfii_pi3_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd49)); -assign csrbank2_dfii_pi3_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd50)); -assign csrbank2_dfii_pi3_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd50)); -assign csrbank2_dfii_pi3_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd51)); -assign csrbank2_dfii_pi3_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd51)); -assign csrbank2_dfii_pi3_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd52)); -assign csrbank2_dfii_pi3_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd52)); +assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd22)); +assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd22)); +assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd23)); +assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd23)); +assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd24)); +assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd24)); assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; -assign csrbank2_dfii_pi0_address1_w = litedramcore_phaseinjector0_address_storage[13:8]; -assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[7:0]; +assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0]; assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; -assign csrbank2_dfii_pi0_wrdata3_w = litedramcore_phaseinjector0_wrdata_storage[31:24]; -assign csrbank2_dfii_pi0_wrdata2_w = litedramcore_phaseinjector0_wrdata_storage[23:16]; -assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[15:8]; -assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[7:0]; -assign csrbank2_dfii_pi0_rddata3_w = litedramcore_phaseinjector0_status[31:24]; -assign csrbank2_dfii_pi0_rddata2_w = litedramcore_phaseinjector0_status[23:16]; -assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_status[15:8]; -assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_status[7:0]; -assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata0_we; +assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0]; +assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata_we; assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0]; -assign csrbank2_dfii_pi1_address1_w = litedramcore_phaseinjector1_address_storage[13:8]; -assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[7:0]; +assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0]; assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; -assign csrbank2_dfii_pi1_wrdata3_w = litedramcore_phaseinjector1_wrdata_storage[31:24]; -assign csrbank2_dfii_pi1_wrdata2_w = litedramcore_phaseinjector1_wrdata_storage[23:16]; -assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[15:8]; -assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[7:0]; -assign csrbank2_dfii_pi1_rddata3_w = litedramcore_phaseinjector1_status[31:24]; -assign csrbank2_dfii_pi1_rddata2_w = litedramcore_phaseinjector1_status[23:16]; -assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_status[15:8]; -assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_status[7:0]; -assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata0_we; +assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0]; +assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata_we; assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0]; -assign csrbank2_dfii_pi2_address1_w = litedramcore_phaseinjector2_address_storage[13:8]; -assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[7:0]; +assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0]; assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0]; -assign csrbank2_dfii_pi2_wrdata3_w = litedramcore_phaseinjector2_wrdata_storage[31:24]; -assign csrbank2_dfii_pi2_wrdata2_w = litedramcore_phaseinjector2_wrdata_storage[23:16]; -assign csrbank2_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[15:8]; -assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[7:0]; -assign csrbank2_dfii_pi2_rddata3_w = litedramcore_phaseinjector2_status[31:24]; -assign csrbank2_dfii_pi2_rddata2_w = litedramcore_phaseinjector2_status[23:16]; -assign csrbank2_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_status[15:8]; -assign csrbank2_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_status[7:0]; -assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata0_we; +assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0]; +assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0]; +assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata_we; assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0]; -assign csrbank2_dfii_pi3_address1_w = litedramcore_phaseinjector3_address_storage[13:8]; -assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[7:0]; +assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0]; assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0]; -assign csrbank2_dfii_pi3_wrdata3_w = litedramcore_phaseinjector3_wrdata_storage[31:24]; -assign csrbank2_dfii_pi3_wrdata2_w = litedramcore_phaseinjector3_wrdata_storage[23:16]; -assign csrbank2_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[15:8]; -assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[7:0]; -assign csrbank2_dfii_pi3_rddata3_w = litedramcore_phaseinjector3_status[31:24]; -assign csrbank2_dfii_pi3_rddata2_w = litedramcore_phaseinjector3_status[23:16]; -assign csrbank2_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_status[15:8]; -assign csrbank2_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_status[7:0]; -assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata0_we; +assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0]; +assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0]; +assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata_we; assign adr = csr_port_adr; assign we = csr_port_we; assign dat_w = csr_port_dat_w; @@ -14159,7 +13935,7 @@ always @(posedge sys_clk) begin new_master_rdata_valid8 <= new_master_rdata_valid7; interface0_bank_bus_dat_r <= 1'd0; if (csrbank0_sel) begin - case (interface0_bank_bus_adr[3]) + case (interface0_bank_bus_adr[1]) 1'd0: begin interface0_bank_bus_dat_r <= csrbank0_init_done0_w; end @@ -14178,7 +13954,7 @@ always @(posedge sys_clk) begin init_error_re <= csrbank0_init_error0_re; interface1_bank_bus_dat_r <= 1'd0; if (csrbank1_sel) begin - case (interface1_bank_bus_adr[6:3]) + case (interface1_bank_bus_adr[4:1]) 1'd0: begin interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; end @@ -14225,7 +14001,7 @@ always @(posedge sys_clk) begin a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; interface2_bank_bus_dat_r <= 1'd0; if (csrbank2_sel) begin - case (interface2_bank_bus_adr[8:3]) + case (interface2_bank_bus_adr[5:1]) 1'd0: begin interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; end @@ -14236,154 +14012,70 @@ always @(posedge sys_clk) begin interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; end 3'd4: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; end 3'd5: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; end 3'd6: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w; end 3'd7: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; end 4'd8: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w; + interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; end 4'd9: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; end 4'd10: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; end 4'd11: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; end 4'd12: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w; end 4'd13: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; end 4'd14: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; + interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; end 4'd15: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; end 5'd16: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; end 5'd17: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; end 5'd18: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w; end 5'd19: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata3_w; - end - 5'd20: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata2_w; - end - 5'd21: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w; - end - 5'd22: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; - end - 5'd23: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata3_w; - end - 5'd24: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata2_w; - end - 5'd25: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w; - end - 5'd26: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w; - end - 5'd27: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; - end - 5'd28: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; - end - 5'd29: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address1_w; - end - 5'd30: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; - end - 5'd31: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; - end - 6'd32: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata3_w; - end - 6'd33: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata2_w; - end - 6'd34: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata1_w; - end - 6'd35: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; - end - 6'd36: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata3_w; - end - 6'd37: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata2_w; - end - 6'd38: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata1_w; - end - 6'd39: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata0_w; - end - 6'd40: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; end - 6'd41: begin + 5'd20: begin interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; end - 6'd42: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address1_w; - end - 6'd43: begin + 5'd21: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; end - 6'd44: begin + 5'd22: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; end - 6'd45: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata3_w; - end - 6'd46: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata2_w; - end - 6'd47: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata1_w; - end - 6'd48: begin + 5'd23: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; end - 6'd49: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata3_w; - end - 6'd50: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata2_w; - end - 6'd51: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata1_w; - end - 6'd52: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata0_w; + 5'd24: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w; end endcase end @@ -14395,112 +14087,64 @@ always @(posedge sys_clk) begin litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; end litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; - if (csrbank2_dfii_pi0_address1_re) begin - litedramcore_phaseinjector0_address_storage[13:8] <= csrbank2_dfii_pi0_address1_r; - end if (csrbank2_dfii_pi0_address0_re) begin - litedramcore_phaseinjector0_address_storage[7:0] <= csrbank2_dfii_pi0_address0_r; + litedramcore_phaseinjector0_address_storage[13:0] <= csrbank2_dfii_pi0_address0_r; end litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; if (csrbank2_dfii_pi0_baddress0_re) begin litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; end litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; - if (csrbank2_dfii_pi0_wrdata3_re) begin - litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank2_dfii_pi0_wrdata3_r; - end - if (csrbank2_dfii_pi0_wrdata2_re) begin - litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank2_dfii_pi0_wrdata2_r; - end - if (csrbank2_dfii_pi0_wrdata1_re) begin - litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank2_dfii_pi0_wrdata1_r; - end if (csrbank2_dfii_pi0_wrdata0_re) begin - litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank2_dfii_pi0_wrdata0_r; + litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; end litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; if (csrbank2_dfii_pi1_command0_re) begin litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; end litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; - if (csrbank2_dfii_pi1_address1_re) begin - litedramcore_phaseinjector1_address_storage[13:8] <= csrbank2_dfii_pi1_address1_r; - end if (csrbank2_dfii_pi1_address0_re) begin - litedramcore_phaseinjector1_address_storage[7:0] <= csrbank2_dfii_pi1_address0_r; + litedramcore_phaseinjector1_address_storage[13:0] <= csrbank2_dfii_pi1_address0_r; end litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; if (csrbank2_dfii_pi1_baddress0_re) begin litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; end litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; - if (csrbank2_dfii_pi1_wrdata3_re) begin - litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank2_dfii_pi1_wrdata3_r; - end - if (csrbank2_dfii_pi1_wrdata2_re) begin - litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank2_dfii_pi1_wrdata2_r; - end - if (csrbank2_dfii_pi1_wrdata1_re) begin - litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank2_dfii_pi1_wrdata1_r; - end if (csrbank2_dfii_pi1_wrdata0_re) begin - litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank2_dfii_pi1_wrdata0_r; + litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; end litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; if (csrbank2_dfii_pi2_command0_re) begin litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; end litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; - if (csrbank2_dfii_pi2_address1_re) begin - litedramcore_phaseinjector2_address_storage[13:8] <= csrbank2_dfii_pi2_address1_r; - end if (csrbank2_dfii_pi2_address0_re) begin - litedramcore_phaseinjector2_address_storage[7:0] <= csrbank2_dfii_pi2_address0_r; + litedramcore_phaseinjector2_address_storage[13:0] <= csrbank2_dfii_pi2_address0_r; end litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; if (csrbank2_dfii_pi2_baddress0_re) begin litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; end litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; - if (csrbank2_dfii_pi2_wrdata3_re) begin - litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank2_dfii_pi2_wrdata3_r; - end - if (csrbank2_dfii_pi2_wrdata2_re) begin - litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank2_dfii_pi2_wrdata2_r; - end - if (csrbank2_dfii_pi2_wrdata1_re) begin - litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank2_dfii_pi2_wrdata1_r; - end if (csrbank2_dfii_pi2_wrdata0_re) begin - litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank2_dfii_pi2_wrdata0_r; + litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; end litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; if (csrbank2_dfii_pi3_command0_re) begin litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; end litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; - if (csrbank2_dfii_pi3_address1_re) begin - litedramcore_phaseinjector3_address_storage[13:8] <= csrbank2_dfii_pi3_address1_r; - end if (csrbank2_dfii_pi3_address0_re) begin - litedramcore_phaseinjector3_address_storage[7:0] <= csrbank2_dfii_pi3_address0_r; + litedramcore_phaseinjector3_address_storage[13:0] <= csrbank2_dfii_pi3_address0_r; end litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; if (csrbank2_dfii_pi3_baddress0_re) begin litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; end litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; - if (csrbank2_dfii_pi3_wrdata3_re) begin - litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank2_dfii_pi3_wrdata3_r; - end - if (csrbank2_dfii_pi3_wrdata2_re) begin - litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank2_dfii_pi3_wrdata2_r; - end - if (csrbank2_dfii_pi3_wrdata1_re) begin - litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank2_dfii_pi3_wrdata1_r; - end if (csrbank2_dfii_pi3_wrdata0_re) begin - litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank2_dfii_pi3_wrdata0_r; + litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; end litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; if (sys_rst) begin diff --git a/litedram/generated/nexys-video/litedram-wrapper.vhdl b/litedram/generated/nexys-video/litedram-wrapper.vhdl index 475e088..46ae4b1 100644 --- a/litedram/generated/nexys-video/litedram-wrapper.vhdl +++ b/litedram/generated/nexys-video/litedram-wrapper.vhdl @@ -82,8 +82,8 @@ architecture behaviour of litedram_wrapper is user_rst : out std_ulogic; csr_port0_adr : in std_ulogic_vector(13 downto 0); csr_port0_we : in std_ulogic; - csr_port0_dat_w : in std_ulogic_vector(7 downto 0); - csr_port0_dat_r : out std_ulogic_vector(7 downto 0); + csr_port0_dat_w : in std_ulogic_vector(31 downto 0); + csr_port0_dat_r : out std_ulogic_vector(31 downto 0); user_port_native_0_cmd_valid : in std_ulogic; user_port_native_0_cmd_ready : out std_ulogic; user_port_native_0_cmd_we : in std_ulogic; @@ -116,8 +116,8 @@ architecture behaviour of litedram_wrapper is signal csr_port0_adr : std_ulogic_vector(13 downto 0); signal csr_port0_we : std_ulogic; - signal csr_port0_dat_w : std_ulogic_vector(7 downto 0); - signal csr_port0_dat_r : std_ulogic_vector(7 downto 0); + signal csr_port0_dat_w : std_ulogic_vector(31 downto 0); + signal csr_port0_dat_r : std_ulogic_vector(31 downto 0); signal csr_port_read_comb : std_ulogic_vector(63 downto 0); signal csr_valid : std_ulogic; signal csr_write_valid : std_ulogic; @@ -205,8 +205,8 @@ begin -- DRAM CSR interface signals. We only support access to the bottom byte csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; csr_write_valid <= wb_in.we and wb_in.sel(0); - csr_port0_adr <= wb_in.adr(13 downto 0) when wb_is_csr = '1' else (others => '0'); - csr_port0_dat_w <= wb_in.dat(7 downto 0); + csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0'); + csr_port0_dat_w <= wb_in.dat(31 downto 0); csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; -- Wishbone out signals @@ -215,7 +215,7 @@ begin user_port0_wdata_ready when state = MWRITE else user_port0_rdata_valid when state = MREAD else '0'; - csr_port_read_comb <= x"00000000000000" & csr_port0_dat_r; + csr_port_read_comb <= x"00000000" & csr_port0_dat_r; wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else wb_init_out.dat when wb_is_init = '1' else user_port0_rdata_data(127 downto 64) when ad3 = '1' else diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init index d07879f..7708f27 100644 --- a/litedram/generated/nexys-video/litedram_core.init +++ b/litedram/generated/nexys-video/litedram_core.init @@ -513,17 +513,17 @@ a64b5a7d14004a39 38429d003c4c0001 600000003d20c000 7929002061292000 -3d40c000f9228040 +3d40c000f9228000 614a201839200035 7c0004ac794a0020 4e8000207d2057aa 0000000000000000 3c4c000100000000 6000000038429cbc -39290010e9228040 +39290010e9228000 7d204eaa7c0004ac 4082ffe871290008 -e922804060000000 +e922800060000000 7c604faa7c0004ac 000000004e800020 0000000000000000 @@ -533,7 +533,7 @@ fbc1fff07c0802a6 f80100107c7f1b78 7fbff040f821ffd1 38210030409e000c -893f00004800194c +893f000048001908 409e000c2f89000a 4bffff813860000d 3bff0001887f0000 @@ -549,11 +549,11 @@ f88101983bc10020 f8e101b038c10198 f90101b87fc3f378 f94101c8f92101c0 -60000000480012ed +60000000480012a9 7c641b787c7f1b78 4bffff457fc3f378 7fe3fb7838210170 -00000000480018ac +0000000048001868 0000028001000000 38429b983c4c0001 fbe1fff87c0802a6 @@ -561,50 +561,50 @@ fbe1fff87c0802a6 f821ff91f8010010 3d2000014bfffe81 7d2903a6612986a0 -e922804060000000 +e922800060000000 7c0004ac39290010 4200ffec7d204eaa -38637d183c62ffff +38637cd83c62ffff 3880ffff4bffff3d 7c0004ac54840002 3c62ffff7c8026ea -38637d383fe0c000 +38637cf83fe0c000 4bffff1963ff0008 7bff00203c62ffff -4bffff0938637d58 +4bffff0938637d18 7fe0feea7c0004ac 4182001073e90001 -38637d703c62ffff +38637d303c62ffff 73e900024bfffeed 418200104e000000 -38637d783c62ffff +38637d383c62ffff 3fe2ffff4bfffed5 -7fe3fb783bff7f60 +7fe3fb783bff7f20 3c80c0004bfffec5 7884002060840010 7c8026ea7c0004ac 7884b2823c62ffff -4bfffea138637d80 +4bfffea138637d40 3c80c00041920028 7884002060840018 7c8026ea7c0004ac 788465023c62ffff -4bfffe7938637da0 +4bfffe7938637d60 612900203d20c000 7c0004ac79290020 3c80000f7d204eea 608442403c62ffff -7c89239238637dc0 +7c89239238637d80 7fe3fb784bfffe4d 419200284bfffe45 3c82ffff3ca2ffff -38a57de03c62ffff -38637df838847df0 -48000be54bfffe25 +38a57da03c62ffff +38637db838847db0 +48000bc94bfffe25 3c62ffff60000000 -4bfffe1138637e28 +4bfffe1138637de8 8181000838210070 -480017147d908120 +480016d07d908120 0300000000000000 3863ffff00000180 3923000178630020 @@ -625,726 +625,718 @@ f86900007c6307b4 39400000f90a0000 4e800020f9490000 0000000000000000 -3920000400000000 -7d2903a63884ffff -386300088d240001 -4200fff4f923fff8 +8944000100000000 +794a45e489240000 +892400027d4a4b78 +7d2a5378792983e4 +7929c1e489240003 +552ac03e7d295378 +512a463e512a421e +f923000079490020 000000004e800020 0000000000000000 -3884ffff39200004 -e92300007d2903a6 -9d24000138630008 -4e8000204200fff4 +792ac202e9230000 +9944000299240003 +79294602792a8402 +9924000099440001 +000000004e800020 0000000000000000 -3c4c000100000000 -7c0802a63842990c -f821ff014800156d -3c62ffff7c7e1b78 -3be0000438637ef8 -600000004bfffcdd -394100603cc08020 -3920002a60c60003 -78c600207d5d5378 -38e0000039000004 -7928f8427d0903a6 -7d2900d0792907e0 -7d2842787d293038 -7d0a39ae79090020 -4200ffe038e70001 -394a00043bffffff -4082ffc47bff0021 -3940000939200818 -3860000f3b800001 -39200820fbe90000 -3ea2ffff237e0001 -fbe900007f7b07b4 -3ae008d839200828 -3a8008e03a600025 +384298e83c4c0001 +480015057c0802a6 +7c7e1b78f821ff01 +38637eb83c62ffff +4bfffcb93be00004 +3cc0802060000000 +60c6000339410060 +7d5d53783920002a +3900000478c60020 +7d0903a638e00000 +792907e07928f842 +7d2930387d2900d0 +790900207d284278 +38e700017d0a39ae +3bffffff4200ffe0 +7bff0021394a0004 +392008184082ffc4 +3b80000139400009 +fbe900003860000f +237e000139200820 +7f7b07b43ea2ffff 39200808fbe90000 -3ac100703a400001 -f94900003ab57f20 -7f1dda1439200810 -4bfffe31fb890000 -386008307fa4eb78 -388100644bfffebd -4bfffeb138600898 -3860090038810068 -3881006c4bfffea5 -4bfffe9938600968 -3940001739200950 -fbe900007fc3f378 -fbe9000039200958 -fbe9000039200960 -f949000039200940 -fb89000039200948 -fbe90000392008e8 -fbe90000392008f0 -fbe90000392008f8 -4bfffdd93be00000 -79390020213e0003 -7f3dca147d2907b4 -fa7700007e3d4a14 -3860000ffa540000 -3b4000013b800000 -7b890fa44bfffd85 -7c75482a7ec4b378 -7d38e0ae4bfffe39 -7f89500089580010 -7d39e0ae409e0048 -7f89500089510010 -3b9c0004409e0038 -409effc82bbc0010 -393f00012fba0000 -409e00287d3c07b4 -419e001c2f890020 -7f9fe3787fc3f378 -4bffff884bfffd85 -4bffffc83b400000 -38bf00017f9fe378 -7cbc07b47fc3f378 -213e00034bfffd65 -793700207f7dda14 -7efdba147d2907b4 -3a4000253a8008d8 -3a2000013a6008e0 -fa5400007fbd4a14 -3860000ffa330000 -3b2000013b400000 -7b490fa44bfffcc5 -7c75482a7ec4b378 -7d38d0ae4bfffd79 -7f895000895b0010 -7d37d0ae409e0044 -7f895000895d0010 -3b5a0004409e0034 -409effc82bba0010 -419e00282fb90000 -2f89001f393c0001 -419d00187d3c07b4 -4bfffcc97fc3f378 -3b2000004bffff8c -2f9f00204bffffcc -7fbd0e707fbfe214 -3c62ffff409e006c -4bfffa3138637f08 -7fc3f37860000000 -4bfffc593be00000 -419c00707f9fe800 -3940081839200000 -f92a00003860000f -f92a000039400820 -f92a000039400828 -3940000b39200808 -39200810f9490000 -f949000039400001 -382101004bfffbed -7cbfe0504800129c -7ca50e703c62ffff -7fa4eb787ca50194 -7ca507b438637f10 -600000004bfff9b5 -7fc3f3784bffff84 -4bfffc113bff0001 -4bffff7c7fff07b4 -0100000000000000 -3c4c000100000f80 -7c0802a638429594 -3940000e39200800 -38637fc83c62ffff -f821ffa1f8010010 -4bfff961f9490000 -3821006060000000 -7c0803a6e8010010 -000000004e800020 -0000008001000000 -384295483c4c0001 +3a6000253ae00868 +f94900003a800870 +3a40000139200810 +3ab57ee03ac10070 +7f1dda14fb890000 +7fa4eb784bfffe15 +4bfffea138600828 +3860085838810064 +388100684bfffe95 +4bfffe8938600888 +386008b83881006c +392008a84bfffe7d +7fc3f37839400017 +392008b0fbe90000 +39200898fbe90000 +392008a0f9490000 +39200878fb890000 +39200880fbe90000 +3be00000fbe90000 +213e00034bfffdcd +7d2907b479390020 +7e3d4a147f3dca14 +fa540000fa770000 +3b8000003860000f +4bfffd793b400001 +7ec4b3787b890fa4 +4bfffe4d7c75482a +895800107d38e0ae +409e00487f895000 +895100107d39e0ae +409e00387f895000 +2bbc00103b9c0004 +2fba0000409effc8 +7d3c07b4393f0001 +2f890020409e0028 +7fc3f378419e001c +4bfffd797f9fe378 +3b4000004bffff88 +7f9fe3784bffffc8 +7fc3f37838bf0001 +4bfffd597cbc07b4 +7f7dda14213e0003 +7d2907b479370020 +3a8008687efdba14 +3a6008703a400025 +7fbd4a143a200001 +fa330000fa540000 +3b4000003860000f +4bfffcb93b200001 +7ec4b3787b490fa4 +4bfffd8d7c75482a +895b00107d38d0ae +409e00447f895000 +895d00107d37d0ae +409e00347f895000 +2bba00103b5a0004 +2fb90000409effc8 +393c0001419e0028 +7d3c07b42f89001f +7fc3f378419d0018 +4bffff8c4bfffcbd +4bffffcc3b200000 +7fbfe2142f9f0020 +409e00647fbd0e70 +38637ec83c62ffff +600000004bfffa25 +3be000007fc3f378 +7f9fe8004bfffc4d +39200000419c0068 +3860000f39400818 +39400820f92a0000 +39200808f92a0000 +f94900003940000b +3940000139200810 +4bfffbe9f9490000 +4800125438210100 +3c62ffff7cbfe050 +7ca501947ca50e70 +38637ed07fa4eb78 +4bfff9b17ca507b4 +4bffff8c60000000 +3bff00017fc3f378 +7fff07b44bfffc0d +000000004bffff84 +00000f8001000000 +384295903c4c0001 392008007c0802a6 -3c62ffff39400001 -f801001038637f40 +3c62ffff3940000e +f801001038637f88 f9490000f821ffa1 -600000004bfff915 +600000004bfff95d e801001038210060 4e8000207c0803a6 0100000000000000 3c4c000100000080 -7c0802a6384294fc -7d0903a639000080 -3d2040003d40aaaa -48001179614aaaaa -91490000f821ff81 -4200fff839290004 -3d00aaaa39400080 -3d2040007d4903a6 -6108aaaa3be00000 -7f8a400081490000 -3bff0001419e000c -392900047fff07b4 -390000804200ffe8 -7d0903a63d405555 -614a55553d204000 +7c0802a638429544 +3940000139200800 +38637f003c62ffff +f821ffa1f8010010 +4bfff911f9490000 +3821006060000000 +7c0803a6e8010010 +000000004e800020 +0000008001000000 +384294f83c4c0001 +390000807c0802a6 +3d40aaaa7d0903a6 +614aaaaa3d204000 +f821ff8148001131 3929000491490000 394000804200fff8 -7d4903a63d005555 -610855553d204000 -7f8a400081490000 -3bff0001419e000c -392900047fff07b4 -2fbf00004200ffe8 -3c62ffff419e001c -7fe4fb7838a00100 -4bfff82138637e40 -3d00000860000000 +7d4903a63d00aaaa +3be000003d204000 +814900006108aaaa +419e000c7f8a4000 +7fff07b43bff0001 +4200ffe839290004 +3d40555539000080 +3d2040007d0903a6 +91490000614a5555 +4200fff839290004 +3d00555539400080 +3d2040007d4903a6 +8149000061085555 +419e000c7f8a4000 +7fff07b43bff0001 +4200ffe839290004 +419e001c2fbf0000 +38a001003c62ffff +38637e007fe4fb78 +600000004bfff81d +3ce080203d000008 +60e700037d0903a6 +392000013d404000 +7928f84278e70020 +7d2900d0792907e0 +7d293838394a0004 +912afffc7d294278 +3d0000084200ffe4 7d0903a63ce08020 3d40400060e70003 -78e7002039200001 -792907e07928f842 -394a00047d2900d0 +392000013ba00000 +7928f84278e70020 +7d2900d0792907e0 7d2942787d293838 -4200ffe4912afffc -3ce080203d000008 -60e700037d0903a6 -3ba000003d404000 -78e7002039200001 -792907e07928f842 -7d2938387d2900d0 -810a00007d294278 -419e000c7f884840 -7fbd07b43bbd0001 -4200ffd4394a0004 -419e001c2fbd0000 -3ca000083c62ffff -38637e687fa4eb78 -600000004bfff775 -3940000039202000 -3d2a10007d2903a6 -3929000279480020 -79291764394a0001 -4200ffe891090000 -3940000039202000 -3bc000007d2903a6 -792917643d2a1000 -5529043e81290008 -419e000c7f895000 -7fde07b43bde0001 -4200ffdc394a0001 -419e001c2fbe0000 -38a020003c62ffff -38637e907fc4f378 -600000004bfff6f5 -386000007fffea14 -2f9f00007ffff214 -3c62ffff409e009c -4bfff6d138637eb8 -7d3602a660000000 -792a00203d000008 -392000007d0903a6 -792700203d091000 -3929000179081764 -4200ffec90e80000 -7d2450507c9602a6 -7c844b963c806400 -7d3602a678840020 -792900203d000008 -3d4040007d0903a6 -394a0004810a0000 -7cb602a64200fff8 -3ca064007d254850 -3c62ffff7ca54b96 -78a5006038637ec8 -600000004bfff64d -3821008038600001 -0000000048000f34 -0000038001000000 -384292383c4c0001 -48000e8d7c0802a6 -3be00028f821feb1 -3b8000403bc00001 -3e42ffff3ba00000 -3aa000003e82ffff -3a947f603a527fa8 -386000004bfffc75 -4bfff8213b610070 -fbdc0000fbdf0000 -3ae1006338600001 -3ac10061fbbf0000 -392000024bfff805 -38637f803c62ffff -fbdc0000f93f0000 -3be00000fbbf0000 -600000004bfff5ad -fb6100803d22ffff -f92100a039297f90 -39297f203d22ffff -3d22fffff92100a8 -f92100b039297fa0 -3b80000139210064 -3bc000007f9cf830 -39210068f9210088 -3b0000007f9c07b4 -f92100903ba00000 -f92100983921006c -7fbeeb7848000034 -419e02602f9d0007 -3940004839200028 -3bbd000139000001 -7fbd07b4fb890000 -f90a00007f58d378 -39410060faa90000 -3920002a3b400004 -390000047d595378 -7d0903a638e00000 -7928f8423cc08020 -792907e060c60003 -78c600207d2900d0 -7d2842787d293038 -7d0a39ae79090020 -4200ffd438e70001 -394a00043b5affff -4082ffb87b5a0021 -3940000939200818 -3860000f3a200001 -39200820fb490000 -3a0008e039e00025 -fb49000039c00001 -fb49000039200828 -f949000039200808 -fa29000039200810 -7f24cb784bfff68d -4bfff71938600830 -38600898e8810088 -4bfff7093b200020 -38600900e8810090 -e88100984bfff6fd -4bfff6f138600968 -3940001739200950 -7fa5eb78e86100a0 -fb4900007fe4fb78 -fb49000039200958 -fb49000039200960 -f949000039200940 -fa29000039200948 -3a2008d8392008e8 -392008f0fb490000 -392008f8fb490000 -3b400000fb490000 -600000004bfff3ed -4bfff6197fe3fb78 -f9d00000f9f10000 -3a6000013860000f -394000004bfff5dd -79480fa4e92100a8 -f94100b8e8810080 -4bfff6857c69402a -88fb0001e94100b8 -7f8838007d1650ae -7d1750ae409e00b4 -7f88380088fb0003 -394a0004409e00a4 -409effbc2baa0010 -7e649b78e86100b0 -7f5a9a143b39ffff -4bfff3697f5a07b4 +7f884840810a0000 +3bbd0001419e000c +394a00047fbd07b4 +2fbd00004200ffd4 +3c62ffff419e001c +7fa4eb783ca00008 +4bfff77138637e28 +3920200060000000 +7d2903a639400000 +794800203d2a1000 +394a000139290002 +9109000079291764 +392020004200ffe8 +7d2903a639400000 +3d2a10003bc00000 +8129000879291764 +7f8950005529043e +3bde0001419e000c +394a00017fde07b4 +2fbe00004200ffdc +3c62ffff419e001c +7fc4f37838a02000 +4bfff6f138637e50 +7fffea1460000000 +7ffff21438600000 +409e009c2f9f0000 +38637e783c62ffff +600000004bfff6cd +3d0000087d3602a6 +7d0903a6792a0020 +3d09100039200000 +7908176479270020 +90e8000039290001 +7c9602a64200ffec +3c8064007d245050 +788400207c844b96 +3d0000087d3602a6 +7d0903a679290020 +810a00003d404000 +4200fff8394a0004 +7d2548507cb602a6 +7ca54b963ca06400 +38637e883c62ffff +4bfff64978a50060 +3860000160000000 +48000eec38210080 +0100000000000000 +3c4c000100000380 +7c0802a638429234 +f821feb148000e45 +3bc000013be00028 +3ba000003b800040 +3e82ffff3e42ffff +3a527f683aa00000 +4bfffc753a947f20 +3b61007038600000 +fbdf00004bfff81d +38600001fbdc0000 +fbbf00003ae10063 +4bfff8013ac10061 +3c62ffff39200002 +f93f000038637f40 +fbbf0000fbdc0000 +4bfff5a93be00000 +3d22ffff60000000 +39297f50fb610080 +3d22fffff92100a0 +f92100a839297ee0 +39297f603d22ffff +39210064f92100b0 +7f9cf8303b800001 +f92100883bc00000 +7f9c07b439210068 +3ba000003b000000 +3921006cf9210090 +48000034f9210098 +2f9d00077fbeeb78 +39200028419e0240 +3900000139400048 +fb8900003bbd0001 +7f58d3787fbd07b4 +faa90000f90a0000 +3b40000439410060 +7d5953783920002a +38e0000039000004 +3cc080207d0903a6 +60c600037928f842 +7d2900d0792907e0 +7d29303878c60020 +790900207d284278 +38e700017d0a39ae +3b5affff4200ffd4 +7b5a0021394a0004 +392008184082ffb8 +3a20000139400009 +fb4900003860000f +39e0002539200820 +39c000013a000870 +39200808fb490000 +39200810f9490000 +4bfff691fa290000 +386008287f24cb78 +e88100884bfff71d +3b20002038600858 +e88100904bfff70d +4bfff70138600888 +386008b8e8810098 +392008a84bfff6f5 +e86100a039400017 +7fe4fb787fa5eb78 +392008b0fb490000 +39200898fb490000 +392008a0f9490000 +39200878fa290000 +fb4900003a200868 +fb49000039200880 +4bfff4013b400000 7fe3fb7860000000 -7b3900214bfff5cd -7e4393784082ff78 -600000004bfff34d -3940000b39200818 -fb2900003860000f -fb29000039200820 -fb29000039200828 -f949000039200808 -3940000139200810 -4bfff521f9490000 -4bfff6117fe3fb78 -4bfff3017e83a378 -7f98d00060000000 -7f1ac378419cfdac -3a6000004bfffda8 -3c62ffff4bffff5c -7fe4fb787fc5f378 -4bfff2d138637fb0 -7bde002060000000 -3940004039200028 -38fe000139000001 -7ce903a6fb890000 +f9f100004bfff62d +3860000ff9d00000 +4bfff5f13a600001 +e92100a839400000 +e881008079480fa4 +7c69402af94100b8 +e94100b84bfff6b9 +7d1650ae88fb0001 +409e00ac7f883800 +88fb00037d1750ae +409e009c7f883800 +2baa0010394a0004 +e86100b0409effbc +3b39ffff7e649b78 +7f5a07b47f5a9a14 +600000004bfff37d +4bfff5e17fe3fb78 +4082ff787b390021 +4bfff3617e439378 +3920081860000000 +3860000f3940000b +39200820fb290000 +39200808fb290000 +39200810f9490000 +f949000039400001 +7fe3fb784bfff53d +7e83a3784bfff651 +600000004bfff31d +419cfdcc7f98d000 +4bfffdc87f1ac378 +4bffff643a600000 +7fc5f3783c62ffff +38637f707fe4fb78 +600000004bfff2ed +392000287bde0020 +3900000139400040 +fb89000038fe0001 +f90a00007ce903a6 +39400048faa90000 +7fe3fb7842000034 +4bfff5dd3af7ffff +3b7bffff7e83a378 +600000004bfff2a5 +3ad6ffff2f9f0001 +3be00001419e001c +fb8900004bfffd14 faa90000f90a0000 -4200003439400048 -3af7ffff7fe3fb78 -7e83a3784bfff59d -4bfff2893b7bffff -2f9f000160000000 -419e001c3ad6ffff -4bfffcf43be00001 -f90a0000fb890000 -4bffffc0faa90000 -3860000138210150 -0000000048000b10 -0000128001000000 -38428e503c4c0001 -3c62ffff7c0802a6 -48000abd38637f68 -3be00000f821ff51 -3b8008203b600818 -3bc008003ba00828 -3ae010083b001000 -3b4008103b200808 -4bfff2013ac00003 +382101504bffffc0 +48000ae838600001 +0100000000000000 +3c4c000100001280 +7c0802a638428e6c +38637f283c62ffff +f821ff5148000a99 +3b8008183bc00000 +3be008003ba00820 +3b0010083b201000 +3b6008103b400808 +4bfff2213ae00003 3920000c60000000 -fbf70000fbf80000 -fbfb000038600000 -6063c350fbfc0000 -f93e0000fbfd0000 -3920000e4bfff3e5 -fbfc0000fbfb0000 -fbfd000038602710 -3bc00001f93e0000 -392000024bfff3c5 -386000c839400200 -f95c0000f93b0000 -f93d000039400006 -f93900003920000f -fbfb0000fbda0000 -fadd0000fbfc0000 -fbda0000f9390000 +fbd80000fbd90000 +fbdc000038600000 +6063c350fbdd0000 +4bfff409f93f0000 +fbdc00003920000e +38602710fbdd0000 +3be00001f93f0000 +392002004bfff3ed +386000c839400006 +39200002f93c0000 +3920000ff93d0000 +fbfb0000f93a0000 +fafd0000fbdc0000 +fbfb0000f93a0000 +39400920f95c0000 +f93a0000fbfd0000 f95c0000fbfb0000 -fbdd000039400009 -fbda0000f9390000 -39400920f95b0000 -fbfd0000f95c0000 -fbda0000f9390000 -392000044bfff355 -f93b0000386000c8 -f93c000039200400 -fad90000fbfd0000 -4bfff331fbda0000 -4bfff7e54bfffaf9 -fbd800004bfff82d -408200102c230000 -382100b0fbd70000 -38600001480009d8 -000000004bfffff4 -00000a8001000000 -408200082c240000 -2b8500243881fff0 -38600000f8640000 -3cc000014d9d0020 -60c6260078c683e4 -89490000e9240000 -419d002c2b8a0020 -70e800017cc75436 -2fa5000040820014 -38a0000a409e0054 -392900014800005c -4bffffccf9240000 -409e00382fa50000 -38a0000a2b8a0030 -89490001409e003c -409e00302f8a0078 -38a0001089490001 -409e00202f8a0078 -f924000039290002 -2f85001048000014 -2b8a0030409e000c -38600000419effd8 -38c9ffd048000030 -2b8a000954ca063e -7cc90734419d0034 -4c9c00207f892800 -7c6519d238e70001 -7c691a14f8e40000 -89270000e8e40000 -409effc82fa90000 -3949ff9f4e800020 +f93a0000fbdd0000 +4bfff391fbfb0000 +386000c839200400 +fbdd0000f93c0000 +fbfb0000fafa0000 +4bfffb414bfff375 +4bfff8754bfff82d +2c230000fbf90000 +fbf8000040820010 +480009dc382100b0 +4bfffff438600001 +0100000000000000 +2c24000000000980 +3881fff040820008 +f86400002b850024 +4d9d002038600000 +78c683e43cc00001 +e924000060c62600 +2b8a002089490000 +7cc75436419d002c +4082001470e80001 +409e00542fa50000 +4800005c38a0000a +f924000039290001 +2fa500004bffffcc +2b8a0030409e0038 +409e003c38a0000a +2f8a007889490001 +89490001409e0030 +2f8a007838a00010 +39290002409e0020 +48000014f9240000 +409e000c2f850010 +419effd82b8a0030 +4800003038600000 +54ca063e38c9ffd0 +419d00342b8a0009 +7f8928007cc90734 +38e700014c9c0020 +f8e400007c6519d2 +e8e400007c691a14 +2fa9000089270000 +4e800020409effc8 +554a063e3949ff9f +419d00102b8a0019 +7d2907343929ffa9 +3949ffbf4bffffbc 2b8a0019554a063e -3929ffa9419d0010 -4bffffbc7d290734 -554a063e3949ffbf -4d9d00202b8a0019 -4bffffe43929ffc9 -0000000000000000 -3920000000000000 -2f8a00007d4348ae -7d234b78409e000c -392900014e800020 -000000004bffffe8 -0000000000000000 -2b8900193923ff9f -3863ffe04d9d0020 -4e8000207c6307b4 +3929ffc94d9d0020 +000000004bffffe4 0000000000000000 -3c4c000100000000 -7c0802a638428b6c -7d9080263d203736 -792907c661293534 -9181000865293332 -480007d961293130 -7c7d1b78f821ffa1 -3be000007cde3378 -3d206665f9210020 -792907c661296463 -6129393865296261 -7ca92b78f9210028 -409e00802fa90000 -409e00082fbf0000 -7fbf20403be00001 -419d005838600000 -3b9fffff2e270000 -7d3bf1d27f65f392 -7ca12a147ca92850 -4192001088650020 -600000004bffff41 -2fbb00005463063e -7f65db78e93d0000 -3b9cffff7c69e1ae -e93d0000409effc8 -7fe9fa1438600001 -38210060fbfd0000 -7d90812081810008 -2b9e001048000774 -7929e102409e0014 -7fff07b43bff0001 -7d29f3924bffff68 -000000004bfffff0 -0000058003000000 -38428a603c4c0001 -480006e97c0802a6 -eb630000f821ffb1 -7c9c23787c7f1b78 -3bc000007cbd2b78 -4bfffe797fa3eb78 -7fa3f04060000000 -e95f0000409d0014 -7fa9e0407d3b5050 -38210050419c0010 -480006f038600001 -3bde00017d3df0ae -e93f0000992a0000 -f93f000039290001 -000000004bffffb8 -0000058001000000 -384289e03c4c0001 -480006617c0802a6 -7c7d1b78f821ffa1 -7ca32b787c9b2378 -38a0000a38800000 -eb5d00007cde3378 -7d1943787cfc3b78 -4bfffcb57d3f4b78 -3940000060000000 -2fbe00007c6307b4 -2faa0000409e006c -39400001409e0008 -7f8348007d3f5214 -409d00447d2a07b4 -2f8300007c6a1850 -3929000178690020 -3d408000419c0010 -409e00087f835000 -2c29000139200001 -418200143929ffff -7d5a3850e8fd0000 -419c00307faad840 -3860000038210060 -2b9c001048000604 -7bdee102409e0014 -7d4a07b4394a0001 -7fdee3924bffff7c -9b2700004bfffff0 -394a0001e95d0000 -4bffffa8f95d0000 +7d4348ae39200000 +409e000c2f8a0000 +4e8000207d234b78 +4bffffe839290001 +0000000000000000 +3923ff9f00000000 +4d9d00202b890019 +7c6307b43863ffe0 +000000004e800020 +0000000000000000 +38428bb03c4c0001 +3d2037367c0802a6 +612935347d908026 +65293332792907c6 +6129313091810008 +f821ffa1480007d9 +7cde33787c7d1b78 +f92100203be00000 +612964633d206665 +65296261792907c6 +f921002861293938 +2fa900007ca92b78 +2fbf0000409e0080 +3be00001409e0008 +386000007fbf2040 +2e270000419d0058 +7f65f3923b9fffff +7ca928507d3bf1d2 +886500207ca12a14 +4bffff4141920010 +5463063e60000000 +e93d00002fbb0000 +7c69e1ae7f65db78 +409effc83b9cffff +38600001e93d0000 +fbfd00007fe9fa14 +8181000838210060 +480007747d908120 +409e00142b9e0010 +3bff00017929e102 +4bffff687fff07b4 +4bfffff07d29f392 +0300000000000000 +3c4c000100000580 +7c0802a638428aa4 +f821ffb1480006e9 +7c7f1b78eb630000 +7cbd2b787c9c2378 +7fa3eb783bc00000 +600000004bfffe79 +409d00147fa3f040 +7d3b5050e95f0000 +419c00107fa9e040 +3860000138210050 +7d3df0ae480006f0 +992a00003bde0001 +39290001e93f0000 +4bffffb8f93f0000 0100000000000000 -3c4c000100000780 -7c0802a6384288e4 -f821fed148000539 -f86100607c741b79 -4182006838600000 -419e00602fa40000 -3e42ffff39210040 -3b4100203ac4ffff -60000000f9210070 -392280383ae00000 -3ba100603a527ff0 -89250000f9210078 -2fa90000ebc10060 -7ff4f050419e0010 -419c00207fbfb040 -993e000039200000 -7e941850e8610060 -382101307e8307b4 -2b89002548000508 -409e048839450001 -8925000038e00000 -f8a10068e9010070 -7d2741ae7cea07b4 -8d25000139070001 -2b8900647d0807b4 -2b890069419e0058 -2b890075419e0050 -2b890078419e0048 -2b890058419e0040 -2b890070419e0038 -2b890063419e0030 -2b890073419e0028 -2b890025419e0020 -2b89004f419e0018 -2b89006f419e0010 -409eff8838e70001 -2b890025394a0002 -7d1a42147d4a07b4 -992800207d5a5214 -409e00209aea0020 -f9210060393e0001 -993e000039200025 -38a90002e9210068 -892100414bffff04 -3a2600087fffb050 -3a600030eb660000 -3929ffd23b010042 -4082039c712900fd -3b2000043aa00000 -3a0000013b800000 -7ddb00d039e0002d -2b89006c48000108 -88f8000138d80001 -419d0118419e033c -419e02402b890063 -2b89004f419d0038 -2b890058419e01e8 -3949ffd0419e0188 -2b8a0009554a063e -395c0001419d00c4 -993c00207f81e214 -480000b0795c0020 -419e03042b890068 -419e000c2b890069 -409effc82b890064 -7d41e2142b890075 -7f6adb789aea0020 -57291838419e0034 -7e0948363929ffff -418200207f694839 -e921006099e80000 -f921006039290001 -7d52482a7b291f24 -e88100607dca5038 -38e0000a7d465378 -7f45d378f9410080 -7e689b7839200000 -7c9e20507fa3eb78 -4bfffc9d7c84f850 -e9410080e8810060 -38c0000a7ea7ab78 -7d4553787c9e2050 -7fa3eb787c84f850 -3b1800014bfffaed -e901006089380000 +3c4c000100000580 +7c0802a638428a24 +f821ffa148000661 +7c9b23787c7d1b78 +388000007ca32b78 +7cde337838a0000a +7cfc3b78eb5d0000 +7d3f4b787d194378 +600000004bfffcb5 +7c6307b439400000 +409e006c2fbe0000 +409e00082faa0000 +7d3f521439400001 +7d2a07b47f834800 +7c6a1850409d0044 +786900202f830000 +419c001039290001 +7f8350003d408000 +39200001409e0008 +3929ffff2c290001 +e8fd000041820014 +7faad8407d5a3850 +38210060419c0030 +4800060438600000 +409e00142b9c0010 +394a00017bdee102 +4bffff7c7d4a07b4 +4bfffff07fdee392 +e95d00009b270000 +f95d0000394a0001 +000000004bffffa8 +0000078001000000 +384289283c4c0001 +480005397c0802a6 +7c741b79f821fed1 +38600000f8610060 +2fa4000041820068 +39210040419e0060 +3ac4ffff3e42ffff +f92100703b410020 +3ae000003d22ffff +3a527fb039297ff8 +f92100783ba10060 +ebc1006089250000 419e00102fa90000 -7fbf50407d5e4050 -7e268b78419dfee4 -2b8900734bfffe90 -419d006c419e016c -419e00d42b89006f -409efef02b890070 -38e000107d21e214 -7c8af8507f66db78 -390000209ae90020 -7f45d37839200002 -4bfffc0d7fa3eb78 -e8a10078e8810060 -7c9e20507fa3eb78 -4bfffb757c84f850 -7ea7ab78e8810060 -7f65db7838c00010 -4bffff5c7c9e2050 -419e00182b890078 -419e01cc2b89007a -4bfffeb82b890075 -7d21e2143aa00001 -7c8af85038e00010 -9ae900207e689b78 -7f45d3787b291f24 -7d72482a7fa3eb78 -7f6b583839200000 -f96100807d665b78 -e88100604bfffb89 +7fbfb0407ff4f050 +39200000419c0020 +e8610060993e0000 +7e8307b47e941850 +4800050838210130 +394500012b890025 +38e00000409e0488 +e901007089250000 +7cea07b4f8a10068 +390700017d2741ae +7d0807b48d250001 +419e00582b890064 +419e00502b890069 +419e00482b890075 +419e00402b890078 +419e00382b890058 +419e00302b890070 +419e00282b890063 +419e00202b890073 +419e00182b890025 +419e00102b89004f +38e700012b89006f +394a0002409eff88 +7d4a07b42b890025 +7d5a52147d1a4214 +9aea002099280020 +393e0001409e0020 +39200025f9210060 +e9210068993e0000 +4bffff0438a90002 +7fffb05089210041 +eb6600003a260008 +3b0100423a600030 +712900fd3929ffd2 +3aa000004082039c +3b8000003b200004 +39e0002d3a000001 +480001087ddb00d0 +38d800012b89006c +419e033c88f80001 +2b890063419d0118 +419d0038419e0240 +419e01e82b89004f +419e01882b890058 +554a063e3949ffd0 +419d00c42b8a0009 +7f81e214395c0001 +795c0020993c0020 +2b890068480000b0 +2b890069419e0304 +2b890064419e000c +2b890075409effc8 +9aea00207d41e214 +419e00347f6adb78 +3929ffff57291838 +7f6948397e094836 +99e8000041820020 +39290001e9210060 +7b291f24f9210060 +7dca50387d52482a +7d465378e8810060 +f941008038e0000a +392000007f45d378 +7fa3eb787e689b78 +7c84f8507c9e2050 +e88100604bfffc9d +7ea7ab78e9410080 +7c9e205038c0000a +7c84f8507d455378 +4bfffaed7fa3eb78 +893800003b180001 +2fa90000e9010060 +7d5e4050419e0010 +419dfee47fbf5040 +4bfffe907e268b78 +419e016c2b890073 +2b89006f419d006c +2b890070419e00d4 +7d21e214409efef0 +7f66db7838e00010 +9ae900207c8af850 +3920000239000020 +7fa3eb787f45d378 +e88100604bfffc0d +7fa3eb78e8a10078 +7c84f8507c9e2050 +e88100604bfffb75 38c000107ea7ab78 -e96100807c9e2050 -4bfffeec7d655b78 -38e000087d21e214 +7c9e20507f65db78 +2b8900784bffff5c +2b89007a419e0018 +2b890075419e01cc +3aa000014bfffeb8 +38e000107d21e214 7e689b787c8af850 7b291f249ae90020 7fa3eb787f45d378 392000007d72482a 7d665b787f6b5838 -4bfffb35f9610080 +4bfffb89f9610080 7ea7ab78e8810060 -7c9e205038c00008 -7d21e2144bffffac -38e0000a39000020 -9ae9002038c00001 -392000007f45d378 -7fa3eb787c8af850 -e92100604bfffaf9 -e92100609b690000 -f921006039290001 -7d21e2144bfffe6c -f901009038a0000a -38800000f9410088 -9ae900207f43d378 -600000004bfff7a9 -7f63db78f8610080 -600000004bfff8cd -7fa91840e9210080 -7c634850409d0040 -e9010090e9410088 -392300012fa30000 -409e00087d4af850 -2c29000139200001 -3929ffffe8c10060 -7ce8305041820010 -419d00207faa3840 -7f65db78e8810060 -7c9e20507fa3eb78 -4bfff9cd7c84f850 -38e000204bfffdd4 -e8e1006098e60000 -f8e1006038e70001 -2b87006c4bffffb4 -409efdb03b200008 -4bfffda87cd83378 -3b2000022b870068 -7cd83378409efd9c -4bfffd903b200001 -4bfffd883b200008 -3b0100413a600020 -993e00004bfffc60 -e92100607d455378 -f921006039290001 -000000004bfffb24 -0000128001000000 -f9e1ff78f9c1ff70 -fa21ff88fa01ff80 -fa61ff98fa41ff90 -faa1ffa8fa81ffa0 -fae1ffb8fac1ffb0 -fb21ffc8fb01ffc0 -fb61ffd8fb41ffd0 -fba1ffe8fb81ffe0 -fbe1fff8fbc1fff0 -4e800020f8010010 -e9e1ff78e9c1ff70 -ea21ff88ea01ff80 -ea61ff98ea41ff90 -eaa1ffa8ea81ffa0 -eae1ffb8eac1ffb0 -eb21ffc8eb01ffc0 -eb61ffd8eb41ffd0 -e8010010eb81ffe0 -7c0803a6eba1ffe8 -ebe1fff8ebc1fff0 -ebc1fff04e800020 -ebe1fff8e8010010 -4e8000207c0803a6 +7c9e205038c00010 +7d655b78e9610080 +7d21e2144bfffeec +7c8af85038e00008 +9ae900207e689b78 +7f45d3787b291f24 +7d72482a7fa3eb78 +7f6b583839200000 +f96100807d665b78 +e88100604bfffb35 +38c000087ea7ab78 +4bffffac7c9e2050 +390000207d21e214 +38c0000138e0000a +7f45d3789ae90020 +7c8af85039200000 +4bfffaf97fa3eb78 +9b690000e9210060 +39290001e9210060 +4bfffe6cf9210060 +38a0000a7d21e214 +f9410088f9010090 +7f43d37838800000 +4bfff7a99ae90020 +f861008060000000 +4bfff8cd7f63db78 +e921008060000000 +409d00407fa91840 +e94100887c634850 +2fa30000e9010090 +7d4af85039230001 +39200001409e0008 +e8c100602c290001 +418200103929ffff +7faa38407ce83050 +e8810060419d0020 +7fa3eb787f65db78 +7c84f8507c9e2050 +4bfffdd44bfff9cd +98e6000038e00020 +38e70001e8e10060 +4bffffb4f8e10060 +3b2000082b87006c +7cd83378409efdb0 +2b8700684bfffda8 +409efd9c3b200002 +3b2000017cd83378 +3b2000084bfffd90 +3a6000204bfffd88 +4bfffc603b010041 +7d455378993e0000 +39290001e9210060 +4bfffb24f9210060 +0100000000000000 +f9c1ff7000001280 +fa01ff80f9e1ff78 +fa41ff90fa21ff88 +fa81ffa0fa61ff98 +fac1ffb0faa1ffa8 +fb01ffc0fae1ffb8 +fb41ffd0fb21ffc8 +fb81ffe0fb61ffd8 +fbc1fff0fba1ffe8 +f8010010fbe1fff8 +e9c1ff704e800020 +ea01ff80e9e1ff78 +ea41ff90ea21ff88 +ea81ffa0ea61ff98 +eac1ffb0eaa1ffa8 +eb01ffc0eae1ffb8 +eb41ffd0eb21ffc8 +eb81ffe0eb61ffd8 +eba1ffe8e8010010 +ebc1fff07c0803a6 +4e800020ebe1fff8 +e8010010ebc1fff0 +7c0803a6ebe1fff8 +000000004e800020 6d6f636c65570a0a 63694d206f742065 2120747461776f72 @@ -1410,10 +1402,10 @@ ebe1fff8e8010010 000000000000002d 30252d2b64323025 0000000000006432 -0000000000000850 -00000000000008b8 -0000000000000920 -0000000000000988 +0000000000000830 +0000000000000860 +0000000000000890 +00000000000008c0 6f6e204d41524453 207265646e752077 6572617764726168 diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v index dd74efd..854f4c6 100644 --- a/litedram/generated/nexys-video/litedram_core.v +++ b/litedram/generated/nexys-video/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 10:54:05 +// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 11:57:13 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, @@ -24,8 +24,8 @@ module litedram_core( output wire init_error, input wire [13:0] csr_port0_adr, input wire csr_port0_we, - input wire [7:0] csr_port0_dat_w, - output wire [7:0] csr_port0_dat_r, + input wire [31:0] csr_port0_dat_w, + output wire [31:0] csr_port0_dat_r, output wire user_clk, output wire user_rst, input wire user_port_native_0_cmd_valid, @@ -1485,8 +1485,8 @@ reg init_error_storage = 1'd0; reg init_error_re = 1'd0; wire [13:0] csr_port_adr; wire csr_port_we; -wire [7:0] csr_port_dat_w; -wire [7:0] csr_port_dat_r; +wire [31:0] csr_port_dat_w; +wire [31:0] csr_port_dat_r; wire user_port_cmd_valid; wire user_port_cmd_ready; wire user_port_cmd_payload_we; @@ -1566,8 +1566,8 @@ reg new_master_rdata_valid7 = 1'd0; reg new_master_rdata_valid8 = 1'd0; wire [13:0] interface0_bank_bus_adr; wire interface0_bank_bus_we; -wire [7:0] interface0_bank_bus_dat_w; -reg [7:0] interface0_bank_bus_dat_r = 8'd0; +wire [31:0] interface0_bank_bus_dat_w; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; wire csrbank0_init_done0_re; wire csrbank0_init_done0_r; wire csrbank0_init_done0_we; @@ -1579,8 +1579,8 @@ wire csrbank0_init_error0_w; reg csrbank0_sel = 1'd0; wire [13:0] interface1_bank_bus_adr; wire interface1_bank_bus_we; -wire [7:0] interface1_bank_bus_dat_w; -reg [7:0] interface1_bank_bus_dat_r = 8'd0; +wire [31:0] interface1_bank_bus_dat_w; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; wire csrbank1_half_sys8x_taps0_re; wire [4:0] csrbank1_half_sys8x_taps0_r; wire csrbank1_half_sys8x_taps0_we; @@ -1596,8 +1596,8 @@ wire [1:0] csrbank1_dly_sel0_w; reg csrbank1_sel = 1'd0; wire [13:0] interface2_bank_bus_adr; wire interface2_bank_bus_we; -wire [7:0] interface2_bank_bus_dat_w; -reg [7:0] interface2_bank_bus_dat_r = 8'd0; +wire [31:0] interface2_bank_bus_dat_w; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; wire csrbank2_dfii_control0_re; wire [3:0] csrbank2_dfii_control0_r; wire csrbank2_dfii_control0_we; @@ -1606,199 +1606,87 @@ wire csrbank2_dfii_pi0_command0_re; wire [5:0] csrbank2_dfii_pi0_command0_r; wire csrbank2_dfii_pi0_command0_we; wire [5:0] csrbank2_dfii_pi0_command0_w; -wire csrbank2_dfii_pi0_address1_re; -wire [6:0] csrbank2_dfii_pi0_address1_r; -wire csrbank2_dfii_pi0_address1_we; -wire [6:0] csrbank2_dfii_pi0_address1_w; wire csrbank2_dfii_pi0_address0_re; -wire [7:0] csrbank2_dfii_pi0_address0_r; +wire [14:0] csrbank2_dfii_pi0_address0_r; wire csrbank2_dfii_pi0_address0_we; -wire [7:0] csrbank2_dfii_pi0_address0_w; +wire [14:0] csrbank2_dfii_pi0_address0_w; wire csrbank2_dfii_pi0_baddress0_re; wire [2:0] csrbank2_dfii_pi0_baddress0_r; wire csrbank2_dfii_pi0_baddress0_we; wire [2:0] csrbank2_dfii_pi0_baddress0_w; -wire csrbank2_dfii_pi0_wrdata3_re; -wire [7:0] csrbank2_dfii_pi0_wrdata3_r; -wire csrbank2_dfii_pi0_wrdata3_we; -wire [7:0] csrbank2_dfii_pi0_wrdata3_w; -wire csrbank2_dfii_pi0_wrdata2_re; -wire [7:0] csrbank2_dfii_pi0_wrdata2_r; -wire csrbank2_dfii_pi0_wrdata2_we; -wire [7:0] csrbank2_dfii_pi0_wrdata2_w; -wire csrbank2_dfii_pi0_wrdata1_re; -wire [7:0] csrbank2_dfii_pi0_wrdata1_r; -wire csrbank2_dfii_pi0_wrdata1_we; -wire [7:0] csrbank2_dfii_pi0_wrdata1_w; wire csrbank2_dfii_pi0_wrdata0_re; -wire [7:0] csrbank2_dfii_pi0_wrdata0_r; +wire [31:0] csrbank2_dfii_pi0_wrdata0_r; wire csrbank2_dfii_pi0_wrdata0_we; -wire [7:0] csrbank2_dfii_pi0_wrdata0_w; -wire csrbank2_dfii_pi0_rddata3_re; -wire [7:0] csrbank2_dfii_pi0_rddata3_r; -wire csrbank2_dfii_pi0_rddata3_we; -wire [7:0] csrbank2_dfii_pi0_rddata3_w; -wire csrbank2_dfii_pi0_rddata2_re; -wire [7:0] csrbank2_dfii_pi0_rddata2_r; -wire csrbank2_dfii_pi0_rddata2_we; -wire [7:0] csrbank2_dfii_pi0_rddata2_w; -wire csrbank2_dfii_pi0_rddata1_re; -wire [7:0] csrbank2_dfii_pi0_rddata1_r; -wire csrbank2_dfii_pi0_rddata1_we; -wire [7:0] csrbank2_dfii_pi0_rddata1_w; -wire csrbank2_dfii_pi0_rddata0_re; -wire [7:0] csrbank2_dfii_pi0_rddata0_r; -wire csrbank2_dfii_pi0_rddata0_we; -wire [7:0] csrbank2_dfii_pi0_rddata0_w; +wire [31:0] csrbank2_dfii_pi0_wrdata0_w; +wire csrbank2_dfii_pi0_rddata_re; +wire [31:0] csrbank2_dfii_pi0_rddata_r; +wire csrbank2_dfii_pi0_rddata_we; +wire [31:0] csrbank2_dfii_pi0_rddata_w; wire csrbank2_dfii_pi1_command0_re; wire [5:0] csrbank2_dfii_pi1_command0_r; wire csrbank2_dfii_pi1_command0_we; wire [5:0] csrbank2_dfii_pi1_command0_w; -wire csrbank2_dfii_pi1_address1_re; -wire [6:0] csrbank2_dfii_pi1_address1_r; -wire csrbank2_dfii_pi1_address1_we; -wire [6:0] csrbank2_dfii_pi1_address1_w; wire csrbank2_dfii_pi1_address0_re; -wire [7:0] csrbank2_dfii_pi1_address0_r; +wire [14:0] csrbank2_dfii_pi1_address0_r; wire csrbank2_dfii_pi1_address0_we; -wire [7:0] csrbank2_dfii_pi1_address0_w; +wire [14:0] csrbank2_dfii_pi1_address0_w; wire csrbank2_dfii_pi1_baddress0_re; wire [2:0] csrbank2_dfii_pi1_baddress0_r; wire csrbank2_dfii_pi1_baddress0_we; wire [2:0] csrbank2_dfii_pi1_baddress0_w; -wire csrbank2_dfii_pi1_wrdata3_re; -wire [7:0] csrbank2_dfii_pi1_wrdata3_r; -wire csrbank2_dfii_pi1_wrdata3_we; -wire [7:0] csrbank2_dfii_pi1_wrdata3_w; -wire csrbank2_dfii_pi1_wrdata2_re; -wire [7:0] csrbank2_dfii_pi1_wrdata2_r; -wire csrbank2_dfii_pi1_wrdata2_we; -wire [7:0] csrbank2_dfii_pi1_wrdata2_w; -wire csrbank2_dfii_pi1_wrdata1_re; -wire [7:0] csrbank2_dfii_pi1_wrdata1_r; -wire csrbank2_dfii_pi1_wrdata1_we; -wire [7:0] csrbank2_dfii_pi1_wrdata1_w; wire csrbank2_dfii_pi1_wrdata0_re; -wire [7:0] csrbank2_dfii_pi1_wrdata0_r; +wire [31:0] csrbank2_dfii_pi1_wrdata0_r; wire csrbank2_dfii_pi1_wrdata0_we; -wire [7:0] csrbank2_dfii_pi1_wrdata0_w; -wire csrbank2_dfii_pi1_rddata3_re; -wire [7:0] csrbank2_dfii_pi1_rddata3_r; -wire csrbank2_dfii_pi1_rddata3_we; -wire [7:0] csrbank2_dfii_pi1_rddata3_w; -wire csrbank2_dfii_pi1_rddata2_re; -wire [7:0] csrbank2_dfii_pi1_rddata2_r; -wire csrbank2_dfii_pi1_rddata2_we; -wire [7:0] csrbank2_dfii_pi1_rddata2_w; -wire csrbank2_dfii_pi1_rddata1_re; -wire [7:0] csrbank2_dfii_pi1_rddata1_r; -wire csrbank2_dfii_pi1_rddata1_we; -wire [7:0] csrbank2_dfii_pi1_rddata1_w; -wire csrbank2_dfii_pi1_rddata0_re; -wire [7:0] csrbank2_dfii_pi1_rddata0_r; -wire csrbank2_dfii_pi1_rddata0_we; -wire [7:0] csrbank2_dfii_pi1_rddata0_w; +wire [31:0] csrbank2_dfii_pi1_wrdata0_w; +wire csrbank2_dfii_pi1_rddata_re; +wire [31:0] csrbank2_dfii_pi1_rddata_r; +wire csrbank2_dfii_pi1_rddata_we; +wire [31:0] csrbank2_dfii_pi1_rddata_w; wire csrbank2_dfii_pi2_command0_re; wire [5:0] csrbank2_dfii_pi2_command0_r; wire csrbank2_dfii_pi2_command0_we; wire [5:0] csrbank2_dfii_pi2_command0_w; -wire csrbank2_dfii_pi2_address1_re; -wire [6:0] csrbank2_dfii_pi2_address1_r; -wire csrbank2_dfii_pi2_address1_we; -wire [6:0] csrbank2_dfii_pi2_address1_w; wire csrbank2_dfii_pi2_address0_re; -wire [7:0] csrbank2_dfii_pi2_address0_r; +wire [14:0] csrbank2_dfii_pi2_address0_r; wire csrbank2_dfii_pi2_address0_we; -wire [7:0] csrbank2_dfii_pi2_address0_w; +wire [14:0] csrbank2_dfii_pi2_address0_w; wire csrbank2_dfii_pi2_baddress0_re; wire [2:0] csrbank2_dfii_pi2_baddress0_r; wire csrbank2_dfii_pi2_baddress0_we; wire [2:0] csrbank2_dfii_pi2_baddress0_w; -wire csrbank2_dfii_pi2_wrdata3_re; -wire [7:0] csrbank2_dfii_pi2_wrdata3_r; -wire csrbank2_dfii_pi2_wrdata3_we; -wire [7:0] csrbank2_dfii_pi2_wrdata3_w; -wire csrbank2_dfii_pi2_wrdata2_re; -wire [7:0] csrbank2_dfii_pi2_wrdata2_r; -wire csrbank2_dfii_pi2_wrdata2_we; -wire [7:0] csrbank2_dfii_pi2_wrdata2_w; -wire csrbank2_dfii_pi2_wrdata1_re; -wire [7:0] csrbank2_dfii_pi2_wrdata1_r; -wire csrbank2_dfii_pi2_wrdata1_we; -wire [7:0] csrbank2_dfii_pi2_wrdata1_w; wire csrbank2_dfii_pi2_wrdata0_re; -wire [7:0] csrbank2_dfii_pi2_wrdata0_r; +wire [31:0] csrbank2_dfii_pi2_wrdata0_r; wire csrbank2_dfii_pi2_wrdata0_we; -wire [7:0] csrbank2_dfii_pi2_wrdata0_w; -wire csrbank2_dfii_pi2_rddata3_re; -wire [7:0] csrbank2_dfii_pi2_rddata3_r; -wire csrbank2_dfii_pi2_rddata3_we; -wire [7:0] csrbank2_dfii_pi2_rddata3_w; -wire csrbank2_dfii_pi2_rddata2_re; -wire [7:0] csrbank2_dfii_pi2_rddata2_r; -wire csrbank2_dfii_pi2_rddata2_we; -wire [7:0] csrbank2_dfii_pi2_rddata2_w; -wire csrbank2_dfii_pi2_rddata1_re; -wire [7:0] csrbank2_dfii_pi2_rddata1_r; -wire csrbank2_dfii_pi2_rddata1_we; -wire [7:0] csrbank2_dfii_pi2_rddata1_w; -wire csrbank2_dfii_pi2_rddata0_re; -wire [7:0] csrbank2_dfii_pi2_rddata0_r; -wire csrbank2_dfii_pi2_rddata0_we; -wire [7:0] csrbank2_dfii_pi2_rddata0_w; +wire [31:0] csrbank2_dfii_pi2_wrdata0_w; +wire csrbank2_dfii_pi2_rddata_re; +wire [31:0] csrbank2_dfii_pi2_rddata_r; +wire csrbank2_dfii_pi2_rddata_we; +wire [31:0] csrbank2_dfii_pi2_rddata_w; wire csrbank2_dfii_pi3_command0_re; wire [5:0] csrbank2_dfii_pi3_command0_r; wire csrbank2_dfii_pi3_command0_we; wire [5:0] csrbank2_dfii_pi3_command0_w; -wire csrbank2_dfii_pi3_address1_re; -wire [6:0] csrbank2_dfii_pi3_address1_r; -wire csrbank2_dfii_pi3_address1_we; -wire [6:0] csrbank2_dfii_pi3_address1_w; wire csrbank2_dfii_pi3_address0_re; -wire [7:0] csrbank2_dfii_pi3_address0_r; +wire [14:0] csrbank2_dfii_pi3_address0_r; wire csrbank2_dfii_pi3_address0_we; -wire [7:0] csrbank2_dfii_pi3_address0_w; +wire [14:0] csrbank2_dfii_pi3_address0_w; wire csrbank2_dfii_pi3_baddress0_re; wire [2:0] csrbank2_dfii_pi3_baddress0_r; wire csrbank2_dfii_pi3_baddress0_we; wire [2:0] csrbank2_dfii_pi3_baddress0_w; -wire csrbank2_dfii_pi3_wrdata3_re; -wire [7:0] csrbank2_dfii_pi3_wrdata3_r; -wire csrbank2_dfii_pi3_wrdata3_we; -wire [7:0] csrbank2_dfii_pi3_wrdata3_w; -wire csrbank2_dfii_pi3_wrdata2_re; -wire [7:0] csrbank2_dfii_pi3_wrdata2_r; -wire csrbank2_dfii_pi3_wrdata2_we; -wire [7:0] csrbank2_dfii_pi3_wrdata2_w; -wire csrbank2_dfii_pi3_wrdata1_re; -wire [7:0] csrbank2_dfii_pi3_wrdata1_r; -wire csrbank2_dfii_pi3_wrdata1_we; -wire [7:0] csrbank2_dfii_pi3_wrdata1_w; wire csrbank2_dfii_pi3_wrdata0_re; -wire [7:0] csrbank2_dfii_pi3_wrdata0_r; +wire [31:0] csrbank2_dfii_pi3_wrdata0_r; wire csrbank2_dfii_pi3_wrdata0_we; -wire [7:0] csrbank2_dfii_pi3_wrdata0_w; -wire csrbank2_dfii_pi3_rddata3_re; -wire [7:0] csrbank2_dfii_pi3_rddata3_r; -wire csrbank2_dfii_pi3_rddata3_we; -wire [7:0] csrbank2_dfii_pi3_rddata3_w; -wire csrbank2_dfii_pi3_rddata2_re; -wire [7:0] csrbank2_dfii_pi3_rddata2_r; -wire csrbank2_dfii_pi3_rddata2_we; -wire [7:0] csrbank2_dfii_pi3_rddata2_w; -wire csrbank2_dfii_pi3_rddata1_re; -wire [7:0] csrbank2_dfii_pi3_rddata1_r; -wire csrbank2_dfii_pi3_rddata1_we; -wire [7:0] csrbank2_dfii_pi3_rddata1_w; -wire csrbank2_dfii_pi3_rddata0_re; -wire [7:0] csrbank2_dfii_pi3_rddata0_r; -wire csrbank2_dfii_pi3_rddata0_we; -wire [7:0] csrbank2_dfii_pi3_rddata0_w; +wire [31:0] csrbank2_dfii_pi3_wrdata0_w; +wire csrbank2_dfii_pi3_rddata_re; +wire [31:0] csrbank2_dfii_pi3_rddata_r; +wire csrbank2_dfii_pi3_rddata_we; +wire [31:0] csrbank2_dfii_pi3_rddata_w; reg csrbank2_sel = 1'd0; wire [13:0] adr; wire we; -wire [7:0] dat_w; -wire [7:0] dat_r; +wire [31:0] dat_w; +wire [31:0] dat_r; reg rhs_array_muxed0 = 1'd0; reg [14:0] rhs_array_muxed1 = 15'd0; reg [2:0] rhs_array_muxed2 = 3'd0; @@ -2848,11 +2736,11 @@ assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; reg dummy_d_22; // synthesis translate_on always @(*) begin - litedramcore_master_p2_ras_n <= 1'd1; + litedramcore_master_p1_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; + litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; end else begin - litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n; + litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n; end // synthesis translate_off dummy_d_22 = dummy_s; @@ -2863,9 +2751,9 @@ end reg dummy_d_23; // synthesis translate_on always @(*) begin - litedramcore_slave_p2_rddata <= 32'd0; + litedramcore_slave_p1_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; + litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; end else begin end // synthesis translate_off @@ -2877,11 +2765,11 @@ end reg dummy_d_24; // synthesis translate_on always @(*) begin - litedramcore_master_p2_we_n <= 1'd1; + litedramcore_master_p1_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; + litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; end else begin - litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; + litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n; end // synthesis translate_off dummy_d_24 = dummy_s; @@ -2892,9 +2780,9 @@ end reg dummy_d_25; // synthesis translate_on always @(*) begin - litedramcore_slave_p2_rddata_valid <= 1'd0; + litedramcore_slave_p1_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end else begin end // synthesis translate_off @@ -2906,11 +2794,11 @@ end reg dummy_d_26; // synthesis translate_on always @(*) begin - litedramcore_master_p2_cke <= 1'd0; + litedramcore_master_p1_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; + litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; end else begin - litedramcore_master_p2_cke <= litedramcore_inti_p2_cke; + litedramcore_master_p1_cke <= litedramcore_inti_p1_cke; end // synthesis translate_off dummy_d_26 = dummy_s; @@ -2921,11 +2809,11 @@ end reg dummy_d_27; // synthesis translate_on always @(*) begin - litedramcore_master_p2_odt <= 1'd0; + litedramcore_master_p1_odt <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; + litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; end else begin - litedramcore_master_p2_odt <= litedramcore_inti_p2_odt; + litedramcore_master_p1_odt <= litedramcore_inti_p1_odt; end // synthesis translate_off dummy_d_27 = dummy_s; @@ -2936,11 +2824,11 @@ end reg dummy_d_28; // synthesis translate_on always @(*) begin - litedramcore_master_p2_reset_n <= 1'd0; + litedramcore_master_p1_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; + litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; end else begin - litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n; + litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; end // synthesis translate_off dummy_d_28 = dummy_s; @@ -2951,11 +2839,11 @@ end reg dummy_d_29; // synthesis translate_on always @(*) begin - litedramcore_master_p2_act_n <= 1'd1; + litedramcore_master_p1_act_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; + litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; end else begin - litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n; + litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n; end // synthesis translate_off dummy_d_29 = dummy_s; @@ -2966,11 +2854,11 @@ end reg dummy_d_30; // synthesis translate_on always @(*) begin - litedramcore_master_p2_wrdata <= 32'd0; + litedramcore_master_p1_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; + litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; end else begin - litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata; + litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata; end // synthesis translate_off dummy_d_30 = dummy_s; @@ -2981,10 +2869,10 @@ end reg dummy_d_31; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_rddata <= 32'd0; + litedramcore_inti_p2_rddata <= 32'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata; + litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; end // synthesis translate_off dummy_d_31 = dummy_s; @@ -2995,11 +2883,11 @@ end reg dummy_d_32; // synthesis translate_on always @(*) begin - litedramcore_master_p2_wrdata_en <= 1'd0; + litedramcore_master_p1_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; + litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en; + litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; end // synthesis translate_off dummy_d_32 = dummy_s; @@ -3010,10 +2898,10 @@ end reg dummy_d_33; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_rddata_valid <= 1'd0; + litedramcore_inti_p2_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end // synthesis translate_off dummy_d_33 = dummy_s; @@ -3024,11 +2912,11 @@ end reg dummy_d_34; // synthesis translate_on always @(*) begin - litedramcore_master_p2_wrdata_mask <= 4'd0; + litedramcore_master_p1_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; + litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask; + litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; end // synthesis translate_off dummy_d_34 = dummy_s; @@ -3039,11 +2927,11 @@ end reg dummy_d_35; // synthesis translate_on always @(*) begin - litedramcore_master_p2_rddata_en <= 1'd0; + litedramcore_master_p1_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; + litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; end else begin - litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en; + litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; end // synthesis translate_off dummy_d_35 = dummy_s; @@ -3054,11 +2942,11 @@ end reg dummy_d_36; // synthesis translate_on always @(*) begin - litedramcore_master_p3_address <= 15'd0; + litedramcore_master_p2_address <= 15'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_address <= litedramcore_slave_p3_address; + litedramcore_master_p2_address <= litedramcore_slave_p2_address; end else begin - litedramcore_master_p3_address <= litedramcore_inti_p3_address; + litedramcore_master_p2_address <= litedramcore_inti_p2_address; end // synthesis translate_off dummy_d_36 = dummy_s; @@ -3069,11 +2957,11 @@ end reg dummy_d_37; // synthesis translate_on always @(*) begin - litedramcore_master_p3_bank <= 3'd0; + litedramcore_master_p2_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; + litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; end else begin - litedramcore_master_p3_bank <= litedramcore_inti_p3_bank; + litedramcore_master_p2_bank <= litedramcore_inti_p2_bank; end // synthesis translate_off dummy_d_37 = dummy_s; @@ -3084,11 +2972,11 @@ end reg dummy_d_38; // synthesis translate_on always @(*) begin - litedramcore_master_p3_cas_n <= 1'd1; + litedramcore_master_p2_cas_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; + litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; end else begin - litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n; + litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n; end // synthesis translate_off dummy_d_38 = dummy_s; @@ -3099,11 +2987,11 @@ end reg dummy_d_39; // synthesis translate_on always @(*) begin - litedramcore_master_p3_cs_n <= 1'd1; + litedramcore_master_p2_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; + litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; end else begin - litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n; + litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n; end // synthesis translate_off dummy_d_39 = dummy_s; @@ -3114,11 +3002,11 @@ end reg dummy_d_40; // synthesis translate_on always @(*) begin - litedramcore_master_p3_ras_n <= 1'd1; + litedramcore_master_p2_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; + litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; end else begin - litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n; + litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n; end // synthesis translate_off dummy_d_40 = dummy_s; @@ -3129,9 +3017,9 @@ end reg dummy_d_41; // synthesis translate_on always @(*) begin - litedramcore_slave_p3_rddata <= 32'd0; + litedramcore_slave_p2_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; + litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; end else begin end // synthesis translate_off @@ -3143,11 +3031,11 @@ end reg dummy_d_42; // synthesis translate_on always @(*) begin - litedramcore_master_p3_we_n <= 1'd1; + litedramcore_master_p2_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; + litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; end else begin - litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n; + litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; end // synthesis translate_off dummy_d_42 = dummy_s; @@ -3158,9 +3046,9 @@ end reg dummy_d_43; // synthesis translate_on always @(*) begin - litedramcore_slave_p3_rddata_valid <= 1'd0; + litedramcore_slave_p2_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end else begin end // synthesis translate_off @@ -3172,11 +3060,11 @@ end reg dummy_d_44; // synthesis translate_on always @(*) begin - litedramcore_master_p3_cke <= 1'd0; + litedramcore_master_p2_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; + litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; end else begin - litedramcore_master_p3_cke <= litedramcore_inti_p3_cke; + litedramcore_master_p2_cke <= litedramcore_inti_p2_cke; end // synthesis translate_off dummy_d_44 = dummy_s; @@ -3187,11 +3075,11 @@ end reg dummy_d_45; // synthesis translate_on always @(*) begin - litedramcore_master_p3_odt <= 1'd0; + litedramcore_master_p2_odt <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; + litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; end else begin - litedramcore_master_p3_odt <= litedramcore_inti_p3_odt; + litedramcore_master_p2_odt <= litedramcore_inti_p2_odt; end // synthesis translate_off dummy_d_45 = dummy_s; @@ -3202,11 +3090,11 @@ end reg dummy_d_46; // synthesis translate_on always @(*) begin - litedramcore_master_p3_reset_n <= 1'd0; + litedramcore_master_p2_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; + litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; end else begin - litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n; + litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n; end // synthesis translate_off dummy_d_46 = dummy_s; @@ -3217,11 +3105,11 @@ end reg dummy_d_47; // synthesis translate_on always @(*) begin - litedramcore_master_p3_act_n <= 1'd1; + litedramcore_master_p2_act_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; + litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; end else begin - litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n; + litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n; end // synthesis translate_off dummy_d_47 = dummy_s; @@ -3232,11 +3120,11 @@ end reg dummy_d_48; // synthesis translate_on always @(*) begin - litedramcore_master_p3_wrdata <= 32'd0; + litedramcore_master_p2_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; + litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; end else begin - litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata; + litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata; end // synthesis translate_off dummy_d_48 = dummy_s; @@ -3247,10 +3135,10 @@ end reg dummy_d_49; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_rddata <= 32'd0; + litedramcore_inti_p3_rddata <= 32'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata; + litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata; end // synthesis translate_off dummy_d_49 = dummy_s; @@ -3261,11 +3149,11 @@ end reg dummy_d_50; // synthesis translate_on always @(*) begin - litedramcore_master_p3_wrdata_en <= 1'd0; + litedramcore_master_p2_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; + litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en; + litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en; end // synthesis translate_off dummy_d_50 = dummy_s; @@ -3276,10 +3164,10 @@ end reg dummy_d_51; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_rddata_valid <= 1'd0; + litedramcore_inti_p3_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end // synthesis translate_off dummy_d_51 = dummy_s; @@ -3290,11 +3178,11 @@ end reg dummy_d_52; // synthesis translate_on always @(*) begin - litedramcore_master_p3_wrdata_mask <= 4'd0; + litedramcore_master_p2_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; + litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask; + litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask; end // synthesis translate_off dummy_d_52 = dummy_s; @@ -3305,11 +3193,11 @@ end reg dummy_d_53; // synthesis translate_on always @(*) begin - litedramcore_master_p3_rddata_en <= 1'd0; + litedramcore_master_p2_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; + litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; end else begin - litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en; + litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en; end // synthesis translate_off dummy_d_53 = dummy_s; @@ -3320,11 +3208,11 @@ end reg dummy_d_54; // synthesis translate_on always @(*) begin - litedramcore_master_p0_address <= 15'd0; + litedramcore_master_p3_address <= 15'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_address <= litedramcore_slave_p0_address; + litedramcore_master_p3_address <= litedramcore_slave_p3_address; end else begin - litedramcore_master_p0_address <= litedramcore_inti_p0_address; + litedramcore_master_p3_address <= litedramcore_inti_p3_address; end // synthesis translate_off dummy_d_54 = dummy_s; @@ -3335,11 +3223,11 @@ end reg dummy_d_55; // synthesis translate_on always @(*) begin - litedramcore_master_p0_bank <= 3'd0; + litedramcore_master_p3_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; + litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; end else begin - litedramcore_master_p0_bank <= litedramcore_inti_p0_bank; + litedramcore_master_p3_bank <= litedramcore_inti_p3_bank; end // synthesis translate_off dummy_d_55 = dummy_s; @@ -3350,11 +3238,11 @@ end reg dummy_d_56; // synthesis translate_on always @(*) begin - litedramcore_master_p0_cas_n <= 1'd1; + litedramcore_master_p3_cas_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; + litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; end else begin - litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n; + litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n; end // synthesis translate_off dummy_d_56 = dummy_s; @@ -3365,11 +3253,11 @@ end reg dummy_d_57; // synthesis translate_on always @(*) begin - litedramcore_master_p0_cs_n <= 1'd1; + litedramcore_master_p3_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; end else begin - litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n; + litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n; end // synthesis translate_off dummy_d_57 = dummy_s; @@ -3380,11 +3268,11 @@ end reg dummy_d_58; // synthesis translate_on always @(*) begin - litedramcore_master_p0_ras_n <= 1'd1; + litedramcore_master_p3_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; end else begin - litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n; + litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n; end // synthesis translate_off dummy_d_58 = dummy_s; @@ -3395,9 +3283,9 @@ end reg dummy_d_59; // synthesis translate_on always @(*) begin - litedramcore_slave_p0_rddata <= 32'd0; + litedramcore_slave_p3_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; + litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; end else begin end // synthesis translate_off @@ -3409,11 +3297,11 @@ end reg dummy_d_60; // synthesis translate_on always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; + litedramcore_master_p3_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; end else begin - litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; + litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n; end // synthesis translate_off dummy_d_60 = dummy_s; @@ -3424,9 +3312,9 @@ end reg dummy_d_61; // synthesis translate_on always @(*) begin - litedramcore_slave_p0_rddata_valid <= 1'd0; + litedramcore_slave_p3_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end else begin end // synthesis translate_off @@ -3438,11 +3326,11 @@ end reg dummy_d_62; // synthesis translate_on always @(*) begin - litedramcore_master_p0_cke <= 1'd0; + litedramcore_master_p3_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; + litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; end else begin - litedramcore_master_p0_cke <= litedramcore_inti_p0_cke; + litedramcore_master_p3_cke <= litedramcore_inti_p3_cke; end // synthesis translate_off dummy_d_62 = dummy_s; @@ -3453,11 +3341,11 @@ end reg dummy_d_63; // synthesis translate_on always @(*) begin - litedramcore_master_p0_odt <= 1'd0; + litedramcore_master_p3_odt <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; + litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; end else begin - litedramcore_master_p0_odt <= litedramcore_inti_p0_odt; + litedramcore_master_p3_odt <= litedramcore_inti_p3_odt; end // synthesis translate_off dummy_d_63 = dummy_s; @@ -3468,11 +3356,11 @@ end reg dummy_d_64; // synthesis translate_on always @(*) begin - litedramcore_master_p0_reset_n <= 1'd0; + litedramcore_master_p3_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; + litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; end else begin - litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n; + litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n; end // synthesis translate_off dummy_d_64 = dummy_s; @@ -3483,11 +3371,11 @@ end reg dummy_d_65; // synthesis translate_on always @(*) begin - litedramcore_master_p0_act_n <= 1'd1; + litedramcore_master_p3_act_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; + litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; end else begin - litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n; + litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n; end // synthesis translate_off dummy_d_65 = dummy_s; @@ -3498,11 +3386,11 @@ end reg dummy_d_66; // synthesis translate_on always @(*) begin - litedramcore_master_p0_wrdata <= 32'd0; + litedramcore_master_p3_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; + litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; end else begin - litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata; + litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata; end // synthesis translate_off dummy_d_66 = dummy_s; @@ -3513,10 +3401,10 @@ end reg dummy_d_67; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_rddata <= 32'd0; + litedramcore_inti_p0_rddata <= 32'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata; + litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata; end // synthesis translate_off dummy_d_67 = dummy_s; @@ -3527,11 +3415,11 @@ end reg dummy_d_68; // synthesis translate_on always @(*) begin - litedramcore_master_p0_wrdata_en <= 1'd0; + litedramcore_master_p3_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; + litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en; + litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en; end // synthesis translate_off dummy_d_68 = dummy_s; @@ -3542,10 +3430,10 @@ end reg dummy_d_69; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_rddata_valid <= 1'd0; + litedramcore_inti_p0_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end // synthesis translate_off dummy_d_69 = dummy_s; @@ -3556,11 +3444,11 @@ end reg dummy_d_70; // synthesis translate_on always @(*) begin - litedramcore_master_p0_wrdata_mask <= 4'd0; + litedramcore_master_p3_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; + litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask; + litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask; end // synthesis translate_off dummy_d_70 = dummy_s; @@ -3571,11 +3459,11 @@ end reg dummy_d_71; // synthesis translate_on always @(*) begin - litedramcore_master_p0_rddata_en <= 1'd0; + litedramcore_master_p3_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; + litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; end else begin - litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en; + litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en; end // synthesis translate_off dummy_d_71 = dummy_s; @@ -3586,11 +3474,11 @@ end reg dummy_d_72; // synthesis translate_on always @(*) begin - litedramcore_master_p1_address <= 15'd0; + litedramcore_master_p0_address <= 15'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_address <= litedramcore_slave_p1_address; + litedramcore_master_p0_address <= litedramcore_slave_p0_address; end else begin - litedramcore_master_p1_address <= litedramcore_inti_p1_address; + litedramcore_master_p0_address <= litedramcore_inti_p0_address; end // synthesis translate_off dummy_d_72 = dummy_s; @@ -3601,11 +3489,11 @@ end reg dummy_d_73; // synthesis translate_on always @(*) begin - litedramcore_master_p1_bank <= 3'd0; + litedramcore_master_p0_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; + litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; end else begin - litedramcore_master_p1_bank <= litedramcore_inti_p1_bank; + litedramcore_master_p0_bank <= litedramcore_inti_p0_bank; end // synthesis translate_off dummy_d_73 = dummy_s; @@ -3616,11 +3504,11 @@ end reg dummy_d_74; // synthesis translate_on always @(*) begin - litedramcore_master_p1_cas_n <= 1'd1; + litedramcore_master_p0_cas_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; + litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; end else begin - litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n; + litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n; end // synthesis translate_off dummy_d_74 = dummy_s; @@ -3631,11 +3519,11 @@ end reg dummy_d_75; // synthesis translate_on always @(*) begin - litedramcore_master_p1_cs_n <= 1'd1; + litedramcore_master_p0_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; + litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; end else begin - litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n; + litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n; end // synthesis translate_off dummy_d_75 = dummy_s; @@ -3646,11 +3534,11 @@ end reg dummy_d_76; // synthesis translate_on always @(*) begin - litedramcore_master_p1_ras_n <= 1'd1; + litedramcore_master_p0_ras_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; + litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; end else begin - litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n; + litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n; end // synthesis translate_off dummy_d_76 = dummy_s; @@ -3661,9 +3549,9 @@ end reg dummy_d_77; // synthesis translate_on always @(*) begin - litedramcore_slave_p1_rddata <= 32'd0; + litedramcore_slave_p0_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; + litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; end else begin end // synthesis translate_off @@ -3675,11 +3563,11 @@ end reg dummy_d_78; // synthesis translate_on always @(*) begin - litedramcore_master_p1_we_n <= 1'd1; + litedramcore_master_p0_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; + litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; end else begin - litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n; + litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; end // synthesis translate_off dummy_d_78 = dummy_s; @@ -3690,9 +3578,9 @@ end reg dummy_d_79; // synthesis translate_on always @(*) begin - litedramcore_slave_p1_rddata_valid <= 1'd0; + litedramcore_slave_p0_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end else begin end // synthesis translate_off @@ -3704,11 +3592,11 @@ end reg dummy_d_80; // synthesis translate_on always @(*) begin - litedramcore_master_p1_cke <= 1'd0; + litedramcore_master_p0_cke <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; + litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; end else begin - litedramcore_master_p1_cke <= litedramcore_inti_p1_cke; + litedramcore_master_p0_cke <= litedramcore_inti_p0_cke; end // synthesis translate_off dummy_d_80 = dummy_s; @@ -3719,11 +3607,11 @@ end reg dummy_d_81; // synthesis translate_on always @(*) begin - litedramcore_master_p1_odt <= 1'd0; + litedramcore_master_p0_odt <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; + litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; end else begin - litedramcore_master_p1_odt <= litedramcore_inti_p1_odt; + litedramcore_master_p0_odt <= litedramcore_inti_p0_odt; end // synthesis translate_off dummy_d_81 = dummy_s; @@ -3734,11 +3622,11 @@ end reg dummy_d_82; // synthesis translate_on always @(*) begin - litedramcore_master_p1_reset_n <= 1'd0; + litedramcore_master_p0_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; end else begin - litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; + litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n; end // synthesis translate_off dummy_d_82 = dummy_s; @@ -3749,11 +3637,11 @@ end reg dummy_d_83; // synthesis translate_on always @(*) begin - litedramcore_master_p1_act_n <= 1'd1; + litedramcore_master_p0_act_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; end else begin - litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n; + litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n; end // synthesis translate_off dummy_d_83 = dummy_s; @@ -3764,11 +3652,11 @@ end reg dummy_d_84; // synthesis translate_on always @(*) begin - litedramcore_master_p1_wrdata <= 32'd0; + litedramcore_master_p0_wrdata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; end else begin - litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata; + litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata; end // synthesis translate_off dummy_d_84 = dummy_s; @@ -3779,10 +3667,10 @@ end reg dummy_d_85; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_rddata <= 32'd0; + litedramcore_inti_p1_rddata <= 32'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; + litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata; end // synthesis translate_off dummy_d_85 = dummy_s; @@ -3793,11 +3681,11 @@ end reg dummy_d_86; // synthesis translate_on always @(*) begin - litedramcore_master_p1_wrdata_en <= 1'd0; + litedramcore_master_p0_wrdata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; + litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en; end // synthesis translate_off dummy_d_86 = dummy_s; @@ -3808,10 +3696,10 @@ end reg dummy_d_87; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_rddata_valid <= 1'd0; + litedramcore_inti_p1_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin end else begin - litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end // synthesis translate_off dummy_d_87 = dummy_s; @@ -3822,11 +3710,11 @@ end reg dummy_d_88; // synthesis translate_on always @(*) begin - litedramcore_master_p1_wrdata_mask <= 4'd0; + litedramcore_master_p0_wrdata_mask <= 4'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; + litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask; end // synthesis translate_off dummy_d_88 = dummy_s; @@ -3837,11 +3725,11 @@ end reg dummy_d_89; // synthesis translate_on always @(*) begin - litedramcore_master_p1_rddata_en <= 1'd0; + litedramcore_master_p0_rddata_en <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; + litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; end else begin - litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; + litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en; end // synthesis translate_off dummy_d_89 = dummy_s; @@ -3852,11 +3740,11 @@ end reg dummy_d_90; // synthesis translate_on always @(*) begin - litedramcore_master_p2_address <= 15'd0; + litedramcore_master_p1_address <= 15'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_address <= litedramcore_slave_p2_address; + litedramcore_master_p1_address <= litedramcore_slave_p1_address; end else begin - litedramcore_master_p2_address <= litedramcore_inti_p2_address; + litedramcore_master_p1_address <= litedramcore_inti_p1_address; end // synthesis translate_off dummy_d_90 = dummy_s; @@ -3867,11 +3755,11 @@ end reg dummy_d_91; // synthesis translate_on always @(*) begin - litedramcore_master_p2_bank <= 3'd0; + litedramcore_master_p1_bank <= 3'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; + litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; end else begin - litedramcore_master_p2_bank <= litedramcore_inti_p2_bank; + litedramcore_master_p1_bank <= litedramcore_inti_p1_bank; end // synthesis translate_off dummy_d_91 = dummy_s; @@ -3882,11 +3770,11 @@ end reg dummy_d_92; // synthesis translate_on always @(*) begin - litedramcore_master_p2_cas_n <= 1'd1; + litedramcore_master_p1_cas_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; + litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; end else begin - litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n; + litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n; end // synthesis translate_off dummy_d_92 = dummy_s; @@ -3897,11 +3785,11 @@ end reg dummy_d_93; // synthesis translate_on always @(*) begin - litedramcore_master_p2_cs_n <= 1'd1; + litedramcore_master_p1_cs_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; + litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; end else begin - litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n; + litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n; end // synthesis translate_off dummy_d_93 = dummy_s; @@ -4695,6 +4583,39 @@ end // synthesis translate_off reg dummy_d_122; // synthesis translate_on +always @(*) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_122 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_123; +// synthesis translate_on always @(*) begin litedramcore_bankmachine0_refresh_gnt <= 1'd0; case (bankmachine0_state) @@ -4721,12 +4642,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_122 = dummy_s; + dummy_d_123 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_123; +reg dummy_d_124; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_valid <= 1'd0; @@ -4769,12 +4690,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_123 = dummy_s; + dummy_d_124 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_124; +reg dummy_d_125; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_row_open <= 1'd0; @@ -4802,12 +4723,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_124 = dummy_s; + dummy_d_125 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_125; +reg dummy_d_126; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_row_close <= 1'd0; @@ -4835,12 +4756,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_125 = dummy_s; + dummy_d_126 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_126; +reg dummy_d_127; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; @@ -4876,39 +4797,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_126 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_127; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase // synthesis translate_off dummy_d_127 = dummy_s; // synthesis translate_on @@ -5329,16 +5217,13 @@ end reg dummy_d_138; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine1_req_rdata_valid <= 1'd0; case (bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -5351,6 +5236,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -5362,7 +5262,7 @@ end reg dummy_d_139; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + litedramcore_bankmachine1_refresh_gnt <= 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5371,6 +5271,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -5381,21 +5284,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -5407,19 +5295,22 @@ end reg dummy_d_140; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd0; + litedramcore_bankmachine1_cmd_valid <= 1'd0; case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd1; + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; end end + 3'd4: begin + end 3'd5: begin end 3'd6: begin @@ -5429,6 +5320,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -5440,18 +5343,15 @@ end reg dummy_d_141; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_valid <= 1'd0; + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -5465,18 +5365,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -6133,7 +6021,7 @@ end reg dummy_d_158; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine2_row_open <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6141,7 +6029,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine2_row_open <= 1'd1; end end 3'd4: begin @@ -6166,18 +6054,18 @@ end reg dummy_d_159; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; + litedramcore_bankmachine2_row_close <= 1'd0; case (bankmachine2_state) 1'd1: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; - end end 3'd4: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6199,18 +6087,15 @@ end reg dummy_d_160; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; + litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; case (bankmachine2_state) 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6221,6 +6106,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -6232,13 +6129,16 @@ end reg dummy_d_161; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -6251,18 +6151,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -6684,6 +6572,39 @@ end // synthesis translate_off reg dummy_d_172; // synthesis translate_on +always @(*) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_172 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_173; +// synthesis translate_on always @(*) begin litedramcore_bankmachine3_req_rdata_valid <= 1'd0; case (bankmachine3_state) @@ -6722,12 +6643,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_172 = dummy_s; + dummy_d_173 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_173; +reg dummy_d_174; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_refresh_gnt <= 1'd0; @@ -6755,12 +6676,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_173 = dummy_s; + dummy_d_174 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_174; +reg dummy_d_175; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_valid <= 1'd0; @@ -6803,12 +6724,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_174 = dummy_s; + dummy_d_175 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_175; +reg dummy_d_176; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_row_open <= 1'd0; @@ -6836,12 +6757,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_175 = dummy_s; + dummy_d_176 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_176; +reg dummy_d_177; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_row_close <= 1'd0; @@ -6868,39 +6789,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_176 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_177; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase // synthesis translate_off dummy_d_177 = dummy_s; // synthesis translate_on @@ -7441,18 +7329,15 @@ end reg dummy_d_191; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_valid <= 1'd0; + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -7466,18 +7351,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -7489,15 +7362,18 @@ end reg dummy_d_192; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine4_cmd_valid <= 1'd0; case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 3'd4: begin @@ -7511,6 +7387,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -8086,18 +7974,18 @@ end reg dummy_d_207; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine5_refresh_gnt <= 1'd0; case (bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8119,18 +8007,21 @@ end reg dummy_d_208; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd0; + litedramcore_bankmachine5_cmd_valid <= 1'd0; case (bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -8141,6 +8032,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -8152,44 +8055,29 @@ end reg dummy_d_209; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_valid <= 1'd0; + litedramcore_bankmachine5_row_open <= 1'd0; case (bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + litedramcore_bankmachine5_row_open <= 1'd1; end end 3'd4: begin end 3'd5: begin end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end endcase // synthesis translate_off dummy_d_209 = dummy_s; @@ -8200,7 +8088,7 @@ end reg dummy_d_210; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_row_open <= 1'd0; + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -8208,7 +8096,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open <= 1'd1; + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -8844,39 +8732,6 @@ end // synthesis translate_off reg dummy_d_226; // synthesis translate_on -always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_226 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_227; -// synthesis translate_on always @(*) begin litedramcore_bankmachine6_row_open <= 1'd0; case (bankmachine6_state) @@ -8903,12 +8758,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_227 = dummy_s; + dummy_d_226 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_228; +reg dummy_d_227; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_row_close <= 1'd0; @@ -8936,12 +8791,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_228 = dummy_s; + dummy_d_227 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_229; +reg dummy_d_228; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; @@ -8978,12 +8833,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_229 = dummy_s; + dummy_d_228 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_230; +reg dummy_d_229; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; @@ -9014,12 +8869,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_230 = dummy_s; + dummy_d_229 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_231; +reg dummy_d_230; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_we <= 1'd0; @@ -9061,6 +8916,39 @@ always @(*) begin end end endcase +// synthesis translate_off + dummy_d_230 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_231; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_231 = dummy_s; // synthesis translate_on @@ -9441,6 +9329,39 @@ end // synthesis translate_off reg dummy_d_241; // synthesis translate_on +always @(*) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_241 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_242; +// synthesis translate_on always @(*) begin litedramcore_bankmachine7_refresh_gnt <= 1'd0; case (bankmachine7_state) @@ -9467,12 +9388,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_241 = dummy_s; + dummy_d_242 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_242; +reg dummy_d_243; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_valid <= 1'd0; @@ -9515,12 +9436,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_242 = dummy_s; + dummy_d_243 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_243; +reg dummy_d_244; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_row_open <= 1'd0; @@ -9548,12 +9469,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_243 = dummy_s; + dummy_d_244 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_244; +reg dummy_d_245; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_row_close <= 1'd0; @@ -9581,12 +9502,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_244 = dummy_s; + dummy_d_245 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_245; +reg dummy_d_246; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; @@ -9622,39 +9543,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_245 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_246; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase // synthesis translate_off dummy_d_246 = dummy_s; // synthesis translate_on @@ -10730,7 +10618,7 @@ reg dummy_d_282; // synthesis translate_on always @(*) begin csrbank0_sel <= 1'd0; - csrbank0_sel <= (interface0_bank_bus_adr[13:11] == 2'd2); + csrbank0_sel <= (interface0_bank_bus_adr[13:9] == 2'd2); if (interface0_bank_bus_adr[0]) begin csrbank0_sel <= 1'd0; end @@ -10739,11 +10627,11 @@ always @(*) begin // synthesis translate_on end assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd0)); -assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd0)); +assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd0)); +assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd0)); assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd1)); -assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd1)); +assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd1)); +assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd1)); assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; @@ -10752,7 +10640,7 @@ reg dummy_d_283; // synthesis translate_on always @(*) begin csrbank1_sel <= 1'd0; - csrbank1_sel <= (interface1_bank_bus_adr[13:11] == 1'd0); + csrbank1_sel <= (interface1_bank_bus_adr[13:9] == 1'd0); if (interface1_bank_bus_adr[0]) begin csrbank1_sel <= 1'd0; end @@ -10761,35 +10649,35 @@ always @(*) begin // synthesis translate_on end assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; -assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd0)); -assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd0)); +assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd0)); +assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd0)); assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; -assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd1)); -assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd1)); +assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd1)); +assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd1)); assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd2)); -assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd2)); +assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd2)); +assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd2)); assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd3)); -assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd3)); +assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd3)); +assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd3)); assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd4)); -assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd4)); +assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd4)); +assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd4)); assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; -assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd5)); -assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd5)); +assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd5)); +assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd5)); assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd6)); -assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd6)); assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd7)); -assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd7)); assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd8)); -assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd8)); assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd9)); -assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd9)); assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0]; assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; @@ -10799,7 +10687,7 @@ reg dummy_d_284; // synthesis translate_on always @(*) begin csrbank2_sel <= 1'd0; - csrbank2_sel <= (interface2_bank_bus_adr[13:11] == 1'd1); + csrbank2_sel <= (interface2_bank_bus_adr[13:9] == 1'd1); if (interface2_bank_bus_adr[0]) begin csrbank2_sel <= 1'd0; end @@ -10808,217 +10696,105 @@ always @(*) begin // synthesis translate_on end assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; -assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd0)); -assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd0)); +assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd0)); +assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd0)); assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd1)); -assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd1)); +assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd1)); +assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd1)); assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd2)); -assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd2)); -assign csrbank2_dfii_pi0_address1_r = interface2_bank_bus_dat_w[6:0]; -assign csrbank2_dfii_pi0_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd3)); -assign csrbank2_dfii_pi0_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd3)); -assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd4)); -assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd4)); +assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd2)); +assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd2)); +assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0]; +assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd3)); +assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd3)); assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd5)); -assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd5)); -assign csrbank2_dfii_pi0_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd6)); -assign csrbank2_dfii_pi0_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd6)); -assign csrbank2_dfii_pi0_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd7)); -assign csrbank2_dfii_pi0_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd7)); -assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd8)); -assign csrbank2_dfii_pi0_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd8)); -assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd9)); -assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd9)); -assign csrbank2_dfii_pi0_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd10)); -assign csrbank2_dfii_pi0_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd10)); -assign csrbank2_dfii_pi0_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd11)); -assign csrbank2_dfii_pi0_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd11)); -assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd12)); -assign csrbank2_dfii_pi0_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd12)); -assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi0_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd13)); -assign csrbank2_dfii_pi0_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd13)); +assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd4)); +assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd4)); +assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd5)); +assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd5)); +assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd6)); +assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd6)); assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd14)); -assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd14)); +assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd7)); +assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd7)); assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd15)); -assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd15)); -assign csrbank2_dfii_pi1_address1_r = interface2_bank_bus_dat_w[6:0]; -assign csrbank2_dfii_pi1_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd16)); -assign csrbank2_dfii_pi1_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd16)); -assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd17)); -assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd17)); +assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd8)); +assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd8)); +assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0]; +assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd9)); +assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd9)); assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd18)); -assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd18)); -assign csrbank2_dfii_pi1_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd19)); -assign csrbank2_dfii_pi1_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd19)); -assign csrbank2_dfii_pi1_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd20)); -assign csrbank2_dfii_pi1_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd20)); -assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd21)); -assign csrbank2_dfii_pi1_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd21)); -assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd22)); -assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd22)); -assign csrbank2_dfii_pi1_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd23)); -assign csrbank2_dfii_pi1_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd23)); -assign csrbank2_dfii_pi1_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd24)); -assign csrbank2_dfii_pi1_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd24)); -assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd25)); -assign csrbank2_dfii_pi1_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd25)); -assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi1_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd26)); -assign csrbank2_dfii_pi1_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd26)); +assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd10)); +assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd10)); +assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd11)); +assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd11)); +assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd12)); +assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd12)); assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd27)); -assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd27)); +assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd13)); +assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd13)); assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd28)); -assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd28)); -assign csrbank2_dfii_pi2_address1_r = interface2_bank_bus_dat_w[6:0]; -assign csrbank2_dfii_pi2_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd29)); -assign csrbank2_dfii_pi2_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd29)); -assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd30)); -assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd30)); +assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd14)); +assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd14)); +assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[14:0]; +assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd15)); +assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd15)); assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd31)); -assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd31)); -assign csrbank2_dfii_pi2_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd32)); -assign csrbank2_dfii_pi2_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd32)); -assign csrbank2_dfii_pi2_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd33)); -assign csrbank2_dfii_pi2_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd33)); -assign csrbank2_dfii_pi2_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd34)); -assign csrbank2_dfii_pi2_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd34)); -assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd35)); -assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd35)); -assign csrbank2_dfii_pi2_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd36)); -assign csrbank2_dfii_pi2_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd36)); -assign csrbank2_dfii_pi2_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd37)); -assign csrbank2_dfii_pi2_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd37)); -assign csrbank2_dfii_pi2_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd38)); -assign csrbank2_dfii_pi2_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd38)); -assign csrbank2_dfii_pi2_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi2_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd39)); -assign csrbank2_dfii_pi2_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd39)); +assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd16)); +assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd16)); +assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd17)); +assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd17)); +assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd18)); +assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd18)); assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd40)); -assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd40)); +assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd19)); +assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd19)); assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd41)); -assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd41)); -assign csrbank2_dfii_pi3_address1_r = interface2_bank_bus_dat_w[6:0]; -assign csrbank2_dfii_pi3_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd42)); -assign csrbank2_dfii_pi3_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd42)); -assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd43)); -assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd43)); +assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd20)); +assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd20)); +assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[14:0]; +assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd21)); +assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd21)); assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd44)); -assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd44)); -assign csrbank2_dfii_pi3_wrdata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd45)); -assign csrbank2_dfii_pi3_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd45)); -assign csrbank2_dfii_pi3_wrdata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd46)); -assign csrbank2_dfii_pi3_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd46)); -assign csrbank2_dfii_pi3_wrdata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd47)); -assign csrbank2_dfii_pi3_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd47)); -assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd48)); -assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd48)); -assign csrbank2_dfii_pi3_rddata3_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd49)); -assign csrbank2_dfii_pi3_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd49)); -assign csrbank2_dfii_pi3_rddata2_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd50)); -assign csrbank2_dfii_pi3_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd50)); -assign csrbank2_dfii_pi3_rddata1_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd51)); -assign csrbank2_dfii_pi3_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd51)); -assign csrbank2_dfii_pi3_rddata0_r = interface2_bank_bus_dat_w[7:0]; -assign csrbank2_dfii_pi3_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd52)); -assign csrbank2_dfii_pi3_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd52)); +assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd22)); +assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd22)); +assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd23)); +assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd23)); +assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd24)); +assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd24)); assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; -assign csrbank2_dfii_pi0_address1_w = litedramcore_phaseinjector0_address_storage[14:8]; -assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[7:0]; +assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0]; assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; -assign csrbank2_dfii_pi0_wrdata3_w = litedramcore_phaseinjector0_wrdata_storage[31:24]; -assign csrbank2_dfii_pi0_wrdata2_w = litedramcore_phaseinjector0_wrdata_storage[23:16]; -assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[15:8]; -assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[7:0]; -assign csrbank2_dfii_pi0_rddata3_w = litedramcore_phaseinjector0_status[31:24]; -assign csrbank2_dfii_pi0_rddata2_w = litedramcore_phaseinjector0_status[23:16]; -assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_status[15:8]; -assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_status[7:0]; -assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata0_we; +assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0]; +assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata_we; assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0]; -assign csrbank2_dfii_pi1_address1_w = litedramcore_phaseinjector1_address_storage[14:8]; -assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[7:0]; +assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0]; assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; -assign csrbank2_dfii_pi1_wrdata3_w = litedramcore_phaseinjector1_wrdata_storage[31:24]; -assign csrbank2_dfii_pi1_wrdata2_w = litedramcore_phaseinjector1_wrdata_storage[23:16]; -assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[15:8]; -assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[7:0]; -assign csrbank2_dfii_pi1_rddata3_w = litedramcore_phaseinjector1_status[31:24]; -assign csrbank2_dfii_pi1_rddata2_w = litedramcore_phaseinjector1_status[23:16]; -assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_status[15:8]; -assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_status[7:0]; -assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata0_we; +assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0]; +assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata_we; assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0]; -assign csrbank2_dfii_pi2_address1_w = litedramcore_phaseinjector2_address_storage[14:8]; -assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[7:0]; +assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[14:0]; assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0]; -assign csrbank2_dfii_pi2_wrdata3_w = litedramcore_phaseinjector2_wrdata_storage[31:24]; -assign csrbank2_dfii_pi2_wrdata2_w = litedramcore_phaseinjector2_wrdata_storage[23:16]; -assign csrbank2_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[15:8]; -assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[7:0]; -assign csrbank2_dfii_pi2_rddata3_w = litedramcore_phaseinjector2_status[31:24]; -assign csrbank2_dfii_pi2_rddata2_w = litedramcore_phaseinjector2_status[23:16]; -assign csrbank2_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_status[15:8]; -assign csrbank2_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_status[7:0]; -assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata0_we; +assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0]; +assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0]; +assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata_we; assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0]; -assign csrbank2_dfii_pi3_address1_w = litedramcore_phaseinjector3_address_storage[14:8]; -assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[7:0]; +assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[14:0]; assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0]; -assign csrbank2_dfii_pi3_wrdata3_w = litedramcore_phaseinjector3_wrdata_storage[31:24]; -assign csrbank2_dfii_pi3_wrdata2_w = litedramcore_phaseinjector3_wrdata_storage[23:16]; -assign csrbank2_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[15:8]; -assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[7:0]; -assign csrbank2_dfii_pi3_rddata3_w = litedramcore_phaseinjector3_status[31:24]; -assign csrbank2_dfii_pi3_rddata2_w = litedramcore_phaseinjector3_status[23:16]; -assign csrbank2_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_status[15:8]; -assign csrbank2_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_status[7:0]; -assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata0_we; +assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0]; +assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0]; +assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata_we; assign adr = csr_port_adr; assign we = csr_port_we; assign dat_w = csr_port_dat_w; @@ -14159,7 +13935,7 @@ always @(posedge sys_clk) begin new_master_rdata_valid8 <= new_master_rdata_valid7; interface0_bank_bus_dat_r <= 1'd0; if (csrbank0_sel) begin - case (interface0_bank_bus_adr[3]) + case (interface0_bank_bus_adr[1]) 1'd0: begin interface0_bank_bus_dat_r <= csrbank0_init_done0_w; end @@ -14178,7 +13954,7 @@ always @(posedge sys_clk) begin init_error_re <= csrbank0_init_error0_re; interface1_bank_bus_dat_r <= 1'd0; if (csrbank1_sel) begin - case (interface1_bank_bus_adr[6:3]) + case (interface1_bank_bus_adr[4:1]) 1'd0: begin interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; end @@ -14225,7 +14001,7 @@ always @(posedge sys_clk) begin a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; interface2_bank_bus_dat_r <= 1'd0; if (csrbank2_sel) begin - case (interface2_bank_bus_adr[8:3]) + case (interface2_bank_bus_adr[5:1]) 1'd0: begin interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; end @@ -14236,154 +14012,70 @@ always @(posedge sys_clk) begin interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; end 3'd4: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; end 3'd5: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; end 3'd6: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w; end 3'd7: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; end 4'd8: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w; + interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; end 4'd9: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; end 4'd10: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata3_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; end 4'd11: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata2_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; end 4'd12: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w; end 4'd13: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; end 4'd14: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; + interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; end 4'd15: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; end 5'd16: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address1_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; end 5'd17: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; end 5'd18: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w; end 5'd19: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata3_w; - end - 5'd20: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata2_w; - end - 5'd21: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w; - end - 5'd22: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; - end - 5'd23: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata3_w; - end - 5'd24: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata2_w; - end - 5'd25: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w; - end - 5'd26: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w; - end - 5'd27: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; - end - 5'd28: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; - end - 5'd29: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address1_w; - end - 5'd30: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; - end - 5'd31: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; - end - 6'd32: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata3_w; - end - 6'd33: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata2_w; - end - 6'd34: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata1_w; - end - 6'd35: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; - end - 6'd36: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata3_w; - end - 6'd37: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata2_w; - end - 6'd38: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata1_w; - end - 6'd39: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata0_w; - end - 6'd40: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; end - 6'd41: begin + 5'd20: begin interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; end - 6'd42: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address1_w; - end - 6'd43: begin + 5'd21: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; end - 6'd44: begin + 5'd22: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; end - 6'd45: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata3_w; - end - 6'd46: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata2_w; - end - 6'd47: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata1_w; - end - 6'd48: begin + 5'd23: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; end - 6'd49: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata3_w; - end - 6'd50: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata2_w; - end - 6'd51: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata1_w; - end - 6'd52: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata0_w; + 5'd24: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w; end endcase end @@ -14395,112 +14087,64 @@ always @(posedge sys_clk) begin litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; end litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; - if (csrbank2_dfii_pi0_address1_re) begin - litedramcore_phaseinjector0_address_storage[14:8] <= csrbank2_dfii_pi0_address1_r; - end if (csrbank2_dfii_pi0_address0_re) begin - litedramcore_phaseinjector0_address_storage[7:0] <= csrbank2_dfii_pi0_address0_r; + litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r; end litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; if (csrbank2_dfii_pi0_baddress0_re) begin litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; end litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; - if (csrbank2_dfii_pi0_wrdata3_re) begin - litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank2_dfii_pi0_wrdata3_r; - end - if (csrbank2_dfii_pi0_wrdata2_re) begin - litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank2_dfii_pi0_wrdata2_r; - end - if (csrbank2_dfii_pi0_wrdata1_re) begin - litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank2_dfii_pi0_wrdata1_r; - end if (csrbank2_dfii_pi0_wrdata0_re) begin - litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank2_dfii_pi0_wrdata0_r; + litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; end litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; if (csrbank2_dfii_pi1_command0_re) begin litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; end litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; - if (csrbank2_dfii_pi1_address1_re) begin - litedramcore_phaseinjector1_address_storage[14:8] <= csrbank2_dfii_pi1_address1_r; - end if (csrbank2_dfii_pi1_address0_re) begin - litedramcore_phaseinjector1_address_storage[7:0] <= csrbank2_dfii_pi1_address0_r; + litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r; end litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; if (csrbank2_dfii_pi1_baddress0_re) begin litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; end litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; - if (csrbank2_dfii_pi1_wrdata3_re) begin - litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank2_dfii_pi1_wrdata3_r; - end - if (csrbank2_dfii_pi1_wrdata2_re) begin - litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank2_dfii_pi1_wrdata2_r; - end - if (csrbank2_dfii_pi1_wrdata1_re) begin - litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank2_dfii_pi1_wrdata1_r; - end if (csrbank2_dfii_pi1_wrdata0_re) begin - litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank2_dfii_pi1_wrdata0_r; + litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; end litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; if (csrbank2_dfii_pi2_command0_re) begin litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; end litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; - if (csrbank2_dfii_pi2_address1_re) begin - litedramcore_phaseinjector2_address_storage[14:8] <= csrbank2_dfii_pi2_address1_r; - end if (csrbank2_dfii_pi2_address0_re) begin - litedramcore_phaseinjector2_address_storage[7:0] <= csrbank2_dfii_pi2_address0_r; + litedramcore_phaseinjector2_address_storage[14:0] <= csrbank2_dfii_pi2_address0_r; end litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; if (csrbank2_dfii_pi2_baddress0_re) begin litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; end litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; - if (csrbank2_dfii_pi2_wrdata3_re) begin - litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank2_dfii_pi2_wrdata3_r; - end - if (csrbank2_dfii_pi2_wrdata2_re) begin - litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank2_dfii_pi2_wrdata2_r; - end - if (csrbank2_dfii_pi2_wrdata1_re) begin - litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank2_dfii_pi2_wrdata1_r; - end if (csrbank2_dfii_pi2_wrdata0_re) begin - litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank2_dfii_pi2_wrdata0_r; + litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; end litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; if (csrbank2_dfii_pi3_command0_re) begin litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; end litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; - if (csrbank2_dfii_pi3_address1_re) begin - litedramcore_phaseinjector3_address_storage[14:8] <= csrbank2_dfii_pi3_address1_r; - end if (csrbank2_dfii_pi3_address0_re) begin - litedramcore_phaseinjector3_address_storage[7:0] <= csrbank2_dfii_pi3_address0_r; + litedramcore_phaseinjector3_address_storage[14:0] <= csrbank2_dfii_pi3_address0_r; end litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; if (csrbank2_dfii_pi3_baddress0_re) begin litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; end litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; - if (csrbank2_dfii_pi3_wrdata3_re) begin - litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank2_dfii_pi3_wrdata3_r; - end - if (csrbank2_dfii_pi3_wrdata2_re) begin - litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank2_dfii_pi3_wrdata2_r; - end - if (csrbank2_dfii_pi3_wrdata1_re) begin - litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank2_dfii_pi3_wrdata1_r; - end if (csrbank2_dfii_pi3_wrdata0_re) begin - litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank2_dfii_pi3_wrdata0_r; + litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; end litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; if (sys_rst) begin